diff --git "a/shard_new_new_cleaned_v_text_16.csv" "b/shard_new_new_cleaned_v_text_16.csv" new file mode 100644--- /dev/null +++ "b/shard_new_new_cleaned_v_text_16.csv" @@ -0,0 +1,282443 @@ +text +"LIBAVFILTER_$MAJOR { + global: avfilter_*; av_*; + local: *; +}; +" +"LIBAVCODEC_$MAJOR { + global: av*; + audio_resample; + audio_resample_close; + #deprecated, remove after next bump + img_get_alpha_info; + dsputil_init; + ff_find_pix_fmt; + ff_framenum_to_drop_timecode; + ff_framenum_to_smtpe_timecode; + ff_raw_pix_fmt_tags; + ff_init_smtpe_timecode; + ff_fft*; + ff_mdct*; + ff_dct*; + ff_rdft*; + ff_prores_idct_put_10_sse2; + ff_simple_idct*; + ff_aanscales; + ff_faan*; + ff_mmx_idct; + ff_fdct*; + fdct_ifast; + j_rev_dct; + ff_mmxext_idct; + ff_idct_xvid*; + ff_jpeg_fdct*; + #XBMC's configure checks for ff_vdpau_vc1_decode_picture() + ff_vdpau_vc1_decode_picture; + local: *; +}; +" +"LIBPOSTPROC_$MAJOR { + global: postproc_*; pp_*; + local: *; +}; +" +"LIBSWSCALE_$MAJOR { + global: swscale_*; sws_*; ff_*; + local: *; +}; +" +"LIBAVDEVICE_$MAJOR { + global: avdevice_*; + local: *; +}; +" +"module my_and_module +( + input a, + input b, + output wire ab +); + +assign ab = a && b; + +endmodule +" +"class test; +endclass +" +"class test; +endclass +" +"class test; +endclass +" +"`include ""defines.vh"" + +module rtl +#( + width = `WIDTH +) +( + input clk, + input rst_n, + input a, + input b, + output wire ab, + output reg Qab +); + +wire [width-1:0] a_wire; + +my_and_module my_and_module(.a(a), .b(b), .ab(ab)); + +always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + Qab <= 0; + end else begin + Qab <= ab; + end +end + +endmodule +" +"//============================================================================== +//\tFile:\t\t$URL: svn+ssh://repositorypub@repository.eecs.berkeley.edu/public/Projects/GateLib/branches/dev/Publications/Tutorials/Publications/EECS150/Labs/ChipScopeSerial/Framework/ParityGen.v $ +//\tVersion:\t$Revision: 26904 $ +//\tAuthor:\t\tGreg Gibeling (http://www.gdgib.com) +//\tCopyright:\tCopyright 2003-2010 UC Berkeley +//============================================================================== + +//============================================================================== +//\tSection:\tLicense +//============================================================================== +//\tCopyright (c) 2003-2010, Regents of the University of California +//\tAll rights reserved. +// +//\tRedistribution and use in source and binary forms, with or without modification, +//\tare permitted provided that the following conditions are met: +// +//\t\t- Redistributions of source code must retain the above copyright notice, +//\t\t\tthis list of conditions and the following disclaimer. +//\t\t- Redistributions in binary form must reproduce the above copyright +//\t\t\tnotice, this list of conditions and the following disclaimer +//\t\t\tin the documentation and/or other materials provided with the +//\t\t\tdistribution. +//\t\t- Neither the name of the University of California, Berkeley nor the +//\t\t\tnames of its contributors may be used to endorse or promote +//\t\t\tproducts derived from this software without specific prior +//\t\t\twritten permission. +// +//\tTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" AND +//\tANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +//\tWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +//\tDISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +//\tANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +//\t(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +//\tLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +//\tANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +//\t(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +//\tSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== + +//------------------------------------------------------------------------------ +//\tModule:\t\tParityGen +//\tDesc:\t\tRS232/16550 selectable parity bit generator. +//\tParams:\t\tParity: +//\t\t\t\t\t\t0:\tNone +//\t\t\t\t\t\t1:\tOdd +//\t\t\t\t\t\t2:\tEven +//\t\t\t\t\t\t3:\tMark +//\t\t\t\t\t\t4:\tSpace +//\t\t\t\tWidth:\tInput width (in bits) +//------------------------------------------------------------------------------ +module\tParityGen(In, Out); +\t//-------------------------------------------------------------------------- +\t//\tParameters +\t//-------------------------------------------------------------------------- +\tparameter\t\t\t\tParity =\t\t\t\t0, +\t\t\t\t\t\t\tWidth =\t\t\t\t\t8; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tI/O +\t//-------------------------------------------------------------------------- +\tinput\t[Width-1:0]\t\tIn; +\toutput reg\t\t\t\tOut; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tParity Computation +\t//-------------------------------------------------------------------------- +\talways @ (In) begin +\t\tcase (Parity) +\t\t\t1: Out =\t\t\t\t\t\t\t\t~^In; +\t\t\t2: Out =\t\t\t\t\t\t\t\t^In; +\t\t\t3: Out =\t\t\t\t\t\t\t\t1; +\t\t\t4: Out =\t\t\t\t\t\t\t\t0; +\t\t\tdefault: Out =\t\t\t\t\t\t\t1\'b0; +\t\tendcase +\tend +\t//-------------------------------------------------------------------------- +endmodule +//------------------------------------------------------------------------------" +"//============================================================================== +//\tFile:\t\t$URL: svn+ssh://repositorypub@repository.eecs.berkeley.edu/public/Projects/GateLib/branches/dev/Firmware/UART/Hardware/UATransmitter.v $ +//\tVersion:\t$Revision: 26904 $ +//\tAuthor:\t\tGreg Gibeling (http://www.gdgib.com) +//\tCopyright:\tCopyright 2003-2010 UC Berkeley +//============================================================================== + +//============================================================================== +//\tSection:\tLicense +//============================================================================== +//\tCopyright (c) 2003-2010, Regents of the University of California +//\tAll rights reserved. +// +//\tRedistribution and use in source and binary forms, with or without modification, +//\tare permitted provided that the following conditions are met: +// +//\t\t- Redistributions of source code must retain the above copyright notice, +//\t\t\tthis list of conditions and the following disclaimer. +//\t\t- Redistributions in binary form must reproduce the above copyright +//\t\t\tnotice, this list of conditions and the following disclaimer +//\t\t\tin the documentation and/or other materials provided with the +//\t\t\tdistribution. +//\t\t- Neither the name of the University of California, Berkeley nor the +//\t\t\tnames of its contributors may be used to endorse or promote +//\t\t\tproducts derived from this software without specific prior +//\t\t\twritten permission. +// +//\tTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" AND +//\tANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +//\tWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +//\tDISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +//\tANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +//\t(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +//\tLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +//\tANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +//\t(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +//\tSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== + +//============================================================================== +//\tSection:\tIncludes +//============================================================================== +`include ""Const.v"" +//============================================================================== + +//------------------------------------------------------------------------------ +//\tModule:\t\tUATransmitter +//\tDesc:\t\tStandard Universal Asynchronous RS232/16550 type transmitter. +//\tParams:\t\tClockFreq: Frequency (in Hz) of the ""Clock"" being fed to this +//\t\t\t\t\t\tmodule. +//\t\t\t\tBaud:\tDesired Baud rate. This is the rate at which this +//\t\t\t\t\t\tmodule will send bits, and should be at most 1/4th +//\t\t\t\t\t\tof the clock rate (or so). +//\t\t\t\tWidth:\tWord width (in bits) of the words (bytes) send over +//\t\t\t\t\t\tthe serial line. +//\t\t\t\tParity:\tThe type of parity bit to be appended to each word of +//\t\t\t\t\t\tdata. +//\t\t\t\t\t\t0:\tNone +//\t\t\t\t\t\t1:\tEven +//\t\t\t\t\t\t2:\tOdd +//\t\t\t\t\t\t3:\tMark +//\t\t\t\t\t\t4:\tSpace +//\t\t\t\tStopBits:The number of bit-periods to send the stop condition. +//\t\t\t\t\t\tGenerally 1 or 2, though larger numbers are possible. +//\tEx:\t\t\t(27000000, 9600, 8, 0, 1) Standard 9600baud 8-N-1 serial port +//\t\t\t\t\t\tsettings used as the default by many devices, based +//\t\t\t\t\t\ton a 27MHz clock. +//------------------------------------------------------------------------------ +module UATransmitter(Clock, Reset, DataIn, DataInValid, DataInReady, SOut); +\t//-------------------------------------------------------------------------- +\t//\tParameters +\t//-------------------------------------------------------------------------- +\tparameter\t\t\t\tClockFreq =\t\t\t\t27000000, +\t\t\t\t\t\t\tBaud =\t\t\t\t\t115200, +\t\t\t\t\t\t\tWidth =\t\t\t\t\t8, +\t\t\t\t\t\t\tParity =\t\t\t\t0, +\t\t\t\t\t\t\tStopBits =\t\t\t\t1; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tLocal Parameters +\t//-------------------------------------------------------------------------- +\t`ifdef MACROSAFE +\tlocalparam\t\t\t\tDivisor =\t\t\t\tClockFreq / Baud, +\t\t\t\t\t\t\tDivWidth =\t\t\t\t`log2(Divisor), +\t\t\t\t\t\t\tCapture =\t\t\t\t(Divisor / 2), +\t\t\t\t\t\t\tBitCount =\t\t\t\tWidth + StopBits + (Parity ? 1 : 0) + 1, +\t\t\t\t\t\t\tBCWidth =\t\t\t\t`log2(BitCount + 1), +\t\t\t\t\t\t\tActualBaud =\t\t\tClockFreq / Divisor; +\t`endif + +\t`ifdef SIMULATION +\tlocalparam real\t\t\tMaxBaud =\t\t\t\tClockFreq / ((Divisor * (BitCount - 0.5)) / BitCount), +\t\t\t\t\t\t\tMinBaud =\t\t\t\tClockFreq / ((Divisor * (BitCount + 0.5)) / BitCount); +\t`endif +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tConstant Debugging Statements +\t//-------------------------------------------------------------------------- +\t`ifdef SIMULATION +\t\tinitial begin +\t\t\t$display(""DEBUG[%m @ %t]: UART Parameters"", $time); +\t\t\t$display("" ClockFreq = %d"", ClockFreq); +\t\t\t$display("" Baud = %d"", Baud); +\t\t\t$display("" Width = %d"", Width); +\t\t\t$display("" Parity = %d"", Parity); +\t\t\t$display("" StopBits = %d"", StopBits); + +\t\t\t/*$display("" Divisor = %d"", Divisor); +\t\t\t$display("" DivWidth = %d"", DivWidth); +\t\t\t$display("" Capture = %d"", Capture); +\t\t\t$display("" BitCount = %d"", BitCount); +\t\t\t$display("" BCWidth = %d"", BCWidth);*/ + +\t\t\t$display("" ActualBaud = %d"", ActualBaud); +\t\t\t$display("" MaxBaud = %f"", MaxBaud); +\t\t\t$display("" MinBaud = %f"", MinBaud); +\t\tend +\t`endif +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tSystem Inputs +\t//-------------------------------------------------------------------------- +\tinput\t\t\t\t\tClock, Reset;\t +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tParallel Data Input +\t//-------------------------------------------------------------------------- +\tinput\t[Width-1:0]\t\tDataIn; +\tinput\t\t\t\t\tDataInValid; +\toutput\t\t\t\t\tDataInReady; +\t//-------------------------------------------------------------------------- +\t +\t//-------------------------------------------------------------------------- +\t//\tSerial Interface +\t//-------------------------------------------------------------------------- +\toutput\t\t\t\t\tSOut; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\t Wires and Regs +\t//-------------------------------------------------------------------------- +\twire\t\t\t\t\tIntSOut; + +\twire\t[DivWidth-1:0]\tTxDivCount; +\twire\t[BCWidth-1:0]\tTxBitCount; +\twire\t[BitCount-1:0]\tTxData; +\twire\t\t\t\t\tTxShiftEnable, TxRunning, TxBit, TxStart, TxParity; +\twire\t[BitCount-1:0]\tDataInAugmented; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tAssigns and Decodes +\t//-------------------------------------------------------------------------- +\tassign\tTxShiftEnable =\t\t\t\t\t\t\t(TxDivCount == (Divisor - 1)); +\tassign\tTxRunning =\t\t\t\t\t\t\t\t(TxBitCount < BitCount); +\tassign\tTxBit =\t\t\t\t\t\t\t\t\tTxRunning & TxShiftEnable; +\tassign\tTxStart =\t\t\t\t\t\t\t\tDataInValid & DataInReady; + +\tassign\tDataInReady =\t\t\t\t\t\t\t~TxRunning & ~Reset; +\tassign\tDataInAugmented =\t\t\t\t\t\tParity ? {{StopBits{1\'b1}}, TxParity, DataIn, 1\'b0} : {{StopBits{1\'b1}}, DataIn, 1\'b0}; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tIO Register +\t//-------------------------------------------------------------------------- +\tIORegister\t\tIOR(\t\t.Clock(\t\t\t\tClock), +\t\t\t\t\t\t\t\t.Reset(\t\t\t\t1\'b0), +\t\t\t\t\t\t\t\t.Set(\t\t\t\t1\'b0), +\t\t\t\t\t\t\t\t.Enable(\t\t\t1\'b1), +\t\t\t\t\t\t\t\t.In(\t\t\t\tIntSOut), +\t\t\t\t\t\t\t\t.Out(\t\t\t\tSOut)); +\tdefparam\t\tIOR.Width =\t\t\t\t\t\t1; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tClock Divider Counter +\t//-------------------------------------------------------------------------- +\tCounter\t\t\tTxDivCounter(.Clock(\t\t\tClock), +\t\t\t\t\t\t\t\t.Reset(\t\t\t\tReset | (TxDivCount == (Divisor-1)) | TxStart), +\t\t\t\t\t\t\t\t.Set(\t\t\t\t1\'b0), +\t\t\t\t\t\t\t\t.Load(\t\t\t\t1\'b0), +\t\t\t\t\t\t\t\t.Enable(\t\t\t1\'b1), +\t\t\t\t\t\t\t\t.In(\t\t\t\t{DivWidth{1\'bx}}), +\t\t\t\t\t\t\t\t.Count(\t\t\t\tTxDivCount)); +\tdefparam\t\tTxDivCounter.Width =\t\t\tDivWidth; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tBit Counter +\t//-------------------------------------------------------------------------- +\tCounter\t\t\tTxBitCounter(.Clock(\t\t\tClock), +\t\t\t\t\t\t\t\t.Reset(\t\t\t\tTxStart), +\t\t\t\t\t\t\t\t.Set(\t\t\t\tReset), +\t\t\t\t\t\t\t\t.Load(\t\t\t\t1\'b0), +\t\t\t\t\t\t\t\t.Enable(\t\t\tTxBit), +\t\t\t\t\t\t\t\t.In(\t\t\t\t{BCWidth{1\'bx}}), +\t\t\t\t\t\t\t\t.Count(\t\t\t\tTxBitCount)); +\tdefparam\t\tTxBitCounter.Width =\t\t\tBCWidth; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tShift Register and Bit Reversal +\t//-------------------------------------------------------------------------- +\tShiftRegister\tTxShift(\t.PIn(\t\t\t\tReset ? {BitCount{1\'b1}} : TxData), +\t\t\t\t\t\t\t\t.SIn(\t\t\t\t1\'b1), +\t\t\t\t\t\t\t\t.POut(\t\t\t\t), +\t\t\t\t\t\t\t\t.SOut(\t\t\t\tIntSOut), +\t\t\t\t\t\t\t\t.Load(\t\t\t\tTxStart | Reset), +\t\t\t\t\t\t\t\t.Enable(\t\t\tTxShiftEnable), +\t\t\t\t\t\t\t\t.Clock(\t\t\t\tClock), +\t\t\t\t\t\t\t\t.Reset(\t\t\t\t1\'b0)); +\tdefparam\t\tTxShift.PWidth =\t\t\t\tBitCount; +\tdefparam\t\tTxShift.SWidth =\t\t\t\t1; +\tReverse\t\t\tTxReverse(\t.In(\t\t\t\tDataInAugmented), +\t\t\t\t\t\t\t\t.Out(\t\t\t\tTxData)); +\tdefparam\t\tTxReverse.Width =\t\t\t\tBitCount; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tParity Generator +\t//-------------------------------------------------------------------------- +\tParityGen\t\tTxParityGen(.In(\t\t\t\tDataIn), +\t\t\t\t\t\t\t\t.Out(\t\t\t\tTxParity)); +\tdefparam\t\tTxParityGen.Width =\t\t\t\tWidth; +\tdefparam\t\tTxParityGen.Parity =\t\t\tParity; +\t//-------------------------------------------------------------------------- +endmodule +//------------------------------------------------------------------------------ +" +"//============================================================================== +//\tFile:\t\t$URL: svn+ssh://repositorypub@repository.eecs.berkeley.edu/public/Projects/GateLib/branches/dev/Publications/Tutorials/Publications/EECS150/Labs/ChipScopeSerial/Framework/Counter.v $ +//\tVersion:\t$Revision: 26904 $ +//\tAuthor:\t\tGreg Gibeling (http://www.gdgib.com) +//\tCopyright:\tCopyright 2003-2010 UC Berkeley +//============================================================================== + +//============================================================================== +//\tSection:\tLicense +//============================================================================== +//\tCopyright (c) 2003-2010, Regents of the University of California +//\tAll rights reserved. +// +//\tRedistribution and use in source and binary forms, with or without modification, +//\tare permitted provided that the following conditions are met: +// +//\t\t- Redistributions of source code must retain the above copyright notice, +//\t\t\tthis list of conditions and the following disclaimer. +//\t\t- Redistributions in binary form must reproduce the above copyright +//\t\t\tnotice, this list of conditions and the following disclaimer +//\t\t\tin the documentation and/or other materials provided with the +//\t\t\tdistribution. +//\t\t- Neither the name of the University of California, Berkeley nor the +//\t\t\tnames of its contributors may be used to endorse or promote +//\t\t\tproducts derived from this software without specific prior +//\t\t\twritten permission. +// +//\tTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" AND +//\tANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +//\tWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +//\tDISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +//\tANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +//\t(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +//\tLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +//\tANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +//\t(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +//\tSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== + +//------------------------------------------------------------------------------ +//\tModule:\t\tCounter +//\tDesc:\t\tStandard binary counter. +//\tParams:\t\tWidth:\tThe bitwidth of the counter. +//\t\t\t\tLimited:Should the counter saturate rather than roll over? +//\t\t\t\tDown:\tShould the counter count down (decrement) rather than +//\t\t\t\t\t\tup (increment)? Note that this will, obviously, affect +//\t\t\t\t\t\tthe limit, if used. +//\tAuthor:\t\tGreg Gibeling +//\tVersion:\t$Revision: 26904 $ +//------------------------------------------------------------------------------ +module\tCounter(Clock, Reset, Set, Load, Enable, In, Count); +\t//-------------------------------------------------------------------------- +\t//\tParameters +\t//-------------------------------------------------------------------------- +\tparameter\t\t\t\tWidth = \t\t\t\t32, +\t\t\t\t\t\t\tLimited =\t\t\t\t0, +\t\t\t\t\t\t\tDown =\t\t\t\t\t0, +\t\t\t\t\t\t\tInitial =\t\t\t\t{Width{1\'bx}}, +\t\t\t\t\t\t\tAsyncReset =\t\t\t0, +\t\t\t\t\t\t\tAsyncSet =\t\t\t\t0; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tI/O +\t//-------------------------------------------------------------------------- +\tinput\t\t\t\t\tClock, Reset, Set, Load, Enable; +\tinput\t[Width-1:0]\t\tIn; +\toutput\t[Width-1:0]\t\tCount; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tWires +\t//-------------------------------------------------------------------------- +\twire\t\t\t\t\tNoLimit; +\t +\twire\t\t\t\t\tRegEnable; +\twire\t[Width-1:0]\t\tRegIn; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tAssigns +\t//-------------------------------------------------------------------------- +\tassign\tNoLimit =\t\t\t\t\t\t\t\t!Limited; +\t +\tassign\tRegEnable =\t\t\t\t\t\t\t\tLoad | (Enable & (NoLimit | (Down ? |Count : ~&Count))); +\tassign\tRegIn =\t\t\t\t\t\t\t\t\tLoad ? In : (Down ? (Count - 1) : (Count + 1)); +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tRegister +\t//-------------------------------------------------------------------------- +\tRegister\t\t#(\t\t\t.Width(\t\t\t\tWidth), +\t\t\t\t\t\t\t\t.Initial(\t\t\tInitial), +\t\t\t\t\t\t\t\t.AsyncReset(\t\tAsyncReset), +\t\t\t\t\t\t\t\t.AsyncSet(\t\t\tAsyncSet)) +\t\t\t\t\tRegister(\t.Clock(\t\t\t\tClock), +\t\t\t\t\t\t\t\t.Reset(\t\t\t\tReset), +\t\t\t\t\t\t\t\t.Set(\t\t\t\tSet), +\t\t\t\t\t\t\t\t.Enable(\t\t\tRegEnable), +\t\t\t\t\t\t\t\t.In(\t\t\t\tRegIn), +\t\t\t\t\t\t\t\t.Out(\t\t\t\tCount)); +\t//-------------------------------------------------------------------------- +endmodule +//------------------------------------------------------------------------------ +" +"//============================================================================== +//\tFile:\t\t$URL: svn+ssh://repositorypub@repository.eecs.berkeley.edu/public/Projects/GateLib/branches/dev/Publications/Tutorials/Publications/EECS150/Labs/ChipScopeSerial/Framework/IORegister.v $ +//\tVersion:\t$Revision: 26904 $ +//\tAuthor:\t\tGreg Gibeling (http://www.gdgib.com) +//\tCopyright:\tCopyright 2003-2010 UC Berkeley +//============================================================================== + +//============================================================================== +//\tSection:\tLicense +//============================================================================== +//\tCopyright (c) 2005-2010, Regents of the University of California +//\tAll rights reserved. +// +//\tRedistribution and use in source and binary forms, with or without modification, +//\tare permitted provided that the following conditions are met: +// +//\t\t- Redistributions of source code must retain the above copyright notice, +//\t\t\tthis list of conditions and the following disclaimer. +//\t\t- Redistributions in binary form must reproduce the above copyright +//\t\t\tnotice, this list of conditions and the following disclaimer +//\t\t\tin the documentation and/or other materials provided with the +//\t\t\tdistribution. +//\t\t- Neither the name of the University of California, Berkeley nor the +//\t\t\tnames of its contributors may be used to endorse or promote +//\t\t\tproducts derived from this software without specific prior +//\t\t\twritten permission. +// +//\tTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" AND +//\tANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +//\tWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +//\tDISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +//\tANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +//\t(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +//\tLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +//\tANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +//\t(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +//\tSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== + +//------------------------------------------------------------------------------ +//\tModule:\t\tIORegister +//\tDesc:\t\tA register which should be packed in to IO pads. +//\tAuthor:\t\tGreg Gibeling +//\tVersion:\t$Revision: 26904 $ +//------------------------------------------------------------------------------ +module\tIORegister(Clock, Reset, Set, Enable, In, Out); +\t//-------------------------------------------------------------------------- +\t//\tParameters +\t//-------------------------------------------------------------------------- +\tparameter\t\t\t\tWidth = \t\t\t\t32, +\t\t\t\t\t\t\tInitial =\t\t\t\t{Width{1\'bx}}, +\t\t\t\t\t\t\tAsyncReset =\t\t\t0, +\t\t\t\t\t\t\tAsyncSet =\t\t\t\t0, +\t\t\t\t\t\t\tResetValue =\t\t\t{Width{1\'b0}}, +\t\t\t\t\t\t\tSetValue =\t\t\t\t{Width{1\'b1}}; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tInputs & Outputs +\t//-------------------------------------------------------------------------- +\tinput\t\t\t\t\tClock, Enable, Reset, Set; +\tinput\t[Width-1:0]\t\tIn; +\toutput reg [Width-1:0]\tOut =\t\t\t\t\tInitial /* synthesis syn_useioff = 1 iob = true useioff = 1 */; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tBehavioral Register +\t//-------------------------------------------------------------------------- +\tgenerate if (AsyncReset) begin:AR +\t\tif (AsyncSet) begin:AS +\t\t\talways @ (posedge Clock or posedge Reset or posedge Set) begin +\t\t\t\tif (Reset) Out <=\t\t\t\t\tResetValue; +\t\t\t\telse if (Set) Out <=\t\t\t\tSetValue; +\t\t\t\telse if (Enable) Out <=\t\t\t\tIn; +\t\t\tend +\t\tend else begin:SS +\t\t\talways @ (posedge Clock or posedge Reset) begin +\t\t\t\tif (Reset) Out <=\t\t\t\t\tResetValue; +\t\t\t\telse if (Set) Out <=\t\t\t\tSetValue; +\t\t\t\telse if (Enable) Out <=\t\t\t\tIn; +\t\t\tend +\t\tend +\tend else begin:SR +\t\tif (AsyncSet) begin:AS +\t\t\talways @ (posedge Clock or posedge Set) begin +\t\t\t\tif (Reset) Out <=\t\t\t\t\tResetValue; +\t\t\t\telse if (Set) Out <=\t\t\t\tSetValue; +\t\t\t\telse if (Enable) Out <=\t\t\t\tIn; +\t\t\tend +\t\tend else begin:SS +\t\t\talways @ (posedge Clock) begin +\t\t\t\tif (Reset) Out <=\t\t\t\t\tResetValue; +\t\t\t\telse if (Set) Out <=\t\t\t\tSetValue; +\t\t\t\telse if (Enable) Out <=\t\t\t\tIn; +\t\t\tend +\t\tend +\tend endgenerate +\t//-------------------------------------------------------------------------- +endmodule +//------------------------------------------------------------------------------ +" +"//============================================================================== +//\tFile:\t\t$URL: svn+ssh://repositorypub@repository.eecs.berkeley.edu/public/Projects/GateLib/branches/dev/Firmware/UART/Hardware/UART.v $ +//\tVersion:\t$Revision: 26904 $ +//\tAuthor:\t\tGreg Gibeling (http://www.gdgib.com) +//\tCopyright:\tCopyright 2003-2010 UC Berkeley +//============================================================================== + +//============================================================================== +//\tSection:\tLicense +//============================================================================== +//\tCopyright (c) 2003-2010, Regents of the University of California +//\tAll rights reserved. +// +//\tRedistribution and use in source and binary forms, with or without modification, +//\tare permitted provided that the following conditions are met: +// +//\t\t- Redistributions of source code must retain the above copyright notice, +//\t\t\tthis list of conditions and the following disclaimer. +//\t\t- Redistributions in binary form must reproduce the above copyright +//\t\t\tnotice, this list of conditions and the following disclaimer +//\t\t\tin the documentation and/or other materials provided with the +//\t\t\tdistribution. +//\t\t- Neither the name of the University of California, Berkeley nor the +//\t\t\tnames of its contributors may be used to endorse or promote +//\t\t\tproducts derived from this software without specific prior +//\t\t\twritten permission. +// +//\tTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" AND +//\tANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +//\tWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +//\tDISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +//\tANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +//\t(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +//\tLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +//\tANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +//\t(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +//\tSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== + +//============================================================================== +//\tSection:\tIncludes +//============================================================================== +`include ""Const.v"" +//============================================================================== + +//------------------------------------------------------------------------------ +//\tModule:\t\tUART +//\tDesc:\t\tStandard Universal Asynchronous RS232/16550 type transceiver. +//\tParams:\t\tClockFreq: Frequency (in Hz) of the ""Clock"" being fed to this +//\t\t\t\t\t\tmodule. +//\t\t\t\tBaud:\tDesired Baud rate. This is the rate at which this +//\t\t\t\t\t\tmodule will send bits, and should be at most 1/4th +//\t\t\t\t\t\tof the clock rate (or so). +//\t\t\t\tWidth:\tWord width (in bits) of the words (bytes) send over +//\t\t\t\t\t\tthe serial line. +//\t\t\t\tParity:\tThe type of parity bit to be appended to each word of +//\t\t\t\t\t\tdata. +//\t\t\t\t\t\t0:\tNone +//\t\t\t\t\t\t1:\tOdd +//\t\t\t\t\t\t2:\tEven +//\t\t\t\t\t\t3:\tMark +//\t\t\t\t\t\t4:\tSpace +//\t\t\t\tStopBits:The number of bit-periods to send the stop condition. +//\t\t\t\t\t\tGenerally 1 or 2, though larger numbers are possible. +//\tEx:\t\t\t(27000000, 9600, 8, 0, 1) Standard 9600baud 8-N-1 serial port +//\t\t\t\t\t\tsettings used as the default by many devices, based +//\t\t\t\t\t\ton a 27MHz clock. +//------------------------------------------------------------------------------ +module\tUART(Clock, Reset, DataIn, DataInValid, DataInReady, DataOut, DataOutValid, DataOutReady, SIn, SOut); +\t//-------------------------------------------------------------------------- +\t//\tParameters +\t//-------------------------------------------------------------------------- +\tparameter\t\t\t\tClockFreq =\t\t\t\t27000000, +\t\t\t\t\t\t\tBaud =\t\t\t\t\t115200, +\t\t\t\t\t\t\tWidth =\t\t\t\t\t8, +\t\t\t\t\t\t\tParity =\t\t\t\t0, +\t\t\t\t\t\t\tStopBits =\t\t\t\t1; +\t//-------------------------------------------------------------------------- +\t +\t//-------------------------------------------------------------------------- +\t//\tSystem Inputs +\t//-------------------------------------------------------------------------- +\tinput\t\t\t\t\tClock, Reset;\t +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tParallel Data Input +\t//-------------------------------------------------------------------------- +\tinput\t[Width-1:0]\t\tDataIn; +\tinput\t\t\t\t\tDataInValid; +\toutput\t\t\t\t\tDataInReady; +\t//-------------------------------------------------------------------------- +\t +\t//-------------------------------------------------------------------------- +\t//\tParallel Data Output +\t//-------------------------------------------------------------------------- +\toutput\t[Width-1:0]\t\tDataOut; +\toutput\t\t\t\t\tDataOutValid; +\tinput\t\t\t\t\tDataOutReady; +\t//-------------------------------------------------------------------------- +\t +\t//-------------------------------------------------------------------------- +\t//\tSerial Interface +\t//-------------------------------------------------------------------------- +\tinput\t\t\t\t\tSIn; +\toutput\t\t\t\t\tSOut; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tTransmitter +\t//-------------------------------------------------------------------------- +\tUATransmitter\tTX(\t\t\t.Clock(\t\t\t\tClock), +\t\t\t\t\t\t\t\t.Reset(\t\t\t\tReset), +\t\t\t\t\t\t\t\t.DataIn(\t\t\tDataIn), +\t\t\t\t\t\t\t\t.DataInValid(\t\tDataInValid), +\t\t\t\t\t\t\t\t.DataInReady(\t\tDataInReady), +\t\t\t\t\t\t\t\t.SOut(\t\t\t\tSOut)); +\tdefparam\t\tTX.ClockFreq =\t\t\t\t\tClockFreq; +\tdefparam\t\tTX.Baud =\t\t\t\t\t\tBaud; +\tdefparam\t\tTX.Width =\t\t\t\t\t\tWidth; +\tdefparam\t\tTX.Parity =\t\t\t\t\t\tParity; +\tdefparam\t\tTX.StopBits =\t\t\t\t\tStopBits; +\t//-------------------------------------------------------------------------- +\t +\t//-------------------------------------------------------------------------- +\t//\tReceiver +\t//-------------------------------------------------------------------------- +\tUAReceiver\t\tRX(\t\t\t.Clock(\t\t\t\tClock), +\t\t\t\t\t\t\t\t.Reset(\t\t\t\tReset), +\t\t\t\t\t\t\t\t.DataOut(\t\t\tDataOut), +\t\t\t\t\t\t\t\t.DataOutValid(\t\tDataOutValid), +\t\t\t\t\t\t\t\t.DataOutReady(\t\tDataOutReady), +\t\t\t\t\t\t\t\t.SIn(\t\t\t\tSIn)); +\tdefparam\t\tRX.ClockFreq =\t\t\t\t\tClockFreq; +\tdefparam\t\tRX.Baud =\t\t\t\t\t\tBaud; +\tdefparam\t\tRX.Width =\t\t\t\t\t\tWidth; +\tdefparam\t\tRX.Parity =\t\t\t\t\t\tParity; +\tdefparam\t\tRX.StopBits =\t\t\t\t\tStopBits; +\t//-------------------------------------------------------------------------- +endmodule +//------------------------------------------------------------------------------" +"//============================================================================== +//\tFile:\t\t$URL: svn+ssh://repositorypub@repository.eecs.berkeley.edu/public/Projects/GateLib/branches/dev/Publications/Tutorials/Publications/EECS150/Labs/ChipScopeSerial/Framework/Reverse.v $ +//\tVersion:\t$Revision: 26904 $ +//\tAuthor:\t\tGreg Gibeling (http://www.gdgib.com) +//\tCopyright:\tCopyright 2003-2010 UC Berkeley +//============================================================================== + +//============================================================================== +//\tSection:\tLicense +//============================================================================== +//\tCopyright (c) 2003-2010, Regents of the University of California +//\tAll rights reserved. +// +//\tRedistribution and use in source and binary forms, with or without modification, +//\tare permitted provided that the following conditions are met: +// +//\t\t- Redistributions of source code must retain the above copyright notice, +//\t\t\tthis list of conditions and the following disclaimer. +//\t\t- Redistributions in binary form must reproduce the above copyright +//\t\t\tnotice, this list of conditions and the following disclaimer +//\t\t\tin the documentation and/or other materials provided with the +//\t\t\tdistribution. +//\t\t- Neither the name of the University of California, Berkeley nor the +//\t\t\tnames of its contributors may be used to endorse or promote +//\t\t\tproducts derived from this software without specific prior +//\t\t\twritten permission. +// +//\tTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" AND +//\tANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +//\tWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +//\tDISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +//\tANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +//\t(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +//\tLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +//\tANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +//\t(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +//\tSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== + +//------------------------------------------------------------------------------ +//\tModule:\t\tReverse +//\tDesc:\t\tParameterized bit reversal module: a fancy wire. +//\t\t\t\tEssentially this module is just a very complex set of wires, all +//\t\t\t\tit does it reverse the bits in a bus. A ""group"" is a group of +//\t\t\t\t""chunks"" that should be reversed, ""set"" is the number of +//\t\t\t\t""chunks"" per ""group"". This module will reverse the order of the +//\t\t\t\t""chunks"" within each ""group"". +//\tParams:\t\tWidth:\tThis sets the input and output bus width of the module +//\t\t\t\tChunk:\tThis is the size of a block of wires which should +//\t\t\t\t\t\tbe kept in order. The default is 1 meaning each wire +//\t\t\t\t\t\tshould be treated separately. +//\t\t\t\tSet:\tThe number of chunks in a set, the default is the +//\t\t\t\t\t\tbitwidth of the input bus, meaning that the whole input +//\t\t\t\t\t\tbus is treated as a set. +//\tEx:\t\t\t(32,1,32) Will reverse the bit order of a 32bit bus. +//\t\t\t\t(32,1,8)Will reverse the MSb/LSb order of the bytes in a 32bit +//\t\t\t\t\t\tbus. +//\t\t\t\t(32,4,2)will reverse the MSNibble/LSNibble of each byte in a +//\t\t\t\t\t\t32bit bus. +//\tAuthor:\t\tGreg Gibeling +//\tVersion:\t$Revision: 26904 $ +//------------------------------------------------------------------------------ +module\tReverse(In, Out); +\t//-------------------------------------------------------------------------- +\t//\tParameters +\t//-------------------------------------------------------------------------- +\tparameter\t\t\t\tWidth =\t\t\t\t\t32, +\t\t\t\t\t\t\tChunk =\t\t\t\t\t1, +\t\t\t\t\t\t\tSet =\t\t\t\t\tWidth; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tConstants +\t//-------------------------------------------------------------------------- +\tlocalparam\t\t\t\tGroup =\t\t\t\t\tChunk * Set; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tI/O +\t//-------------------------------------------------------------------------- +\tinput\t[Width-1:0]\t\tIn; +\toutput\t[Width-1:0]\t\tOut; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tA Complicated Wire +\t//-------------------------------------------------------------------------- +\tgenvar\t\t\t\t\ti; +\tgenerate for(i = 0; i < Width; i = i + 1) begin:REVERSE +\t\tassign Out[i] =\t\t\t\t\t\t\t\tIn[((Set - 1 - ((i % Group) / Chunk)) * Chunk) + ((i % Group) % Chunk) + ((i / Group) * Group)]; +\tend endgenerate +\t//-------------------------------------------------------------------------- +endmodule +//------------------------------------------------------------------------------ +" +"//============================================================================== +//\tFile:\t\t$URL: svn+ssh://repositorypub@repository.eecs.berkeley.edu/public/Projects/GateLib/branches/dev/Publications/Tutorials/Publications/EECS150/Labs/ChipScopeSerial/Framework/ShiftRegister.v $ +//\tVersion:\t$Revision: 26904 $ +//\tAuthor:\t\tGreg Gibeling (http://www.gdgib.com) +//\tCopyright:\tCopyright 2003-2010 UC Berkeley +//============================================================================== + +//============================================================================== +//\tSection:\tLicense +//============================================================================== +//\tCopyright (c) 2005-2010, Regents of the University of California +//\tAll rights reserved. +// +//\tRedistribution and use in source and binary forms, with or without modification, +//\tare permitted provided that the following conditions are met: +// +//\t\t- Redistributions of source code must retain the above copyright notice, +//\t\t\tthis list of conditions and the following disclaimer. +//\t\t- Redistributions in binary form must reproduce the above copyright +//\t\t\tnotice, this list of conditions and the following disclaimer +//\t\t\tin the documentation and/or other materials provided with the +//\t\t\tdistribution. +//\t\t- Neither the name of the University of California, Berkeley nor the +//\t\t\tnames of its contributors may be used to endorse or promote +//\t\t\tproducts derived from this software without specific prior +//\t\t\twritten permission. +// +//\tTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" AND +//\tANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +//\tWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +//\tDISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +//\tANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +//\t(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +//\tLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +//\tANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +//\t(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +//\tSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== + +//------------------------------------------------------------------------------ +//\tModule:\t\tShiftRegister +//\tDesc:\t\tThis is a general parallel to serial and serial to parallel +//\t\t\t\tconverter. Note that it can work with \'serial\' data streams +//\t\t\t\tthat are more than a single bit wide. This is useful for +//\t\t\t\texample when a signal must cross a 32b/8b boundary. +//\t\t\t\tThis also means it can be used to delay a signal quite easily. +//\tParams:\t\tPWidth:\tSets the bitwidth of the parallel data (both in and +//\t\t\t\t\t\tout of the module) +//\t\t\t\tSWidth:\tSets the bitwidth of the serial data (both in and out +//\t\t\t\t\t\tof the module) +//\t\t\t\tReverse:Shift MSb to LSb? +//\tEx:\t\t\t(32,1) will convert 32bit wide data into 1bit serial data +//\t\t\t\t(32,8) will convert 32bit words into bytes +//\tAuthor:\t\tGreg Gibeling +//\tVersion:\t$Revision: 26904 $ +//------------------------------------------------------------------------------ +module\tShiftRegister(Clock, Reset, Load, Enable, PIn, SIn, POut, SOut); +\t//-------------------------------------------------------------------------- +\t//\tParameters +\t//-------------------------------------------------------------------------- +\tparameter\t\t\t\tPWidth =\t\t\t\t32,\t\t// The parallel width +\t\t\t\t\t\t\tSWidth =\t\t\t\t1,\t\t// The serial width +\t\t\t\t\t\t\tReverse =\t\t\t\t0, +\t\t\t\t\t\t\tInitial =\t\t\t\t{PWidth{1\'bx}}, +\t\t\t\t\t\t\tAsyncReset =\t\t\t0; +\t//-------------------------------------------------------------------------- +\t +\t//-------------------------------------------------------------------------- +\t//\tControl Inputs +\t//-------------------------------------------------------------------------- +\tinput\t\t\t\t\tClock, Reset, Load, Enable; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tParallel and Serial I/O +\t//-------------------------------------------------------------------------- +\tinput\t[PWidth-1:0]\tPIn; +\tinput\t[SWidth-1:0]\tSIn; +\toutput \t[PWidth-1:0]\tPOut; +\toutput\t[SWidth-1:0]\tSOut; +\t//-------------------------------------------------------------------------- +\t +\t//-------------------------------------------------------------------------- +\t//\tAssigns +\t//-------------------------------------------------------------------------- +\tassign\tSOut =\t\t\t\t\t\t\t\t\tReverse ? POut[SWidth-1:0] : POut[PWidth-1:PWidth-SWidth]; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tBehavioral Shift Register Core +\t//-------------------------------------------------------------------------- +\tgenerate if (PWidth == SWidth) begin:REG +\t\tHardRegister #(\t\t\t.Width(\t\t\t\tPWidth), +\t\t\t\t\t\t\t\t.Initial(\t\t\tInitial), +\t\t\t\t\t\t\t\t.AsyncReset(\t\tAsyncReset)) +\t\t\t\t\tRegister(\t.Clock(\t\t\t\tClock), +\t\t\t\t\t\t\t\t.Reset(\t\t\t\tReset), +\t\t\t\t\t\t\t\t.Set(\t\t\t\t1\'b0), +\t\t\t\t\t\t\t\t.Enable(\t\t\tLoad | Enable), +\t\t\t\t\t\t\t\t.In(\t\t\t\tLoad ? PIn : SIn), +\t\t\t\t\t\t\t\t.Out(\t\t\t\tPOut)); +\tend else begin:SHIFT +\t\tHardRegister #(\t\t\t.Width(\t\t\t\tPWidth), +\t\t\t\t\t\t\t\t.Initial(\t\t\tInitial), +\t\t\t\t\t\t\t\t.AsyncReset(\t\tAsyncReset)) +\t\t\t\t\tRegister(\t.Clock(\t\t\t\tClock), +\t\t\t\t\t\t\t\t.Reset(\t\t\t\tReset), +\t\t\t\t\t\t\t\t.Set(\t\t\t\t1\'b0), +\t\t\t\t\t\t\t\t.Enable(\t\t\tLoad | Enable), +\t\t\t\t\t\t\t\t.In(\t\t\t\tLoad ? PIn : (Reverse ? {SIn, POut[PWidth-1:SWidth]} : {POut[PWidth-SWidth-1:0], SIn})), +\t\t\t\t\t\t\t\t.Out(\t\t\t\tPOut)); +\tend endgenerate +\t//-------------------------------------------------------------------------- +endmodule +//------------------------------------------------------------------------------ +" +"//============================================================================== +//\tFile:\t\t$URL: svn+ssh://repositorypub@repository.eecs.berkeley.edu/public/Projects/GateLib/branches/dev/Publications/Tutorials/Publications/EECS150/Labs/ChipScopeSerial/Framework/HardRegister.v $ +//\tVersion:\t$Revision: 26904 $ +//\tAuthor:\t\tGreg Gibeling (http://www.gdgib.com) +//\tCopyright:\tCopyright 2003-2010 UC Berkeley +//============================================================================== + +//============================================================================== +//\tSection:\tLicense +//============================================================================== +//\tCopyright (c) 2005-2010, Regents of the University of California +//\tAll rights reserved. +// +//\tRedistribution and use in source and binary forms, with or without modification, +//\tare permitted provided that the following conditions are met: +// +//\t\t- Redistributions of source code must retain the above copyright notice, +//\t\t\tthis list of conditions and the following disclaimer. +//\t\t- Redistributions in binary form must reproduce the above copyright +//\t\t\tnotice, this list of conditions and the following disclaimer +//\t\t\tin the documentation and/or other materials provided with the +//\t\t\tdistribution. +//\t\t- Neither the name of the University of California, Berkeley nor the +//\t\t\tnames of its contributors may be used to endorse or promote +//\t\t\tproducts derived from this software without specific prior +//\t\t\twritten permission. +// +//\tTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" AND +//\tANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +//\tWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +//\tDISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +//\tANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +//\t(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +//\tLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +//\tANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +//\t(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +//\tSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== + +//------------------------------------------------------------------------------ +//\tModule:\t\tHardRegister +//\tDesc:\t\tA register which should not be removed by synthesis +//\tAuthor:\t\tGreg Gibeling +//\tVersion:\t$Revision: 26904 $ +//------------------------------------------------------------------------------ +module\tHardRegister(Clock, Reset, Set, Enable, In, Out) /* synthesis syn_hier = ""hard"" */; +\t//-------------------------------------------------------------------------- +\t//\tParameters +\t//-------------------------------------------------------------------------- +\tparameter\t\t\t\tWidth = \t\t\t\t32, +\t\t\t\t\t\t\tInitial =\t\t\t\t{Width{1\'bx}}, +\t\t\t\t\t\t\tAsyncReset =\t\t\t0, +\t\t\t\t\t\t\tAsyncSet =\t\t\t\t0, +\t\t\t\t\t\t\tResetValue =\t\t\t{Width{1\'b0}}, +\t\t\t\t\t\t\tSetValue =\t\t\t\t{Width{1\'b1}}; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tInputs & Outputs +\t//-------------------------------------------------------------------------- +\tinput\t\t\t\t\tClock, Enable, Reset, Set; +\tinput\t[Width-1:0]\t\tIn; +\toutput reg [Width-1:0]\tOut =\t\t\t\t\tInitial /* synthesis syn_keep = 1 */; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tBehavioral Register +\t//-------------------------------------------------------------------------- +\tgenerate if (AsyncReset) begin:AR +\t\tif (AsyncSet) begin:AS +\t\t\talways @ (posedge Clock or posedge Reset or posedge Set) begin +\t\t\t\tif (Reset) Out <=\t\t\t\t\tResetValue; +\t\t\t\telse if (Set) Out <=\t\t\t\tSetValue; +\t\t\t\telse if (Enable) Out <=\t\t\t\tIn; +\t\t\tend +\t\tend else begin:SS +\t\t\talways @ (posedge Clock or posedge Reset) begin +\t\t\t\tif (Reset) Out <=\t\t\t\t\tResetValue; +\t\t\t\telse if (Set) Out <=\t\t\t\tSetValue; +\t\t\t\telse if (Enable) Out <=\t\t\t\tIn; +\t\t\tend +\t\tend +\tend else begin:SR +\t\tif (AsyncSet) begin:AS +\t\t\talways @ (posedge Clock or posedge Set) begin +\t\t\t\tif (Reset) Out <=\t\t\t\t\tResetValue; +\t\t\t\telse if (Set) Out <=\t\t\t\tSetValue; +\t\t\t\telse if (Enable) Out <=\t\t\t\tIn; +\t\t\tend +\t\tend else begin:SS +\t\t\talways @ (posedge Clock) begin +\t\t\t\tif (Reset) Out <=\t\t\t\t\tResetValue; +\t\t\t\telse if (Set) Out <=\t\t\t\tSetValue; +\t\t\t\telse if (Enable) Out <=\t\t\t\tIn; +\t\t\tend +\t\tend +\tend endgenerate +\t//-------------------------------------------------------------------------- +endmodule +//------------------------------------------------------------------------------ +" +"//============================================================================== +//\tFile:\t\t$URL: svn+ssh://repositorypub@repository.eecs.berkeley.edu/public/Projects/GateLib/branches/dev/Firmware/UART/Hardware/UAReceiver.v $ +//\tVersion:\t$Revision: 26904 $ +//\tAuthor:\t\tGreg Gibeling (http://www.gdgib.com) +//\tCopyright:\tCopyright 2003-2010 UC Berkeley +//============================================================================== + +//============================================================================== +//\tSection:\tLicense +//============================================================================== +//\tCopyright (c) 2003-2010, Regents of the University of California +//\tAll rights reserved. +// +//\tRedistribution and use in source and binary forms, with or without modification, +//\tare permitted provided that the following conditions are met: +// +//\t\t- Redistributions of source code must retain the above copyright notice, +//\t\t\tthis list of conditions and the following disclaimer. +//\t\t- Redistributions in binary form must reproduce the above copyright +//\t\t\tnotice, this list of conditions and the following disclaimer +//\t\t\tin the documentation and/or other materials provided with the +//\t\t\tdistribution. +//\t\t- Neither the name of the University of California, Berkeley nor the +//\t\t\tnames of its contributors may be used to endorse or promote +//\t\t\tproducts derived from this software without specific prior +//\t\t\twritten permission. +// +//\tTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" AND +//\tANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +//\tWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +//\tDISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +//\tANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +//\t(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +//\tLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +//\tANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +//\t(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +//\tSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== + +//============================================================================== +//\tSection:\tIncludes +//============================================================================== +`include ""Const.v"" +//============================================================================== + +//------------------------------------------------------------------------------ +//\tModule:\t\tUAReceiver +//\tDesc:\t\tStandard Universal Asynchronous RS232/16550 type receiver. +//\tParams:\t\tClockFreq: Frequency (in Hz) of the ""Clock"" being fed to this +//\t\t\t\t\t\tmodule. +//\t\t\t\tBaud:\tDesired Baud rate. This is the rate at which this +//\t\t\t\t\t\tmodule will send bits, and should be at most 1/4th +//\t\t\t\t\t\tof the clock rate (or so). +//\t\t\t\tWidth:\tWord width (in bits) of the words (bytes) send over +//\t\t\t\t\t\tthe serial line. +//\t\t\t\tParity:\tThe type of parity bit to be appended to each word of +//\t\t\t\t\t\tdata. +//\t\t\t\t\t\t0:\tNone +//\t\t\t\t\t\t1:\tEven +//\t\t\t\t\t\t2:\tOdd +//\t\t\t\t\t\t3:\tMark +//\t\t\t\t\t\t4:\tSpace +//\t\t\t\tStopBits:The number of bit-periods to send the stop condition. +//\t\t\t\t\t\tGenerally 1 or 2, though larger numbers are possible. +//\tEx:\t\t\t(27000000, 9600, 8, 0, 1) Standard 9600baud 8-N-1 serial port +//\t\t\t\t\t\tsettings used as the default by many devices, based +//\t\t\t\t\t\ton a 27MHz clock. +//------------------------------------------------------------------------------ +module UAReceiver(Clock, Reset, DataOut, DataOutValid, DataOutReady, SIn); +\t//-------------------------------------------------------------------------- +\t//\tParameters +\t//-------------------------------------------------------------------------- +\tparameter\t\t\t\tClockFreq =\t\t\t\t27000000, +\t\t\t\t\t\t\tBaud =\t\t\t\t\t115200, +\t\t\t\t\t\t\tWidth =\t\t\t\t\t8, +\t\t\t\t\t\t\tParity =\t\t\t\t0, +\t\t\t\t\t\t\tStopBits =\t\t\t\t1; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tLocal Parameters +\t//-------------------------------------------------------------------------- +\t`ifdef MACROSAFE +\tlocalparam\t\t\t\tDivisor =\t\t\t\tClockFreq / Baud, +\t\t\t\t\t\t\tDivWidth =\t\t\t\t`log2(Divisor), +\t\t\t\t\t\t\tCapture =\t\t\t\t(Divisor / 2), +\t\t\t\t\t\t\tBitCount =\t\t\t\tWidth + StopBits + (Parity ? 1 : 0) + 1, +\t\t\t\t\t\t\tBCWidth =\t\t\t\t`log2(BitCount + 1), +\t\t\t\t\t\t\tActualBaud =\t\t\tClockFreq / Divisor; +\t`endif + +\t`ifdef SIMULATION +\tlocalparam real\t\t\tMaxBaud =\t\t\t\tClockFreq / ((Divisor * (BitCount - 0.5)) / BitCount), +\t\t\t\t\t\t\tMinBaud =\t\t\t\tClockFreq / ((Divisor * (BitCount + 0.5)) / BitCount); +\t`endif +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tConstant Debugging Statements +\t//-------------------------------------------------------------------------- +\t`ifdef SIMULATION +\t\tinitial begin +\t\t\t$display(""DEBUG[%m @ %t]: UART Parameters"", $time); +\t\t\t$display("" ClockFreq = %d"", ClockFreq); +\t\t\t$display("" Baud = %d"", Baud); +\t\t\t$display("" Width = %d"", Width); +\t\t\t$display("" Parity = %d"", Parity); +\t\t\t$display("" StopBits = %d"", StopBits); + +\t\t\t/*$display("" Divisor = %d"", Divisor); +\t\t\t$display("" DivWidth = %d"", DivWidth); +\t\t\t$display("" Capture = %d"", Capture); +\t\t\t$display("" BitCount = %d"", BitCount); +\t\t\t$display("" BCWidth = %d"", BCWidth);*/ + +\t\t\t$display("" ActualBaud = %d"", ActualBaud); +\t\t\t$display("" MaxBaud = %f"", MaxBaud); +\t\t\t$display("" MinBaud = %f"", MinBaud); +\t\tend +\t`endif +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tSystem Inputs +\t//-------------------------------------------------------------------------- +\tinput\t\t\t\t\tClock, Reset;\t +\t//-------------------------------------------------------------------------- +\t +\t//-------------------------------------------------------------------------- +\t//\tParallel Data Output +\t//-------------------------------------------------------------------------- +\toutput\t[Width-1:0]\t\tDataOut; +\toutput\t\t\t\t\tDataOutValid; +\tinput\t\t\t\t\tDataOutReady; +\t//-------------------------------------------------------------------------- +\t +\t//-------------------------------------------------------------------------- +\t//\tSerial Interface +\t//-------------------------------------------------------------------------- +\tinput\t\t\t\t\tSIn; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\t Wires and Regs +\t//-------------------------------------------------------------------------- +\twire\t\t\t\t\tIntSIn; + +\twire\t[DivWidth-1:0]\tRxDivCount; +\twire\t[BCWidth-1:0]\tRxBitCount; +\twire\t[BitCount-1:0]\tRxData; +\twire\t\t\t\t\tRxShiftEnable, RxRunning, RxBit, RxStart, RxTransfered; + +\twire\t\t\t\t\tRxStartBit, RxActualParity; +\twire\t[StopBits-1:0]\tRxStopBits; + +\twire\t\t\t\t\tRxParity; +\twire\t[Width-1:0]\t\tRxDataStripped; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tAssigns and Decodes +\t//-------------------------------------------------------------------------- +\tassign\tRxShiftEnable =\t\t\t\t\t\t\t(RxDivCount == Capture); +\tassign\tRxRunning =\t\t\t\t\t\t\t\t(RxBitCount < BitCount); +\tassign\tRxBit =\t\t\t\t\t\t\t\t\tRxRunning & RxShiftEnable; +\tassign\tRxStart =\t\t\t\t\t\t\t\t~IntSIn & ~RxRunning; +\t +\tassign\tRxStartBit =\t\t\t\t\t\t\tRxData[BitCount-1]; +\tassign\tRxActualParity =\t\t\t\t\t\tRxData[StopBits]; +\tassign\tRxStopBits =\t\t\t\t\t\t\tRxData[StopBits-1:0]; +\t +\tassign\tDataOutValid =\t\t\t\t\t\t\t(~RxStartBit) & (&RxStopBits) & ~RxTransfered & (Parity ? ~(RxParity ^ RxActualParity) : 1\'b1); +\tassign\tRxDataStripped =\t\t\t\t\t\tParity ? RxData[BitCount-2:StopBits+1] : RxData[BitCount-2:StopBits]; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tIO Register +\t//-------------------------------------------------------------------------- +\tIORegister\t\tIOR(\t\t.Clock(\t\t\t\tClock), +\t\t\t\t\t\t\t\t.Reset(\t\t\t\t1\'b0), +\t\t\t\t\t\t\t\t.Set(\t\t\t\t1\'b0), +\t\t\t\t\t\t\t\t.Enable(\t\t\t1\'b1), +\t\t\t\t\t\t\t\t.In(\t\t\t\tSIn), +\t\t\t\t\t\t\t\t.Out(\t\t\t\tIntSIn)); +\tdefparam\t\tIOR.Width =\t\t\t\t\t\t1; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tClock Divider Counter +\t//-------------------------------------------------------------------------- +\tCounter\t\t\tRxDivCounter(.Clock(\t\t\tClock), +\t\t\t\t\t\t\t\t.Reset(\t\t\t\tReset | (RxDivCount == (Divisor-1)) | RxStart), +\t\t\t\t\t\t\t\t.Set(\t\t\t\t1\'b0), +\t\t\t\t\t\t\t\t.Load(\t\t\t\t1\'b0), +\t\t\t\t\t\t\t\t.Enable(\t\t\t1\'b1), +\t\t\t\t\t\t\t\t.In(\t\t\t\t{DivWidth{1\'bx}}), +\t\t\t\t\t\t\t\t.Count(\t\t\t\tRxDivCount)); +\tdefparam\t\tRxDivCounter.Width =\t\t\tDivWidth; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tBit Counter +\t//-------------------------------------------------------------------------- +\tCounter\t\t\tRxBitCounter(.Clock(\t\t\tClock), +\t\t\t\t\t\t\t\t.Reset(\t\t\t\tRxStart), +\t\t\t\t\t\t\t\t.Set(\t\t\t\tReset), +\t\t\t\t\t\t\t\t.Load(\t\t\t\t1\'b0), +\t\t\t\t\t\t\t\t.Enable(\t\t\tRxBit), +\t\t\t\t\t\t\t\t.In(\t\t\t\t{BCWidth{1\'bx}}), +\t\t\t\t\t\t\t\t.Count(\t\t\t\tRxBitCount)); +\tdefparam\t\tRxBitCounter.Width =\t\t\tBCWidth; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tShift Register and Bit Reversal +\t//-------------------------------------------------------------------------- +\tShiftRegister\tRxShift(\t.PIn(\t\t\t\t{BitCount{1\'b1}}), +\t\t\t\t\t\t\t\t.SIn(\t\t\t\tIntSIn), +\t\t\t\t\t\t\t\t.POut(\t\t\t\tRxData), +\t\t\t\t\t\t\t\t.SOut(\t\t\t\t), +\t\t\t\t\t\t\t\t.Load(\t\t\t\tReset), +\t\t\t\t\t\t\t\t.Enable(\t\t\tRxShiftEnable), +\t\t\t\t\t\t\t\t.Clock(\t\t\t\tClock), +\t\t\t\t\t\t\t\t.Reset(\t\t\t\t1\'b0)); +\tdefparam\t\tRxShift.PWidth =\t\t\t\tBitCount; +\tdefparam\t\tRxShift.SWidth =\t\t\t\t1; +\tReverse\t\t\tRxReverse(\t.In(\t\t\t\tRxDataStripped), +\t\t\t\t\t\t\t\t.Out(\t\t\t\tDataOut)); +\tdefparam\t\tRxReverse.Width =\t\t\t\tWidth; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tRegister +\t//-------------------------------------------------------------------------- +\tRegister\t\tRXTR(\t\t.Clock(\t\t\t\tClock), +\t\t\t\t\t\t\t\t.Reset(\t\t\t\t1\'b0), +\t\t\t\t\t\t\t\t.Set(\t\t\t\tReset | (DataOutReady & DataOutValid)), +\t\t\t\t\t\t\t\t.Enable(\t\t\tRxShiftEnable), +\t\t\t\t\t\t\t\t.In(\t\t\t\t(RxBitCount != (BitCount - 1))), +\t\t\t\t\t\t\t\t.Out(\t\t\t\tRxTransfered)); +\tdefparam\t\tRXTR.Width =\t\t\t\t\t1; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tParity Generator +\t//-------------------------------------------------------------------------- +\tParityGen\t\tRxParityGen(.In(\t\t\t\tDataOut), +\t\t\t\t\t\t\t\t.Out(\t\t\t\tRxParity)); +\tdefparam\t\tRxParityGen.Width =\t\t\t\tWidth; +\tdefparam\t\tRxParityGen.Parity =\t\t\tParity; +\t//-------------------------------------------------------------------------- +endmodule +//------------------------------------------------------------------------------ +" +"//============================================================================== +//\tFile:\t\t$URL: svn+ssh://repositorypub@repository.eecs.berkeley.edu/public/Projects/GateLib/branches/dev/Publications/Tutorials/Publications/EECS150/Labs/ChipScopeSerial/Framework/Register.v $ +//\tVersion:\t$Revision: 26904 $ +//\tAuthor:\t\tGreg Gibeling (http://www.gdgib.com) +//\tCopyright:\tCopyright 2003-2010 UC Berkeley +//============================================================================== + +//============================================================================== +//\tSection:\tLicense +//============================================================================== +//\tCopyright (c) 2003-2010, Regents of the University of California +//\tAll rights reserved. +// +//\tRedistribution and use in source and binary forms, with or without modification, +//\tare permitted provided that the following conditions are met: +// +//\t\t- Redistributions of source code must retain the above copyright notice, +//\t\t\tthis list of conditions and the following disclaimer. +//\t\t- Redistributions in binary form must reproduce the above copyright +//\t\t\tnotice, this list of conditions and the following disclaimer +//\t\t\tin the documentation and/or other materials provided with the +//\t\t\tdistribution. +//\t\t- Neither the name of the University of California, Berkeley nor the +//\t\t\tnames of its contributors may be used to endorse or promote +//\t\t\tproducts derived from this software without specific prior +//\t\t\twritten permission. +// +//\tTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" AND +//\tANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +//\tWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +//\tDISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +//\tANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +//\t(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +//\tLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +//\tANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +//\t(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +//\tSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== + +//------------------------------------------------------------------------------ +//\tModule:\t\tRegister +//\tDesc:\t\tIf you don\'t know, I can\'t help you. +//\tAuthor:\t\tGreg Gibeling +//\tVersion:\t$Revision: 26904 $ +//------------------------------------------------------------------------------ +module\tRegister(Clock, Reset, Set, Enable, In, Out); +\t//-------------------------------------------------------------------------- +\t//\tParameters +\t//-------------------------------------------------------------------------- +\tparameter\t\t\t\tWidth = \t\t\t\t32, +\t\t\t\t\t\t\tInitial =\t\t\t\t{Width{1\'bx}}, +\t\t\t\t\t\t\tAsyncReset =\t\t\t0, +\t\t\t\t\t\t\tAsyncSet =\t\t\t\t0, +\t\t\t\t\t\t\tResetValue =\t\t\t{Width{1\'b0}}, +\t\t\t\t\t\t\tSetValue =\t\t\t\t{Width{1\'b1}}; +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tInputs & Outputs +\t//-------------------------------------------------------------------------- +\tinput\t\t\t\t\tClock, Enable, Reset, Set; +\tinput\t[Width-1:0]\t\tIn; +\toutput reg [Width-1:0]\tOut =\t\t\t\t\tInitial; +\t//-------------------------------------------------------------------------- +\t +\t//-------------------------------------------------------------------------- +\t//\tBehavioral Register +\t//-------------------------------------------------------------------------- +\tgenerate if (AsyncReset) begin:AR +\t\tif (AsyncSet) begin:AS +\t\t\talways @ (posedge Clock or posedge Reset or posedge Set) begin +\t\t\t\tif (Reset) Out <=\t\t\t\t\tResetValue; +\t\t\t\telse if (Set) Out <=\t\t\t\tSetValue; +\t\t\t\telse if (Enable) Out <=\t\t\t\tIn; +\t\t\tend +\t\tend else begin:SS +\t\t\talways @ (posedge Clock or posedge Reset) begin +\t\t\t\tif (Reset) Out <=\t\t\t\t\tResetValue; +\t\t\t\telse if (Set) Out <=\t\t\t\tSetValue; +\t\t\t\telse if (Enable) Out <=\t\t\t\tIn; +\t\t\tend +\t\tend +\tend else begin:SR +\t\tif (AsyncSet) begin:AS +\t\t\talways @ (posedge Clock or posedge Set) begin +\t\t\t\tif (Reset) Out <=\t\t\t\t\tResetValue; +\t\t\t\telse if (Set) Out <=\t\t\t\tSetValue; +\t\t\t\telse if (Enable) Out <=\t\t\t\tIn; +\t\t\tend +\t\tend else begin:SS +\t\t\talways @ (posedge Clock) begin +\t\t\t\tif (Reset) Out <=\t\t\t\t\tResetValue; +\t\t\t\telse if (Set) Out <=\t\t\t\tSetValue; +\t\t\t\telse if (Enable) Out <=\t\t\t\tIn; +\t\t\tend +\t\tend +\tend endgenerate +\t//-------------------------------------------------------------------------- +endmodule +//------------------------------------------------------------------------------ +" +"//============================================================================== +//\tFile: $URL: svn+ssh://repositorypub@repository.eecs.berkeley.edu/public/Projects/GateLib/branches/dev/Publications/Tutorials/Publications/EECS150/Labs/ChipScopeSerial/Solution/Gateway.v $ +//\tVersion: $Revision: 26904 $ +//\tAuthor: John Wawrzynek +//\t\t\t Chris Fletcher (http://cwfletcher.net) +//\tCopyright: Copyright 2009-2010 UC Berkeley +//============================================================================== + +//============================================================================== +//\tSection:\tLicense +//============================================================================== +//\tCopyright (c) 2005-2010, Regents of the University of California +//\tAll rights reserved. +// +//\tRedistribution and use in source and binary forms, with or without modification, +//\tare permitted provided that the following conditions are met: +// +//\t\t- Redistributions of source code must retain the above copyright notice, +//\t\t\tthis list of conditions and the following disclaimer. +//\t\t- Redistributions in binary form must reproduce the above copyright +//\t\t\tnotice, this list of conditions and the following disclaimer +//\t\t\tin the documentation and/or other materials provided with the +//\t\t\tdistribution. +//\t\t- Neither the name of the University of California, Berkeley nor the +//\t\t\tnames of its contributors may be used to endorse or promote +//\t\t\tproducts derived from this software without specific prior +//\t\t\twritten permission. +// +//\tTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" AND +//\tANY EXPRESS OR InIMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE InIMPLIED +//\tWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +//\tDISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +//\tANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +//\t(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +//\tLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +//\tANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +//\t(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +//\tSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== + +//------------------------------------------------------------------------------ +//\tModule:\t +//\tDesc:\t +// +//\tAuthor:\tJohn Wawrzynek +//\t\t\tChris Fletcher +//\tVersion:\t$Revision: 26904 $ +//------------------------------------------------------------------------------ +module Gateway( +\t\t\t//------------------------------------------------------------------ +\t\t\t//\tClock and Related Signals +\t\t\t//------------------------------------------------------------------ +\t\t\tClock, +\t\t\tReset, +\t\t\t//------------------------------------------------------------------ +\t\t\t +\t\t\t//------------------------------------------------------------------ +\t\t\t//\tUART Interface +\t\t\t//------------------------------------------------------------------ +\t\t\tDataIn, +\t\t\tDataInValid, +\t\t\tDataInReady, +\t\t\tDataOut, +\t\t\tDataOutValid, +\t\t\tDataOutReady, +\t\t\t//------------------------------------------------------------------ +\t\t\t +\t\t\t//------------------------------------------------------------------ +\t\t\t//\tProcessor Interface +\t\t\t//------------------------------------------------------------------ +\t\t\tProcessorDataIn, +\t\t\tProcessorDataOut, +\t\t\tProcessorAddress, +\t\t\tProcessorMemRead, +\t\t\tProcessorMemWrite +\t\t\t//------------------------------------------------------------------ +\t); +\t//-------------------------------------------------------------------------- +\t//\tParameters +\t//-------------------------------------------------------------------------- +\tparameter\t\tCWidth = \t\t\t\t\t\t8, \t\t\t\t// char width +\t\t\t\t\tWWidth = \t\t\t\t\t\t32, \t\t\t// word width +\t\t\t\t\tAWidth =\t\t\t\t\t\tWWidth; +\t//-------------------------------------------------------------------------- +\t +\t//-------------------------------------------------------------------------- +\t//\tAddress map +\t//-------------------------------------------------------------------------- +\tlocalparam\t\tADDRESS_ControlIn = \t\t\t32\'hffff_0000,\t// control input +\t\t\t\t\tADDRESS_DataIn =\t\t\t\t32\'hffff_0004,\t// data input +\t\t\t\t\tADDRESS_ControlOut =\t\t\t32\'hffff_0008,\t// control output +\t\t\t\t\tADDRESS_DataOut = \t\t\t\t32\'hffff_000C;\t// data output +\t//-------------------------------------------------------------------------- + +\t//-------------------------------------------------------------------------- +\t//\tClock and Related Signals +\t//-------------------------------------------------------------------------- +\tinput wire \t\t\t\t\t\t\t\t\t\tClock, Reset; +\t//-------------------------------------------------------------------------- +\t +\t//-------------------------------------------------------------------------- +\t//\tUART Interface +\t//-------------------------------------------------------------------------- +\tinput\t\t\t[CWidth-1:0]\t\t\t\t\tDataIn; +\tinput\t\t\t\t\t\t\t\t\t\t\tDataInValid; +\toutput\t\t\t\t\t\t\t\t\t\t\tDataInReady; +\toutput\t\t\t[CWidth-1:0]\t\t\t\t\tDataOut; +\toutput\t\t\t\t\t\t\t\t\t\t\tDataOutValid; +\tinput\t\t\t\t\t\t\t\t\t\t\tDataOutReady; +\t//-------------------------------------------------------------------------- +\t +\t//-------------------------------------------------------------------------- +\t//\tProcessor Interface +\t//-------------------------------------------------------------------------- +\toutput wire\t\t[WWidth-1:0]\t\t\t\t\tProcessorDataIn; +\tinput wire\t\t[WWidth-1:0]\t\t\t\t\tProcessorDataOut, ProcessorAddress; +\tinput wire\t\t\t\t\t\t\t\t\t\tProcessorMemRead, ProcessorMemWrite; +\t//-------------------------------------------------------------------------- +\t +\t//-------------------------------------------------------------------------- +\t//\tWires / Reg Declarations +\t//-------------------------------------------------------------------------- +\twire\t\t\t[CWidth-1:0]\t\t\t\t\tDataInReg; +\twire\t\t\t\t\t\t\t\t\t\t\tControlInReady, PollingControlIn, PollingControlOut, WritingData; +\t//--------------------------------------------------------------------------\t +\t +\t//-------------------------------------------------------------------------- +\t//\tPort Assigns +\t//-------------------------------------------------------------------------- +\tassign\t\t\tDataInReady =\t\t\t\t\t~ControlInReady; +\tassign\t\t\tProcessorDataIn =\t\t\t\t(PollingControlIn) ? {{WWidth-1{1\'b0}}, ControlInReady} : (PollingControlOut) ? {{WWidth-1{1\'b0}}, DataOutValid} : {{WWidth-CWidth-1{1\'b0}}, DataInReg}; +\t//--------------------------------------------------------------------------\t\t + +\t//-------------------------------------------------------------------------- +\t//\tAssigns +\t//-------------------------------------------------------------------------- +\tassign\t\t\tUARTDataInTransfer = \t\t\tDataInReady & DataInValid; +\tassign\t\t\tUARTDataOutTransfer = \t\t\tDataOutReady & DataOutValid; +\tassign\t\t\tPollingControlIn =\t\t\t\tProcessorAddress == ADDRESS_ControlIn; +\tassign\t\t\tPollingControlOut = \t\t\tProcessorAddress == ADDRESS_ControlOut; +\tassign\t\t\tReadingData = \t\t\t\t\tProcessorMemRead & ProcessorAddress == ADDRESS_DataIn; +\tassign\t\t\tWritingData = \t\t\t\t\tProcessorMemWrite & ProcessorAddress == ADDRESS_DataOut;\t +\t//-------------------------------------------------------------------------- +\t +\t//-------------------------------------------------------------------------- +\t//\tControl Registers +\t//-------------------------------------------------------------------------- +\tRegister \t\t#(\t\t\t.Width(\t\t\t\t1)) +\t\t\t\t\tcIn (.Clock(Clock), .Reset(Reset | ReadingData), .Set(UARTDataInTransfer), .Enable(1\'b0), .In(1\'bx), .Out(ControlInReady)), +\t\t\t\t\tcOut (.Clock(Clock), .Reset(Reset | UARTDataOutTransfer), .Set(WritingData), .Enable(1\'b0), .In(1\'bx), .Out(DataOutValid)); +\t//--------------------------------------------------------------------------\t\t\t\t +\t +\t//-------------------------------------------------------------------------- +\t//\tData Registers +\t//-------------------------------------------------------------------------- +\tRegister\t\t#(\t\t\t.Width(\t\t\t\tCWidth)) +\t\t\t\t\tdIn (.Clock(Clock), .Reset(Reset), .Set(1\'b0), .Enable(UARTDataInTransfer), .In(DataIn), .Out(DataInReg)), +\t\t\t\t\tdOut (.Clock(Clock), .Reset(Reset), .Set(1\'b0), .Enable(WritingData), .In(ProcessorDataOut[7:0]), .Out(DataOut));\t +\t//-------------------------------------------------------------------------- +endmodule +//------------------------------------------------------------------------------ +" +"//============================================================================== +//\tFile:\t\t$URL: svn+ssh://repositorypub@repository.eecs.berkeley.edu/public/Projects/GateLib/branches/dev/Publications/Tutorials/Publications/EECS150/Labs/ChipScopeSerial/Framework/Const.v $ +//\tVersion:\t$Revision: 26904 $ +//\tAuthor:\t\tGreg Gibeling (http://www.gdgib.com) +//\tCopyright:\tCopyright 2003-2010 UC Berkeley +//============================================================================== + +//============================================================================== +//\tSection:\tLicense +//============================================================================== +//\tCopyright (c) 2005-2010, Regents of the University of California +//\tAll rights reserved. +// +//\tRedistribution and use in source and binary forms, with or without modification, +//\tare permitted provided that the following conditions are met: +// +//\t\t- Redistributions of source code must retain the above copyright notice, +//\t\t\tthis list of conditions and the following disclaimer. +//\t\t- Redistributions in binary form must reproduce the above copyright +//\t\t\tnotice, this list of conditions and the following disclaimer +//\t\t\tin the documentation and/or other materials provided with the +//\t\t\tdistribution. +//\t\t- Neither the name of the University of California, Berkeley nor the +//\t\t\tnames of its contributors may be used to endorse or promote +//\t\t\tproducts derived from this software without specific prior +//\t\t\twritten permission. +// +//\tTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" AND +//\tANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +//\tWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +//\tDISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +//\tANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +//\t(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +//\tLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +//\tANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +//\t(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +//\tSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//============================================================================== + +//------------------------------------------------------------------------------ +//\tSection:\tSimulation Flag +//\tDesc:\t\tThis little nebulous block will define the flags: +//\t\t\t\t-SIMULATION\tSimulating +//\t\t\t\t-MODELSIM\tSimulating using ModelSim +//\t\t\t\t-XST\t\tSynthesizing with XST +//\t\t\t\t-SYNPLIFY\tSynthesizing with Synplify +//\t\t\t\t-SYNTHESIS\tSynthesizing +//\t\t\t\t-MACROSAFE\tSafe to use macros (Synplify or ModelSim) +// +//\tYOU SHOULD DEFINE THE ""MODELSIM"" FLAG FOR SIMULATION!!!! +//------------------------------------------------------------------------------ +`ifdef synthesis // if Synplify +\t`define SYNPLIFY +\t`define SYNTHESIS +\t`define MACROSAFE +`else // if not Synplify +\t`ifdef MODELSIM +\t\t`define SIMULATION +\t\t`define MACROSAFE +\t`else +\t\t`define XST +\t\t// synthesis translate_off // if XST then stop compiling +\t\t\t`undef XST +\t\t\t`define SIMULATION +\t\t\t`define MODELSIM +\t\t// synthesis translate_on // if XST then resume compiling +\t\t`ifdef XST +\t\t\t`define SYNTHESIS +\t\t\t`define MACROSAFE +\t\t`endif +\t`endif +`endif +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +//\tSection:\tLog2 Macro +//\tDesc:\t\tA macro to take the log base 2 of any number. Useful for +//\t\t\t\tcalculating bitwidths. Warning, this actually calculates +//\t\t\t\tlog2(x-1), not log2(x). +//------------------------------------------------------------------------------ +`ifdef MACROSAFE +`define log2(x)\t\t((((x) > 1) ? 1 : 0) + \\ +\t\t\t(((x) > 2) ? 1 : 0) + \\ +\t\t\t(((x) > 4) ? 1 : 0) + \\ +\t\t\t(((x) > 8) ? 1 : 0) + \\ +\t\t\t(((x) > 16) ? 1 : 0) + \\ +\t\t\t(((x) > 32) ? 1 : 0) + \\ +\t\t\t(((x) > 64) ? 1 : 0) + \\ +\t\t\t(((x) > 128) ? 1 : 0) + \\ +\t\t\t(((x) > 256) ? 1 : 0) + \\ +\t\t\t(((x) > 512) ? 1 : 0) + \\ +\t\t\t(((x) > 1024) ? 1 : 0) + \\ +\t\t\t(((x) > 2048) ? 1 : 0) + \\ +\t\t\t(((x) > 4096) ? 1 : 0) + \\ +\t\t\t(((x) > 8192) ? 1 : 0) + \\ +\t\t\t(((x) > 16384) ? 1 : 0) + \\ +\t\t\t(((x) > 32768) ? 1 : 0) + \\ +\t\t\t(((x) > 65536) ? 1 : 0) + \\ +\t\t\t(((x) > 131072) ? 1 : 0) + \\ +\t\t\t(((x) > 262144) ? 1 : 0) + \\ +\t\t\t(((x) > 524288) ? 1 : 0) + \\ +\t\t\t(((x) > 1048576) ? 1 : 0) + \\ +\t\t\t(((x) > 2097152) ? 1 : 0) + \\ +\t\t\t(((x) > 4194304) ? 1 : 0) + \\ +\t\t\t(((x) > 8388608) ? 1 : 0) + \\ +\t\t\t(((x) > 16777216) ? 1 : 0) + \\ +\t\t\t(((x) > 33554432) ? 1 : 0) + \\ +\t\t\t(((x) > 67108864) ? 1 : 0) + \\ +\t\t\t(((x) > 134217728) ? 1 : 0) + \\ +\t\t\t(((x) > 268435456) ? 1 : 0) + \\ +\t\t\t(((x) > 536870912) ? 1 : 0) + \\ +\t\t\t(((x) > 1073741824) ? 1 : 0)) +`endif +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +//\tSection:\tLog2 Floor Macro +//\tDesc:\t\tA macro to take the floor of the log base 2 of any number. +//------------------------------------------------------------------------------ +`ifdef MACROSAFE +`define log2f(x)\t((((x) >= 2) ? 1 : 0) + \\ +\t\t\t(((x) >= 4) ? 1 : 0) + \\ +\t\t\t(((x) >= 8) ? 1 : 0) + \\ +\t\t\t(((x) >= 16) ? 1 : 0) + \\ +\t\t\t(((x) >= 32) ? 1 : 0) + \\ +\t\t\t(((x) >= 64) ? 1 : 0) + \\ +\t\t\t(((x) >= 128) ? 1 : 0) + \\ +\t\t\t(((x) >= 256) ? 1 : 0) + \\ +\t\t\t(((x) >= 512) ? 1 : 0) + \\ +\t\t\t(((x) >= 1024) ? 1 : 0) + \\ +\t\t\t(((x) >= 2048) ? 1 : 0) + \\ +\t\t\t(((x) >= 4096) ? 1 : 0) + \\ +\t\t\t(((x) >= 8192) ? 1 : 0) + \\ +\t\t\t(((x) >= 16384) ? 1 : 0) + \\ +\t\t\t(((x) >= 32768) ? 1 : 0) + \\ +\t\t\t(((x) >= 65536) ? 1 : 0) + \\ +\t\t\t(((x) >= 131072) ? 1 : 0) + \\ +\t\t\t(((x) >= 262144) ? 1 : 0) + \\ +\t\t\t(((x) >= 524288) ? 1 : 0) + \\ +\t\t\t(((x) >= 1048576) ? 1 : 0) + \\ +\t\t\t(((x) >= 2097152) ? 1 : 0) + \\ +\t\t\t(((x) >= 4194304) ? 1 : 0) + \\ +\t\t\t(((x) >= 8388608) ? 1 : 0) + \\ +\t\t\t(((x) >= 16777216) ? 1 : 0) + \\ +\t\t\t(((x) >= 33554432) ? 1 : 0) + \\ +\t\t\t(((x) >= 67108864) ? 1 : 0) + \\ +\t\t\t(((x) >= 134217728) ? 1 : 0) + \\ +\t\t\t(((x) >= 268435456) ? 1 : 0) + \\ +\t\t\t(((x) >= 536870912) ? 1 : 0) + \\ +\t\t\t(((x) >= 1073741824) ? 1 : 0)) +`endif +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +//\tSection:\tPow2 Macro +//\tDesc:\t\tA macro to take the 2 to the power of any number. Useful for +//\t\t\t\tcalculating bitwidths. +//------------------------------------------------------------------------------ +`ifdef MACROSAFE +`define pow2(x)\t\t((((x) >= 1) ? 2 : 1) * \\ +\t\t\t(((x) >= 2) ? 2 : 1) * \\ +\t\t\t(((x) >= 3) ? 2 : 1) * \\ +\t\t\t(((x) >= 4) ? 2 : 1) * \\ +\t\t\t(((x) >= 5) ? 2 : 1) * \\ +\t\t\t(((x) >= 6) ? 2 : 1) * \\ +\t\t\t(((x) >= 7) ? 2 : 1) * \\ +\t\t\t(((x) >= 8) ? 2 : 1) * \\ +\t\t\t(((x) >= 9) ? 2 : 1) * \\ +\t\t\t(((x) >= 10) ? 2 : 1) * \\ +\t\t\t(((x) >= 11) ? 2 : 1) * \\ +\t\t\t(((x) >= 12) ? 2 : 1) * \\ +\t\t\t(((x) >= 13) ? 2 : 1) * \\ +\t\t\t(((x) >= 14) ? 2 : 1) * \\ +\t\t\t(((x) >= 15) ? 2 : 1) * \\ +\t\t\t(((x) >= 16) ? 2 : 1) * \\ +\t\t\t(((x) >= 17) ? 2 : 1) * \\ +\t\t\t(((x) >= 18) ? 2 : 1) * \\ +\t\t\t(((x) >= 19) ? 2 : 1) * \\ +\t\t\t(((x) >= 20) ? 2 : 1) * \\ +\t\t\t(((x) >= 21) ? 2 : 1) * \\ +\t\t\t(((x) >= 22) ? 2 : 1) * \\ +\t\t\t(((x) >= 23) ? 2 : 1) * \\ +\t\t\t(((x) >= 24) ? 2 : 1) * \\ +\t\t\t(((x) >= 25) ? 2 : 1) * \\ +\t\t\t(((x) >= 26) ? 2 : 1) * \\ +\t\t\t(((x) >= 27) ? 2 : 1) * \\ +\t\t\t(((x) >= 28) ? 2 : 1) * \\ +\t\t\t(((x) >= 29) ? 2 : 1) * \\ +\t\t\t(((x) >= 30) ? 2 : 1) * \\ +\t\t\t(((x) >= 31) ? 2 : 1)) +`endif +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +//\tSection:\tMax/Min Macros +//\tDesc:\t\tStandard binary max/min macros +//------------------------------------------------------------------------------ +`ifdef MACROSAFE +`define max(x,y)\t((x) > (y) ? (x) : (y)) +`define min(x,y)\t((x) < (y) ? (x) : (y)) +`endif +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +//\tSection:\tInteger Division Macros +//\tDesc:\t\tRounding and ceiling for integer division +//------------------------------------------------------------------------------ +`ifdef MACROSAFE +`define\tdivceil(x,y)\t(((x) + ((y) - 1)) / (y)) +`define\tdivrnd(x,y)\t(((x) + ((y) >> 1)) / (y)) +`endif +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +//\tSection:\tPopulation Count +//\tDesc:\t\tA population counter macro for 32bit values +//------------------------------------------------------------------------------ +`ifdef MACROSAFE +`define popcount(x)\t\t((((x) & 1) ? 1 : 0) + \\ +\t\t\t(((x) & 2) ? 1 : 0) + \\ +\t\t\t(((x) & 4) ? 1 : 0) + \\ +\t\t\t(((x) & 8) ? 1 : 0) + \\ +\t\t\t(((x) & 16) ? 1 : 0) + \\ +\t\t\t(((x) & 32) ? 1 : 0) + \\ +\t\t\t(((x) & 64) ? 1 : 0) + \\ +\t\t\t(((x) & 128) ? 1 : 0) + \\ +\t\t\t(((x) & 256) ? 1 : 0) + \\ +\t\t\t(((x) & 512) ? 1 : 0) + \\ +\t\t\t(((x) & 1024) ? 1 : 0) + \\ +\t\t\t(((x) & 2048) ? 1 : 0) + \\ +\t\t\t(((x) & 4096) ? 1 : 0) + \\ +\t\t\t(((x) & 8192) ? 1 : 0) + \\ +\t\t\t(((x) & 16384) ? 1 : 0) + \\ +\t\t\t(((x) & 32768) ? 1 : 0) + \\ +\t\t\t(((x) & 65536) ? 1 : 0) + \\ +\t\t\t(((x) & 131072) ? 1 : 0) + \\ +\t\t\t(((x) & 262144) ? 1 : 0) + \\ +\t\t\t(((x) & 524288) ? 1 : 0) + \\ +\t\t\t(((x) & 1048576) ? 1 : 0) + \\ +\t\t\t(((x) & 2097152) ? 1 : 0) + \\ +\t\t\t(((x) & 4194304) ? 1 : 0) + \\ +\t\t\t(((x) & 8388608) ? 1 : 0) + \\ +\t\t\t(((x) & 16777216) ? 1 : 0) + \\ +\t\t\t(((x) & 33554432) ? 1 : 0) + \\ +\t\t\t(((x) & 67108864) ? 1 : 0) + \\ +\t\t\t(((x) & 134217728) ? 1 : 0) + \\ +\t\t\t(((x) & 268435456) ? 1 : 0) + \\ +\t\t\t(((x) & 536870912) ? 1 : 0) + \\ +\t\t\t(((x) & 1073741824) ? 1 : 0)) +`endif +//------------------------------------------------------------------------------ +" +"/* + * Copyright (c) 2009 Zeus Gomez Marmolejo + * + * This file is part of the Zet processor. This processor is free + * hardware; you can redistribute it and/or modify it under the terms of + * the GNU General Public License as published by the Free Software + * Foundation; either version 3, or (at your option) any later version. + * + * Zet is distrubuted in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + * License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Zet; see the file COPYING. If not, see + * . + */ + +module hex_display ( + input [15:0] num, + input en, + + output [6:0] hex0, + output [6:0] hex1, + output [6:0] hex2, + output [6:0] hex3 + ); + + // Module instantiations + seg_7 hex_group0 ( + .num (num[3:0]), + .en (en), + .seg (hex0) + ); + + seg_7 hex_group1 ( + .num (num[7:4]), + .en (en), + .seg (hex1) + ); + + seg_7 hex_group2 ( + .num (num[11:8]), + .en (en), + .seg (hex2) + ); + + seg_7 hex_group3 ( + .num (num[15:12]), + .en (en), + .seg (hex3) + ); + +endmodule +" +"////////////////////////////////////////////////////////////////////////////////\r +// Original Author: Schuyler Eldridge\r +// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)\r +// button_debounce.v\r +// Created: 4.5.2012\r +// Modified: 4.5.2012\r +//\r +// Testbench for button_debounce.v.\r +// \r +// Copyright (C) 2012 Schuyler Eldridge, Boston University\r +//\r +// This program is free software: you can redistribute it and/or modify\r +// it under the terms of the GNU General Public License as published by\r +// the Free Software Foundation, either version 3 of the License.\r +//\r +// This program is distributed in the hope that it will be useful,\r +// but WITHOUT ANY WARRANTY; without even the implied warranty of\r +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r +// GNU General Public License for more details.\r +//\r +// You should have received a copy of the GNU General Public License\r +// along with this program. If not, see .\r +////////////////////////////////////////////////////////////////////////////////\r +`timescale 1ns / 1ps\r +module t_button_debounce();\r +\r + parameter\r + CLK_FREQUENCY = 66000000,\r + DEBOUNCE_HZ = 2;\r +\r + reg clk, reset_n, button;\r + wire debounce;\r + \r + button_debounce\r + #(\r + .CLK_FREQUENCY(CLK_FREQUENCY),\r + .DEBOUNCE_HZ(DEBOUNCE_HZ)\r + )\r + button_debounce\r + (\r + .clk(clk),\r + .reset_n(reset_n),\r + .button(button),\r + .debounce(debounce)\r + );\r +\r + initial begin\r + clk = 1'bx; reset_n = 1'bx; button = 1'bx;\r + #10 reset_n = 1;\r + #10 reset_n = 0; clk = 0;\r + #10 reset_n = 1;\r + #10 button = 0;\r + end\r +\r + always\r + #5 clk = ~clk;\r +\r + always begin\r + #100 button = ~button;\r + #0.1 button = ~button;\r + #0.1 button = ~button;\r + #0.1 button = ~button;\r + #0.1 button = ~button;\r + #0.1 button = ~button;\r + #0.1 button = ~button;\r + #0.1 button = ~button;\r + #0.1 button = ~button;\r + end\r + \r +endmodule\r +" +"////////////////////////////////////////////////////////////////////////////////\r +// Original Author: Schuyler Eldridge\r +// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)\r +// div_pipelined.v\r +// Created: 4.3.2012\r +// Modified: 4.5.2012\r +//\r +// Testbench for div_pipelined.v\r +//\r +// Copyright (C) 2012 Schuyler Eldridge, Boston University\r +//\r +// This program is free software: you can redistribute it and/or modify\r +// it under the terms of the GNU General Public License as published by\r +// the Free Software Foundation, either version 3 of the License.\r +//\r +// This program is distributed in the hope that it will be useful,\r +// but WITHOUT ANY WARRANTY; without even the implied warranty of\r +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r +// GNU General Public License for more details.\r +//\r +// You should have received a copy of the GNU General Public License\r +// along with this program. If not, see .\r +////////////////////////////////////////////////////////////////////////////////\r +`timescale 1ns / 1ps\r +module t_div_pipelined();\r +\r + reg clk, start, reset_n;\r + reg [7:0] dividend, divisor;\r + wire data_valid, div_by_zero;\r + wire [7:0] quotient, quotient_correct;\r +\r + parameter\r + BITS = 8;\r +\r + div_pipelined\r + #(\r + .BITS(BITS)\r + )\r + div_pipelined\r + (\r + .clk(clk),\r + .reset_n(reset_n),\r + .dividend(dividend),\r + .divisor(divisor),\r + .quotient(quotient),\r + .div_by_zero(div_by_zero),\r + // .quotient_correct(quotient_correct),\r + .start(start),\r + .data_valid(data_valid)\r + );\r +\r + initial begin\r + #10 reset_n = 0;\r + #50 reset_n = 1;\r + #1\r + clk = 0;\r + dividend = -1;\r + divisor = 127;\r + #1000 $finish;\r + end\r +\r +// always\r +// #20 dividend = dividend + 1;\r +\r + always begin\r + #10 divisor = divisor - 1; start = 1;\r + #10 start = 0;\r + end\r +\r + always\r + #5 clk = ~clk;\r +\r + \r +endmodule\r + " +"////////////////////////////////////////////////////////////////////////////////\r +// Original Author: Schuyler Eldridge\r +// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)\r +// sqrt_pipelined.v\r +// Created: 4.2.2012\r +// Modified: 4.5.2012\r +//\r +// Implements a fixed-point parameterized pipelined square root\r +// operation on an unsigned input of any bit length. The number of\r +// stages in the pipeline is equal to the number of output bits in the\r +// computation. This pipelien sustains a throughput of one computation\r +// per clock cycle.\r +// \r +// Copyright (C) 2012 Schuyler Eldridge, Boston University\r +//\r +// This program is free software: you can redistribute it and/or modify\r +// it under the terms of the GNU General Public License as published by\r +// the Free Software Foundation, either version 3 of the License.\r +//\r +// This program is distributed in the hope that it will be useful,\r +// but WITHOUT ANY WARRANTY; without even the implied warranty of\r +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r +// GNU General Public License for more details.\r +//\r +// You should have received a copy of the GNU General Public License\r +// along with this program. If not, see .\r +////////////////////////////////////////////////////////////////////////////////\r +`timescale 1ns / 1ps\r +module sqrt_pipelined\r + (\r + input clk, // clock\r + input reset_n, // asynchronous reset\r + input start, // optional start signal\r + input [INPUT_BITS-1:0] radicand, // unsigned radicand\r + output reg data_valid, // optional data valid signal\r + output reg [OUTPUT_BITS-1:0] root // unsigned root \r + );\r +\r + // WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP\r + // LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE\r + // OVERWRITTEN!\r + parameter\r + INPUT_BITS = 16; // number of input bits (any integer)\r + localparam\r + OUTPUT_BITS = INPUT_BITS / 2 + INPUT_BITS % 2; // number of output bits\r + \r + reg [OUTPUT_BITS-1:0] start_gen; // valid data propagation\r + reg [OUTPUT_BITS*INPUT_BITS-1:0] root_gen; // root values\r + reg [OUTPUT_BITS*INPUT_BITS-1:0] radicand_gen; // radicand values\r + wire [OUTPUT_BITS*INPUT_BITS-1:0] mask_gen; // mask values\r +\r + // This is the first stage of the pipeline.\r + always @ (posedge clk or negedge reset_n) begin\r + if (!reset_n) begin\r + start_gen[0] <= 0;\r + radicand_gen[INPUT_BITS-1:0] <= 0;\r + root_gen[INPUT_BITS-1:0] <= 0;\r + end\r + else begin\r + start_gen[0] <= start;\r + if ( mask_gen[INPUT_BITS-1:0] <= radicand ) begin\r + radicand_gen[INPUT_BITS-1:0] <= radicand - mask_gen[INPUT_BITS-1:0];\r + root_gen[INPUT_BITS-1:0] <= mask_gen[INPUT_BITS-1:0];\r + end\r + else begin\r + radicand_gen[INPUT_BITS-1:0] <= radicand;\r + root_gen[INPUT_BITS-1:0] <= 0;\r + end\r + end\r + end\r +\r + // Main generate loop to create the masks and pipeline stages.\r + generate\r + genvar i;\r + // Generate all the mask values. These are built up in the\r + // following fashion:\r + // LAST MASK: 0x00...001 \r + // 0x00...004 Increasing # OUTPUT_BITS\r + // 0x00...010 |\r + // 0x00...040 v\r + // ...\r + // FIRST MASK: 0x10...000 # masks == # OUTPUT_BITS\r + // \r + // Note that the first mask used can either be of the 0x1... or\r + // 0x4... variety. This is purely determined by the number of\r + // computation stages. However, the last mask used will always be\r + // 0x1 and the second to last mask used will always be 0x4.\r + for (i = 0; i < OUTPUT_BITS; i = i + 1) begin: mask_4\r + if (i % 2) // i is odd, this is a 4 mask\r + assign mask_gen[INPUT_BITS*(OUTPUT_BITS-i)-1:INPUT_BITS*(OUTPUT_BITS-i-1)] = 4 << 4 * (i/2);\r + else // i is even, this is a 1 mask\r + assign mask_gen[INPUT_BITS*(OUTPUT_BITS-i)-1:INPUT_BITS*(OUTPUT_BITS-i-1)] = 1 << 4 * (i/2);\r + end\r + // Generate all the pipeline stages to compute the square root of\r + // the input radicand stream. The general approach is to compare\r + // the current values of the root plus the mask to the\r + // radicand. If root/mask sum is greater than the radicand,\r + // subtract the mask and the root from the radicand and store the\r + // radicand for the next stage. Additionally, the root is\r + // increased by the value of the mask and stored for the next\r + // stage. If this test fails, then the radicand and the root\r + // retain their value through to the next stage. The one weird\r + // thing is that the mask indices appear to be incremented by one\r + // additional position. This is not the case, however, because the\r + // first mask is used in the first stage (always block after the\r + // generate statement).\r + for (i = 0; i < OUTPUT_BITS - 1; i = i + 1) begin: pipeline\r + always @ (posedge clk or negedge reset_n) begin : pipeline_stage\r + if (!reset_n) begin\r + start_gen[i+1] <= 0;\r + radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= 0;\r + root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= 0;\r + end\r + else begin\r + start_gen[i+1] <= start_gen[i];\r + if ((root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] + \r + mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)]) <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i]) begin\r +\t radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] - \r + mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] - \r + root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i];\r +\t root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= (root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] >> 1) + \r + mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)];\r + end\r + else begin\r +\t radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i];\r +\t root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] >> 1;\r + end\r + end\r + end\r + end\r + endgenerate\r +\r + // This is the final stage which just implements a rounding\r + // operation. This stage could be tacked on as a combinational logic\r + // stage, but who cares about latency, anyway? This is NOT a true\r + // rounding stage. In order to add convergent rounding, you need to\r + // increase the input bit width by 2 (increase the number of\r + // pipeline stages by 1) and implement rounding in the module that\r + // instantiates this one. \r + always @ (posedge clk or negedge reset_n) begin\r + if (!reset_n) begin\r + data_valid <= 0;\r + root <= 0;\r + end\r + else begin\r + data_valid <= start_gen[OUTPUT_BITS-1];\r + if (root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS] > root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS])\r + root <= root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS] + 1;\r + else\r + root <= root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS];\r + end\r + end\r +\r +endmodule\r +" +"////////////////////////////////////////////////////////////////////////////////\r +// Original Author: Schuyler Eldridge\r +// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)\r +// pipeline_registers.v\r +// Created: 4.4.2012\r +// Modified: 4.4.2012\r +//\r +// Implements a series of pipeline registers specified by the input\r +// parameters BIT_WIDTH and NUMBER_OF_STAGES. BIT_WIDTH determines the\r +// size of the signal passed through each of the pipeline\r +// registers. NUMBER_OF_STAGES is the number of pipeline registers\r +// generated. This accepts values of 0 (yes, it just passes data from\r +// input to output...) up to however many stages specified.\r +// Copyright (C) 2012 Schuyler Eldridge, Boston University\r +//\r +// This program is free software: you can redistribute it and/or modify\r +// it under the terms of the GNU General Public License as published by\r +// the Free Software Foundation, either version 3 of the License.\r +//\r +// This program is distributed in the hope that it will be useful,\r +// but WITHOUT ANY WARRANTY; without even the implied warranty of\r +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r +// GNU General Public License for more details.\r +//\r +// You should have received a copy of the GNU General Public License\r +// along with this program. If not, see .\r +////////////////////////////////////////////////////////////////////////////////\r +`timescale 1ns / 1ps\r +module pipeline_registers\r + (\r + input clk,\r + input reset_n,\r + input [BIT_WIDTH-1:0] pipe_in,\r + output reg [BIT_WIDTH-1:0] pipe_out\r + );\r +\r + // WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP\r + // LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE\r + // OVERWRITTEN!\r + parameter \r + BIT_WIDTH = 10,\r + NUMBER_OF_STAGES = 5;\r +\r + // Main generate function for conditional hardware instantiation\r + generate\r + genvar i;\r + // Pass-through case for the odd event that no pipeline stages are\r + // specified.\r + if (NUMBER_OF_STAGES == 0) begin\r + always @ *\r + pipe_out = pipe_in;\r + end\r + // Single flop case for a single stage pipeline\r + else if (NUMBER_OF_STAGES == 1) begin\r + always @ (posedge clk or negedge reset_n)\r + pipe_out <= (!reset_n) ? 0 : pipe_in;\r + end\r + // Case for 2 or more pipeline stages\r + else begin\r + // Create the necessary regs\r + reg [BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:0] pipe_gen;\r + // Create logic for the initial and final pipeline registers\r + always @ (posedge clk or negedge reset_n) begin\r + if (!reset_n) begin\r + pipe_gen[BIT_WIDTH-1:0] <= 0;\r + pipe_out <= 0;\r + end\r + else begin\r + pipe_gen[BIT_WIDTH-1:0] <= pipe_in;\r + pipe_out <= pipe_gen[BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:BIT_WIDTH*(NUMBER_OF_STAGES-2)];\r + end\r + end\r + // Create the intermediate pipeline registers if there are 3 or\r + // more pipeline stages\r + for (i = 1; i < NUMBER_OF_STAGES-1; i = i + 1) begin : pipeline\r + always @ (posedge clk or negedge reset_n)\r + pipe_gen[BIT_WIDTH*(i+1)-1:BIT_WIDTH*i] <= (!reset_n) ? 0 : pipe_gen[BIT_WIDTH*i-1:BIT_WIDTH*(i-1)];\r + end\r + end\r + endgenerate\r + \r +endmodule\r +" +"////////////////////////////////////////////////////////////////////////////////\r +// Original Author: Schuyler Eldridge\r +// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)\r +// t_sqrt_pipelined.v\r +// Created: 4.2.2012\r +// Modified: 4.5.2012\r +//\r +// Testbench for generic sqrt operation\r +// \r +// Copyright (C) 2012 Schuyler Eldridge, Boston University\r +//\r +// This program is free software: you can redistribute it and/or modify\r +// it under the terms of the GNU General Public License as published by\r +// the Free Software Foundation, either version 3 of the License.\r +//\r +// This program is distributed in the hope that it will be useful,\r +// but WITHOUT ANY WARRANTY; without even the implied warranty of\r +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r +// GNU General Public License for more details.\r +//\r +// You should have received a copy of the GNU General Public License\r +// along with this program. If not, see .\r +////////////////////////////////////////////////////////////////////////////////\r +`timescale 1ns / 1ps\r +module t_sqrt_pipelined();\r +\r + parameter \r + INPUT_BITS = 4;\r + localparam\r + OUTPUT_BITS = INPUT_BITS / 2 + INPUT_BITS % 2;\r + \r + reg [INPUT_BITS-1:0] radicand;\r + reg clk, start, reset_n;\r +\r + wire [OUTPUT_BITS-1:0] root;\r + wire data_valid;\r +// wire [7:0] root_good;\r +\r + sqrt_pipelined \r + #(\r + .INPUT_BITS(INPUT_BITS)\r + )\r + sqrt_pipelined \r + (\r + .clk(clk),\r + .reset_n(reset_n),\r + .start(start),\r + .radicand(radicand), \r + .data_valid(data_valid),\r + .root(root)\r + );\r +\r + initial begin\r + radicand = 16'bx; clk = 1'bx; start = 1'bx; reset_n = 1'bx;;\r + #10 reset_n = 0; clk = 0;\r + #50 reset_n = 1; radicand = 0;\r +// #40 radicand = 81; start = 1;\r +// #10 radicand = 16'bx; start = 0;\r + #10000 $finish;\r + end\r +\r + always\r + #5 clk = ~clk;\r +\r + always begin\r + #10 radicand = radicand + 1; start = 1;\r + #10 start = 0;\r + end\r + \r +\r +// always begin\r +// #80 start = 1;\r +// #10 start = 0;\r +// end\r +\r +endmodule\r +\r +" +"/* + * VGA top level file + * Copyright (C) 2010 Zeus Gomez Marmolejo + * + * This file is part of the Zet processor. This processor is free + * hardware; you can redistribute it and/or modify it under the terms of + * the GNU General Public License as published by the Free Software + * Foundation; either version 3, or (at your option) any later version. + * + * Zet is distrubuted in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + * License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Zet; see the file COPYING. If not, see + * . + */ + +module vga ( + // Wishbone signals + input wb_clk_i, // 25 Mhz VDU clock + input wb_rst_i, + input [15:0] wb_dat_i, + output [15:0] wb_dat_o, + input [16:1] wb_adr_i, + input wb_we_i, + input wb_tga_i, + input [ 1:0] wb_sel_i, + input wb_stb_i, + input wb_cyc_i, + output wb_ack_o, + + // VGA pad signals + output [ 3:0] vga_red_o, + output [ 3:0] vga_green_o, + output [ 3:0] vga_blue_o, + output horiz_sync, + output vert_sync, + + // CSR SRAM master interface + output [17:1] csrm_adr_o, + output [ 1:0] csrm_sel_o, + output csrm_we_o, + output [15:0] csrm_dat_o, + input [15:0] csrm_dat_i + ); + + + // Registers and nets + // + // csr address + reg [17:1] csr_adr_i; + reg csr_stb_i; + + // Config wires + wire [15:0] conf_wb_dat_o; + wire conf_wb_ack_o; + + // Mem wires + wire [15:0] mem_wb_dat_o; + wire mem_wb_ack_o; + + // LCD wires + wire [17:1] csr_adr_o; + wire [15:0] csr_dat_i; + wire csr_stb_o; + wire v_retrace; + wire vh_retrace; + wire w_vert_sync; + + // VGA configuration registers + wire shift_reg1; + wire graphics_alpha; + wire memory_mapping1; + wire [ 1:0] write_mode; + wire [ 1:0] raster_op; + wire read_mode; + wire [ 7:0] bitmask; + wire [ 3:0] set_reset; + wire [ 3:0] enable_set_reset; + wire [ 3:0] map_mask; + wire x_dotclockdiv2; + wire chain_four; + wire [ 1:0] read_map_select; + wire [ 3:0] color_compare; + wire [ 3:0] color_dont_care; + + // Wishbone master to SRAM + wire [17:1] wbm_adr_o; + wire [ 1:0] wbm_sel_o; + wire wbm_we_o; + wire [15:0] wbm_dat_o; + wire [15:0] wbm_dat_i; + wire wbm_stb_o; + wire wbm_ack_i; + + wire stb; + + // CRT wires + wire [ 5:0] cur_start; + wire [ 5:0] cur_end; + wire [15:0] start_addr; + wire [ 4:0] vcursor; + wire [ 6:0] hcursor; + wire [ 6:0] horiz_total; + wire [ 6:0] end_horiz; + wire [ 6:0] st_hor_retr; + wire [ 4:0] end_hor_retr; + wire [ 9:0] vert_total; + wire [ 9:0] end_vert; + wire [ 9:0] st_ver_retr; + wire [ 3:0] end_ver_retr; + + // attribute_ctrl wires + wire [3:0] pal_addr; + wire pal_we; + wire [7:0] pal_read; + wire [7:0] pal_write; + + // dac_regs wires + wire dac_we; + wire [1:0] dac_read_data_cycle; + wire [7:0] dac_read_data_register; + wire [3:0] dac_read_data; + wire [1:0] dac_write_data_cycle; + wire [7:0] dac_write_data_register; + wire [3:0] dac_write_data; + + // Module instances + // + vga_config_iface config_iface ( + .wb_clk_i (wb_clk_i), + .wb_rst_i (wb_rst_i), + .wb_dat_i (wb_dat_i), + .wb_dat_o (conf_wb_dat_o), + .wb_adr_i (wb_adr_i[4:1]), + .wb_we_i (wb_we_i), + .wb_sel_i (wb_sel_i), + .wb_stb_i (stb & wb_tga_i), + .wb_ack_o (conf_wb_ack_o), + + .shift_reg1 (shift_reg1), + .graphics_alpha (graphics_alpha), + .memory_mapping1 (memory_mapping1), + .write_mode (write_mode), + .raster_op (raster_op), + .read_mode (read_mode), + .bitmask (bitmask), + .set_reset (set_reset), + .enable_set_reset (enable_set_reset), + .map_mask (map_mask), + .x_dotclockdiv2 (x_dotclockdiv2), + .chain_four (chain_four), + .read_map_select (read_map_select), + .color_compare (color_compare), + .color_dont_care (color_dont_care), + + .pal_addr (pal_addr), + .pal_we (pal_we), + .pal_read (pal_read), + .pal_write (pal_write), + + .dac_we (dac_we), + .dac_read_data_cycle (dac_read_data_cycle), + .dac_read_data_register (dac_read_data_register), + .dac_read_data (dac_read_data), + .dac_write_data_cycle (dac_write_data_cycle), + .dac_write_data_register (dac_write_data_register), + .dac_write_data (dac_write_data), + + .cur_start (cur_start), + .cur_end (cur_end), + .start_addr (start_addr), + .vcursor (vcursor), + .hcursor (hcursor), + + .horiz_total (horiz_total), + .end_horiz (end_horiz), + .st_hor_retr (st_hor_retr), + .end_hor_retr (end_hor_retr), + .vert_total (vert_total), + .end_vert (end_vert), + .st_ver_retr (st_ver_retr), + .end_ver_retr (end_ver_retr), + + .v_retrace (v_retrace), + .vh_retrace (vh_retrace) + ); + + vga_lcd lcd ( + .clk (wb_clk_i), + .rst (wb_rst_i), + + .shift_reg1 (shift_reg1), + .graphics_alpha (graphics_alpha), + + .pal_addr (pal_addr), + .pal_we (pal_we), + .pal_read (pal_read), + .pal_write (pal_write), + + .dac_we (dac_we), + .dac_read_data_cycle (dac_read_data_cycle), + .dac_read_data_register (dac_read_data_register), + .dac_read_data (dac_read_data), + .dac_write_data_cycle (dac_write_data_cycle), + .dac_write_data_register (dac_write_data_register), + .dac_write_data (dac_write_data), + + .csr_adr_o (csr_adr_o), + .csr_dat_i (csr_dat_i), + .csr_stb_o (csr_stb_o), + + .vga_red_o (vga_red_o), + .vga_green_o (vga_green_o), + .vga_blue_o (vga_blue_o), + .horiz_sync (horiz_sync), + .vert_sync (w_vert_sync), + + .cur_start (cur_start), + .cur_end (cur_end), + .vcursor (vcursor), + .hcursor (hcursor), + + .horiz_total (horiz_total), + .end_horiz (end_horiz), + .st_hor_retr (st_hor_retr), + .end_hor_retr (end_hor_retr), + .vert_total (vert_total), + .end_vert (end_vert), + .st_ver_retr (st_ver_retr), + .end_ver_retr (end_ver_retr), + + .x_dotclockdiv2 (x_dotclockdiv2), + + .v_retrace (v_retrace), + .vh_retrace (vh_retrace) + ); + + vga_cpu_mem_iface cpu_mem_iface ( + .wb_clk_i (wb_clk_i), + .wb_rst_i (wb_rst_i), + + .wbs_adr_i (wb_adr_i), + .wbs_sel_i (wb_sel_i), + .wbs_we_i (wb_we_i), + .wbs_dat_i (wb_dat_i), + .wbs_dat_o (mem_wb_dat_o), + .wbs_stb_i (stb & !wb_tga_i), + .wbs_ack_o (mem_wb_ack_o), + + .wbm_adr_o (wbm_adr_o), + .wbm_sel_o (wbm_sel_o), + .wbm_we_o (wbm_we_o), + .wbm_dat_o (wbm_dat_o), + .wbm_dat_i (wbm_dat_i), + .wbm_stb_o (wbm_stb_o), + .wbm_ack_i (wbm_ack_i), + + .chain_four (chain_four), + .memory_mapping1 (memory_mapping1), + .write_mode (write_mode), + .raster_op (raster_op), + .read_mode (read_mode), + .bitmask (bitmask), + .set_reset (set_reset), + .enable_set_reset (enable_set_reset), + .map_mask (map_mask), + .read_map_select (read_map_select), + .color_compare (color_compare), + .color_dont_care (color_dont_care) + ); + + vga_mem_arbitrer mem_arbitrer ( + .clk_i (wb_clk_i), + .rst_i (wb_rst_i), + + .wb_adr_i (wbm_adr_o), + .wb_sel_i (wbm_sel_o), + .wb_we_i (wbm_we_o), + .wb_dat_i (wbm_dat_o), + .wb_dat_o (wbm_dat_i), + .wb_stb_i (wbm_stb_o), + .wb_ack_o (wbm_ack_i), + + .csr_adr_i (csr_adr_i), + .csr_dat_o (csr_dat_i), + .csr_stb_i (csr_stb_i), + + .csrm_adr_o (csrm_adr_o), + .csrm_sel_o (csrm_sel_o), + .csrm_we_o (csrm_we_o), + .csrm_dat_o (csrm_dat_o), + .csrm_dat_i (csrm_dat_i) + ); + + // Continous assignments + assign wb_dat_o = wb_tga_i ? conf_wb_dat_o : mem_wb_dat_o; + assign wb_ack_o = wb_tga_i ? conf_wb_ack_o : mem_wb_ack_o; + assign stb = wb_stb_i & wb_cyc_i; + assign vert_sync = ~graphics_alpha ^ w_vert_sync; + + // Behaviour + // csr_adr_i + always @(posedge wb_clk_i) + csr_adr_i <= wb_rst_i ? 17'h0 : csr_adr_o + start_addr[15:1]; + + // csr_stb_i + always @(posedge wb_clk_i) + csr_stb_i <= wb_rst_i ? 1'b0 : csr_stb_o; + +endmodule +" +"`timescale 1ns / 1ps +// Copyright (C) 2008 Schuyler Eldridge, Boston University +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +module mux(opA,opB,sum,dsp_sel,out); +\tinput [3:0] opA,opB; +\tinput [4:0] sum; +\tinput [1:0] dsp_sel; +\toutput [3:0] out; +\t +\treg cout; +\t +\talways @ (sum) +\t\tbegin +\t\t\tif (sum[4] == 1) +\t\t\t\tcout <= 4'b0001; +\t\t\telse +\t\t\t\tcout <= 4'b0000; +\t\tend +\t +\treg out; +\t +\talways @(dsp_sel,sum,cout,opB,opA) +\t\tbegin +\t\t\tif (dsp_sel == 2'b00) +\t\t\t\tout <= sum[3:0]; +\t\t\telse if (dsp_sel == 2'b01) +\t\t\t\tout <= cout; +\t\t\telse if (dsp_sel == 2'b10) +\t\t\t\tout <= opB; +\t\t\telse if (dsp_sel == 2'b11) +\t\t\t\tout <= opA; +\t\tend + +endmodule +" +"////////////////////////////////////////////////////////////////////////////////\r +// Original Author: Schuyler Eldridge\r +// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)\r +// sign_extender.v\r +// Created: 5.16.2012\r +// Modified: 5.16.2012\r +//\r +// Generic sign extension module\r +//\r +// Copyright (C) 2012 Schuyler Eldridge, Boston University\r +//\r +// This program is free software: you can redistribute it and/or modify\r +// it under the terms of the GNU General Public License as published by\r +// the Free Software Foundation, either version 3 of the License.\r +//\r +// This program is distributed in the hope that it will be useful,\r +// but WITHOUT ANY WARRANTY; without even the implied warranty of\r +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r +// GNU General Public License for more details.\r +//\r +// You should have received a copy of the GNU General Public License\r +// along with this program. If not, see .\r +////////////////////////////////////////////////////////////////////////////////\r +`timescale 1ns/1ps\r +module sign_extender\r + #(\r + parameter\r + INPUT_WIDTH = 8,\r + OUTPUT_WIDTH = 16\r + )\r + (\r + input [INPUT_WIDTH-1:0] original,\r + output reg [OUTPUT_WIDTH-1:0] sign_extended_original\r + );\r +\r + wire [OUTPUT_WIDTH-INPUT_WIDTH-1:0] sign_extend;\r +\r + generate\r + genvar i;\r + for (i = 0; i < OUTPUT_WIDTH-INPUT_WIDTH; i = i + 1) begin : gen_sign_extend\r + assign sign_extend[i] = (original[INPUT_WIDTH-1]) ? 1'b1 : 1'b0;\r + end\r + endgenerate\r +\r + always @ * begin\r + sign_extended_original = {sign_extend,original};\r + end\r +\r +endmodule\r +" +"Require Export Sorted. +Require Export Mergesort. +" +"////////////////////////////////////////////////////////////////////////////////\r +// Original Author: Schuyler Eldridge\r +// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)\r +// button_debounce.v\r +// Created: 10/10/2009\r +// Modified: 3/20/2012\r +//\r +// Counter based debounce circuit originally written for EC551 (back\r +// in the day) and then modified (i.e. chagned entirely) into 3 always\r +// block format. This debouncer generates a signal that goes high for\r +// 1 clock cycle after the clock sees an asserted value on the button\r +// line. This action is then disabled until the counter hits a\r +// specified count value that is determined by the clock frequency and\r +// desired debounce frequency. An alternative implementation would not\r +// use a counter, but would use the shift register approach, looking\r +// for repeated matches (say 5) on the button line.\r +// \r +// Copyright (C) 2012 Schuyler Eldridge, Boston University\r +//\r +// This program is free software: you can redistribute it and/or modify\r +// it under the terms of the GNU General Public License as published by\r +// the Free Software Foundation, either version 3 of the License.\r +//\r +// This program is distributed in the hope that it will be useful,\r +// but WITHOUT ANY WARRANTY; without even the implied warranty of\r +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r +// GNU General Public License for more details.\r +//\r +// You should have received a copy of the GNU General Public License\r +// along with this program. If not, see .\r +////////////////////////////////////////////////////////////////////////////////\r +`timescale 1ns / 1ps\r +module button_debounce\r + (\r + input clk, // clock\r + input reset_n, // asynchronous reset \r + input button, // bouncy button\r + output reg debounce // debounced 1-cycle signal\r + );\r + \r + parameter\r + CLK_FREQUENCY = 66000000,\r + DEBOUNCE_HZ = 2;\r + // These parameters are specified such that you can choose any power\r + // of 2 frequency for a debouncer between 1 Hz and\r + // CLK_FREQUENCY. Note, that this will throw errors if you choose a\r + // non power of 2 frequency (i.e. count_value evaluates to some\r + // number / 3 which isn't interpreted as a logical right shift). I'm\r + // assuming this will not work for DEBOUNCE_HZ values less than 1,\r + // however, I'm uncertain of the value of a debouncer for fractional\r + // hertz button presses.\r + localparam\r + COUNT_VALUE = CLK_FREQUENCY / DEBOUNCE_HZ,\r + WAIT = 0,\r + FIRE = 1,\r + COUNT = 2;\r +\r + reg [1:0] state, next_state;\r + reg [25:0] count;\r + \r + always @ (posedge clk or negedge reset_n)\r + state <= (!reset_n) ? WAIT : next_state;\r +\r + always @ (posedge clk or negedge reset_n) begin\r + if (!reset_n) begin\r + debounce <= 0;\r + count <= 0;\r + end\r + else begin\r + debounce <= 0;\r + count <= 0;\r + case (state)\r + WAIT: begin\r + end\r + FIRE: begin\r + debounce <= 1;\r + end\r + COUNT: begin\r + count <= count + 1;\r + end\r + endcase \r + end\r + end\r +\r + always @ * begin\r + case (state)\r + WAIT: next_state = (button) ? FIRE : state;\r + FIRE: next_state = COUNT;\r + COUNT: next_state = (count > COUNT_VALUE - 1) ? WAIT : state;\r + default: next_state = WAIT;\r + endcase\r + end\r +\r +endmodule\r +" +"/* + * PS2 Mouse Interface + * Copyright (C) 2010 Donna Polehn + * + * This file is part of the Zet processor. This processor is free + * hardware; you can redistribute it and/or modify it under the terms of + * the GNU General Public License as published by the Free Software + * Foundation; either version 3, or (at your option) any later version. + * + * Zet is distrubuted in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + * License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Zet; see the file COPYING. If not, see + * . + */ + +module ps2_mouse ( + input clk, // Clock Input + input reset, // Reset Input + inout ps2_clk, // PS2 Clock, Bidirectional + inout ps2_dat, // PS2 Data, Bidirectional + + input [7:0] the_command, // Command to send to mouse + input send_command, // Signal to send + output command_was_sent, // Signal command finished sending + output error_communication_timed_out, + + output [7:0] received_data, // Received data + output received_data_en, // If 1 - new data has been received + output start_receiving_data, + output wait_for_incoming_data + ); + + // -------------------------------------------------------------------- + // Internal wires and registers Declarations + // -------------------------------------------------------------------- + wire ps2_clk_posedge; // Internal Wires + wire ps2_clk_negedge; + + reg [7:0] idle_counter; // Internal Registers + reg ps2_clk_reg; + reg ps2_data_reg; + reg last_ps2_clk; + + reg [2:0] ns_ps2_transceiver; // State Machine Registers + reg [2:0] s_ps2_transceiver; + + // -------------------------------------------------------------------- + // Constant Declarations + // -------------------------------------------------------------------- + localparam PS2_STATE_0_IDLE = 3'h0, // states + PS2_STATE_1_DATA_IN = 3'h1, + PS2_STATE_2_COMMAND_OUT = 3'h2, + PS2_STATE_3_END_TRANSFER = 3'h3, + PS2_STATE_4_END_DELAYED = 3'h4; + + // -------------------------------------------------------------------- + // Finite State Machine(s) + // -------------------------------------------------------------------- + always @(posedge clk) begin + if(reset == 1'b1) s_ps2_transceiver <= PS2_STATE_0_IDLE; + else s_ps2_transceiver <= ns_ps2_transceiver; + end + + always @(*) begin + ns_ps2_transceiver = PS2_STATE_0_IDLE; // Defaults + + case (s_ps2_transceiver) + PS2_STATE_0_IDLE: + begin + if((idle_counter == 8'hFF) && (send_command == 1'b1)) + ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT; + else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1)) + ns_ps2_transceiver = PS2_STATE_1_DATA_IN; + else ns_ps2_transceiver = PS2_STATE_0_IDLE; + end + PS2_STATE_1_DATA_IN: + begin + // if((received_data_en == 1'b1) && (ps2_clk_posedge == 1'b1)) + if((received_data_en == 1'b1)) ns_ps2_transceiver = PS2_STATE_0_IDLE; + else ns_ps2_transceiver = PS2_STATE_1_DATA_IN; + end + PS2_STATE_2_COMMAND_OUT: + begin + if((command_was_sent == 1'b1) || (error_communication_timed_out == 1'b1)) + ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER; + else ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT; + end + PS2_STATE_3_END_TRANSFER: + begin + if(send_command == 1'b0) ns_ps2_transceiver = PS2_STATE_0_IDLE; + else if((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1)) + ns_ps2_transceiver = PS2_STATE_4_END_DELAYED; + else ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER; + end + PS2_STATE_4_END_DELAYED: + begin + if(received_data_en == 1'b1) begin + if(send_command == 1'b0) ns_ps2_transceiver = PS2_STATE_0_IDLE; + else ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER; + end + else ns_ps2_transceiver = PS2_STATE_4_END_DELAYED; + end + + default: + ns_ps2_transceiver = PS2_STATE_0_IDLE; + endcase + end + + // -------------------------------------------------------------------- + // Sequential logic + // -------------------------------------------------------------------- + always @(posedge clk) begin + if(reset == 1'b1) begin + last_ps2_clk <= 1'b1; + ps2_clk_reg <= 1'b1; + ps2_data_reg <= 1'b1; + end + else begin + last_ps2_clk <= ps2_clk_reg; + ps2_clk_reg <= ps2_clk; + ps2_data_reg <= ps2_dat; + end + end + + always @(posedge clk) begin + if(reset == 1'b1) idle_counter <= 6'h00; + else if((s_ps2_transceiver == PS2_STATE_0_IDLE) && (idle_counter != 8'hFF)) + idle_counter <= idle_counter + 6'h01; + else if (s_ps2_transceiver != PS2_STATE_0_IDLE) + idle_counter <= 6'h00; + end + + // -------------------------------------------------------------------- + // Combinational logic + // -------------------------------------------------------------------- + assign ps2_clk_posedge = ((ps2_clk_reg == 1'b1) && (last_ps2_clk == 1'b0)) ? 1'b1 : 1'b0; + assign ps2_clk_negedge = ((ps2_clk_reg == 1'b0) && (last_ps2_clk == 1'b1)) ? 1'b1 : 1'b0; + + assign start_receiving_data = (s_ps2_transceiver == PS2_STATE_1_DATA_IN); + assign wait_for_incoming_data = (s_ps2_transceiver == PS2_STATE_3_END_TRANSFER); + + // -------------------------------------------------------------------- + // Internal Modules + // -------------------------------------------------------------------- + ps2_mouse_cmdout mouse_cmdout ( + .clk (clk), // Inputs + .reset (reset), + .the_command (the_command), + .send_command (send_command), + .ps2_clk_posedge (ps2_clk_posedge), + .ps2_clk_negedge (ps2_clk_negedge), + .ps2_clk (ps2_clk), // Bidirectionals + .ps2_dat (ps2_dat), + .command_was_sent (command_was_sent), // Outputs + .error_communication_timed_out (error_communication_timed_out) + ); + + ps2_mouse_datain mouse_datain ( + .clk (clk), // Inputs + .reset (reset), + .wait_for_incoming_data (wait_for_incoming_data), + .start_receiving_data (start_receiving_data), + .ps2_clk_posedge (ps2_clk_posedge), + .ps2_clk_negedge (ps2_clk_negedge), + .ps2_data (ps2_data_reg), + .received_data (received_data), // Outputs + .received_data_en (received_data_en) + ); + +endmodule + +" +"`timescale 1ns / 1ps +// Copyright (C) 2008 Schuyler Eldridge, Boston University +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +module control(clk,en,dsp_sel,an); + input clk, en; + output [1:0]dsp_sel; + output [3:0]an; + wire a,b,c,d,e,f,g,h,i,j,k,l; + + assign an[3] = a; + assign an[2] = b; + assign an[1] = c; + assign an[0] = d; + + assign dsp_sel[1] = e; + + assign dsp_sel[0] = i; + + + FDRSE #( + .INIT(1'b0) // Initial value of register (1'b0 or 1'b1) + ) DFF3( + .Q(a), // Data output + .C(clk), // Clock input + .CE(en), // Clock enable input + .D(d), // Data input + .R(1'b0), // Synchronous reset input + .S(1'b0) // Synchronous set input + ); + FDRSE #( + .INIT(1'b1) // Initial value of register (1'b0 or 1'b1) + ) DFF2( + .Q(b), // Data output + .C(clk), // Clock input + .CE(en), // Clock enable input + .D(a), // Data input + .R(1'b0), // Synchronous reset input + .S(1'b0) // Synchronous set input + ); + FDRSE #( + .INIT(1'b1) // Initial value of register (1'b0 or 1'b1) + ) DFF1( + .Q(c), // Data output + .C(clk), // Clock input + .CE(en), // Clock enable input + .D(b), // Data input + .R(1'b0), // Synchronous reset input + .S(1'b0) // Synchronous set input + ); + FDRSE #( + .INIT(1'b1) // Initial value of register (1'b0 or 1'b1) + ) DFF0( + .Q(d), // Data output + .C(clk), // Clock input + .CE(en), // Clock enable input + .D(c), // Data input + .R(1'b0), // Synchronous reset input + .S(1'b0) // Synchronous set input + ); + + + FDRSE #( + .INIT(1'b1) // Initial value of register (1'b0 or 1'b1) + ) DFF7( + .Q(e), // Data output + .C(clk), // Clock input + .CE(en), // Clock enable input + .D(h), // Data input + .R(1'b0), // Synchronous reset input + .S(1'b0) // Synchronous set input + ); + FDRSE #( + .INIT(1'b1) // Initial value of register (1'b0 or 1'b1) + ) DFF6( + .Q(f), // Data output + .C(clk), // Clock input + .CE(en), // Clock enable input + .D(e), // Data input + .R(1'b0), // Synchronous reset input + .S(1'b0) // Synchronous set input + ); + FDRSE #( + .INIT(1'b0) // Initial value of register (1'b0 or 1'b1) + ) DFF5( + .Q(g), // Data output + .C(clk), // Clock input + .CE(en), // Clock enable input + .D(f), // Data input + .R(1'b0), // Synchronous reset input + .S(1'b0) // Synchronous set input + ); + FDRSE #( + .INIT(1'b0) // Initial value of register (1'b0 or 1'b1) + ) DFF4( + .Q(h), // Data output + .C(clk), // Clock input + .CE(en), // Clock enable input + .D(g), // Data input + .R(1'b0), // Synchronous reset input + .S(1'b0) // Synchronous set input + ); + + + FDRSE #( + .INIT(1'b1) // Initial value of register (1'b0 or 1'b1) + ) DFF11( + .Q(i), // Data output + .C(clk), // Clock input + .CE(en), // Clock enable input + .D(l), // Data input + .R(1'b0), // Synchronous reset input + .S(1'b0) // Synchronous set input + ); + FDRSE #( + .INIT(1'b0) // Initial value of register (1'b0 or 1'b1) + ) DFF10( + .Q(j), // Data output + .C(clk), // Clock input + .CE(en), // Clock enable input + .D(i), // Data input + .R(1'b0), // Synchronous reset input + .S(1'b0) // Synchronous set input + ); + FDRSE #( + .INIT(1'b1) // Initial value of register (1'b0 or 1'b1) + ) DFF9( + .Q(k), // Data output + .C(clk), // Clock input + .CE(en), // Clock enable input + .D(j), // Data input + .R(1'b0), // Synchronous reset input + .S(1'b0) // Synchronous set input + ); + FDRSE #( + .INIT(1'b0) // Initial value of register (1'b0 or 1'b1) + ) DFF8( + .Q(l), // Data output + .C(clk), // Clock input + .CE(en), // Clock enable input + .D(k), // Data input + .R(1'b0), // Synchronous reset input + .S(1'b0) // Synchronous set input + ); +endmodule +" +"// file: clk_divider_tb.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, ""Critical +// Applications""). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// + +//---------------------------------------------------------------------------- +// Clocking wizard demonstration testbench +//---------------------------------------------------------------------------- +// This demonstration testbench instantiates the example design for the +// clocking wizard. Input clocks are toggled, which cause the clocking +// network to lock and the counters to increment. +//---------------------------------------------------------------------------- + +`timescale 1ps/1ps + +`define wait_lock @(posedge LOCKED) + +module clk_divider_tb (); + + // Clock to Q delay of 100ps + localparam TCQ = 100; + + + // timescale is 1ps/1ps + localparam ONE_NS = 1000; + localparam PHASE_ERR_MARGIN = 100; // 100ps + // how many cycles to run + localparam COUNT_PHASE = 1024; + // we\'ll be using the period in many locations + localparam time PER1 = 10.0*ONE_NS; + localparam time PER1_1 = PER1/2; + localparam time PER1_2 = PER1 - PER1/2; + + // Declare the input clock signals + reg CLK_IN1 = 1; + + // The high bit of the sampling counter + wire COUNT; + // Status and control signals + reg RESET = 0; + wire LOCKED; + reg COUNTER_RESET = 0; +wire [1:1] CLK_OUT; +//Freq Check using the M & D values setting and actual Frequency generated + + + // Input clock generation + //------------------------------------ + always begin + CLK_IN1 = #PER1_1 ~CLK_IN1; + CLK_IN1 = #PER1_2 ~CLK_IN1; + end + + // Test sequence + reg [15*8-1:0] test_phase = """"; + initial begin + // Set up any display statements using time to be readable + $timeformat(-12, 2, ""ps"", 10); + COUNTER_RESET = 0; + test_phase = ""reset""; + RESET = 1; + #(PER1*6); + RESET = 0; + test_phase = ""wait lock""; + `wait_lock; + #(PER1*6); + COUNTER_RESET = 1; + #(PER1*20) + COUNTER_RESET = 0; + + test_phase = ""counting""; + #(PER1*COUNT_PHASE); + + $display(""SIMULATION PASSED""); + $display(""SYSTEM_CLOCK_COUNTER : %0d\ +"",$time/PER1); + $finish; + end + + // Instantiation of the example design containing the clock + // network and sampling counters + //--------------------------------------------------------- + clk_divider_exdes + #( + .TCQ (TCQ) + ) dut + (// Clock in ports + .CLK_IN1 (CLK_IN1), + // Reset for logic in example design + .COUNTER_RESET (COUNTER_RESET), + .CLK_OUT (CLK_OUT), + // High bits of the counters + .COUNT (COUNT), + // Status and control signals + .RESET (RESET), + .LOCKED (LOCKED)); + +// Freq Check + +endmodule +" +"// file: clk_divider_tb.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, ""Critical +// Applications""). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// + +//---------------------------------------------------------------------------- +// Clocking wizard demonstration testbench +//---------------------------------------------------------------------------- +// This demonstration testbench instantiates the example design for the +// clocking wizard. Input clocks are toggled, which cause the clocking +// network to lock and the counters to increment. +//---------------------------------------------------------------------------- + +`timescale 1ps/1ps + +`define wait_lock @(posedge LOCKED) + +module clk_divider_tb (); + + // Clock to Q delay of 100ps + localparam TCQ = 100; + + + // timescale is 1ps/1ps + localparam ONE_NS = 1000; + localparam PHASE_ERR_MARGIN = 100; // 100ps + // how many cycles to run + localparam COUNT_PHASE = 1024; + // we\'ll be using the period in many locations + localparam time PER1 = 10.0*ONE_NS; + localparam time PER1_1 = PER1/2; + localparam time PER1_2 = PER1 - PER1/2; + + // Declare the input clock signals + reg CLK_IN1 = 1; + + // The high bit of the sampling counter + wire COUNT; + // Status and control signals + reg RESET = 0; + wire LOCKED; + reg COUNTER_RESET = 0; +wire [1:1] CLK_OUT; +//Freq Check using the M & D values setting and actual Frequency generated + + reg [13:0] timeout_counter = 14\'b00000000000000; + + // Input clock generation + //------------------------------------ + always begin + CLK_IN1 = #PER1_1 ~CLK_IN1; + CLK_IN1 = #PER1_2 ~CLK_IN1; + end + + // Test sequence + reg [15*8-1:0] test_phase = """"; + initial begin + // Set up any display statements using time to be readable + $timeformat(-12, 2, ""ps"", 10); + $display (""Timing checks are not valid""); + COUNTER_RESET = 0; + test_phase = ""reset""; + RESET = 1; + #(PER1*6); + RESET = 0; + test_phase = ""wait lock""; + `wait_lock; + #(PER1*6); + COUNTER_RESET = 1; + #(PER1*19.5) + COUNTER_RESET = 0; + #(PER1*1) + $display (""Timing checks are valid""); + test_phase = ""counting""; + #(PER1*COUNT_PHASE); + + $display(""SIMULATION PASSED""); + $display(""SYSTEM_CLOCK_COUNTER : %0d\ +"",$time/PER1); + $finish; + end + + + always@(posedge CLK_IN1) begin + timeout_counter <= timeout_counter + 1\'b1; + if (timeout_counter == 14\'b10000000000000) begin + if (LOCKED != 1\'b1) begin + $display(""ERROR : NO LOCK signal""); + $display(""SYSTEM_CLOCK_COUNTER : %0d\ +"",$time/PER1); + $finish; + end + end + end + + // Instantiation of the example design containing the clock + // network and sampling counters + //--------------------------------------------------------- + clk_divider_exdes + dut + (// Clock in ports + .CLK_IN1 (CLK_IN1), + // Reset for logic in example design + .COUNTER_RESET (COUNTER_RESET), + .CLK_OUT (CLK_OUT), + // High bits of the counters + .COUNT (COUNT), + // Status and control signals + .RESET (RESET), + .LOCKED (LOCKED)); + + +// Freq Check + +endmodule +" +"// file: clk_divider.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, ""Critical +// Applications""). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// ""Output Output Phase Duty Pk-to-Pk Phase"" +// ""Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"" +//---------------------------------------------------------------------------- +// CLK_OUT1____50.000______0.000______50.0______300.000____150.000 +// +//---------------------------------------------------------------------------- +// ""Input Clock Freq (MHz) Input Jitter (UI)"" +//---------------------------------------------------------------------------- +// __primary_________100.000____________0.010 + +`timescale 1ps/1ps + +(* CORE_GENERATION_INFO = ""clk_divider,clk_wiz_v3_6,{component_name=clk_divider,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}"" *) +module clk_divider + (// Clock in ports + input CLK_IN1, + // Clock out ports + output CLK_OUT1, + // Status and control signals + input RESET, + output LOCKED + ); + + // Input buffering + //------------------------------------ + IBUFG clkin1_buf + (.O (clkin1), + .I (CLK_IN1)); + + + // Clocking primitive + //------------------------------------ + + // Instantiation of the DCM primitive + // * Unused inputs are tied off + // * Unused outputs are labeled unused + wire psdone_unused; + wire locked_int; + wire [7:0] status_int; + wire clkfb; + wire clk0; + wire clkdv; + + DCM_SP + #(.CLKDV_DIVIDE (2.000), + .CLKFX_DIVIDE (1), + .CLKFX_MULTIPLY (4), + .CLKIN_DIVIDE_BY_2 (""FALSE""), + .CLKIN_PERIOD (10.0), + .CLKOUT_PHASE_SHIFT (""NONE""), + .CLK_FEEDBACK (""1X""), + .DESKEW_ADJUST (""SYSTEM_SYNCHRONOUS""), + .PHASE_SHIFT (0), + .STARTUP_WAIT (""FALSE"")) + dcm_sp_inst + // Input clock + (.CLKIN (clkin1), + .CLKFB (clkfb), + // Output clocks + .CLK0 (clk0), + .CLK90 (), + .CLK180 (), + .CLK270 (), + .CLK2X (), + .CLK2X180 (), + .CLKFX (), + .CLKFX180 (), + .CLKDV (clkdv), + // Ports for dynamic phase shift + .PSCLK (1\'b0), + .PSEN (1\'b0), + .PSINCDEC (1\'b0), + .PSDONE (), + // Other control and status signals + .LOCKED (locked_int), + .STATUS (status_int), + + .RST (RESET), + // Unused pin- tie low + .DSSEN (1\'b0)); + + assign LOCKED = locked_int; + + // Output buffering + //----------------------------------- + BUFG clkf_buf + (.O (clkfb), + .I (clk0)); + + BUFG clkout1_buf + (.O (CLK_OUT1), + .I (clkdv)); + + + + +endmodule +" +"// file: clk_divider_exdes.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE ""AS IS"" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, ""Critical +// Applications""). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// + +//---------------------------------------------------------------------------- +// Clocking wizard example design +//---------------------------------------------------------------------------- +// This example design instantiates the created clocking network, where each +// output clock drives a counter. The high bit of each counter is ported. +//---------------------------------------------------------------------------- + +`timescale 1ps/1ps + +module clk_divider_exdes + #( + parameter TCQ = 100 + ) + (// Clock in ports + input CLK_IN1, + // Reset that only drives logic in example design + input COUNTER_RESET, + output [1:1] CLK_OUT, + // High bits of counters driven by clocks + output COUNT, + // Status and control signals + input RESET, + output LOCKED + ); + + // Parameters for the counters + //------------------------------- + // Counter width + localparam C_W = 16; + // When the clock goes out of lock, reset the counters + wire reset_int = !LOCKED || RESET || COUNTER_RESET; + + reg rst_sync; + reg rst_sync_int; + reg rst_sync_int1; + reg rst_sync_int2; + + + + // Declare the clocks and counter + wire clk_int; + wire clk_n; + wire clk; + reg [C_W-1:0] counter; + + // Instantiation of the clocking network + //-------------------------------------- + clk_divider clknetwork + (// Clock in ports + .CLK_IN1 (CLK_IN1), + // Clock out ports + .CLK_OUT1 (clk_int), + // Status and control signals + .RESET (RESET), + .LOCKED (LOCKED)); + + assign clk_n = ~clk; + + ODDR2 clkout_oddr + (.Q (CLK_OUT[1]), + .C0 (clk), + .C1 (clk_n), + .CE (1\'b1), + .D0 (1\'b1), + .D1 (1\'b0), + .R (1\'b0), + .S (1\'b0)); + + // Connect the output clocks to the design + //----------------------------------------- + assign clk = clk_int; + + + // Reset synchronizer + //----------------------------------- + always @(posedge reset_int or posedge clk) begin + if (reset_int) begin + rst_sync <= 1\'b1; + rst_sync_int <= 1\'b1; + rst_sync_int1 <= 1\'b1; + rst_sync_int2 <= 1\'b1; + end + else begin + rst_sync <= 1\'b0; + rst_sync_int <= rst_sync; + rst_sync_int1 <= rst_sync_int; + rst_sync_int2 <= rst_sync_int1; + end + end + + + // Output clock sampling + //----------------------------------- + always @(posedge clk or posedge rst_sync_int2) begin + if (rst_sync_int2) begin + counter <= #TCQ { C_W { 1\'b 0 } }; + end else begin + counter <= #TCQ counter + 1\'b 1; + end + end + + // alias the high bit to the output + assign COUNT = counter[C_W-1]; + + + +endmodule +" +"//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2004 Xilinx, Inc. +// All Rights Reserved +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\\/ / +// /___/ \\ / Vendor: Xilinx +// \\ \\ \\/ Version: 1.02 +// \\ \\ Filename: ROM_form.v +// / / Date Last Modified: September 7 2004 +// /___/ /\\ Date Created: July 2003 +// \\ \\ / \\ +// \\___\\/\\___\\ +// +//Device: \tXilinx +//Purpose: \t +//\tThis is the Verilog template file for the KCPSM3 assembler. +//\tIt is used to configure a Spartan-3, Virtex-II or Virtex-IIPRO block +//\tRAM to act as a single port program ROM. +// +//\tThis Verilog file is not valid as input directly into a synthesis or +//\tsimulation tool.\tThe assembler will read this template and insert the +//\tdata required to complete the definition of program ROM and write it out +//\tto a new \'.v\' file associated with the name of the original \'.psm\' file +//\tbeing assembled. +// +//\tThis template can be modified to define alternative memory definitions +//\tsuch as dual port. However, you are responsible for ensuring the template +//\tis correct as the assembler does not perform any checking of the Verilog. +// +//\tThe assembler identifies all text enclosed by {} characters, and replaces +//\tthese character strings. All templates should include these {} character +//\tstrings for the assembler to work correctly. +// +//\tThis template defines a block RAM configured in 1024 x 18-bit single port +//\tmode and conneceted to act as a single port ROM. +// +//Reference: +// \tNone +//Revision History: +// Rev 1.00 - jc - Converted to verilog, July 2003. +// Rev 1.01 - sus - Added text to confirm to Xilinx HDL std, August 4 2004. +// Rev 1.02 - njs - Added attributes for Synplicity August 5 2004. +//\tRev 1.03 - sus - Added text to conform to Xilinx generated +//\t\t\t\tHDL spec, September 7 2004 +// +//////////////////////////////////////////////////////////////////////////////// +// Contact: e-mail picoblaze@xilinx.com +////////////////////////////////////////////////////////////////////////////////// +// +// Disclaimer: +// LIMITED WARRANTY AND DISCLAIMER. These designs are +// provided to you ""as is"". Xilinx and its licensors make and you +// receive no warranties or conditions, express, implied, +// statutory or otherwise, and Xilinx specifically disclaims any +// implied warranties of merchantability, non-infringement, or +// fitness for a particular purpose. Xilinx does not warrant that +// the functions contained in these designs will meet your +// requirements, or that the operation of these designs will be +// uninterrupted or error free, or that defects in the Designs +// will be corrected. Furthermore, Xilinx does not warrant or +// make any representations regarding use or the results of the +// use of the designs in terms of correctness, accuracy, +// reliability, or otherwise. +// +// LIMITATION OF LIABILITY. In no event will Xilinx or its +// licensors be liable for any loss of data, lost profits, cost +// or procurement of substitute goods or services, or for any +// special, incidental, consequential, or indirect damages +// arising from the use or operation of the designs or +// accompanying documentation, however caused and on any theory +// of liability. This limitation will apply even if Xilinx +// has been advised of the possibility of such damage. This +// limitation shall apply not-withstanding the failure of the +// essential purpose of any limited remedies herein. +////////////////////////////////////////////////////////////////////////////////// + +The next line is used to determine where the template actually starts and must exist. +{begin template} +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2004 Xilinx, Inc. +// All Rights Reserved +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\\/ / +// /___/ \\ / Vendor: Xilinx +// \\ \\ \\/ Version: v1.30 +// \\ \\ Application : KCPSM3 +// / / Filename: {name}.v +// /___/ /\\ +// \\ \\ / \\ +// \\___\\/\\___\\ +// +//Command: kcpsm3 {name}.psm +//Device: Spartan-3, Spartan-3E, Virtex-II, and Virtex-II Pro FPGAs +//Design Name: {name} +//Generated {timestamp}. +//Purpose: +//\t{name} verilog program definition. +// +//Reference: +//\tPicoBlaze 8-bit Embedded Microcontroller User Guide +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1ps + +module {name} (address, instruction, clk); + +input [9:0] address; +input clk; + +output [17:0] instruction; + +RAMB16_S18 ram_1024_x_18( +\t.DI \t(16\'h0000), +\t.DIP \t(2\'b00), +\t.EN\t(1\'b1), +\t.WE\t(1\'b0), +\t.SSR\t(1\'b0), +\t.CLK\t(clk), +\t.ADDR\t(address), +\t.DO\t(instruction[15:0]), +\t.DOP\t(instruction[17:16])) +/*synthesis +init_00 = ""{INIT_00}"" +init_01 = ""{INIT_01}"" +init_02 = ""{INIT_02}"" +init_03 = ""{INIT_03}"" +init_04 = ""{INIT_04}"" +init_05 = ""{INIT_05}"" +init_06 = ""{INIT_06}"" +init_07 = ""{INIT_07}"" +init_08 = ""{INIT_08}"" +init_09 = ""{INIT_09}"" +init_0A = ""{INIT_0A}"" +init_0B = ""{INIT_0B}"" +init_0C = ""{INIT_0C}"" +init_0D = ""{INIT_0D}"" +init_0E = ""{INIT_0E}"" +init_0F = ""{INIT_0F}"" +init_10 = ""{INIT_10}"" +init_11 = ""{INIT_11}"" +init_12 = ""{INIT_12}"" +init_13 = ""{INIT_13}"" +init_14 = ""{INIT_14}"" +init_15 = ""{INIT_15}"" +init_16 = ""{INIT_16}"" +init_17 = ""{INIT_17}"" +init_18 = ""{INIT_18}"" +init_19 = ""{INIT_19}"" +init_1A = ""{INIT_1A}"" +init_1B = ""{INIT_1B}"" +init_1C = ""{INIT_1C}"" +init_1D = ""{INIT_1D}"" +init_1E = ""{INIT_1E}"" +init_1F = ""{INIT_1F}"" +init_20 = ""{INIT_20}"" +init_21 = ""{INIT_21}"" +init_22 = ""{INIT_22}"" +init_23 = ""{INIT_23}"" +init_24 = ""{INIT_24}"" +init_25 = ""{INIT_25}"" +init_26 = ""{INIT_26}"" +init_27 = ""{INIT_27}"" +init_28 = ""{INIT_28}"" +init_29 = ""{INIT_29}"" +init_2A = ""{INIT_2A}"" +init_2B = ""{INIT_2B}"" +init_2C = ""{INIT_2C}"" +init_2D = ""{INIT_2D}"" +init_2E = ""{INIT_2E}"" +init_2F = ""{INIT_2F}"" +init_30 = ""{INIT_30}"" +init_31 = ""{INIT_31}"" +init_32 = ""{INIT_32}"" +init_33 = ""{INIT_33}"" +init_34 = ""{INIT_34}"" +init_35 = ""{INIT_35}"" +init_36 = ""{INIT_36}"" +init_37 = ""{INIT_37}"" +init_38 = ""{INIT_38}"" +init_39 = ""{INIT_39}"" +init_3A = ""{INIT_3A}"" +init_3B = ""{INIT_3B}"" +init_3C = ""{INIT_3C}"" +init_3D = ""{INIT_3D}"" +init_3E = ""{INIT_3E}"" +init_3F = ""{INIT_3F}"" +initp_00 = ""{INITP_00}"" +initp_01 = ""{INITP_01}"" +initp_02 = ""{INITP_02}"" +initp_03 = ""{INITP_03}"" +initp_04 = ""{INITP_04}"" +initp_05 = ""{INITP_05}"" +initp_06 = ""{INITP_06}"" +initp_07 = ""{INITP_07}"" */; + +// synthesis translate_off +// Attributes for Simulation +defparam ram_1024_x_18.INIT_00 = 256\'h{INIT_00}; +defparam ram_1024_x_18.INIT_01 = 256\'h{INIT_01}; +defparam ram_1024_x_18.INIT_02 = 256\'h{INIT_02}; +defparam ram_1024_x_18.INIT_03 = 256\'h{INIT_03}; +defparam ram_1024_x_18.INIT_04 = 256\'h{INIT_04}; +defparam ram_1024_x_18.INIT_05 = 256\'h{INIT_05}; +defparam ram_1024_x_18.INIT_06 = 256\'h{INIT_06}; +defparam ram_1024_x_18.INIT_07 = 256\'h{INIT_07}; +defparam ram_1024_x_18.INIT_08 = 256\'h{INIT_08}; +defparam ram_1024_x_18.INIT_09 = 256\'h{INIT_09}; +defparam ram_1024_x_18.INIT_0A = 256\'h{INIT_0A}; +defparam ram_1024_x_18.INIT_0B = 256\'h{INIT_0B}; +defparam ram_1024_x_18.INIT_0C = 256\'h{INIT_0C}; +defparam ram_1024_x_18.INIT_0D = 256\'h{INIT_0D}; +defparam ram_1024_x_18.INIT_0E = 256\'h{INIT_0E}; +defparam ram_1024_x_18.INIT_0F = 256\'h{INIT_0F}; +defparam ram_1024_x_18.INIT_10 = 256\'h{INIT_10}; +defparam ram_1024_x_18.INIT_11 = 256\'h{INIT_11}; +defparam ram_1024_x_18.INIT_12 = 256\'h{INIT_12}; +defparam ram_1024_x_18.INIT_13 = 256\'h{INIT_13}; +defparam ram_1024_x_18.INIT_14 = 256\'h{INIT_14}; +defparam ram_1024_x_18.INIT_15 = 256\'h{INIT_15}; +defparam ram_1024_x_18.INIT_16 = 256\'h{INIT_16}; +defparam ram_1024_x_18.INIT_17 = 256\'h{INIT_17}; +defparam ram_1024_x_18.INIT_18 = 256\'h{INIT_18}; +defparam ram_1024_x_18.INIT_19 = 256\'h{INIT_19}; +defparam ram_1024_x_18.INIT_1A = 256\'h{INIT_1A}; +defparam ram_1024_x_18.INIT_1B = 256\'h{INIT_1B}; +defparam ram_1024_x_18.INIT_1C = 256\'h{INIT_1C}; +defparam ram_1024_x_18.INIT_1D = 256\'h{INIT_1D}; +defparam ram_1024_x_18.INIT_1E = 256\'h{INIT_1E}; +defparam ram_1024_x_18.INIT_1F = 256\'h{INIT_1F}; +defparam ram_1024_x_18.INIT_20 = 256\'h{INIT_20}; +defparam ram_1024_x_18.INIT_21 = 256\'h{INIT_21}; +defparam ram_1024_x_18.INIT_22 = 256\'h{INIT_22}; +defparam ram_1024_x_18.INIT_23 = 256\'h{INIT_23}; +defparam ram_1024_x_18.INIT_24 = 256\'h{INIT_24}; +defparam ram_1024_x_18.INIT_25 = 256\'h{INIT_25}; +defparam ram_1024_x_18.INIT_26 = 256\'h{INIT_26}; +defparam ram_1024_x_18.INIT_27 = 256\'h{INIT_27}; +defparam ram_1024_x_18.INIT_28 = 256\'h{INIT_28}; +defparam ram_1024_x_18.INIT_29 = 256\'h{INIT_29}; +defparam ram_1024_x_18.INIT_2A = 256\'h{INIT_2A}; +defparam ram_1024_x_18.INIT_2B = 256\'h{INIT_2B}; +defparam ram_1024_x_18.INIT_2C = 256\'h{INIT_2C}; +defparam ram_1024_x_18.INIT_2D = 256\'h{INIT_2D}; +defparam ram_1024_x_18.INIT_2E = 256\'h{INIT_2E}; +defparam ram_1024_x_18.INIT_2F = 256\'h{INIT_2F}; +defparam ram_1024_x_18.INIT_30 = 256\'h{INIT_30}; +defparam ram_1024_x_18.INIT_31 = 256\'h{INIT_31}; +defparam ram_1024_x_18.INIT_32 = 256\'h{INIT_32}; +defparam ram_1024_x_18.INIT_33 = 256\'h{INIT_33}; +defparam ram_1024_x_18.INIT_34 = 256\'h{INIT_34}; +defparam ram_1024_x_18.INIT_35 = 256\'h{INIT_35}; +defparam ram_1024_x_18.INIT_36 = 256\'h{INIT_36}; +defparam ram_1024_x_18.INIT_37 = 256\'h{INIT_37}; +defparam ram_1024_x_18.INIT_38 = 256\'h{INIT_38}; +defparam ram_1024_x_18.INIT_39 = 256\'h{INIT_39}; +defparam ram_1024_x_18.INIT_3A = 256\'h{INIT_3A}; +defparam ram_1024_x_18.INIT_3B = 256\'h{INIT_3B}; +defparam ram_1024_x_18.INIT_3C = 256\'h{INIT_3C}; +defparam ram_1024_x_18.INIT_3D = 256\'h{INIT_3D}; +defparam ram_1024_x_18.INIT_3E = 256\'h{INIT_3E}; +defparam ram_1024_x_18.INIT_3F = 256\'h{INIT_3F}; +defparam ram_1024_x_18.INITP_00 = 256\'h{INITP_00}; +defparam ram_1024_x_18.INITP_01 = 256\'h{INITP_01}; +defparam ram_1024_x_18.INITP_02 = 256\'h{INITP_02}; +defparam ram_1024_x_18.INITP_03 = 256\'h{INITP_03}; +defparam ram_1024_x_18.INITP_04 = 256\'h{INITP_04}; +defparam ram_1024_x_18.INITP_05 = 256\'h{INITP_05}; +defparam ram_1024_x_18.INITP_06 = 256\'h{INITP_06}; +defparam ram_1024_x_18.INITP_07 = 256\'h{INITP_07}; + +// synthesis translate_on +// Attributes for XST (Synplicity attributes are in-line) +// synthesis attribute INIT_00 of ram_1024_x_18 is ""{INIT_00}"" +// synthesis attribute INIT_01 of ram_1024_x_18 is ""{INIT_01}"" +// synthesis attribute INIT_02 of ram_1024_x_18 is ""{INIT_02}"" +// synthesis attribute INIT_03 of ram_1024_x_18 is ""{INIT_03}"" +// synthesis attribute INIT_04 of ram_1024_x_18 is ""{INIT_04}"" +// synthesis attribute INIT_05 of ram_1024_x_18 is ""{INIT_05}"" +// synthesis attribute INIT_06 of ram_1024_x_18 is ""{INIT_06}"" +// synthesis attribute INIT_07 of ram_1024_x_18 is ""{INIT_07}"" +// synthesis attribute INIT_08 of ram_1024_x_18 is ""{INIT_08}"" +// synthesis attribute INIT_09 of ram_1024_x_18 is ""{INIT_09}"" +// synthesis attribute INIT_0A of ram_1024_x_18 is ""{INIT_0A}"" +// synthesis attribute INIT_0B of ram_1024_x_18 is ""{INIT_0B}"" +// synthesis attribute INIT_0C of ram_1024_x_18 is ""{INIT_0C}"" +// synthesis attribute INIT_0D of ram_1024_x_18 is ""{INIT_0D}"" +// synthesis attribute INIT_0E of ram_1024_x_18 is ""{INIT_0E}"" +// synthesis attribute INIT_0F of ram_1024_x_18 is ""{INIT_0F}"" +// synthesis attribute INIT_10 of ram_1024_x_18 is ""{INIT_10}"" +// synthesis attribute INIT_11 of ram_1024_x_18 is ""{INIT_11}"" +// synthesis attribute INIT_12 of ram_1024_x_18 is ""{INIT_12}"" +// synthesis attribute INIT_13 of ram_1024_x_18 is ""{INIT_13}"" +// synthesis attribute INIT_14 of ram_1024_x_18 is ""{INIT_14}"" +// synthesis attribute INIT_15 of ram_1024_x_18 is ""{INIT_15}"" +// synthesis attribute INIT_16 of ram_1024_x_18 is ""{INIT_16}"" +// synthesis attribute INIT_17 of ram_1024_x_18 is ""{INIT_17}"" +// synthesis attribute INIT_18 of ram_1024_x_18 is ""{INIT_18}"" +// synthesis attribute INIT_19 of ram_1024_x_18 is ""{INIT_19}"" +// synthesis attribute INIT_1A of ram_1024_x_18 is ""{INIT_1A}"" +// synthesis attribute INIT_1B of ram_1024_x_18 is ""{INIT_1B}"" +// synthesis attribute INIT_1C of ram_1024_x_18 is ""{INIT_1C}"" +// synthesis attribute INIT_1D of ram_1024_x_18 is ""{INIT_1D}"" +// synthesis attribute INIT_1E of ram_1024_x_18 is ""{INIT_1E}"" +// synthesis attribute INIT_1F of ram_1024_x_18 is ""{INIT_1F}"" +// synthesis attribute INIT_20 of ram_1024_x_18 is ""{INIT_20}"" +// synthesis attribute INIT_21 of ram_1024_x_18 is ""{INIT_21}"" +// synthesis attribute INIT_22 of ram_1024_x_18 is ""{INIT_22}"" +// synthesis attribute INIT_23 of ram_1024_x_18 is ""{INIT_23}"" +// synthesis attribute INIT_24 of ram_1024_x_18 is ""{INIT_24}"" +// synthesis attribute INIT_25 of ram_1024_x_18 is ""{INIT_25}"" +// synthesis attribute INIT_26 of ram_1024_x_18 is ""{INIT_26}"" +// synthesis attribute INIT_27 of ram_1024_x_18 is ""{INIT_27}"" +// synthesis attribute INIT_28 of ram_1024_x_18 is ""{INIT_28}"" +// synthesis attribute INIT_29 of ram_1024_x_18 is ""{INIT_29}"" +// synthesis attribute INIT_2A of ram_1024_x_18 is ""{INIT_2A}"" +// synthesis attribute INIT_2B of ram_1024_x_18 is ""{INIT_2B}"" +// synthesis attribute INIT_2C of ram_1024_x_18 is ""{INIT_2C}"" +// synthesis attribute INIT_2D of ram_1024_x_18 is ""{INIT_2D}"" +// synthesis attribute INIT_2E of ram_1024_x_18 is ""{INIT_2E}"" +// synthesis attribute INIT_2F of ram_1024_x_18 is ""{INIT_2F}"" +// synthesis attribute INIT_30 of ram_1024_x_18 is ""{INIT_30}"" +// synthesis attribute INIT_31 of ram_1024_x_18 is ""{INIT_31}"" +// synthesis attribute INIT_32 of ram_1024_x_18 is ""{INIT_32}"" +// synthesis attribute INIT_33 of ram_1024_x_18 is ""{INIT_33}"" +// synthesis attribute INIT_34 of ram_1024_x_18 is ""{INIT_34}"" +// synthesis attribute INIT_35 of ram_1024_x_18 is ""{INIT_35}"" +// synthesis attribute INIT_36 of ram_1024_x_18 is ""{INIT_36}"" +// synthesis attribute INIT_37 of ram_1024_x_18 is ""{INIT_37}"" +// synthesis attribute INIT_38 of ram_1024_x_18 is ""{INIT_38}"" +// synthesis attribute INIT_39 of ram_1024_x_18 is ""{INIT_39}"" +// synthesis attribute INIT_3A of ram_1024_x_18 is ""{INIT_3A}"" +// synthesis attribute INIT_3B of ram_1024_x_18 is ""{INIT_3B}"" +// synthesis attribute INIT_3C of ram_1024_x_18 is ""{INIT_3C}"" +// synthesis attribute INIT_3D of ram_1024_x_18 is ""{INIT_3D}"" +// synthesis attribute INIT_3E of ram_1024_x_18 is ""{INIT_3E}"" +// synthesis attribute INIT_3F of ram_1024_x_18 is ""{INIT_3F}"" +// synthesis attribute INITP_00 of ram_1024_x_18 is ""{INITP_00}"" +// synthesis attribute INITP_01 of ram_1024_x_18 is ""{INITP_01}"" +// synthesis attribute INITP_02 of ram_1024_x_18 is ""{INITP_02}"" +// synthesis attribute INITP_03 of ram_1024_x_18 is ""{INITP_03}"" +// synthesis attribute INITP_04 of ram_1024_x_18 is ""{INITP_04}"" +// synthesis attribute INITP_05 of ram_1024_x_18 is ""{INITP_05}"" +// synthesis attribute INITP_06 of ram_1024_x_18 is ""{INITP_06}"" +// synthesis attribute INITP_07 of ram_1024_x_18 is ""{INITP_07}"" + +endmodule + +// END OF FILE {name}.v" +"//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2004 Xilinx, Inc. +// All Rights Reserved +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\\/ / +// /___/ \\ / Vendor: Xilinx +// \\ \\ \\/ Version: 1.02 +// \\ \\ Filename: ROM_form.v +// / / Date Last Modified: September 7 2004 +// /___/ /\\ Date Created: July 2003 +// \\ \\ / \\ +// \\___\\/\\___\\ +// +//Device: \tXilinx +//Purpose: \t +//\tThis is the Verilog template file for the KCPSM3 assembler. +//\tIt is used to configure a Spartan-3, Virtex-II or Virtex-IIPRO block +//\tRAM to act as a single port program ROM. +// +//\tThis Verilog file is not valid as input directly into a synthesis or +//\tsimulation tool.\tThe assembler will read this template and insert the +//\tdata required to complete the definition of program ROM and write it out +//\tto a new \'.v\' file associated with the name of the original \'.psm\' file +//\tbeing assembled. +// +//\tThis template can be modified to define alternative memory definitions +//\tsuch as dual port. However, you are responsible for ensuring the template +//\tis correct as the assembler does not perform any checking of the Verilog. +// +//\tThe assembler identifies all text enclosed by {} characters, and replaces +//\tthese character strings. All templates should include these {} character +//\tstrings for the assembler to work correctly. +// +//\tThis template defines a block RAM configured in 1024 x 18-bit single port +//\tmode and conneceted to act as a single port ROM. +// +//Reference: +// \tNone +//Revision History: +// Rev 1.00 - jc - Converted to verilog, July 2003. +// Rev 1.01 - sus - Added text to confirm to Xilinx HDL std, August 4 2004. +// Rev 1.02 - njs - Added attributes for Synplicity August 5 2004. +//\tRev 1.03 - sus - Added text to conform to Xilinx generated +//\t\t\t\tHDL spec, September 7 2004 +// +//////////////////////////////////////////////////////////////////////////////// +// Contact: e-mail picoblaze@xilinx.com +////////////////////////////////////////////////////////////////////////////////// +// +// Disclaimer: +// LIMITED WARRANTY AND DISCLAIMER. These designs are +// provided to you ""as is"". Xilinx and its licensors make and you +// receive no warranties or conditions, express, implied, +// statutory or otherwise, and Xilinx specifically disclaims any +// implied warranties of merchantability, non-infringement, or +// fitness for a particular purpose. Xilinx does not warrant that +// the functions contained in these designs will meet your +// requirements, or that the operation of these designs will be +// uninterrupted or error free, or that defects in the Designs +// will be corrected. Furthermore, Xilinx does not warrant or +// make any representations regarding use or the results of the +// use of the designs in terms of correctness, accuracy, +// reliability, or otherwise. +// +// LIMITATION OF LIABILITY. In no event will Xilinx or its +// licensors be liable for any loss of data, lost profits, cost +// or procurement of substitute goods or services, or for any +// special, incidental, consequential, or indirect damages +// arising from the use or operation of the designs or +// accompanying documentation, however caused and on any theory +// of liability. This limitation will apply even if Xilinx +// has been advised of the possibility of such damage. This +// limitation shall apply not-withstanding the failure of the +// essential purpose of any limited remedies herein. +////////////////////////////////////////////////////////////////////////////////// + +The next line is used to determine where the template actually starts and must exist. +{begin template} +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2004 Xilinx, Inc. +// All Rights Reserved +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\\/ / +// /___/ \\ / Vendor: Xilinx +// \\ \\ \\/ Version: v1.30 +// \\ \\ Application : KCPSM3 +// / / Filename: {name}.v +// /___/ /\\ +// \\ \\ / \\ +// \\___\\/\\___\\ +// +//Command: kcpsm3 {name}.psm +//Device: Spartan-3, Spartan-3E, Virtex-II, and Virtex-II Pro FPGAs +//Design Name: {name} +//Generated {timestamp}. +//Purpose: +//\t{name} verilog program definition. +// +//Reference: +//\tPicoBlaze 8-bit Embedded Microcontroller User Guide +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1ps + +module {name} (address, instruction, clk); + +input [9:0] address; +input clk; + +output [17:0] instruction; + +RAMB16_S18 ram_1024_x_18( +\t.DI \t(16\'h0000), +\t.DIP \t(2\'b00), +\t.EN\t(1\'b1), +\t.WE\t(1\'b0), +\t.SSR\t(1\'b0), +\t.CLK\t(clk), +\t.ADDR\t(address), +\t.DO\t(instruction[15:0]), +\t.DOP\t(instruction[17:16])) +/*synthesis +init_00 = ""{INIT_00}"" +init_01 = ""{INIT_01}"" +init_02 = ""{INIT_02}"" +init_03 = ""{INIT_03}"" +init_04 = ""{INIT_04}"" +init_05 = ""{INIT_05}"" +init_06 = ""{INIT_06}"" +init_07 = ""{INIT_07}"" +init_08 = ""{INIT_08}"" +init_09 = ""{INIT_09}"" +init_0A = ""{INIT_0A}"" +init_0B = ""{INIT_0B}"" +init_0C = ""{INIT_0C}"" +init_0D = ""{INIT_0D}"" +init_0E = ""{INIT_0E}"" +init_0F = ""{INIT_0F}"" +init_10 = ""{INIT_10}"" +init_11 = ""{INIT_11}"" +init_12 = ""{INIT_12}"" +init_13 = ""{INIT_13}"" +init_14 = ""{INIT_14}"" +init_15 = ""{INIT_15}"" +init_16 = ""{INIT_16}"" +init_17 = ""{INIT_17}"" +init_18 = ""{INIT_18}"" +init_19 = ""{INIT_19}"" +init_1A = ""{INIT_1A}"" +init_1B = ""{INIT_1B}"" +init_1C = ""{INIT_1C}"" +init_1D = ""{INIT_1D}"" +init_1E = ""{INIT_1E}"" +init_1F = ""{INIT_1F}"" +init_20 = ""{INIT_20}"" +init_21 = ""{INIT_21}"" +init_22 = ""{INIT_22}"" +init_23 = ""{INIT_23}"" +init_24 = ""{INIT_24}"" +init_25 = ""{INIT_25}"" +init_26 = ""{INIT_26}"" +init_27 = ""{INIT_27}"" +init_28 = ""{INIT_28}"" +init_29 = ""{INIT_29}"" +init_2A = ""{INIT_2A}"" +init_2B = ""{INIT_2B}"" +init_2C = ""{INIT_2C}"" +init_2D = ""{INIT_2D}"" +init_2E = ""{INIT_2E}"" +init_2F = ""{INIT_2F}"" +init_30 = ""{INIT_30}"" +init_31 = ""{INIT_31}"" +init_32 = ""{INIT_32}"" +init_33 = ""{INIT_33}"" +init_34 = ""{INIT_34}"" +init_35 = ""{INIT_35}"" +init_36 = ""{INIT_36}"" +init_37 = ""{INIT_37}"" +init_38 = ""{INIT_38}"" +init_39 = ""{INIT_39}"" +init_3A = ""{INIT_3A}"" +init_3B = ""{INIT_3B}"" +init_3C = ""{INIT_3C}"" +init_3D = ""{INIT_3D}"" +init_3E = ""{INIT_3E}"" +init_3F = ""{INIT_3F}"" +initp_00 = ""{INITP_00}"" +initp_01 = ""{INITP_01}"" +initp_02 = ""{INITP_02}"" +initp_03 = ""{INITP_03}"" +initp_04 = ""{INITP_04}"" +initp_05 = ""{INITP_05}"" +initp_06 = ""{INITP_06}"" +initp_07 = ""{INITP_07}"" */; + +// synthesis translate_off +// Attributes for Simulation +defparam ram_1024_x_18.INIT_00 = 256\'h{INIT_00}; +defparam ram_1024_x_18.INIT_01 = 256\'h{INIT_01}; +defparam ram_1024_x_18.INIT_02 = 256\'h{INIT_02}; +defparam ram_1024_x_18.INIT_03 = 256\'h{INIT_03}; +defparam ram_1024_x_18.INIT_04 = 256\'h{INIT_04}; +defparam ram_1024_x_18.INIT_05 = 256\'h{INIT_05}; +defparam ram_1024_x_18.INIT_06 = 256\'h{INIT_06}; +defparam ram_1024_x_18.INIT_07 = 256\'h{INIT_07}; +defparam ram_1024_x_18.INIT_08 = 256\'h{INIT_08}; +defparam ram_1024_x_18.INIT_09 = 256\'h{INIT_09}; +defparam ram_1024_x_18.INIT_0A = 256\'h{INIT_0A}; +defparam ram_1024_x_18.INIT_0B = 256\'h{INIT_0B}; +defparam ram_1024_x_18.INIT_0C = 256\'h{INIT_0C}; +defparam ram_1024_x_18.INIT_0D = 256\'h{INIT_0D}; +defparam ram_1024_x_18.INIT_0E = 256\'h{INIT_0E}; +defparam ram_1024_x_18.INIT_0F = 256\'h{INIT_0F}; +defparam ram_1024_x_18.INIT_10 = 256\'h{INIT_10}; +defparam ram_1024_x_18.INIT_11 = 256\'h{INIT_11}; +defparam ram_1024_x_18.INIT_12 = 256\'h{INIT_12}; +defparam ram_1024_x_18.INIT_13 = 256\'h{INIT_13}; +defparam ram_1024_x_18.INIT_14 = 256\'h{INIT_14}; +defparam ram_1024_x_18.INIT_15 = 256\'h{INIT_15}; +defparam ram_1024_x_18.INIT_16 = 256\'h{INIT_16}; +defparam ram_1024_x_18.INIT_17 = 256\'h{INIT_17}; +defparam ram_1024_x_18.INIT_18 = 256\'h{INIT_18}; +defparam ram_1024_x_18.INIT_19 = 256\'h{INIT_19}; +defparam ram_1024_x_18.INIT_1A = 256\'h{INIT_1A}; +defparam ram_1024_x_18.INIT_1B = 256\'h{INIT_1B}; +defparam ram_1024_x_18.INIT_1C = 256\'h{INIT_1C}; +defparam ram_1024_x_18.INIT_1D = 256\'h{INIT_1D}; +defparam ram_1024_x_18.INIT_1E = 256\'h{INIT_1E}; +defparam ram_1024_x_18.INIT_1F = 256\'h{INIT_1F}; +defparam ram_1024_x_18.INIT_20 = 256\'h{INIT_20}; +defparam ram_1024_x_18.INIT_21 = 256\'h{INIT_21}; +defparam ram_1024_x_18.INIT_22 = 256\'h{INIT_22}; +defparam ram_1024_x_18.INIT_23 = 256\'h{INIT_23}; +defparam ram_1024_x_18.INIT_24 = 256\'h{INIT_24}; +defparam ram_1024_x_18.INIT_25 = 256\'h{INIT_25}; +defparam ram_1024_x_18.INIT_26 = 256\'h{INIT_26}; +defparam ram_1024_x_18.INIT_27 = 256\'h{INIT_27}; +defparam ram_1024_x_18.INIT_28 = 256\'h{INIT_28}; +defparam ram_1024_x_18.INIT_29 = 256\'h{INIT_29}; +defparam ram_1024_x_18.INIT_2A = 256\'h{INIT_2A}; +defparam ram_1024_x_18.INIT_2B = 256\'h{INIT_2B}; +defparam ram_1024_x_18.INIT_2C = 256\'h{INIT_2C}; +defparam ram_1024_x_18.INIT_2D = 256\'h{INIT_2D}; +defparam ram_1024_x_18.INIT_2E = 256\'h{INIT_2E}; +defparam ram_1024_x_18.INIT_2F = 256\'h{INIT_2F}; +defparam ram_1024_x_18.INIT_30 = 256\'h{INIT_30}; +defparam ram_1024_x_18.INIT_31 = 256\'h{INIT_31}; +defparam ram_1024_x_18.INIT_32 = 256\'h{INIT_32}; +defparam ram_1024_x_18.INIT_33 = 256\'h{INIT_33}; +defparam ram_1024_x_18.INIT_34 = 256\'h{INIT_34}; +defparam ram_1024_x_18.INIT_35 = 256\'h{INIT_35}; +defparam ram_1024_x_18.INIT_36 = 256\'h{INIT_36}; +defparam ram_1024_x_18.INIT_37 = 256\'h{INIT_37}; +defparam ram_1024_x_18.INIT_38 = 256\'h{INIT_38}; +defparam ram_1024_x_18.INIT_39 = 256\'h{INIT_39}; +defparam ram_1024_x_18.INIT_3A = 256\'h{INIT_3A}; +defparam ram_1024_x_18.INIT_3B = 256\'h{INIT_3B}; +defparam ram_1024_x_18.INIT_3C = 256\'h{INIT_3C}; +defparam ram_1024_x_18.INIT_3D = 256\'h{INIT_3D}; +defparam ram_1024_x_18.INIT_3E = 256\'h{INIT_3E}; +defparam ram_1024_x_18.INIT_3F = 256\'h{INIT_3F}; +defparam ram_1024_x_18.INITP_00 = 256\'h{INITP_00}; +defparam ram_1024_x_18.INITP_01 = 256\'h{INITP_01}; +defparam ram_1024_x_18.INITP_02 = 256\'h{INITP_02}; +defparam ram_1024_x_18.INITP_03 = 256\'h{INITP_03}; +defparam ram_1024_x_18.INITP_04 = 256\'h{INITP_04}; +defparam ram_1024_x_18.INITP_05 = 256\'h{INITP_05}; +defparam ram_1024_x_18.INITP_06 = 256\'h{INITP_06}; +defparam ram_1024_x_18.INITP_07 = 256\'h{INITP_07}; + +// synthesis translate_on +// Attributes for XST (Synplicity attributes are in-line) +// synthesis attribute INIT_00 of ram_1024_x_18 is ""{INIT_00}"" +// synthesis attribute INIT_01 of ram_1024_x_18 is ""{INIT_01}"" +// synthesis attribute INIT_02 of ram_1024_x_18 is ""{INIT_02}"" +// synthesis attribute INIT_03 of ram_1024_x_18 is ""{INIT_03}"" +// synthesis attribute INIT_04 of ram_1024_x_18 is ""{INIT_04}"" +// synthesis attribute INIT_05 of ram_1024_x_18 is ""{INIT_05}"" +// synthesis attribute INIT_06 of ram_1024_x_18 is ""{INIT_06}"" +// synthesis attribute INIT_07 of ram_1024_x_18 is ""{INIT_07}"" +// synthesis attribute INIT_08 of ram_1024_x_18 is ""{INIT_08}"" +// synthesis attribute INIT_09 of ram_1024_x_18 is ""{INIT_09}"" +// synthesis attribute INIT_0A of ram_1024_x_18 is ""{INIT_0A}"" +// synthesis attribute INIT_0B of ram_1024_x_18 is ""{INIT_0B}"" +// synthesis attribute INIT_0C of ram_1024_x_18 is ""{INIT_0C}"" +// synthesis attribute INIT_0D of ram_1024_x_18 is ""{INIT_0D}"" +// synthesis attribute INIT_0E of ram_1024_x_18 is ""{INIT_0E}"" +// synthesis attribute INIT_0F of ram_1024_x_18 is ""{INIT_0F}"" +// synthesis attribute INIT_10 of ram_1024_x_18 is ""{INIT_10}"" +// synthesis attribute INIT_11 of ram_1024_x_18 is ""{INIT_11}"" +// synthesis attribute INIT_12 of ram_1024_x_18 is ""{INIT_12}"" +// synthesis attribute INIT_13 of ram_1024_x_18 is ""{INIT_13}"" +// synthesis attribute INIT_14 of ram_1024_x_18 is ""{INIT_14}"" +// synthesis attribute INIT_15 of ram_1024_x_18 is ""{INIT_15}"" +// synthesis attribute INIT_16 of ram_1024_x_18 is ""{INIT_16}"" +// synthesis attribute INIT_17 of ram_1024_x_18 is ""{INIT_17}"" +// synthesis attribute INIT_18 of ram_1024_x_18 is ""{INIT_18}"" +// synthesis attribute INIT_19 of ram_1024_x_18 is ""{INIT_19}"" +// synthesis attribute INIT_1A of ram_1024_x_18 is ""{INIT_1A}"" +// synthesis attribute INIT_1B of ram_1024_x_18 is ""{INIT_1B}"" +// synthesis attribute INIT_1C of ram_1024_x_18 is ""{INIT_1C}"" +// synthesis attribute INIT_1D of ram_1024_x_18 is ""{INIT_1D}"" +// synthesis attribute INIT_1E of ram_1024_x_18 is ""{INIT_1E}"" +// synthesis attribute INIT_1F of ram_1024_x_18 is ""{INIT_1F}"" +// synthesis attribute INIT_20 of ram_1024_x_18 is ""{INIT_20}"" +// synthesis attribute INIT_21 of ram_1024_x_18 is ""{INIT_21}"" +// synthesis attribute INIT_22 of ram_1024_x_18 is ""{INIT_22}"" +// synthesis attribute INIT_23 of ram_1024_x_18 is ""{INIT_23}"" +// synthesis attribute INIT_24 of ram_1024_x_18 is ""{INIT_24}"" +// synthesis attribute INIT_25 of ram_1024_x_18 is ""{INIT_25}"" +// synthesis attribute INIT_26 of ram_1024_x_18 is ""{INIT_26}"" +// synthesis attribute INIT_27 of ram_1024_x_18 is ""{INIT_27}"" +// synthesis attribute INIT_28 of ram_1024_x_18 is ""{INIT_28}"" +// synthesis attribute INIT_29 of ram_1024_x_18 is ""{INIT_29}"" +// synthesis attribute INIT_2A of ram_1024_x_18 is ""{INIT_2A}"" +// synthesis attribute INIT_2B of ram_1024_x_18 is ""{INIT_2B}"" +// synthesis attribute INIT_2C of ram_1024_x_18 is ""{INIT_2C}"" +// synthesis attribute INIT_2D of ram_1024_x_18 is ""{INIT_2D}"" +// synthesis attribute INIT_2E of ram_1024_x_18 is ""{INIT_2E}"" +// synthesis attribute INIT_2F of ram_1024_x_18 is ""{INIT_2F}"" +// synthesis attribute INIT_30 of ram_1024_x_18 is ""{INIT_30}"" +// synthesis attribute INIT_31 of ram_1024_x_18 is ""{INIT_31}"" +// synthesis attribute INIT_32 of ram_1024_x_18 is ""{INIT_32}"" +// synthesis attribute INIT_33 of ram_1024_x_18 is ""{INIT_33}"" +// synthesis attribute INIT_34 of ram_1024_x_18 is ""{INIT_34}"" +// synthesis attribute INIT_35 of ram_1024_x_18 is ""{INIT_35}"" +// synthesis attribute INIT_36 of ram_1024_x_18 is ""{INIT_36}"" +// synthesis attribute INIT_37 of ram_1024_x_18 is ""{INIT_37}"" +// synthesis attribute INIT_38 of ram_1024_x_18 is ""{INIT_38}"" +// synthesis attribute INIT_39 of ram_1024_x_18 is ""{INIT_39}"" +// synthesis attribute INIT_3A of ram_1024_x_18 is ""{INIT_3A}"" +// synthesis attribute INIT_3B of ram_1024_x_18 is ""{INIT_3B}"" +// synthesis attribute INIT_3C of ram_1024_x_18 is ""{INIT_3C}"" +// synthesis attribute INIT_3D of ram_1024_x_18 is ""{INIT_3D}"" +// synthesis attribute INIT_3E of ram_1024_x_18 is ""{INIT_3E}"" +// synthesis attribute INIT_3F of ram_1024_x_18 is ""{INIT_3F}"" +// synthesis attribute INITP_00 of ram_1024_x_18 is ""{INITP_00}"" +// synthesis attribute INITP_01 of ram_1024_x_18 is ""{INITP_01}"" +// synthesis attribute INITP_02 of ram_1024_x_18 is ""{INITP_02}"" +// synthesis attribute INITP_03 of ram_1024_x_18 is ""{INITP_03}"" +// synthesis attribute INITP_04 of ram_1024_x_18 is ""{INITP_04}"" +// synthesis attribute INITP_05 of ram_1024_x_18 is ""{INITP_05}"" +// synthesis attribute INITP_06 of ram_1024_x_18 is ""{INITP_06}"" +// synthesis attribute INITP_07 of ram_1024_x_18 is ""{INITP_07}"" + +endmodule + +// END OF FILE {name}.v" +"//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2004 Xilinx, Inc. +// All Rights Reserved +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\\/ / +// /___/ \\ / Vendor: Xilinx +// \\ \\ \\/ Version: 1.02 +// \\ \\ Filename: ROM_form.v +// / / Date Last Modified: September 7 2004 +// /___/ /\\ Date Created: July 2003 +// \\ \\ / \\ +// \\___\\/\\___\\ +// +//Device: \tXilinx +//Purpose: \t +//\tThis is the Verilog template file for the KCPSM3 assembler. +//\tIt is used to configure a Spartan-3, Virtex-II or Virtex-IIPRO block +//\tRAM to act as a single port program ROM. +// +//\tThis Verilog file is not valid as input directly into a synthesis or +//\tsimulation tool.\tThe assembler will read this template and insert the +//\tdata required to complete the definition of program ROM and write it out +//\tto a new \'.v\' file associated with the name of the original \'.psm\' file +//\tbeing assembled. +// +//\tThis template can be modified to define alternative memory definitions +//\tsuch as dual port. However, you are responsible for ensuring the template +//\tis correct as the assembler does not perform any checking of the Verilog. +// +//\tThe assembler identifies all text enclosed by {} characters, and replaces +//\tthese character strings. All templates should include these {} character +//\tstrings for the assembler to work correctly. +// +//\tThis template defines a block RAM configured in 1024 x 18-bit single port +//\tmode and conneceted to act as a single port ROM. +// +//Reference: +// \tNone +//Revision History: +// Rev 1.00 - jc - Converted to verilog, July 2003. +// Rev 1.01 - sus - Added text to confirm to Xilinx HDL std, August 4 2004. +// Rev 1.02 - njs - Added attributes for Synplicity August 5 2004. +//\tRev 1.03 - sus - Added text to conform to Xilinx generated +//\t\t\t\tHDL spec, September 7 2004 +// +//////////////////////////////////////////////////////////////////////////////// +// Contact: e-mail picoblaze@xilinx.com +////////////////////////////////////////////////////////////////////////////////// +// +// Disclaimer: +// LIMITED WARRANTY AND DISCLAIMER. These designs are +// provided to you ""as is"". Xilinx and its licensors make and you +// receive no warranties or conditions, express, implied, +// statutory or otherwise, and Xilinx specifically disclaims any +// implied warranties of merchantability, non-infringement, or +// fitness for a particular purpose. Xilinx does not warrant that +// the functions contained in these designs will meet your +// requirements, or that the operation of these designs will be +// uninterrupted or error free, or that defects in the Designs +// will be corrected. Furthermore, Xilinx does not warrant or +// make any representations regarding use or the results of the +// use of the designs in terms of correctness, accuracy, +// reliability, or otherwise. +// +// LIMITATION OF LIABILITY. In no event will Xilinx or its +// licensors be liable for any loss of data, lost profits, cost +// or procurement of substitute goods or services, or for any +// special, incidental, consequential, or indirect damages +// arising from the use or operation of the designs or +// accompanying documentation, however caused and on any theory +// of liability. This limitation will apply even if Xilinx +// has been advised of the possibility of such damage. This +// limitation shall apply not-withstanding the failure of the +// essential purpose of any limited remedies herein. +////////////////////////////////////////////////////////////////////////////////// + +The next line is used to determine where the template actually starts and must exist. +{begin template} +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2004 Xilinx, Inc. +// All Rights Reserved +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\\/ / +// /___/ \\ / Vendor: Xilinx +// \\ \\ \\/ Version: v1.30 +// \\ \\ Application : KCPSM3 +// / / Filename: {name}.v +// /___/ /\\ +// \\ \\ / \\ +// \\___\\/\\___\\ +// +//Command: kcpsm3 {name}.psm +//Device: Spartan-3, Spartan-3E, Virtex-II, and Virtex-II Pro FPGAs +//Design Name: {name} +//Generated {timestamp}. +//Purpose: +//\t{name} verilog program definition. +// +//Reference: +//\tPicoBlaze 8-bit Embedded Microcontroller User Guide +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1ps + +module {name} (address, instruction, clk); + +input [9:0] address; +input clk; + +output [17:0] instruction; + +RAMB16_S18 ram_1024_x_18( +\t.DI \t(16\'h0000), +\t.DIP \t(2\'b00), +\t.EN\t(1\'b1), +\t.WE\t(1\'b0), +\t.SSR\t(1\'b0), +\t.CLK\t(clk), +\t.ADDR\t(address), +\t.DO\t(instruction[15:0]), +\t.DOP\t(instruction[17:16])) +/*synthesis +init_00 = ""{INIT_00}"" +init_01 = ""{INIT_01}"" +init_02 = ""{INIT_02}"" +init_03 = ""{INIT_03}"" +init_04 = ""{INIT_04}"" +init_05 = ""{INIT_05}"" +init_06 = ""{INIT_06}"" +init_07 = ""{INIT_07}"" +init_08 = ""{INIT_08}"" +init_09 = ""{INIT_09}"" +init_0A = ""{INIT_0A}"" +init_0B = ""{INIT_0B}"" +init_0C = ""{INIT_0C}"" +init_0D = ""{INIT_0D}"" +init_0E = ""{INIT_0E}"" +init_0F = ""{INIT_0F}"" +init_10 = ""{INIT_10}"" +init_11 = ""{INIT_11}"" +init_12 = ""{INIT_12}"" +init_13 = ""{INIT_13}"" +init_14 = ""{INIT_14}"" +init_15 = ""{INIT_15}"" +init_16 = ""{INIT_16}"" +init_17 = ""{INIT_17}"" +init_18 = ""{INIT_18}"" +init_19 = ""{INIT_19}"" +init_1A = ""{INIT_1A}"" +init_1B = ""{INIT_1B}"" +init_1C = ""{INIT_1C}"" +init_1D = ""{INIT_1D}"" +init_1E = ""{INIT_1E}"" +init_1F = ""{INIT_1F}"" +init_20 = ""{INIT_20}"" +init_21 = ""{INIT_21}"" +init_22 = ""{INIT_22}"" +init_23 = ""{INIT_23}"" +init_24 = ""{INIT_24}"" +init_25 = ""{INIT_25}"" +init_26 = ""{INIT_26}"" +init_27 = ""{INIT_27}"" +init_28 = ""{INIT_28}"" +init_29 = ""{INIT_29}"" +init_2A = ""{INIT_2A}"" +init_2B = ""{INIT_2B}"" +init_2C = ""{INIT_2C}"" +init_2D = ""{INIT_2D}"" +init_2E = ""{INIT_2E}"" +init_2F = ""{INIT_2F}"" +init_30 = ""{INIT_30}"" +init_31 = ""{INIT_31}"" +init_32 = ""{INIT_32}"" +init_33 = ""{INIT_33}"" +init_34 = ""{INIT_34}"" +init_35 = ""{INIT_35}"" +init_36 = ""{INIT_36}"" +init_37 = ""{INIT_37}"" +init_38 = ""{INIT_38}"" +init_39 = ""{INIT_39}"" +init_3A = ""{INIT_3A}"" +init_3B = ""{INIT_3B}"" +init_3C = ""{INIT_3C}"" +init_3D = ""{INIT_3D}"" +init_3E = ""{INIT_3E}"" +init_3F = ""{INIT_3F}"" +initp_00 = ""{INITP_00}"" +initp_01 = ""{INITP_01}"" +initp_02 = ""{INITP_02}"" +initp_03 = ""{INITP_03}"" +initp_04 = ""{INITP_04}"" +initp_05 = ""{INITP_05}"" +initp_06 = ""{INITP_06}"" +initp_07 = ""{INITP_07}"" */; + +// synthesis translate_off +// Attributes for Simulation +defparam ram_1024_x_18.INIT_00 = 256\'h{INIT_00}; +defparam ram_1024_x_18.INIT_01 = 256\'h{INIT_01}; +defparam ram_1024_x_18.INIT_02 = 256\'h{INIT_02}; +defparam ram_1024_x_18.INIT_03 = 256\'h{INIT_03}; +defparam ram_1024_x_18.INIT_04 = 256\'h{INIT_04}; +defparam ram_1024_x_18.INIT_05 = 256\'h{INIT_05}; +defparam ram_1024_x_18.INIT_06 = 256\'h{INIT_06}; +defparam ram_1024_x_18.INIT_07 = 256\'h{INIT_07}; +defparam ram_1024_x_18.INIT_08 = 256\'h{INIT_08}; +defparam ram_1024_x_18.INIT_09 = 256\'h{INIT_09}; +defparam ram_1024_x_18.INIT_0A = 256\'h{INIT_0A}; +defparam ram_1024_x_18.INIT_0B = 256\'h{INIT_0B}; +defparam ram_1024_x_18.INIT_0C = 256\'h{INIT_0C}; +defparam ram_1024_x_18.INIT_0D = 256\'h{INIT_0D}; +defparam ram_1024_x_18.INIT_0E = 256\'h{INIT_0E}; +defparam ram_1024_x_18.INIT_0F = 256\'h{INIT_0F}; +defparam ram_1024_x_18.INIT_10 = 256\'h{INIT_10}; +defparam ram_1024_x_18.INIT_11 = 256\'h{INIT_11}; +defparam ram_1024_x_18.INIT_12 = 256\'h{INIT_12}; +defparam ram_1024_x_18.INIT_13 = 256\'h{INIT_13}; +defparam ram_1024_x_18.INIT_14 = 256\'h{INIT_14}; +defparam ram_1024_x_18.INIT_15 = 256\'h{INIT_15}; +defparam ram_1024_x_18.INIT_16 = 256\'h{INIT_16}; +defparam ram_1024_x_18.INIT_17 = 256\'h{INIT_17}; +defparam ram_1024_x_18.INIT_18 = 256\'h{INIT_18}; +defparam ram_1024_x_18.INIT_19 = 256\'h{INIT_19}; +defparam ram_1024_x_18.INIT_1A = 256\'h{INIT_1A}; +defparam ram_1024_x_18.INIT_1B = 256\'h{INIT_1B}; +defparam ram_1024_x_18.INIT_1C = 256\'h{INIT_1C}; +defparam ram_1024_x_18.INIT_1D = 256\'h{INIT_1D}; +defparam ram_1024_x_18.INIT_1E = 256\'h{INIT_1E}; +defparam ram_1024_x_18.INIT_1F = 256\'h{INIT_1F}; +defparam ram_1024_x_18.INIT_20 = 256\'h{INIT_20}; +defparam ram_1024_x_18.INIT_21 = 256\'h{INIT_21}; +defparam ram_1024_x_18.INIT_22 = 256\'h{INIT_22}; +defparam ram_1024_x_18.INIT_23 = 256\'h{INIT_23}; +defparam ram_1024_x_18.INIT_24 = 256\'h{INIT_24}; +defparam ram_1024_x_18.INIT_25 = 256\'h{INIT_25}; +defparam ram_1024_x_18.INIT_26 = 256\'h{INIT_26}; +defparam ram_1024_x_18.INIT_27 = 256\'h{INIT_27}; +defparam ram_1024_x_18.INIT_28 = 256\'h{INIT_28}; +defparam ram_1024_x_18.INIT_29 = 256\'h{INIT_29}; +defparam ram_1024_x_18.INIT_2A = 256\'h{INIT_2A}; +defparam ram_1024_x_18.INIT_2B = 256\'h{INIT_2B}; +defparam ram_1024_x_18.INIT_2C = 256\'h{INIT_2C}; +defparam ram_1024_x_18.INIT_2D = 256\'h{INIT_2D}; +defparam ram_1024_x_18.INIT_2E = 256\'h{INIT_2E}; +defparam ram_1024_x_18.INIT_2F = 256\'h{INIT_2F}; +defparam ram_1024_x_18.INIT_30 = 256\'h{INIT_30}; +defparam ram_1024_x_18.INIT_31 = 256\'h{INIT_31}; +defparam ram_1024_x_18.INIT_32 = 256\'h{INIT_32}; +defparam ram_1024_x_18.INIT_33 = 256\'h{INIT_33}; +defparam ram_1024_x_18.INIT_34 = 256\'h{INIT_34}; +defparam ram_1024_x_18.INIT_35 = 256\'h{INIT_35}; +defparam ram_1024_x_18.INIT_36 = 256\'h{INIT_36}; +defparam ram_1024_x_18.INIT_37 = 256\'h{INIT_37}; +defparam ram_1024_x_18.INIT_38 = 256\'h{INIT_38}; +defparam ram_1024_x_18.INIT_39 = 256\'h{INIT_39}; +defparam ram_1024_x_18.INIT_3A = 256\'h{INIT_3A}; +defparam ram_1024_x_18.INIT_3B = 256\'h{INIT_3B}; +defparam ram_1024_x_18.INIT_3C = 256\'h{INIT_3C}; +defparam ram_1024_x_18.INIT_3D = 256\'h{INIT_3D}; +defparam ram_1024_x_18.INIT_3E = 256\'h{INIT_3E}; +defparam ram_1024_x_18.INIT_3F = 256\'h{INIT_3F}; +defparam ram_1024_x_18.INITP_00 = 256\'h{INITP_00}; +defparam ram_1024_x_18.INITP_01 = 256\'h{INITP_01}; +defparam ram_1024_x_18.INITP_02 = 256\'h{INITP_02}; +defparam ram_1024_x_18.INITP_03 = 256\'h{INITP_03}; +defparam ram_1024_x_18.INITP_04 = 256\'h{INITP_04}; +defparam ram_1024_x_18.INITP_05 = 256\'h{INITP_05}; +defparam ram_1024_x_18.INITP_06 = 256\'h{INITP_06}; +defparam ram_1024_x_18.INITP_07 = 256\'h{INITP_07}; + +// synthesis translate_on +// Attributes for XST (Synplicity attributes are in-line) +// synthesis attribute INIT_00 of ram_1024_x_18 is ""{INIT_00}"" +// synthesis attribute INIT_01 of ram_1024_x_18 is ""{INIT_01}"" +// synthesis attribute INIT_02 of ram_1024_x_18 is ""{INIT_02}"" +// synthesis attribute INIT_03 of ram_1024_x_18 is ""{INIT_03}"" +// synthesis attribute INIT_04 of ram_1024_x_18 is ""{INIT_04}"" +// synthesis attribute INIT_05 of ram_1024_x_18 is ""{INIT_05}"" +// synthesis attribute INIT_06 of ram_1024_x_18 is ""{INIT_06}"" +// synthesis attribute INIT_07 of ram_1024_x_18 is ""{INIT_07}"" +// synthesis attribute INIT_08 of ram_1024_x_18 is ""{INIT_08}"" +// synthesis attribute INIT_09 of ram_1024_x_18 is ""{INIT_09}"" +// synthesis attribute INIT_0A of ram_1024_x_18 is ""{INIT_0A}"" +// synthesis attribute INIT_0B of ram_1024_x_18 is ""{INIT_0B}"" +// synthesis attribute INIT_0C of ram_1024_x_18 is ""{INIT_0C}"" +// synthesis attribute INIT_0D of ram_1024_x_18 is ""{INIT_0D}"" +// synthesis attribute INIT_0E of ram_1024_x_18 is ""{INIT_0E}"" +// synthesis attribute INIT_0F of ram_1024_x_18 is ""{INIT_0F}"" +// synthesis attribute INIT_10 of ram_1024_x_18 is ""{INIT_10}"" +// synthesis attribute INIT_11 of ram_1024_x_18 is ""{INIT_11}"" +// synthesis attribute INIT_12 of ram_1024_x_18 is ""{INIT_12}"" +// synthesis attribute INIT_13 of ram_1024_x_18 is ""{INIT_13}"" +// synthesis attribute INIT_14 of ram_1024_x_18 is ""{INIT_14}"" +// synthesis attribute INIT_15 of ram_1024_x_18 is ""{INIT_15}"" +// synthesis attribute INIT_16 of ram_1024_x_18 is ""{INIT_16}"" +// synthesis attribute INIT_17 of ram_1024_x_18 is ""{INIT_17}"" +// synthesis attribute INIT_18 of ram_1024_x_18 is ""{INIT_18}"" +// synthesis attribute INIT_19 of ram_1024_x_18 is ""{INIT_19}"" +// synthesis attribute INIT_1A of ram_1024_x_18 is ""{INIT_1A}"" +// synthesis attribute INIT_1B of ram_1024_x_18 is ""{INIT_1B}"" +// synthesis attribute INIT_1C of ram_1024_x_18 is ""{INIT_1C}"" +// synthesis attribute INIT_1D of ram_1024_x_18 is ""{INIT_1D}"" +// synthesis attribute INIT_1E of ram_1024_x_18 is ""{INIT_1E}"" +// synthesis attribute INIT_1F of ram_1024_x_18 is ""{INIT_1F}"" +// synthesis attribute INIT_20 of ram_1024_x_18 is ""{INIT_20}"" +// synthesis attribute INIT_21 of ram_1024_x_18 is ""{INIT_21}"" +// synthesis attribute INIT_22 of ram_1024_x_18 is ""{INIT_22}"" +// synthesis attribute INIT_23 of ram_1024_x_18 is ""{INIT_23}"" +// synthesis attribute INIT_24 of ram_1024_x_18 is ""{INIT_24}"" +// synthesis attribute INIT_25 of ram_1024_x_18 is ""{INIT_25}"" +// synthesis attribute INIT_26 of ram_1024_x_18 is ""{INIT_26}"" +// synthesis attribute INIT_27 of ram_1024_x_18 is ""{INIT_27}"" +// synthesis attribute INIT_28 of ram_1024_x_18 is ""{INIT_28}"" +// synthesis attribute INIT_29 of ram_1024_x_18 is ""{INIT_29}"" +// synthesis attribute INIT_2A of ram_1024_x_18 is ""{INIT_2A}"" +// synthesis attribute INIT_2B of ram_1024_x_18 is ""{INIT_2B}"" +// synthesis attribute INIT_2C of ram_1024_x_18 is ""{INIT_2C}"" +// synthesis attribute INIT_2D of ram_1024_x_18 is ""{INIT_2D}"" +// synthesis attribute INIT_2E of ram_1024_x_18 is ""{INIT_2E}"" +// synthesis attribute INIT_2F of ram_1024_x_18 is ""{INIT_2F}"" +// synthesis attribute INIT_30 of ram_1024_x_18 is ""{INIT_30}"" +// synthesis attribute INIT_31 of ram_1024_x_18 is ""{INIT_31}"" +// synthesis attribute INIT_32 of ram_1024_x_18 is ""{INIT_32}"" +// synthesis attribute INIT_33 of ram_1024_x_18 is ""{INIT_33}"" +// synthesis attribute INIT_34 of ram_1024_x_18 is ""{INIT_34}"" +// synthesis attribute INIT_35 of ram_1024_x_18 is ""{INIT_35}"" +// synthesis attribute INIT_36 of ram_1024_x_18 is ""{INIT_36}"" +// synthesis attribute INIT_37 of ram_1024_x_18 is ""{INIT_37}"" +// synthesis attribute INIT_38 of ram_1024_x_18 is ""{INIT_38}"" +// synthesis attribute INIT_39 of ram_1024_x_18 is ""{INIT_39}"" +// synthesis attribute INIT_3A of ram_1024_x_18 is ""{INIT_3A}"" +// synthesis attribute INIT_3B of ram_1024_x_18 is ""{INIT_3B}"" +// synthesis attribute INIT_3C of ram_1024_x_18 is ""{INIT_3C}"" +// synthesis attribute INIT_3D of ram_1024_x_18 is ""{INIT_3D}"" +// synthesis attribute INIT_3E of ram_1024_x_18 is ""{INIT_3E}"" +// synthesis attribute INIT_3F of ram_1024_x_18 is ""{INIT_3F}"" +// synthesis attribute INITP_00 of ram_1024_x_18 is ""{INITP_00}"" +// synthesis attribute INITP_01 of ram_1024_x_18 is ""{INITP_01}"" +// synthesis attribute INITP_02 of ram_1024_x_18 is ""{INITP_02}"" +// synthesis attribute INITP_03 of ram_1024_x_18 is ""{INITP_03}"" +// synthesis attribute INITP_04 of ram_1024_x_18 is ""{INITP_04}"" +// synthesis attribute INITP_05 of ram_1024_x_18 is ""{INITP_05}"" +// synthesis attribute INITP_06 of ram_1024_x_18 is ""{INITP_06}"" +// synthesis attribute INITP_07 of ram_1024_x_18 is ""{INITP_07}"" + +endmodule + +// END OF FILE {name}.v" +"/* + -------------------------------------------------------------------------- + Pegasus - Copyright (C) 2012 Gregory Matthew James. + + This file is part of Pegasus. + + Pegasus is free; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + Pegasus is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + -------------------------------------------------------------------------- +*/ + +/* + -------------------------------------------------------------------------- + -- Project Code : pegasus + -- Module Name : peg_l2_mac_tx + -- Author : mammenx + -- Associated modules: + -- Function : Wrapper for L2 MAC TX. + -------------------------------------------------------------------------- +*/ + +`timescale 1ns / 10ps + +`inlcude ""pkt_intf_defines.sv"" + +module peg_l2_mac_tx #( + parameter PKT_DATA_W = 8, + parameter PKT_SIZE_W = 16 +) + +( + + input clk, + input rst_n, + + //Inputs from L2 MAC RX + input mac_pause_en, + + //MAC Logic Link Control packet interface + `pkt_intf_ports_s(llc_tx_,,PKT_DATA_W), + + //RS packet interface + pkt_intf_ports_m(rs_tx_,,PKT_DATA_W) +); + +//----------------------- Global parameters Declarations ------------------ + + +//----------------------- Input Declarations ------------------------------ + + +//----------------------- Inout Declarations ------------------------------ + + +//----------------------- Output Declarations ----------------------------- + + +//----------------------- Output Register Declaration --------------------- + + +//----------------------- Internal Register Declarations ------------------ + + +//----------------------- Internal Wire Declarations ---------------------- + +//----------------------- Input/Output Registers -------------------------- + +//----------------------- Start of Code ----------------------------------- + + peg_l2_mac_tx_framer #( + .PKT_DATA_W(PKT_DATA_W), + .PKT_SIZE_W(PKT_SIZE_W) + ) + u_l2_mac_tx_framer + ( + + .clk (clk), + .rst_n (rst_n), + + //Config interface + .config_l2_mac_tx_en (), + .config_l2_mac_tx_padding_en (), + .config_l2_mac_tx_fcs_en (), + .config_l2_mac_addr (), + .config_l2_mac_tx_pause_gen (), + .config_l2_mac_tx_pause_time (), + + //Status interface + .l2_mac_tx_fsm_state (), + + //Pause Interface from MAC RX + .mac_pause_en (mac_pause_en), + + //MAC Logic Link Control packet interface + `pkt_intf_port_connect(llc_tx_,,llc_tx_,), + + //RS packet interface + `pkt_intf_port_connect(rs_tx_,,rs_tx_,) + + ); + + +endmodule // peg_l2_mac_tx + + +/* + -------------------------------------------------------------------------- + + --
+ + + -- + +[28-07-2014 04:18:29 PM][mammenx] Created basic wrapper + +[28-05-14 20:18:21] [mammenx] Moved log section to bottom of file + + -------------------------------------------------------------------------- +*/ +" +"/* + -------------------------------------------------------------------------- + Pegasus - Copyright (C) 2012 Gregory Matthew James. + + This file is part of Pegasus. + + Pegasus is free; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + Pegasus is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + -------------------------------------------------------------------------- +*/ + +/* + -------------------------------------------------------------------------- + -- Project Code : pegasus + -- Module Name : peg_l2_mac_rx + -- Author : mammenx + -- Associated modules: + -- Function : Wrapper for L2 MAC TX. + -------------------------------------------------------------------------- +*/ + +`timescale 1ns / 10ps + +`inlcude ""pkt_intf_defines.sv"" + +module peg_l2_mac_rx #( + parameter PKT_DATA_W = 8, + parameter PKT_SIZE_W = 16, + parameter NUM_FIELDS = 8, + parameter BFFR_SIZE = 48 +) + +( + + input clk, + input rst_n, + + //Outputs to MAC TX + output mac_pause_en, + + //MAC Logic Link packet interface + `pkt_intf_ports_m(llc_rx_,,PKT_DATA_W), + + //RS packet interface + `pkt_intf_ports_s(rs_rx_,,PKT_DATA_W) +); + +//----------------------- Global parameters Declarations ------------------ + + +//----------------------- Input Declarations ------------------------------ + + +//----------------------- Inout Declarations ------------------------------ + + +//----------------------- Output Declarations ----------------------------- + + +//----------------------- Output Register Declaration --------------------- + + +//----------------------- Internal Register Declarations ------------------ + + +//----------------------- Internal Wire Declarations ---------------------- + wire [NUM_FIELDS-1:0] rx_field_valid_vec_w; + wire [BFFR_SIZE-1:0] rx_bffr_w; + + wire fcs_calc_rst_w; + wire fcs_calc_en_w; + wire [PKT_DATA_W-1:0] fcs_calc_data_w; + +//----------------------- Input/Output Registers -------------------------- + +//----------------------- Start of Code ----------------------------------- + + peg_l2_mac_rx_parser #( + .PKT_DATA_W(PKT_DATA_W), + .PKT_SIZE_W(PKT_SIZE_W), + .NUM_FIELDS(NUM_FIELDS), + .BFFR_SIZE(BFFR_SIZE) + ) + u_l2_mac_rx_parser + ( + .clk (clk), + .rst_n (rst_n), + + //Config interface + .config_l2_mac_rx_en, + .config_l2_mac_rx_fcs_en, + .config_l2_mac_rx_strip_preamble_sfd, + .config_l2_mac_rx_strip_fcs, + + //Status interface + .l2_mac_rx_fsm_state, + + //Interface to RX Filter & Pause Gen + .rx_field_valid_vec (rx_field_valid_vec_w), + .rx_bffr (rx_bffr_w), + + //Interface to FCS Calculator + .rx_fcs_rst (fcs_calc_rst_w), + .rx_fcs_calc_en (fcs_calc_en_w), + .rx_fcs_calc_data (fcs_calc_data_w), + + //RS packet interface + `pkt_intf_port_connect(rs_rx_,,rs_rx_,), + + //LLC packet interface + `pkt_intf_port_connect(llc_rx_,,llc_rx_,) + + ); + + + peg_l2_mac_pause_cntr #( + .BPCLK(PKT_DATA_W) + ) + u_pause_cntr + ( + .clk (clk), + .rst_n (rst_n), + + //Config + .pause_en (), + + //Inputs from Parser + .pause_time_valid (rx_field_valid_vec_w[MAC_FIDX_PAUSE_TIME]), + .pause_time (rx_bffr_w[15:0]), + + //Pause Status + .pause_valid (mac_pause_en) + + ); + + + peg_l2_fcs_gen #( + .DATA_W(PKT_DATA_W), + .CRC_INIT_VAL(32\'d0) + ) + u_l2_fcs_gen + ( + .clk (clk), + .rst_n (rst_n), + + .fcs_calc_rst (fcs_calc_rst_w), + .fcs_calc_valid (fcs_calc_en_w), + .fcs_calc_data (fcs_calc_data_w), + + .fcs () + + ); + + + +endmodule // peg_l2_mac_rx + + +/* + -------------------------------------------------------------------------- + + --
+ + + -- + +[28-07-2014 04:18:29 PM][mammenx] Created basic wrapper + +[28-05-14 20:18:21] [mammenx] Moved log section to bottom of file + + -------------------------------------------------------------------------- +*/ +" +"/* + -------------------------------------------------------------------------- + Pegasus - Copyright (C) 2012 Gregory Matthew James. + + This file is part of Pegasus. + + Pegasus is free; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + Pegasus is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + -------------------------------------------------------------------------- +*/ + +/* + -------------------------------------------------------------------------- + -- Project Code : pegasus + -- Module Name : pkt_ff_wptr + -- Author : mammenx + -- Associated modules: + -- Function : This module maintains the write pointer logic for + the fifo. + -------------------------------------------------------------------------- +*/ + +`timescale 1ns / 10ps + + +module pkt_ff_wptr #(PTR_W = 8) + +( + + //--------------------- Misc Ports (Logic) ----------- + clk, + rst_n, + + valid, + sop, + eop, + error. + + wptr + + //--------------------- Interfaces -------------------- + + +); + +//----------------------- Global parameters Declarations ------------------ + + +//----------------------- Input Declarations ------------------------------ + input clk; + input rst_n; + + input valid; + input sop; + input eop; + input error; + +//----------------------- Inout Declarations ------------------------------ + + +//----------------------- Output Declarations ----------------------------- + output [PTR_W-1:0] wptr; + +//----------------------- Output Register Declaration --------------------- + + +//----------------------- Internal Register Declarations ------------------ + reg [PTR_W-1:0] sop_ptr_f; + +//----------------------- Internal Wire Declarations ---------------------- + reg wptr_rewind_n_c; + reg wptr_inc_en_c; + +//----------------------- Internal Interface Declarations ----------------- + + +//----------------------- FSM Declarations -------------------------------- + + +//----------------------- Start of Code ----------------------------------- + + + always@(posedge clk, negedge rst_n) + begin + if(~rst_n) + begin + sop_ptr_f <= 0; + end + else + begin + //Record the start of packet location for future rewind + sop_ptr_f <= (valid & sop) ? wptr : sop_ptr_f; + + end + end + + //Reset the wptr to last SOP location + assign wptr_rewind_n_c = (valid & error) ? 1'b0 : rst_n; + + //Logic to decide when to increment wptr + assign wptr_inc_en_c = valid & ~error; + + //Implement wptr as a gray counter + gry_cntr u_wptr_gry_cntr + ( + + .clk (clk), + .rst_n (wptr_rewind_n_c), + + .rst_val (sop_ptr_f), + + .en (wptr_inc_en_c), + .gry_cnt (wptr), + .gry_cnt_nxt () + + ); + + defparam u_wptr_gry_cntr.WIDTH = PTR_W; + + + +endmodule // pkt_ff_wptr + +/* + -------------------------------------------------------------------------- + + --
+ + + -- + +[28-06-2014 03:30:57 PM][mammenx] Moved to Verilog + +[08-06-2014 02:11:10 PM][mammenx] Modified gry_cntr reset signal + +[08-06-2014 02:07:20 PM][mammenx] Brought out gry_cnt_nxt port + +[08-06-2014 12:54:08 PM][mammenx] Initial Commit + +[28-05-14 20:18:21] [mammenx] Moved log section to bottom of file + + -------------------------------------------------------------------------- +*/ +" +"/* + -------------------------------------------------------------------------- + Pegasus - Copyright (C) 2012 Gregory Matthew James. + + This file is part of Pegasus. + + Pegasus is free; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + Pegasus is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + -------------------------------------------------------------------------- +*/ + +/* + -------------------------------------------------------------------------- + -- Project Code : pegasus + -- Module Name : dd_sync + -- Author : mammenx + -- Associated modules: + -- Function : This module synchronizes a signal (of parameterized + width) to the destination clock. + -------------------------------------------------------------------------- +*/ + +`timescale 1ns / 10ps + + +module dd_sync #(WIDTH = 1, STAGES = 2, RST_VAL = 0) + +( + + //--------------------- Misc Ports (Logic) ----------- + clk, + rst_n, + + data_i, + data_sync_o + + //--------------------- Interfaces -------------------- + + +); + +//----------------------- Global parameters Declarations ------------------ + + +//----------------------- Input Declarations ------------------------------ + input clk; + input rst_n; + + input [WIDTH-1:0] data_i; + +//----------------------- Inout Declarations ------------------------------ + + +//----------------------- Output Declarations ----------------------------- + output [WIDTH-1:0] data_sync_o; + +//----------------------- Output Register Declaration --------------------- + + +//----------------------- Internal Register Declarations ------------------ + reg [WIDTH-1:0] sync_pipe_f [0:STAGES-1]; + +//----------------------- Internal Wire Declarations ---------------------- + + +//----------------------- Internal Interface Declarations ----------------- + + +//----------------------- FSM Declarations -------------------------------- + + +//----------------------- Start of Code ----------------------------------- + + genvar i; + + generate + for(i=0; i + + + -- + +[28-06-2014 03:30:07 PM][mammenx] Moved to Verilog + +[08-06-2014 11:32:22 AM][mammenx] Corrected multi-dimension order for sync_pipe_f + +[08-06-2014 11:11:26 AM][mammenx] Added RST_VAL parameter + +[08-06-2014 11:09:00 AM][mammenx] Initial Version + +[28-05-14 20:18:21] [mammenx] Moved log section to bottom of file + + -------------------------------------------------------------------------- +*/ +" +"/* + -------------------------------------------------------------------------- + Pegasus - Copyright (C) 2012 Gregory Matthew James. + + This file is part of Pegasus. + + Pegasus is free; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + Pegasus is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + -------------------------------------------------------------------------- +*/ + +/* + -------------------------------------------------------------------------- + -- Project Code : pegasus + -- Module Name : pkt_ff_async + -- Author : mammenx + -- Associated modules: pkt_ff_async_mem, pkt_ff_rptr, pkt_ff_wptr + -- Function : The top module for pkt_ff_async. + -------------------------------------------------------------------------- +*/ + +`timescale 1ns / 10ps + + +module pkt_ff_async #(WIDTH = 32, DEPTH = 128, MAX_NO_PKTS=2) +( + + //--------------------- Misc Ports (Logic) ----------- + input ingr_clk, + input ingr_rst_n, + + input egr_clk, + input egr_rst_n, + + //Ingress packet interface + input ingr_valid, + input ingr_sop, + input ingr_eop, + input [WIDTH-1:0] ingr_data, + output ingr_ready, + input ingr_error, + + //Egress packet interface + output egr_valid, + output egr_sop, + output egr_eop, + output [WIDTH-1:0] egr_data, + input egr_ready, + output egr_error + + //--------------------- Interfaces -------------------- + +); + +//----------------------- Global parameters Declarations ------------------ + localparam PTR_W = $clog2(DEPTH); + +//----------------------- Input Declarations ------------------------------ + + +//----------------------- Inout Declarations ------------------------------ + + +//----------------------- Output Declarations ----------------------------- + + +//----------------------- Output Register Declaration --------------------- + + +//----------------------- Internal Register Declarations ------------------ + reg [PTR_W-1:0] credit_cnt_ingr_f; + reg credit_ingr_push_f; + reg [PTR_W-1:0] credit_cnt_egr_f; + + +//----------------------- Internal Wire Declarations ---------------------- + wire [PTR_W-1:0] wptr_w; + wire [PTR_W-1:0] rptr_w; + + wire data_ff_rd_en_c; + wire data_ff_wr_en_c; + + wire credit_ff_full_w; + wire credit_ff_empty_w; + wire [PTR_W-1:0] credit_ff_rdata_w; + wire credit_egr_pop_c; + +//----------------------- Internal Interface Declarations ----------------- + + +//----------------------- FSM Declarations -------------------------------- + + + +//----------------------- Start of Code ----------------------------------- + + //Generate read/write signals for data fifo + assign data_ff_wr_en_c = ingr_valid & ingr_ready & ~ingr_error; + assign data_ff_rd_en_c = egr_valid & egr_ready; + + pkt_ff_wptr u_wptr + ( + .clk (ingr_clk), + .rst_n (ingr_rst_n), + + .valid (ingr_valid), + .sop (ingr_sop), + .eop (ingr_eop), + .error (ingr_error), + + .wptr (wptr_w) + + ); + defparam u_wptr.PTR_W = PTR_W; + + + pkt_ff_rptr u_rptr + ( + .clk (egr_clk), + .rst_n (egr_rst_n), + + .rd_en (data_ff_rd_en_c), + + .rptr (rptr_w) + + ); + defparam u_rptr.PTR_W = PTR_W; + + + pkt_ff_async_mem u_mem + ( + .data (ingr_data), + .rdaddress (rptr_w), + .rdclock (egr_clk), + .wraddress (wptr_w), + .wrclock (ingr_clk), + .wren (data_ff_wr_en_c), + .q (egr_data) + ); + defparam u_mem.DWIDTH = WIDTH; + defparam u_mem.DEPTH = DEPTH; + + + + /* + * Credit management logic + */ + always@(posedge ingr_clk, negedge ingr_rst_n) + begin + if(~ingr_rst_n) + begin + credit_cnt_ingr_f <= 0; + credit_ingr_push_f <= 0; + end + else + begin + if(ingr_valid & ingr_ready) + begin + if(ingr_sof) + begin + credit_cnt_ingr_f <= WIDTH; + end + else + begin + credit_cnt_ingr_f <= credit_cnt_ingr_f + WIDTH; + end + end + else + begin + credit_cnt_ingr_f <= credit_cnt_ingr_f; + end + + credit_ingr_push_f <= ingr_valid & ingr_ready & + ingr_eof & ~ingr_error; + end + end + + always@(posedge egr_clk, negedge egr_rst_n) + begin + if(~egr_rst_n) + begin + credit_cnt_egr_f <= 0; + end + else + begin + if(credit_cnt_egr_f == 0) + begin + if(~credit_ff_empty_w) + begin + credit_cnt_egr_f <= credit_ff_rdata_w; + end + end + else if(egr_ready) + begin + credit_cnt_egr_f <= credit_cnt_egr_f - WIDTH; + end + end + end + + assign egr_valid = (credit_cnt_egr_f > 0) ? 1'b1 : 1'b0; + assign egr_sop = (credit_cnt_egr_f == credit_ff_rdata_w) ? ~credit_ff_empty_w : 1'b0; + assign egr_eop = (credit_cnt_egr_f <= WIDTH) ? egr_valid : 1'b0; + assign egr_error = 0; + + assign credit_egr_pop_c = egr_eop & egr_ready; + + assign ingr_ready = ~credit_ff_full_w; + + + credit_ff_async u_credit_ff + ( + .aclr (~ingr_rst_n | ~egr_rst_n), + .data (credit_cnt_ingr_f), + .rdclk (egr_clk), + .rdreq (credit_egr_pop_c), + .wrclk (ingr_clk), + .wrreq (credit_ingr_push_f), + .q (credit_ff_rdata_w), + .rdempty (credit_ff_empty_w), + .wrfull (credit_ff_full_w) + ); + defparam u_credit_ff.WIDTH = PTR_W; + defparam u_credit_ff.DEPTH = MAX_NO_PKTS; + + + +endmodule // pkt_ff_async + +/* + -------------------------------------------------------------------------- + + --
+ + + -- + +[28-06-2014 03:30:57 PM][mammenx] Moved to Verilog + +[08-06-2014 04:16:44 PM][mammenx] Initial Commit + +[28-05-14 20:18:21] [mammenx] Moved log section to bottom of file + + -------------------------------------------------------------------------- +*/ +" +"// megafunction wizard: %FIFO% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: dcfifo + +// ============================================================ +// File Name: credit_ff_async.v +// Megafunction Name(s): +// \t\t\tdcfifo +// +// Simulation Library Files(s): +// \t\t\taltera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2011 Altera Corporation +//Your use of Altera Corporation\'s design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module credit_ff_async #(WIDTH=8,DEPTH=512) ( +\taclr, +\tdata, +\trdclk, +\trdreq, +\twrclk, +\twrreq, +\tq, +\trdempty, +\twrfull); + +\tinput\t aclr; +\tinput\t[WIDTH-1:0] data; +\tinput\t rdclk; +\tinput\t rdreq; +\tinput\t wrclk; +\tinput\t wrreq; +\toutput\t[WIDTH-1:0] q; +\toutput\t rdempty; +\toutput\t wrfull; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif +\ttri0\t aclr; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + +\twire sub_wire0; +\twire [WIDTH-1:0] sub_wire1; +\twire sub_wire2; +\twire wrfull = sub_wire0; +\twire [WIDTH-1:0] q = sub_wire1[WIDTH-1:0]; +\twire rdempty = sub_wire2; + +\tdcfifo\tdcfifo_component ( +\t\t\t\t.rdclk (rdclk), +\t\t\t\t.wrclk (wrclk), +\t\t\t\t.wrreq (wrreq), +\t\t\t\t.aclr (aclr), +\t\t\t\t.data (data), +\t\t\t\t.rdreq (rdreq), +\t\t\t\t.wrfull (sub_wire0), +\t\t\t\t.q (sub_wire1), +\t\t\t\t.rdempty (sub_wire2), +\t\t\t\t.rdfull (), +\t\t\t\t.rdusedw (), +\t\t\t\t.wrempty (), +\t\t\t\t.wrusedw ()); +\tdefparam +\t\tdcfifo_component.intended_device_family = ""Cyclone II"", +\t\tdcfifo_component.lpm_hint = ""RAM_BLOCK_TYPE=M4K"", +\t\tdcfifo_component.lpm_numwords = DEPTH, +\t\tdcfifo_component.lpm_showahead = ""ON"", +\t\tdcfifo_component.lpm_type = ""dcfifo"", +\t\tdcfifo_component.lpm_width = WIDTH, +\t\tdcfifo_component.lpm_widthu = WIDTH+1, +\t\tdcfifo_component.overflow_checking = ""OFF"", +\t\tdcfifo_component.rdsync_delaypipe = 4, +\t\tdcfifo_component.underflow_checking = ""OFF"", +\t\tdcfifo_component.use_eab = ""ON"", +\t\tdcfifo_component.write_aclr_synch = ""OFF"", +\t\tdcfifo_component.wrsync_delaypipe = 4; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC ""0"" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC ""-1"" +// Retrieval info: PRIVATE: AlmostFull NUMERIC ""0"" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC ""-1"" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC ""0"" +// Retrieval info: PRIVATE: Clock NUMERIC ""4"" +// Retrieval info: PRIVATE: Depth NUMERIC ""512"" +// Retrieval info: PRIVATE: Empty NUMERIC ""1"" +// Retrieval info: PRIVATE: Full NUMERIC ""1"" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING ""Cyclone II"" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC ""0"" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC ""0"" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC ""0"" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC ""1"" +// Retrieval info: PRIVATE: Optimize NUMERIC ""0"" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC ""2"" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING ""0"" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC ""1"" +// Retrieval info: PRIVATE: UsedW NUMERIC ""1"" +// Retrieval info: PRIVATE: Width NUMERIC ""8"" +// Retrieval info: PRIVATE: dc_aclr NUMERIC ""1"" +// Retrieval info: PRIVATE: diff_widths NUMERIC ""0"" +// Retrieval info: PRIVATE: msb_usedw NUMERIC ""0"" +// Retrieval info: PRIVATE: output_width NUMERIC ""8"" +// Retrieval info: PRIVATE: rsEmpty NUMERIC ""1"" +// Retrieval info: PRIVATE: rsFull NUMERIC ""0"" +// Retrieval info: PRIVATE: rsUsedW NUMERIC ""0"" +// Retrieval info: PRIVATE: sc_aclr NUMERIC ""0"" +// Retrieval info: PRIVATE: sc_sclr NUMERIC ""0"" +// Retrieval info: PRIVATE: wsEmpty NUMERIC ""0"" +// Retrieval info: PRIVATE: wsFull NUMERIC ""1"" +// Retrieval info: PRIVATE: wsUsedW NUMERIC ""0"" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING ""Cyclone II"" +// Retrieval info: CONSTANT: LPM_HINT STRING ""RAM_BLOCK_TYPE=M4K"" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC ""512"" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING ""ON"" +// Retrieval info: CONSTANT: LPM_TYPE STRING ""dcfifo"" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC ""8"" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC ""9"" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING ""OFF"" +// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC ""4"" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING ""OFF"" +// Retrieval info: CONSTANT: USE_EAB STRING ""ON"" +// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING ""OFF"" +// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC ""4"" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND ""aclr"" +// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL ""data[7..0]"" +// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL ""q[7..0]"" +// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL ""rdclk"" +// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL ""rdempty"" +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL ""rdreq"" +// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL ""wrclk"" +// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL ""wrfull"" +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL ""wrreq"" +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0 +// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0 +// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 +// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL credit_ff_async.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL credit_ff_async.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL credit_ff_async.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL credit_ff_async.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL credit_ff_async_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL credit_ff_async_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +" +"/* + -------------------------------------------------------------------------- + Pegasus - Copyright (C) 2012 Gregory Matthew James. + + This file is part of Pegasus. + + Pegasus is free; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + Pegasus is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + -------------------------------------------------------------------------- +*/ + +/* + -------------------------------------------------------------------------- + -- Project Code : pegasus + -- Module Name : peg_l2_fcs_gen + -- Author : mammenx + -- Associated modules: + -- Function : This module generates FCS from the data stream. + -------------------------------------------------------------------------- +*/ + +`timescale 1ns / 10ps + + +module peg_l2_fcs_gen #( + parameter DATA_W = 8, + parameter CRC_INIT_VAL = 32'd0 +) + +( + input clk, + input rst_n, + + input fcs_calc_rst, + input fcs_calc_valid, + input [DATA_W-1:0] fcs_calc_data, + + output [31:0] fcs + +); + +//----------------------- Global parameters Declarations ------------------ + + +//----------------------- Input Declarations ------------------------------ + + +//----------------------- Inout Declarations ------------------------------ + + +//----------------------- Output Declarations ----------------------------- + + +//----------------------- Output Register Declaration --------------------- + + +//----------------------- Internal Register Declarations ------------------ + reg [31:0] crc_f; + + genvar i; + +//----------------------- Internal Wire Declarations ---------------------- + + +//----------------------- Input/Output Registers -------------------------- + +//----------------------- Start of Code ----------------------------------- + + always@(posedge clk, negedge rst_n) + begin + if(~rst_n) + begin + crc_f <= CRC_INIT_VAL; + end + else + begin + if(fcs_calc_rst) + begin + crc_f <= CRC_INIT_VAL; + end + else if(fcs_calc_valid) + begin + crc_f <= nextCRC32_D8(fcs_calc_data,crc_f); + end + end + end + + //FCS is bit reversed & complimented version of CRC + generate + for(i=0; i<32; i++) + begin + assign fcs[i] = ~crc_f[31-i]; + end + endgenerate + + +endmodule // peg_l2_fcs_gen + + +/* + -------------------------------------------------------------------------- + + --
+ + + -- + +[28-07-2014 04:18:29 PM][mammenx] Created basic wrapper + +[28-05-14 20:18:21] [mammenx] Moved log section to bottom of file + + -------------------------------------------------------------------------- +*/ +" +"// megafunction wizard: %RAM: 2-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: pkt_ff_async_mem.v +// Megafunction Name(s): +// \t\t\taltsyncram +// +// Simulation Library Files(s): +// \t\t\taltera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2011 Altera Corporation +//Your use of Altera Corporation\'s design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pkt_ff_async_mem #(DWIDTH=32, DEPTH=128) ( +\tdata, +\trdaddress, +\trdclock, +\twraddress, +\twrclock, +\twren, +\tq); + + localparam AWIDTH = $clog2(DEPTH); + +\tinput\t[DWIDTH-1:0] data; +\tinput\t[AWIDTH-1:0] rdaddress; +\tinput\t rdclock; +\tinput\t[AWIDTH-1:0] wraddress; +\tinput\t wrclock; +\tinput\t wren; +\toutput\t[DWIDTH-1:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif +\ttri1\t wrclock; +\ttri0\t wren; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + +\twire [DWIDTH-1:0] sub_wire0; +\twire [DWIDTH-1:0] q = sub_wire0[DWIDTH-1:0]; + +\taltsyncram\taltsyncram_component ( +\t\t\t\t.address_a (wraddress), +\t\t\t\t.clock0 (wrclock), +\t\t\t\t.data_a (data), +\t\t\t\t.wren_a (wren), +\t\t\t\t.address_b (rdaddress), +\t\t\t\t.clock1 (rdclock), +\t\t\t\t.q_b (sub_wire0), +\t\t\t\t.aclr0 (1\'b0), +\t\t\t\t.aclr1 (1\'b0), +\t\t\t\t.addressstall_a (1\'b0), +\t\t\t\t.addressstall_b (1\'b0), +\t\t\t\t.byteena_a (1\'b1), +\t\t\t\t.byteena_b (1\'b1), +\t\t\t\t.clocken0 (1\'b1), +\t\t\t\t.clocken1 (1\'b1), +\t\t\t\t.clocken2 (1\'b1), +\t\t\t\t.clocken3 (1\'b1), +\t\t\t\t.data_b ({DWIDTH{1\'b1}}), +\t\t\t\t.eccstatus (), +\t\t\t\t.q_a (), +\t\t\t\t.rden_a (1\'b1), +\t\t\t\t.rden_b (1\'b1), +\t\t\t\t.wren_b (1\'b0)); +\tdefparam +\t\taltsyncram_component.address_reg_b = ""CLOCK1"", +\t\taltsyncram_component.clock_enable_input_a = ""BYPASS"", +\t\taltsyncram_component.clock_enable_input_b = ""BYPASS"", +\t\taltsyncram_component.clock_enable_output_a = ""BYPASS"", +\t\taltsyncram_component.clock_enable_output_b = ""BYPASS"", +\t\taltsyncram_component.intended_device_family = ""Cyclone II"", +\t\taltsyncram_component.lpm_type = ""altsyncram"", +\t\taltsyncram_component.numwords_a = DEPTH, +\t\taltsyncram_component.numwords_b = DEPTH, +\t\taltsyncram_component.operation_mode = ""DUAL_PORT"", +\t\taltsyncram_component.outdata_aclr_b = ""NONE"", +\t\taltsyncram_component.outdata_reg_b = ""UNREGISTERED"", +\t\taltsyncram_component.power_up_uninitialized = ""FALSE"", +\t\taltsyncram_component.ram_block_type = ""M4K"", +\t\taltsyncram_component.widthad_a = AWIDTH, +\t\taltsyncram_component.widthad_b = AWIDTH, +\t\taltsyncram_component.width_a = DWIDTH, +\t\taltsyncram_component.width_b = DWIDTH, +\t\taltsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC ""0"" +// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC ""0"" +// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC ""0"" +// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC ""0"" +// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC ""0"" +// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC ""0"" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC ""8"" +// Retrieval info: PRIVATE: BlankMemory NUMERIC ""1"" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC ""0"" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC ""0"" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC ""0"" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC ""0"" +// Retrieval info: PRIVATE: CLRdata NUMERIC ""0"" +// Retrieval info: PRIVATE: CLRq NUMERIC ""0"" +// Retrieval info: PRIVATE: CLRrdaddress NUMERIC ""0"" +// Retrieval info: PRIVATE: CLRrren NUMERIC ""0"" +// Retrieval info: PRIVATE: CLRwraddress NUMERIC ""0"" +// Retrieval info: PRIVATE: CLRwren NUMERIC ""0"" +// Retrieval info: PRIVATE: Clock NUMERIC ""1"" +// Retrieval info: PRIVATE: Clock_A NUMERIC ""0"" +// Retrieval info: PRIVATE: Clock_B NUMERIC ""0"" +// Retrieval info: PRIVATE: ECC NUMERIC ""0"" +// Retrieval info: PRIVATE: ECC_PIPELINE_STAGE NUMERIC ""0"" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC ""0"" +// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC ""0"" +// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC ""0"" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING ""PORT_B"" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC ""0"" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING ""Cyclone II"" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC ""0"" +// Retrieval info: PRIVATE: JTAG_ID STRING ""NONE"" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC ""0"" +// Retrieval info: PRIVATE: MEMSIZE NUMERIC ""4096"" +// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC ""0"" +// Retrieval info: PRIVATE: MIFfilename STRING """" +// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC ""2"" +// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC ""0"" +// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC ""0"" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC ""2"" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC ""2"" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC ""3"" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC ""3"" +// Retrieval info: PRIVATE: REGdata NUMERIC ""1"" +// Retrieval info: PRIVATE: REGq NUMERIC ""1"" +// Retrieval info: PRIVATE: REGrdaddress NUMERIC ""1"" +// Retrieval info: PRIVATE: REGrren NUMERIC ""1"" +// Retrieval info: PRIVATE: REGwraddress NUMERIC ""1"" +// Retrieval info: PRIVATE: REGwren NUMERIC ""1"" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING ""0"" +// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC ""0"" +// Retrieval info: PRIVATE: UseDPRAM NUMERIC ""1"" +// Retrieval info: PRIVATE: VarWidth NUMERIC ""0"" +// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC ""32"" +// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC ""32"" +// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC ""32"" +// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC ""32"" +// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC ""0"" +// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC ""0"" +// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC ""0"" +// Retrieval info: PRIVATE: enable NUMERIC ""0"" +// Retrieval info: PRIVATE: rden NUMERIC ""0"" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_REG_B STRING ""CLOCK1"" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING ""BYPASS"" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING ""BYPASS"" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING ""BYPASS"" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING ""BYPASS"" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING ""Cyclone II"" +// Retrieval info: CONSTANT: LPM_TYPE STRING ""altsyncram"" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC ""128"" +// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC ""128"" +// Retrieval info: CONSTANT: OPERATION_MODE STRING ""DUAL_PORT"" +// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING ""NONE"" +// Retrieval info: CONSTANT: OUTDATA_REG_B STRING ""UNREGISTERED"" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING ""FALSE"" +// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING ""M4K"" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC ""7"" +// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC ""7"" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC ""32"" +// Retrieval info: CONSTANT: WIDTH_B NUMERIC ""32"" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC ""1"" +// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL ""data[31..0]"" +// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL ""q[31..0]"" +// Retrieval info: USED_PORT: rdaddress 0 0 7 0 INPUT NODEFVAL ""rdaddress[6..0]"" +// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL ""rdclock"" +// Retrieval info: USED_PORT: wraddress 0 0 7 0 INPUT NODEFVAL ""wraddress[6..0]"" +// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC ""wrclock"" +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND ""wren"" +// Retrieval info: CONNECT: @address_a 0 0 7 0 wraddress 0 0 7 0 +// Retrieval info: CONNECT: @address_b 0 0 7 0 rdaddress 0 0 7 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0 +// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pkt_ff_async_mem.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pkt_ff_async_mem.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pkt_ff_async_mem.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pkt_ff_async_mem.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pkt_ff_async_mem_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pkt_ff_async_mem_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +" +"/* + -------------------------------------------------------------------------- + Pegasus - Copyright (C) 2012 Gregory Matthew James. + + This file is part of Pegasus. + + Pegasus is free; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + Pegasus is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + -------------------------------------------------------------------------- +*/ + +/* + -------------------------------------------------------------------------- + -- Project Code : pegasus + -- Module Name : peg_l2_mac_tx_framer + -- Author : mammenx + -- Associated modules: + -- Function : This module contains the logic to frame L2 MAC frames + for transmission. This has a 8b pipeline that is + intended for upto 1Gbps speeds @ 125MHz clock. + -------------------------------------------------------------------------- +*/ + +`timescale 1ns / 10ps + + +module peg_l2_mac_tx_framer #( + + parameter PKT_DATA_W = 8, + parameter PKT_SIZE_W = 16 + +) + +( + + input clk, + input rst_n, + + //Config interface + input config_l2_mac_tx_en, + input config_l2_mac_tx_padding_en, + input config_l2_mac_tx_fcs_en, + input [47:0] config_l2_mac_addr, + input config_l2_mac_tx_pause_gen, + input [15:0] config_l2_mac_tx_pause_time, + + //Status interface + output [3:0] l2_mac_tx_fsm_state, + + //Pause Interface from MAC RX + input mac_pause_en, + + //MAC Logic Link Control packet interface + input llc_tx_valid, + input llc_tx_sop, + input llc_tx_eop, + input [PKT_DATA_W-1:0] llc_tx_data, + output llc_tx_ready, + input llc_tx_error, + + //RS packet interface + output rs_tx_valid, + output rs_tx_sop, + output rs_tx_eop, + output [PKT_DATA_W-1:0] rs_tx_data, + input rs_tx_ready, + output rs_tx_error + +); + +//----------------------- Global parameters Declarations ------------------ + `include ""peg_l2_params.v"" + + parameter PKT_SIZE_INC_VAL = PKT_DATA_W / 8; + parameter DATA_BFFR_SIZE = 5*8; + +//----------------------- Input Declarations ------------------------------ + + +//----------------------- Inout Declarations ------------------------------ + + +//----------------------- Output Declarations ----------------------------- + + +//----------------------- Output Register Declaration --------------------- + reg llc_tx_ready; + +//----------------------- Internal Register Declarations ------------------ + reg [15:0] data_cntr_f; + reg [DATA_BFFR_SIZE-1:0] data_bffr_f; + reg [15:0] final_pkt_size_f; + reg crc_en_f; + reg [31:0] crc_f; + reg pause_frm_f; + +//----------------------- Internal Wire Declarations ---------------------- + wire [15:0] data_bytes_w; + wire [DATA_BFFR_SIZE+PKT_DATA_W-1:0] data_bffr_w; + wire padding_required_c; + wire [PKT_DATA_W-1:0] crc_data_c; + wire state_change_c; + wire [31:0] fcs_c; + wire [2:0] fcs_index_c; + + genvar i; + +//----------------------- FSM Parameters -------------------------------------- +//only for FSM state vector representation +parameter [3:0] // synopsys enum fsm_pstate +IDLE_S = 4\'d0, +PREAMBLE_S = 4\'d1, +SFD_S = 4\'d2, +DA_S = 4\'d3, +SA_S = 4\'d4, +LEN_TYPE_S = 4\'d5, +VLAN_TAG_S = 4\'d6, +PAUSE_OPCODE_S = 4\'d7, +PAUSE_TIME_S = 4\'d8, +DATA_S = 4\'d9, +PADDING_S = 4\'d10, +FCS_S = 4\'d11; + +//----------------------- FSM Register Declarations ------------------ +reg [3:0] // synopsys enum fsm_pstate +fsm_pstate, next_state; + +//----------------------- FSM String Declarations ------------------ +//synthesis translate_off +reg [8*16:0] state_name;//""state name"" is user defined +//synthesis translate_on + +//----------------------- FSM Debugging Logic Declarations ------------------ +//synthesis translate_off +always @ (fsm_pstate) +begin +case (fsm_pstate) + +IDLE_S : state_name = ""IDLE_S""; + +PREAMBLE_S : state_name = ""PREAMBLE_S""; + +SFD_S : state_name = ""SFD_S""; + +DA_S : state_name = ""DA_S""; + +SA_S : state_name = ""SA_S""; + +LEN_TYPE_S : state_name = ""LEN_TYPE_S""; + +PAUSE_OPCODE_S : state_name = ""PAUSE_OPCODE_S""; + +PAUSE_TIME_S : state_name = ""PAUSE_TIME_S""; + +VLAN_TAG_S : state_name = ""VLAN_TAG_S""; + +DATA_S : state_name = ""DATA_S""; + +PADDING_S : state_name = ""PADDING_S""; + +FCS_S : state_name = ""FCS_S""; + +default : state_name = ""INVALID STATE!""; +endcase +end +//synthesis translate_on + +//----------------------- Input/Output Registers -------------------------- + +//----------------------- Start of Code ----------------------------------- + + + /* Main FSM Logic */ + always@(posedge clk, negedge rst_n) + begin + if(~rst_n) + begin + fsm_pstate <= IDLE_S; + data_cntr_f <= 0; + data_bffr_f <= 0; + final_pkt_size_f <= 0; + pause_frm_f <= 0; + end + else + begin + fsm_pstate <= next_state; + + if(fsm_pstate == IDLE_S) + begin + pause_frm_f <= config_l2_mac_tx_en & config_l2_mac_tx_pause_gen; + end + else if(fsm_pstate == FCS_S) + begin + pause_frm_f <= 1\'b0; + end + + if(fsm_pstate == IDLE_S) + begin + data_cntr_f <= 0; + end + else if(rs_tx_valid & rs_tx_ready) + begin + data_cntr_f <= data_cntr_f + 1\'b1; + end + + if(rs_tx_valid & rs_tx_ready) + begin + data_bffr_f <= {data_bffr_f[DATA_BFFR_SIZE-PKT_DATA_W-1:0],rs_tx_data}; + end + + if((fsm_pstate != FCS_S) & (next_state == FCS)) + begin + final_pkt_size_f <= data_cntr_f + 3\'d4; + end + end + end + + assign data_bffr_w = {data_bffr_f,rs_tx_data}; + + assign data_bytes_w = data_cntr_f; + + //Check if pkt has minimum size + assign padding_required_c = (data_bytes_w < MAC_MIN_FRM_LEN) ? (config_l2_mac_tx_padding_en | pause_frm_f) : 1\'b0; + + assign state_change_c = (next_state != fsm_pstate) ? 1\'b1 : 1\'b0; + + always@(*) + begin + next_state = fsm_pstate; + llc_tx_ready = 1\'b0; + + case(fsm_pstate) + + IDLE_S : + begin + if(((llc_tx_valid & llc_tx_sop) | config_l2_mac_tx_pause_gen) & config_l2_mac_tx_en) + begin + next_state = PREAMBLE_S; + end + end + + PREAMBLE_S : + begin + if((llc_tx_valid | pause_frm_f) & rs_tx_ready & (data_bytes_w == (MAC_SFD_OFFSET-1))) + begin + next_state = SFD_S; + end + end + + SFD_S : + begin + if((llc_tx_valid | pause_frm_f) & rs_tx_ready & (data_bytes_w == (MAC_DA_OFFSET-1))) + llc_tx_ready = ~pause_frm_f; + next_state = DA_S; + end + end + + DA_S : + begin + if((llc_tx_valid | pause_frm_f) & rs_tx_ready & (data_bytes_w == (MAC_SA_OFFSET-1))) + begin + llc_tx_ready = ~pause_frm_f; + next_state = SA_S; + end + end + + SA_S : + begin + if((llc_tx_valid | pause_frm_f) & rs_tx_ready & (data_bytes_w == (MAC_LEN_TYPE_OFFSET-1))) + begin + llc_tx_ready = ~pause_frm_f; + next_state = LEN_TYPE_S; + end + end + + LEN_TYPE_S : + begin + if(rs_tx_ready & (data_bytes_w == (MAC_DATA_OFFSET-1))) + begin + llc_tx_ready = llc_tx_valid & ~pause_frm_f; + + if(pause_frm_f) + begin + next_state = PAUSE_OPCODE_S; + end + else if(llc_tx_valid) + begin + if(data_bffr_w[15:0] == VLAN_TYPE_VALUE) + begin + next_state = VLAN_TAG_S; + end + else + begin + next_state = DATA_S; + end + end + end + end + + PAUSE_OPCODE_S : + begin + if(rs_tx_ready & (data_bytes_w == MAC_PAUSE_TIME_OFFSET-1)) + begin + next_state = PAUSE_TIME_S; + end + end + + PAUSE_TIME_S : + begin + if(rs_tx_ready & (data_bytes_w == MAC_PAUSE_TIME_OFFSET+1)) + begin + next_state = PADDING_S; + end + end + + VLAN_TAG_S : + begin + if(llc_tx_valid & rs_tx_ready & (data_bytes_w == (MAC_VLAN_DATA_OFFSET-1))) + begin + llc_tx_ready = 1\'b1; + next_state = DATA_S; + end + end + + DATA_S : + begin + if(llc_tx_valid & llc_tx_eop & rs_tx_ready) + begin + llc_tx_ready = 1\'b1; + + if(padding_required_c) + begin + next_state = PADDING_S; + end + else if(config_l2_mac_tx_fcs_en) + begin + next_state = FCS_S; + end + else + begin + next_state = IDLE_S; + end + end + end + + PADDING_S : + begin + if(~padding_required_c & rs_tx_ready) + begin + next_state = FCS_S; + end + end + + FCS : + begin + if((data_bytes_w == final_pkt_size_f) & rs_tx_ready)) + begin + next_state = IDLE_S; + end + end + + endcase + end + + //First 32b of CRC data input should be complimented + assign crc_data_c = (data_cntr_f <= 4) ? ~llc_tx_data : + ((fsm_pstate == PADDING_S) ? 0 : llc_tx_data); + + /* FCS Calculation Logic */ + always@(posedge clk, negedge rst_n) + begin + if(~rst_n) + begin + crc_en_f <= 0; + crc_f <= 0; + end + else + begin + if(next_state == FCS_S) + begin + crc_en_f <= state_change_c ? 1\'b0 : crc_en_f; + end + else if(fsm_pstate == PREAMBLE_S) + begin + crc_en_f <= state_change_c & config_l2_mac_tx_fcs_en; + end + + if(fsm_pstate == IDLE_S) + begin + crc_f <= 0; + end + else if(crc_en_f & llc_tx_valid) + begin + crc_f <= nextCRC32_D8(crc_data_c, crc_f); + end + end + end + + //FCS is bit reversed & complimented version of CRC + generate + for(i=0; i<32; i++) + begin + assign fcs_c[i] = ~crc_f[31-i]; + end + endgenerate + + assign fcs_index_c = {(final_pkt_size_f[2:0] - data_cntr_f[2:0]), {$clog2(PKT_DATA_W){1\'b0}}}; + + /* Data framing logic */ + always@(posedge clk, negedge rst_n) + begin + if(~rst_n) + begin + rs_tx_valid <= 0; + rs_tx_sop <= 0; + rs_tx_eop <= 0; + rs_tx_data <= 0; + rs_tx_error <= 0; + end + else + begin + case(fsm_pstate) + + IDLE_S : + begin + rs_tx_valid <= state_change_c ? 1\'b1 : 1\'b0; + rs_tx_sop <= state_change_c ? 1\'b1 : 1\'b0; + rs_tx_eop <= 0; + rs_tx_data <= PREAMBLE_VALUE; + rs_tx_error <= 0; + end + + PREAMBLE_S : + begin + rs_tx_valid <= 1\'b1; + rs_tx_sop <= rs_tx_sop & ~rs_tx_ready; + rs_tx_eop <= 0; + rs_tx_data <= state_change_c ? SFD_VALUE : rs_tx_data; + rs_tx_error <= 0; + end + + SFD_S, + SA_S, + DA_S, + LEN_TYPE_S, + VLAN_TAG_S : + begin + rs_tx_valid <= 1\'b1; + rs_tx_sop <= 0; + rs_tx_eop <= 0; + + if(pause_frm_f) + begin + rs_tx_data <= (data_bytes_w == MAC_LEN_TYPE_OFFSET) ? CTRL_TYPE_VALUE[7:0] : CTRL_TYPE_VALUE[15:8]; + end + else if(state_change_c) + begin + rs_tx_data <= llc_tx_data; + end + else + begin + rs_tx_data <= rs_tx_data; + end + + rs_tx_error <= 0; + end + + PAUSE_OPCODE_S : + begin + rs_tx_valid <= 1\'b1; + rs_tx_sop <= 0; + rs_tx_eop <= 1\'b0; + rs_tx_data <= (data_cntr_f == MAC_CTRL_OPCODE_OFFSET) ? PAUSE_CTRL_OPCODE[7:0] : PAUSE_CTRL_OPCODE[15:8]; + rs_tx_error <= 0; + end + + PAUSE_TIME_S : + begin + rs_tx_valid <= 1\'b1; + rs_tx_sop <= 0; + rs_tx_eop <= 1\'b0; + rs_tx_data <= (data_cntr_f == MAC_PAUSE_TIME_OFFSET) ? + config_l2_mac_tx_pause_time[7:0] : + config_l2_mac_tx_pause_time[15:8]; + rs_tx_error <= 0; + end + + DATA_S : + begin + rs_tx_valid <= 1\'b1; + rs_tx_sop <= 0; + rs_tx_eop <= (next_state == IDLE_S) 1\'b1 : 1\'b0; + rs_tx_data <= state_change_c ? llc_tx_data : rs_tx_data; + rs_tx_error <= 0; + end + + PADDING_S : + begin + rs_tx_valid <= 1\'b1; + rs_tx_sop <= 0; + rs_tx_eop <= 0; + rs_tx_data <= 0; + rs_tx_error <= 0; + end + + FCS : + begin + rs_tx_valid <= state_change_c ? 1\'b0 : 1\'b1; + rs_tx_sop <= 0; + rs_tx_eop <= state_change_c ? 1\'b1 : 1\'b0; + rs_tx_data <= fcs_c[fcs_index_c +: PKT_DATA_W]; + rs_tx_error <= 0; + end + + endcase + end + end + +endmodule // peg_l2_mac_tx_framer + + +/* + -------------------------------------------------------------------------- + + --
+ + + -- + +[28-07-2014 04:18:29 PM][mammenx] Created basic wrapper + +[28-07-2014 12:12:47 PM][mammenx] Added Pause Frame support + +[02-07-2014 12:52:58 AM][mammenx] Initial version + +[28-05-14 20:18:21] [mammenx] Moved log section to bottom of file + + -------------------------------------------------------------------------- +*/ +" +"/* + -------------------------------------------------------------------------- + Pegasus - Copyright (C) 2012 Gregory Matthew James. + + This file is part of Pegasus. + + Pegasus is free; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + Pegasus is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + -------------------------------------------------------------------------- +*/ + +/* + -------------------------------------------------------------------------- + -- Project Code : pegasus + -- Module Name : peg_l2_mac_pause_cntr + -- Author : mammenx + -- Associated modules: + -- Function : This block is a counter used to generate pause + intervals. + -------------------------------------------------------------------------- +*/ + +`timescale 1ns / 10ps + + +module peg_l2_mac_pause_cntr #( + + parameter BPCLK = 64, //Bits per clock cycle + parameter MAC_SPEED = 100000000 //bps + +) + +( + input clk, + input rst_n, + + //Config + input pause_en, + + //Inputs from Parser + input pause_time_valid, + input [15:0] pause_time, + + //Pause Status + output pause_valid + +); + +//----------------------- Global parameters Declarations ------------------ + localparam PAUSE_SCALE_FAC = $clog(512 / BPCLK); + localparam CNTR_W = 16 + PAUSE_SCALE_FAC; + +//----------------------- Input Declarations ------------------------------ + + +//----------------------- Inout Declarations ------------------------------ + + +//----------------------- Output Declarations ----------------------------- + + +//----------------------- Output Register Declaration --------------------- + + +//----------------------- Internal Register Declarations ------------------ + reg [15:0] pause_time_f; + reg [CNTR_W-1:0] pause_cntr_f; + +//----------------------- Internal Wire Declarations ---------------------- + + +//----------------------- Input/Output Registers -------------------------- + +//----------------------- Start of Code ----------------------------------- + + always@(posedge clk, negedge rst_n) + begin + if(~rst_n) + begin + pause_time_f <= 0; + pause_cntr_f <= 0; + end + else + begin + //Register the pause time from parser + pause_time_f <= pause_time_valid ? pause_time : pause_time_f; + + //Counter logic + if(pause_valid) + begin + pause_cntr_f <= 0; + end + else if(pause_en) + begin + pause_cntr_f <= pause_cntr_f + 1'b1; + end + else + begin + pause_cntr_f <= pause_cntr_f; + end + end + end + + //Generate status + assign pause_en = (pause_time_f > pause_cntr_f[CNTR_W-1:PAUSE_SCALE_FAC]) ? 1'b1 : 1'b0; + +endmodule // peg_l2_mac_pause_cntr + + +/* + -------------------------------------------------------------------------- + + --
+ + + -- + +[02-07-2014 12:52:58 AM][mammenx] Initial version + +[28-05-14 20:18:21] [mammenx] Moved log section to bottom of file + + -------------------------------------------------------------------------- +*/ +" +"/* + -------------------------------------------------------------------------- + Pegasus - Copyright (C) 2012 Gregory Matthew James. + + This file is part of Pegasus. + + Pegasus is free; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + Pegasus is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + -------------------------------------------------------------------------- +*/ + +/* + -------------------------------------------------------------------------- + -- Project Code : pegasus + -- Module Name : gry_cntr + -- Author : mammenx + -- Associated modules: + -- Function : A parameterized gray code counter. + -------------------------------------------------------------------------- +*/ + +`timescale 1ns / 10ps + + +module gry_cntr #(WIDTH = 8) + + ( + + //--------------------- Misc Ports (Logic) ----------- + clk, + rst_n, + + rst_val, + + en, + gry_cnt, + gry_cnt_nxt + + + //--------------------- Interfaces -------------------- + + + ); + +//----------------------- Global parameters Declarations ------------------ + + +//----------------------- Input Declarations ------------------------------ + input clk; + input rst_n; + + input [WIDTH-1:0] rst_val; + + input en; + +//----------------------- Inout Declarations ------------------------------ + + +//----------------------- Output Declarations ----------------------------- + output [WIDTH-1:0] gry_cnt; + output [WIDTH-1:0] gry_cnt_nxt; + +//----------------------- Output Register Declaration --------------------- + reg [WIDTH-1:0] gry_cnt; + reg [WIDTH-1:0] gry_cnt_nxt; + + +//----------------------- Internal Register Declarations ------------------ + reg [WIDTH-1:0] bin_cnt_f; + +//----------------------- Internal Wire Declarations ---------------------- + reg [WIDTH-1:0] rst_val2bin_c; + reg [WIDTH-1:0] bin_cnt_nxt_c; + + genvar i; + +//----------------------- Internal Interface Declarations ----------------- + + +//----------------------- FSM Declarations -------------------------------- + + +//----------------------- Start of Code ----------------------------------- + + //Convert to binary + generate + for(i=WIDTH-1; i>=0; i--) + begin : RST_VAL2BIN + assign rst_val2bin_c[i] = ^rst_val[WIDTH-1:i]; + end + endgenerate + + always@(posedge clk, negedge rst_n) + begin + if(~rst_n) + begin + bin_cnt_f <= rst_val2bin_c; + gry_cnt <= rst_val; + end + else + begin + bin_cnt_f <= bin_cnt_nxt_c; + gry_cnt <= gry_cnt_nxt; + end + end + + assign bin_cnt_nxt_c = bin_cnt_f + en; + + assign gry_cnt_nxt = bin_cnt_nxt_c ^ {1'b0,bin_cnt_nxt_c[WIDTH-1:1]}; + +endmodule // gry_cntr + +/* + -------------------------------------------------------------------------- + + --
+ + + -- + +[28-06-2014 03:30:07 PM][mammenx] Moved to Verilog + +[08-06-2014 02:07:20 PM][mammenx] Brought out gry_cnt_nxt port + +[08-06-2014 12:46:15 PM][mammenx] Modified rest load + +[07-06-2014 09:55:48 PM][mammenx] Initial version + +[28-05-14 20:18:21] [mammenx] Moved log section to bottom of file + + -------------------------------------------------------------------------- +*/ +" +"/* + -------------------------------------------------------------------------- + Pegasus - Copyright (C) 2012 Gregory Matthew James. + + This file is part of Pegasus. + + Pegasus is free; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + Pegasus is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + -------------------------------------------------------------------------- +*/ + +/* + -------------------------------------------------------------------------- + -- Project Code : pegasus + -- Package Name : peg_l2_params + -- Author : mammenx + -- Description : This file contains the different parameters + and definitions used in L2 block. + -------------------------------------------------------------------------- +*/ + + parameter PREAMBLE_VALUE = 8\'b01010101; + parameter SFD_VALUE = 8\'b11010101; + parameter VLAN_TYPE_VALUE = 16\'h8100; + parameter CTRL_TYPE_VALUE = 16\'h8808; + parameter PAUSE_CTRL_OPCODE = 16\'h0001; + parameter GLBL_MULTICAST_ADDR = 48\'h01_80_C2_00_00_01; + + parameter RS_TYPE = ""RMII""; + + //Byte offsets for different MAC fields + parameter MAC_PREAMBLE_OFFSET = 0; + parameter MAC_SFD_OFFSET = 7; + parameter MAC_DA_OFFSET = 8; + parameter MAC_SA_OFFSET = 14; + parameter MAC_LEN_TYPE_OFFSET = 20; + parameter MAC_CTRL_OPCODE_OFFSET= 22; + parameter MAC_DATA_OFFSET = 22; + parameter MAC_PAUSE_TIME_OFFSET = 24; + parameter MAC_VLAN_DATA_OFFSET = 26; + + //Parameters for indexing the field buffer + parameter MAC_FIDX_DADDR = 0; + parameter MAC_FIDX_SADDR = 1; + parameter MAC_FIDX_LEN_TYPE = 2; + parameter MAC_FIDX_VLAN_TAG = 3; + parameter MAC_FIDX_CTRL_OPCODE = 4; + parameter MAC_FIDX_PAUSE_TIME = 5; + parameter MAC_FIDX_FCS = 6; + + //Function to calculate CRC + function [31:0] nextCRC32_D8; + + input [7:0] Data; + input [31:0] crc; + reg [7:0] d; + reg [31:0] c; + reg [31:0] newcrc; + begin + d = Data; + c = crc; + + newcrc[0] = d[6] ^ d[0] ^ c[24] ^ c[30]; + newcrc[1] = d[7] ^ d[6] ^ d[1] ^ d[0] ^ c[24] ^ c[25] ^ c[30] ^ c[31]; + newcrc[2] = d[7] ^ d[6] ^ d[2] ^ d[1] ^ d[0] ^ c[24] ^ c[25] ^ c[26] ^ c[30] ^ c[31]; + newcrc[3] = d[7] ^ d[3] ^ d[2] ^ d[1] ^ c[25] ^ c[26] ^ c[27] ^ c[31]; + newcrc[4] = d[6] ^ d[4] ^ d[3] ^ d[2] ^ d[0] ^ c[24] ^ c[26] ^ c[27] ^ c[28] ^ c[30]; + newcrc[5] = d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[24] ^ c[25] ^ c[27] ^ c[28] ^ c[29] ^ c[30] ^ c[31]; + newcrc[6] = d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[25] ^ c[26] ^ c[28] ^ c[29] ^ c[30] ^ c[31]; + newcrc[7] = d[7] ^ d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[24] ^ c[26] ^ c[27] ^ c[29] ^ c[31]; + newcrc[8] = d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[0] ^ c[24] ^ c[25] ^ c[27] ^ c[28]; + newcrc[9] = d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[1] ^ c[25] ^ c[26] ^ c[28] ^ c[29]; + newcrc[10] = d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[2] ^ c[24] ^ c[26] ^ c[27] ^ c[29]; + newcrc[11] = d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[3] ^ c[24] ^ c[25] ^ c[27] ^ c[28]; + newcrc[12] = d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ d[0] ^ c[4] ^ c[24] ^ c[25] ^ c[26] ^ c[28] ^ c[29] ^ c[30]; + newcrc[13] = d[7] ^ d[6] ^ d[5] ^ d[3] ^ d[2] ^ d[1] ^ c[5] ^ c[25] ^ c[26] ^ c[27] ^ c[29] ^ c[30] ^ c[31]; + newcrc[14] = d[7] ^ d[6] ^ d[4] ^ d[3] ^ d[2] ^ c[6] ^ c[26] ^ c[27] ^ c[28] ^ c[30] ^ c[31]; + newcrc[15] = d[7] ^ d[5] ^ d[4] ^ d[3] ^ c[7] ^ c[27] ^ c[28] ^ c[29] ^ c[31]; + newcrc[16] = d[5] ^ d[4] ^ d[0] ^ c[8] ^ c[24] ^ c[28] ^ c[29]; + newcrc[17] = d[6] ^ d[5] ^ d[1] ^ c[9] ^ c[25] ^ c[29] ^ c[30]; + newcrc[18] = d[7] ^ d[6] ^ d[2] ^ c[10] ^ c[26] ^ c[30] ^ c[31]; + newcrc[19] = d[7] ^ d[3] ^ c[11] ^ c[27] ^ c[31]; + newcrc[20] = d[4] ^ c[12] ^ c[28]; + newcrc[21] = d[5] ^ c[13] ^ c[29]; + newcrc[22] = d[0] ^ c[14] ^ c[24]; + newcrc[23] = d[6] ^ d[1] ^ d[0] ^ c[15] ^ c[24] ^ c[25] ^ c[30]; + newcrc[24] = d[7] ^ d[2] ^ d[1] ^ c[16] ^ c[25] ^ c[26] ^ c[31]; + newcrc[25] = d[3] ^ d[2] ^ c[17] ^ c[26] ^ c[27]; + newcrc[26] = d[6] ^ d[4] ^ d[3] ^ d[0] ^ c[18] ^ c[24] ^ c[27] ^ c[28] ^ c[30]; + newcrc[27] = d[7] ^ d[5] ^ d[4] ^ d[1] ^ c[19] ^ c[25] ^ c[28] ^ c[29] ^ c[31]; + newcrc[28] = d[6] ^ d[5] ^ d[2] ^ c[20] ^ c[26] ^ c[29] ^ c[30]; + newcrc[29] = d[7] ^ d[6] ^ d[3] ^ c[21] ^ c[27] ^ c[30] ^ c[31]; + newcrc[30] = d[7] ^ d[4] ^ c[22] ^ c[28] ^ c[31]; + newcrc[31] = d[5] ^ c[23] ^ c[29]; + nextCRC32_D8 = newcrc; + end + endfunction + +/* + -------------------------------------------------------------------------- + + --
+ + + -- + +[28-07-2014 12:12:47 PM][mammenx] Added Pause Frame support + +[02-07-2014 12:53:29 AM][mammenx] Added misc MAC parameters & CRC function + +[28-06-2014 04:43:57 PM][mammenx] Removed System Verilog + +[24-06-2014 08:01:48 PM][mammenx] Added CRC function + +[18-06-2014 08:39:55 PM][mammenx] Added VLAN Tag & MAC Header structure types + +[18-06-2014 07:27:24 PM][mammenx] Initial Commit + + -------------------------------------------------------------------------- +*/ +" +"/* + -------------------------------------------------------------------------- + Pegasus - Copyright (C) 2012 Gregory Matthew James. + + This file is part of Pegasus. + + Pegasus is free; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + Pegasus is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + -------------------------------------------------------------------------- +*/ + +/* + -------------------------------------------------------------------------- + -- Project Code : pegasus + -- Module Name : peg_l2_mac_rx_parser + -- Author : mammenx + -- Associated modules: + -- Function : This module parses an ingress packet stream to + extract the different fields in an L2 frame. This + has an 8b pipeline that is intended for upto 1Gbps + speeds @ 125MHz clock. + -------------------------------------------------------------------------- +*/ + +`timescale 1ns / 10ps + + +module peg_l2_mac_rx_parser #( + parameter PKT_DATA_W = 8, + parameter PKT_SIZE_W = 16, + parameter NUM_FIELDS = 8, + parameter BFFR_SIZE = 48 +) + +( + input clk, + input rst_n, + + //Config interface + input config_l2_mac_rx_en, + input config_l2_mac_rx_fcs_en, + input config_l2_mac_rx_strip_preamble_sfd, + input config_l2_mac_rx_strip_fcs, + + //Status interface + output [3:0] l2_mac_rx_fsm_state, + + //Interface to RX Filter & Pause Gen + output [NUM_FIELDS-1:0] rx_field_valid_vec, + output [BFFR_SIZE-1:0] rx_bffr, + + //Interface to FCS Calculator + output rx_fcs_rst, + output rx_fcs_calc_en, + output [PKT_DATA_W-1:0] rx_fcs_calc_data, + + //RS packet interface + input rs_rx_valid, + input rs_rx_sop, + input rs_rx_eop, + input [PKT_DATA_W-1:0] rs_rx_data, + output rs_rx_ready, + input rs_rx_error, + + //LLC packet interface + output llc_rx_valid, + output llc_rx_sop, + output llc_rx_eop, + output [PKT_DATA_W-1:0] llc_rx_data, + input llc_rx_ready, + output llc_rx_error + +); + +//----------------------- Global parameters Declarations ------------------ + `include ""peg_l2_params.v"" + + parameter PKT_SIZE_INC_VAL = PKT_DATA_W / 8; + +//----------------------- Input Declarations ------------------------------ + + +//----------------------- Inout Declarations ------------------------------ + + +//----------------------- Output Declarations ----------------------------- + + +//----------------------- Output Register Declaration --------------------- + reg [NUM_FIELDS-1:0] rx_field_valid_vec; + reg [BFFR_SIZE-1:0] rx_bffr; + + reg rx_fcs_rst; + reg rx_fcs_calc_en; + + reg llc_rx_valid; + reg llc_rx_sop; + reg llc_rx_eop; + +//----------------------- Internal Register Declarations ------------------ + reg [15:0] data_cntr_f; + reg vlan_frm_f; + reg ctrl_frm_f; + reg pause_frm_f; + reg [2:0] fcs_en_delay_vec_f; + reg fcs_en_nxt_c; + reg [2:0] llc_rx_valid_del_vec_f; + reg llc_rx_valid_nxt_c; + reg [2:0] llc_rx_sop_del_vec_f; + reg llc_rx_sop_nxt_c; + +//----------------------- Internal Wire Declarations ---------------------- + wire rx_data_valid_c; + wire [15:0] data_bytes_w; + wire [BFFR_SIZE-1:0] bffr_nxt_w; + + wire preamble_valid_c; + wire sfd_valid_c; + + +//----------------------- FSM Parameters -------------------------------------- +//only for FSM state vector representation +parameter [3:0] // synopsys enum fsm_pstate +IDLE_S = 4\'d0, +PREAMBLE_S = 4\'d1, +SFD_S = 4\'d2, +DA_S = 4\'d3, +SA_S = 4\'d4, +LEN_TYPE_S = 4\'d5, +VLAN_TAG_S = 4\'d6, +DATA_S = 4\'d7, +FCS_S = 4\'d8; + +//----------------------- FSM Register Declarations ------------------ +reg [3:0] // synopsys enum fsm_pstate +fsm_pstate, next_state; + +//----------------------- FSM String Declarations ------------------ +//synthesis translate_off +reg [8*16:0] state_name;//""state name"" is user defined +//synthesis translate_on + +//----------------------- FSM Debugging Logic Declarations ------------------ +//synthesis translate_off +always @ (fsm_pstate) +begin +case (fsm_pstate) + +IDLE_S : state_name = ""IDLE_S""; + +PREAMBLE_S : state_name = ""PREAMBLE_S""; + +SFD_S : state_name = ""SFD_S""; + +DA_S : state_name = ""DA_S""; + +SA_S : state_name = ""SA_S""; + +LEN_TYPE_S : state_name = ""LEN_TYPE_S""; + +VLAN_TAG_S : state_name = ""VLAN_TAG_S""; + +DATA_S : state_name = ""DATA_S""; + +FCS_S : state_name = ""FCS_S""; + +default : state_name = ""INVALID STATE!""; +endcase +end +//synthesis translate_on + +//----------------------- Input/Output Registers -------------------------- + +//----------------------- Start of Code ----------------------------------- + + always@(posedge clk, negedge rst_n) + begin + if(~rst_n) + begin + fsm_pstate <= IDLE_S; + data_cntr_f <= 0; + vlan_frm_f <= 0; + ctrl_frm_f <= 0; + pause_frm_f <= 0; + fcs_en_delay_vec_f <= 0; + llc_rx_valid_del_vec_f <= 0; + llc_rx_sop_del_vec_f <= 0; + + rx_fcs_rst <= 0; + rx_fcs_calc_en <= 0; + + llc_rx_valid <= 0; + llc_rx_sop <= 0; + llc_rx_eop <= 0; + end + else + begin + fsm_pstate <= next_state; + + if(fsm_pstate == IDLE_S) + begin + fcs_en_delay_vec_f <= 0; + llc_rx_valid_del_vec_f<= 0; + llc_rx_sop_del_vec_f <= 0; + end + else if(fsm_pstate == FCS_S) + begin + fcs_en_delay_vec_f <= 0; + llc_rx_sop_del_vec_f <= 0; + llc_rx_valid_del_vec_f<= {llc_rx_valid_del_vec_f[1:0],1\'b0}; + end + else + begin + fcs_en_delay_vec_f <= rx_data_valid_c ? {fcs_en_delay_vec_f[1:0], fcs_en_nxt_c} : fcs_en_delay_vec_f; + llc_rx_valid_del_vec_f<= rx_data_valid_c ? {llc_rx_valid_del_vec_f[1:0],llc_rx_valid_nxt_c} : llc_rx_valid_del_vec_f; + llc_rx_sop_del_vec_f <= rx_data_valid_c ? {llc_rx_sop_del_vec_f[1:0],llc_rx_sop_nxt_c} : llc_rx_sop_del_vec_f; + end + + rx_fcs_calc_en <= rx_data_valid_c & fcs_en_delay_vec_f[2] & (fsm_pstate != IDLE_S); + + rx_fcs_rst <= (fsm_pstate == SFD_S) ? 1\'b1 : 1\'b0; + + llc_rx_valid <= (fsm_pstate == FCS_S) ? llc_rx_valid_del_vec_f[2] : rx_data_valid_c & llc_rx_valid_del_vec_f[2]; + + llc_rx_sop <= rx_data_valid_c & llc_rx_valid_del_vec_f[2] & (fsm_pstate != IDLE_S); + + if((fsm_pstate == DATA_S) & rx_data_valid_c & rs_rx_eop) + begin + llc_rx_eop <= config_l2_mac_rx_strip_fcs; + end + else if(fsm_pstate == FCS_S) + begin + llc_rx_eop <= (llc_rx_valid_del_vec_f == 3\'b100) ? 1\'b1 : 1\'b0; + end + else + begin + llc_rx_eop <= 1\'b0; + end + + if(fsm_pstate == IDLE_S) + begin + data_cntr_f <= 0; + end + else if(rx_data_valid_c) + begin + data_cntr_f <= data_cntr_f + PKT_SIZE_INC_VAL; + end + + if(fsm_pstate == IDLE_S) + begin + vlan_frm_f <= 0; + end + else if(data_bytes_w == MAC_DATA_OFFSET-1) + begin + vlan_frm_f <= (bffr_nxt_w[15:0] == VLAN_TYPE_VALUE) ? rx_data_valid_c : 1\'b0; + end + + if(fsm_pstate == IDLE_S) + begin + ctrl_frm_f <= 0; + end + else if(data_bytes_w == MAC_DATA_OFFSET-1) + begin + ctrl_frm_f <= (bffr_nxt_w[15:0] == CTRL_TYPE_VALUE) ? rx_data_valid_c : 1\'b0; + end + + if(fsm_pstate == IDLE_S) + begin + pause_frm_f <= 0; + end + else if(data_bytes_w == MAC_PAUSE_TIME_OFFSET+1) + begin + pause_frm_f <= (bffr_nxt_w[15:0] == PAUSE_CTRL_OPCODE) ? rx_data_valid_c & ctrl_frm_f : 1\'b0; + end + end + end + + assign rx_fcs_calc_data = (data_bytes_w <= 4) ? ~rx_bffr[(2*PKT_DATA_W) +: PKT_DATA_W] + : rx_bffr[(2*PKT_DATA_W) +: PKT_DATA_W]; + + assign rx_data_valid_c = rs_rx_valid & rs_rx_ready; + assign rs_rx_ready = 1\'b1; + + assign data_bytes_w = {{(PKT_SIZE_INC_VAL-1){1\'b0}},data_cntr_f[15:PKT_SIZE_INC_VAL-1]}; + + always@(*) + begin + next_state = fsm_pstate; + fcs_en_nxt_c = 1\'b0; + llc_rx_valid_nxt_c = 1\'b0; + llc_rx_sop_nxt_c = 1\'b0; + + case(fsm_pstate) + + IDLE_S : + begin + if(rx_data_valid_c & rs_rx_sop & config_l2_mac_rx_en) + begin + llc_rx_valid_nxt_c = ~config_l2_mac_rx_strip_preamble_sfd; + llc_rx_sop_nxt_c = ~config_l2_mac_rx_strip_preamble_sfd; + next_state = PREAMBLE_S; + end + end + + PREAMBLE_S : + begin + llc_rx_valid_nxt_c = ~config_l2_mac_rx_strip_preamble_sfd; + + if(rx_data_valid_c & (data_bytes_w == MAC_SFD_OFFSET-1)) + begin + next_state = preamble_valid_c ? SFD_S : IDLE_S; + end + end + + SFD_S : + begin + llc_rx_valid_nxt_c = ~config_l2_mac_rx_strip_preamble_sfd; + + if(rx_data_valid_c & (data_bytes_w == MAC_SA_OFFSET-1)) + begin + llc_rx_sop_nxt_c = config_l2_mac_rx_strip_preamble_sfd; + next_state = sfd_valid_c ? DA_S : IDLE_S; + end + end + + DA_S : + begin + llc_rx_valid_nxt_c = 1\'b1; + fcs_en_nxt_c = config_l2_mac_rx_fcs_en; + + if(rx_data_valid_c & (data_bytes_w == MAC_SA_OFFSET-1)) + begin + next_state = SA_S; + end + end + + SA_S : + begin + llc_rx_valid_nxt_c = 1\'b1; + fcs_en_nxt_c = config_l2_mac_rx_fcs_en; + + if(rx_data_valid_c & (data_bytes_w == MAC_LEN_TYPE_OFFSET-1)) + begin + next_state = LEN_TYPE_S; + end + end + + LEN_TYPE_S : + begin + llc_rx_valid_nxt_c = 1\'b1; + fcs_en_nxt_c = config_l2_mac_rx_fcs_en; + + if(rx_data_valid_c & (data_bytes_w == MAC_DATA_OFFSET)) + begin + next_state = (bffr_nxt_w == VLAN_TYPE_VALUE) ? VLAN_TAG_S : DATA_S; + end + end + + VLAN_TAG_S : + begin + llc_rx_valid_nxt_c = 1\'b1; + fcs_en_nxt_c = config_l2_mac_rx_fcs_en; + + if(rx_data_valid_c & (data_bytes_w == MAC_VLAN_DATA_OFFSET)) + begin + next_state = DATA_S; + end + end + + DATA_S : + begin + llc_rx_valid_nxt_c = 1\'b1; + fcs_en_nxt_c = config_l2_mac_rx_fcs_en; + + if(rx_data_valid_c & rs_rx_eop) + begin + next_state = config_l2_mac_rx_strip_fcs ? IDLE_S : FCS_S; + end + end + + FCS_S : + begin + if(llc_rx_valid_del_vec_f == 3\'b000) + begin + next_state = IDLE_S; + end + end + + endcase + end + + assign preamble_valid_c = (bffr_nxt_w[55:0] == {7{PREAMBLE_VALUE}}) ? 1\'b1 : 1\'b0; + assign sfd_valid_c = (bffr_nxt_w[7:0] == SFD_VALUE) ? 1\'b1 : 1\'b0; + + /* Output Buffer logic */ + always@(posedge clk, negedge rst_n) + begin + if(~rst_n) + begin + rx_field_valid_vec <= 0; + rx_bffr <= 0; + end + else + begin + rx_bffr <= rx_data_valid_c ? bffr_nxt_w : rx_bffr; + + rx_field_valid_vec[MAC_FIDX_DADDR] <= (data_bytes_w == MAC_SA_OFFSET-1) ? rx_data_valid_c : 1\'b0; + rx_field_valid_vec[MAC_FIDX_SADDR] <= (data_bytes_w == MAC_LEN_TYPE_OFFSET-1) ? rx_data_valid_c : 1\'b0; + rx_field_valid_vec[MAC_FIDX_LEN_TYPE] <= (data_bytes_w == MAC_DATA_OFFSET-1) ? rx_data_valid_c : 1\'b0; + rx_field_valid_vec[MAC_FIDX_VLAN_TAG] <= (data_bytes_w == MAC_VLAN_DATA_OFFSET-1) ? rx_data_valid_c & vlan_frm_f : 1\'b0; + rx_field_valid_vec[MAC_FIDX_CTRL_OPCODE] <= (data_bytes_w == MAC_PAUSE_TIME_OFFSET-1) ? rx_data_valid_c & ctrl_frm_f : 1\'b0; + rx_field_valid_vec[MAC_FIDX_PAUSE_TIME] <= (data_bytes_w == MAC_PAUSE_TIME_OFFSET+1) ? rx_data_valid_c & pause_frm_f : 1\'b0; + rx_field_valid_vec[MAC_FIDX_FCS] <= (fsm_pstate == DATA_S) ? rx_data_valid_c & rs_rx_eop : 1\'b0; + end + end + + assign bffr_nxt_w = {rx_bffr[BFFR_SIZE-PKT_DATA_W-1:0],rs_rx_data}; + +endmodule // peg_l2_mac_rx_parser + + +/* + -------------------------------------------------------------------------- + + --
+ + + -- + +[28-07-2014 04:18:29 PM][mammenx] Created basic wrapper + +[28-07-2014 12:13:48 PM][mammenx] Initial Commit + +[28-05-14 20:18:21] [mammenx] Moved log section to bottom of file + + -------------------------------------------------------------------------- +*/ +" +"/* + -------------------------------------------------------------------------- + Pegasus - Copyright (C) 2012 Gregory Matthew James. + + This file is part of Pegasus. + + Pegasus is free; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + Pegasus is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + -------------------------------------------------------------------------- +*/ + +/* + -------------------------------------------------------------------------- + -- Project Code : pegasus + -- Module Name : pkt_ff_rptr + -- Author : mammenx + -- Associated modules: + -- Function : This module maintains logic for updating the read + pointer. + -------------------------------------------------------------------------- +*/ + +`timescale 1ns / 10ps + + +module pkt_ff_rptr #(PTR_W = 8) +( + + //--------------------- Misc Ports (Logic) ----------- + clk, + rst_n, + + rd_en, + + rptr + + //--------------------- Interfaces -------------------- + + +); + +//----------------------- Global parameters Declarations ------------------ + + +//----------------------- Input Declarations ------------------------------ + input clk; + input rst_n; + + input rd_en; + +//----------------------- Inout Declarations ------------------------------ + + +//----------------------- Output Declarations ----------------------------- + output [PTR_W-1:0] rptr; + +//----------------------- Output Register Declaration --------------------- + + +//----------------------- Internal Register Declarations ------------------ + + +//----------------------- Internal Wire Declarations ---------------------- + + +//----------------------- Internal Interface Declarations ----------------- + + +//----------------------- FSM Declarations -------------------------------- + + +//----------------------- Start of Code ----------------------------------- + + //Implement rptr as a gray counter + gry_cntr u_rptr_gry_cntr + ( + + .clk (clk), + .rst_n (rst_n), + + .rst_val ({PTR_W{1'b0}}), + + .en (rd_en), + .gry_cnt (), + .gry_cnt_nxt (rptr) + + ); + + defparam u_rptr_gry_cntr.WIDTH = PTR_W; + + +endmodule // pkt_ff_rptr + +/* + -------------------------------------------------------------------------- + + --
+ + + -- + +[28-06-2014 03:30:57 PM][mammenx] Moved to Verilog + +[08-06-2014 02:14:35 PM][mammenx] Initial Commit + +[28-05-14 20:18:21] [mammenx] Moved log section to bottom of file + + -------------------------------------------------------------------------- +*/ +" +"/* + -------------------------------------------------------------------------- + Pegasus - Copyright (C) 2012 Gregory Matthew James. + + This file is part of Pegasus. + + Pegasus is free; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + Pegasus is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + -------------------------------------------------------------------------- +*/ + +/* + -------------------------------------------------------------------------- + -- Project Code : pegasus + -- Module Name : + -- Author : mammenx + -- Associated modules: + -- Function : + -------------------------------------------------------------------------- +*/ + +`timescale 1ns / 10ps + + +module ( + + ); + +//----------------------- Global parameters Declarations ------------------ + + +//----------------------- Input Declarations ------------------------------ + + +//----------------------- Inout Declarations ------------------------------ + + +//----------------------- Output Declarations ----------------------------- + + +//----------------------- Output Register Declaration --------------------- + + +//----------------------- Internal Register Declarations ------------------ + + +//----------------------- Internal Wire Declarations ---------------------- + + +//----------------------- FSM Parameters -------------------------------------- +//only for FSM state vector representation +parameter [?:0] // synopsys enum fsm_pstate +IDLE = , + +//----------------------- FSM Register Declarations ------------------ +reg [?:0] // synopsys enum fsm_pstate +fsm_pstate, next_state; + +//----------------------- FSM String Declarations ------------------ +//synthesis translate_off +reg [8*?:0] state_name;//""state name"" is user defined +//synthesis translate_on + +//----------------------- FSM Debugging Logic Declarations ------------------ +//synthesis translate_off +always @ (fsm_pstate) +begin +case (fsm_pstate) + + : state_name = ""IDLE""; + + : state_name = ""state2""; +. +. +. + : state_name = ""default""; +endcase +end +//synthesis translate_on + +//----------------------- Input/Output Registers -------------------------- + +//----------------------- Start of Code ----------------------------------- +//code should be <=200 lines + +/* comments for assign statements +*/ + +//assign statements + +/* comments for combinatory logic + Asynchronous part of FSM +*/ + + +/* comments for sequential logic +*/ +//; + +endmodule // + + +/* + -------------------------------------------------------------------------- + + --
+ + + -- + +[28-05-14 20:18:21] [mammenx] Moved log section to bottom of file + + -------------------------------------------------------------------------- +*/ +" +"import time +import http + +fn main() { + data := http.get('https://vlang.io/utc_now') or { + println('failed to fetch data from the server') + } + t := time.unix(data) + println(t.clean()) // 27 Jun 2019 14:32 +}" +"/* +Copyright (C) 2019-2021, Gisselquist Technology, LLC + +This program is free software (firmware): you can redistribute it and/or +modify it under the terms of the GNU General Public License as published +by the Free Software Foundation, either version 3 of the License, or (at +your option) any later version. + +This program is distributed in the hope that it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License along +with this program. (It's in the $(ROOT)/doc directory. Run make with no +target there if the PDF file isn't present.) If not, see + for a copy. + +License: GPL, v3, as defined and found on www.gnu.org, +http://www.gnu.org/licenses/gpl.html +*/ +`default_nettype none +module skidbuffer #( + parameter [0:0] OPT_LOWPOWER = 0, + parameter [0:0] OPT_OUTREG = 1, + parameter [0:0] OPT_PASSTHROUGH = 0, + parameter DW = 8 +) ( + input wire i_clk, + i_reset, + input wire i_valid, + output reg o_ready, + input wire [DW-1:0] i_data, + output reg o_valid, + input wire i_ready, + output reg [DW-1:0] o_data +); + reg [DW-1:0] r_data; + generate + if (OPT_PASSTHROUGH) begin : PASSTHROUGH + always @(*) o_ready = i_ready; + always @(*) o_valid = i_valid; + always @(*) + if (!i_valid && OPT_LOWPOWER) o_data = 0; + else o_data = i_data; + always @(*) r_data = 0; + end else begin : LOGIC + reg r_valid; + initial r_valid = 0; + always @(posedge i_clk) + if (i_reset) r_valid <= 0; + else if ((i_valid && o_ready) && (o_valid && !i_ready)) r_valid <= 1; + else if (i_ready) r_valid <= 0; + initial r_data = 0; + always @(posedge i_clk) + if (OPT_LOWPOWER && i_reset) r_data <= 0; + else if (OPT_LOWPOWER && (!o_valid || i_ready)) r_data <= 0; + else if ((!OPT_LOWPOWER || !OPT_OUTREG || i_valid) && o_ready) r_data <= i_data; + always @(*) o_ready = !r_valid; + if (!OPT_OUTREG) begin + always @(*) o_valid = !i_reset && (i_valid || r_valid); + always @(*) + if (r_valid) o_data = r_data; + else if (!OPT_LOWPOWER || i_valid) o_data = i_data; + else o_data = 0; + end else begin : REG_OUTPUT + initial o_valid = 0; + always @(posedge i_clk) + if (i_reset) o_valid <= 0; + else if (!o_valid || i_ready) o_valid <= (i_valid || r_valid); + initial o_data = 0; + always @(posedge i_clk) + if (OPT_LOWPOWER && i_reset) o_data <= 0; + else if (!o_valid || i_ready) begin + if (r_valid) o_data <= r_data; + else if (!OPT_LOWPOWER || i_valid) o_data <= i_data; + else o_data <= 0; + end + end + end + endgenerate +`ifdef FORMAL +`ifdef VERIFIC + `define FORMAL_VERIFIC +`endif +`endif +`ifdef FORMAL_VERIFIC + property RESET_CLEARS_IVALID; + @(posedge i_clk) i_reset |=> !i_valid; + endproperty + property IDATA_HELD_WHEN_NOT_READY; + @(posedge i_clk) disable iff (i_reset) i_valid && !o_ready |=> i_valid && $stable( + i_data + ); + endproperty +`ifdef SKIDBUFFER + assume property (IDATA_HELD_WHEN_NOT_READY); +`else + assert property (IDATA_HELD_WHEN_NOT_READY); +`endif + generate + if (!OPT_PASSTHROUGH) begin + assert property (@(posedge i_clk) OPT_OUTREG && i_reset |=> o_ready && !o_valid); + assert property (@(posedge i_clk) !OPT_OUTREG && i_reset |-> !o_valid); + assert property (@(posedge i_clk) +disable iff (i_reset) +o_valid && !i_ready +|=> (o_valid && $stable( + o_data + ))); + assert property (@(posedge i_clk) +disable iff (i_reset) +(i_valid && o_ready +&& (!OPT_OUTREG || o_valid) && !i_ready) +|=> (!o_ready && r_data == $past( + i_data + ))); + if (!OPT_OUTREG) begin + assert property (@(posedge i_clk) disable iff (i_reset) i_ready |=> (o_valid == i_valid)); + end else begin + assert property (@(posedge i_clk) disable iff (i_reset) i_valid && o_ready |=> o_valid); + assert property (@(posedge i_clk) +disable iff (i_reset) +!i_valid && o_ready && i_ready |=> !o_valid); + end + assert property (@(posedge i_clk) !o_ready && i_ready |=> o_ready); + if (OPT_LOWPOWER) begin + assert property (@(posedge i_clk) (OPT_OUTREG || !i_reset) && !o_valid |-> o_data == 0); + assert property (@(posedge i_clk) o_ready |-> r_data == 0); + end +`ifdef SKIDBUFFER + reg f_changed_data; + cover property (@(posedge i_clk) +disable iff (i_reset) +(!o_valid && !i_valid) +##1 i_valid && i_ready [*3] +##1 i_valid && !i_ready +##1 i_valid && i_ready [*2] +##1 i_valid && !i_ready [*2] +##1 i_valid && i_ready [*3] +##1 o_valid && i_ready [*0:5] +##1 (!o_valid && !i_valid && f_changed_data)); + initial f_changed_data = 0; + always @(posedge i_clk) + if (i_reset) f_changed_data <= 1; + else if (i_valid && $past(!i_valid || o_ready)) begin + if (i_data != $past(i_data + 1)) f_changed_data <= 0; + end else if (!i_valid && i_data != 0) f_changed_data <= 0; +`endif + end + endgenerate +`endif +endmodule +`ifndef YOSYS +`default_nettype wire +`endif +" +"/* +Copyright (C) 2015-2021, Gisselquist Technology, LLC + +This program is free software (firmware): you can redistribute it and/or +modify it under the terms of the GNU General Public License as published +by the Free Software Foundation, either version 3 of the License, or (at +your option) any later version. + +This program is distributed in the hope that it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License along +with this program. (It's in the $(ROOT)/doc directory. Run make with no +target there if the PDF file isn't present.) If not, see + for a copy. + +License: GPL, v3, as defined and found on www.gnu.org, +http://www.gnu.org/licenses/gpl.html +*/ +`default_nettype none +module rxuart #( + parameter [30:0] INITIAL_SETUP = 31'd868, + parameter [3:0] RXU_BIT_ZERO = 4'h0, + RXU_BIT_ONE = 4'h1, + RXU_BIT_TWO = 4'h2, + RXU_BIT_THREE = 4'h3, + RXU_BIT_SEVEN = 4'h7, + RXU_PARITY = 4'h8, + RXU_STOP = 4'h9, + RXU_SECOND_STOP = 4'ha, + RXU_BREAK = 4'hd, + RXU_RESET_IDLE = 4'he, + RXU_IDLE = 4'hf +) ( + input wire i_clk, + i_reset, + input wire [30:0] i_setup, + input wire i_uart_rx, + output reg o_wr, + output reg [7:0] o_data, + output reg o_break, + output reg o_parity_err, + o_frame_err, + output wire o_ck_uart +); + wire [27:0] clocks_per_baud, break_condition, half_baud; + wire [1:0] data_bits; + wire use_parity, parity_even, dblstop, fixd_parity; + reg [29:0] r_setup; + reg [3:0] state; + reg [27:0] baud_counter; + reg zero_baud_counter; + reg q_uart, qq_uart, ck_uart; + reg [27:0] chg_counter; + reg line_synch; + reg half_baud_time; + reg [7:0] data_reg; + reg calc_parity; + reg pre_wr; + assign clocks_per_baud = {4'h0, r_setup[23:0]}; + assign data_bits = r_setup[29:28]; + assign dblstop = r_setup[27]; + assign use_parity = r_setup[26]; + assign fixd_parity = r_setup[25]; + assign parity_even = r_setup[24]; + assign break_condition = {r_setup[23:0], 4'h0}; + assign half_baud = {5'h00, r_setup[23:1]} - 28'h1; + initial q_uart = 1'b0; + initial qq_uart = 1'b0; + initial ck_uart = 1'b0; + always @(posedge i_clk) begin + q_uart <= i_uart_rx; + qq_uart <= q_uart; + ck_uart <= qq_uart; + end + assign o_ck_uart = ck_uart; + initial chg_counter = 28'h00; + always @(posedge i_clk) + if (i_reset) chg_counter <= 28'h00; + else if (qq_uart != ck_uart) chg_counter <= 28'h00; + else if (chg_counter < break_condition) chg_counter <= chg_counter + 1; + initial o_break = 1'b0; + always @(posedge i_clk) o_break <= ((chg_counter >= break_condition) && (~ck_uart)) ? 1'b1 : 1'b0; + initial line_synch = 1'b0; + always @(posedge i_clk) line_synch <= ((chg_counter >= break_condition) && (ck_uart)); + initial half_baud_time = 0; + always @(posedge i_clk) half_baud_time <= (~ck_uart) && (chg_counter >= half_baud); + initial r_setup = INITIAL_SETUP[29:0]; + always @(posedge i_clk) if (state >= RXU_RESET_IDLE) r_setup <= i_setup[29:0]; + initial state = RXU_RESET_IDLE; + always @(posedge i_clk) + if (i_reset) state <= RXU_RESET_IDLE; + else if (state == RXU_RESET_IDLE) begin + if (line_synch) state <= RXU_IDLE; + else state <= RXU_RESET_IDLE; + end else if (o_break) begin + state <= RXU_BREAK; + end else if (state == RXU_BREAK) begin + if (ck_uart) state <= RXU_IDLE; + else state <= RXU_BREAK; + end else if (state == RXU_IDLE) begin + if ((~ck_uart) && (half_baud_time)) begin + case (data_bits) + 2'b00: state <= RXU_BIT_ZERO; + 2'b01: state <= RXU_BIT_ONE; + 2'b10: state <= RXU_BIT_TWO; + 2'b11: state <= RXU_BIT_THREE; + endcase + end else state <= RXU_IDLE; + end else if (zero_baud_counter) begin + if (state < RXU_BIT_SEVEN) state <= state + 1; + else if (state == RXU_BIT_SEVEN) state <= (use_parity) ? RXU_PARITY : RXU_STOP; + else if (state == RXU_PARITY) state <= RXU_STOP; + else if (state == RXU_STOP) begin + if (~ck_uart) state <= RXU_RESET_IDLE; + else if (dblstop) state <= RXU_SECOND_STOP; + else state <= RXU_IDLE; + end else begin + if (~ck_uart) state <= RXU_RESET_IDLE; + else state <= RXU_IDLE; + end + end + always @(posedge i_clk) + if ((zero_baud_counter) && (state != RXU_PARITY)) + data_reg <= {ck_uart, data_reg[7:1]}; + always @(posedge i_clk) + if (state == RXU_IDLE) calc_parity <= 0; + else if (zero_baud_counter) calc_parity <= calc_parity ^ ck_uart; + initial o_parity_err = 1'b0; + always @(posedge i_clk) + if ((zero_baud_counter) && (state == RXU_PARITY)) begin + if (fixd_parity) o_parity_err <= (ck_uart ^ parity_even); + else if (parity_even) o_parity_err <= (calc_parity != ck_uart); + else o_parity_err <= (calc_parity == ck_uart); + end else if (state >= RXU_BREAK) o_parity_err <= 1'b0; + initial o_frame_err = 1'b0; + always @(posedge i_clk) + if ((zero_baud_counter) && ((state == RXU_STOP) || (state == RXU_SECOND_STOP))) + o_frame_err <= (o_frame_err) || (~ck_uart); + else if ((zero_baud_counter) || (state >= RXU_BREAK)) o_frame_err <= 1'b0; + initial o_data = 8'h00; + initial pre_wr = 1'b0; + always @(posedge i_clk) + if (i_reset) begin + pre_wr <= 1'b0; + o_data <= 8'h00; + end else if ((zero_baud_counter) && (state == RXU_STOP)) begin + pre_wr <= 1'b1; + case (data_bits) + 2'b00: o_data <= data_reg; + 2'b01: o_data <= {1'b0, data_reg[7:1]}; + 2'b10: o_data <= {2'b0, data_reg[7:2]}; + 2'b11: o_data <= {3'b0, data_reg[7:3]}; + endcase + end else if ((zero_baud_counter) || (state == RXU_IDLE)) pre_wr <= 1'b0; + initial o_wr = 1'b0; + always @(posedge i_clk) + if ((zero_baud_counter) || (state == RXU_IDLE)) o_wr <= (pre_wr) && (!i_reset); + else o_wr <= 1'b0; + always @(posedge i_clk) + if (i_reset) baud_counter <= clocks_per_baud - 28'h01; + else if (zero_baud_counter) baud_counter <= clocks_per_baud - 28'h01; + else + case (state) + RXU_RESET_IDLE: baud_counter <= clocks_per_baud - 28'h01; + RXU_BREAK: baud_counter <= clocks_per_baud - 28'h01; + RXU_IDLE: baud_counter <= clocks_per_baud - 28'h01; + default: baud_counter <= baud_counter - 28'h01; + endcase + initial zero_baud_counter = 1'b0; + always @(posedge i_clk) + if (state == RXU_IDLE) zero_baud_counter <= 1'b0; + else zero_baud_counter <= (baud_counter == 28'h01); +endmodule +" +"/* +Copyright (C) 2015-2021, Gisselquist Technology, LLC + +This program is free software (firmware): you can redistribute it and/or +modify it under the terms of the GNU General Public License as published +by the Free Software Foundation, either version 3 of the License, or (at +your option) any later version. + +This program is distributed in the hope that it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License along +with this program. (It's in the $(ROOT)/doc directory. Run make with no +target there if the PDF file isn't present.) If not, see + for a copy. + +License: GPL, v3, as defined and found on www.gnu.org, +http://www.gnu.org/licenses/gpl.html +*/ +`default_nettype none +module txuart #( + parameter [30:0] INITIAL_SETUP = 31'd868, + parameter [3:0] TXU_BIT_ZERO = 4'h0, + parameter [3:0] TXU_BIT_ONE = 4'h1, + parameter [3:0] TXU_BIT_TWO = 4'h2, + parameter [3:0] TXU_BIT_THREE = 4'h3, + parameter [3:0] TXU_BIT_SEVEN = 4'h7, + parameter [3:0] TXU_PARITY = 4'h8, + parameter [3:0] TXU_STOP = 4'h9, + parameter [3:0] TXU_SECOND_STOP = 4'ha, + parameter [3:0] TXU_BREAK = 4'he, + parameter [3:0] TXU_IDLE = 4'hf +) ( + input wire i_clk, + i_reset, + input wire [30:0] i_setup, + input wire i_break, + input wire i_wr, + input wire [7:0] i_data, + input wire i_cts_n, + output reg o_uart_tx, + output wire o_busy +); + wire [27:0] clocks_per_baud, break_condition; + wire [1:0] i_data_bits, data_bits; + wire use_parity, parity_odd, dblstop, fixd_parity, fixdp_value, hw_flow_control, i_parity_odd; + reg [30:0] r_setup; + assign clocks_per_baud = {4'h0, r_setup[23:0]}; + assign break_condition = {r_setup[23:0], 4'h0}; + assign hw_flow_control = !r_setup[30]; + assign i_data_bits = i_setup[29:28]; + assign data_bits = r_setup[29:28]; + assign dblstop = r_setup[27]; + assign use_parity = r_setup[26]; + assign fixd_parity = r_setup[25]; + assign i_parity_odd = i_setup[24]; + assign parity_odd = r_setup[24]; + assign fixdp_value = r_setup[24]; + reg [27:0] baud_counter; + reg [ 3:0] state; + reg [ 7:0] lcl_data; + reg calc_parity, r_busy, zero_baud_counter, last_state; + reg q_cts_n, qq_cts_n, ck_cts; + always @(posedge i_clk) {qq_cts_n, q_cts_n} <= {q_cts_n, i_cts_n}; + always @(posedge i_clk) ck_cts <= (!qq_cts_n) || (!hw_flow_control); + initial r_busy = 1'b1; + initial state = TXU_IDLE; + always @(posedge i_clk) + if (i_reset) begin + r_busy <= 1'b1; + state <= TXU_IDLE; + end else if (i_break) begin + state <= TXU_BREAK; + r_busy <= 1'b1; + end else if (!zero_baud_counter) begin + r_busy <= 1'b1; + end else if (state == TXU_BREAK) begin + state <= TXU_IDLE; + r_busy <= !ck_cts; + end else if (state == TXU_IDLE) begin + if ((i_wr) && (!r_busy)) begin + r_busy <= 1'b1; + case (i_data_bits) + 2'b00: state <= TXU_BIT_ZERO; + 2'b01: state <= TXU_BIT_ONE; + 2'b10: state <= TXU_BIT_TWO; + 2'b11: state <= TXU_BIT_THREE; + endcase + end else begin + r_busy <= !ck_cts; + end + end else begin + r_busy <= 1'b1; + if (state[3] == 0) begin + if (state == TXU_BIT_SEVEN) state <= (use_parity) ? TXU_PARITY : TXU_STOP; + else state <= state + 1; + end else if (state == TXU_PARITY) begin + state <= TXU_STOP; + end else if (state == TXU_STOP) begin + if (dblstop) state <= TXU_SECOND_STOP; + else state <= TXU_IDLE; + end else begin + state <= TXU_IDLE; + end + end + assign o_busy = (r_busy); + initial r_setup = INITIAL_SETUP; + always @(posedge i_clk) if (!o_busy) r_setup <= i_setup; + initial lcl_data = 8'hff; + always @(posedge i_clk) + if (!r_busy) lcl_data <= i_data; + else if (zero_baud_counter) lcl_data <= {1'b0, lcl_data[7:1]}; + initial o_uart_tx = 1'b1; + always @(posedge i_clk) + if (i_reset) o_uart_tx <= 1'b1; + else if ((i_break) || ((i_wr) && (!r_busy))) o_uart_tx <= 1'b0; + else if (zero_baud_counter) + casez (state) + 4'b0???: o_uart_tx <= lcl_data[0]; + TXU_PARITY: o_uart_tx <= calc_parity; + default: o_uart_tx <= 1'b1; + endcase + initial calc_parity = 1'b0; + always @(posedge i_clk) + if (!o_busy) calc_parity <= i_setup[24]; + else if (fixd_parity) calc_parity <= fixdp_value; + else if (zero_baud_counter) begin + if (state[3] == 0) calc_parity <= calc_parity ^ lcl_data[0]; + else if (state == TXU_IDLE) calc_parity <= parity_odd; + end else if (!r_busy) calc_parity <= parity_odd; + initial zero_baud_counter = 1'b0; + initial baud_counter = 28'h05; + always @(posedge i_clk) begin + zero_baud_counter <= (baud_counter == 28'h01); + if ((i_reset) || (i_break)) begin + baud_counter <= break_condition; + zero_baud_counter <= 1'b0; + end else if (!zero_baud_counter) baud_counter <= baud_counter - 28'h01; + else if (state == TXU_BREAK) begin + baud_counter <= 0; + zero_baud_counter <= 1'b1; + end else if (state == TXU_IDLE) begin + baud_counter <= 28'h0; + zero_baud_counter <= 1'b1; + if ((i_wr) && (!r_busy)) begin + baud_counter <= {4'h0, i_setup[23:0]} - 28'h01; + zero_baud_counter <= 1'b0; + end + end else if (last_state) baud_counter <= clocks_per_baud - 28'h02; + else baud_counter <= clocks_per_baud - 28'h01; + end + initial last_state = 1'b0; + always @(posedge i_clk) + if (dblstop) last_state <= (state == TXU_SECOND_STOP); + else last_state <= (state == TXU_STOP); + wire unused; + assign unused = &{1'b0, i_parity_odd, data_bits}; +`ifdef FORMAL + reg fsv_parity; + reg [30:0] fsv_setup; + reg [7:0] fsv_data; + reg f_past_valid; + reg [5:0] f_five_seq; + reg [6:0] f_six_seq; + reg [7:0] f_seven_seq; + reg [8:0] f_eight_seq; + reg [2:0] f_stop_seq; + initial f_past_valid = 1'b0; + always @(posedge i_clk) f_past_valid <= 1'b1; + always @(posedge i_clk) if ((i_wr) && (!o_busy)) fsv_data <= i_data; + initial fsv_setup = INITIAL_SETUP; + always @(posedge i_clk) if (!o_busy) fsv_setup <= i_setup; + always @(*) assert (r_setup == fsv_setup); + always @(posedge i_clk) assert (zero_baud_counter == (baud_counter == 0)); + always @(*) if (!o_busy) assert (zero_baud_counter); + /* +* +* Will only pass if !i_break && !i_reset, otherwise the setup can +* change in the middle of this operation +* +always @(posedge i_clk) +if ((f_past_valid)&&(!$past(i_reset))&&(!$past(i_break)) +&&(($past(o_busy))||($past(i_wr)))) +assert(baud_counter <= { fsv_setup[23:0], 4'h0 }); +*/ + always @(posedge i_clk) + if ((f_past_valid) && (!$past( + zero_baud_counter + )) && (!$past( + i_reset + )) && (!$past( + i_break + ))) begin + assert ($stable(o_uart_tx)); + assert ($stable(state)); + assert ($stable(lcl_data)); + if ((state != TXU_IDLE) && (state != TXU_BREAK)) assert ($stable(calc_parity)); + assert (baud_counter == $past(baud_counter) - 1'b1); + end + initial f_five_seq = 0; + always @(posedge i_clk) + if ((i_reset) || (i_break)) f_five_seq = 0; + else if ((state == TXU_IDLE) && (i_wr) && (!o_busy) && (i_data_bits == 2'b11)) f_five_seq <= 1; + else if (zero_baud_counter) f_five_seq <= f_five_seq << 1; + always @(*) + if (|f_five_seq) begin + assert (fsv_setup[29:28] == data_bits); + assert (data_bits == 2'b11); + assert (baud_counter < fsv_setup[23:0]); + assert (1'b0 == |f_six_seq); + assert (1'b0 == |f_seven_seq); + assert (1'b0 == |f_eight_seq); + assert (r_busy); + assert (state > 4'h2); + end + always @(*) + case (f_five_seq) + 6'h00: begin + assert (1); + end + 6'h01: begin + assert (state == 4'h3); + assert (o_uart_tx == 1'b0); + assert (lcl_data[4:0] == fsv_data[4:0]); + if (!fixd_parity) assert (calc_parity == parity_odd); + end + 6'h02: begin + assert (state == 4'h4); + assert (o_uart_tx == fsv_data[0]); + assert (lcl_data[3:0] == fsv_data[4:1]); + if (!fixd_parity) assert (calc_parity == fsv_data[0] ^ parity_odd); + end + 6'h04: begin + assert (state == 4'h5); + assert (o_uart_tx == fsv_data[1]); + assert (lcl_data[2:0] == fsv_data[4:2]); + if (!fixd_parity) assert (calc_parity == (^fsv_data[1:0]) ^ parity_odd); + end + 6'h08: begin + assert (state == 4'h6); + assert (o_uart_tx == fsv_data[2]); + assert (lcl_data[1:0] == fsv_data[4:3]); + if (!fixd_parity) assert (calc_parity == (^fsv_data[2:0]) ^ parity_odd); + end + 6'h10: begin + assert (state == 4'h7); + assert (o_uart_tx == fsv_data[3]); + assert (lcl_data[0] == fsv_data[4]); + if (!fixd_parity) assert (calc_parity == (^fsv_data[3:0]) ^ parity_odd); + end + 6'h20: begin + if (use_parity) + assert (state == 4'h8); + else assert (state == 4'h9); + assert (o_uart_tx == fsv_data[4]); + if (!fixd_parity) assert (calc_parity == (^fsv_data[4:0]) ^ parity_odd); + end + default: begin + assert (0); + end + endcase + initial f_six_seq = 0; + always @(posedge i_clk) + if ((i_reset) || (i_break)) f_six_seq = 0; + else if ((state == TXU_IDLE) && (i_wr) && (!o_busy) && (i_data_bits == 2'b10)) f_six_seq <= 1; + else if (zero_baud_counter) f_six_seq <= f_six_seq << 1; + always @(*) + if (|f_six_seq) begin + assert (fsv_setup[29:28] == 2'b10); + assert (fsv_setup[29:28] == data_bits); + assert (baud_counter < fsv_setup[23:0]); + assert (1'b0 == |f_five_seq); + assert (1'b0 == |f_seven_seq); + assert (1'b0 == |f_eight_seq); + assert (r_busy); + assert (state > 4'h1); + end + always @(*) + case (f_six_seq) + 7'h00: begin + assert (1); + end + 7'h01: begin + assert (state == 4'h2); + assert (o_uart_tx == 1'b0); + assert (lcl_data[5:0] == fsv_data[5:0]); + if (!fixd_parity) assert (calc_parity == parity_odd); + end + 7'h02: begin + assert (state == 4'h3); + assert (o_uart_tx == fsv_data[0]); + assert (lcl_data[4:0] == fsv_data[5:1]); + if (!fixd_parity) assert (calc_parity == fsv_data[0] ^ parity_odd); + end + 7'h04: begin + assert (state == 4'h4); + assert (o_uart_tx == fsv_data[1]); + assert (lcl_data[3:0] == fsv_data[5:2]); + if (!fixd_parity) assert (calc_parity == (^fsv_data[1:0]) ^ parity_odd); + end + 7'h08: begin + assert (state == 4'h5); + assert (o_uart_tx == fsv_data[2]); + assert (lcl_data[2:0] == fsv_data[5:3]); + if (!fixd_parity) assert (calc_parity == (^fsv_data[2:0]) ^ parity_odd); + end + 7'h10: begin + assert (state == 4'h6); + assert (o_uart_tx == fsv_data[3]); + assert (lcl_data[1:0] == fsv_data[5:4]); + if (!fixd_parity) assert (calc_parity == (^fsv_data[3:0]) ^ parity_odd); + end + 7'h20: begin + assert (state == 4'h7); + assert (lcl_data[0] == fsv_data[5]); + assert (o_uart_tx == fsv_data[4]); + if (!fixd_parity) assert (calc_parity == ((^fsv_data[4:0]) ^ parity_odd)); + end + 7'h40: begin + if (use_parity) + assert (state == 4'h8); + else assert (state == 4'h9); + assert (o_uart_tx == fsv_data[5]); + if (!fixd_parity) assert (calc_parity == ((^fsv_data[5:0]) ^ parity_odd)); + end + default: begin + if (f_past_valid) assert (0); + end + endcase + initial f_seven_seq = 0; + always @(posedge i_clk) + if ((i_reset) || (i_break)) f_seven_seq = 0; + else if ((state == TXU_IDLE) && (i_wr) && (!o_busy) && (i_data_bits == 2'b01)) f_seven_seq <= 1; + else if (zero_baud_counter) f_seven_seq <= f_seven_seq << 1; + always @(*) + if (|f_seven_seq) begin + assert (fsv_setup[29:28] == 2'b01); + assert (fsv_setup[29:28] == data_bits); + assert (baud_counter < fsv_setup[23:0]); + assert (1'b0 == |f_five_seq); + assert (1'b0 == |f_six_seq); + assert (1'b0 == |f_eight_seq); + assert (r_busy); + assert (state != 4'h0); + end + always @(*) + case (f_seven_seq) + 8'h00: begin + assert (1); + end + 8'h01: begin + assert (state == 4'h1); + assert (o_uart_tx == 1'b0); + assert (lcl_data[6:0] == fsv_data[6:0]); + if (!fixd_parity) assert (calc_parity == parity_odd); + end + 8'h02: begin + assert (state == 4'h2); + assert (o_uart_tx == fsv_data[0]); + assert (lcl_data[5:0] == fsv_data[6:1]); + if (!fixd_parity) assert (calc_parity == fsv_data[0] ^ parity_odd); + end + 8'h04: begin + assert (state == 4'h3); + assert (o_uart_tx == fsv_data[1]); + assert (lcl_data[4:0] == fsv_data[6:2]); + if (!fixd_parity) assert (calc_parity == (^fsv_data[1:0]) ^ parity_odd); + end + 8'h08: begin + assert (state == 4'h4); + assert (o_uart_tx == fsv_data[2]); + assert (lcl_data[3:0] == fsv_data[6:3]); + if (!fixd_parity) assert (calc_parity == (^fsv_data[2:0]) ^ parity_odd); + end + 8'h10: begin + assert (state == 4'h5); + assert (o_uart_tx == fsv_data[3]); + assert (lcl_data[2:0] == fsv_data[6:4]); + if (!fixd_parity) assert (calc_parity == (^fsv_data[3:0]) ^ parity_odd); + end + 8'h20: begin + assert (state == 4'h6); + assert (o_uart_tx == fsv_data[4]); + assert (lcl_data[1:0] == fsv_data[6:5]); + if (!fixd_parity) assert (calc_parity == ((^fsv_data[4:0]) ^ parity_odd)); + end + 8'h40: begin + assert (state == 4'h7); + assert (lcl_data[0] == fsv_data[6]); + assert (o_uart_tx == fsv_data[5]); + if (!fixd_parity) assert (calc_parity == ((^fsv_data[5:0]) ^ parity_odd)); + end + 8'h80: begin + if (use_parity) + assert (state == 4'h8); + else assert (state == 4'h9); + assert (o_uart_tx == fsv_data[6]); + if (!fixd_parity) assert (calc_parity == ((^fsv_data[6:0]) ^ parity_odd)); + end + default: begin + if (f_past_valid) assert (0); + end + endcase + initial f_eight_seq = 0; + always @(posedge i_clk) + if ((i_reset) || (i_break)) f_eight_seq = 0; + else if ((state == TXU_IDLE) && (i_wr) && (!o_busy) && (i_data_bits == 2'b00)) f_eight_seq <= 1; + else if (zero_baud_counter) f_eight_seq <= f_eight_seq << 1; + always @(*) + if (|f_eight_seq) begin + assert (fsv_setup[29:28] == 2'b00); + assert (fsv_setup[29:28] == data_bits); + assert (baud_counter < {6'h0, fsv_setup[23:0]}); + assert (1'b0 == |f_five_seq); + assert (1'b0 == |f_six_seq); + assert (1'b0 == |f_seven_seq); + assert (r_busy); + end + always @(*) + case (f_eight_seq) + 9'h000: begin + assert (1); + end + 9'h001: begin + assert (state == 4'h0); + assert (o_uart_tx == 1'b0); + assert (lcl_data[7:0] == fsv_data[7:0]); + if (!fixd_parity) assert (calc_parity == parity_odd); + end + 9'h002: begin + assert (state == 4'h1); + assert (o_uart_tx == fsv_data[0]); + assert (lcl_data[6:0] == fsv_data[7:1]); + if (!fixd_parity) assert (calc_parity == fsv_data[0] ^ parity_odd); + end + 9'h004: begin + assert (state == 4'h2); + assert (o_uart_tx == fsv_data[1]); + assert (lcl_data[5:0] == fsv_data[7:2]); + if (!fixd_parity) assert (calc_parity == (^fsv_data[1:0]) ^ parity_odd); + end + 9'h008: begin + assert (state == 4'h3); + assert (o_uart_tx == fsv_data[2]); + assert (lcl_data[4:0] == fsv_data[7:3]); + if (!fixd_parity) assert (calc_parity == (^fsv_data[2:0]) ^ parity_odd); + end + 9'h010: begin + assert (state == 4'h4); + assert (o_uart_tx == fsv_data[3]); + assert (lcl_data[3:0] == fsv_data[7:4]); + if (!fixd_parity) assert (calc_parity == (^fsv_data[3:0]) ^ parity_odd); + end + 9'h020: begin + assert (state == 4'h5); + assert (o_uart_tx == fsv_data[4]); + assert (lcl_data[2:0] == fsv_data[7:5]); + if (!fixd_parity) assert (calc_parity == (^fsv_data[4:0]) ^ parity_odd); + end + 9'h040: begin + assert (state == 4'h6); + assert (o_uart_tx == fsv_data[5]); + assert (lcl_data[1:0] == fsv_data[7:6]); + if (!fixd_parity) assert (calc_parity == (^fsv_data[5:0]) ^ parity_odd); + end + 9'h080: begin + assert (state == 4'h7); + assert (o_uart_tx == fsv_data[6]); + assert (lcl_data[0] == fsv_data[7]); + if (!fixd_parity) assert (calc_parity == ((^fsv_data[6:0]) ^ parity_odd)); + end + 9'h100: begin + if (use_parity) + assert (state == 4'h8); + else assert (state == 4'h9); + assert (o_uart_tx == fsv_data[7]); + if (!fixd_parity) assert (calc_parity == ((^fsv_data[7:0]) ^ parity_odd)); + end + default: begin + if (f_past_valid) assert (0); + end + endcase + always @(posedge i_clk) + if (((|f_five_seq[5:0]) || (|f_six_seq[6:0]) || (|f_seven_seq[7:0]) +|| (|f_eight_seq[8:0])) +&& ($past( + zero_baud_counter + ))) + assert (baud_counter == {4'h0, fsv_setup[23:0]} - 1); + initial f_stop_seq = 1'b0; + always @(posedge i_clk) + if ((i_reset) || (i_break)) f_stop_seq <= 0; + else if (zero_baud_counter) begin + f_stop_seq <= 0; + if (f_stop_seq[0]) begin + if (dblstop) f_stop_seq[1] <= 1'b1; + else f_stop_seq[2] <= 1'b1; + end + if (f_stop_seq[1]) f_stop_seq[2] <= 1'b1; + if (f_eight_seq[8] | f_seven_seq[7] | f_six_seq[6] | f_five_seq[5]) begin + if (use_parity) f_stop_seq[0] <= 1'b1; + else if (dblstop) f_stop_seq[1] <= 1'b1; + else f_stop_seq[2] <= 1'b1; + end + end + always @(*) + if (|f_stop_seq) begin + assert (1'b0 == |f_five_seq[4:0]); + assert (1'b0 == |f_six_seq[5:0]); + assert (1'b0 == |f_seven_seq[6:0]); + assert (1'b0 == |f_eight_seq[7:0]); + assert (r_busy); + end + always @(*) + if (f_stop_seq[0]) begin + if (dblstop) + assert (state == TXU_STOP); + else assert (state == TXU_STOP); + assert (use_parity); + assert (o_uart_tx == fsv_parity); + end + + always @(*) + if (f_stop_seq[1]) begin + assert (state == TXU_SECOND_STOP); + assert (dblstop); + assert (o_uart_tx); + end + always @(*) + if (f_stop_seq[2]) begin + assert (state == 4'hf); + assert (o_uart_tx); + assert (baud_counter < fsv_setup[23:0] - 1'b1); + end + + always @(*) + if (fsv_setup[25]) fsv_parity <= fsv_setup[24]; + else + case (fsv_setup[29:28]) + 2'b00: fsv_parity = (^fsv_data[7:0]) ^ fsv_setup[24]; + 2'b01: fsv_parity = (^fsv_data[6:0]) ^ fsv_setup[24]; + 2'b10: fsv_parity = (^fsv_data[5:0]) ^ fsv_setup[24]; + 2'b11: fsv_parity = (^fsv_data[4:0]) ^ fsv_setup[24]; + endcase + reg [1:0] f_break_seq; + initial f_break_seq = 2'b00; + always @(posedge i_clk) + if (i_reset) f_break_seq <= 2'b00; + else if (i_break) f_break_seq <= 2'b01; + else if (!zero_baud_counter) f_break_seq <= {|f_break_seq, 1'b0}; + else f_break_seq <= 0; + always @(posedge i_clk) + if (f_break_seq[0]) + assert (baud_counter == {$past(fsv_setup[23:0]), 4'h0}); + always @(posedge i_clk) + if ((f_past_valid) && ($past(f_break_seq[1])) && (state != TXU_BREAK)) begin + assert (state == TXU_IDLE); + assert (o_uart_tx == 1'b1); + end + always @(*) + if (|f_break_seq) begin + assert (state == TXU_BREAK); + assert (r_busy); + assert (o_uart_tx == 1'b0); + end +`ifndef TXUART + reg [28:0] f_counter; + initial f_counter = 0; + always @(posedge i_clk) + if (!o_busy) f_counter <= 1'b0; + else f_counter <= f_counter + 1'b1; + always @(*) + if (f_five_seq[0] | f_six_seq[0] | f_seven_seq[0] | f_eight_seq[0]) + assert (f_counter == (fsv_setup[23:0] - baud_counter - 1)); + else if (f_five_seq[1] | f_six_seq[1] | f_seven_seq[1] | f_eight_seq[1]) + assert (f_counter == ({4'h0, fsv_setup[23:0], 1'b0} - baud_counter - 1)); + else if (f_five_seq[2] | f_six_seq[2] | f_seven_seq[2] | f_eight_seq[2]) + assert(f_counter == ({4'h0, fsv_setup[23:0], 1'b0} ++{5'h0, fsv_setup[23:0]} +- baud_counter - 1)); + else if (f_five_seq[3] | f_six_seq[3] | f_seven_seq[3] | f_eight_seq[3]) + assert (f_counter == ({3'h0, fsv_setup[23:0], 2'b0} - baud_counter - 1)); + else if (f_five_seq[4] | f_six_seq[4] | f_seven_seq[4] | f_eight_seq[4]) + assert(f_counter == ({3'h0, fsv_setup[23:0], 2'b0} ++{5'h0, fsv_setup[23:0]} +- baud_counter - 1)); + else if (f_five_seq[5] | f_six_seq[5] | f_seven_seq[5] | f_eight_seq[5]) + assert(f_counter == ({3'h0, fsv_setup[23:0], 2'b0} ++{4'h0, fsv_setup[23:0], 1'b0} +- baud_counter - 1)); + else if (f_six_seq[6] | f_seven_seq[6] | f_eight_seq[6]) + assert(f_counter == ({3'h0, fsv_setup[23:0], 2'b0} ++{5'h0, fsv_setup[23:0]} ++{4'h0, fsv_setup[23:0], 1'b0} +- baud_counter - 1)); + else if (f_seven_seq[7] | f_eight_seq[7]) + assert (f_counter == ({2'h0, fsv_setup[23:0], 3'b0} - baud_counter - 1)); + else if (f_eight_seq[8]) + assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} ++{5'h0, fsv_setup[23:0]} +- baud_counter - 1)); + else if (f_stop_seq[0] || (!use_parity && f_stop_seq[1])) begin + case (data_bits) + 2'b00: + assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} ++{4'h0, fsv_setup[23:0], 1'b0} +- baud_counter - 1)); + 2'b01: + assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} ++{5'h0, fsv_setup[23:0]} +- baud_counter - 1)); + 2'b10: + assert (f_counter == ({2'h0, fsv_setup[23:0], 3'b0} - baud_counter - 1)); + 2'b11: + assert(f_counter == ({3'h0, fsv_setup[23:0], 2'b0} ++{5'h0, fsv_setup[23:0]} ++{4'h0, fsv_setup[23:0], 1'b0} +- baud_counter - 1)); + endcase + end else if (!use_parity && !dblstop && f_stop_seq[2]) begin + case (data_bits) + 2'b00: + assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} ++{4'h0, fsv_setup[23:0], 1'b0} +- baud_counter - 2)); + 2'b01: + assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} ++{5'h0, fsv_setup[23:0]} +- baud_counter - 2)); + 2'b10: + assert (f_counter == ({2'h0, fsv_setup[23:0], 3'b0} - baud_counter - 2)); + 2'b11: + assert(f_counter == ({3'h0, fsv_setup[23:0], 2'b0} ++{5'h0, fsv_setup[23:0]} ++{4'h0, fsv_setup[23:0], 1'b0} +- baud_counter - 2)); + endcase + end else if (f_stop_seq[1]) begin + assert (dblstop && use_parity); + case (data_bits) + 2'b00: + assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} ++{5'h0, fsv_setup[23:0]} ++{4'h0, fsv_setup[23:0], 1'b0} +- baud_counter - 1)); + 2'b01: + assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} ++{4'h0, fsv_setup[23:0], 1'b0} +- baud_counter - 1)); + 2'b10: + assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} ++{5'h0, fsv_setup[23:0]} +- baud_counter - 1)); + 2'b11: + assert (f_counter == ({2'h0, fsv_setup[23:0], 3'b0} - baud_counter - 1)); + endcase + end else if ((dblstop ^ use_parity) && f_stop_seq[2]) begin + case (data_bits) + 2'b00: + assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} ++{5'h0, fsv_setup[23:0]} ++{4'h0, fsv_setup[23:0], 1'b0} +- baud_counter - 2)); + 2'b01: + assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} ++{4'h0, fsv_setup[23:0], 1'b0} +- baud_counter - 2)); + 2'b10: + assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} ++{5'h0, fsv_setup[23:0]} +- baud_counter - 2)); + 2'b11: + assert (f_counter == ({2'h0, fsv_setup[23:0], 3'b0} - baud_counter - 2)); + endcase + end else if (f_stop_seq[2]) begin + assert (dblstop); + assert (use_parity); + case (data_bits) + 2'b00: + assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} ++{3'h0, fsv_setup[23:0], 2'b00} +- baud_counter - 2)); + 2'b01: + assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} ++{5'h0, fsv_setup[23:0]} ++{4'h0, fsv_setup[23:0], 1'b0} +- baud_counter - 2)); + 2'b10: + assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} ++{4'h0, fsv_setup[23:0], 1'b0} +- baud_counter - 2)); + 2'b11: + assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} ++{5'h0, fsv_setup[23:0]} +- baud_counter - 2)); + endcase + end +`endif + always @(*) assert ((state < 4'hb) || (state >= 4'he)); + always @(*) assume (i_setup[23:0] > 2); + always @(*) assert (fsv_setup[23:0] > 2); +`endif +endmodule +" +"/* +Copyright (C) 2015-2021, Gisselquist Technology, LLC + +This program is free software (firmware): you can redistribute it and/or +modify it under the terms of the GNU General Public License as published +by the Free Software Foundation, either version 3 of the License, or (at +your option) any later version. + +This program is distributed in the hope that it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License along +with this program. (It's in the $(ROOT)/doc directory. Run make with no +target there if the PDF file isn't present.) If not, see + for a copy. + +License: GPL, v3, as defined and found on www.gnu.org, +http://www.gnu.org/licenses/gpl.html +*/ +`default_nettype none +module ufifo #( + parameter BW = 8, + parameter [3:0] LGFLEN = 4, + parameter [0:0] RXFIFO = 1'b1, + parameter FLEN = (1 << LGFLEN) +) ( + input wire i_clk, + i_reset, + input wire i_wr, + input wire [(BW-1):0] i_data, + output wire o_empty_n, + input wire i_rd, + output wire [(BW-1):0] o_data, + output wire [15:0] o_status, + output wire o_err +); + reg [(BW-1):0] fifo[0:(FLEN-1)]; + reg [(BW-1):0] r_data, last_write; + reg [(LGFLEN-1):0] wr_addr, rd_addr, r_next; + reg will_overflow, will_underflow; + reg osrc; + wire [(LGFLEN-1):0] w_waddr_plus_one, w_waddr_plus_two; + wire w_write, w_read; + reg [(LGFLEN-1):0] r_fill; + wire [3:0] lglen; + wire w_half_full; + reg [9:0] w_fill; + assign w_write = (i_wr && (!will_overflow || i_rd)); + assign w_read = (i_rd && o_empty_n); + assign w_waddr_plus_two = wr_addr + 2; + assign w_waddr_plus_one = wr_addr + 1; + initial will_overflow = 1'b0; + always @(posedge i_clk) + if (i_reset) will_overflow <= 1'b0; + else if (i_rd) will_overflow <= (will_overflow) && (i_wr); + else if (w_write) will_overflow <= (will_overflow) || (w_waddr_plus_two == rd_addr); + else if (w_waddr_plus_one == rd_addr) will_overflow <= 1'b1; + initial wr_addr = 0; + always @(posedge i_clk) + if (i_reset) wr_addr <= {(LGFLEN) {1'b0}}; + else if (w_write) wr_addr <= w_waddr_plus_one; + always @(posedge i_clk) if (w_write) fifo[wr_addr] <= i_data; + initial will_underflow = 1'b1; + always @(posedge i_clk) + if (i_reset) will_underflow <= 1'b1; + else if (i_wr) will_underflow <= 1'b0; + else if (w_read) will_underflow <= (will_underflow) || (r_next == wr_addr); + initial rd_addr = 0; + initial r_next = 1; + always @(posedge i_clk) + if (i_reset) begin + rd_addr <= 0; + r_next <= 1; + end else if (w_read) begin + rd_addr <= rd_addr + 1; + r_next <= rd_addr + 2; + end + always @(posedge i_clk) if (w_read) r_data <= fifo[r_next[LGFLEN-1:0]]; + always @(posedge i_clk) + if (i_wr && (!o_empty_n || (w_read && r_next == wr_addr))) + last_write <= i_data; + initial osrc = 1'b0; + always @(posedge i_clk) + if (i_reset) osrc <= 1'b0; + else if (i_wr && (!o_empty_n || (w_read && r_next == wr_addr))) osrc <= 1'b1; + else if (i_rd) osrc <= 1'b0; + assign o_data = (osrc) ? last_write : r_data; + generate + if (RXFIFO) begin : RXFIFO_FILL + initial r_fill = 0; + always @(posedge i_clk) + if (i_reset) r_fill <= 0; + else + case ({ + w_write, w_read + }) + 2'b01: r_fill <= r_fill - 1'b1; + 2'b10: r_fill <= r_fill + 1'b1; + default: begin + end + endcase + end else begin : TXFIFO_FILL + initial r_fill = -1; + always @(posedge i_clk) + if (i_reset) r_fill <= -1; + else + case ({ + w_write, w_read + }) + 2'b01: r_fill <= r_fill + 1'b1; + 2'b10: r_fill <= r_fill - 1'b1; + default: begin + end + endcase + end + endgenerate + assign o_err = (i_wr && !w_write); + assign lglen = LGFLEN; + always @(*) begin + w_fill = 0; + w_fill[(LGFLEN-1):0] = r_fill; + end + assign w_half_full = r_fill[(LGFLEN-1)]; + assign o_status = {lglen, w_fill, w_half_full, (RXFIFO != 0) ? !will_underflow : !will_overflow}; + assign o_empty_n = !will_underflow; +`ifdef FORMAL + reg f_past_valid; + initial f_past_valid = 0; + always @(posedge i_clk) f_past_valid <= 1; + reg [LGFLEN-1:0] f_fill; + wire [LGFLEN-1:0] f_raddr_plus_one; + always @(*) f_fill = wr_addr - rd_addr; + always @(*) assert (will_underflow == (f_fill == 0)); + always @(*) assert (will_overflow == (&f_fill)); + assign f_raddr_plus_one = rd_addr + 1; + always @(*) assert (f_raddr_plus_one == r_next); + always @(*) + if (will_underflow) begin + assert (!w_read); + assert (!osrc); + end + always @(posedge i_clk) + if (RXFIFO) + assert (r_fill == f_fill); + else assert (r_fill == (~f_fill)); +`ifdef UFIFO + (* anyconst *) reg [LGFLEN-1:0] f_const_addr; + (* anyconst *) reg [BW-1:0] f_const_data, f_const_second; + reg [LGFLEN-1:0] f_next_addr; + reg [1:0] f_state; + reg f_first_in_fifo, f_second_in_fifo; + reg [LGFLEN-1:0] f_distance_to_first, f_distance_to_second; + always @(*) begin + f_next_addr = f_const_addr + 1; + f_distance_to_first = f_const_addr - rd_addr; + f_distance_to_second = f_next_addr - rd_addr; + f_first_in_fifo = (f_distance_to_first < f_fill) +&& !will_underflow +&& (fifo[f_const_addr] == f_const_data); + f_second_in_fifo = (f_distance_to_second < f_fill) +&& !will_underflow +&& (fifo[f_next_addr] == f_const_second); + end + initial f_state = 2'b00; + always @(posedge i_clk) + if (i_reset) f_state <= 2'b00; + else + case (f_state) + 2'b00: + if (w_write && (wr_addr == f_const_addr) && (i_data == f_const_data)) f_state <= 2'b01; + 2'b01: + if (w_read && (rd_addr == f_const_addr)) f_state <= 2'b00; + else if (w_write && (wr_addr == f_next_addr)) + f_state <= (i_data == f_const_second) ? 2'b10 : 2'b00; + 2'b10: if (w_read && (rd_addr == f_const_addr)) f_state <= 2'b11; + 2'b11: if (w_read) f_state <= 2'b00; + endcase + always @(*) + case (f_state) + 2'b00: begin + end + 2'b01: begin + assert (!will_underflow); + assert (f_first_in_fifo); + assert (!f_second_in_fifo); + assert (wr_addr == f_next_addr); + assert (fifo[f_const_addr] == f_const_data); + if (rd_addr == f_const_addr) assert (o_data == f_const_data); + end + 2'b10: begin + assert (f_first_in_fifo); + assert (f_second_in_fifo); + end + 2'b11: begin + assert (f_second_in_fifo); + assert (rd_addr == f_next_addr); + assert (o_data == f_const_second); + end + endcase +`endif + reg cvr_filled; + always @(*) cover (o_empty_n); +`ifdef UFIFO + always @(*) cover (o_err); + initial cvr_filled = 0; + always @(posedge i_clk) + if (i_reset) cvr_filled <= 0; + else if (&f_fill[LGFLEN-1:0]) cvr_filled <= 1; + always @(*) cover (cvr_filled && !o_empty_n); +`endif +`endif +endmodule +" +"/* +Copyright (C) 2015-2021, Gisselquist Technology, LLC + +This program is free software (firmware): you can redistribute it and/or +modify it under the terms of the GNU General Public License as published +by the Free Software Foundation, either version 3 of the License, or (at +your option) any later version. + +This program is distributed in the hope that it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License along +with this program. (It's in the $(ROOT)/doc directory. Run make with no +target there if the PDF file isn't present.) If not, see + for a copy. + +License: GPL, v3, as defined and found on www.gnu.org, +http://www.gnu.org/licenses/gpl.html +*/ +`default_nettype none +module rxuartlite #( + parameter TIMER_BITS = 10, +`ifdef FORMAL + parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 16, +`else + parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 868, +`endif + parameter TB = TIMER_BITS, + parameter [ 3:0] RXUL_BIT_ZERO = 4'h0, + parameter [ 3:0] RXUL_BIT_ONE = 4'h1, + parameter [ 3:0] RXUL_BIT_TWO = 4'h2, + parameter [ 3:0] RXUL_BIT_THREE = 4'h3, + parameter [ 3:0] RXUL_BIT_FOUR = 4'h4, + parameter [ 3:0] RXUL_BIT_FIVE = 4'h5, + parameter [ 3:0] RXUL_BIT_SIX = 4'h6, + parameter [ 3:0] RXUL_BIT_SEVEN = 4'h7, + parameter [ 3:0] RXUL_STOP = 4'h8, + parameter [ 3:0] RXUL_WAIT = 4'h9, + parameter [ 3:0] RXUL_IDLE = 4'hf +) ( + input wire i_clk, + input wire i_uart_rx, + output reg o_wr, + output reg [7:0] o_data +); + wire [(TB-1):0] half_baud; + reg [3:0] state; + assign half_baud = {1'b0, CLOCKS_PER_BAUD[(TB-1):1]}; + reg [(TB-1):0] baud_counter; + reg zero_baud_counter; + reg q_uart, qq_uart, ck_uart; + reg [(TB-1):0] chg_counter; + reg half_baud_time; + reg [7:0] data_reg; + initial q_uart = 1'b1; + initial qq_uart = 1'b1; + initial ck_uart = 1'b1; + always @(posedge i_clk) {ck_uart, qq_uart, q_uart} <= {qq_uart, q_uart, i_uart_rx}; + initial chg_counter = {(TB) {1'b1}}; + always @(posedge i_clk) + if (qq_uart != ck_uart) chg_counter <= 0; + else if (chg_counter != {(TB) {1'b1}}) chg_counter <= chg_counter + 1; + initial half_baud_time = 0; + always @(posedge i_clk) half_baud_time <= (!ck_uart) && (chg_counter >= half_baud - 1'b1 - 1'b1); + initial state = RXUL_IDLE; + always @(posedge i_clk) + if (state == RXUL_IDLE) begin + state <= RXUL_IDLE; + if ((!ck_uart) && (half_baud_time)) state <= RXUL_BIT_ZERO; + end else if ((state >= RXUL_WAIT) && (ck_uart)) state <= RXUL_IDLE; + else if (zero_baud_counter) begin + if (state <= RXUL_STOP) state <= state + 1; + end + always @(posedge i_clk) + if ((zero_baud_counter) && (state != RXUL_STOP)) + data_reg <= {qq_uart, data_reg[7:1]}; + initial o_wr = 1'b0; + initial o_data = 8'h00; + always @(posedge i_clk) + if ((zero_baud_counter) && (state == RXUL_STOP) && (ck_uart)) begin + o_wr <= 1'b1; + o_data <= data_reg; + end else o_wr <= 1'b0; + initial baud_counter = 0; + always @(posedge i_clk) + if (((state == RXUL_IDLE)) && (!ck_uart) && (half_baud_time)) + baud_counter <= CLOCKS_PER_BAUD - 1'b1; + else if (state == RXUL_WAIT) baud_counter <= 0; + else if ((zero_baud_counter) && (state < RXUL_STOP)) baud_counter <= CLOCKS_PER_BAUD - 1'b1; + else if (!zero_baud_counter) baud_counter <= baud_counter - 1'b1; + initial zero_baud_counter = 1'b1; + always @(posedge i_clk) + if ((state == RXUL_IDLE) && (!ck_uart) && (half_baud_time)) zero_baud_counter <= 1'b0; + else if (state == RXUL_WAIT) zero_baud_counter <= 1'b1; + else if ((zero_baud_counter) && (state < RXUL_STOP)) zero_baud_counter <= 1'b0; + else if (baud_counter == 1) zero_baud_counter <= 1'b1; +`ifdef FORMAL + `define FORMAL_VERILATOR +`else +`ifdef VERILATOR + `define FORMAL_VERILATOR +`endif +`endif +`ifdef FORMAL + `define ASSUME assume + `define ASSERT assert +`ifdef VERIFIC + (* gclk *) wire gbl_clk; + global clocking @(posedge gbl_clk); + endclocking +`endif + localparam F_CKRES = 10; + (* anyseq *) wire f_tx_start; + (* anyconst *) wire [(F_CKRES-1):0] f_tx_step; + reg f_tx_zclk; + reg [(TB-1):0] f_tx_timer; + wire [7:0] f_rx_newdata; + reg [(TB-1):0] f_tx_baud; + wire f_tx_zbaud; + wire [(TB-1):0] f_max_baud_difference; + reg [(TB-1):0] f_baud_difference; + reg [(TB+3):0] f_tx_count, f_rx_count; + (* anyseq *) wire [7:0] f_tx_data; + wire f_txclk; + reg [1:0] f_rx_clock; + reg [(F_CKRES-1):0] f_tx_clock; + reg f_past_valid, f_past_valid_tx; + reg [9:0] f_tx_reg; + reg f_tx_busy; + initial f_past_valid = 1'b0; + always @(posedge i_clk) f_past_valid <= 1'b1; + initial f_rx_clock = 3'h0; + always @($global_clock) f_rx_clock <= f_rx_clock + 1'b1; + always @(*) assume (i_clk == f_rx_clock[1]); + localparam [(F_CKRES-1):0] F_MIDSTEP = {2'b01, {(F_CKRES - 2) {1'b0}}}; + localparam [(F_CKRES-1):0] F_HALFSTEP = F_MIDSTEP / 32; + localparam [(F_CKRES-1):0] F_MINSTEP = F_MIDSTEP - F_HALFSTEP + 1; + localparam [(F_CKRES-1):0] F_MAXSTEP = F_MIDSTEP + F_HALFSTEP - 1; + initial assert (F_MINSTEP <= F_MIDSTEP); + initial assert (F_MIDSTEP <= F_MAXSTEP); + always @(*) + assume ((f_tx_step == F_MINSTEP) || (f_tx_step == F_MIDSTEP) || (f_tx_step == F_MAXSTEP)); + always @($global_clock) f_tx_clock <= f_tx_clock + f_tx_step; + assign f_txclk = f_tx_clock[F_CKRES-1]; + initial f_past_valid_tx = 1'b0; + always @(posedge f_txclk) f_past_valid_tx <= 1'b1; + initial assume (i_uart_rx); + always @(*) if (f_tx_busy) assume (!f_tx_start); + initial f_tx_baud = 0; + always @(posedge f_txclk) + if ((f_tx_zbaud) && ((f_tx_busy) || (f_tx_start))) f_tx_baud <= CLOCKS_PER_BAUD - 1'b1; + else if (!f_tx_zbaud) f_tx_baud <= f_tx_baud - 1'b1; + always @(*) `ASSERT(f_tx_baud < CLOCKS_PER_BAUD); + always @(*) if (!f_tx_busy) `ASSERT(f_tx_baud == 0); + assign f_tx_zbaud = (f_tx_baud == 0); + initial assume (f_tx_data == 0); + always @(posedge f_txclk) + if ((!f_tx_zbaud) || (f_tx_busy) || (!f_tx_start)) + assume (f_tx_data == $past(f_tx_data)); + always @($global_clock) + if ((f_past_valid) && (!$rose(f_txclk))) + assume ($stable(f_tx_data)); + else if (f_tx_busy) assume ($stable(f_tx_data)); + always @($global_clock) + if ((!f_past_valid) || (!$rose(f_txclk))) begin + assume ($stable(f_tx_start)); + assume ($stable(f_tx_data)); + end + initial f_tx_busy = 1'b0; + initial f_tx_reg = 0; + always @(posedge f_txclk) + if (!f_tx_zbaud) begin + `ASSERT(f_tx_busy); + end else begin + f_tx_reg <= {1'b0, f_tx_reg[9:1]}; + if (f_tx_start) f_tx_reg <= {1'b1, f_tx_data, 1'b0}; + end + always @(*) + if (!f_tx_zbaud) f_tx_busy <= 1'b1; + else if (|f_tx_reg) f_tx_busy <= 1'b1; + else f_tx_busy <= 1'b0; + always @(posedge f_txclk) + if (f_tx_reg[9]) `ASSERT(f_tx_reg[8:0] == {f_tx_data, 1'b0}); + else if (f_tx_reg[8]) `ASSERT(f_tx_reg[7:0] == f_tx_data[7:0]); + else if (f_tx_reg[7]) `ASSERT(f_tx_reg[6:0] == f_tx_data[7:1]); + else if (f_tx_reg[6]) `ASSERT(f_tx_reg[5:0] == f_tx_data[7:2]); + else if (f_tx_reg[5]) `ASSERT(f_tx_reg[4:0] == f_tx_data[7:3]); + else if (f_tx_reg[4]) `ASSERT(f_tx_reg[3:0] == f_tx_data[7:4]); + else if (f_tx_reg[3]) `ASSERT(f_tx_reg[2:0] == f_tx_data[7:5]); + else if (f_tx_reg[2]) `ASSERT(f_tx_reg[1:0] == f_tx_data[7:6]); + else if (f_tx_reg[1]) `ASSERT(f_tx_reg[0] == f_tx_data[7]); + initial f_tx_count = 0; + always @(posedge f_txclk) + if (!f_tx_busy) f_tx_count <= 0; + else f_tx_count <= f_tx_count + 1'b1; + always @(*) + if (f_tx_reg == 10'h0) + assume (i_uart_rx); + else assume (i_uart_rx == f_tx_reg[0]); + always @(posedge f_txclk) + if (!f_tx_busy) begin + if ((!f_past_valid_tx) || (!$past(f_tx_busy))) `ASSERT(f_tx_count == 0); + end else if (f_tx_reg[9]) `ASSERT(f_tx_count == CLOCKS_PER_BAUD - 1 - f_tx_baud); + else if (f_tx_reg[8]) `ASSERT(f_tx_count == 2 * CLOCKS_PER_BAUD - 1 - f_tx_baud); + else if (f_tx_reg[7]) `ASSERT(f_tx_count == 3 * CLOCKS_PER_BAUD - 1 - f_tx_baud); + else if (f_tx_reg[6]) `ASSERT(f_tx_count == 4 * CLOCKS_PER_BAUD - 1 - f_tx_baud); + else if (f_tx_reg[5]) `ASSERT(f_tx_count == 5 * CLOCKS_PER_BAUD - 1 - f_tx_baud); + else if (f_tx_reg[4]) `ASSERT(f_tx_count == 6 * CLOCKS_PER_BAUD - 1 - f_tx_baud); + else if (f_tx_reg[3]) `ASSERT(f_tx_count == 7 * CLOCKS_PER_BAUD - 1 - f_tx_baud); + else if (f_tx_reg[2]) `ASSERT(f_tx_count == 8 * CLOCKS_PER_BAUD - 1 - f_tx_baud); + else if (f_tx_reg[1]) `ASSERT(f_tx_count == 9 * CLOCKS_PER_BAUD - 1 - f_tx_baud); + else if (f_tx_reg[0]) `ASSERT(f_tx_count == 10 * CLOCKS_PER_BAUD - 1 - f_tx_baud); + else `ASSERT(f_tx_count == 11 * CLOCKS_PER_BAUD - 1 - f_tx_baud); + initial f_rx_count = 0; + always @(posedge i_clk) + if (state == RXUL_IDLE) f_rx_count = (!ck_uart) ? (chg_counter + 2) : 0; + else f_rx_count <= f_rx_count + 1'b1; + always @(posedge i_clk) + if (state == 0) `ASSERT(f_rx_count == half_baud + (CLOCKS_PER_BAUD - baud_counter)); + else if (state == 1) `ASSERT(f_rx_count == half_baud + 2 * CLOCKS_PER_BAUD - baud_counter); + else if (state == 2) `ASSERT(f_rx_count == half_baud + 3 * CLOCKS_PER_BAUD - baud_counter); + else if (state == 3) `ASSERT(f_rx_count == half_baud + 4 * CLOCKS_PER_BAUD - baud_counter); + else if (state == 4) `ASSERT(f_rx_count == half_baud + 5 * CLOCKS_PER_BAUD - baud_counter); + else if (state == 5) `ASSERT(f_rx_count == half_baud + 6 * CLOCKS_PER_BAUD - baud_counter); + else if (state == 6) `ASSERT(f_rx_count == half_baud + 7 * CLOCKS_PER_BAUD - baud_counter); + else if (state == 7) `ASSERT(f_rx_count == half_baud + 8 * CLOCKS_PER_BAUD - baud_counter); + else if (state == 8) + `ASSERT( + (f_rx_count == half_baud + 9 * CLOCKS_PER_BAUD +- baud_counter) +||(f_rx_count == half_baud + 10 * CLOCKS_PER_BAUD +- baud_counter)); + always @(*) + `ASSERT( + ((!zero_baud_counter) +&&(state == RXUL_IDLE) +&&(baud_counter == 0)) +||((zero_baud_counter)&&(baud_counter == 0)) +||((!zero_baud_counter)&&(baud_counter != 0))); + always @(posedge i_clk) + if (!f_past_valid) + `ASSERT((state == RXUL_IDLE) && (baud_counter == 0) && (zero_baud_counter)); + always @(*) begin + `ASSERT({ck_uart, qq_uart, q_uart, i_uart_rx} != 4'h2); + `ASSERT({ck_uart, qq_uart, q_uart, i_uart_rx} != 4'h4); + `ASSERT({ck_uart, qq_uart, q_uart, i_uart_rx} != 4'h5); + `ASSERT({ck_uart, qq_uart, q_uart, i_uart_rx} != 4'h6); + `ASSERT({ck_uart, qq_uart, q_uart, i_uart_rx} != 4'h9); + `ASSERT({ck_uart, qq_uart, q_uart, i_uart_rx} != 4'ha); + `ASSERT({ck_uart, qq_uart, q_uart, i_uart_rx} != 4'hb); + `ASSERT({ck_uart, qq_uart, q_uart, i_uart_rx} != 4'hd); + end + always @(posedge i_clk) + if ((f_past_valid) && ($past(state) >= RXUL_WAIT) && ($past(ck_uart))) + `ASSERT(state == RXUL_IDLE); + always @(posedge i_clk) + if ((f_past_valid) && ($past( + state + ) >= RXUL_WAIT) && (($past( + state + ) != RXUL_IDLE) || (state == RXUL_IDLE))) + `ASSERT(zero_baud_counter); + always @(posedge i_clk) + if ((f_past_valid) && ($past(state) == RXUL_IDLE) && (state == RXUL_IDLE)) begin + `ASSERT(($past(ck_uart)) || (chg_counter <= {1'b0, CLOCKS_PER_BAUD[(TB-1):1]})); + end + always @(posedge f_txclk) + if (!f_past_valid_tx) + `ASSERT((state == RXUL_IDLE) && (baud_counter == 0) && (zero_baud_counter) && (!f_tx_busy)); + wire [(TB+3):0] f_tx_count_two_clocks_ago; + assign f_tx_count_two_clocks_ago = f_tx_count - 2; + always @(*) + if (f_tx_count >= f_rx_count + 2) f_baud_difference = f_tx_count_two_clocks_ago - f_rx_count; + else f_baud_difference = f_rx_count - f_tx_count_two_clocks_ago; + localparam F_SYNC_DLY = 8; + reg [(TB+4+F_CKRES-1):0] f_sub_baud_difference; + reg [F_CKRES-1:0] ck_tx_clock; + reg [((F_SYNC_DLY-1)*F_CKRES)-1:0] q_tx_clock; + reg [TB+3:0] ck_tx_count; + reg [(F_SYNC_DLY-1)*(TB+4)-1:0] q_tx_count; + initial q_tx_count = 0; + initial ck_tx_count = 0; + initial q_tx_clock = 0; + initial ck_tx_clock = 0; + always @($global_clock) {ck_tx_clock, q_tx_clock} <= {q_tx_clock, f_tx_clock}; + always @($global_clock) {ck_tx_count, q_tx_count} <= {q_tx_count, f_tx_count}; + reg [TB+4+F_CKRES-1:0] f_ck_tx_time, f_rx_time; + always @(*) f_ck_tx_time = {ck_tx_count, !ck_tx_clock[F_CKRES-1], ck_tx_clock[F_CKRES-2:0]}; + always @(*) f_rx_time = {f_rx_count, !f_rx_clock[1], f_rx_clock[0], {(F_CKRES - 2) {1'b0}}}; + reg [TB+4+F_CKRES-1:0] f_signed_difference; + always @(*) f_signed_difference = f_ck_tx_time - f_rx_time; + always @(*) + if (f_signed_difference[TB+4+F_CKRES-1]) f_sub_baud_difference = -f_signed_difference; + else f_sub_baud_difference = f_signed_difference; + always @($global_clock) if (state == RXUL_WAIT) `ASSERT((!f_tx_busy) || (f_tx_reg[9:1] == 0)); + always @($global_clock) + if (state == RXUL_IDLE) begin + `ASSERT((!f_tx_busy) || (f_tx_reg[9]) || (f_tx_reg[9:1] == 0)); + if (!ck_uart); + else `ASSERT((f_tx_reg[9:1] == 0) || (f_tx_count < (3 + CLOCKS_PER_BAUD / 2))); + end else if (state == 0) + `ASSERT(f_sub_baud_difference <= 2 * ((CLOCKS_PER_BAUD << F_CKRES) / 20)); + else if (state == 1) `ASSERT(f_sub_baud_difference <= 3 * ((CLOCKS_PER_BAUD << F_CKRES) / 20)); + else if (state == 2) `ASSERT(f_sub_baud_difference <= 4 * ((CLOCKS_PER_BAUD << F_CKRES) / 20)); + else if (state == 3) `ASSERT(f_sub_baud_difference <= 5 * ((CLOCKS_PER_BAUD << F_CKRES) / 20)); + else if (state == 4) `ASSERT(f_sub_baud_difference <= 6 * ((CLOCKS_PER_BAUD << F_CKRES) / 20)); + else if (state == 5) `ASSERT(f_sub_baud_difference <= 7 * ((CLOCKS_PER_BAUD << F_CKRES) / 20)); + else if (state == 6) `ASSERT(f_sub_baud_difference <= 8 * ((CLOCKS_PER_BAUD << F_CKRES) / 20)); + else if (state == 7) `ASSERT(f_sub_baud_difference <= 9 * ((CLOCKS_PER_BAUD << F_CKRES) / 20)); + else if (state == 8) `ASSERT(f_sub_baud_difference <= 10 * ((CLOCKS_PER_BAUD << F_CKRES) / 20)); + always @(posedge i_clk) if (o_wr) `ASSERT(o_data == $past(f_tx_data, 4)); + always @(posedge i_clk) begin + if (state == 4'h0) `ASSERT(!data_reg[7]); + if (state == 4'h1) `ASSERT((data_reg[7] == $past(f_tx_data[0])) && (!data_reg[6])); + if (state == 4'h2) `ASSERT(data_reg[7:6] == $past(f_tx_data[1:0])); + if (state == 4'h3) `ASSERT(data_reg[7:5] == $past(f_tx_data[2:0])); + if (state == 4'h4) `ASSERT(data_reg[7:4] == $past(f_tx_data[3:0])); + if (state == 4'h5) `ASSERT(data_reg[7:3] == $past(f_tx_data[4:0])); + if (state == 4'h6) `ASSERT(data_reg[7:2] == $past(f_tx_data[5:0])); + if (state == 4'h7) `ASSERT(data_reg[7:1] == $past(f_tx_data[6:0])); + if (state == 4'h8) `ASSERT(data_reg[7:0] == $past(f_tx_data[7:0])); + end + always @(posedge i_clk) cover (o_wr); + always @(posedge i_clk) begin + cover (!ck_uart); + cover ((f_past_valid) && ($rose(ck_uart))); + cover ((zero_baud_counter) && (state == RXUL_BIT_ZERO)); + cover ((zero_baud_counter) && (state == RXUL_BIT_ONE)); + cover ((zero_baud_counter) && (state == RXUL_BIT_TWO)); + cover ((zero_baud_counter) && (state == RXUL_BIT_THREE)); + cover ((zero_baud_counter) && (state == RXUL_BIT_FOUR)); + cover ((zero_baud_counter) && (state == RXUL_BIT_FIVE)); + cover ((zero_baud_counter) && (state == RXUL_BIT_SIX)); + cover ((zero_baud_counter) && (state == RXUL_BIT_SEVEN)); + cover ((zero_baud_counter) && (state == RXUL_STOP)); + cover ((zero_baud_counter) && (state == RXUL_WAIT)); + end +`endif +`ifdef FORMAL_VERILATOR + always @(*) assert ((state == 4'hf) || (state <= RXUL_WAIT)); + always @(*) assert (zero_baud_counter == (baud_counter == 0) ? 1'b1 : 1'b0); + always @(*) assert (baud_counter <= CLOCKS_PER_BAUD - 1'b1); +`endif +endmodule +" +"/* +Copyright (C) 2020-2021, Gisselquist Technology, LLC + +This program is free software (firmware): you can redistribute it and/or +modify it under the terms of the GNU General Public License as published +by the Free Software Foundation, either version 3 of the License, or (at +your option) any later version. + +This program is distributed in the hope that it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License along +with this program. (It's in the $(ROOT)/doc directory. Run make with no +target there if the PDF file isn't present.) If not, see + for a copy. + +License: GPL, v3, as defined and found on www.gnu.org, +http://www.gnu.org/licenses/gpl.html +*/ +`default_nettype none +module axiluart #( + parameter [30:0] INITIAL_SETUP = 31'd25, + parameter [3:0] LGFLEN = 4, + parameter [0:0] HARDWARE_FLOW_CONTROL_PRESENT = 1'b1, + parameter [3:0] LCLLGFLEN = (LGFLEN > 4'ha) ? 4'ha : ((LGFLEN < 4'h2) ? 4'h2 : LGFLEN), + parameter C_AXI_ADDR_WIDTH = 4, + parameter C_AXI_DATA_WIDTH = 32, + parameter [0:0] OPT_SKIDBUFFER = 1'b0, + parameter [0:0] OPT_LOWPOWER = 0, + parameter ADDRLSB = $clog2(C_AXI_DATA_WIDTH) - 3 +) ( + input wire S_AXI_ACLK, + input wire S_AXI_ARESETN, + input wire S_AXI_AWVALID, + output wire S_AXI_AWREADY, + input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR, + input wire [2:0] S_AXI_AWPROT, + input wire S_AXI_WVALID, + output wire S_AXI_WREADY, + input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA, + input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB, + output wire S_AXI_BVALID, + input wire S_AXI_BREADY, + output wire [1:0] S_AXI_BRESP, + input wire S_AXI_ARVALID, + output wire S_AXI_ARREADY, + input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR, + input wire [2:0] S_AXI_ARPROT, + output wire S_AXI_RVALID, + input wire S_AXI_RREADY, + output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA, + output wire [1:0] S_AXI_RRESP, + input wire i_uart_rx, + output wire o_uart_tx, + input wire i_cts_n, + output reg o_rts_n, + output wire o_uart_rx_int, + output wire o_uart_tx_int, + output wire o_uart_rxfifo_int, + output wire o_uart_txfifo_int +); + wire i_reset = !S_AXI_ARESETN; + wire axil_write_ready; + wire [C_AXI_ADDR_WIDTH-ADDRLSB-1:0] awskd_addr; + wire [C_AXI_DATA_WIDTH-1:0] wskd_data; + wire [C_AXI_DATA_WIDTH/8-1:0] wskd_strb; + reg axil_bvalid; + wire axil_read_ready; + wire [C_AXI_ADDR_WIDTH-ADDRLSB-1:0] arskd_addr; + reg [C_AXI_DATA_WIDTH-1:0] axil_read_data; + reg axil_read_valid; + wire tx_busy; + reg [30:0] uart_setup; + wire rx_stb, rx_break, rx_perr, rx_ferr, ck_uart; + wire [7:0] rx_uart_data; + reg rx_uart_reset; + wire rx_empty_n, rx_fifo_err; + wire [7:0] rxf_axil_data; + wire [15:0] rxf_status; + reg rxf_axil_read; + reg r_rx_perr, r_rx_ferr; + wire [(LCLLGFLEN-1):0] check_cutoff; + wire [31:0] axil_rx_data; + wire tx_empty_n, txf_err, tx_break; + wire [ 7:0] tx_data; + wire [15:0] txf_status; + reg txf_axil_write, tx_uart_reset; + reg [7:0] txf_axil_data; + wire [31:0] axil_tx_data; + wire [31:0] axil_fifo_data; + reg [1:0] r_axil_addr; + reg r_preread; + reg [31:0] new_setup; + generate + if (OPT_SKIDBUFFER) begin : SKIDBUFFER_WRITE + wire awskd_valid, wskd_valid; + skidbuffer #( + .OPT_OUTREG(0), + .OPT_LOWPOWER(OPT_LOWPOWER), + .DW(C_AXI_ADDR_WIDTH - ADDRLSB) + ) axilawskid ( + .i_clk (S_AXI_ACLK), + .i_reset(i_reset), + .i_valid(S_AXI_AWVALID), + .o_ready(S_AXI_AWREADY), + .i_data (S_AXI_AWADDR[C_AXI_ADDR_WIDTH-1:ADDRLSB]), + .o_valid(awskd_valid), + .i_ready(axil_write_ready), + .o_data (awskd_addr) + ); + skidbuffer #( + .OPT_OUTREG(0), + .OPT_LOWPOWER(OPT_LOWPOWER), + .DW(C_AXI_DATA_WIDTH + C_AXI_DATA_WIDTH / 8) + ) axilwskid ( + .i_clk (S_AXI_ACLK), + .i_reset(i_reset), + .i_valid(S_AXI_WVALID), + .o_ready(S_AXI_WREADY), + .i_data ({S_AXI_WDATA, S_AXI_WSTRB}), + .o_valid(wskd_valid), + .i_ready(axil_write_ready), + .o_data ({wskd_data, wskd_strb}) + ); + assign axil_write_ready = awskd_valid && wskd_valid && (!S_AXI_BVALID || S_AXI_BREADY); + end else begin : SIMPLE_WRITES + reg axil_awready; + initial axil_awready = 1'b0; + always @(posedge S_AXI_ACLK) + if (!S_AXI_ARESETN) axil_awready <= 1'b0; + else + axil_awready <= !axil_awready +&& (S_AXI_AWVALID && S_AXI_WVALID) +&& (!S_AXI_BVALID || S_AXI_BREADY); + assign S_AXI_AWREADY = axil_awready; + assign S_AXI_WREADY = axil_awready; + assign awskd_addr = S_AXI_AWADDR[C_AXI_ADDR_WIDTH-1:ADDRLSB]; + assign wskd_data = S_AXI_WDATA; + assign wskd_strb = S_AXI_WSTRB; + assign axil_write_ready = axil_awready; + end + endgenerate + initial axil_bvalid = 0; + always @(posedge S_AXI_ACLK) + if (i_reset) axil_bvalid <= 0; + else if (axil_write_ready) axil_bvalid <= 1; + else if (S_AXI_BREADY) axil_bvalid <= 0; + assign S_AXI_BVALID = axil_bvalid; + assign S_AXI_BRESP = 2'b00; + generate + if (OPT_SKIDBUFFER) begin : SKIDBUFFER_READ + wire arskd_valid; + skidbuffer #( + .OPT_OUTREG(0), + .OPT_LOWPOWER(OPT_LOWPOWER), + .DW(C_AXI_ADDR_WIDTH - ADDRLSB) + ) axilarskid ( + .i_clk (S_AXI_ACLK), + .i_reset(i_reset), + .i_valid(S_AXI_ARVALID), + .o_ready(S_AXI_ARREADY), + .i_data (S_AXI_ARADDR[C_AXI_ADDR_WIDTH-1:ADDRLSB]), + .o_valid(arskd_valid), + .i_ready(axil_read_ready), + .o_data (arskd_addr) + ); + assign axil_read_ready = arskd_valid && (!r_preread || !axil_read_valid || S_AXI_RREADY); + end else begin : SIMPLE_READS + reg axil_arready; + initial axil_arready = 1; + always @(posedge S_AXI_ACLK) + if (!S_AXI_ARESETN) axil_arready <= 1; + else if (S_AXI_ARVALID && S_AXI_ARREADY) axil_arready <= 0; + else if (S_AXI_RVALID && S_AXI_RREADY) axil_arready <= 1; + assign arskd_addr = S_AXI_ARADDR[C_AXI_ADDR_WIDTH-1:ADDRLSB]; + assign S_AXI_ARREADY = axil_arready; + assign axil_read_ready = (S_AXI_ARVALID && S_AXI_ARREADY); + end + endgenerate + initial axil_read_valid = 1'b0; + always @(posedge S_AXI_ACLK) + if (i_reset) axil_read_valid <= 1'b0; + else if (r_preread) axil_read_valid <= 1'b1; + else if (S_AXI_RREADY) axil_read_valid <= 1'b0; + assign S_AXI_RVALID = axil_read_valid; + assign S_AXI_RDATA = axil_read_data; + assign S_AXI_RRESP = 2'b00; + localparam [1:0] UART_SETUP = 2'b00, UART_FIFO = 2'b01, UART_RXREG = 2'b10, UART_TXREG = 2'b11; + always @(*) new_setup = apply_wstrb({1'b0, uart_setup}, wskd_data, wskd_strb); + initial uart_setup = INITIAL_SETUP | ((HARDWARE_FLOW_CONTROL_PRESENT == 1'b0) ? 31'h40000000 : 0); + always @(posedge S_AXI_ACLK) + if ((axil_write_ready) && (awskd_addr == UART_SETUP)) begin + uart_setup <= new_setup[30:0]; + if (!HARDWARE_FLOW_CONTROL_PRESENT) uart_setup[30] <= 1'b1; + end +`ifdef FORMAL + (* anyseq *) reg w_rx_break, w_rx_perr, w_rx_ferr, w_ck_uart; + assign rx_break = w_rx_break; + assign w_rx_perr = w_rx_perr; + assign w_rx_ferr = w_rx_ferr; + assign ck_uart = w_ck_uart; +`else +`ifdef USE_LITE_UART + rxuartlite #( + .CLOCKS_PER_BAUD(INITIAL_SETUP[23:0]) + ) rx ( + S_AXI_ACLK, + i_uart_rx, + rx_stb, + rx_uart_data + ); + assign rx_break = 1'b0; + assign rx_perr = 1'b0; + assign rx_ferr = 1'b0; + assign ck_uart = 1'b0; +`else + rxuart #( + .INITIAL_SETUP(INITIAL_SETUP) + ) rx ( + S_AXI_ACLK, + (!S_AXI_ARESETN) || (rx_uart_reset), + uart_setup, + i_uart_rx, + rx_stb, + rx_uart_data, + rx_break, + rx_perr, + rx_ferr, + ck_uart + ); +`endif +`endif + ufifo #( + .LGFLEN(LCLLGFLEN), + .RXFIFO(1) + ) rxfifo ( + S_AXI_ACLK, + (!S_AXI_ARESETN) || (rx_break) || (rx_uart_reset), + rx_stb, + rx_uart_data, + rx_empty_n, + rxf_axil_read, + rxf_axil_data, + rxf_status, + rx_fifo_err + ); + assign o_uart_rxfifo_int = rxf_status[1]; + assign o_uart_rx_int = rxf_status[0]; + assign check_cutoff = -3; + always @(posedge S_AXI_ACLK) + o_rts_n <= ((HARDWARE_FLOW_CONTROL_PRESENT) +&&(!uart_setup[30]) +&&(rxf_status[(LCLLGFLEN+1):2] > check_cutoff)); + initial rxf_axil_read = 1'b0; + always @(posedge S_AXI_ACLK) + rxf_axil_read <= (axil_read_ready) && (arskd_addr[1:0] == UART_RXREG); + initial r_rx_perr = 1'b0; + initial r_rx_ferr = 1'b0; + always @(posedge S_AXI_ACLK) + if ((rx_uart_reset) || (rx_break)) begin + r_rx_perr <= 1'b0; + r_rx_ferr <= 1'b0; + end else if (axil_write_ready && awskd_addr == UART_RXREG && wskd_strb[1]) begin + r_rx_perr <= (r_rx_perr) && (!wskd_data[9]); + r_rx_ferr <= (r_rx_ferr) && (!wskd_data[10]); + end else if (rx_stb) begin + r_rx_perr <= (r_rx_perr) || (rx_perr); + r_rx_ferr <= (r_rx_ferr) || (rx_ferr); + end + initial rx_uart_reset = 1'b1; + always @(posedge S_AXI_ACLK) + if ((!S_AXI_ARESETN) || ((axil_write_ready) && (awskd_addr[1:0] == UART_SETUP) && (&wskd_strb))) + rx_uart_reset <= 1'b1; + else if (axil_write_ready && (awskd_addr[1:0] == UART_RXREG) && wskd_strb[1]) + rx_uart_reset <= wskd_data[12]; + else rx_uart_reset <= 1'b0; + assign axil_rx_data = { + 16'h00, 3'h0, rx_fifo_err, rx_break, rx_ferr, r_rx_perr, !rx_empty_n, rxf_axil_data + }; + initial txf_axil_write = 1'b0; + always @(posedge S_AXI_ACLK) begin + txf_axil_write <= (axil_write_ready) && (awskd_addr == UART_TXREG) && wskd_strb[0]; + txf_axil_data <= wskd_data[7:0]; + end + ufifo #( + .LGFLEN(LGFLEN), + .RXFIFO(0) + ) txfifo ( + S_AXI_ACLK, + (tx_break) || (tx_uart_reset), + txf_axil_write, + txf_axil_data, + tx_empty_n, + (!tx_busy) && (tx_empty_n), + tx_data, + txf_status, + txf_err + ); + assign o_uart_tx_int = txf_status[0]; + assign o_uart_txfifo_int = txf_status[1]; +`ifndef USE_LITE_UART + reg r_tx_break; + initial r_tx_break = 1'b0; + always @(posedge S_AXI_ACLK) + if (!S_AXI_ARESETN) r_tx_break <= 1'b0; + else if (axil_write_ready && (awskd_addr[1:0] == UART_TXREG) && wskd_strb[1]) + r_tx_break <= wskd_data[9]; + assign tx_break = r_tx_break; +`else + assign tx_break = 1'b0; +`endif + initial tx_uart_reset = 1'b1; + always @(posedge S_AXI_ACLK) + if ((!S_AXI_ARESETN) || ((axil_write_ready) && (awskd_addr == UART_SETUP))) + tx_uart_reset <= 1'b1; + else if ((axil_write_ready) && (awskd_addr[1:0] == UART_TXREG) && wskd_strb[1]) + tx_uart_reset <= wskd_data[12]; + else tx_uart_reset <= 1'b0; +`ifdef FORMAL + (* anyseq *) reg w_uart_tx, w_tx_busy; + assign tx_busy = w_uart_tx; + assign o_uart_tx = w_uart_tx; +`else +`ifdef USE_LITE_UART + txuartlite #( + .CLOCKS_PER_BAUD(INITIAL_SETUP[23:0]) + ) tx ( + S_AXI_ACLK, + (tx_empty_n), + tx_data, + o_uart_tx, + tx_busy + ); +`else + wire cts_n; + assign cts_n = (HARDWARE_FLOW_CONTROL_PRESENT) && (i_cts_n); + txuart #( + .INITIAL_SETUP(INITIAL_SETUP) + ) tx ( + S_AXI_ACLK, + 1'b0, + uart_setup, + r_tx_break, + (tx_empty_n), + tx_data, + cts_n, + o_uart_tx, + tx_busy + ); +`endif +`endif + assign axil_tx_data = { + 16'h00, + i_cts_n, + txf_status[1:0], + txf_err, + ck_uart, + o_uart_tx, + tx_break, + (tx_busy | txf_status[0]), + (tx_busy | txf_status[0]) ? txf_axil_data : 8'b00 + }; + assign axil_fifo_data = {txf_status, rxf_status}; + initial r_preread = 0; + always @(posedge S_AXI_ACLK) + if (!S_AXI_ARESETN) r_preread <= 0; + else if (axil_read_ready) r_preread <= 1; + else if (!S_AXI_RVALID || S_AXI_RREADY) r_preread <= 0; + always @(posedge S_AXI_ACLK) if (axil_read_ready) r_axil_addr <= arskd_addr; + always @(posedge S_AXI_ACLK) + if (!S_AXI_RVALID || S_AXI_RREADY) begin + casez (r_axil_addr) + UART_SETUP: axil_read_data <= {1'b0, uart_setup}; + UART_FIFO: axil_read_data <= axil_fifo_data; + UART_RXREG: axil_read_data <= axil_rx_data; + UART_TXREG: axil_read_data <= axil_tx_data; + endcase + if (OPT_LOWPOWER && !r_preread) axil_read_data <= 0; + end + function [C_AXI_DATA_WIDTH-1:0] apply_wstrb; + input [C_AXI_DATA_WIDTH-1:0] prior_data; + input [C_AXI_DATA_WIDTH-1:0] new_data; + input [C_AXI_DATA_WIDTH/8-1:0] wstrb; + integer k; + for (k = 0; k < C_AXI_DATA_WIDTH / 8; k = k + 1) begin + apply_wstrb[k*8+:8] = wstrb[k] ? new_data[k*8+:8] : prior_data[k*8+:8]; + end + endfunction + wire unused; + assign unused = &{ 1'b0, S_AXI_AWPROT, S_AXI_ARPROT, +S_AXI_ARADDR[ADDRLSB-1:0], +S_AXI_AWADDR[ADDRLSB-1:0], new_setup[31] }; +`ifdef FORMAL + reg f_past_valid; + initial f_past_valid = 0; + always @(posedge S_AXI_ACLK) f_past_valid <= 1; + localparam F_AXIL_LGDEPTH = 4; + wire [F_AXIL_LGDEPTH-1:0] faxil_rd_outstanding, faxil_wr_outstanding, faxil_awr_outstanding; + faxil_slave #( + .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH), + .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH), + .F_LGDEPTH(F_AXIL_LGDEPTH), + .F_AXI_MAXWAIT(4), + .F_AXI_MAXDELAY(4), + .F_AXI_MAXRSTALL(3), + .F_OPT_COVER_BURST(4) + ) faxil ( + .i_clk(S_AXI_ACLK), + .i_axi_reset_n(S_AXI_ARESETN), + .i_axi_awvalid(S_AXI_AWVALID), + .i_axi_awready(S_AXI_AWREADY), + .i_axi_awaddr(S_AXI_AWADDR), + .i_axi_awcache(4'h0), + .i_axi_awprot(S_AXI_AWPROT), + .i_axi_wvalid(S_AXI_WVALID), + .i_axi_wready(S_AXI_WREADY), + .i_axi_wdata(S_AXI_WDATA), + .i_axi_wstrb(S_AXI_WSTRB), + .i_axi_bvalid(S_AXI_BVALID), + .i_axi_bready(S_AXI_BREADY), + .i_axi_bresp(S_AXI_BRESP), + .i_axi_arvalid(S_AXI_ARVALID), + .i_axi_arready(S_AXI_ARREADY), + .i_axi_araddr(S_AXI_ARADDR), + .i_axi_arcache(4'h0), + .i_axi_arprot(S_AXI_ARPROT), + .i_axi_rvalid(S_AXI_RVALID), + .i_axi_rready(S_AXI_RREADY), + .i_axi_rdata(S_AXI_RDATA), + .i_axi_rresp(S_AXI_RRESP), + .f_axi_rd_outstanding(faxil_rd_outstanding), + .f_axi_wr_outstanding(faxil_wr_outstanding), + .f_axi_awr_outstanding(faxil_awr_outstanding) + ); + always @(*) + if (OPT_SKIDBUFFER) begin + assert (faxil_awr_outstanding == (S_AXI_BVALID ? 1 : 0) + (S_AXI_AWREADY ? 0 : 1)); + assert (faxil_wr_outstanding == (S_AXI_BVALID ? 1 : 0) + (S_AXI_WREADY ? 0 : 1)); + assert(faxil_rd_outstanding == (S_AXI_RVALID ? 1:0) ++ (r_preread ? 1:0) +(S_AXI_ARREADY ? 0:1)); + end else begin + assert (faxil_wr_outstanding == (S_AXI_BVALID ? 1 : 0)); + assert (faxil_awr_outstanding == faxil_wr_outstanding); + assert (faxil_rd_outstanding == (S_AXI_RVALID ? 1 : 0) + (r_preread ? 1 : 0)); + assert (S_AXI_ARREADY == (!S_AXI_RVALID && !r_preread)); + end +`ifdef VERIFIC + assert property (@(posedge S_AXI_ACLK) +disable iff (!S_AXI_ARESETN || (S_AXI_RVALID && !S_AXI_RREADY)) +S_AXI_ARVALID && S_AXI_ARREADY && S_AXI_ARADDR[3:2]== UART_SETUP +|=> r_preread && r_axil_addr == UART_SETUP +##1 S_AXI_RVALID && axil_read_data +== { 1'b0, $past( + uart_setup + )}); + assert property (@(posedge S_AXI_ACLK) +disable iff (!S_AXI_ARESETN || (S_AXI_RVALID && !S_AXI_RREADY)) +S_AXI_ARVALID && S_AXI_ARREADY && S_AXI_ARADDR[3:2] == UART_FIFO +|=> r_preread && r_axil_addr == UART_FIFO +##1 S_AXI_RVALID && axil_read_data == $past( + axil_fifo_data + )); + assert property (@(posedge S_AXI_ACLK) +disable iff (!S_AXI_ARESETN || (S_AXI_RVALID && !S_AXI_RREADY)) +S_AXI_ARVALID && S_AXI_ARREADY && S_AXI_ARADDR[3:2]== UART_RXREG +|=> r_preread && r_axil_addr == UART_RXREG +##1 S_AXI_RVALID && axil_read_data == $past( + axil_rx_data + )); + assert property (@(posedge S_AXI_ACLK) +disable iff (!S_AXI_ARESETN || (S_AXI_RVALID && !S_AXI_RREADY)) +S_AXI_ARVALID && S_AXI_ARREADY && S_AXI_ARADDR[3:2]== UART_TXREG +|=> r_preread && r_axil_addr == UART_TXREG +##1 S_AXI_RVALID && axil_read_data == $past( + axil_tx_data + )); +`endif + always @(*) if (OPT_LOWPOWER && !S_AXI_RVALID) assert (S_AXI_RDATA == 0); +`endif +endmodule +" +"import json + +struct User { +\tname string +\tage int +mut: +\tis_registered bool +} + +fn main() { +\ts := \'[{""name"":""Frodo"", ""age"":25}, {""name"":""Bobby"", ""age"":10}]\' +\tusers := json.decode([]User, s) or { +\t\teprintln(\'Failed to parse json\') +\t\treturn +\t} +\tfor user in users { +\t\tprintln(\'$user.name: $user.age\') +\t} +\tprintln(\'\') +\tfor i, user in users { +\t\tprintln(\'$i) $user.name\') +\t\tif !user.can_register() { +\t\t\tprintln(\'Cannot register $user.name, they are too young\') +\t\t\tcontinue +\t\t} +\t\tusers[i].register() // `user` is immutable, we have to modify the array +\t} +\t// Let\'s encode users again just for fun +\tprintln(\'\') +\tprintln(json.encode(users)) +} + +fn (u User) can_register() bool { + return u.age >= 16 +} + +fn (u mut User) register() { + u.is_registered = true +}" +"/* +Copyright (C) 2015-2021, Gisselquist Technology, LLC + +This program is free software (firmware): you can redistribute it and/or +modify it under the terms of the GNU General Public License as published +by the Free Software Foundation, either version 3 of the License, or (at +your option) any later version. + +This program is distributed in the hope that it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License along +with this program. (It's in the $(ROOT)/doc directory. Run make with no +target there if the PDF file isn't present.) If not, see + for a copy. + +License: GPL, v3, as defined and found on www.gnu.org, +http://www.gnu.org/licenses/gpl.html +*/ +`default_nettype none +module wbuart #( + parameter [30:0] INITIAL_SETUP = 31'd25, + parameter [3:0] LGFLEN = 4, + parameter [0:0] HARDWARE_FLOW_CONTROL_PRESENT = 1'b1, + parameter [3:0] LCLLGFLEN = (LGFLEN > 4'ha) ? 4'ha : ((LGFLEN < 4'h2) ? 4'h2 : LGFLEN) +) ( + input wire i_clk, + i_reset, + input wire i_wb_cyc, + input wire i_wb_stb, + i_wb_we, + input wire [1:0] i_wb_addr, + input wire [31:0] i_wb_data, + input wire [3:0] i_wb_sel, + output wire o_wb_stall, + output reg o_wb_ack, + output reg [31:0] o_wb_data, + input wire i_uart_rx, + output wire o_uart_tx, + input wire i_cts_n, + output reg o_rts_n, + output wire o_uart_rx_int, + o_uart_tx_int, + o_uart_rxfifo_int, + o_uart_txfifo_int +); + localparam [1:0] UART_SETUP = 2'b00, UART_FIFO = 2'b01, UART_RXREG = 2'b10, UART_TXREG = 2'b11; + wire tx_busy; + reg [30:0] uart_setup; + wire rx_stb, rx_break, rx_perr, rx_ferr, ck_uart; + wire [7:0] rx_uart_data; + reg rx_uart_reset; + wire rx_empty_n, rx_fifo_err; + wire [7:0] rxf_wb_data; + wire [15:0] rxf_status; + reg rxf_wb_read; + wire [(LCLLGFLEN-1):0] check_cutoff; + reg r_rx_perr, r_rx_ferr; + wire [31:0] wb_rx_data; + wire tx_empty_n, txf_err, tx_break; + wire [ 7:0] tx_data; + wire [15:0] txf_status; + reg txf_wb_write, tx_uart_reset; + reg [7:0] txf_wb_data; + wire [31:0] wb_tx_data; + wire [31:0] wb_fifo_data; + reg [1:0] r_wb_addr; + reg r_wb_ack; + initial uart_setup = INITIAL_SETUP | ((HARDWARE_FLOW_CONTROL_PRESENT == 1'b0) ? 31'h40000000 : 0); + always @(posedge i_clk) + if ((i_wb_stb) && (i_wb_addr == UART_SETUP) && (i_wb_we)) begin + if (i_wb_sel[0]) uart_setup[7:0] <= i_wb_data[7:0]; + if (i_wb_sel[1]) uart_setup[15:8] <= i_wb_data[15:8]; + if (i_wb_sel[2]) uart_setup[23:16] <= i_wb_data[23:16]; + if (i_wb_sel[3]) + uart_setup[30:24] <= { + (i_wb_data[30]) || (!HARDWARE_FLOW_CONTROL_PRESENT), i_wb_data[29:24] + }; + end +`ifdef USE_LITE_UART + rxuartlite #( + .CLOCKS_PER_BAUD(INITIAL_SETUP[23:0]) + ) rx ( + i_clk, + i_uart_rx, + rx_stb, + rx_uart_data + ); + assign rx_break = 1'b0; + assign rx_perr = 1'b0; + assign rx_ferr = 1'b0; + assign ck_uart = 1'b0; +`else + rxuart #( + .INITIAL_SETUP(INITIAL_SETUP) + ) rx ( + i_clk, + (i_reset) || (rx_uart_reset), + uart_setup, + i_uart_rx, + rx_stb, + rx_uart_data, + rx_break, + rx_perr, + rx_ferr, + ck_uart + ); +`endif + ufifo #( + .LGFLEN(LCLLGFLEN), + .RXFIFO(1) + ) rxfifo ( + i_clk, + (i_reset) || (rx_break) || (rx_uart_reset), + rx_stb, + rx_uart_data, + rx_empty_n, + rxf_wb_read, + rxf_wb_data, + rxf_status, + rx_fifo_err + ); + assign o_uart_rxfifo_int = rxf_status[1]; + assign o_uart_rx_int = rxf_status[0]; + assign check_cutoff = -3; + always @(posedge i_clk) + o_rts_n <= ((HARDWARE_FLOW_CONTROL_PRESENT) +&&(!uart_setup[30]) +&&(rxf_status[(LCLLGFLEN+1):2] > check_cutoff)); + initial rxf_wb_read = 1'b0; + always @(posedge i_clk) rxf_wb_read <= (i_wb_stb) && (i_wb_addr[1:0] == UART_RXREG) && (!i_wb_we); + initial r_rx_perr = 1'b0; + initial r_rx_ferr = 1'b0; + always @(posedge i_clk) + if ((rx_uart_reset) || (rx_break)) begin + r_rx_perr <= 1'b0; + r_rx_ferr <= 1'b0; + end else if ((i_wb_stb) && (i_wb_addr[1:0] == UART_RXREG) && (i_wb_we)) begin + if (i_wb_sel[1]) begin + r_rx_perr <= (r_rx_perr) && (~i_wb_data[9]); + r_rx_ferr <= (r_rx_ferr) && (~i_wb_data[10]); + end + end else if (rx_stb) begin + r_rx_perr <= (r_rx_perr) || (rx_perr); + r_rx_ferr <= (r_rx_ferr) || (rx_ferr); + end + initial rx_uart_reset = 1'b1; + always @(posedge i_clk) + if ((i_reset) || ((i_wb_stb) && (i_wb_addr[1:0] == UART_SETUP) && (i_wb_we))) + rx_uart_reset <= 1'b1; + else if ((i_wb_stb) && (i_wb_addr[1:0] == UART_RXREG) && (i_wb_we) && i_wb_sel[1]) + rx_uart_reset <= i_wb_data[12]; + else rx_uart_reset <= 1'b0; + assign wb_rx_data = { + 16'h00, 3'h0, rx_fifo_err, rx_break, rx_ferr, r_rx_perr, !rx_empty_n, rxf_wb_data + }; + initial txf_wb_write = 1'b0; + always @(posedge i_clk) begin + txf_wb_write <= (i_wb_stb) && (i_wb_addr == UART_TXREG) && (i_wb_we) && (i_wb_sel[0]); + txf_wb_data <= i_wb_data[7:0]; + end + ufifo #( + .LGFLEN(LGFLEN), + .RXFIFO(0) + ) txfifo ( + i_clk, + (tx_break) || (tx_uart_reset), + txf_wb_write, + txf_wb_data, + tx_empty_n, + (!tx_busy) && (tx_empty_n), + tx_data, + txf_status, + txf_err + ); + assign o_uart_tx_int = txf_status[0]; + assign o_uart_txfifo_int = txf_status[1]; +`ifndef USE_LITE_UART + reg r_tx_break; + initial r_tx_break = 1'b0; + always @(posedge i_clk) + if (i_reset) r_tx_break <= 1'b0; + else if ((i_wb_stb) && (i_wb_addr[1:0] == UART_TXREG) && (i_wb_we) && (i_wb_sel[1])) + r_tx_break <= i_wb_data[9]; + assign tx_break = r_tx_break; +`else + assign tx_break = 1'b0; +`endif + initial tx_uart_reset = 1'b1; + always @(posedge i_clk) + if ((i_reset) || ((i_wb_stb) && (i_wb_addr == UART_SETUP) && (i_wb_we))) tx_uart_reset <= 1'b1; + else if ((i_wb_stb) && (i_wb_addr[1:0] == UART_TXREG) && (i_wb_we) && i_wb_sel[1]) + tx_uart_reset <= i_wb_data[12]; + else tx_uart_reset <= 1'b0; +`ifdef USE_LITE_UART + txuartlite #( + .CLOCKS_PER_BAUD(INITIAL_SETUP[23:0]) + ) tx ( + i_clk, + (tx_empty_n), + tx_data, + o_uart_tx, + tx_busy + ); +`else + wire cts_n; + assign cts_n = (HARDWARE_FLOW_CONTROL_PRESENT) && (i_cts_n); + txuart #( + .INITIAL_SETUP(INITIAL_SETUP) + ) tx ( + i_clk, + 1'b0, + uart_setup, + r_tx_break, + (tx_empty_n), + tx_data, + cts_n, + o_uart_tx, + tx_busy + ); +`endif + assign wb_tx_data = { + 16'h00, + i_cts_n, + txf_status[1:0], + txf_err, + ck_uart, + o_uart_tx, + tx_break, + (tx_busy | txf_status[0]), + (tx_busy | txf_status[0]) ? txf_wb_data : 8'b00 + }; + assign wb_fifo_data = {txf_status, rxf_status}; + always @(posedge i_clk) r_wb_addr <= i_wb_addr; + initial r_wb_ack = 1'b0; + always @(posedge i_clk) r_wb_ack <= i_wb_stb; + initial o_wb_ack = 1'b0; + always @(posedge i_clk) o_wb_ack <= i_wb_cyc && r_wb_ack; + always @(posedge i_clk) + casez (r_wb_addr) + UART_SETUP: o_wb_data <= {1'b0, uart_setup}; + UART_FIFO: o_wb_data <= wb_fifo_data; + UART_RXREG: o_wb_data <= wb_rx_data; + UART_TXREG: o_wb_data <= wb_tx_data; + endcase + assign o_wb_stall = 1'b0; + wire unused; + assign unused = &{1'b0, i_wb_data[31]}; +endmodule +" +"fn main() { +\tareas := ['game', 'web', 'tools', 'science', 'systems', +\t 'embedded', 'GUI', 'mobile'] +\tfor area in areas { +\t\tprintln('Hello, $area developers!') +\t} +}" +"import os + +// Print file lines that starth with ""DEBUG:"" +fn main() { +\t// `read_file` returns an optional (`?string`), it must be checked +\ttext := os.read_file(\'app.log\') or { +\t\tprintln(\'failed to read the file\') +\t\treturn +\t} +\tlines := text.split_into_lines() +\tfor line in lines { +\t\tif line.starts_with(\'DEBUG:\') { +\t\t\tprintln(line) +\t\t} +\t} +} +" +"/* +Copyright (C) 2015-2021, Gisselquist Technology, LLC + +This program is free software (firmware): you can redistribute it and/or +modify it under the terms of the GNU General Public License as published +by the Free Software Foundation, either version 3 of the License, or (at +your option) any later version. + +This program is distributed in the hope that it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License along +with this program. (It's in the $(ROOT)/doc directory. Run make with no +target there if the PDF file isn't present.) If not, see + for a copy. + +License: GPL, v3, as defined and found on www.gnu.org, +http://www.gnu.org/licenses/gpl.html +*/ +`default_nettype none +module txuartlite #( + parameter [4:0] TIMING_BITS = 5'd24, + parameter TB = TIMING_BITS, + parameter [(TB-1):0] CLOCKS_PER_BAUD = 8 +) ( + input wire i_clk, + input wire i_wr, + input wire [7:0] i_data, + output reg o_uart_tx, + output wire o_busy +); + localparam [3:0] TXUL_BIT_ZERO = 4'h0, TXUL_STOP = 4'h8, TXUL_IDLE = 4'hf; + reg [(TB-1):0] baud_counter; + reg [3:0] state; + reg [7:0] lcl_data; + reg r_busy, zero_baud_counter; + initial r_busy = 1'b1; + initial state = TXUL_IDLE; + always @(posedge i_clk) begin + if (!zero_baud_counter) r_busy <= 1'b1; + else if (state > TXUL_STOP) begin + state <= TXUL_IDLE; + r_busy <= 1'b0; + if ((i_wr) && (!r_busy)) begin + r_busy <= 1'b1; + state <= TXUL_BIT_ZERO; + end + end else begin + r_busy <= 1'b1; + if (state <= TXUL_STOP) state <= state + 1'b1; + else state <= TXUL_IDLE; + end + end + assign o_busy = (r_busy); + initial lcl_data = 8'hff; + always @(posedge i_clk) + if ((i_wr) && (!r_busy)) lcl_data <= i_data; + else if (zero_baud_counter) lcl_data <= {1'b1, lcl_data[7:1]}; + initial o_uart_tx = 1'b1; + always @(posedge i_clk) + if ((i_wr) && (!r_busy)) o_uart_tx <= 1'b0; + else if (zero_baud_counter) o_uart_tx <= lcl_data[0]; + initial zero_baud_counter = 1'b1; + initial baud_counter = 0; + always @(posedge i_clk) begin + zero_baud_counter <= (baud_counter == 1); + if (state == TXUL_IDLE) begin + baud_counter <= 0; + zero_baud_counter <= 1'b1; + if ((i_wr) && (!r_busy)) begin + baud_counter <= CLOCKS_PER_BAUD - 1'b1; + zero_baud_counter <= 1'b0; + end + end else if (!zero_baud_counter) baud_counter <= baud_counter - 1'b1; + else if (state > TXUL_STOP) begin + baud_counter <= 0; + zero_baud_counter <= 1'b1; + end else if (state == TXUL_STOP) baud_counter <= CLOCKS_PER_BAUD - 2; + else baud_counter <= CLOCKS_PER_BAUD - 1'b1; + end +`ifdef FORMAL +`ifdef TXUARTLITE + `define ASSUME assume +`else + `define ASSUME assert +`endif + reg f_past_valid, f_last_clk; + reg [(TB-1):0] f_baud_count; + reg [9:0] f_txbits; + reg [3:0] f_bitcount; + reg [7:0] f_request_tx_data; + wire [3:0] subcount; + initial f_past_valid = 1'b0; + always @(posedge i_clk) f_past_valid <= 1'b1; + initial `ASSUME(!i_wr); + always @(posedge i_clk) + if ((f_past_valid) && ($past(i_wr)) && ($past(o_busy))) begin + `ASSUME(i_wr == $past(i_wr)); + `ASSUME(i_data == $past(i_data)); + end + always @(posedge i_clk) assert (zero_baud_counter == (baud_counter == 0)); + always @(posedge i_clk) + if ((f_past_valid) && ($past(baud_counter != 0)) && ($past(state != TXUL_IDLE))) + assert (baud_counter == $past(baud_counter - 1'b1)); + always @(posedge i_clk) + if ((f_past_valid) && (!$past(zero_baud_counter)) && ($past(state != TXUL_IDLE))) + assert ($stable(o_uart_tx)); + initial f_baud_count = 1'b0; + always @(posedge i_clk) + if (zero_baud_counter) f_baud_count <= 0; + else f_baud_count <= f_baud_count + 1'b1; + always @(posedge i_clk) assert (f_baud_count < CLOCKS_PER_BAUD); + always @(posedge i_clk) if (baud_counter != 0) assert (o_busy); + initial f_txbits = 0; + always @(posedge i_clk) if (zero_baud_counter) f_txbits <= {o_uart_tx, f_txbits[9:1]}; + always @(posedge i_clk) + if ((f_past_valid) && (!$past(zero_baud_counter)) && (!$past(state == TXUL_IDLE))) + assert (state == $past(state)); + initial f_bitcount = 0; + always @(posedge i_clk) + if ((!f_past_valid) || (!$past(f_past_valid))) f_bitcount <= 0; + else if ((state == TXUL_IDLE) && (zero_baud_counter)) f_bitcount <= 0; + else if (zero_baud_counter) f_bitcount <= f_bitcount + 1'b1; + always @(posedge i_clk) assert (f_bitcount <= 4'ha); + always @(*) if (!o_busy) assert (zero_baud_counter); + always @(posedge i_clk) if ((i_wr) && (!o_busy)) f_request_tx_data <= i_data; + assign subcount = 10 - f_bitcount; + always @(posedge i_clk) if (f_bitcount > 0) assert (!f_txbits[subcount]); + always @(posedge i_clk) + if (f_bitcount == 4'ha) begin + assert (f_txbits[8:1] == f_request_tx_data); + assert (f_txbits[9]); + end + always @(posedge i_clk) assert ((state <= TXUL_STOP + 1'b1) || (state == TXUL_IDLE)); + always @(posedge i_clk) + if ((f_past_valid) && ($past(f_past_valid)) && ($past(o_busy))) + cover (!o_busy); +`endif +`ifdef VERIFIC_SVA + reg [7:0] fsv_data; + always @(posedge i_clk) if ((i_wr) && (!o_busy)) fsv_data <= i_data; + sequence BAUD_INTERVAL(CKS, DAT, SR, ST); + ((o_uart_tx == DAT)&&(state == ST) +&&(lcl_data == SR) +&&(!zero_baud_counter))[*(CKS-1)] +##1 (o_uart_tx == DAT)&&(state == ST) +&&(lcl_data == SR) +&&(zero_baud_counter); + endsequence + sequence SEND(CKS, DATA); + BAUD_INTERVAL( + CKS, 1'b0, DATA, 4'h0 + ) ##1 BAUD_INTERVAL( + CKS, DATA[0], {{(1) {1'b1}}, DATA[7:1]}, 4'h1 + ) ##1 BAUD_INTERVAL( + CKS, DATA[1], {{(2) {1'b1}}, DATA[7:2]}, 4'h2 + ) ##1 BAUD_INTERVAL( + CKS, DATA[2], {{(3) {1'b1}}, DATA[7:3]}, 4'h3 + ) ##1 BAUD_INTERVAL( + CKS, DATA[3], {{(4) {1'b1}}, DATA[7:4]}, 4'h4 + ) ##1 BAUD_INTERVAL( + CKS, DATA[4], {{(5) {1'b1}}, DATA[7:5]}, 4'h5 + ) ##1 BAUD_INTERVAL( + CKS, DATA[5], {{(6) {1'b1}}, DATA[7:6]}, 4'h6 + ) ##1 BAUD_INTERVAL( + CKS, DATA[6], {{(7) {1'b1}}, DATA[7:7]}, 4'h7 + ) ##1 BAUD_INTERVAL( + CKS, DATA[7], 8'hff, 4'h8 + ) ##1 BAUD_INTERVAL( + CKS - 1, 1'b1, 8'hff, 4'h9 + ); + endsequence + assert property (@(posedge i_clk) (i_wr) && (!o_busy) |=> ((o_busy) throughout SEND( + CLOCKS_PER_BAUD, fsv_data + )) ##1 (!o_busy) && (o_uart_tx) && (zero_baud_counter)); + assume property (@(posedge i_clk) (i_wr) && (o_busy) |=> (i_wr) && ($stable(i_data))); + always @(*) assert ((o_busy) || (zero_baud_counter)); + always @(*) assert (zero_baud_counter == (baud_counter == 0)); + always @(*) assert (baud_counter < CLOCKS_PER_BAUD); + always @(*) assert ((state <= TXUL_STOP + 1'b1) || (state == TXUL_IDLE)); +`endif +endmodule +" +"/* +Copyright (c) 2001 Stephan Boettcher + +This source code is free software; you can redistribute it +and/or modify it in source code form under the terms of the GNU +General Public License as published by the Free Software +Foundation; either version 2 of the License, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +*/ +module test_lfsr; + reg cp; + reg in; + wire out; + reg reset; + lfsr sr ( + cp, + reset, + in, + out + ); + reg errors; + initial errors = 0; + integer i; + initial begin + in = 0; + cp = 0; + #2 reset = 1; + #2 reset = 0; + #1; + for (i = 0; i < 512; i = i + 1) #5 cp = ~cp; + in = 0; + cp = 0; + #2 reset = 1; + #2 reset = 0; + #1; + for (i = 0; i < 512; i = i + 1) #5 cp <= ~cp; + #5; + if (errors == 0) $display(""PASSED""); + #10 $finish; + end + reg [7:0] here; + reg [7:0] next; + reg [7:0] old_val; + reg [7:0] new_val; + always @(reset) + if (reset) begin + here = 1; + #1; + old_val = {out, sr.s}; + if (old_val === here) begin + $display(""%b RESET"", old_val); + end else begin + $display(""%b RESET FAILED: expect %b"", old_val, here); + errors = 1; + end + end + always begin + @(posedge cp) old_val = {out, sr.s}; + next = {here[6:0], ^(here & sr.P) ^ in}; + @(negedge cp) new_val = {out, sr.s}; + if (old_val != here || new_val !== next) begin + $display(""%b->%b FAILED: expect %b->%b"", old_val, new_val, here, next); + errors = 1; + end else begin + $display(""%b->%b"", old_val, new_val); + end + here = next; + end +endmodule +module lfsr ( + clk, + reset, + in, + out +); + parameter P = 8\'b1101_1001; + input clk; + input reset; + input in; + output out; + wire [6:0] s; + wire i = ^{P &{out, s}} ^ in; + jkff ff1 ( + s[0], + clk, + i, + ~i, + reset, + 0 + ); + jkff ff2 ( + s[1], + clk, + s[0], + ~s[0], + 0, + reset + ); + jkff ff3 ( + s[2], + clk, + s[1], + ~s[1], + 0, + reset + ); + jkff ff4 ( + s[3], + clk, + s[2], + ~s[2], + 0, + reset + ); + jkff ff8 ( + out, + clk, + s[6], + ~s[6], + 0, + reset + ); + jkff ff7 ( + s[6], + clk, + s[5], + ~s[5], + 0, + reset + ); + jkff ff6 ( + s[5], + clk, + s[4], + ~s[4], + 0, + reset + ); + jkff ff5 ( + s[4], + clk, + s[3], + ~s[3], + 0, + reset + ); +endmodule +primitive jkff(q, cp, j, k, s, r); + output q; + input cp, j, k, s, r; + reg q; + table + ? ? ? (?0) 0 : ? : -; + ? ? ? 0 (?0) : ? : -; + ? * ? 0 0 : ? : -; + ? ? * 0 0 : ? : -; + ? ? ? 1 0 : ? : 1; + ? ? ? 0 1 : ? : 0; + ? ? ? x 0 : 1 : 1; + ? ? ? 0 x : 0 : 0; + (?0) ? ? 0 0 : ? : -; + (1x) ? ? 0 0 : ? : -; + (?1) 0 ? 0 0 : 0 : 0; + (?1) ? 0 0 0 : 1 : 1; + (0x) 0 ? 0 0 : 0 : 0; + (0x) ? 0 0 0 : 1 : 1; + (01) 1 ? 0 0 : 0 : 1; + (01) ? 1 0 0 : 1 : 0; + (01) 1 0 0 0 : x : 1; + (01) 0 1 0 0 : x : 0; + endtable +endprimitive +" +"`timescale 1ns / 1ps + +module toplevel( + input io_J3, + input io_H16, + input io_G15, + output io_G16, + input io_F15, + output io_B12, + input io_B10, + output [7:0] io_led + ); + + wire [31:0] io_gpioA_read; + wire [31:0] io_gpioA_write; + wire [31:0] io_gpioA_writeEnable; + wire io_mainClk; + wire io_jtag_tck; + + SB_GB mainClkBuffer ( + .USER_SIGNAL_TO_GLOBAL_BUFFER (io_J3), + .GLOBAL_BUFFER_OUTPUT ( io_mainClk) + ); + + SB_GB jtagClkBuffer ( + .USER_SIGNAL_TO_GLOBAL_BUFFER (io_H16), + .GLOBAL_BUFFER_OUTPUT ( io_jtag_tck) + ); + + assign io_led = io_gpioA_write[7 : 0]; + + Murax murax ( + .io_asyncReset(0), + .io_mainClk (io_mainClk ), + .io_jtag_tck(io_jtag_tck), + .io_jtag_tdi(io_G15), + .io_jtag_tdo(io_G16), + .io_jtag_tms(io_F15), + .io_gpioA_read (io_gpioA_read), + .io_gpioA_write (io_gpioA_write), + .io_gpioA_writeEnable(io_gpioA_writeEnable), + .io_uart_txd(io_B12), + .io_uart_rxd(io_B10) + );\t\t +endmodule" +"module toplevel_pll(REFERENCECLK, + PLLOUTCORE, + PLLOUTGLOBAL, + RESET); + +input REFERENCECLK; +input RESET; /* To initialize the simulation properly, the RESET signal (Active Low) must be asserted at the beginning of the simulation */ +output PLLOUTCORE; +output PLLOUTGLOBAL; + +SB_PLL40_CORE toplevel_pll_inst(.REFERENCECLK(REFERENCECLK), + .PLLOUTCORE(PLLOUTCORE), + .PLLOUTGLOBAL(PLLOUTGLOBAL), + .EXTFEEDBACK(), + .DYNAMICDELAY(), + .RESETB(RESET), + .BYPASS(1\'b0), + .LATCHINPUTVALUE(), + .LOCK(), + .SDI(), + .SDO(), + .SCLK()); + +//\\\\ Fin=100, Fout=12; +defparam toplevel_pll_inst.DIVR = 4\'b0010; +defparam toplevel_pll_inst.DIVF = 7\'b0010110; +defparam toplevel_pll_inst.DIVQ = 3\'b110; +defparam toplevel_pll_inst.FILTER_RANGE = 3\'b011; +defparam toplevel_pll_inst.FEEDBACK_PATH = ""SIMPLE""; +defparam toplevel_pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = ""FIXED""; +defparam toplevel_pll_inst.FDA_FEEDBACK = 4\'b0000; +defparam toplevel_pll_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = ""FIXED""; +defparam toplevel_pll_inst.FDA_RELATIVE = 4\'b0000; +defparam toplevel_pll_inst.SHIFTREG_DIV_MODE = 2\'b00; +defparam toplevel_pll_inst.PLLOUT_SELECT = ""GENCLK""; +defparam toplevel_pll_inst.ENABLE_ICEGATE = 1\'b0; + +endmodule +" +"`timescale 1ns / 1ps + +module toplevel( + input wire clk100, + input wire cpu_reset,//active low + + input wire tck, + input wire tms, + input wire tdi, + input wire trst,//ignored + output reg tdo, + + input wire serial_rx, + output wire serial_tx, + + input wire user_sw0, + input wire user_sw1, + input wire user_sw2, + input wire user_sw3, + + input wire user_btn0, + input wire user_btn1, + input wire user_btn2, + input wire user_btn3, + + output wire user_led0, + output wire user_led1, + output wire user_led2, + output wire user_led3 + ); + + wire [31:0] io_gpioA_read; + wire [31:0] io_gpioA_write; + wire [31:0] io_gpioA_writeEnable; + + wire io_asyncReset = ~cpu_reset; + + assign {user_led3,user_led2,user_led1,user_led0} = io_gpioA_write[3 : 0]; + assign io_gpioA_read[3:0] = {user_sw3,user_sw2,user_sw1,user_sw0}; + assign io_gpioA_read[7:4] = {user_btn3,user_btn2,user_btn1,user_btn0}; + assign io_gpioA_read[11:8] = {tck,tms,tdi,trst}; + + reg tesic_tck,tesic_tms,tesic_tdi; + wire tesic_tdo; + reg soc_tck,soc_tms,soc_tdi; + wire soc_tdo; + + always @(*) begin + {soc_tck, soc_tms, soc_tdi } = {tck,tms,tdi}; + tdo = soc_tdo; + end + + Murax core ( + .io_asyncReset(io_asyncReset), + .io_mainClk (clk100 ), + .io_jtag_tck(soc_tck), + .io_jtag_tdi(soc_tdi), + .io_jtag_tdo(soc_tdo), + .io_jtag_tms(soc_tms), + .io_gpioA_read (io_gpioA_read), + .io_gpioA_write (io_gpioA_write), + .io_gpioA_writeEnable(io_gpioA_writeEnable), + .io_uart_txd(serial_tx), + .io_uart_rxd(serial_rx) + ); +endmodule +" +"`timescale 1ns / 1ps + +module toplevel( + input CLK, + input BUT1, + input BUT2, + output LED1, + output LED2 + ); + + assign LED1 = io_gpioA_write[0]; + assign LED2 = io_gpioA_write[7]; + + wire [31:0] io_gpioA_read; + wire [31:0] io_gpioA_write; + wire [31:0] io_gpioA_writeEnable; + wire io_mainClk; + + // Use PLL to downclock external clock. + toplevel_pll toplevel_pll_inst(.REFERENCECLK(CLK), + .PLLOUTCORE(io_mainClk), + .PLLOUTGLOBAL(), + .RESET(1'b1)); + + Murax murax ( + .io_asyncReset(1'b0), + .io_mainClk (io_mainClk), + .io_jtag_tck(1'b0), + .io_jtag_tdi(1'b0), + .io_jtag_tdo(), + .io_jtag_tms(1'b0), + .io_gpioA_read (io_gpioA_read), + .io_gpioA_write (io_gpioA_write), + .io_gpioA_writeEnable(io_gpioA_writeEnable), + .io_uart_txd(), + .io_uart_rxd(0'b0) + ); + +endmodule +" +"module ghrd_10m50da_top ( + //Clock and Reset + input wire clk_50, + input wire fpga_reset_n, + //QSPI +// output wire \t qspi_clk, +// inout wire[3:0] qspi_io, +// output wire qspi_csn, + //16550 UART + input wire\t uart_rx, + output wire \t\t uart_tx, + output wire [4:0] user_led +); +//Heart-beat counter +reg [25:0] heart_beat_cnt; + +// SoC sub-system module +ghrd_10m50da ghrd_10m50da_inst ( +\t\t.clk_clk (clk_50), +\t\t.reset_reset_n (fpga_reset_n), +//\t\t.ext_flash_flash_dataout_conduit_dataout (qspi_io), +//\t\t.ext_flash_flash_dclk_out_conduit_dclk_out (qspi_clk), +//\t\t.ext_flash_flash_ncs_conduit_ncs (qspi_csn), +\t\t//16550 UART +\t\t.a_16550_uart_0_rs_232_serial_sin (uart_rx), // a_16550_uart_0_rs_232_serial.sin +\t\t.a_16550_uart_0_rs_232_serial_sout (uart_tx), // .sout +\t\t.a_16550_uart_0_rs_232_serial_sout_oe () // .sout_oe +); + + + +//Heart beat by 50MHz clock +always @(posedge clk_50 or negedge fpga_reset_n) + if (!fpga_reset_n) + heart_beat_cnt <= 26'h0; //0x3FFFFFF + else + heart_beat_cnt <= heart_beat_cnt + 1'b1; + +assign user_led = {4'hf,heart_beat_cnt[25]}; + + +endmodule + + +" +"@00000000\r +13 0E 10 00 B3 00 00 06 63 9C 00 08 13 0E 20 00 \r +93 00 00 00 13 01 00 00 B3 80 20 06 63 92 00 08 \r +13 0E 30 00 B7 00 02 01 93 80 40 30 13 01 00 00 \r +B3 81 20 06 63 96 11 06 13 0E 40 00 37 12 06 03 \r +13 02 C2 90 B7 00 02 01 93 80 40 30 37 01 04 02 \r +13 01 81 60 B3 81 20 06 63 94 41 04 13 0E 50 00 \r +37 02 00 FF 13 02 22 10 93 00 F0 FF 37 01 01 00 \r +13 01 31 20 B3 81 20 06 63 94 41 02 13 0E 60 00 \r +93 02 60 00 93 00 10 00 13 01 20 00 93 01 30 00 \r +B3 80 20 06 B3 80 30 06 63 94 50 00 6F 00 00 01 \r +37 01 10 F0 13 01 41 F2 23 20 C1 01 37 01 10 F0 \r +13 01 01 F2 23 20 01 00 13 00 00 00 13 00 00 00 \r +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 \r +" +"@00000000\r +6F 00 C0 04 13 00 00 00 13 00 00 00 13 00 00 00 \r +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 \r +F3 2E 00 30 93 FE 0E 08 63 8A 0E 00 B7 2E 00 00 \r +93 8E 0E 80 73 90 0E 30 73 00 20 30 F3 2E 10 34 \r +93 8E 4E 00 73 90 1E 34 73 00 20 30 13 0E 10 00 \r +37 05 00 10 93 05 40 06 13 06 50 06 93 06 60 06 \r +23 20 D5 00 2F 26 B5 18 13 07 10 00 63 18 E6 2E \r +03 27 05 00 63 94 E6 2E 13 0E 20 00 37 05 00 10 \r +13 05 45 00 93 05 70 06 13 06 80 06 93 06 90 06 \r +23 20 D5 00 2F 26 B5 18 13 07 10 00 63 10 E6 2C \r +03 27 05 00 63 9C E6 2A 13 0E 30 00 37 05 00 10 \r +13 05 45 00 93 05 70 06 13 06 80 06 93 06 90 06 \r +2F 26 B5 18 13 07 10 00 63 1A E6 28 03 27 05 00 \r +63 96 E6 28 13 0E 40 00 37 05 00 10 13 05 85 00 \r +93 05 A0 06 13 06 B0 06 93 06 C0 06 23 20 D5 00 \r +AF 27 05 10 2F 26 B5 18 63 92 D7 26 63 10 06 26 \r +03 27 05 00 63 9C E5 24 13 0E 50 00 37 05 00 10 \r +13 05 85 00 93 05 D0 06 13 06 E0 06 93 06 F0 06 \r +23 20 D5 00 2F 26 B5 18 63 1A 06 22 03 27 05 00 \r +63 96 E5 22 13 0E 60 00 37 05 00 10 13 05 C5 00 \r +93 05 00 07 13 06 10 07 93 06 20 07 37 04 00 10 \r +13 04 04 01 93 04 30 07 13 09 40 07 93 09 50 07 \r +23 20 D5 00 23 20 34 01 AF 27 05 10 AF 2A 04 10 \r +2F 26 B5 18 2F 29 94 18 63 92 D7 1E 63 10 06 1E \r +03 27 05 00 63 9C E5 1C 63 9A 3A 1D 63 18 09 1C \r +03 2A 04 00 63 94 44 1D 13 0E 70 00 37 05 00 10 \r +13 05 45 01 93 05 80 07 13 06 90 07 93 06 A0 07 \r +93 0E 00 01 23 20 D5 00 AF 27 05 10 2F 26 B5 18 \r +63 9E D7 18 63 1C 06 18 03 27 05 00 63 98 E5 18 \r +93 8E FE FF 13 05 45 00 93 85 35 00 13 06 36 00 \r +93 86 36 00 E3 98 0E FC 13 0E 80 00 37 05 00 10 \r +13 05 85 01 93 05 80 07 13 06 90 07 93 06 A0 07 \r +83 27 05 00 2F 26 B5 18 13 07 10 00 63 18 E6 14 \r +03 27 05 00 63 94 E7 14 13 0E 90 00 37 05 00 10 \r +13 05 05 10 93 05 B0 07 13 06 C0 07 93 06 D0 07 \r +23 20 D5 00 AF 27 05 10 73 00 00 00 2F 26 B5 18 \r +13 07 10 00 63 1C E6 10 03 27 05 00 63 98 E6 10 \r +13 0E A0 00 37 05 00 10 13 05 05 20 37 08 00 10 \r +13 08 48 20 93 05 E0 07 13 06 F0 07 93 06 00 08 \r +93 08 10 08 23 20 D5 00 23 20 18 01 AF 27 08 10 \r +2F 26 B5 18 13 07 10 00 63 1A E6 0C 03 27 08 00 \r +63 96 E8 0C 13 0E B0 00 37 05 00 10 13 05 05 30 \r +93 05 20 08 13 06 30 08 93 06 40 08 23 20 D5 00 \r +B7 1E 00 00 93 8E 0E 80 73 90 4E 30 93 0E 80 00 \r +AF 27 05 10 73 90 0E 30 13 00 00 00 13 00 00 00 \r +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 \r +2F 26 B5 18 13 07 10 00 63 1A E6 06 03 27 05 00 \r +63 96 E6 06 13 0E C0 00 37 05 00 10 13 05 05 40 \r +93 05 C0 08 13 06 D0 08 93 06 E0 08 23 20 D5 00 \r +B7 1E 00 00 93 8E 0E 80 73 90 4E 30 B7 2E 00 00 \r +93 8E 8E 80 AF 27 05 10 73 90 0E 30 13 00 00 00 \r +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 \r +13 00 00 00 2F 26 B5 18 13 07 10 00 63 18 E6 00 \r +03 27 05 00 63 94 E6 00 6F 00 00 01 37 01 10 F0 \r +13 01 41 F2 23 20 C1 01 37 01 10 F0 13 01 01 F2 \r +23 20 01 00 13 00 00 00 13 00 00 00 13 00 00 00 \r +13 00 00 00 13 00 00 00 13 00 00 00 \r +" +"@00000000\r +13 0E 10 00 F3 20 40 B0 73 21 40 B0 F3 21 40 B0 \r +63 48 11 06 63 C6 21 06 13 0E 20 00 B7 C0 5D 00 \r +93 80 A0 98 73 90 40 B0 73 21 40 B0 63 4A 11 04 \r +13 0E 30 00 F3 20 50 B0 73 21 50 B0 F3 21 50 B0 \r +63 D0 20 04 63 5E 31 02 13 0E 40 00 73 90 60 B0 \r +F3 20 40 B0 13 01 00 10 63 F4 20 02 13 0E 50 00 \r +F3 20 70 B0 F3 20 40 B0 37 01 00 40 13 01 01 10 \r +B7 01 00 40 63 F6 20 00 63 E4 30 00 6F 00 00 01 \r +37 01 10 F0 13 01 41 F2 23 20 C1 01 37 01 10 F0 \r +13 01 01 F2 23 20 01 00 13 00 00 00 13 00 00 00 \r +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 \r +" +"// megafunction wizard: %ROM: 1-PORT%\r +// GENERATION: STANDARD\r +// VERSION: WM1.0\r +// MODULE: altsyncram \r +\r +// ============================================================\r +// File Name: memory.v\r +// Megafunction Name(s):\r +// \t\t\taltsyncram\r +//\r +// Simulation Library Files(s):\r +// \t\t\taltera_mf\r +// ============================================================\r +// ************************************************************\r +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\r +//\r +// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition\r +// ************************************************************\r +\r +\r +//Copyright (C) 1991-2013 Altera Corporation\r +//Your use of Altera Corporation\'s design tools, logic functions \r +//and other software and tools, and its AMPP partner logic \r +//functions, and any output files from any of the foregoing \r +//(including device programming or simulation files), and any \r +//associated documentation or information are expressly subject \r +//to the terms and conditions of the Altera Program License \r +//Subscription Agreement, Altera MegaCore Function License \r +//Agreement, or other applicable license agreement, including, \r +//without limitation, that your use is for the sole purpose of \r +//programming logic devices manufactured by Altera and sold by \r +//Altera or its authorized distributors. Please refer to the \r +//applicable agreement for further details.\r +\r +\r +// synopsys translate_off\r +`timescale 1 ps / 1 ps\r +// synopsys translate_on\r +module memory (\r +\taddress,\r +\tclock,\r +\tq);\r +\r +\tinput\t[4:0] address;\r +\tinput\t clock;\r +\toutput\t[8:0] q;\r +`ifndef ALTERA_RESERVED_QIS\r +// synopsys translate_off\r +`endif\r +\ttri1\t clock;\r +`ifndef ALTERA_RESERVED_QIS\r +// synopsys translate_on\r +`endif\r +\r +\twire [8:0] sub_wire0;\r +\twire [8:0] q = sub_wire0[8:0];\r +\r +\taltsyncram\taltsyncram_component (\r +\t\t\t\t.address_a (address),\r +\t\t\t\t.clock0 (clock),\r +\t\t\t\t.q_a (sub_wire0),\r +\t\t\t\t.aclr0 (1\'b0),\r +\t\t\t\t.aclr1 (1\'b0),\r +\t\t\t\t.address_b (1\'b1),\r +\t\t\t\t.addressstall_a (1\'b0),\r +\t\t\t\t.addressstall_b (1\'b0),\r +\t\t\t\t.byteena_a (1\'b1),\r +\t\t\t\t.byteena_b (1\'b1),\r +\t\t\t\t.clock1 (1\'b1),\r +\t\t\t\t.clocken0 (1\'b1),\r +\t\t\t\t.clocken1 (1\'b1),\r +\t\t\t\t.clocken2 (1\'b1),\r +\t\t\t\t.clocken3 (1\'b1),\r +\t\t\t\t.data_a ({9{1\'b1}}),\r +\t\t\t\t.data_b (1\'b1),\r +\t\t\t\t.eccstatus (),\r +\t\t\t\t.q_b (),\r +\t\t\t\t.rden_a (1\'b1),\r +\t\t\t\t.rden_b (1\'b1),\r +\t\t\t\t.wren_a (1\'b0),\r +\t\t\t\t.wren_b (1\'b0));\r +\tdefparam\r +\t\taltsyncram_component.clock_enable_input_a = ""BYPASS"",\r +\t\taltsyncram_component.clock_enable_output_a = ""BYPASS"",\r +\t\taltsyncram_component.init_file = ""inst_mem.mif"",\r +\t\taltsyncram_component.intended_device_family = ""Cyclone II"",\r +\t\taltsyncram_component.lpm_hint = ""ENABLE_RUNTIME_MOD=NO"",\r +\t\taltsyncram_component.lpm_type = ""altsyncram"",\r +\t\taltsyncram_component.numwords_a = 32,\r +\t\taltsyncram_component.operation_mode = ""ROM"",\r +\t\taltsyncram_component.outdata_aclr_a = ""NONE"",\r +\t\taltsyncram_component.outdata_reg_a = ""UNREGISTERED"",\r +\t\taltsyncram_component.widthad_a = 5,\r +\t\taltsyncram_component.width_a = 9,\r +\t\taltsyncram_component.width_byteena_a = 1;\r +\r +\r +endmodule\r +\r +// ============================================================\r +// CNX file retrieval info\r +// ============================================================\r +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC ""0""\r +// Retrieval info: PRIVATE: AclrAddr NUMERIC ""0""\r +// Retrieval info: PRIVATE: AclrByte NUMERIC ""0""\r +// Retrieval info: PRIVATE: AclrOutput NUMERIC ""0""\r +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC ""0""\r +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC ""9""\r +// Retrieval info: PRIVATE: BlankMemory NUMERIC ""0""\r +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC ""0""\r +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC ""0""\r +// Retrieval info: PRIVATE: Clken NUMERIC ""0""\r +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC ""0""\r +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING ""PORT_A""\r +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC ""0""\r +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING ""Cyclone II""\r +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC ""0""\r +// Retrieval info: PRIVATE: JTAG_ID STRING ""NONE""\r +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC ""0""\r +// Retrieval info: PRIVATE: MIFfilename STRING ""inst_mem.mif""\r +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC ""32""\r +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC ""0""\r +// Retrieval info: PRIVATE: RegAddr NUMERIC ""1""\r +// Retrieval info: PRIVATE: RegOutput NUMERIC ""0""\r +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING ""0""\r +// Retrieval info: PRIVATE: SingleClock NUMERIC ""1""\r +// Retrieval info: PRIVATE: UseDQRAM NUMERIC ""0""\r +// Retrieval info: PRIVATE: WidthAddr NUMERIC ""5""\r +// Retrieval info: PRIVATE: WidthData NUMERIC ""9""\r +// Retrieval info: PRIVATE: rden NUMERIC ""0""\r +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING ""BYPASS""\r +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING ""BYPASS""\r +// Retrieval info: CONSTANT: INIT_FILE STRING ""inst_mem.mif""\r +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING ""Cyclone II""\r +// Retrieval info: CONSTANT: LPM_HINT STRING ""ENABLE_RUNTIME_MOD=NO""\r +// Retrieval info: CONSTANT: LPM_TYPE STRING ""altsyncram""\r +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC ""32""\r +// Retrieval info: CONSTANT: OPERATION_MODE STRING ""ROM""\r +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING ""NONE""\r +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING ""UNREGISTERED""\r +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC ""5""\r +// Retrieval info: CONSTANT: WIDTH_A NUMERIC ""9""\r +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC ""1""\r +// Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL ""address[4..0]""\r +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC ""clock""\r +// Retrieval info: USED_PORT: q 0 0 9 0 OUTPUT NODEFVAL ""q[8..0]""\r +// Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0\r +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0\r +// Retrieval info: CONNECT: q 0 0 9 0 @q_a 0 0 9 0\r +// Retrieval info: GEN_FILE: TYPE_NORMAL memory.v TRUE\r +// Retrieval info: GEN_FILE: TYPE_NORMAL memory.inc FALSE\r +// Retrieval info: GEN_FILE: TYPE_NORMAL memory.cmp FALSE\r +// Retrieval info: GEN_FILE: TYPE_NORMAL memory.bsf FALSE\r +// Retrieval info: GEN_FILE: TYPE_NORMAL memory_inst.v TRUE\r +// Retrieval info: GEN_FILE: TYPE_NORMAL memory_bb.v TRUE\r +// Retrieval info: LIB_FILE: altera_mf\r +" +"/**\r + * Embedded Systems (EECE6017C) - Lab 3\r + * Simple Processor\r + * Author(s): Alex Stephens (AWS)\r + *\t \t Josh Boroff (JBB)\r + *\t \t Adam Wilford (AFW)\r + * Target FPGA: Altera Cyclone II 2C20 (EP2C20F484C7)\r + * Tool: Quartus II 64-bit\r + * Version: 13.0.1 sp1\r + *\r + * Development Log:\r + * Date\t\tDeveloper\tDescription\r + * 09 18 13 \t\t\t\tInitial development\r + * 09 19 13\tAWS\t\t\tAdded GPRs and associated control signals. Defined bus drivers.\r + */\r +\r +/**\r + * Module mem - The top level module that contains the memory, counter, and proc to do processor operations to memory\r + * mclock - the clock used for the memory \r + * pclock - the clock used for the processor\r + * resetn - the reset button for the systems\r + * run - the trigger used for running the system command\r + * done - the signal released when an operation has completed\r + * bus - the output of the bus lines \r + */\r +module mem(mclock, pclock, resetn, run, done, bus);\r +\t\r +\tinput mclock, pclock, resetn, run;\r +\toutput done;\r +\toutput [8:0] bus;\r +\t\r +\t\r +\twire [4:0] n;//data wire between the counter module and the memory module\r +\twire [8:0] data;//data wire between memory and proc transfer\r +\t\r +\tcounter count(mclock, resetn, n);//the module for counting\r +\t\r +\tmemory memory_control(n, mclock, data);// the module for memory\r +\t\r +\tproc processor(data, resetn, pclock, run, done, bus);// the module for the processor\r +\t\r +endmodule\r +" +"/**\r + * Embedded Systems (EECE6017C) - Lab 3\r + * Simple Processor\r + * Author(s): Alex Stephens (AWS)\r + *\t \t Josh Boroff (JBB)\r + *\t \t Adam Wilford (AFW)\r + * Target FPGA: Altera Cyclone II 2C20 (EP2C20F484C7)\r + * Tool: Quartus II 64-bit\r + * Version: 13.0.1 sp1\r + *\r + */\r +\r +/**\r + * Module counter - This module is used to increment a count of 5 bits\r + * clock - synchronizes this counter with another system\r + * reset - input for when the counter should be reset to 0\r + * countEn - Enable counting\r + * load - Put the loadVal into the counter\r + * loadVal - Value to start the counter at\r + * n - The output value of the counter\r + */\r +\r +module counter(clock, reset, countEn, load, loadVal, n);\r +\tinput clock, enable, load, reset;\r +\tinput [8:0] loadVal;\r +\toutput reg [8:0] n;\r +\t\r +\tinitial n = 9\'b000000000;\r +\t\r +\talways @(posedge clock or negedge reset or posedge load or posedge countEn) \r +\tbegin\r +\t\tif(!reset) n = 9\'b000000000;//reset to 0\r +\t\telse if(clock) begin\r +\t\t\tif(!load && countEn) begin\r +\t\t\t\tn = n + 1;//increment\r +\t\t\tend\r +\t\t\telse if(load && !countEn) begin\r +\t\t\t\tn = loadVal;\r +\t\t\tend\t\r +\t\t\telse if(load && countEn) begin\r +\t\t\t\t$display(""Load and countEn both high! They should not both be high at the same time! Loading loadVal+1\ +"");\r +\t\t\t\tn = loadVal + 1;\r +\t\t\tend\r +\t\t\telse begin\r +\t\t\t\t// do nothing\r +\t\t\tend\r +\t\tend\r +\tend\r +endmodule" +"/**\r + * Embedded Systems (EECE6017C) - Lab 3\r + * Simple Processor\r + * Author(s): Alex Stephens (AWS)\r + *\t \t Josh Boroff (JBB)\r + *\t \t Adam Wilford (AFW)\r + * Target FPGA: Altera Cyclone II 2C20 (EP2C20F484C7)\r + * Tool: Quartus II 64-bit\r + * Version: 13.0.1 sp1\r + *\r + * Development Log:\r + */\r +\r +/**\r + * Module dec3to8 - used to change the 3 bit instructions, x's, and y's into 8 bits\r + * W - the 3 bit input\r + * En - the enable\r + * Y - the output of the 3 bits into 8 bits\r + */\r +module dec3to8(W, En, Y); //change\r +\tinput [2:0] W;\r +\tinput En;\r +\toutput [0:7] Y;\r +\treg [0:7] Y;\r +\talways @(W or En)\r +\tbegin\r +\t\tif (En == 1)\r +\t\t\tcase (W)\r +\t\t\t\t3'b000: Y = 8'b10000000;\r +\t\t\t\t3'b001: Y = 8'b01000000;\r +\t\t\t\t3'b010: Y = 8'b00100000;\r +\t\t\t\t3'b011: Y = 8'b00010000;\r +\t\t\t\t3'b100: Y = 8'b00001000;\r +\t\t\t\t3'b101: Y = 8'b00000100;\r +\t\t\t\t3'b110: Y = 8'b00000010;\r +\t\t\t\t3'b111: Y = 8'b00000001;\r +\t\t\tendcase\r +\t\telse\r +\t\t\tY = 8'b00000000;\r +\tend\r +endmodule" +"// megafunction wizard: %ROM: 1-PORT%VBB%\r +// GENERATION: STANDARD\r +// VERSION: WM1.0\r +// MODULE: altsyncram \r +\r +// ============================================================\r +// File Name: memory.v\r +// Megafunction Name(s):\r +// \t\t\taltsyncram\r +//\r +// Simulation Library Files(s):\r +// \t\t\taltera_mf\r +// ============================================================\r +// ************************************************************\r +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\r +//\r +// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition\r +// ************************************************************\r +\r +//Copyright (C) 1991-2013 Altera Corporation\r +//Your use of Altera Corporation\'s design tools, logic functions \r +//and other software and tools, and its AMPP partner logic \r +//functions, and any output files from any of the foregoing \r +//(including device programming or simulation files), and any \r +//associated documentation or information are expressly subject \r +//to the terms and conditions of the Altera Program License \r +//Subscription Agreement, Altera MegaCore Function License \r +//Agreement, or other applicable license agreement, including, \r +//without limitation, that your use is for the sole purpose of \r +//programming logic devices manufactured by Altera and sold by \r +//Altera or its authorized distributors. Please refer to the \r +//applicable agreement for further details.\r +\r +module memory (\r +\taddress,\r +\tclock,\r +\tq);\r +\r +\tinput\t[4:0] address;\r +\tinput\t clock;\r +\toutput\t[8:0] q;\r +`ifndef ALTERA_RESERVED_QIS\r +// synopsys translate_off\r +`endif\r +\ttri1\t clock;\r +`ifndef ALTERA_RESERVED_QIS\r +// synopsys translate_on\r +`endif\r +\r +endmodule\r +\r +// ============================================================\r +// CNX file retrieval info\r +// ============================================================\r +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC ""0""\r +// Retrieval info: PRIVATE: AclrAddr NUMERIC ""0""\r +// Retrieval info: PRIVATE: AclrByte NUMERIC ""0""\r +// Retrieval info: PRIVATE: AclrOutput NUMERIC ""0""\r +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC ""0""\r +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC ""9""\r +// Retrieval info: PRIVATE: BlankMemory NUMERIC ""0""\r +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC ""0""\r +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC ""0""\r +// Retrieval info: PRIVATE: Clken NUMERIC ""0""\r +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC ""0""\r +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING ""PORT_A""\r +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC ""0""\r +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING ""Cyclone II""\r +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC ""0""\r +// Retrieval info: PRIVATE: JTAG_ID STRING ""NONE""\r +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC ""0""\r +// Retrieval info: PRIVATE: MIFfilename STRING ""inst_mem.mif""\r +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC ""32""\r +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC ""0""\r +// Retrieval info: PRIVATE: RegAddr NUMERIC ""1""\r +// Retrieval info: PRIVATE: RegOutput NUMERIC ""0""\r +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING ""0""\r +// Retrieval info: PRIVATE: SingleClock NUMERIC ""1""\r +// Retrieval info: PRIVATE: UseDQRAM NUMERIC ""0""\r +// Retrieval info: PRIVATE: WidthAddr NUMERIC ""5""\r +// Retrieval info: PRIVATE: WidthData NUMERIC ""9""\r +// Retrieval info: PRIVATE: rden NUMERIC ""0""\r +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING ""BYPASS""\r +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING ""BYPASS""\r +// Retrieval info: CONSTANT: INIT_FILE STRING ""inst_mem.mif""\r +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING ""Cyclone II""\r +// Retrieval info: CONSTANT: LPM_HINT STRING ""ENABLE_RUNTIME_MOD=NO""\r +// Retrieval info: CONSTANT: LPM_TYPE STRING ""altsyncram""\r +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC ""32""\r +// Retrieval info: CONSTANT: OPERATION_MODE STRING ""ROM""\r +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING ""NONE""\r +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING ""UNREGISTERED""\r +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC ""5""\r +// Retrieval info: CONSTANT: WIDTH_A NUMERIC ""9""\r +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC ""1""\r +// Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL ""address[4..0]""\r +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC ""clock""\r +// Retrieval info: USED_PORT: q 0 0 9 0 OUTPUT NODEFVAL ""q[8..0]""\r +// Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0\r +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0\r +// Retrieval info: CONNECT: q 0 0 9 0 @q_a 0 0 9 0\r +// Retrieval info: GEN_FILE: TYPE_NORMAL memory.v TRUE\r +// Retrieval info: GEN_FILE: TYPE_NORMAL memory.inc FALSE\r +// Retrieval info: GEN_FILE: TYPE_NORMAL memory.cmp FALSE\r +// Retrieval info: GEN_FILE: TYPE_NORMAL memory.bsf FALSE\r +// Retrieval info: GEN_FILE: TYPE_NORMAL memory_inst.v TRUE\r +// Retrieval info: GEN_FILE: TYPE_NORMAL memory_bb.v TRUE\r +// Retrieval info: LIB_FILE: altera_mf\r +" +"/**\r + * Embedded Systems (EECE6017C) - Lab 3\r + * Simple Processor\r + * Author(s): Alex Stephens (AWS)\r + *\t \t Josh Boroff (JBB)\r + *\t \t Adam Wilford (AFW)\r + * Target FPGA: Altera Cyclone II 2C20 (EP2C20F484C7)\r + * Tool: Quartus II 64-bit\r + * Version: 13.0.1 sp1\r + *\r + */\r +\r +/**\r + * Module regn - this module is used to create the registers from example code\r + * R - Bus wires for inputing into the reg\r + * Rin - the input signal to say if data needs out\r + * Clock - the clock for things to happen\r + * Q - the output of what is in the reg\r + */\r +module regn(R, Rin, Clock, Q); +parameter n = 9; +input [n-1:0] R; +input Rin, Clock; +output [n-1:0] Q; +reg [n-1:0] Q; +always @(posedge Clock) +\tif (Rin) +\t\tQ <= R; +endmodule" +"memory\tmemory_inst (\r +\t.address ( address_sig ),\r +\t.clock ( clock_sig ),\r +\t.q ( q_sig )\r +\t);\r +" +"/** + * Embedded Systems (EECE6017C) - Lab 3 + * Simple Processor + * Author(s): Alex Stephens (AWS) + *\t \t Josh Boroff (JBB) + *\t \t Adam Wilford (AFW) + * Target FPGA: Altera Cyclone II 2C20 (EP2C20F484C7) + * Tool: Quartus II 64-bit + * Version: 13.0.1 sp1 + * + * Development Log: + * Date\t\tDeveloper\tDescription + * 09 19 13\tAWS\t\t\tInitial + */ + +/** + * module Addsub + * Adds or subtracts two 9-bit inputs + * Sub (1-bit) [in] - When this is asserted, this module will subtract the two numbers + * A (9-bit, Little Endian) [in] - First operand, 2's complement signed integer + * B (9-bit, Little Endian) [in] - Second operand, 2's complement signed integer + * Out (9-bit, Little Endian) [out] - Result of operation, 2's complement signed integer + */ +module addsub(Sub, A, B, Out); +\tinput [8:0] A, B; +\tinput Sub; +\toutput [8:0] Out; +\t +\tassign Out = Sub ? A - B : A + B; +\t +endmodule" +"/**\r + * Embedded Systems (EECE6017C) - Lab 4\r + * Simple Processor\r + * Author(s): Alex Stephens (AWS)\r + *\t \t Josh Boroff (JBB)\r + *\t \t Adam Wilford (AFW)\r + * Target FPGA: Altera Cyclone II 2C20 (EP2C20F484C7)\r + * Tool: Quartus II 64-bit\r + * Version: 13.0.1 sp1\r + *\r + * Development Log:\r + * Date\t\tDeveloper\tDescription\r + * 09 18 13 \t\t\t\tInitial development\r + * 09 19 13\tAWS\t\t\tAdded GPRs and associated control signals. Defined bus drivers.\r + * 09 25 13\t\t\t\t\tBegan development on enhanced version on new branch\r + */\r +\r +/**\r + * Module proc\r + * Enhanced processor with a 9-bit synchronous memory interface and program counter\r + * DIN (9-bit, Little Endian) [in] - Data input, values from memory are read in through this port.\r + * Resetn (1-bit) [in] - Active low reset\r + * Clock (1-bit) [in] - Enable for internal registers\r + * Run (1-bit) [in] - While hight, this signal will allow the processor to continue execution\r + * Done (1-bit) [out] - This signal goes high when an instruction has completed\r + * DOUT (9-bit, Little Endian) [out] - Data being sent to memory\r + * ADDR (9-bit, Little Endian) [out] - Address to access from memory\r + * W (1-bit) [out] - Memory write enable\r + */\r +module proc (DIN, Resetn, Clock, Run, Done, DOUT, ADDR, W);\r +\tinput [8:0] DIN;\r +\tinput Resetn, Clock, Run;\r +\toutput reg Done, W;\r +\toutput reg [8:0] DOUT, ADDR;\r +\r +\r +\tparameter T0 = 3\'b000, T1 = 3\'b001, T2 = 3\'b010, T3 = 3\'b011, T4 = 3\'b100;\r +\tparameter mv = 3\'b000, mvi = 3\'b001, add = 3\'b010, sub = 3\'b011, ld = 3\'b100, st = 3\'b101, mvnz = 3\'b110;\r +\tparameter reg0 = 10\'b1000000000,\r +\t\t\t\t reg1 = 10\'b0100000000,\r +\t\t\t\t reg2 = 10\'b0010000000,\r +\t\t\t\t reg3 = 10\'b0001000000,\r +\t\t\t\t reg4 = 10\'b0000100000,\r +\t\t\t\t reg5 = 10\'b0000010000,\r +\t\t\t\t reg6 = 10\'b0000001000,\r +\t\t\t\t reg7 = 10\'b0000000100,\r +\t\t\t\t gout = 10\'b0000000010,\r +\t\t\t\t dinout = 10\'b0000000001;\r +\t\r +\t//declare variables\r +\treg [1:0] Tstep_Q;\r +\treg [1:0] Tstep_D;\r +\twire [2:0] I;\r +\twire [0:7] regX, regY; ///<-- These are 1-hot encoding, Big Endian!!\r +\twire [8:0] IRoutWires;\r +\twire [8:0] GinWires, GoutWires;\r +\twire [8:0] AoutWires;\r +\twire GNZ;\r +\tand(GNZ, GoutWires[0],\r +\t\t\t\tGoutWires[1],\r +\t\t\t\tGoutWires[2],\r +\t\t\t\tGoutWires[3],\r +\t\t\t\tGoutWires[4],\r +\t\t\t\tGoutWires[5],\r +\t\t\t\tGoutWires[6],\r +\t\t\t\tGoutWires[7],\r +\t\t\t\tGoutWires[8]\r +\t);\r +\t// Register input signals\r +\treg [0:7] Rin;\r +\treg [0:9] busDriver; ///< [R0out, ..., R7out, Gout, DINout]\r +\t\r +\t// Control Signals\r +\treg IRin, DINout, RYout, RYin, RXout, RXin, Ain, Gin, Gout, AddSub,\r +\t\t PCincr, ADDRin, DOUTin;\r + \r +\tassign I = IRoutWires[8:6];\r +\tdec3to8 decX (IRoutWires[5:3], 1\'b1, regX);\r +\tdec3to8 decY (IRoutWires[2:0], 1\'b1, regY);\r +\t\t\r +\t// Control FSM state table change\r + always @(Tstep_Q, Run, Done)\r + begin\r +\t\tif(Done) begin\r +\t\t\tTstep_D <= T0;\r +\t\tend\r +\t\telse begin\r + case (Tstep_Q)\r + T0: // data is loaded into IR in this time step\r +\t\t\t\tbegin\r +\t\t\t\tif(!Run)\r +\t\t\t\t\tTstep_D <= T0;\r +\t\t\t\telse\r +\t\t\t\t\tTstep_D <= T1;\r +\t\t\t\tend\r + T1:\r +\t\t\t\tbegin\r +\t\t\t\t\tTstep_D <= T2;\r +\t\t\t\tend\r +\t\t\t\tT2:\r +\t\t\t\tbegin\r +\t\t\t\t\tTstep_D <= T3;\r +\t\t\t\tend\r +\t\t\t\tT3:\r +\t\t\t\tbegin\r +\t\t\t\t\tTstep_D <= T4;\r +\t\t\t\tend\r +\t\t\t\tT4:\r +\t\t\t\tbegin\r +\t\t\t\t\tTstep_D <=T0;\r +\t\t\t\tend\r + endcase\r +\t end\r + end\r +\r +\t// Control FSM outputs\r +\talways @(Tstep_Q or I or regX or regY)\r +\tbegin\r +\t\t//: : : specify initial values\r +\t\tIRin <= 0;\r +\t\tDone <= 0;\r +\t\tDINout <= 0;\r +\t\tRYout <= 0;\r +\t\tRYin <= 0;\r +\t\tRXout <= 0;\r +\t\tRXin <= 0;\r +\t\tAin <= 0;\r +\t\tGin <= 0;\r +\t\tGout <= 0;\r +\t\tAddSub <= 0;\r +\t\t//reg IRin, DINout, RYout, RYin, RXout, RXin, Ain, Gin, Gout, AddSub;\r +\t\tcase (Tstep_Q)\r +\t\tT0: // store DIN in IR in time step 0\r +\t\t\tbegin\r +\t\t\t//IRin <= 1;\r +\t\t\t\tPCout <= 1;\r +\t\t\t\tADDRin <= 1;\r +\t\t\tend\r +\t\tT1:\r +\t\t\tbegin\r +\t\t\t\tIRin <=1;\r +\t\t\t\tPCincr <=1;\r +\t\tT2: //define signals in time step 1\r +\t\t\tcase (I)\r +\t\t\t\tmv: \r +\t\t\t\tbegin\r +\t\t\t\t\tRYout <= 1;\r +\t\t\t\t\tRXin <= 1;\r +\t\t\t\t\tDone <= 1;\t\t\t\r +\t\t\t\tend\r +\t\t\t\tmvi:\r +\t\t\t\tbegin\r +\t\t\t\t\tPCout <=1;\r +\t\t\t\t\tADDRin <=1;\r +\t\t\t\tend\r +\t\t\t\tadd:\r +\t\t\t\tbegin\r +\t\t\t\t\tRXout <= 1;\r +\t\t\t\t\tAin <= 1;\r +\t\t\t\tend\r +\t\t\t\tsub:\r +\t\t\t\tbegin\r +\t\t\t\t\tRXout <= 1;\r +\t\t\t\t\tAin <= 1;\r +\t\t\t\tend\r +\t\t\t\tld:\r +\t\t\t\tbegin\r +\t\t\t\t\tRYout <=1;\r +\t\t\t\t\tADDRin <=1;\r +\t\t\t\tend\r +\t\t\t\tst:\r +\t\t\t\tbegin\r +\t\t\t\t\tRYout <=1;\r +\t\t\t\t\tADDRin <=1;\r +\t\t\t\tend\r +\t\t\t\tmvnz:\r +\t\t\t\tbegin\r +\t\t\t\t\tif(GNZ)\r +\t\t\t\t\tbegin\r +\t\t\t\t\t\tRYout <=1;\r +\t\t\t\t\t\tADDRin <=1;\r +\t\t\t\t\tend\r +\t\t\t\t\telse Done <= 1;\r +\t\t\t\tend\r +\t\t\t\tdefault:\r +\t\t\t\tbegin\r +\t\t\t\tIRin <= 0;\r +\t\t\t\tDone <= 0;\r +\t\t\t\tDINout <= 0;\r +\t\t\t\tRYout <= 0;\r +\t\t\t\tRYin <= 0;\r +\t\t\t\tRXout <= 0;\r +\t\t\t\tRXin <= 0;\r +\t\t\t\tAin <= 0;\r +\t\t\t\tGin <= 0;\r +\t\t\t\tGout <= 0;\r +\t\t\t\tAddSub <= 0;\r +\t\t\t\tend\r +\t\t\tendcase\r +\t\tT3: //define signals in time step 3\r +\t\t\tcase (I)\r +\t\t\t\tmvi:\r +\t\t\t\tbegin\t\r +\t\t\t\t\tPCincr <=1;\r +\t\t\t\t\tDINout <=1;\r +\t\t\t\t\tRXin <=1;\r +\t\t\t\t\tDone <=1;\r +\t\t\t\tadd:\r +\t\t\t\tbegin\r +\t\t\t\t\tRYout <= 1;\r +\t\t\t\t\tGin <= 1;\t\t\t\t\r +\t\t\t\tend\r +\t\t\t\tsub:\r +\t\t\t\tbegin\r +\t\t\t\t\tRYout <= 1;\r +\t\t\t\t\tGin <= 1;\r +\t\t\t\t\tAddSub <= 1;\r +\t\t\t\tend\r +\t\t\t\tld:\r +\t\t\t\tbegin\r +\t\t\t\t\tDINout <=1;\r +\t\t\t\t\tRXin <=1;\r +\t\t\t\t\tDone <=1;\r +\t\t\t\tend\r +\t\t\t\tst:\r +\t\t\t\tbegin\t\r +\t\t\t\t\tRXout <=1;\r +\t\t\t\t\tDOUTin <=1;\r +\t\t\t\t\tW_D <=1;\r +\t\t\t\t\tDone <=1;//This may need to be in another step unsure\r +\t\t\t\tdefault:\r +\t\t\t\tbegin\r +\t\t\t\t\tIRin <= 0;\r +\t\t\t\t\tDone <= 0;\r +\t\t\t\t\tDINout <= 0;\r +\t\t\t\t\tRYout <= 0;\r +\t\t\t\t\tRYin <= 0;\r +\t\t\t\t\tRXout <= 0;\r +\t\t\t\t\tRXin <= 0;\r +\t\t\t\t\tAin <= 0;\r +\t\t\t\t\tGin <= 0;\r +\t\t\t\t\tGout <= 0;\r +\t\t\t\t\tAddSub <= 0;\r +\t\t\t\tend\r +\t\t\tendcase\r +\t\tT4: //define signals in time step 3\r +\t\t\tcase (I)\r +\t\t\t\tadd:\r +\t\t\t\tbegin\r +\t\t\t\t\tDone <= 1;\r +\t\t\t\t\tGout <= 1;\r +\t\t\t\t\tRXin <= 1;\r +\t\t\t\tend\r +\t\t\t\tsub:\r +\t\t\t\tbegin\r +\t\t\t\t\tDone <= 1;\r +\t\t\t\t\tRXin <= 1;\r +\t\t\t\t\tGout <= 1;\t\t\t\t\r +\t\t\t\tend\r +\t\t\t\tdefault:\r +\t\t\t\tbegin\r +\t\t\t\t\tIRin <= 0;\r +\t\t\t\t\tDone <= 0;\r +\t\t\t\t\tDINout <= 0;\r +\t\t\t\t\tRYout <= 0;\r +\t\t\t\t\tRYin <= 0;\r +\t\t\t\t\tRXout <= 0;\r +\t\t\t\t\tRXin <= 0;\r +\t\t\t\t\tAin <= 0;\r +\t\t\t\t\tGin <= 0;\r +\t\t\t\t\tGout <= 0;\r +\t\t\t\t\tAddSub <= 0;\r +\t\t\t\tend\r +\t\t\tendcase\r +\t\tendcase\r +\tend\r +\t\r +\t// Control FSM flip-flops\r +\talways @(posedge Clock, negedge Resetn) begin\r +\t\tif (!Resetn) begin\r +\t\t\t// Reset all FSM flip-flops\r +\t\t\t/*\r +\t\t\tbusDriver = dinout;\r +\t\t\tDINout = 0;\r +\t\t\tRYout = 0;\r +\t\t\tRYin = 0;\r +\t\t\tRXout = 0;\r +\t\t\tRXin = 0;\r +\t\t\tAin = 0;\r +\t\t\tGin = 0;\r +\t\t\tGout = 0;\r +\t\t\tAddSub = 0;\r +\t\t\tTstep_Q = 2\'b00;\r +\t\t\tTstep_D = 2\'b00;\r +\t\t\t*/\r +\t\tend\r +\t\telse Tstep_Q <= Tstep_D;\r +\t\t\r +\tend\r +\t\r +\t/** General Purpose Register Instantiations **/\r +\t\r +\t// Register outputs\r +\twire [8:0] R0, R1, R2, R3, R4, R5, R6, R7;\r +\t\r +\t// General Purpose Registers\r +\tregn reg_0(BusWires, Rin[0], Clock, R0);\r +\r +\tregn reg_1(BusWires, Rin[1], Clock, R1);\t\t\t\t\r +\t\r +\tregn reg_2(BusWires, Rin[2], Clock, R2);\r +\t\t\t\t\r +\tregn reg_3(BusWires, Rin[3], Clock, R3);\r +\t\r +\tregn reg_4(BusWires, Rin[4], Clock, R4);\r +\t\r +\tregn reg_5(BusWires, Rin[5], Clock, R5);\r +\t\r +\tregn reg_6(BusWires, Rin[6], Clock, R6);\r +\t\r +\tcounter reg_pc(Clock, Resetn, PCincr, Rin[7], R7);\r +\t\r +\t/** Register A **/\r +\tregn reg_a(BusWires, Ain, Clock, AoutWires);\r +\t\r +\t/** Register G **/\r +\r +\tregn reg_g(GinWires, Gin, Clock, GoutWires);\r +\t\r +\t/** Instruction Register **/\r +\tregn reg_ir(DIN, IRin, Clock, IRoutWires);\r +\t\r +\taddsub Addsub(AddSub, AoutWires, BusWires, GinWires);\r +\t\r +\r +\talways @ (RXout, RYout, Gout, DINout, regX, regY)\r +\tbegin // Check control signals and set appropriate flip-flops\r +\t\t//RYin, RXin, Ain, Gin, AddSub;\r +\t\t\t// Set the bus driver\r +\t\t\tif(DINout && !(RXout || RYout || Gout)) begin\r +\t\t\t\tbusDriver = 10\'b0000000001;\r +\t\t\tend\r +\t\t\telse if(RXout && !(DINout || RYout || Gout)) begin\r +\t\t\t\tbusDriver = {regX, 1\'b0, 1\'b0};\r +\t\t\tend\r +\t\t\telse if(RYout && !(RXout || DINout || Gout)) begin\r +\t\t\t\tbusDriver = {regY, 1\'b0, 1\'b0};\r +\t\t\tend\r +\t\t\telse if(Gout && !(RXout || RYout || DINout)) begin\r +\t\t\t\tbusDriver = 10\'b0000000010;\r +\t\t\tend\r +\t\t\telse begin\r +\t\t\t\t$display(""Ambiguous bus driver!! Setting to DINout\ +"");\r +\t\t\t\tbusDriver = 10\'b0000000001;\r +\t\t\tend\r +\t\t\t\r +\tend\r +\t\r +\talways @ (RXin, RYin, regX, regY)\r +\tbegin\r +\t\tRin = 8\'b00000000;\r +\t\tif(RXin) begin\r +\t\t\tRin = Rin | regX;\r +\t\tend\r +\t\t\r +\t\tif(RYin) begin\r +\t\t\tRin = Rin | regY;\r +\t\tend\r +\tend\r +\t\r +\t// Define the bus\r +\talways @ (busDriver, R0, R1, R2, R3, R4, R5, R6, R7, GoutWires, DIN) begin\r +\t\tcase(busDriver)\r +\t\t\treg0: BusWires <= R0;\r +\t\t\treg1: BusWires <= R1;\r +\t\t\treg2: BusWires <= R2;\r +\t\t\treg3: BusWires <= R3;\r +\t\t\treg4: BusWires <= R4;\r +\t\t\treg5: BusWires <= R5;\r +\t\t\treg6: BusWires <= R6;\r +\t\t\treg7: BusWires <= R7;\r +\t\t\tgout: BusWires <= GoutWires;\r +\t\t\tdinout: BusWires <= DIN;\r +\t\t\tdefault:\r +\t\t\tbegin\r +\t\t\t\t$display(""Undefined bus driver!! Defaulting to DIN!!\ +"");\r +\t\t\t\tBusWires <= DIN;\r +\t\t\tend\r +\t\tendcase\r +\tend\r +\t\r +\r +\t\r +\t\r +endmodule +" +"module Quadrature(clk, enc_a, enc_b, count);\r + input clk;\r + input enc_a;\r + input enc_b;\r + output count;\r + \r + reg signed [15:0] count;\r +\r + wire [1:0] cur_state;\r + reg [1:0] last_state;\r +\r + // Debounce encoder inputs\r + Debouncer dbc_a(clk, enc_a, cur_state[0]);\r + Debouncer dbc_b(clk, enc_b, cur_state[1]);\r +\r +\r + always @ (posedge clk) begin\r + case ({last_state, cur_state})\r + 4'b0001: count <= count + 1;\r + 4'b0111: count <= count + 1;\r + 4'b1110: count <= count + 1;\r + 4'b1000: count <= count + 1;\r +\r + 4'b0010: count <= count - 1;\r + 4'b1011: count <= count - 1;\r + 4'b1101: count <= count - 1;\r + 4'b0100: count <= count - 1;\r + endcase\r + last_state <= cur_state;\r + end\r +endmodule\r +" +"module Servo(clk, out, pos, enable);\r +\tinput clk;\r +\toutput out;\r +\treg out;\r +\tinput [9:0] pos;\r + input enable;\r +\r +\t// fpga4fun\r +\tparameter ClkDiv = 31;\r +\tparameter PulseCountSize = 11;\r +\r +\treg [6:0] ClkCount;\r +\treg [PulseCountSize:0] PulseCount;\r +\treg ClkTick;\r +\r +\talways @(posedge clk) begin\r +\t\tClkTick <= (ClkCount==ClkDiv-2);\r +\r +\t\tif(ClkTick) \r +\t\t\tClkCount <= 0; \r +\t\telse \r +\t\t\tClkCount <= ClkCount + 1;\r +\r +\t\tif(ClkTick) \r +\t\t\tPulseCount <= PulseCount + 1;\r +\t\r +\t\tout = enable ? (PulseCount < {2'b00, pos}) : 0;\r + end\r +\t// fpga4fun\r +\r +endmodule\r +" +"module Motor(clk, out, ctl, vel);\r +\tinput clk;\r +\toutput [1:0] out;\r +\treg pwmout;\r +\treg [7:0] pwmcount;\r +\tinput [7:0] vel;\r +\tinput [1:0] ctl;\r +\t\r +\talways @ (posedge clk)\r +\tbegin\r +\t\tpwmcount <= pwmcount + 1;\r +\t\tif (pwmcount==0)\r +\t\t\tpwmout = 1;\r +\t\telse\r +\t\tif (pwmcount==vel)\r +\t\t\tpwmout = 0;\r +\tend\r +\t\r +\t\r +\twire fwd = (ctl==2'b01);\t\r +\twire rev = (ctl==2'b10);\t\r +//\twire brake = (ctl==2'b00);\r +\r +\tassign out[0] = fwd ? pwmout : 0;\r +\tassign out[1] = rev ? pwmout : 0;\r +\t\r +endmodule\r +" +"`include ""Motor.v""\r +`include ""Servo.v""\r +`include ""Encoder.v""\r +`include ""Debouncer.v""\r +`include ""Quadrature.v""\r +`include ""Pwm.v""\r +\r +module happyio(clk, ad, a, aout, ale, nRD, nWR, mot0, mot1, mot2, mot3, mot4, mot5, Servo, Enc, Digital, ramce);\r +\t// clock\r +\tinput clk;\r +\t// AVR XMEM interface\r +\tinput [7:0] a;\r +\tinout [7:0] ad;\r +\tinput ale;\r +\tinput nRD, nWR;\r +\t// address [0..7] output\r +\toutput [7:0] aout;\r +\t// IO Pins\r +\toutput [1:0] mot0;\r +\toutput [1:0] mot1;\r +\toutput [1:0] mot2;\r +\toutput [1:0] mot3;\r +\toutput [1:0] mot4;\r +\toutput [1:0] mot5;\r +\tinput [3:0] Enc;\r +\tinout [7:0] Digital;\r +\toutput [5:0] Servo;\r +\toutput ramce;\r +\r +\t\r +\t// tri-state digital IO\r +\treg [7:0] digitalPinMode = 8\'h00;\r +\twire [7:0] digitalOutput;\r +\treg [7:0] digitalPwm [7:0];\r +\r +\tassign Digital[0] = digitalPinMode[0] ? digitalOutput[0] : 1\'bz;\r +\tassign Digital[1] = digitalPinMode[1] ? digitalOutput[1] : 1\'bz;\r +\tassign Digital[2] = digitalPinMode[2] ? digitalOutput[2] : 1\'bz;\r +\tassign Digital[3] = digitalPinMode[3] ? digitalOutput[3] : 1\'bz;\r +\tassign Digital[4] = digitalPinMode[4] ? digitalOutput[4] : 1\'bz;\r +\tassign Digital[5] = digitalPinMode[5] ? digitalOutput[5] : 1\'bz;\r +\tassign Digital[6] = digitalPinMode[6] ? digitalOutput[6] : 1\'bz;\r +\tassign Digital[7] = digitalPinMode[7] ? digitalOutput[7] : 1\'bz;\r +\r +\t//reg ramce;\r +\r +\t// internal\r +\treg [15:0] addr;\r +\twire\t [7:0] aout;\r +\twire [7:0] data;\r +\treg [7:0] dataOut;\r +\r +\t// registers (motors)\r +\treg [1:0] ma1_ctl;\r +\treg [7:0] ma1_vel;\r +\treg [1:0] ma2_ctl;\r +\treg [7:0] ma2_vel;\r +\treg [1:0] mb1_ctl;\r +\treg [7:0] mb1_vel;\r +\treg [1:0] mb2_ctl;\r +\treg [7:0] mb2_vel;\r +\treg [1:0] mc1_ctl;\r +\treg [7:0] mc1_vel;\r +\treg [1:0] mc2_ctl;\r +\treg [7:0] mc2_vel;\r +\t\r +\t// registers (encoders)\r +\twire [15:0] enc0;\r +\twire [15:0] enc1;\r +\twire [15:0] enc2;\r +\twire [15:0] enc3;\r +\t\r +\t// registers (servos)\r +\treg [9:0] srv0;\r +\treg [9:0] srv1;\r +\treg [9:0] srv2;\r +\treg [9:0] srv3;\r +\treg [9:0] srv4;\r +\treg [9:0] srv5;\r + reg srv0_e;\r + reg srv1_e;\r + reg srv2_e;\r + reg srv3_e;\r + reg srv4_e;\r + reg srv5_e;\r +\r +\treg [7:0] tempLo;\r +\treg [7:0] tempHi;\r +\r +\t// bidirectional data bus\r +\t assign ad = (addr[15] | nRD ) ? 8\'hzz : dataOut ;\r +\t//assign ad = 8\'hzz;\r +\t\r +\t// latch the lower 8 bits of address\r +\tassign data = ad;\r +\talways @(negedge ale) begin\r +\t\t\taddr[7:0] = ad[7:0];\r +\t\t\taddr[15:8] = a[7:0];\r +\tend\r +\r +\tassign aout[7:0] = addr[7:0];\r +\r +\t// assign ram ce\t\r +\tassign ramce = ~addr[15];\r +\t//always @ (addr[15] or nRD or nWR) begin\r +\t//\tramce = ~addr[15];\r +\t//end \r +\r +\t// read control\r +\talways @ (negedge nRD)\r +\tbegin\r +\t\tcase (addr)\r +\t\t\t// 0x1100 - 0x110B : motors\r +\t\t\t16\'h1100:\tdataOut[1:0] = ma1_ctl;\r +\t\t\t16\'h1101:\tdataOut = ma1_vel;\r +\t\t\t16\'h1102:\tdataOut[1:0] = ma2_ctl;\r +\t\t\t16\'h1103:\tdataOut = ma2_vel;\r +\t\t\t16\'h1104:\tdataOut[1:0] = mb1_ctl;\r +\t\t\t16\'h1105:\tdataOut = mb1_vel;\r +\t\t\t16\'h1106:\tdataOut[1:0] = mb2_ctl;\r +\t\t\t16\'h1107:\tdataOut = mb2_vel;\r +\t\t\t16\'h1108:\tdataOut[1:0] = mc1_ctl;\r +\t\t\t16\'h1109:\tdataOut = mc1_vel;\r +\t\t\t16\'h110A:\tdataOut[1:0] = mc2_ctl;\r +\t\t\t16\'h110B:\tdataOut = mc2_vel;\r +\t\t\t// 0x110C - 0x1113 : encoders\r +\t\t\t16\'h110C:\t{tempHi, dataOut} = enc0;\r +\t\t\t16\'h110D:\tdataOut = tempHi;\r +\t\t\t16\'h110E:\t{tempHi, dataOut} = enc1;\r +\t\t\t16\'h110F:\tdataOut = tempHi;\r +\t\t\t16\'h1110:\t{tempHi, dataOut} = enc2;\r +\t\t\t16\'h1111:\tdataOut = tempHi;\r +\t\t\t16\'h1112:\t{tempHi, dataOut} = enc3;\r +\t\t\t16\'h1113:\tdataOut = tempHi;\r +\t\t\t// 0x1120 - 0x112B : servos\r +\t\t\t/*\r +\t\t\t16\'h1118:\tdataOut = srv0;\r +\t\t\t16\'h1119:\tdataOut = srv1;\r +\t\t\t16\'h111A:\tdataOut = srv2;\r +\t\t\t16\'h111B:\tdataOut = srv3;\r +\t\t\t16\'h111C:\tdataOut = srv4;\r +\t\t\t16\'h111D:\tdataOut = srv5;\r +\t\t\t*/\r +\t\t\t// 0x11 : digital in\r +\t\t\t16\'h111E:\tdataOut = Digital;\r +\t\t\t// 0x11FE : major version\r +\t\t\t16\'h11FE:\tdataOut = 0;\r +\t\t\t// 0x11FF : minor version\r +\t\t\t16\'h11FF:\tdataOut = 7;\r +\t\tendcase\r +\tend\r +\t\r +\t// write control\r +\talways @ (negedge nWR or posedge clk)\r +\tbegin \r +\t\tif (!nWR)\r +\t\tcase (addr)\r +\t\t\t// 0x1100 - 0x110B : motors\r +\t\t\t16\'h1100:\tma1_ctl = data;\r +\t\t\t16\'h1101:\tma1_vel = data;\r +\t\t\t16\'h1102:\tma2_ctl = data;\r +\t\t\t16\'h1103:\tma2_vel = data;\r +\t\t\t16\'h1104:\tmb1_ctl = data;\r +\t\t\t16\'h1105:\tmb1_vel = data;\r +\t\t\t16\'h1106:\tmb2_ctl = data;\r +\t\t\t16\'h1107:\tmb2_vel = data;\r +\t\t\t16\'h1108:\tmc1_ctl = data;\r +\t\t\t16\'h1109:\tmc1_vel = data;\r +\t\t\t16\'h110A:\tmc2_ctl = data;\r +\t\t\t16\'h110B:\tmc2_vel = data;\r +\t\t\t// 0x110C - 0x1113 : encoders\r +\t\t\t// ...\r +\t\t\t// 0x1120 - 0x112B : servos\r +\t\t\t16\'h1120:\ttempLo = data;\r +\t\t\t16\'h1121: \tbegin\r +\t\t\t\t\t\t\tsrv0 = {data[1:0],tempLo}; \r +\t\t\t\t\t\t\tsrv0_e = data[7];\r +\t\t\t\t\t\tend\r +\t\t\t16\'h1122:\ttempLo = data;\r +\t\t\t16\'h1123: \tbegin\r +\t\t\t\t\t\t\tsrv1 = {data[1:0],tempLo}; \r +\t\t\t\t\t\t\tsrv1_e = data[7];\r +\t\t\t\t\t\tend\r +\t\t\t16\'h1124:\ttempLo = data;\r +\t\t\t16\'h1125: \tbegin\r +\t\t\t\t\t\t\tsrv2 = {data[1:0],tempLo}; \r +\t\t\t\t\t\t\tsrv2_e = data[7];\r +\t\t\t\t\t\tend\r +\t\t\t16\'h1126:\ttempLo = data;\r +\t\t\t16\'h1127: \tbegin\r +\t\t\t\t\t\t\tsrv3 = {data[1:0],tempLo}; \r +\t\t\t\t\t\t\tsrv3_e = data[7];\r +\t\t\t\t\t\tend\r +\t\t\t16\'h1128:\ttempLo = data;\r +\t\t\t16\'h1129: \tbegin\r +\t\t\t\t\t\t\tsrv4 = {data[1:0],tempLo}; \r +\t\t\t\t\t\t\tsrv4_e = data[7];\r +\t\t\t\t\t\tend\r +\t\t\t16\'h112A:\ttempLo = data;\r +\t\t\t16\'h112B: \tbegin\r +\t\t\t\t\t\t\tsrv5 = {data[1:0],tempLo}; \r +\t\t\t\t\t\t\tsrv5_e = data[7];\r +\t\t\t\t\t\tend\r +\r +\r +\t\t\t// Digital I/O mode\r +\t\t\t16\'h1130:\tdigitalPinMode = data;\r +\r +\t\t\t// Digital Output\r +\t\t\t16\'h1131:\tdigitalPwm[0] = data;\r +\t\t\t16\'h1132:\tdigitalPwm[1] = data;\r +\t\t\t16\'h1133:\tdigitalPwm[2] = data;\r +\t\t\t16\'h1134:\tdigitalPwm[3] = data;\r +\t\t\t16\'h1135:\tdigitalPwm[4] = data;\r +\t\t\t16\'h1136:\tdigitalPwm[5] = data;\r +\t\t\t16\'h1137:\tdigitalPwm[6] = data;\r +\t\t\t16\'h1138:\tdigitalPwm[7] = data;\r +\t\t\t// ...\r +\t\tendcase\r +\tend\r +\t\r +\r +\t// motor drivers\r +\tMotor motor0(clk,mot0,ma2_ctl,ma2_vel);\r +\tMotor motor1(clk,mot1,ma1_ctl,ma1_vel);\r +\tMotor motor2(clk,mot2,mb2_ctl,mb2_vel);\r +\tMotor motor3(clk,mot3,mb1_ctl,mb1_vel);\r +\tMotor motor4(clk,mot4,mc2_ctl,mc2_vel);\r +\tMotor motor5(clk,mot5,mc1_ctl,mc1_vel);\r +\r +\t// encoder drivers\r + `ifndef QUADRATURE\r +\tEncoder encoder0(clk,Enc[0],enc0);\r +\tEncoder encoder1(clk,Enc[1],enc1);\r +\tEncoder encoder2(clk,Enc[2],enc2);\r +\tEncoder encoder3(clk,Enc[3],enc3);\r + `else\r +\tQuadrature quad0(clk,Enc[0],Enc[1], enc0);\r +\tQuadrature quad1(clk,Enc[2],Enc[3], enc1);\r + `endif\r +\r +\t// servo drivers\r +\tServo servo0(clk,Servo[0],srv0, srv0_e);\r +\tServo servo1(clk,Servo[1],srv1, srv1_e);\r +\tServo servo2(clk,Servo[2],srv2, srv2_e);\r +\tServo servo3(clk,Servo[3],srv3, srv3_e);\r +\tServo servo4(clk,Servo[4],srv4, srv4_e);\r +\tServo servo5(clk,Servo[5],srv5, srv5_e);\r +\r +\t// digital IO\r +\tPwm pwm0(clk, digitalOutput[0], digitalPwm[0]);\r +\tPwm pwm1(clk, digitalOutput[1], digitalPwm[1]);\r +\tPwm pwm2(clk, digitalOutput[2], digitalPwm[2]);\r +\tPwm pwm3(clk, digitalOutput[3], digitalPwm[3]);\r +\tPwm pwm4(clk, digitalOutput[4], digitalPwm[4]);\r +\tPwm pwm5(clk, digitalOutput[5], digitalPwm[5]);\r +\tPwm pwm6(clk, digitalOutput[6], digitalPwm[6]);\r +\tPwm pwm7(clk, digitalOutput[7], digitalPwm[7]);\r +\r +endmodule\r +" +"module Debouncer (clk, dirty, clean); + input clk; + input dirty; + output reg clean; + + reg [6:0] debounce; + reg last_dirty; + + always @ (posedge clk) begin + if (dirty != last_dirty) begin + last_dirty <= dirty; + debounce <= 0; + end else if (debounce == 127) begin + clean <= last_dirty; + end else begin + debounce <= debounce+1; + end + end +endmodule + +" +"module Pwm(clk, out, val);\r +\tinput clk;\r +\toutput reg out;\r +\treg [7:0] pwmcount = 0;\r +\tinput [7:0] val;\r +\t\r +\talways @ (posedge clk) begin\r +\t\tpwmcount <= pwmcount + 1;\r + if (val == 0) begin\r + out <= 0;\r + end else if (val == 255) begin\r + out <= 1;\r + end else if (pwmcount==0) begin\r +\t\t\tout <= 1;\r +\t\tend else if (pwmcount==val) begin\r +\t\t\tout <= 0;\r + end\r +\tend\r +endmodule\r +" +"module Encoder(clk, enc, count);\r +\tinput clk;\r +\tinput enc;\r +\treg enc_clean, enc_new;\r +\treg [7:0] debounce;\r +\toutput [15:0] count;\r +\treg [15:0] count;\r +\r +\talways @ (posedge clk)\r + if (enc != enc_new) begin enc_new <= enc; debounce <= 0; end\r + else if (debounce == 127) enc_clean <= enc_new;\r + else debounce <= debounce+1;\r +\r +\talways @ (posedge enc_clean)\r +\t\tcount <= count + 1;\r +\t\r +endmodule\r +" +"//Test Bench for Register File + +`define N 16 +`define K 4 +module regfile_tb; + + reg clk; + wire [`N-1:0] a,b; + reg [`N-1:0] x; + reg [`K-1:0] sa, sb, d; + reg ld; + + +regfile #(.n(`N), .k(`K)) r1 (clk, x, ld, d, sa, sb, a, b); + +initial begin + clk = 0; +end + +initial begin + $monitor(""time:%t\\tld: %b\\tsa: %d\\tsb: %d\\td %d\\tx: %d\\ta: %d\\tb: %d"", $time, ld, sa, sb, d, x, a, b); +end + +initial begin + // Load 10 into register 2 + #0 begin + $display(""\ +Starting test 1""); + ld = 1; + x = 16\'d10; + d = 3; + sa = 3; + sb = 3; + end + // Retrieve 10 from register 2 + #2 begin + $display(""Reading register""); + ld = 0; + x = 0; + d = 3; + sa = 3;//4\'b0010; + sb = 3;//4\'b0010; + end + + #2 begin + $display(""Writing + Reading""); + ld = 1; + x = 16\'d15; + d = 1; + sa = 3; + sb = 3; + end + + #2 begin + $display(""Reading both registers""); + ld = 0; + x = 0; + d = 0; + sa = 1; + sb = 3; + end + #2 begin + $display(""Read again""); + ld = 0; + x = 0; + d = 0; + sa = 1; + sb = 3; + end + #4 $finish; +end + +//Simulate Clock +always begin + #1 clk = !clk; +end + +endmodule +" +"//Fibonacci Test Bench + +//Test Bench for Multiplier Functional Unit +module FibonacciTB; + + reg clk, reset; + wire [15:0] result; + reg [7:0] n; + wire ready; + + +//Data containing 0 +reg [7:0] test0Data = 8\'b0; + +//Data containing 1 +reg [7:0] test1Data = 8\'b1; + +// Test regular fibonacci number +reg [7:0] testOrdinary = 8\'d6; + +//Test overflow number +reg [7:0] testOverflow = 8\'d25; + +defparam f1.inBits = 8; +defparam f1.outBits = 16; +fibonacci f1 (clk, reset, n, result, ready); + +initial begin + clk = 0; + reset = 0; +end + +initial begin +// $monitor(""time:%t\\treset: %b\\tready: %b\\tresult: %d\ +n: %d"",$time, reset, ready, result, n); +end + +initial begin + #50 begin $display(""Starting test 1""); reset = 1; n = testOrdinary; end + #11 reset = 0; + #90 begin $display(""Starting test 2""); reset = 1; n = test0Data; end //Test fib(0) == 0 + #11 reset = 0; + #50 begin $display(""Starting test 3""); reset = 1; n = test1Data; end //Test fib(1) == 1 + #11 reset = 0; + #50 begin $display(""Starting test 4""); reset = 1; n = testOverflow; end //Test overflowing + #11 reset = 0; + #300 $finish; +end + +//Simulate Clock +always begin + #5 clk = !clk; +end + +endmodule +" +"//Circuit which generates Fibonacci numbers + +module fibonacci ( +clk, //clock +reset, //reset the Multiplier +n, //Fibonacci number to calculate +result, //result of fibonacci calculation +ready //signals if the result is ready +); + +parameter inBits = 8; //No of bits for n +parameter outBits = 16; //No of bits of Fib number + +//----Input Ports--- +input clk; +input reset; +input [inBits-1:0] n; + +//---Output Ports--- +output reg [outBits-1:0] result; +output reg ready; + +//---Internal Registers--- +reg [outBits-1:0] last; +reg [inBits-1:0] no; +reg [inBits-1:0] count; + + +always @(posedge clk) begin + if (reset) begin + result <= 16\'b0; + last <= 16\'b0; + no <= n; + count <= 16\'b0; + //0th fibonacci number is 0, need to generate 1 afterwards + end else begin + if (result == 0 && !ready) begin + result <= 1; + end else if (ready) begin + result <= result; + end else begin + result <= result + last; + end + last <= result; + count <= count + 1; + end + ready <= count >= no; + $display(""reset %b, count %d, result %d, ready %b, no %d, last %d"",reset, count, result, ready, no, last); +end + + +endmodule +" +"//Multiplier Functional Unit which multiplies 2 numbers + + +module multiplier ( +clk, //clock +reset, //reset the Multiplier +x, //First Number to be multiplied +y, //Second Number to be multiplied +prod, //result of multiplication +ready //signals if the result is ready +); + +parameter bits = 8; + +//----Input Ports--- +input clk; +input reset; +input [bits - 1:0] x; +input [bits - 1:0] y; + +//---Output Ports-- +output reg [(bits * 2) - 1:0] prod; +output reg ready; + +//--Internal Data-- +reg [7:0] rx; +reg [15:0] ry; + +always @(posedge clk) begin + if (reset) begin + rx <= x; + ry <= 16\'b0 + y; + prod <= 16\'b0; + + end else begin + rx <= rx >> 1; + ry <= ry << 1; + // If LSB of rx is 1 then ""multiply"" otherwise no change + if (rx & 8\'b1) begin + prod <= prod + ry; + end else begin + prod <= prod; + end + + end + // When one result reaches 0 nothing left to multiply + //$display(""reset %b ready %b rx %d ry %d prod %d, x %d, y %d"", reset, ready, rx, ry, prod, x ,y); + ready <= !rx || !ry; +end + + +endmodule +" +" +//Test Bench for Multiplier Functional Unit +module MultiplierTB; + + reg clk, reset; + wire [15:0] result; + reg [7:0] x, y; + wire ready; + + +//Data containing 0 +reg [7:0] test0Data = 8\'b00000000; + +//Data containing 1 +reg [7:0] test1Data = 8\'b00000001; + +//Data for testing left and right multiplication with identity (1) +//gives the data +reg [7:0] testLeftIdentity = 8\'d67; +reg [7:0] testRightIdentity = 8\'d96; + +// Data for testing multiplying by 0 on lhs and rhs still gives 0 +reg [7:0] testLHS0Data = 8\'d37; +reg [7:0] testRHS0Data = 8\'d96; + + +// Data for testing 2 regular numbers multiply correctly +reg [7:0] testRegularData1 = 8\'d20; +reg [7:0] testRegularData2 = 8\'d10; + + +reg [7:0] test2RegularData1 = 8\'d255; +reg [7:0] test2RegularData2= 8\'d255; + + +defparam m1.bits = 8; +multiplier m1 (clk, reset, x, y, result, ready); + +initial begin + clk = 0; + reset = 0; +end + +initial begin + $monitor(""time:%t\\treset: %b\\tready: %b\\tresult: %d\ +x: %d\\ty: %d"", $time, reset, ready, result, x, y); +end + +initial begin + #50 begin $display(""Starting test 1""); reset = 1; x = testRegularData1; y = testRegularData2; end + #11 reset = 0; + #70 begin $display(""Starting test 2""); reset = 1; x = test2RegularData1; y = test2RegularData2; end + #11 reset = 0; + #200 begin $display(""Starting test 3""); reset = 1; x = test0Data; y = test0Data; end //Test 0x0 == 0 + #11 reset = 0; + #50 begin $display(""Starting test 4""); reset = 1; x = testLHS0Data; y = test0Data; end //Test x*0 == 0 + #11 reset = 0; + #50 begin $display(""Starting test 5""); reset = 1; x = test0Data; y = testRHS0Data; end //Test 0*x == 0 + #11 reset = 0; + #50 begin $display(""Starting test 6""); reset = 1; x = test1Data; y = testLeftIdentity; end //Test 1*x == x + #11 reset = 0; + #50 begin $display(""Starting test 7""); reset = 1;x = testRightIdentity; y = test1Data; end //Test x*1 == x + #11 reset = 0; + #80 $finish; +end + +//Simulate Clock +always begin + #5 clk = !clk; +end + +endmodule +" +"//Module which prints Hello World +module HelloWorld; + +initial begin + $display(""Hello World""); + $finish; +end + +endmodule +" +"//Register File +module regfile ( +clk, // Clock +x, //External Input +ld, //Whether or not to load destination register from extenral input +d, //Destination register +sa, //1st Source Register +sb, // 2nd Source Register +a, // Output a +b // Output b +); + +parameter n = 16; //n bits per register +parameter k = 4; //2^k registers + +//--- Input Ports --- +input clk; +input [n-1:0] x; +input ld; +input [k-1:0] d, sa, sb; + +//--- Output Ports --- +output wire [n - 1:0] a, b; + + +//-- Internal Data --- +wire [n - 1:0] a0, a1, b0, b1; + +wire ld0, ld1; + +generate + // Base case of 2 regfiles left + if (k == 1) begin + regfile1 #(.n(n)) rfile1A(clk, x, ld0, a0, b0); + regfile1 #(.n(n)) rfile1B(clk, x, ld1, a1, b1); + // 2^k bit regfile + end else begin + regfile #(.k(k-1), .n(n)) rFileA(clk, x, ld0, d[k-2:0], sa[k-2:0], sb[k-2:0], a0, b0); + regfile #(.k(k-1), .n(n)) rFileB(clk, x, ld1, d[k-2:0], sa[k-2:0], sb[k-2:0], a1, b1); + end +endgenerate + +function [n-1:0] mux1w; + input v; + input [n-1:0]x1; + input [n-1:0]x2; + begin + if (v) begin + mux1w = x2; + + end else begin + mux1w = x1; + end + end +endfunction + + +assign ld0 = (!d[k-1]) & ld; +assign ld1 = d[k-1] & ld; +assign a = mux1w(sa[k-1], a0, a1); +assign b = mux1w(sb[k-1], b0, b1); + +endmodule + + + +module regfile1 ( +clk, // Clock +x, //External Input +ld, //Whether or not to load destination register from external input +r, // Output a +r // Output b +); + +parameter n = 16; //n bit register + +//--- Inputs --- +input clk; +input [n - 1: 0] x; +input ld; + +//--- Outputs --- +output reg [n-1:0] r; + +always @(posedge clk) begin + if (ld) begin + r <= x; + end else begin + r <= r; + end +end + + +endmodule + +" +"Require Import Bedrock EchoServerDriver AMD64_gas. + +Module M. + Definition heapSize := 1024 * 10. + Definition port : W := 8081%N. + Definition numWorkers : W := 10. +End M. + +Module E := Make(M). + +Definition compiled := moduleS E.m. +Recursive Extraction compiled. +" +"Require Import Bedrock WebServerDriver AMD64_gas. + +Module M. + Definition heapSize := (1024 * 1024 * 25)%N. + Definition port : W := 8080%N. + Definition numWorkers : W := 10. +End M. + +Module E := Make(M). + +Definition compiled := moduleS E.m. +Recursive Extraction compiled. +" +"Require Import AutoSep Malloc. + + +Section adt. + Variable P : W -> W -> HProp. + Variable res : nat. + + Definition newS := SPEC(""extra_stack"") reserving res + PRE[_] mallocHeap 0 + POST[R] P 0 R * mallocHeap 0. + + Definition deleteS := SPEC(""extra_stack"", ""self"") reserving res + Al c, + PRE[V] P c (V ""self"") * mallocHeap 0 + POST[_] mallocHeap 0. + + Definition readS := SPEC(""extra_stack"", ""self"") reserving res + Al c, + PRE[V] P c (V ""self"") * mallocHeap 0 + POST[R] [| R = c |] * P c (V ""self"") * mallocHeap 0. + + Definition writeS := SPEC(""extra_stack"", ""self"", ""n"") reserving res + Al c, + PRE[V] P c (V ""self"") * mallocHeap 0 + POST[_] P (V ""n"") (V ""self"") * mallocHeap 0. +End adt. +" +"Set Implicit Arguments. + +Require Import StringSet. +Module String_as_OT := StringKey. + +Require Import FMapAVL. +Module Import StringMap := Make String_as_OT. + +Require Import OrdersAlt. +Module String_as_OT_new := Update_OT String_as_OT. +Require Import Equalities. +Module String_as_UDT := Make_UDT String_as_OT. +" +"Require Import S. + +Module Make (E : S). + + Definition t := list E.t. + +End Make." +"Require Import Thread. +Export Thread. + +Module Type S. + Variable globalSched : W. +End S. + +Module Make(M : S). +Import M. + +Module M'. + Definition globalSched := M.globalSched. + + Open Scope Sep_scope. + + Definition globalInv (_ : files) : HProp := Emp. +End M'. + +Ltac unf := unfold M'.globalInv in *. + +Module T := Thread.Make(M'). + +Import T. +Export T. + +Ltac sep := T.sep unf. +Ltac sep_auto := sep auto_ext. + +End Make. +" +"Set Implicit Arguments. + +Require Import LabelMap. +Require Import Equalities. +Module K := Make_UDT LabelKey. +Module M := LabelMap. +Require Import FMapFacts. +Include (Properties M). +Include (Facts M). +Require Import FMapFacts1. +Include (WFacts_fun K M). +Include (UWFacts_fun K M). +Require Import FMapFacts2. +Include (UWFacts_fun K M)." +"Set Implicit Arguments. + +Require Import String. + +Definition glabel := (string * string)%type. + +" +"Set Implicit Arguments. + +Require Import StringMap. +Module K := String_as_UDT. +Module M := StringMap. +Require Import FMapFacts. +Include (Properties M). +Include (Facts M). +Require Import FMapFacts1. +Include (WFacts_fun K M). +Include (UWFacts_fun K M). +Require Import FMapFacts2. +Include (UWFacts_fun K M). +" +"Require Import Bedrock ConnectDriver AMD64_gas. + +Module M. + Definition heapSize := 1024 * 10. +End M. + +Module E := Make(M). + +Definition compiled := moduleS E.m. +Recursive Extraction compiled. +" +"Set Implicit Arguments. + +Module Type ADT. + + Parameter ADTValue : Type. + +End ADT. + + +(* + Record ADT := + { + Model : Type + }. + + Record ADTValue := + { + Type_ : ADT; + Value : Model Type_ + }. + *) + +" +"Require Import AutoSep. +Require Import Syntax. +Require Import SyntaxExpr Memory IL String. + +Set Implicit Arguments. + +Coercion Const : W >-> Expr. +Coercion Var : string >-> Expr. + +Infix ""+"" := (SyntaxExpr.Binop Plus) : expr_scope. +Infix ""-"" := (SyntaxExpr.Binop Minus) : expr_scope. +Infix ""*"" := (SyntaxExpr.Binop Times) : expr_scope. +Infix ""="" := (SyntaxExpr.TestE IL.Eq) : expr_scope. +Infix ""<>"" := (SyntaxExpr.TestE IL.Ne) : expr_scope. +Infix ""<"" := (SyntaxExpr.TestE IL.Lt) : expr_scope. +Infix ""<="" := (SyntaxExpr.TestE IL.Le) : expr_scope. + +Delimit Scope expr_scope with expr. +Local Open Scope expr. + +Infix "";;"" := Syntax.Seq : stmt_scope. + +Notation ""\'skip\'"" := Syntax.Skip : stmt_scope. + +Notation ""\'If\' cond { trueStmt } \'else\' { falseStmt }"" := (Syntax.If cond%expr trueStmt falseStmt) : stmt_scope. + +Notation ""x <- e"" := (Syntax.Assign x e%expr) : stmt_scope. + +Delimit Scope stmt_scope with stmt. +Local Open Scope stmt. + +Definition DirectCall x f args := (Syntax.Label ""_f"" f ;; Syntax.Call x ""_f"" args)%stmt. + +Notation ""\'DCall\' f ()"" := (DirectCall None f nil) + (no associativity, at level 95, f at level 0) : stmt_scope. + +Notation ""\'DCall\' f ( x1 , .. , xN )"" := (DirectCall None f (cons x1 (.. (cons xN nil) ..))%expr) + (no associativity, at level 95, f at level 0) : stmt_scope. + +Notation ""x <-- \'DCall\' f ()"" := (DirectCall (Some x) f nil) + (no associativity, at level 95, f at level 0) : stmt_scope. + +Notation ""x <-- \'DCall\' f ( x1 , .. , xN )"" := (DirectCall (Some x) f (cons x1 (.. (cons xN nil) ..))%expr) (no associativity, at level 95, f at level 0) : stmt_scope. + +Notation ""a ! b"" := (a, b) (only parsing) : stmt_scope. + +Local Close Scope stmt. +Local Close Scope expr. +" +"Require Import StringSet. +Import StringSet. + +Set Implicit Arguments. + +Definition union_list ls := List.fold_right union empty ls." +"Require Import Bedrock XmlTest2Driver AMD64_gas. + +Definition compiled := moduleS E.m. +Recursive Extraction compiled. +" +"Require Import Bedrock Echo3Driver AMD64_gas. + +Module M. + Definition heapSize := 1024. +End M. + +Module E := Make(M). + +Definition compiled := moduleS E.m. +Recursive Extraction compiled. +" +"Require Import Bedrock XmlTestDriver AMD64_gas. + +Definition compiled := moduleS E.m. +Recursive Extraction compiled. +" +"Set Implicit Arguments. + +Require Import GLabelKey. +Module K := GLabel_as_UDT. +Require Import GLabelMap. +Module M := GLabelMap. +Require Import FMapFacts. +Include (Properties M). +Include (Facts M). +Require Import FMapFacts1. +Include (WFacts_fun K M). +Include (UWFacts_fun K M). +Require Import FMapFacts2. +Include (UWFacts_fun K M). +" +"Require Import Bedrock MiniMasterDriver AMD64_gas. + +Definition compiled := moduleS E.m. +Recursive Extraction compiled. +" +"Notation ""$$ x"":= (Const ($ x)) (at level 0): expr_scope. +Notation ""## x"":= (Var x) (at level 0): expr_scope. +Infix "".+"":= (Binop Plus) (at level 50): expr_scope. +Infix "".-"":= (Binop Minus) (at level 50): expr_scope. +Infix "".*"":= (Binop Times) (at level 50): expr_scope. +Infix "".="":= (TestE Eq) (at level 50): expr_scope. +Infix "".<>"":= (TestE Ne) (at level 50): expr_scope. +Infix "".<"":= (TestE Lt) (at level 50): expr_scope. +Infix "".<="":= (TestE Le) (at level 50): expr_scope. + +Delimit Scope expr_scope with expr. +" +"Require Import List. + +Set Implicit Arguments. + +Definition max_list := fold_right max. + +" +"Require Import PreAutoSep. + +Export PreAutoSep. + +Require Import Bool StreamParse ArrayQuery. +Export StreamParse ArrayQuery. + +Ltac vcgen_simp := cbv beta iota zeta delta [map app imps + LabelMap.add Entry Blocks Postcondition VerifCond + Straightline_ Seq_ Diverge_ Fail_ Skip_ Assert_ + Structured.If_ Structured.While_ Goto_ Structured.Call_ IGoto + setArgs Programming.Reserved Programming.Formals Programming.Precondition + importsMap fullImports buildLocals blocks union Nplus Nsucc length N_of_nat + List.fold_left ascii_lt string_lt label'_lt + LabelKey.compare' LabelKey.compare LabelKey.eq_dec + LabelMap.find + toCmd Seq Instr Diverge Fail Skip Assert_ + Programming.If_ Programming.While_ Goto Programming.Call_ RvImm' + Assign' localsInvariant + regInL lvalIn immInR labelIn variableSlot string_eq ascii_eq + andb eqb qspecOut + ICall_ Structured.ICall_ + Assert_ Structured.Assert_ + LabelMap.Raw.find LabelMap.this LabelMap.Raw.add + LabelMap.empty LabelMap.Raw.empty string_dec + Ascii.ascii_dec string_rec string_rect sumbool_rec sumbool_rect Ascii.ascii_rec Ascii.ascii_rect + Bool.bool_dec bool_rec bool_rect eq_rec_r eq_rec eq_rect eq_sym + fst snd labl + Ascii.N_of_ascii Ascii.N_of_digits N.compare Nmult Pos.compare Pos.compare_cont + Pos.mul Pos.add LabelMap.Raw.bal + Int.Z_as_Int.gt_le_dec Int.Z_as_Int.ge_lt_dec LabelMap.Raw.create + ZArith_dec.Z_gt_le_dec Int.Z_as_Int.plus Int.Z_as_Int.max LabelMap.Raw.height + ZArith_dec.Z_gt_dec Int.Z_as_Int._1 BinInt.Z.add Int.Z_as_Int._0 Int.Z_as_Int._2 BinInt.Z.max + ZArith_dec.Zcompare_rec ZArith_dec.Z_ge_lt_dec BinInt.Z.compare ZArith_dec.Zcompare_rect + ZArith_dec.Z_ge_dec label'_eq label'_rec label'_rect + COperand1 CTest COperand2 Pos.succ + makeVcs + + Cond_ Cond + Lambda__ Lambda_ + + Wrap.Wrap + Parse1 ParseOne ParseOne' + Query ForArray +]. + +Ltac vcgen := + structured_auto vcgen_simp; + autorewrite with sepFormula in *; simpl in *; + unfold starB, hvarB, hpropB in *; fold hprop in *; refold. +" +"Require Import Bedrock RosMasterDriver AMD64_gas. + +Definition compiled := moduleS E.m. +Recursive Extraction compiled. +" +"Set Implicit Arguments. + +Require Import StringSet. +Import StringSet. +Require Import FSetProperties. +Module Import Properties := Properties StringSet. +Import FM. + +Local Infix ""+"" := union. +Local Infix ""<="" := Subset. + +Ltac subset_solver := + repeat + match goal with + | |- ?A <= ?A => eapply subset_refl + | |- empty <= _ => eapply subset_empty + | |- _ + _ <= _ => eapply union_subset_3 + | |- ?S <= ?A + _ => + match A with + context [ S ] => eapply subset_trans; [ | eapply union_subset_1] + end + | |- ?S <= _ + ?B => + match B with + context [ S ] => eapply subset_trans; [ .. | eapply union_subset_2] + end + end. +" +"Require Import Bedrock ListBuilderDriver AMD64_gas. + +Module M. + Definition heapSize := 1024. +End M. + +Module E := Make(M). + +Definition compiled := moduleS E.m. +Recursive Extraction compiled. +" +"Require Import Bedrock ArrayTestDriver AMD64_gas. + +Module M. + Definition heapSize := 1024. +End M. + +Module E := Make(M). + +Definition compiled := moduleS E.m1. +Recursive Extraction compiled. +" +"Set Implicit Arguments. + +Section Body. + + Require Import AutoSep. + Variable vars : list string. + + Variable temp_size : nat. + + Variable imports : LabelMap.t assert. + + Variable imports_global : importsGlobal imports. + + Variable modName : string. + + Require Import SemanticsExpr. + + Definition stack_slot n := LvMem (Sp + (4 * n)%nat)%loc. + Definition vars_start := 4 * 2. + Definition var_slot x := LvMem (Sp + (vars_start + variablePosition vars x)%nat)%loc. + Definition temp_start := vars_start + 4 * length vars. + Definition temp_slot n := LvMem (Sp + (temp_start + 4 * n)%nat)%loc. + Definition frame_len := temp_start + 4 * temp_size. + Definition frame_len_w := natToW frame_len. + Definition callee_stack_start := frame_len. + Definition callee_stack_slot n := LvMem (Sp + (callee_stack_start + 4 * n)%nat)%loc. + + Definition Seq2 := @Seq_ _ imports_global modName. + + Definition Strline := Straightline_ imports modName. + + Definition Skip__ := Skip_ imports modName. + + Definition If__ := Structured.If_ imports_global. + + Definition While__ := Structured.While_ imports_global. + + Fixpoint Seq__ ls := + match ls with + | nil => Skip__ + | a :: ls' => Seq2 a (Seq__ ls') + end. + + Definition SaveRv lv := Strline (IL.Assign lv (RvLval (LvReg Rv)) :: nil). + + Definition CheckExtraStack (n : nat) cmd := + Seq2 + (Strline (IL.Assign Rv (stack_slot 1) :: nil)) + (Structured.If_ imports_global n Le Rv cmd + (Diverge_ imports modName)). + + Require SaveRet. + Local Open Scope nat. + + Require Import ConvertLabel. + Import Syntax. + Variable loop_inv : Expr -> Stmt -> Stmt -> assert. + Variable after_call : option string -> Stmt -> assert. + Variable compile_expr : Expr -> nat -> cmd imports modName. + Variable compile_exprs : list Expr -> nat -> nat -> cmd imports modName. + + Fixpoint cmp (s k : Stmt) : cmd imports modName := + match s with + | Syntax.Skip => + Skip__ + | Syntax.Seq a b => + Seq2 (cmp a (Syntax.Seq b k)) + (cmp b k) + | Syntax.If cond t f => + Seq2 (compile_expr cond 0) + (If__ Rv Ne (natToW 0) (cmp t k) (cmp f k)) + | Syntax.While cond body => + Seq2 (compile_expr cond 0) + (While__ (loop_inv cond body k) Rv Ne (natToW 0) + (Seq2 (cmp body (Syntax.Seq (Syntax.While cond body) k)) + (compile_expr cond 0))) + | Syntax.Call var f args => + let callee_frame_len := 2 + length args in + CheckExtraStack + callee_frame_len + (Seq__ + (compile_exprs + args 0 (callee_stack_start + 8) + :: compile_expr f 0 + :: Strline + (IL.Binop + (callee_stack_slot 1) (stack_slot 1) Minus callee_frame_len + :: IL.Binop Sp Sp Plus frame_len_w :: nil) + :: Structured.ICall_ imports modName Rv (after_call var k) + :: Strline (IL.Binop Sp Sp Minus frame_len_w :: nil) + :: SaveRet.compile vars var imports_global modName :: nil)) + | Syntax.Label x lbl => + Strline (IL.Assign (var_slot x) lbl :: nil) + | Syntax.Assign x e => + Seq2 (compile_expr e 0) + (SaveRv (var_slot x)) + end. + +End Body. + +Require Import ADT. +Require Import RepInv. + +Module Make (Import E : ADT) (Import M : RepInv E). + + Require Import Inv. + Module Import InvMake := Make E. + Import SemanticsMake. + Module Import InvMake2 := Make M. + + Section TopSection. + + Variable vars : list string. + + Variable temp_size : nat. + + Variable rv_postcond : W -> vals -> Prop. + + Definition loop_inv cond body k : assert := + let s := Syntax.Seq (Syntax.While cond body) k in + inv_template vars temp_size (fun rv v => rv = eval (fst v) cond) rv_postcond s. + + Require Import Malloc. + Require Import Semantics. + + Definition after_call ret k : assert := + st ~> Ex fs, + let stn := fst st in + funcs_ok stn fs /\\ + ExX, Ex vs, Ex heap1, Ex heap2, Ex temps, Ex rp, Ex e_stack, Ex ret_w, Ex ret_a, + let old_sp := st#Sp ^- (frame_len_w vars temp_size) in + ![^[is_state old_sp rp e_stack e_stack vars (vs, heap1) temps * is_heap heap2 * layout_option ret_w ret_a * mallocHeap 0] * #0] st /\\ + let env := (ConvertLabel.from_bedrock_label_map (Labels stn), fs stn) in + [| let vs := upd_option vs ret st#Rv in + let heap12 := heap_merge heap1 heap2 in + let heap := heap_upd_option heap12 ret_w ret_a in + let v := (vs, heap) in + (separated heap12 ret_w ret_a -> Safe env k v) /\\ + length temps = temp_size |] /\\ + (rp, stn) + @@@ ( + st' ~> Ex v', Ex temps', + ![^[is_state st'#Sp rp e_stack e_stack vars v' temps' * mallocHeap 0] * #1] st' /\\ + [| let vs := upd_option vs ret st#Rv in + let heap12 := heap_merge heap1 heap2 in + let heap := heap_upd_option heap12 ret_w ret_a in + let v := (vs, heap) in + separated heap12 ret_w ret_a /\\ + RunsTo env k v v' /\\ + length temps' = temp_size /\\ + st'#Sp = old_sp /\\ + rv_postcond st'#Rv (fst v') |]). + + Variable imports : LabelMap.t assert. + + Variable imports_global : importsGlobal imports. + + Variable modName : string. + + Require CompileExpr. + + Definition compile_expr e n := CompileExpr.compile vars temp_size imports_global modName e n. + + Require CompileExprs. + + Definition compile_exprs es n dst := CompileExprs.compile vars temp_size es n dst imports_global modName. + + Definition compile := cmp vars temp_size imports_global loop_inv after_call compile_expr compile_exprs. + + End TopSection. + +End Make." +"Require Import AutoSep. +Require Import ListFactsNew. + +Ltac hide_upd_sublist := + repeat match goal with + | H : context [ upd_sublist ?L _ _ ] |- _ => set (upd_sublist L _ _) in * + end. + +" +"Require Import Bedrock Factorial AMD64_gas. + +Definition compiled := moduleS factProg. +Recursive Extraction compiled. +" +"Require Import Bedrock SharedListDriver AMD64_gas. + +Module M. + Definition heapSize := 1024. +End M. + +Module E := Make(M). + +Definition compiled := moduleS E.m. +Recursive Extraction compiled. +" +"Set Implicit Arguments. + +Require Import Labels. +Require Import GLabel. + +Definition to_bedrock_label (l : glabel) : label := (fst l, Global (snd l)). + +Coercion to_bedrock_label : glabel >-> label. + +Definition from_bedrock_label_map A (f : label -> A) (lbl : glabel) := f lbl. + +" +"Require Import Syntax. + +Notation skip := Syntax.Skip. + +Infix "";:"" := Syntax.Seq (left associativity, at level 110). + +" +"Ltac unfold_all := + repeat match goal with + | H := _ |- _ => unfold H in *; clear H + end. + +Ltac inv_clear H := + inversion H; unfold_all; subst; clear H. + +Ltac eapply_in_any t := + match goal with + H : _ |- _ => eapply t in H + end. + +" +"Require Import SyntaxExpr. + +(* The depth of stack actually used by compileExpr *) +Fixpoint depth expr := + match expr with + | Var _ => 0 + | Const _ => 0 + | Binop _ a b => max (depth a) (S (depth b)) + | TestE _ a b => max (depth a) (S (depth b)) + end. + +" +"Require Import UseCellDriver AMD64_gas. + +Module M. + Definition heapSize := 1024. +End M. + +Module E := Make(M). + +Definition compiled := moduleS E.m1. +Recursive Extraction compiled. +" +"Set Implicit Arguments. + +Require Import WordKey. +Module K := W_as_UDT. +Require Import WordMap. +Module M := WordMap. +Require Import FMapFacts. +Include (Properties M). +Include (Facts M). +Require Import FMapFacts1. +Include (WFacts_fun K M). +Include (UWFacts_fun K M). +Require Import FMapFacts2. +Include (UWFacts_fun K M). +" +"Require Import SyntaxExpr SemanticsExpr. +Require Import List. + +Fixpoint varsIn expr:= +match expr with + | Var s => s :: nil + | Const w => nil + | SyntaxExpr.Binop op a b => varsIn a ++ varsIn b + | SyntaxExpr.TestE op a b => varsIn a ++ varsIn b +end. + +" +"Require Import Bedrock RtosDriver I386_gas. + +Module M. + Definition heapSize := (1024 * 1024)%N. +End M. + +Module E := Make(M). + +Definition compiled := moduleS E.m. +Recursive Extraction compiled. +" +"Require Import List. +Require Import IL. +Require Import ReifyExpr. +Require Import SymIL. + +(* Reify the instructions *) +Ltac collectTypes_loc isConst l Ts k := + match l with + | Reg _ => k Ts + | Imm ?i => ReifyExpr.collectTypes_expr isConst i Ts k + | Indir _ ?i => ReifyExpr.collectTypes_expr isConst i Ts k + end. +Ltac reify_loc isConst l types funcs uvars vars k := + match l with + | Reg ?r => + let res := constr:(@SymReg types r) in + k uvars funcs res + | Imm ?i => + ReifyExpr.reify_expr isConst i types funcs uvars vars ltac:(fun uvars funcs i => + let l := constr:(@SymImm types i) in k uvars funcs l) + | Indir ?r ?i => + ReifyExpr.reify_expr isConst i types funcs uvars vars ltac:(fun uvars funcs i => + let l := constr:(@SymIndir types r i) in k uvars funcs l) + end. + +Ltac collectTypes_lvalue isConst l Ts k := + match l with + | LvReg _ => k Ts + | LvMem ?l => collectTypes_loc isConst l Ts k + | LvMem8 ?l => collectTypes_loc isConst l Ts k + end. + +Ltac reify_lvalue isConst l types funcs uvars vars k := + match l with + | LvReg ?r => let l := constr:(@SymLvReg types r) in k uvars funcs l + | LvMem ?l => + reify_loc isConst l types funcs uvars vars ltac:(fun uvars funcs l => + let l := constr:(@SymLvMem types l) in k uvars funcs l) + | LvMem8 ?l => + reify_loc isConst l types funcs uvars vars ltac:(fun uvars funcs l => + let l := constr:(@SymLvMem8 types l) in k uvars funcs l) + end. + +Ltac collectTypes_rvalue isConst r Ts k := + match r with + | RvLval ?l => collectTypes_lvalue isConst l Ts k + | RvImm ?i => ReifyExpr.collectTypes_expr isConst i Ts k + | RvLabel _ => let Ts := Reflect.cons_uniq label Ts in k Ts + end. + +Ltac reify_rvalue isConst r types funcs uvars vars k := + match r with + | RvLval ?l => + reify_lvalue isConst l types funcs uvars vars ltac:(fun uvars funcs l => + let l := constr:(@SymRvLval types l) in k uvars funcs l) + | RvImm ?i => + ReifyExpr.reify_expr isConst i types funcs uvars vars ltac:(fun uvars funcs i => + let l := constr:(@SymRvImm types i) in k uvars funcs l) + | RvLabel ?l => + let r := constr:(@SymRvLabel types l) in k uvars funcs r + end. + +Ltac collectTypes_instr isConst i Ts k := + match i with + | Assign ?l ?r => + collectTypes_lvalue isConst l Ts ltac:(fun Ts => + collectTypes_rvalue isConst r Ts k) + | Binop ?l ?r1 _ ?r2 => + collectTypes_lvalue isConst l Ts ltac:(fun Ts => + collectTypes_rvalue isConst r1 Ts ltac:(fun Ts => + collectTypes_rvalue isConst r2 Ts k )) + end. +Ltac reify_instr isConst i types funcs uvars vars k := + match i with + | Assign ?l ?r => + reify_lvalue isConst l types funcs uvars vars ltac:(fun uvars funcs l => + reify_rvalue isConst r types funcs uvars vars ltac:(fun uvars funcs r => + let res := constr:(@SymAssign types l r) in k uvars funcs res)) + | Binop ?l ?r1 ?o ?r2 => + reify_lvalue isConst l types funcs uvars vars ltac:(fun uvars funcs l => + reify_rvalue isConst r1 types funcs uvars vars ltac:(fun uvars funcs r1 => + reify_rvalue isConst r2 types funcs uvars vars ltac:(fun uvars funcs r2 => + let res := constr:(@SymBinop types l r1 o r2) in k uvars funcs res))) + end. + +Ltac collectTypes_instrs isConst is Ts k := + match is with + | nil => k Ts + | ?i :: ?is => + collectTypes_instr isConst i Ts ltac:(fun Ts => + collectTypes_instrs isConst is Ts k) + end. +Ltac reify_instrs isConst is types funcs uvars vars k := + match is with + | nil => + let is := constr:(@nil (sym_instr types)) in k uvars funcs is + | ?i :: ?is => + reify_instr isConst i types funcs uvars vars ltac:(fun uvars funcs i => + reify_instrs isConst is types funcs uvars vars ltac:(fun uvars funcs is => + let res := constr:(i :: is) in k uvars funcs res)) + end." +"Require Import Bedrock RosMasterDriver I386_gas. + +Definition compiled := moduleS E.m. +Recursive Extraction compiled. +" +"Module Type S. + + Parameter t : Type. + +End S." +"Require Import FactorialRecurDriver AMD64_gas. + +Module M. + Definition heapSize := 1024. +End M. + +Module E := Make(M). + +Definition compiled := moduleS E.m1. +Recursive Extraction compiled. +" +"(* FastString -- speedy versions of string functions from String + +This library defines tail-recursive, unverified versions of some of the +functions in String. It\'s intended to be used in unverified applications +(e.g., the Bedrock assembly generator) where speed is important. *) + +Require Import Ascii List. +Require Export String. + +Module Import ForReverse. + + Fixpoint foldString {A} (f : A -> ascii -> A) (str : string) (zero : A) : A := + match str with + | EmptyString => zero + | String character str\' => foldString f str\' (f zero character) + end. + + Definition prependReversed : string -> string -> string := + foldString (fun char str => String str char). + +End ForReverse. + +Definition reverse str := prependReversed str """". + +Definition concat (strs : list string) : string := + reverse (fold_left (fun x y => prependReversed y x) strs """"%string). + +Definition append x y := concat (x :: y :: nil). +Infix ""++"" := append : string_scope. + + +(* Intercalate. This implementation is direct from the Haskell base +package. *) + +Module Import ForIntercalate. + Fixpoint prependToAll (sep : string) (xs : list string) := + match xs with + | nil => nil + | x :: xs => sep :: x :: prependToAll sep xs + end. +End ForIntercalate. + +Definition intersperse (sep : string) (xs : list string) : list string := + match xs with + | nil => nil + | x :: xs => x :: prependToAll sep xs + end. + +Definition intercalate (sep : string) (xs : list string) : string := + concat (intersperse sep xs). +" +"Require Import Bedrock CallbackDriver AMD64_gas. + +Definition compiled := moduleS E.m. +Recursive Extraction compiled. +" +"Require Import Bedrock MiniMasterDriver I386_gas. + +Definition compiled := moduleS E.m. +Recursive Extraction compiled. +" +"Set Implicit Arguments. + +Require Import Syntax. +Require Import String. + +Record FuncCore := + { + ArgVars : list string; + RetVar : string; + Body : Stmt + }. + +" +"Require Import FreeVarsExpr. +Require Import Syntax. +Require Import StringSet. +Require Import Option. +Require Import Union. +Import StringSet. + +Set Implicit Arguments. + +Local Notation e_free_vars := FreeVarsExpr.free_vars. + +Fixpoint free_vars (s : Syntax.Stmt) := + match s with + | Syntax.Skip => empty + | Syntax.Seq a b => union (free_vars a) (free_vars b) + | Syntax.If cond t f => union (union (e_free_vars cond) (free_vars t)) (free_vars f) + | Syntax.While cond body => union (e_free_vars cond) (free_vars body) + | Syntax.Call var f args => + union + (union + (default empty (option_map singleton var)) + (e_free_vars f)) + (union_list (List.map e_free_vars args)) + | Syntax.Label x lbl => singleton x + | Syntax.Assign x e => union (singleton x) (e_free_vars e) + end. + +" +"Require Export String List NArith. + +Require Export Heaps SepTheoryX SepIL. + +Require Export Nomega Word Memory IL LabelMap PropX PropXTac XCAP Structured StructuredModule Linker Programming. + +Require Export ILTac SymILTac Arrays Allocated. + +Open Scope string_scope. +" +"Require Import Syntax. +Require DepthExpr. +Require Import Max. + +Set Implicit Arguments. + +Local Notation edepth := DepthExpr.depth. + +Fixpoint depth statement := + match statement with + | Syntax.Skip => 0 + | Syntax.Seq a b => max (depth a) (depth b) + | Syntax.If cond t f => max (edepth cond) (max (depth t) (depth f)) + | While cond body => max (edepth cond) (depth body) + | Syntax.Call _ f args => max (edepth f) (max_list 0 (List.map edepth args)) + | Syntax.Label _ _ => 0 + | Syntax.Assign _ e => edepth e + end." +"Set Implicit Arguments. + +Ltac not_not := + match goal with + | H : ~ _ |- ~ _ => unfold not; intro; contradict H + end. + +Ltac nintro := unfold not; intros. + +" +"Require Import Bedrock PrintIntDriver AMD64_gas. + +Module M. + Definition heapSize := 1024. +End M. + +Module E := Make(M). + +Definition compiled := moduleS E.m1. +Recursive Extraction compiled. +" +"Require Import Bedrock RtosDriver AMD64_gas. + +Module M. + Definition heapSize := (1024 * 1024)%N. +End M. + +Module E := Make(M). + +Definition compiled := moduleS E.m. +Recursive Extraction compiled. +" +"Require Import SyntaxExpr. +Require Import StringSet. +Import StringSet. + +Set Implicit Arguments. + +Fixpoint free_vars expr:= + match expr with + |Var s => singleton s + |Const w => empty + |Binop op a b => union (free_vars a) (free_vars b) + |TestE te a b => union (free_vars a) (free_vars b) + end. + +" +"Require Import SyntaxFunc. +Require Import String. +Export SyntaxFunc. + +Set Implicit Arguments. + +Record Module := + { + Name : string; + Functions : list Func + }." +"Require Import AutoSep Malloc. + +Require Import WordKey. + +Require Import MSetRBT. +Module WordSet := Make W_as_OT_new. + +Section adt. + Variable P : WordSet.t -> W -> HProp. + Variable res : nat. + + Definition newS := SPEC(""extra_stack"") reserving res + PRE[_] mallocHeap 0 + POST[R] P WordSet.empty R * mallocHeap 0. + + Definition deleteS := SPEC(""extra_stack"", ""self"") reserving res + Al s, + PRE[V] P s (V ""self"") * mallocHeap 0 + POST[_] mallocHeap 0. + + Definition memS := SPEC(""extra_stack"", ""self"", ""n"") reserving res + Al s, + PRE[V] P s (V ""self"") * mallocHeap 0 + POST[R] [| R = WordSet.mem (V ""n"") s |] * P s (V ""self"") * mallocHeap 0. + + Definition addS := SPEC(""extra_stack"", ""self"", ""n"") reserving res + Al s, + PRE[V] P s (V ""self"") * mallocHeap 0 + POST[_] P (WordSet.add (V ""n"") s) (V ""self"") * mallocHeap 0. + + Definition sizeS := SPEC(""extra_stack"", ""self"") reserving res + Al s, + PRE[V] P s (V ""self"") * mallocHeap 0 + POST[R] [| R = WordSet.cardinal s |] * P s (V ""self"") * mallocHeap 0. +End adt. +" +"Require Import ReturnZeroDriver AMD64_gas. + +Module M. + Definition heapSize := 1024. +End M. + +Module E := Make(M). + +Definition compiled := moduleS E.m1. +Recursive Extraction compiled. +" +"Set Implicit Arguments. + +Require Import WordKey. + +Require Import FMapAVL. +Module Import WordMap := Make W_as_OT. +" +"Set Implicit Arguments. + +Require Import StringSet. +Require Import Equalities. +Module K := Make_UDT StringKey. +Module M := StringSet. +Require Import FSetProperties. +Include (Properties M). +Require Import FSetFacts. +Include (Facts M). +Require Import FSetFacts1. +Include (UWFacts_fun K M). +" +"Require Import String. + +Definition impl_module_name s := (""__impl_"" ++ s)%string." +"Require Import Word. + +Definition B := word 8. +Definition W := word 32. + +Section mem_ops. + Variable addr mem : Type. + Variable footprint_w : addr -> addr * addr * addr * addr. + + Variable mem_get : mem -> addr -> option B. + + Definition mem_get_word (implode : B * B * B * B -> W) (p : addr) (m : mem) + : option W := + let '(a,b,c,d) := footprint_w p in + match mem_get m a , mem_get m b , mem_get m c , mem_get m d with + | Some a , Some b , Some c , Some d => + Some (implode (a,b,c,d)) + | _ , _ , _ , _ => None + end. + + Variable mem_set : mem -> addr -> B -> option mem. + + Definition mem_set_word (explode : W -> B * B * B * B) (p : addr) (v : W) + (m : mem) : option mem := + let '(a,b,c,d) := footprint_w p in + let '(av,bv,cv,dv) := explode v in + match mem_set m d dv with + | Some m => match mem_set m c cv with + | Some m => match mem_set m b bv with + | Some m => mem_set m a av + | None => None + end + | None => None + end + | None => None + end. + +End mem_ops. +" +"Require Import IL Memory String. +Require Import SyntaxExpr. + +Set Implicit Arguments. + +Fixpoint eval vs expr := + match expr with + | Var str => vs str + | Const w => w + | Binop op a b => evalBinop op (eval vs a) (eval vs b) + | TestE op a b => if evalTest op (eval vs a) (eval vs b) then $1 else $0 + end." +"Set Implicit Arguments. + +Require Import GLabelKey. + +Require Import FMapAVL. +Module GLabelMap := Make GLabel_as_OT." +"Require Import Prover Env. +Require Import ILEnv. +Require provers.AssumptionProver. +Require provers.ReflexivityProver. +Require provers.WordProver. +Require provers.ArrayBoundProver. + +Set Implicit Arguments. +Set Strict Implicit. + +(** * The Combo Prover **) + +Definition comboTypes := repr_combine bedrock_types_r sep.Array.types_r. +Definition comboFuncs types' := repr_combine (bedrock_funcs_r (repr comboTypes types')) + (Array.funcs_r (repr comboTypes types')). + +Definition ComboProver : ProverPackage := +{| ProverTypes := comboTypes + ; ProverFuncs := comboFuncs + ; Prover_correct := fun ts fs => composite_ProverT_correct + (composite_ProverT_correct (provers.AssumptionProver.assumptionProver_correct _) + (provers.ReflexivityProver.reflexivityProver_correct _)) + (composite_ProverT_correct + (provers.WordProver.wordProver_correct (types' := repr comboTypes ts) (repr (comboFuncs ts) fs)) + (provers.ArrayBoundProver.boundProver_correct (types' := repr comboTypes ts) (repr (comboFuncs ts) fs))) +|}. +" +"Set Implicit Arguments. + +Definition default A def (x : option A) := + match x with + | Some v => v + | None => def + end." +"Require Import CountUniqueDriver AMD64_gas. + +Module M. + Definition heapSize := 1024. +End M. + +Module E := Make(M). + +Definition compiled := moduleS E.m1. +Recursive Extraction compiled. +" +"Require Import Bedrock Echo2Driver AMD64_gas. + +Module M. + Definition heapSize := 1024. +End M. + +Module E := Make(M). + +Definition compiled := moduleS E.m1. +Recursive Extraction compiled. +" +"Require Import AutoSep. + +Set Implicit Arguments. + + +Ltac make_Himp := match goal with + | [ |- interp _ (![?P] _ ---> ![?Q] _)%PropX ] => + let H := fresh in assert (P ===> Q); [ | rewrite sepFormula_eq in *; apply H ] + | [ |- himp _ ?P ?Q ] => let H := fresh in assert (H : P ===> Q); [ | apply H ] + end. +" +"Require Import FactorialDriver AMD64_gas. + +Module M. + Definition heapSize := 1024. +End M. + +Module E := Make(M). + +Definition compiled := moduleS E.m1. +Recursive Extraction compiled. +" +"Set Implicit Arguments. + +Require Import Syntax. +Require Import String. +Require Import FuncCore. +Export Syntax FuncCore. + +Record Func := + { + Name : string; + Core : FuncCore + }. + +Coercion Core : Func >-> FuncCore. + +" +"Require Parser. +Require Datatypes. +Require Analysis. +Require Word. + +Require Import ExtrOcamlBasic. +Require Import ExtrOcamlString. + +Extraction Language Ocaml. + +Extraction ""Main.ml"" Main.Make. +Extraction ""Parser.ml"" Parser.pinstrs Datatypes.get_token. +Extraction ""Analysis.ml"" Analysis.state Analysis.run_filter Word.wordToNat Word.natToWord. +" +"Require Import AutoSep Malloc. + + +Section adt. + Variable P : list W -> W -> HProp. + Variable res : nat. + + Definition newS := SPEC(""extra_stack"", ""len"") reserving res + PRE[V] [| goodSize (2 + wordToNat (V ""len"")) |] * mallocHeap 0 + POST[R] Ex ws, P ws R * [| length ws = wordToNat (V ""len"") |] * mallocHeap 0. + + Definition deleteS := SPEC(""extra_stack"", ""self"") reserving res + Al ws, + PRE[V] P ws (V ""self"") * mallocHeap 0 + POST[_] mallocHeap 0. + + Definition readS := SPEC(""extra_stack"", ""self"", ""n"") reserving res + Al ws, + PRE[V] P ws (V ""self"") * [| V ""n"" < natToW (length ws) |] * mallocHeap 0 + POST[R] [| R = Array.sel ws (V ""n"") |] * P ws (V ""self"") * mallocHeap 0. + + Definition writeS := SPEC(""extra_stack"", ""self"", ""n"", ""v"") reserving res + Al ws, + PRE[V] P ws (V ""self"") * [| V ""n"" < natToW (length ws) |] * mallocHeap 0 + POST[_] P (Array.upd ws (V ""n"") (V ""v"")) (V ""self"") * mallocHeap 0. +End adt. +" +"Require Import Bedrock AbortDriver AMD64_gas. + +Module M. + Definition heapSize := 1024. +End M. + +Module E := Make(M). + +Definition compiled := moduleS E.m1. +Recursive Extraction compiled. +" +"Require Import Bedrock EchoDriver AMD64_gas. + +Module M. + Definition heapSize := 1024. +End M. + +Module E := Make(M). + +Definition compiled := moduleS E.m1. +Recursive Extraction compiled. +" +"Set Implicit Arguments. + +Require Import GoodFunction. + +Definition IsGoodModuleName (s : string) := prefix ""_"" s = false. + +Record GoodModule := + { + Name : string; + GoodModuleName : IsGoodModuleName Name; + Functions : list GoodFunction; + NoDupFuncNames : NoDup (map (fun (f : GoodFunction) => SyntaxFunc.Name f) Functions) + }." +"Set Implicit Arguments. + +Require Import ADT. +Require Import RepInv. + +Module Make (Import E : ADT) (Import M : RepInv E). + + Require Import PostOk. + Module Import PostOkMake := Make E M. + Require Import VerifCondOk. + Module Import VerifCondOkMake := Make E M. + Import CompileStmtSpecMake. + Import InvMake. + Import Semantics. + Import SemanticsMake. + Import InvMake2. + + Section TopSection. + + Require Import AutoSep. + + Variable vars : list string. + + Variable temp_size : nat. + + Variable imports : LabelMap.t assert. + + Variable imports_global : importsGlobal imports. + + Variable modName : string. + + Require Import Syntax. + + Variable rv_postcond : W -> vals -> Prop. + + Notation do_compile := (CompileStmtImplMake.compile vars temp_size rv_postcond imports_global modName). + + Variable s k : Stmt. + + Require Import Wrap. + Definition compile : cmd imports modName. + refine ( + Wrap imports imports_global modName + (do_compile s k) + (fun _ => postcond vars temp_size k rv_postcond) + (verifCond vars temp_size s k rv_postcond) + _ _). + eapply post_ok. + eapply verifCond_ok. + Defined. + + End TopSection. + +End Make." +"Require Import XmlLang. +Export XmlOutput XmlLang. + + +Coercion XmlLang.Cdata : string >-> XmlLang.pat. +Notation ""$ x"" := (XmlLang.Var x) (at level 0) : pat_scope. +Notation ""$$ x"" := (XmlLang.TreeVar x) (at level 0) : pat_scope. +Infix ""/"" := XmlLang.Tag : pat_scope. +Infix ""&"" := XmlLang.Both (at level 41, right associativity) : pat_scope. +Infix "";;"" := XmlLang.Ordered : pat_scope. +Delimit Scope pat_scope with pat. +Bind Scope pat_scope with pat. + +Coercion Const : string >-> exp. +Notation ""$ x"" := (Input x) : exp_scope. +Delimit Scope exp_scope with exp. +Bind Scope exp_scope with exp. + +Notation ""col = e"" := ((col, e%exp) :: nil) : condition_scope. +Infix ""&&"" := app : condition_scope. +Delimit Scope condition_scope with condition. + +Coercion XCdata : string >-> xml. +Notation ""$ x"" := (XVar x) : out_scope. +Notation ""tab # col"" := (XColumn tab col) (at level 0) : out_scope. +Definition xcons (x : xml) (xs : list xml) : list xml := x :: xs. +Notation ""<*> tag x1 , .. , xN "" := (XTag tag (xcons x1 .. (xcons xN nil) ..)) + (tag at level 0) : out_scope. +Delimit Scope out_scope with out. +Notation ""\'From\' tab \'Where\' cond \'Write\' o"" := + (XSelect tab cond%condition o%out) + (at level 0, tab at level 0, cond at level 0, o at level 0) : out_scope. +Notation ""\'From\' tab \'Write\' o"" := + (XSelect tab nil o%out) + (at level 0, tab at level 0, o at level 0) : out_scope. +Definition forJoin (o : xml) := + match o with + | XColumn tab col => (tab, col) + | _ => ("""", """") + end. +Notation ""\'Join\' x1 \'to\' x2 ;;; o"" := + (let (tab1, col1) := forJoin x1 in + let (tab2, col2) := forJoin x2 in + XIfEqual tab1 col1 tab2 col2 o%out) + (at level 95, col1 at level 0, col2 at level 0, o at level 0) : out_scope. +Bind Scope out_scope with xml. + +Definition econs (x : exp) (xs : list exp) : list exp := x :: xs. +Notation ""\'Insert\' t ( e1 , .. , eN )"" := (XmlLang.Insert t (econs e1%exp .. (econs eN%exp nil) ..)) + (at level 0, t at level 0) : action_scope. +Notation ""\'Delete\' tab \'Where\' cond"" := + (Delete tab cond%condition) + (at level 0, tab at level 0, cond at level 0) : action_scope. +Notation ""\'Write\' o"" := (Output o%out) (at level 0, o at level 0) : action_scope. +Infix "";;"" := Seq : action_scope. +Notation ""\'IfHas\' tab \'Where\' cond \'then\' a1 \'else\' a2 \'end\'"" := + (IfExists tab cond%condition a1 a2) + (at level 0, tab at level 0, cond at level 0, a1 at level 0, a2 at level 0) : action_scope. +Delimit Scope action_scope with action. +Notation ""\'From\' tab \'Where\' cond \'Do\' a"" := + (XmlLang.Select tab cond%condition a%action) + (at level 0, tab at level 0, cond at level 0, a at level 0) : action_scope. +Notation ""\'From\' tab \'Do\' a"" := + (XmlLang.Select tab nil a%action) + (at level 0, tab at level 0, a at level 0) : action_scope. +Notation ""\'Send\' x1 \'Value\' x2"" := + (XmlLang.SendTo x1%out x2%out) (at level 0, x1 at level 0, x2 at level 0) : action_scope. +Bind Scope action_scope with action. + +Notation ""\'Match\' p \'Do\' a \'end\'"" := (Rule p%pat a%action) : program_scope. +Infix "";;"" := PSeq : program_scope. +Delimit Scope program_scope with program. +Bind Scope program_scope with program. + +Ltac wf\'\' := + match goal with + | [ |- exists t, _ /\\ Name t = ?s /\\ _ ] => + match goal with + | [ |- context[{| Name := s; Address := ?a; Schema := ?sch |}] ] => + exists {| Name := s; Address := a; Schema := sch |}; simpl; intuition + end + | _ => + repeat match goal with + | [ H : List.Exists _ _ |- _ ] => inversion H; clear H; subst + end; simpl in *; tauto + | _ => constructor + end. + +Ltac wf\' := + match goal with + | [ |- (_ <= _)%nat ] => compute; omega + | [ |- (_ >= _)%N ] => discriminate + | [ |- (_ < _)%N ] => reflexivity + | [ |- NoDup _ ] => NoDup + | [ |- twfs _ ] => repeat constructor + | [ |- uf _ ] => repeat (constructor; simpl; intuition (try congruence)) + | _ => simpl; intuition (try (congruence || reflexivity || NoDup)); repeat wf\'\' + end. + +Ltac wf := constructor; wf\'. +" +"// File example.v +// +// Below is an example of a comment that is mis-parsed by exuberant ctags. +// It uses the multi-line comment format, i.e. /* ... */ except that in +// this case, the character sequence immediately preceeding the closing +// delimiter is an asterisk. (Any even number of asterisks would have the +// same problem. +// The line immediately afterwards is used to demonstrate the problem. +// the module name 'wahoo' isn't recognised, because the parser mistakenly +// thinks we are still in a multi-line comment. +/* + * I am a multi-line comment + * I happen to end in a strange + * (but legal) way: **/ +module wahoo () +begin +end +" +"/************************************************************************** +**** +* test task one +* the line below has 53 asteriks +*****************************************************/ +task pass_task_1; +begin +end +endtask + +/************************************************************************** +**** +* test task one +* the line below has 54 asteriks +******************************************************/ +task fail_task_2; +begin +end +endtask + +/************************************************************************** +**** +* test function one +* the line below has 53 asteriks +*****************************************************/ +function pass_func_1; +begin +end +endfunction + +/************************************************************************** +**** +* test function two +* the line below has 54 asteriks +******************************************************/ +function fail_func_2; +begin +end +endfunction + +/************************************************************************** +**** +* test function one +* the line below has 53 asteriks +*****************************************************/ +`define pass_define_1 1'b1; + +/************************************************************************** +**** +* test function two +* the line below has 54 asteriks +******************************************************/ +`define fail_define_2 1'b1; +" +"// somewhat contrived, but i came across a real-life file that caused this +// crash. +value= +hello/ +world; +" +"/* + * In Verilog, the following two lines are both valid syntax: + * + * `define GUEST + * `define GUEST + * + * The first defines ""GUEST"" as existing, but with no assigned + * value. The second defines ""GUEST"" as existing with an + * assigned value. Ctags55 correctly handles both cases, but + * Ctags551 - Ctags554 only handles the `define with value + * correctly. Here is some test code to demonstrate this: + */ +`define HOSTA +`define HOSTB +`define HOSTC +`define HOSTD + +`define GUESTA 1 +`define GUESTB 2 +`define GUESTC 3 +`define GUESTD 4 +/* + * Ctags55 correctly generates a tag for all `defines in the + * code, but Ctags554 does not generate tags for ""HOSTB"" + * or ""HOSTD"". + */ +" +"/* +* +**/ +module top(outsig, insig); +output outsig; +input insig; +assign outsig = insig; +endmodule +" +"parameter ramaddr_0 = {1'b1,9'd0}; +" +"// Taken from http://www.europa.com/~celiac/fsm_samp.html + +// These are the symbolic names for states +parameter [1:0] //synopsys enum state_info + S0 = 2'h0, + S1 = 2'h1, + S2 = 2'h2, + S3 = 2'h3; + +// These are the current state and next state variables +reg [1:0] /* synopsys enum state_info */ state; +reg [1:0] /* synopsys enum state_info */ next_state; + + +// synopsys state_vector state + +always @ (state or y or x) +begin + next_state = state; + case (state) // synopsys full_case parallel_case + S0: begin + if (x) begin + next_state = S1; + end + else begin + + next_state = S2; + end + end + S1: begin + if (y) begin + next_state = S2; + end + else begin + next_state = S0; + end + end + S2: begin + if (x & y) begin + next_state = S3; + end + else begin + next_state = S0; + end + end + S3: begin + next_state = S0; + end + endcase +end + + +always @ (posedge clk or posedge reset) +begin + if (reset) begin + state <= S0; + end + else begin + state <= next_state; + end +end +" +"// http://www.eg.bucknell.edu/~cs320/1995-fall/verilog-manual.html#RTFToC33 + +// Digital model of a traffic light +// By Dan Hyde August 10, 1995 +module traffic; +parameter on = 1, off = 0, red_tics = 35, + amber_tics = 3, green_tics = 20; +reg clock, red, amber, green; + +// will stop the simulation after 1000 time units +initial begin: stop_at + #1000; $stop; +end + +// initialize the lights and set up monitoring of registers +initial begin: Init + red = off; amber = off; green = off; + $display("" Time green amber red""); + $monitor(""%3d %b %b %b"", $time, green, amber, red); +end + +// task to wait for \'tics\' positive edge clocks +// before turning light off +task light; + output color; + input [31:0] tics; + begin + repeat(tics) // wait to detect tics positive edges on clock + @(posedge clock); + color = off; + end +endtask + +// waveform for clock period of 2 time units +always begin: clock_wave + #1 clock = 0; + #1 clock = 1; +end + +always begin: main_process + red = on; + light(red, red_tics); // call task to wait + green = on; + light(green, green_tics); + amber = on; + light(amber, amber_tics); +end + +endmodule +" +"/* +Bugs item #762027, was opened at 2003-06-27 18:32 +Message generated for change (Tracker Item Submitted) made by Item Submitter +You can respond by visiting: +https://sourceforge.net/tracker/?func=detail&atid=106556&aid=762027&group_id=6556 + +Category: None +Group: None +Status: Open +Resolution: None +Priority: 5 +Submitted By: cdic (cdic) +Assigned to: Nobody/Anonymous (nobody) +Summary: multi-line definition w/o back-slash will be missing + +Initial Comment: +There is a small bug (language verilog): +*/ + wire N_84, N_83; // is ok. + + wire N_84, + N_83; // then N_83 will be missing in tags. +/* +Thanks for fixing it. + +cdic +*/ +" +"/** + * microcodeundefs.v - Microcoded Accumulator CPU + * Copyright (C) 2015 Orlando Arias, David Mascenik + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +`undef MCROM_WIDTH +`undef OFFSET_WIDTH +`undef AC_SOURCE +`undef WRITE_AC +`undef MAR_SOURCE +`undef WRITE_MAR +`undef MDR_SOURCE +`undef WRITE_MDR +`undef ALU_OP_SELECT +`undef PC_SOURCE +`undef WRITE_PC +`undef WRITE_FLAGS +`undef ALUCTL +`undef ROM_OFFSET_EN +`undef OFFSET_NEXT_SEL/* vim: set ts=4 tw=79 syntax=verilog */ +" +"/** + * clk_gen.v - Microcoded Accumulator CPU + * Copyright (C) 2015 Orlando Arias, David Mascenik + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 18:29:34 04/26/2015 +// Design Name: +// Module Name: clk_gen +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module clk_gen( +\t\tinput wire\t\t\t\tbutton, +\t\tinput wire\t\t\t\tclk, +\t\tinput wire\t\t\t\tres, +\t\toutput wire\t\t\t\tclk_div + ); + +\treg [3 : 0] ripple; +\tassign clk_div = &ripple; +\t +\talways @(posedge clk) begin +\t\tif(res) +\t\t\tripple <= 4'b0; +\t\telse begin +\t\t\tripple[0] <= button; +\t\t\tripple[1] <= ripple[0]; +\t\t\tripple[2] <= ripple[1]; +\t\t\tripple[3] <= ripple[2]; +\t\tend +\tend +endmodule +/* vim: set ts=4 tw=79 syntax=verilog */ +" +"/** + * microcodedefs.v - Microcoded Accumulator CPU + * Copyright (C) 2015 Orlando Arias, David Mascenik + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +`include ""aludefs.v"" +/* microcode ROM width */ +`define MCROM_WIDTH\t\t27 +`define OFFSET_WIDTH \t6 /* number of bits in microcode offset */ +/* microcode ROM word layout */ + +`define AC_SOURCE\t\t1:0\t\t\t\t/* accumulator source */ +`define WRITE_AC\t\t2\t\t\t\t/* enable write to accumulator */ +`define MAR_SOURCE\t\t3\t\t\t\t/* memory address register source */ +`define WRITE_MAR\t\t4\t\t\t\t/* enable write to memory address register */ +`define MDR_SOURCE\t\t6:5\t\t\t\t/* memory data register source */ +`define WRITE_MDR\t\t7\t\t\t\t/* enable write to memory data register */ +`define PC_SOURCE\t\t9:8\t\t\t\t/* program counter register source */ +`define WRITE_PC\t\t10\t\t\t\t/* enable write to program counter register */ +`define WRITE_IR\t\t11\t\t\t\t/* enable write to instruction register */ +`define WRITE_FLAGS\t\t12\t\t\t\t/* enable write to flags register */ +`define WRITE_MEM\t\t13\t\t\t\t/* enable write to memory */ +`define ALU_OP_SELECT\t16:14\t\t\t/* ALU operand selection */ +`define ALUCTL\t\t(16 + `ALUCTLW):17\t/* ALU control */ + +/* offset of next microcode address */ +`define OFFSET_NEXT\t\t(`MCROM_WIDTH - 2):(`MCROM_WIDTH - `OFFSET_WIDTH - 1) +/* offset selection */ +`define OFFSET_NEXT_SEL\t(`MCROM_WIDTH - 1) + +`include ""aluundefs.v""/* vim: set ts=4 tw=79 syntax=verilog */ +" +"/** + * ff_d.v - Microcoded Accumulator CPU + * Copyright (C) 2015 Orlando Arias, David Mascenik + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +`timescale 1ns / 1ps + +module ff_d #(parameter WIDTH=8) ( +\t\tinput wire\t\t[WIDTH - 1 : 0]\tD,\t\t/* data input */ +\t\tinput wire\t\t\t\t\t\ten,\t\t/* enable */ +\t\tinput wire\t\t\t\t\t\tclk,\t/* clock */ +\t\tinput wire\t\t\t\t\t\tres,\t/* synchronous active high reset */ +\t\toutput wire\t\t[WIDTH - 1 : 0]\tQ\t\t/* output */ + ); +\t +\treg [WIDTH - 1 : 0] storage; +\tassign Q = storage; +\t +\talways @(posedge clk) begin +\t\tif(res)\t\t\t\t\t\t\t\t\t/* handle synchronous reset */ +\t\t\tstorage <= {WIDTH{1'b0}}; +\t\telse if(en)\t\t\t\t\t\t\t\t/* handle save data */ +\t\t\tstorage <= D; +\tend +endmodule +/* vim: set ts=4 tw=79 syntax=verilog */ +" +"/** + * controller_unit_tb.v - Microcoded Accumulator CPU + * Copyright (C) 2015 Orlando Arias, David Mascenik + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +`timescale 1ns / 1ps + +module controller_unit_tb; + +\t/* input signals */ +\treg [7:0] opcode; +\treg clk; +\treg res; + +\t/* output signals */ +\twire [1:0] ac_source; +\twire write_ac; +\twire mar_source; +\twire write_mar; +\twire [1:0] mdr_source; +\twire write_mdr; +\twire write_flags; +\twire [1:0] pc_source; +\twire write_pc; +\twire write_ir; +\twire write_mem; +\twire [2:0] ALU_op_select; +\twire [2:0] ALUctl; + +\t/* unit under testing */ +\tcontroller_unit uut ( +\t\t\t.opcode(opcode), +\t\t\t.clk(clk), +\t\t\t.res(res), +\t\t\t.ac_source(ac_source), +\t\t\t.write_ac(write_ac), +\t\t\t.mar_source(mar_source), +\t\t\t.write_mar(write_mar), +\t\t\t.mdr_source(mdr_source), +\t\t\t.write_mdr(write_mdr), +\t\t\t.write_flags(write_flags), +\t\t\t.pc_source(pc_source), +\t\t\t.write_pc(write_pc), +\t\t\t.write_ir(write_ir), +\t\t\t.write_mem(write_mem), +\t\t\t.ALU_op_select(ALU_op_select), +\t\t\t.ALUctl(ALUctl) +\t\t); + +\tinitial begin +\t\t/* initialize signals */ +\t\topcode = 8\'h03; +\t\tclk = 0; +\t\tres = 1; + +\t\t$dumpfile(""controller_unit.vcd""); +\t\t$dumpvars; + +\t\t/* release reset */ +\t\t#100\tres = 0; +\t\t +\t\t/* finish simulation */ +\t\t#1000\t$finish; +\tend +\t +\talways +\t\t#50\t\tclk = ~clk; + +endmodule + +/* vim: set ts=4 tw=79 syntax=verilog */ +" +"/** + * processor.v - Microcoded Accumulator CPU + * Copyright (C) 2015 Orlando Arias, David Mascenik + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +`timescale 1ns / 1ps +`include ""aludefs.v"" +module processor( +\t\t/* inputs */ +\t\tinput wire\t\t\t\t\tclk,\t\t\t/* clock */ +\t\tinput wire\t\t\t\t\tres,\t\t\t/* reset */ +\t\tinput wire\t\t[15 : 0]\tinstruction_in,\t/* instruction word */ +\t\tinput wire\t\t[ 7 : 0]\tmdr_in,\t\t\t/* memory data input */ +\t\t/* outputs */ +\t\toutput wire\t\t[ 7 : 0]\tpc_out,\t\t\t/* program counter */ +\t\toutput wire\t\t[ 7 : 0]\tmdr_out,\t\t/* memory data output */ +\t\toutput wire\t\t[ 7 : 0]\tmar_out,\t\t/* memory address */ +\t\toutput wire\t\t\t\t\twrite_mem\t\t/* memory write enable */ + ); + +\t/* internal signals */ +\twire\t[15 : 0]\tinstruction;\t/* instruction register output */ +\twire\t[`FWIDTH - 1 : 0] flags;\t/* ALU flags register */ +\twire \t[ 7 : 0] \topcode,\t\t\t/* intruction opcode */ +\t\t\t\t\t\timmediate;\t\t/* instruction immediate constant */ +\twire\t[ 1 : 0]\tac_source;\t\t/* accumulator register source */ +\twire \t\t\t\twrite_ac,\t\t/* write accumulator register */ +\t\t\t\t\t\tmar_source,\t\t/* memory address register source */ +\t\t\t\t\t\twrite_mar;\t\t/* write memory address register */ +\twire\t[ 1 : 0]\tmdr_source;\t\t/* memory data register source */ +\twire\t\t\t\twrite_mdr,\t\t/* write memory data register */ +\t\t\t\t\t\twrite_flags;\t/* write flags register */ +\twire\t[ 1 : 0]\tpc_source;\t\t/* program counter register source */ +\twire\t\t\t\twrite_pc,\t\t/* write program counter register */ +\t\t\t\t\t\twrite_ir;\t\t/* write instruction register */ +\twire\t[ 2 : 0]\tALU_op_select;\t/* ALU operator select */ +\twire\t[`ALUCTLW - 1 : 0] ALUctl;\t/* ALU control signal bus */ +\t +\t +\tassign opcode = instruction[15 : 8]; +\tassign immediate = instruction[ 7 : 0]; + +\t/* instruction register */ +\tff_d #(.WIDTH(16)) ir ( +\t\t\t.D(instruction_in), +\t\t\t.en(write_ir), +\t\t\t.clk(clk), +\t\t\t.res(res), +\t\t\t.Q(instruction) +\t\t); + +\t/* control unit */ +\tcontroller_unit cr0 ( +\t\t\t/* inputs */ +\t\t\t.opcode(opcode), +\t\t\t.flags(flags), +\t\t\t.clk(clk), +\t\t\t.res(res), +\t\t\t/* outputs */ +\t\t\t.ac_source(ac_source), +\t\t\t.write_ac(write_ac), +\t\t\t.mar_source(mar_source), +\t\t\t.write_mar(write_mar), +\t\t\t.mdr_source(mdr_source), +\t\t\t.write_mdr(write_mdr), +\t\t\t.write_flags(write_flags), +\t\t\t.pc_source(pc_source), +\t\t\t.write_pc(write_pc), +\t\t\t.write_ir(write_ir), +\t\t\t.write_mem(write_mem), +\t\t\t.ALU_op_select(ALU_op_select), +\t\t\t.ALUctl(ALUctl) +\t\t); +\t\t +\t/* datapath */ +\tdatapath dp0 ( +\t\t\t.immediate(immediate), +\t\t\t.mdr_in(mdr_in), +\t\t\t.clk(clk), +\t\t\t.res(res), +\t\t\t.ac_source(ac_source), +\t\t\t.write_ac(write_ac), +\t\t\t.mar_source(mar_source), +\t\t\t.write_mar(write_mar), +\t\t\t.mdr_source(mdr_source), +\t\t\t.write_mdr(write_mdr), +\t\t\t.write_flags(write_flags), +\t\t\t.pc_source(pc_source), +\t\t\t.write_pc(write_pc), +\t\t\t.ALU_op_select(ALU_op_select), +\t\t\t.ALUctl(ALUctl), +\t\t\t.mar_out(mar_out), +\t\t\t.mdr_out(mdr_out), +\t\t\t.pc_out(pc_out), +\t\t\t.flags(flags) +\t\t); +endmodule +`include ""aluundefs.v"" +/* vim: set ts=4 tw=79 syntax=verilog */ +" +"/** + * clock_divider.v - Microcoded Accumulator CPU + * Copyright (C) 2015 Orlando Arias, David Mascenik + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +`timescale 1ns / 1ps + +module clock_divider( +\t\tinput wire\t\t\t\t\tclk, +\t\tinput wire\t\t\t\t\tres, +\t\tinput wire\t\t[ 1 : 0]\tprescaler, +\t\toutput wire\t\t\t\t\tclk_out + ); + +\treg \t\t\t\t\tclk_div; +\treg [ 2**16 - 1 : 0 ]\tcounter; +\treg [ 2**16 - 1 : 0 ]\tcounter2; +\t +\tassign clk_out = clk_div; +\t +\talways @(prescaler or clk or counter or counter2) begin +\t\tcase(prescaler) +\t\t\t2'b00:\tclk_div = clk; +\t\t\t2'b01:\tclk_div = counter[0]; +\t\t\t2'b10:\tclk_div = counter[2**16 - 1]; +\t\t\t2'b11:\tclk_div = counter2[2**8 - 1]; +\t\tendcase +\tend + +\talways @(posedge clk) begin +\t\tif(res) begin +\t\t\tcounter <= {(2**22 - 1){1'b0}}; +\t\t\tcounter2 <= {(2**22 - 1){1'b0}}; +\t\tend +\t\telse counter <= counter + 1'b1; +\tend +\t +\talways @(counter[2**16 - 1]) +\t\tcounter2 <= counter2 + 1'b1; +\t + +endmodule +/* vim: set ts=4 tw=79 syntax=verilog */ +" +"/** + * memory_decoder.v - Microcoded Accumulator CPU + * Copyright (C) 2015 Orlando Arias, David Mascenik + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +`timescale 1ns / 1ps + +/* memory decoder unit */ +module memory_decoder( +\t\tinput wire\t\t[ 7 : 0]\taddress,\t\t/* address input */ +\t\tinput wire\t\t[ 7 : 0]\tdata_in,\t\t/* data input */ +\t\tinput wire\t\t[ 7 : 0]\tswitch_in,\t\t/* I/O switch input */ +\t\tinput wire\t\t\t\t\tclk,\t\t\t/* clock */ +\t\tinput wire\t\t\t\t\tres,\t\t\t/* reset */ +\t\tinput wire\t\t\t\t\twrite_enable,\t/* memory write enable */ +\t\toutput wire\t\t[ 7 : 0]\tLED_status,\t\t/* I/O LED output */ +\t\toutput wire\t\t[ 7 : 0]\tdata_out\t\t/* memory data output */ + ); + +\t/* internal wires and registers */ +\twire\t[ 7 : 0]\tmemory_data_out; +\twire\t\t[ 7 : 0]\tswitch_data_out; +\t +\twire mem_write_enable, LED_write_enable; +\t +\t/* mask write to address 0xff for LED usage */ +\tassign mem_write_enable = write_enable & (~&address); +\t/* sram block */ +\tsram sram0 ( +\t\t\t.address(address), +\t\t\t.data_in(data_in), +\t\t\t.clk(clk), +\t\t\t.write_enable(mem_write_enable), +\t\t\t.data_out(memory_data_out) +\t\t); +\t +\t/* decode LED address */ +\tassign LED_write_enable = write_enable & (&address); +\t/* LED output driver flip flop */ +\tff_d #(.WIDTH(8)) led_driver0 ( +\t\t\t.D(data_in), +\t\t\t.en(LED_write_enable), +\t\t\t.clk(clk), +\t\t\t.res(res), +\t\t\t.Q(LED_status) +\t\t); +\t +\t/* switch input driver flip flop */ +\tff_d #(.WIDTH(8)) switch_driver0 ( +\t\t\t.D(switch_in), +\t\t\t.en(1'b1), +\t\t\t.clk(clk), +\t\t\t.res(res), +\t\t\t.Q(switch_data_out) +\t\t); +\t +\t/* decode read address */ +\tassign data_out = (~&address) ? memory_data_out : switch_data_out; +\t +endmodule +/* vim: set ts=4 tw=79 syntax=verilog */ +" +"/** + * ALU.v - Microcoded Accumulator CPU + * Copyright (C) 2015 Orlando Arias, David Mascenik + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +`timescale 1ns / 1ps +`include ""aludefs.v"" + +module ALU #(parameter WIDTH=8) ( +\t\tinput wire\t\t[WIDTH - 1 : 0] \top1, +\t\tinput wire\t\t[WIDTH - 1 : 0] \top2, +\t\tinput wire\t\t[`ALUCTLW - 1: 0]\tctl, +\t\tinput wire\t\t[`FWIDTH - 1 : 0]\tflags_in, +\t\toutput wire\t\t[WIDTH - 1 : 0] \tresult, +\t\toutput wire\t\t[`FWIDTH - 1 : 0]\tflags_out + ); +\t +\t/* internal signals */ +\treg [`FWIDTH - 1 : 0] flags; +\treg [WIDTH - 1 : 0] alu_out; +\twire msb1, msb2, msb3; +\t +\t/* ALU output */ +\tassign flags_out = flags; +\tassign result = alu_out; +\t +\t/* internal wiring */ +\tassign msb1 = op1[WIDTH - 1]; +\tassign msb2 = op2[WIDTH - 1]; +\tassign msb3 = result[WIDTH - 1]; +\t +\t/* ALU multiplexer and behaviour */ +\talways @(*) begin +\t\tflags = {`FWIDTH{1\'b0}}; +\t\tcase(ctl) +\t\t\t3\'b000:\tbegin\t/* add: op1 + op2 */ +\t\t\t\t\t/* sum and carry */ +\t\t\t\t\t{flags[`CARRY_FLAG], alu_out} = op1 + op2; +\t\t\t\t\t/* overflow detect */ +\t\t\t\t\tflags[`OVERFLOW_FLAG] =\t((~msb1) & (~msb2) & msb3) +\t\t\t\t\t\t\t\t\t\t\t| (msb1 & msb2 & (~msb3)); +\t\t\t\t\t/* negative flag */ +\t\t\t\t\tflags[`NEGATIVE_FLAG] = msb3; +\t\t\t\tend +\t\t\t3\'b001:\tbegin\t/* add with carry: op1 + op2 + carry_in */ +\t\t\t\t\t/* sum and carry */ +\t\t\t\t\t{flags[`CARRY_FLAG], alu_out} = op1 + op2 + flags_in[`CARRY_FLAG]; +\t\t\t\t\t/* overflow detect */ +\t\t\t\t\tflags[`OVERFLOW_FLAG] =\t((~msb1) & (~msb2) & msb3) +\t\t\t\t\t\t\t\t\t\t\t| (msb1 & msb2 & (~msb3)); +\t\t\t\t\t/* negative flag */ +\t\t\t\t\tflags[`NEGATIVE_FLAG] = msb3; +\t\t\t\tend +\t\t\t3\'b010:\tbegin\t/* subtract: op2 - op1 */ +\t\t\t\t\t{flags[`CARRY_FLAG], alu_out} = op2 - op1; +\t\t\t\t\t/* overflow detect */ +\t\t\t\t\tflags[`OVERFLOW_FLAG] =\t((~msb1) & (~msb2) & msb3) +\t\t\t\t\t\t\t\t\t\t\t| (msb1 & msb2 & (~msb3)); +\t\t\t\t\t/* negative flag */ +\t\t\t\t\tflags[`NEGATIVE_FLAG] = msb3; +\t\t\t\tend +\t\t\t3\'b011:\tbegin\t/* subtract with carry */ +\t\t\t\t\t{flags[`CARRY_FLAG], alu_out} = op2 - op1 - flags_in[`CARRY_FLAG]; +\t\t\t\t\t/* overflow detect */ +\t\t\t\t\tflags[`OVERFLOW_FLAG] =\t((~msb1) & (~msb2) & msb3) +\t\t\t\t\t\t\t\t\t\t\t| (msb1 & msb2 & (~msb3)); +\t\t\t\t\t/* negative flag */ +\t\t\t\t\tflags[`NEGATIVE_FLAG] = msb3; +\t\t\t\tend +\t\t\t3\'b100:\tbegin\t/* nand */ +\t\t\t\t\talu_out = ~(op1 & op2); +\t\t\t\tend +\t\t\t3\'b101:\tbegin\t/* nor */ +\t\t\t\t\talu_out = ~(op1 | op2); +\t\t\t\tend +\t\t\t3\'b110:\tbegin\t/* xor */ +\t\t\t\t\talu_out = op1 ^ op2; +\t\t\t\tend +\t\t\t3\'b111:\tbegin\t/* shift right arithmetic */ +\t\t\t\t\talu_out = {op1[WIDTH - 1], op1[WIDTH - 1 : 1]}; +\t\t\t\t\tflags[`CARRY_FLAG] = op1[0]; +\t\t\t\tend +\t\t\tdefault: +\t\t\t\talu_out = {WIDTH{1\'b0}}; +\t\tendcase +\t\tflags[`ZERO_FLAG] = ~|alu_out; +\tend +\t +endmodule + +`include ""aluundefs.v"" +/* vim: set ts=4 tw=79 syntax=verilog */ +" +"/** + * decoder_complex_tb.v - Microcoded Accumulator CPU + * Copyright (C) 2015 Orlando Arias, David Mascenik + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +`timescale 1ns / 1ps + +module decoder_complex_tb; +\t/* inputs and control signals */ +\treg [7:0] opcode; +\treg clk; + +\t/* output signal */ +\twire [5:0] rom_offset; + +\t/* unit under testing */ +\tdecoder_complex uut ( +\t\t\t.opcode(opcode), +\t\t\t.rom_offset(rom_offset) +\t\t); + +\tinitial begin +\t\t/* signal initialization */ +\t\topcode = 0; +\t\tclk = 0; + +\t\t/* finish simulation */ +\t\t#1000\t$finish; +\tend +\t +\talways +\t\t#50\t\tclk = ~clk; + +\talways @(posedge clk) +\t\topcode = opcode + 1'b1; + +endmodule + +/* vim: set ts=4 tw=79 syntax=verilog */ +" +"/** + * datapath.v - Microcoded Accumulator CPU + * Copyright (C) 2015 Orlando Arias, David Mascenik + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +`timescale 1ns / 1ps + +`include ""aludefs.v"" + +module datapath( +\t\t/* regular inputs */ +\t\tinput wire\t\t[ 7 : 0]\t\timmediate,\t\t/* instruction predicate */ +\t\tinput wire\t\t[ 7 : 0]\t\tmdr_in,\t\t\t/* memory data register input */ +\t\t/* toplevel signals */ +\t\tinput wire\t\t\t\t\t\tclk,\t\t\t/* clock signal */ +\t\tinput wire\t\t\t\t\t\tres,\t\t\t/* reset signal */ +\t\t/* control signals */ +\t\tinput wire\t\t[ 1 : 0]\t\tac_source,\t\t/* accumulator source */ +\t\tinput wire\t\t\t\t\t\twrite_ac,\t\t/* write accumulator */ +\t\tinput wire\t\t\t\t\t\tmar_source,\t\t/* memory address register source */ +\t\tinput wire\t\t\t\t\t\twrite_mar,\t\t/* write memory address register */ +\t\tinput wire\t\t[ 1 : 0]\t\tmdr_source,\t\t/* memory data register source */ +\t\tinput wire\t\t\t\t\t\twrite_mdr,\t\t/* write memory data register */ +\t\tinput wire\t\t\t\t\t\twrite_flags,\t/* write flags register */ +\t\tinput wire\t\t[ 1 : 0]\t\tpc_source,\t\t/* program counter source */ +\t\tinput wire\t\t\t\t\t\twrite_pc,\t\t/* write program counter */ +\t\tinput wire\t\t[ 2 : 0]\t\tALU_op_select,\t/* ALU operand source */ +\t\tinput wire\t\t[`ALUCTLW - 1: 0]\tALUctl,\t\t/* ALU control signal bus */ +\t\t/* output signals */ +\t\toutput wire\t\t[ 7 : 0]\t\t\tmar_out,\t/* memory address */ +\t\toutput wire\t\t[ 7 : 0]\t\t\tmdr_out,\t/* data */ +\t\toutput wire\t\t[ 7 : 0]\t\t\tpc_out,\t\t/* program counter */ +\t\toutput wire\t\t[`FWIDTH - 1 : 0]\tflags\t\t/* ALU flags */ + ); +\t +\t/* internal signals */ +\twire [ 7 : 0] ALU_feedback,\t\t\t\t\t\t/* ALU output and feedback path */ +\t\t\tpc_next,\t\t\t\t\t\t\t\t/* next program counter */ +\t\t\tac_out,\t\t\t\t\t\t\t\t\t/* accumulator data output */ +\t\t\tac_in,\t\t\t\t\t\t\t\t\t/* accumulator data input */ +\t\t\talu_operand,\t\t\t\t\t\t\t/* second ALU operand */ +\t\t\tmar_data,\t\t\t\t\t\t\t\t/* memory address register data source */ +\t\t\tmdr_data;\t\t\t\t\t\t\t\t/* memory data register data source */ +\t +\twire [`FWIDTH - 1 : 0] flags_out;\t\t\t\t/* flags */ +\t +\t/* program counter jump select +\t * pc_source: +\t * 00: regular execution +\t * 01: direct jump +\t * 10: indirect jump +\t * 11: jump with offset +\t * rationale: +\t * mechanism allows for implementation of both direct jumps +\t * and indirect jumps. +\t */ +\tmux4 #(.WIDTH(8)) pc_mux ( +\t\t\t.in0(pc_out + 8\'b1), +\t\t\t.in1(immediate), +\t\t\t.in2(ac_out), +\t\t\t.in3(pc_out + ac_out), +\t\t\t.sel(pc_source), +\t\t\t.mux_out(pc_next) +\t\t); + +\t/* program counter register */ +\tff_d #(.WIDTH(8)) pc ( +\t\t\t.D(pc_next), +\t\t\t.en(write_pc), +\t\t\t.clk(clk), +\t\t\t.res(res), +\t\t\t.Q(pc_out) +\t\t); +\t +\t/* flags register +\t * rationale: +\t * keep ALU flags for new operations/CPU status +\t */ +\tff_d #(.WIDTH(`FWIDTH)) flags_register ( +\t\t\t.D(flags_out), +\t\t\t.en(write_flags), +\t\t\t.clk(clk), +\t\t\t.res(res), +\t\t\t.Q(flags) +\t\t); + +\t/* accumulator input select: +\t * ac_source: +\t * 00: store value in memory address register +\t * 01: store value in memory data register +\t * 10: store result from ALU into accumulator +\t * 11: store immediate into accumulator +\t * rationale: +\t * mechanism allows for accumulator behaviour and for loading +\t * a numeric constant into accumulator. +\t */ +\tmux4 #(.WIDTH(8)) ac_mux ( +\t\t\t.in0(mar_out), +\t\t\t.in1(mdr_out), +\t\t\t.in2(ALU_feedback), +\t\t\t.in3(immediate), +\t\t\t.sel(ac_source), +\t\t\t.mux_out(ac_in) +\t\t); +\t/* accumulator register */ +\tff_d #(.WIDTH(8)) ac ( +\t\t\t.D(ac_in), +\t\t\t.en(write_ac), +\t\t\t.clk(clk), +\t\t\t.res(res), +\t\t\t.Q(ac_out) +\t\t); +\t +\t/* memory address register data source select +\t * mar_source: +\t * 1: use source from immediate constant +\t * 0: use source from accumulator register +\t * rationale: +\t * allows for both direct and indirect addressing of memory data +\t */ +\tassign mar_data = mar_source ? immediate : ac_out; +\t +\t/* memory address register */ +\tff_d #(.WIDTH(8)) mar ( +\t\t\t.D(mar_data), +\t\t\t.en(write_mar), +\t\t\t.clk(clk), +\t\t\t.res(res), +\t\t\t.Q(mar_out) +\t\t); +\t +\t/* memory data register data source select +\t * mdr_source: +\t * 00: the constant 0 +\t * 01: memory bus value +\t *\t10: immediate value +\t * 11: accumulator register +\t * rationale: +\t * allows for both direct and indirect +\t * addressing of memory data +\t * allows to easily clear a memory address +\t */ +\tmux4 #(.WIDTH(8)) mdr_mux ( +\t\t\t.in0(8\'b0), +\t\t\t.in1(mdr_in), +\t\t\t.in2(immediate), +\t\t\t.in3(ac_out), +\t\t\t.sel(mdr_source), +\t\t\t.mux_out(mdr_data) +\t\t); +\t +\t/* memory data register */ +\tff_d #(.WIDTH(8)) mdr ( +\t\t\t.D(mdr_data), +\t\t\t.en(write_mdr), +\t\t\t.clk(clk), +\t\t\t.res(res), +\t\t\t.Q(mdr_out) +\t\t); +\t +\t/* ALU operand source select +\t * ALU_op_select: +\t * 000: the constant 0 +\t * 001: the constant 1 +\t * 010: the constant 2 +\t * 011: the constant -1 +\t * 100: the constant -2 +\t * 101: accumulator register +\t * 110: immediate constant +\t * 111: memory data register +\t * rationale: +\t * allows for the ease of implementation of +\t * arithmetic/logic instructions +\t */ +\tmux8 #(.WIDTH(8)) ALU_op_mux ( +\t\t\t.in0(8\'b0), +\t\t\t.in1(8\'b01), +\t\t\t.in2(8\'b10), +\t\t\t.in3(8\'hff), +\t\t\t.in4(8\'hfe), +\t\t\t.in5(ac_out), +\t\t\t.in6(immediate), +\t\t\t.in7(mdr_out), +\t\t\t.sel(ALU_op_select), +\t\t\t.mux_out(alu_operand) +\t\t); +\t +\t/* ALU */ +\tALU alu0 ( +\t\t\t.op1(ac_out), +\t\t\t.op2(alu_operand), +\t\t\t.ctl(ALUctl), +\t\t\t.flags_in(flags), +\t\t\t.result(ALU_feedback), +\t\t\t.flags_out(flags_out) +\t\t); +endmodule +`include ""aluundefs.v"" +/* vim: set ts=4 tw=79 syntax=verilog */ +" +"/** + * mux.v - Microcoded Accumulator CPU + * Copyright (C) 2015 Orlando Arias, David Mascenik + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +`timescale 1ns / 1ps + +module mux4 #(parameter WIDTH=8) ( +\t\tinput wire\t[WIDTH - 1 : 0]\t\tin0,\t\t/* multiplexer input 0 */ +\t\tinput wire\t[WIDTH - 1 : 0]\t\tin1,\t\t/* multiplexer input 1 */ +\t\tinput wire\t[WIDTH - 1 : 0]\t\tin2,\t\t/* multiplexer input 2 */ +\t\tinput wire\t[WIDTH - 1 : 0]\t\tin3,\t\t/* multiplexer input 3 */ +\t\tinput wire\t[ 1: 0]\t\t\t\tsel,\t\t/* select lines */ +\t\toutput reg\t[WIDTH - 1 : 0]\t\tmux_out\t\t/* multiplexer output */ +\t); +\t +\talways @(*) begin +\t\tcase(sel) +\t\t\t2'b00:\t\tmux_out = in0; +\t\t\t2'b01:\t\tmux_out = in1; +\t\t\t2'b10:\t\tmux_out = in2; +\t\t\t2'b11:\t\tmux_out = in3; +\t\tendcase +\tend +endmodule + +module mux8 #(parameter WIDTH=8) ( +\t\tinput wire\t[WIDTH - 1 : 0]\t\tin0,\t\t/* multiplexer input 0 */ +\t\tinput wire\t[WIDTH - 1 : 0]\t\tin1,\t\t/* multiplexer input 1 */ +\t\tinput wire\t[WIDTH - 1 : 0]\t\tin2,\t\t/* multiplexer input 2 */ +\t\tinput wire\t[WIDTH - 1 : 0]\t\tin3,\t\t/* multiplexer input 3 */ +\t\tinput wire\t[WIDTH - 1 : 0]\t\tin4,\t\t/* multiplexer input 4 */ +\t\tinput wire\t[WIDTH - 1 : 0]\t\tin5,\t\t/* multiplexer input 5 */ +\t\tinput wire\t[WIDTH - 1 : 0]\t\tin6,\t\t/* multiplexer input 6 */ +\t\tinput wire\t[WIDTH - 1 : 0]\t\tin7,\t\t/* multiplexer input 7 */ +\t\tinput wire\t[ 2: 0]\t\t\t\tsel,\t\t/* select lines */ +\t\toutput reg\t[WIDTH - 1 : 0]\t\tmux_out\t\t/* multiplexer output */ +\t); + +\talways @(*) begin +\t\tcase(sel) +\t\t\t3'b000:\t\tmux_out = in0; +\t\t\t3'b001:\t\tmux_out = in1; +\t\t\t3'b010:\t\tmux_out = in2; +\t\t\t3'b011:\t\tmux_out = in3; +\t\t\t3'b100:\t\tmux_out = in4; +\t\t\t3'b101:\t\tmux_out = in5; +\t\t\t3'b110:\t\tmux_out = in6; +\t\t\t3'b111:\t\tmux_out = in7; +\t\tendcase +\tend +endmodule +/* vim: set ts=4 tw=79 syntax=verilog */ +" +"/** + * aludefs.v - Microcoded Accumulator CPU + * Copyright (C) 2015 Orlando Arias, David Mascenik + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* flags register width */ +`define FWIDTH\t\t\t4 + +/* CPU flags */ +`define ZERO_FLAG\t\t0 +`define CARRY_FLAG\t\t1 +`define NEGATIVE_FLAG\t2 +`define OVERFLOW_FLAG\t3 + +/* ALU control bus width */ +`define ALUCTLW\t\t\t3 + +/* Microcode ROM offset width */ +`define MC_OFFSET_WIDTH\t6 +/* vim: set ts=4 tw=79 syntax=verilog */ +" +"/** + * pc_system.v - Microcoded Accumulator CPU + * Copyright (C) 2015 Orlando Arias, David Mascenik + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +`timescale 1ns / 1ps + +module pc_system( +\t\tinput wire\t\t[ 7 : 0]\tswitch_in, +\t\tinput wire\t\t\t\t\tbutton, +\t\tinput wire\t\t\t\t\tclk, +\t\tinput wire\t\t\t\t\tres, +\t\toutput wire \t[ 7 : 0]\tLED_status, +\t\toutput wire\t\t[ 3 : 0]\tanode, +\t\toutput wire\t\t[ 6 : 0]\tcathode + ); +\t +\t/* clock divider */ +\twire clk_div; +\t +\t/* processor signals */ +\twire [ 7 : 0] pc_out, mar_out, mdr_in, mdr_out; +\twire [15 : 0] instruction_in; + +\t/* direct board clock */ +\tassign clk_div = clk; +\t +\t/* clock divider */ +\t/*clock_divider clk_div0 ( +\t\t\t.clk(clk), +\t\t\t.res(res), +\t\t\t.prescaler(2'b10), +\t\t\t.clk_out(clk_div) +\t\t);*/ +\t +\t/* clock generator */ +\t/*clk_gen clk0( +\t\t\t.button(button), +\t\t\t.clk(clk), +\t\t\t.res(res), +\t\t\t.clk_div(clk_div) +\t\t); +\t*/ + +\t/* debug unit +\t * show instruction in 7-segment display +\t */ +\tinsn_out debug_unit0 ( +\t\t\t.insn(instruction_in), +\t\t\t.clk(clk), +\t\t\t.res(res), +\t\t\t.anode(anode), +\t\t\t.cathode(cathode) +\t\t); + +\t/* memory decoder unit */ +\tmemory_decoder md0 ( +\t\t\t.address(mar_out), +\t\t\t.data_in(mdr_out), +\t\t\t.switch_in(switch_in), +\t\t\t.clk(clk_div), +\t\t\t.res(res), +\t\t\t.write_enable(write_mem), +\t\t\t.LED_status(LED_status), +\t\t\t.data_out(mdr_in) +\t\t); +\t +\t/* the processor */ +\tprocessor core0 ( +\t\t\t.clk(clk_div), +\t\t\t.res(res), +\t\t\t.instruction_in(instruction_in), +\t\t\t.mdr_in(mdr_in), +\t\t\t.pc_out(pc_out), +\t\t\t.mdr_out(mdr_out), +\t\t\t.mar_out(mar_out), +\t\t\t.write_mem(write_mem) +\t\t); +\t +\t/* program memory subsystem */ +\tprogmem prom0 ( +\t\t\t.pc(pc_out), +\t\t\t.instruction(instruction_in) +\t\t); + +endmodule +/* vim: set ts=4 tw=79 syntax=verilog */ +" +"/** + * insn_out.v - Microcoded Accumulator CPU + * Copyright (C) 2015 Orlando Arias, David Mascenik + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +`timescale 1ns / 1ps + +/* instruction output driver */ +module insn_out( +\t\tinput wire\t\t[15 : 0]\tinsn, +\t\tinput wire\t\t\t\t\tclk, +\t\tinput wire\t\t\t\t\tres, +\t\toutput wire\t\t[ 3 : 0]\tanode, +\t\toutput wire\t\t[ 6 : 0]\tcathode +\t); + +\t/* internal frequency scaler parameter */ +\tparameter MSB = 16; +\t +\treg [MSB : 0] counter; +\treg [ 3 : 0] nibble; +\t +\t/* seven segment display driver instance */ +\tsseg_driver ssgd0 ( +\t\t\t.digit(nibble),\t\t\t\t\t/* digit to show */ +\t\t\t.sel(counter[MSB:MSB - 1]),\t\t/* digit selection */ +\t\t\t.anode(anode),\t\t\t\t\t/* decoded common anode enable */ +\t\t\t.cathode(cathode)\t\t\t\t/* decoded seven segment cathode */ +\t\t); +\t +\t/* internal counter */ +\talways @(posedge clk) begin +\t\tif(res) counter <= {(MSB+1){1'b0}}; +\t\telse counter <= counter + 1'b1; +\tend +\t +\t/* nibble multiplexing */ +\talways @(counter[MSB:MSB - 1] or insn) begin +\t\tcase(counter[MSB:MSB - 1]) +\t\t\t2'b00:\tnibble = insn[ 3 : 0]; +\t\t\t2'b01:\tnibble = insn[ 7 : 4]; +\t\t\t2'b10:\tnibble = insn[11 : 8]; +\t\t\t2'b11:\tnibble = insn[15 :12]; +\t\tendcase +\tend + +endmodule +/* vim: set ts=4 tw=79 syntax=verilog */ +" +"/** + * decoder_complex.v - Microcoded Accumulator CPU + * Copyright (C) 2015 Orlando Arias, David Mascenik + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +`timescale 1ns / 1ps + +`include ""aludefs.v"" + +module decoder_complex( +\t\tinput wire\t[ 7 : 0]\t\t\t\t\topcode,\t\t\t/* opcode */ +\t\tinput wire\t[`FWIDTH - 1 : 0]\t\t\tflags,\t\t\t/* ALU flags */ +\t\toutput reg\t[`MC_OFFSET_WIDTH - 1 : 0]\top_decoder_out\t/* microcode offset */ +\t); + +\talways @(*) begin +\t\tcase(opcode) +\t\t\t/* add from immediate memory address into accumulator */ +\t\t\t8\'h00:\top_decoder_out = `MC_OFFSET_WIDTH\'h0a; +\t\t\t/* store from accumulator into immediate address */ +\t\t\t8\'h01:\top_decoder_out = `MC_OFFSET_WIDTH\'h08; +\t\t\t/* load from immediate address into accumulator */ +\t\t\t8\'h02:\top_decoder_out = `MC_OFFSET_WIDTH\'h04; +\t\t\t/* absolute branch to immediate address */ +\t\t\t8\'h03:\top_decoder_out = `MC_OFFSET_WIDTH\'h0e; +\t\t\t/* jump if negative */ +\t\t\t8\'h04:\top_decoder_out = +\t\t\t\t\t\t\tflags[`NEGATIVE_FLAG] ? +\t\t\t\t\t\t\t\t`MC_OFFSET_WIDTH\'h0e +\t\t\t\t\t\t\t\t: `MC_OFFSET_WIDTH\'h0f; +\t\t\t/* subtract from immediate memory address into accumulator */ +\t\t\t8\'h05:\top_decoder_out = `MC_OFFSET_WIDTH\'h16; +\t\t\t/* exclusive OR from immediate memory address into accumulator */ +\t\t\t8\'h06:\top_decoder_out = `MC_OFFSET_WIDTH\'h1a; +\t\t\t/* NOR from immediate memory address into accumulator */ +\t\t\t8\'h07:\top_decoder_out = `MC_OFFSET_WIDTH\'h1e; +\t\t\t/* NAND from immediate memory address into accumulator */ +\t\t\t8\'h08:\top_decoder_out = `MC_OFFSET_WIDTH\'h22; +\t\t\t/* jump if positive */ +\t\t\t8\'h09:\top_decoder_out = +\t\t\t\t\t\t\tflags[`NEGATIVE_FLAG] ? +\t\t\t\t\t\t\t\t`MC_OFFSET_WIDTH\'h0f +\t\t\t\t\t\t\t\t: `MC_OFFSET_WIDTH\'h0e; +\t\t\t/* jump if zero */ +\t\t\t8\'h0a:\top_decoder_out = +\t\t\t\t\t\t\tflags[`ZERO_FLAG] ? +\t\t\t\t\t\t\t\t`MC_OFFSET_WIDTH\'h0e +\t\t\t\t\t\t\t\t: `MC_OFFSET_WIDTH\'h0f; +\t\t\t/* add immediate into accumulator */ +\t\t\t8\'h0b:\top_decoder_out = `MC_OFFSET_WIDTH\'h26; +\t\t\t/* accumulator arithmetic shift left */ +\t\t\t8\'h0d:\top_decoder_out = `MC_OFFSET_WIDTH\'h29; +\t\t\t/* accumulator arithmetic shift right */ +\t\t\t8\'h0e:\top_decoder_out = `MC_OFFSET_WIDTH\'h28; +\t\t\t/* jump if carry set */ +\t\t\t8\'h70:\top_decoder_out = +\t\t\t\t\t\t\tflags[`CARRY_FLAG] ? +\t\t\t\t\t\t\t\t`MC_OFFSET_WIDTH\'h0e +\t\t\t\t\t\t\t\t: `MC_OFFSET_WIDTH\'h0f; +\t\t\t/* jump if overflow set */ +\t\t\t8\'h71:\top_decoder_out = +\t\t\t\t\t\t\tflags[`OVERFLOW_FLAG] ? +\t\t\t\t\t\t\t\t`MC_OFFSET_WIDTH\'h0e +\t\t\t\t\t\t\t\t: `MC_OFFSET_WIDTH\'h0f; +\t\t\t/* increment accumulator */ +\t\t\t8\'h72:\top_decoder_out = `MC_OFFSET_WIDTH\'h10; +\t\t\t/* compare with immediate constant */ +\t\t\t8\'h73:\top_decoder_out = `MC_OFFSET_WIDTH\'h11; +\t\t\t/* compare with value at immediate address */ +\t\t\t8\'h74:\top_decoder_out = `MC_OFFSET_WIDTH\'h12; +\t\t\t/* invert accumulator */ +\t\t\t8\'h75:\top_decoder_out = `MC_OFFSET_WIDTH\'h27; +\t\t\t/* clear accumulator register */ +\t\t\t8\'h7e:\top_decoder_out = `MC_OFFSET_WIDTH\'h02; +\t\t\t/* load immediate into accumulator register */ +\t\t\t8\'h7f:\top_decoder_out = `MC_OFFSET_WIDTH\'h03; +\t\t\tdefault:op_decoder_out = {`MC_OFFSET_WIDTH{1\'b1}}; +\t\tendcase +\tend +endmodule + +`include ""aluundefs.v"" +/* vim: set ts=4 tw=79 syntax=verilog */ +" +"/** + * mcrom_tb.v - Microcoded Accumulator CPU + * Copyright (C) 2015 Orlando Arias, David Mascenik + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +`timescale 1ns / 1ps +`include ""microcodedefs.v"" + +module mcrom_tb; + +\t/* input and signals */ +\treg [ 5 : 0] offset; +\treg clk; + +\t/* output */ +\twire [`MCROM_WIDTH - 1 : 0] mc_word; + +\t/* unit under testing */ +\tmicrocode_rom uut ( +\t\t\t.offset(offset), +\t\t\t.mc_word(mc_word) +\t\t); + +\tinitial begin +\t\t/* initialize signals */ +\t\toffset = 0; +\t\tclk = 0; +\t\t/* end simulation after 1000 ticks */ +\t\t#1000\t$finish; +\tend + +\talways +\t\t#50\t\tclk = ~clk; +\t +\talways @(posedge clk) +\t\toffset = offset + 1; +\t\t +endmodule + +/* vim: set ts=4 tw=79 syntax=verilog */ +" +"/** + * controller_unit.v - Microcoded Accumulator CPU + * Copyright (C) 2015 Orlando Arias, David Mascenik + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +`timescale 1ns / 1ps + +`include ""microcodedefs.v"" +`include ""aludefs.v"" + +module controller_unit( +\t\t/* input signals */ +\t\tinput wire\t\t[ 7 : 0]\t\t\topcode,\t\t/* opcode byte */ +\t\tinput wire\t\t[`FWIDTH - 1 : 0]\tflags,\t\t/* ALU flags */ +\t\tinput wire\t\t\t\t\t\t\tclk,\t\t/* clock signal */ +\t\tinput wire\t\t\t\t\t\t\tres,\t\t/* reset signal */ +\t\t/* output signals */ +\t\toutput wire\t\t[1 : 0]\t\t\t\tac_source,\t/* accumulator source */ +\t\toutput wire\t\t\t\t\t\t\twrite_ac,\t/* write accumulator */ +\t\toutput wire\t\t\t\t\t\t\tmar_source,\t/* memory address register source */ +\t\toutput wire\t\t\t\t\t\t\twrite_mar,\t/* write memory address register */ +\t\toutput wire\t\t[1 : 0]\t\t\t\tmdr_source,\t/* memory data register source */ +\t\toutput wire\t\t\t\t\t\t\twrite_mdr,\t/* write memory data register */ +\t\toutput wire\t\t\t\t\t\t\twrite_flags,/* write flags register */ +\t\toutput wire\t\t[ 1 : 0]\t\t\tpc_source,\t/* program counter source */ +\t\toutput wire\t\t\t\t\t\t\twrite_pc,\t/* write program counter */ +\t\toutput wire\t\t\t\t\t\t\twrite_ir,\t/* write instruction register */ +\t\toutput wire\t\t\t\t\t\t\twrite_mem,\t/* write memory */ +\t\toutput wire\t\t[ 2 : 0]\t\t\tALU_op_select,\t/* ALU operator */ +\t\toutput wire\t\t[`ALUCTLW - 1: 0]\tALUctl\t\t/* ALU control signal bus */ + ); + +\t/* internal signals */ +\twire [`MCROM_WIDTH - 1 : 0] mc_word; +\twire [`OFFSET_WIDTH - 1 : 0] offset, rom_offset_next, op_decoder_out; +\twire [ 1 : 0] offset_next_select; + +\t +\t/* instance the decoder complex */ +\tdecoder_complex idec0 ( +\t\t\t.opcode(opcode), +\t\t\t.flags(flags), +\t\t\t.op_decoder_out(op_decoder_out) +\t\t); +\t +\t/* instance the microcode rom */ +\tmicrocode_rom rom0 ( +\t\t\t.clk(clk), +\t\t\t.offset(offset), +\t\t\t.mc_word(mc_word) +\t\t); +\t +\t/* select the next address in the microcode ROM */ +\tmux4 #(.WIDTH(`OFFSET_WIDTH)) mux0( +\t\t\t.in0(op_decoder_out),\t\t/* decoder complex output */ +\t\t\t.in1(rom_offset_next),\t\t/* offset from ROM */ +\t\t\t.in2(`OFFSET_WIDTH\'b0),\t\t/* start of ROM */ +\t\t\t.in3(`OFFSET_WIDTH\'b0),\t\t/* start of ROM */ +\t\t\t.sel(offset_next_select),\t/* next ROM address selection */ +\t\t\t.mux_out(offset)\t\t\t/* next offset on microcode ROM */ +\t\t); + +\t/* control signals assignment */ +\tassign offset_next_select \t= {res, res ? 1\'b1 : mc_word[`OFFSET_NEXT_SEL]}; +\tassign rom_offset_next\t\t= mc_word[`OFFSET_NEXT]; +\tassign ac_source \t\t\t= mc_word[`AC_SOURCE]; +\tassign write_ac \t\t\t= mc_word[`WRITE_AC]; +\tassign mar_source \t\t\t= mc_word[`MAR_SOURCE]; +\tassign write_mar \t\t\t= mc_word[`WRITE_MAR]; +\tassign mdr_source \t\t\t= mc_word[`MDR_SOURCE]; +\tassign write_mdr \t\t\t= mc_word[`WRITE_MDR]; +\tassign write_flags \t\t\t= mc_word[`WRITE_FLAGS]; +\tassign pc_source \t\t\t= mc_word[`PC_SOURCE]; +\tassign write_pc \t\t\t= mc_word[`WRITE_PC]; +\tassign write_ir\t\t\t\t= mc_word[`WRITE_IR]; +\tassign write_mem\t\t\t= mc_word[`WRITE_MEM]; +\tassign ALU_op_select \t\t= mc_word[`ALU_OP_SELECT]; +\tassign ALUctl \t\t\t\t= mc_word[`ALUCTL]; +endmodule + +`include ""microcodeundefs.v"" +`include ""aluundefs.v"" +/* vim: set ts=4 tw=79 syntax=verilog */ +" +"/** + * aluundefs.v - Microcoded Accumulator CPU + * Copyright (C) 2015 Orlando Arias, David Mascenik + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* undefines */ +`undef FWIDTH +`undef ZERO_FLAG +`undef CARRY_FLAG +`undef NEGATIVE_FLAG +`undef OVERFLOW_FLAG +`undef ALUCTLW +`undef MC_OFFSET_WIDTH/* vim: set ts=4 tw=79 syntax=verilog */ +" +"/** + * processor_tb.v - Microcoded Accumulator CPU + * Copyright (C) 2015 Orlando Arias, David Mascenik + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +`timescale 1ns / 1ps + +module processor_tb; + +\t/* inputs */ +\treg clk; +\treg res; +\treg [15:0] instruction_in; +\treg [7:0] mdr_in; +\t +\t/* SRAM block */ +\treg [7 : 0] memory [255 : 0]; + +\t/* outputs */ +\twire [7:0] pc_out; +\twire [7:0] mdr_out; +\twire [7:0] mar_out; +\twire write_mem; + +\t/* unit under testing */ +\tprocessor uut ( +\t\t\t.clk(clk), +\t\t\t.res(res), +\t\t\t.instruction_in(instruction_in), +\t\t\t.mdr_in(mdr_in), +\t\t\t.pc_out(pc_out), +\t\t\t.mdr_out(mdr_out), +\t\t\t.mar_out(mar_out), +\t\t\t.write_mem(write_mem) +\t\t); + +\tinitial begin +\t\t/* initialize inputs */ +\t\tclk = 0; +\t\tres = 1; + +\t\t/* release reset signal */ +\t\t#100\tres = 0; + +\t\t/* finish simulation */ +\tend +\t +\t/* clock */ +\talways +\t\t#10\t\tclk = ~clk; +\t +\t/* data memory subsystem emulation */ +\talways @(posedge clk) begin +\t\tif(write_mem) +\t\t\tmemory[mar_out] <= mdr_out; +\t\t\tmdr_in <= memory[mar_out]; +\tend + +\t/* ROM subsystem emulation */ +\talways @(pc_out) begin +\t\tcase(pc_out) +\t\t\t8'h00:\tinstruction_in = 16'h7f00;\t/* start:\tldi 0 */ +\t\t\t8'h01:\tinstruction_in = 16'h0100;\t/* \t\t\tsto 0x00 */ +\t\t\t8'h02:\tinstruction_in = 16'h0101;\t/* \t\t\tsto 0x01 */ +\t\t\t8'h03:\tinstruction_in = 16'h7200;\t/* loop:\tinc */ +\t\t\t8'h04:\tinstruction_in = 16'h730a;\t/* \t\t\tcmpi 0x0a */ +\t\t\t8'h05:\tinstruction_in = 16'h0aff;\t/* \t\t\tjz end */ +\t\t\t8'h06:\tinstruction_in = 16'h0101;\t/* \t\t\tsto 0x01 */ +\t\t\t8'h07:\tinstruction_in = 16'h0000;\t/* \t\t\tadd 0x00 */ +\t\t\t8'h08:\tinstruction_in = 16'h0100;\t/* \t\t\tsto 0x00 */ +\t\t\t8'h09:\tinstruction_in = 16'h0201;\t/* \t\t\tlo 0x01\t*/ +\t\t\t8'h0a:\tinstruction_in = 16'h0303;\t/* \t\t\tjmp loop */ +\t\t\tdefault: +\t\t\t\tbegin +\t\t\t\t\tinstruction_in = 16'hffff;\t/* end: \thalt */ +\t\t\t\t\t$finish; +\t\t\t\tend +\t\tendcase +\tend + +endmodule + +/* vim: set ts=4 tw=79 syntax=verilog */ +" +"/** + * progmem.v - Microcoded Accumulator CPU + * Copyright (C) 2015 Orlando Arias, David Mascenik + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +`timescale 1ns / 1ps + +/* program memory */ +module progmem( +\t\tinput wire\t\t[ 7 : 0]\tpc, +\t\toutput reg\t\t[15 : 0]\tinstruction + ); + +\t/* ROM subsystem emulation */ +\talways @(pc) begin +\t\tcase(pc) +\t\t\t8'h00:\tinstruction = 16'h7f00;\t/* start:\tldi 0 */ +\t\t\t8'h01:\tinstruction = 16'h0100;\t/* \t\t\tsto 0x00 */ +\t\t\t8'h02:\tinstruction = 16'h0101;\t/* \t\t\tsto 0x01 */ +\t\t\t8'h03:\tinstruction = 16'h7200;\t/* loop:\tinc */ +\t\t\t8'h04:\tinstruction = 16'h74ff;\t/* \t\t\tcmp 0xff */ +\t\t\t8'h05:\tinstruction = 16'h0a0c;\t/* \t\t\tjz loop_e */ +\t\t\t8'h06:\tinstruction = 16'h0101;\t/* \t\t\tsto 0x01 */ +\t\t\t8'h07:\tinstruction = 16'h0000;\t/* \t\t\tadd 0x00 */ +\t\t\t8'h08:\tinstruction = 16'h0100;\t/* \t\t\tsto 0x00 */ +\t\t\t8'h09:\tinstruction = 16'h01ff;\t/*\t\t\tsto 0xff */ +\t\t\t8'h0a:\tinstruction = 16'h0201;\t/* \t\t\tlo 0x01\t*/ +\t\t\t8'h0b:\tinstruction = 16'h0303;\t/* \t\t\tjmp loop */ +\t\t\t8'h0c:\tinstruction = 16'h030c;\t/* self:\tjmp self */ +\t\t\tdefault: +\t\t\t\tbegin +\t\t\t\t\tinstruction = 16'hffff;\t/* end: \thalt */ +\t\t\t\tend +\t\tendcase +\tend + +endmodule +/* vim: set ts=4 tw=79 syntax=verilog */ +" +"/** + * sram.v - Microcoded Accumulator CPU + * Copyright (C) 2015 Orlando Arias, David Mascenik + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +`timescale 1ns / 1ps + +/* Xilinx BRAM module creation */ +module sram( +\t\tinput wire\t\t[ 7 : 0]\taddress,\t\t/* address bus */ +\t\tinput wire\t\t[ 7 : 0]\tdata_in,\t\t/* data input bus */ +\t\tinput wire\t\t\t\t\tclk,\t\t\t/* clock */ +\t\tinput wire\t\t\t\t\twrite_enable,\t/* memory write enable */ +\t\toutput reg\t\t[ 7 : 0]\tdata_out\t\t/* data output bus */ + ); + +\t/* 255x8 SRAM block */ +\treg [ 7 : 0] memory [255 : 0]; +\t +\t/* Xilinx BRAM module generation */ +\talways @(posedge clk) begin +\t\tif(write_enable) +\t\t\tmemory[address] <= data_in; +\t\tdata_out <= memory[address]; +\tend + +endmodule +/* vim: set ts=4 tw=79 syntax=verilog */ +" +"/** + * sseg_driver.v - Microcoded Accumulator CPU + * Copyright (C) 2015 Orlando Arias, David Mascenik + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +`timescale 1ns / 1ps + +/* seven segment display driver */ +module sseg_driver( +\t\tinput wire\t\t[ 3 : 0]\tdigit,\t\t/* digit to show */ +\t\tinput wire\t\t[ 1 : 0]\tsel,\t\t/* place to show */ +\t\toutput reg\t\t[ 3 : 0]\tanode,\t\t/* common anode enable */ +\t\toutput reg\t\t[ 6 : 0]\tcathode\t\t/* cathode enable */ + ); + +\t/* decode anode enable signal */ +\talways @(sel) begin +\t\tcase(sel) +\t\t\t2'b00:\tanode = 4'b1110; +\t\t\t2'b01:\tanode = 4'b1101; +\t\t\t2'b10:\tanode = 4'b1011; +\t\t\t2'b11:\tanode = 4'b0111; +\t\tendcase +\tend +\t +\t/* decode digit into 7-segment driver output */ +\talways @(digit) begin +\t\tcase(digit)\t\t\t/* ABCDEFG */ +\t\t\t4'h0:\tcathode = 7'b0000001; +\t\t\t4'h1:\tcathode = 7'b1001111; +\t\t\t4'h2:\tcathode = 7'b0010010; +\t\t\t4'h3:\tcathode = 7'b0000110; +\t\t\t4'h4:\tcathode = 7'b1001100; +\t\t\t4'h5:\tcathode = 7'b0100100; +\t\t\t4'h6:\tcathode = 7'b0100000; +\t\t\t4'h7:\tcathode = 7'b0001111; +\t\t\t4'h8:\tcathode = 7'b0000000; +\t\t\t4'h9:\tcathode = 7'b0000100; +\t\t\t4'ha:\tcathode = 7'b0001000; +\t\t\t4'hb:\tcathode = 7'b1100000; +\t\t\t4'hc:\tcathode = 7'b0110001; +\t\t\t4'hd:\tcathode = 7'b1000010; +\t\t\t4'he:\tcathode = 7'b0110000; +\t\t\t4'hf:\tcathode = 7'b0111000; +\t\tendcase +\tend + +endmodule +/* vim: set ts=4 tw=79 syntax=verilog */ +" +"/** + * microcode_rom.v - Microcoded Accumulator CPU + * Copyright (C) 2015 Orlando Arias, David Mascenik + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +`timescale 1ns / 1ps +`include ""microcodedefs.v"" + +module microcode_rom( +\t\tinput wire\t\t\t\t\t\t\t\tclk,\t\t/* clock input */ +\t\tinput wire\t\t[`OFFSET_WIDTH - 1 : 0]\toffset,\t\t/* ROM address */ +\t\toutput reg\t\t[`MCROM_WIDTH - 1 : 0]\tmc_word\t\t/* ROM word output */ + ); + +\talways @(posedge clk) begin +\t\tcase(offset) +\t\t\t/* fetch */ +\t\t\t`OFFSET_WIDTH\'h00: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_000001_xxx_xxx_0_0_1_0_xx_0_xx_0_x_0_xx; +\t\t\t/* decode */ +\t\t\t`OFFSET_WIDTH\'h01: +\t\t\t\tmc_word = `MCROM_WIDTH\'b0_xxxxxx_xxx_xxx_0_0_0_0_xx_0_xx_0_x_0_xx; +\t\t\t/* clear accumulator register */ +\t\t\t`OFFSET_WIDTH\'h02: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_000000_110_101_0_1_0_1_00_0_xx_0_x_1_10; +\t\t\t/* load immediate into accumulator */ +\t\t\t`OFFSET_WIDTH\'h03: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_000000_xxx_xxx_0_0_0_1_00_0_xx_0_x_1_11; +\t\t\t/* load from immediate memory address into accumulator */ +\t\t\t`OFFSET_WIDTH\'h04: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_000101_xxx_xxx_0_0_0_0_xx_0_xx_1_1_0_xx; +\t\t\t`OFFSET_WIDTH\'h05: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_000110_xxx_xxx_0_0_0_0_xx_0_xx_0_x_0_xx; +\t\t\t`OFFSET_WIDTH\'h06: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_000111_xxx_xxx_0_0_0_0_xx_1_01_0_x_0_xx; +\t\t\t`OFFSET_WIDTH\'h07: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_000000_xxx_xxx_0_0_0_1_00_0_xx_0_x_1_01; +\t\t\t/* store from accumulator into immediate memory address */ +\t\t\t`OFFSET_WIDTH\'h08: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_001001_xxx_xxx_0_0_0_0_xx_1_11_1_1_0_xx; +\t\t\t`OFFSET_WIDTH\'h09: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_000000_xxx_xxx_1_0_0_1_00_0_xx_0_x_0_xx; +\t\t\t/* add from immediate memory address into accumulator */ +\t\t\t`OFFSET_WIDTH\'h0a: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_001011_xxx_xxx_0_0_0_0_xx_0_xx_1_1_0_xx; +\t\t\t`OFFSET_WIDTH\'h0b: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_001100_xxx_xxx_0_0_0_0_xx_0_xx_0_x_0_xx; +\t\t\t`OFFSET_WIDTH\'h0c: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_001101_xxx_xxx_0_0_0_0_xx_1_01_0_x_0_xx; +\t\t\t`OFFSET_WIDTH\'h0d: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_000000_000_111_0_1_0_1_00_0_xx_0_x_1_10; +\t\t\t/* absolute branch to immediate address or conditional branch taken */ +\t\t\t`OFFSET_WIDTH\'h0e: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_000000_xxx_xxx_0_0_0_1_01_0_xx_0_x_0_xx; +\t\t\t/* conditional branch not taken */ +\t\t\t`OFFSET_WIDTH\'h0f: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_000000_xxx_xxx_0_0_0_1_00_0_xx_0_x_0_xx; +\t\t\t/* increment accumulator */ +\t\t\t`OFFSET_WIDTH\'h10: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_000000_000_001_0_1_0_1_00_0_xx_0_x_1_10; +\t\t\t/* compare with immediate constant */ +\t\t\t`OFFSET_WIDTH\'h11: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_000000_010_110_0_1_0_1_00_0_xx_0_x_0_xx; +\t\t\t/* compare with value at immediate address */ +\t\t\t`OFFSET_WIDTH\'h12: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_010011_xxx_xxx_0_0_0_0_xx_0_xx_1_1_0_xx; +\t\t\t`OFFSET_WIDTH\'h13: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_010100_xxx_xxx_0_0_0_0_xx_0_xx_0_x_0_xx; +\t\t\t`OFFSET_WIDTH\'h14: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_010101_xxx_xxx_0_0_0_0_xx_1_01_0_x_0_xx; +\t\t\t`OFFSET_WIDTH\'h15: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_000000_010_111_0_1_0_1_00_0_xx_0_x_0_xx; +\t\t\t/* subtract from immediate memory address into accumulator */ +\t\t\t`OFFSET_WIDTH\'h16: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_010111_xxx_xxx_0_0_0_0_xx_0_xx_1_1_0_xx; +\t\t\t`OFFSET_WIDTH\'h17: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_011000_xxx_xxx_0_0_0_0_xx_0_xx_0_x_0_xx; +\t\t\t`OFFSET_WIDTH\'h18: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_011001_xxx_xxx_0_0_0_0_xx_1_01_0_x_0_xx; +\t\t\t`OFFSET_WIDTH\'h19: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_000000_010_111_0_1_0_1_00_0_xx_0_x_1_10; +\t\t\t/* exclusive OR from immediate memory address into accumulator */ +\t\t\t`OFFSET_WIDTH\'h1a: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_011011_xxx_xxx_0_0_0_0_xx_0_xx_1_1_0_xx; +\t\t\t`OFFSET_WIDTH\'h1b: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_011100_xxx_xxx_0_0_0_0_xx_0_xx_0_x_0_xx; +\t\t\t`OFFSET_WIDTH\'h1c: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_011101_xxx_xxx_0_0_0_0_xx_1_01_0_x_0_xx; +\t\t\t`OFFSET_WIDTH\'h1d: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_000000_110_111_0_1_0_1_00_0_xx_0_x_1_10; +\t\t\t/* NOR from immediate memory address into accumulator */ +\t\t\t`OFFSET_WIDTH\'h1e: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_011111_xxx_xxx_0_0_0_0_xx_0_xx_1_1_0_xx; +\t\t\t`OFFSET_WIDTH\'h1f: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_100000_xxx_xxx_0_0_0_0_xx_0_xx_0_x_0_xx; +\t\t\t`OFFSET_WIDTH\'h20: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_100001_xxx_xxx_0_0_0_0_xx_1_01_0_x_0_xx; +\t\t\t`OFFSET_WIDTH\'h21: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_000000_101_111_0_1_0_1_00_0_xx_0_x_1_10; +\t\t\t/* NAND from immediate memory address into accumulator */ +\t\t\t`OFFSET_WIDTH\'h22: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_100011_xxx_xxx_0_0_0_0_xx_0_xx_1_1_0_xx; +\t\t\t`OFFSET_WIDTH\'h23: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_100100_xxx_xxx_0_0_0_0_xx_0_xx_0_x_0_xx; +\t\t\t`OFFSET_WIDTH\'h24: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_100101_xxx_xxx_0_0_0_0_xx_1_01_0_x_0_xx; +\t\t\t`OFFSET_WIDTH\'h25: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_000000_100_111_0_1_0_1_00_0_xx_0_x_1_10; +\t\t\t/* add immediate into accumulator */ +\t\t\t`OFFSET_WIDTH\'h26: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_000000_000_110_0_1_0_1_00_0_xx_0_x_1_10; +\t\t\t/* invert accumulator */ +\t\t\t`OFFSET_WIDTH\'h27: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_000000_110_011_0_1_0_1_00_0_xx_0_x_1_10; +\t\t\t/* shift right arithmetic accumulator */ +\t\t\t`OFFSET_WIDTH\'h28: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_000000_111_101_0_1_0_1_00_0_xx_0_x_1_10; +\t\t\t/* shift left arithmetic accumulator */ +\t\t\t`OFFSET_WIDTH\'h29: +\t\t\t\tmc_word = `MCROM_WIDTH\'b1_000000_000_101_0_1_0_1_00_0_xx_0_x_1_10; +\t\t\t/* halt condition */ +\t\t\tdefault: +\t\t\t\tmc_word = {{(`OFFSET_WIDTH+1){1\'b1}}, +\t\t\t\t\t\t\t{(`MCROM_WIDTH - `OFFSET_WIDTH - 1){1\'b0}}}; +\t\tendcase +\tend +endmodule + +`include ""microcodeundefs.v"" +/* vim: set ts=4 tw=79 syntax=verilog */ +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2006 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer cyc; initial cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + reg \t out1; + reg [4:0] out2; + sub sub (.in(crc[23:0]), .out1(out1), .out2(out2)); + + always @ (posedge clk) begin + //$write(""[%0t] cyc==%0d crc=%x sum=%x out=%x,%x\ +"",$time, cyc, crc, sum, out1,out2); + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58\'h0,out1,out2}; + if (cyc==0) begin +\t // Setup +\t crc <= 64\'h00000000_00000097; +\t sum <= 64\'h0; + end + else if (cyc==90) begin +\t if (sum !== 64\'hf0afc2bfa78277c5) $stop; + end + else if (cyc==91) begin + end + else if (cyc==92) begin + end + else if (cyc==93) begin + end + else if (cyc==94) begin + end + else if (cyc==99) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end + +endmodule + +module sub (/*AUTOARG*/ + // Outputs + out1, out2, + // Inputs + in + ); + + input [23:0] in; + output reg \t out1; + output reg [4:0] out2; + + always @* begin + // Test empty cases + casez (in[0]) + endcase + casez (in) +\t24\'b0000_0000_0000_0000_0000_0000 : {out1,out2} = {1\'b0,5\'h00}; +\t24\'b????_????_????_????_????_???1 : {out1,out2} = {1\'b1,5\'h00}; +\t24\'b????_????_????_????_????_??10 : {out1,out2} = {1\'b1,5\'h01}; +\t24\'b????_????_????_????_????_?100 : {out1,out2} = {1\'b1,5\'h02}; +\t24\'b????_????_????_????_????_1000 : {out1,out2} = {1\'b1,5\'h03}; +\t24\'b????_????_????_????_???1_0000 : {out1,out2} = {1\'b1,5\'h04}; +\t24\'b????_????_????_????_??10_0000 : {out1,out2} = {1\'b1,5\'h05}; +\t24\'b????_????_????_????_?100_0000 : {out1,out2} = {1\'b1,5\'h06}; +\t24\'b????_????_????_????_1000_0000 : {out1,out2} = {1\'b1,5\'h07}; +\t// Same pattern, but reversed to test we work OK. +\t24\'b1000_0000_0000_0000_0000_0000 : {out1,out2} = {1\'b1,5\'h17}; +\t24\'b?100_0000_0000_0000_0000_0000 : {out1,out2} = {1\'b1,5\'h16}; +\t24\'b??10_0000_0000_0000_0000_0000 : {out1,out2} = {1\'b1,5\'h15}; +\t24\'b???1_0000_0000_0000_0000_0000 : {out1,out2} = {1\'b1,5\'h14}; +\t24\'b????_1000_0000_0000_0000_0000 : {out1,out2} = {1\'b1,5\'h13}; +\t24\'b????_?100_0000_0000_0000_0000 : {out1,out2} = {1\'b1,5\'h12}; +\t24\'b????_??10_0000_0000_0000_0000 : {out1,out2} = {1\'b1,5\'h11}; +\t24\'b????_???1_0000_0000_0000_0000 : {out1,out2} = {1\'b1,5\'h10}; +\t24\'b????_????_1000_0000_0000_0000 : {out1,out2} = {1\'b1,5\'h0f}; +\t24\'b????_????_?100_0000_0000_0000 : {out1,out2} = {1\'b1,5\'h0e}; +\t24\'b????_????_??10_0000_0000_0000 : {out1,out2} = {1\'b1,5\'h0d}; +\t24\'b????_????_???1_0000_0000_0000 : {out1,out2} = {1\'b1,5\'h0c}; +\t24\'b????_????_????_1000_0000_0000 : {out1,out2} = {1\'b1,5\'h0b}; +\t24\'b????_????_????_?100_0000_0000 : {out1,out2} = {1\'b1,5\'h0a}; +\t24\'b????_????_????_??10_0000_0000 : {out1,out2} = {1\'b1,5\'h09}; +\t24\'b????_????_????_???1_0000_0000 : {out1,out2} = {1\'b1,5\'h08}; + endcase + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +//bug505 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + parameter WIDTH = 33; + localparam MAX_WIDTH = 11; + localparam NUM_OUT = num_out(WIDTH); + + wire [NUM_OUT-1:0] z; + + function integer num_out; + input integer width; + num_out = 1; + while ((width + num_out - 1) / num_out > MAX_WIDTH) + num_out = num_out * 2; + endfunction + + initial begin + if (NUM_OUT != 4) $stop; + if ($bits(z) != 4) $stop; + $write(""*-* All Finished *-*\ +""); + $finish; + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2006 by Wilson Snyder. + +// Check that we report warnings only once on parameterized modules +// Also check that we don't suppress warnings on the same line + +module t (); + sub #(.A(1)) sub1(); + sub #(.A(2)) sub2(); + sub #(.A(3)) sub3(); +endmodule + +module sub; + parameter A = 0; + + reg [A:0] unus1; reg [A:0] unus2; +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +module t (/*AUTOARG*/); + + function integer max2; + input integer x; + input integer y; + begin +\t begin : blk +\t automatic int temp; +\t temp = x; +\t end + end + max2 = ( x > y ) ? x : y; + endfunction + + function integer max4; + input integer x; + input integer y; + input integer z; + input integer w; + // MAX2 is used multiple times + max4 = max2( max2( x, y ), max2( z, w ) ); + endfunction + + localparam MAX4 = max4( 1, 1, 0, 0 ); + + initial begin + if (MAX4 != 1) $stop; + $write(""*-* All Finished *-*\ +""); + $finish; + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // counters + int cnt; + int cnt_bit ; + int cnt_byte; + int cnt_int ; + int cnt_ar1d; + int cnt_ar2d; + + // sizes + int siz_bit ; + int siz_byte; + int siz_int ; + int siz_ar1d; + int siz_ar2d; + + // add all counters + assign cnt = cnt_bit + cnt_byte + cnt_int + cnt_ar1d + cnt_ar2d; + + // finish report + always @ (posedge clk) + if (cnt == 5) begin + if (siz_bit != 1) $stop(); + if (siz_byte != 8) $stop(); + if (siz_int != 32) $stop(); + if (siz_ar1d != 24) $stop(); + if (siz_ar2d != 16) $stop(); + end else if (cnt > 5) begin + $write(""*-* All Finished *-*\ +""); + $finish; + end + + // instances with various types + mod_typ #(.TYP (bit )) mod_bit (clk, cnt_bit [ 1-1:0], siz_bit ); + mod_typ #(.TYP (byte )) mod_byte (clk, cnt_byte[ 8-1:0], siz_byte); + mod_typ #(.TYP (int )) mod_int (clk, cnt_int [32-1:0], siz_int ); + mod_typ #(.TYP (bit [23:0] )) mod_ar1d (clk, cnt_ar1d[24-1:0], siz_ar1d); + mod_typ #(.TYP (bit [3:0][3:0])) mod_ar2d (clk, cnt_ar2d[16-1:0], siz_ar2d); + +endmodule : t + + +module mod_typ #( + parameter type TYP = byte +)( + input logic clk, + output TYP cnt = 0, + output int siz +); + + always @ (posedge clk) + cnt <= cnt + 1; + + assign siz = $bits (cnt); + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +// bug749 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + genvar g; + for (g=1; g<3; ++g) begin : gblk + sub2 #(.IN(g)) u (); + //sub #(.IN(g)) u2 (); + end + + sub1 #(.IN(0)) u (); + + always @ (posedge clk) begin + if (t.u.IN != 0) $stop; + if (t.u.FLAVOR != 1) $stop; + //if (t.u2.IN != 0) $stop; // This should be not found + if (t.gblk[1].u.IN != 1) $stop; + if (t.gblk[2].u.IN != 2) $stop; + if (t.gblk[1].u.FLAVOR != 2) $stop; + if (t.gblk[2].u.FLAVOR != 2) $stop; + $write(""*-* All Finished *-*\ +""); + $finish; + end +endmodule + +module sub1 (/*AUTOARG*/); + parameter [31:0] IN = 99; + parameter FLAVOR = 1; +`ifdef TEST_VERBOSE + initial $display(""%m""); +`endif +endmodule + +module sub2 (/*AUTOARG*/); + parameter [31:0] IN = 99; + parameter FLAVOR = 2; +`ifdef TEST_VERBOSE + initial $display(""%m""); +`endif +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module x; + + // verilator lint_off UNPACKED + typedef struct { + int \t a; + } notpacked_t; + // verilator lint_on UNPACKED + + typedef struct packed { + notpacked_t b; + } ispacked_t; + + ispacked_t p; + + initial begin + p.b = 1; + if (p.b != 1) $stop; + $write(""*-* All Finished *-*\ +""); + $finish; + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer \tcyc=0; + reg [63:0] \tcrc; + reg [63:0] \tsum; + + // Take CRC data and apply to testblock inputs + wire [1:0] in = crc[1:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [1:0]\t\tout;\t\t\t// From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ +\t // Outputs +\t .out\t\t\t(out[1:0]), +\t // Inputs +\t .in\t\t\t(in[1:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {62\'h0, out}; + + // What checksum will we end up with +`define EXPECTED_SUM 64\'hbb2d9709592f64bd + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write(""[%0t] cyc==%0d crc=%x result=%x\ +"",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin +\t // Setup +\t crc <= 64\'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin +\t sum <= 64\'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin +\t $write(""[%0t] cyc==%0d crc=%x sum=%x\ +"",$time, cyc, crc, sum); +\t if (crc !== 64\'hc77bb9b3784ea091) $stop; +\t if (sum !== `EXPECTED_SUM) $stop; +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, + // Inputs + in + ); + input [1:0] in; + output reg [1:0] out; + always @* begin + // bug99: Internal Error: ../V3Ast.cpp:495: New node already linked? + case (in[1:0]) +\t2\'d0, 2\'d1, 2\'d2, 2\'d3: begin +\t out = in; +\tend + endcase + end +endmodule + +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + logic oe; + + read r (.clk(clk), .data( ( ( oe == 1'd001 ) && implicit_write ) ) ); + set s (.clk(clk), .enable(implicit_write)); + read u (.clk(clk), .data(~implicit_also)); + +endmodule + +module set ( + input clk, + output enable + ); + assign enable = 1'b0; +endmodule + +module read ( + input clk, + input data + ); + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +interface pads_if(); + modport mp_dig( +\t\t import fIn, +\t\t import fOut ); + + integer exists[8]; + function automatic integer fIn (integer i); + fIn = exists[i]; + endfunction + task automatic fOut (integer i); + exists[i] = 33; + endtask +endinterface + +module t(); + pads_if padsif(); + initial begin + padsif.fOut(3); + if (padsif.fIn(3) != 33) $stop; + $write(""*-* All Finished *-*\ +""); + $finish; + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer \tcyc=0; + reg [63:0] \tcrc; + reg [63:0] \tsum; + + // Take CRC data and apply to testblock inputs + wire [7:0] operand_a = crc[7:0]; + wire [7:0] operand_b = crc[15:8]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [6:0]\t\tout;\t\t\t// From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ +\t // Outputs +\t .out\t\t\t(out[6:0]), +\t // Inputs +\t .clk\t\t\t(clk), +\t .operand_a\t\t(operand_a[7:0]), +\t .operand_b\t\t(operand_b[7:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {57\'h0, out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write(""[%0t] cyc==%0d crc=%x result=%x\ +"",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin +\t // Setup +\t crc <= 64\'h5aef0c8d_d70a4497; +\t sum <= 64\'h0; + end + else if (cyc<10) begin +\t sum <= 64\'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin +\t $write(""[%0t] cyc==%0d crc=%x sum=%x\ +"",$time, cyc, crc, sum); +\t if (crc !== 64\'hc77bb9b3784ea091) $stop; +\t // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64\'h8a78c2ec4946ac38 +\t if (sum !== `EXPECTED_SUM) $stop; +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end + +endmodule + +module Test + ( + // Inputs + input wire \t clk, + input wire [7:0] operand_a, // operand a + input wire [7:0] operand_b, // operand b +\t // Outputs + output wire [6:0] out + ); + + wire [6:0] \t clz_a; + wire [6:0] \t clz_b; + + clz u_clz_a + ( + // Inputs + .data_i (operand_a), + .out (clz_a)); + + clz u_clz_b + ( + // Inputs + .data_i (operand_b), + .out (clz_b)); + + assign out = clz_a - clz_b; +`ifdef TEST_VERBOSE + always @(posedge clk) + $display(""Out(%x) = clz_a(%x) - clz_b(%x)"", out, clz_a, clz_b); +`endif + +endmodule + +`define def_0000_001x 8\'b0000_0010, 8\'b0000_0011 + +`define def_0000_01xx 8\'b0000_0100, 8\'b0000_0101, 8\'b0000_0110, 8\'b0000_0111 + +`define def_0000_10xx 8\'b0000_1000, 8\'b0000_1001, 8\'b0000_1010, 8\'b0000_1011 +`define def_0000_11xx 8\'b0000_1100, 8\'b0000_1101, 8\'b0000_1110, 8\'b0000_1111 +`define def_0000_1xxx `def_0000_10xx, `def_0000_11xx + +`define def_0001_00xx 8\'b0001_0000, 8\'b0001_0001, 8\'b0001_0010, 8\'b0001_0011 +`define def_0001_01xx 8\'b0001_0100, 8\'b0001_0101, 8\'b0001_0110, 8\'b0001_0111 +`define def_0001_10xx 8\'b0001_1000, 8\'b0001_1001, 8\'b0001_1010, 8\'b0001_1011 +`define def_0001_11xx 8\'b0001_1100, 8\'b0001_1101, 8\'b0001_1110, 8\'b0001_1111 + +`define def_0010_00xx 8\'b0010_0000, 8\'b0010_0001, 8\'b0010_0010, 8\'b0010_0011 +`define def_0010_01xx 8\'b0010_0100, 8\'b0010_0101, 8\'b0010_0110, 8\'b0010_0111 +`define def_0010_10xx 8\'b0010_1000, 8\'b0010_1001, 8\'b0010_1010, 8\'b0010_1011 +`define def_0010_11xx 8\'b0010_1100, 8\'b0010_1101, 8\'b0010_1110, 8\'b0010_1111 + +`define def_0011_00xx 8\'b0011_0000, 8\'b0011_0001, 8\'b0011_0010, 8\'b0011_0011 +`define def_0011_01xx 8\'b0011_0100, 8\'b0011_0101, 8\'b0011_0110, 8\'b0011_0111 +`define def_0011_10xx 8\'b0011_1000, 8\'b0011_1001, 8\'b0011_1010, 8\'b0011_1011 +`define def_0011_11xx 8\'b0011_1100, 8\'b0011_1101, 8\'b0011_1110, 8\'b0011_1111 + +`define def_0100_00xx 8\'b0100_0000, 8\'b0100_0001, 8\'b0100_0010, 8\'b0100_0011 +`define def_0100_01xx 8\'b0100_0100, 8\'b0100_0101, 8\'b0100_0110, 8\'b0100_0111 +`define def_0100_10xx 8\'b0100_1000, 8\'b0100_1001, 8\'b0100_1010, 8\'b0100_1011 +`define def_0100_11xx 8\'b0100_1100, 8\'b0100_1101, 8\'b0100_1110, 8\'b0100_1111 + +`define def_0101_00xx 8\'b0101_0000, 8\'b0101_0001, 8\'b0101_0010, 8\'b0101_0011 +`define def_0101_01xx 8\'b0101_0100, 8\'b0101_0101, 8\'b0101_0110, 8\'b0101_0111 +`define def_0101_10xx 8\'b0101_1000, 8\'b0101_1001, 8\'b0101_1010, 8\'b0101_1011 +`define def_0101_11xx 8\'b0101_1100, 8\'b0101_1101, 8\'b0101_1110, 8\'b0101_1111 + +`define def_0110_00xx 8\'b0110_0000, 8\'b0110_0001, 8\'b0110_0010, 8\'b0110_0011 +`define def_0110_01xx 8\'b0110_0100, 8\'b0110_0101, 8\'b0110_0110, 8\'b0110_0111 +`define def_0110_10xx 8\'b0110_1000, 8\'b0110_1001, 8\'b0110_1010, 8\'b0110_1011 +`define def_0110_11xx 8\'b0110_1100, 8\'b0110_1101, 8\'b0110_1110, 8\'b0110_1111 + +`define def_0111_00xx 8\'b0111_0000, 8\'b0111_0001, 8\'b0111_0010, 8\'b0111_0011 +`define def_0111_01xx 8\'b0111_0100, 8\'b0111_0101, 8\'b0111_0110, 8\'b0111_0111 +`define def_0111_10xx 8\'b0111_1000, 8\'b0111_1001, 8\'b0111_1010, 8\'b0111_1011 +`define def_0111_11xx 8\'b0111_1100, 8\'b0111_1101, 8\'b0111_1110, 8\'b0111_1111 + +`define def_1000_00xx 8\'b1000_0000, 8\'b1000_0001, 8\'b1000_0010, 8\'b1000_0011 +`define def_1000_01xx 8\'b1000_0100, 8\'b1000_0101, 8\'b1000_0110, 8\'b1000_0111 +`define def_1000_10xx 8\'b1000_1000, 8\'b1000_1001, 8\'b1000_1010, 8\'b1000_1011 +`define def_1000_11xx 8\'b1000_1100, 8\'b1000_1101, 8\'b1000_1110, 8\'b1000_1111 + +`define def_1001_00xx 8\'b1001_0000, 8\'b1001_0001, 8\'b1001_0010, 8\'b1001_0011 +`define def_1001_01xx 8\'b1001_0100, 8\'b1001_0101, 8\'b1001_0110, 8\'b1001_0111 +`define def_1001_10xx 8\'b1001_1000, 8\'b1001_1001, 8\'b1001_1010, 8\'b1001_1011 +`define def_1001_11xx 8\'b1001_1100, 8\'b1001_1101, 8\'b1001_1110, 8\'b1001_1111 + +`define def_1010_00xx 8\'b1010_0000, 8\'b1010_0001, 8\'b1010_0010, 8\'b1010_0011 +`define def_1010_01xx 8\'b1010_0100, 8\'b1010_0101, 8\'b1010_0110, 8\'b1010_0111 +`define def_1010_10xx 8\'b1010_1000, 8\'b1010_1001, 8\'b1010_1010, 8\'b1010_1011 +`define def_1010_11xx 8\'b1010_1100, 8\'b1010_1101, 8\'b1010_1110, 8\'b1010_1111 + +`define def_1011_00xx 8\'b1011_0000, 8\'b1011_0001, 8\'b1011_0010, 8\'b1011_0011 +`define def_1011_01xx 8\'b1011_0100, 8\'b1011_0101, 8\'b1011_0110, 8\'b1011_0111 +`define def_1011_10xx 8\'b1011_1000, 8\'b1011_1001, 8\'b1011_1010, 8\'b1011_1011 +`define def_1011_11xx 8\'b1011_1100, 8\'b1011_1101, 8\'b1011_1110, 8\'b1011_1111 + +`define def_1100_00xx 8\'b1100_0000, 8\'b1100_0001, 8\'b1100_0010, 8\'b1100_0011 +`define def_1100_01xx 8\'b1100_0100, 8\'b1100_0101, 8\'b1100_0110, 8\'b1100_0111 +`define def_1100_10xx 8\'b1100_1000, 8\'b1100_1001, 8\'b1100_1010, 8\'b1100_1011 +`define def_1100_11xx 8\'b1100_1100, 8\'b1100_1101, 8\'b1100_1110, 8\'b1100_1111 + +`define def_1101_00xx 8\'b1101_0000, 8\'b1101_0001, 8\'b1101_0010, 8\'b1101_0011 +`define def_1101_01xx 8\'b1101_0100, 8\'b1101_0101, 8\'b1101_0110, 8\'b1101_0111 +`define def_1101_10xx 8\'b1101_1000, 8\'b1101_1001, 8\'b1101_1010, 8\'b1101_1011 +`define def_1101_11xx 8\'b1101_1100, 8\'b1101_1101, 8\'b1101_1110, 8\'b1101_1111 + +`define def_1110_00xx 8\'b1110_0000, 8\'b1110_0001, 8\'b1110_0010, 8\'b1110_0011 +`define def_1110_01xx 8\'b1110_0100, 8\'b1110_0101, 8\'b1110_0110, 8\'b1110_0111 +`define def_1110_10xx 8\'b1110_1000, 8\'b1110_1001, 8\'b1110_1010, 8\'b1110_1011 +`define def_1110_11xx 8\'b1110_1100, 8\'b1110_1101, 8\'b1110_1110, 8\'b1110_1111 + +`define def_1111_00xx 8\'b1111_0000, 8\'b1111_0001, 8\'b1111_0010, 8\'b1111_0011 +`define def_1111_01xx 8\'b1111_0100, 8\'b1111_0101, 8\'b1111_0110, 8\'b1111_0111 +`define def_1111_10xx 8\'b1111_1000, 8\'b1111_1001, 8\'b1111_1010, 8\'b1111_1011 +`define def_1111_11xx 8\'b1111_1100, 8\'b1111_1101, 8\'b1111_1110, 8\'b1111_1111 + +`define def_0001_xxxx `def_0001_00xx, `def_0001_01xx, `def_0001_10xx, `def_0001_11xx +`define def_0010_xxxx `def_0010_00xx, `def_0010_01xx, `def_0010_10xx, `def_0010_11xx +`define def_0011_xxxx `def_0011_00xx, `def_0011_01xx, `def_0011_10xx, `def_0011_11xx +`define def_0100_xxxx `def_0100_00xx, `def_0100_01xx, `def_0100_10xx, `def_0100_11xx +`define def_0101_xxxx `def_0101_00xx, `def_0101_01xx, `def_0101_10xx, `def_0101_11xx +`define def_0110_xxxx `def_0110_00xx, `def_0110_01xx, `def_0110_10xx, `def_0110_11xx +`define def_0111_xxxx `def_0111_00xx, `def_0111_01xx, `def_0111_10xx, `def_0111_11xx + +`define def_1000_xxxx `def_1000_00xx, `def_1000_01xx, `def_1000_10xx, `def_1000_11xx +`define def_1001_xxxx `def_1001_00xx, `def_1001_01xx, `def_1001_10xx, `def_1001_11xx +`define def_1010_xxxx `def_1010_00xx, `def_1010_01xx, `def_1010_10xx, `def_1010_11xx +`define def_1011_xxxx `def_1011_00xx, `def_1011_01xx, `def_1011_10xx, `def_1011_11xx +`define def_1100_xxxx `def_1100_00xx, `def_1100_01xx, `def_1100_10xx, `def_1100_11xx +`define def_1101_xxxx `def_1101_00xx, `def_1101_01xx, `def_1101_10xx, `def_1101_11xx +`define def_1110_xxxx `def_1110_00xx, `def_1110_01xx, `def_1110_10xx, `def_1110_11xx +`define def_1111_xxxx `def_1111_00xx, `def_1111_01xx, `def_1111_10xx, `def_1111_11xx + +`define def_1xxx_xxxx `def_1000_xxxx, `def_1001_xxxx, `def_1010_xxxx, `def_1011_xxxx, \\ + `def_1100_xxxx, `def_1101_xxxx, `def_1110_xxxx, `def_1111_xxxx +`define def_01xx_xxxx `def_0100_xxxx, `def_0101_xxxx, `def_0110_xxxx, `def_0111_xxxx +`define def_001x_xxxx `def_0010_xxxx, `def_0011_xxxx + + + +module clz( + input wire [7:0] data_i, + output wire [6:0] out +); + + // ----------------------------- + // Reg declarations + // ----------------------------- + + reg [2:0] clz_byte0; + reg [2:0] clz_byte1; + reg [2:0] clz_byte2; + reg [2:0] clz_byte3; + + always @* + case (data_i) + `def_1xxx_xxxx : clz_byte0 = 3\'b000; + `def_01xx_xxxx : clz_byte0 = 3\'b001; + `def_001x_xxxx : clz_byte0 = 3\'b010; + `def_0001_xxxx : clz_byte0 = 3\'b011; + `def_0000_1xxx : clz_byte0 = 3\'b100; + `def_0000_01xx : clz_byte0 = 3\'b101; + `def_0000_001x : clz_byte0 = 3\'b110; + 8\'b0000_0001 : clz_byte0 = 3\'b111; + 8\'b0000_0000 : clz_byte0 = 3\'b111; + default : clz_byte0 = 3\'bxxx; + endcase + + always @* + case (data_i) + `def_1xxx_xxxx : clz_byte1 = 3\'b000; + `def_01xx_xxxx : clz_byte1 = 3\'b001; + `def_001x_xxxx : clz_byte1 = 3\'b010; + `def_0001_xxxx : clz_byte1 = 3\'b011; + `def_0000_1xxx : clz_byte1 = 3\'b100; + `def_0000_01xx : clz_byte1 = 3\'b101; + `def_0000_001x : clz_byte1 = 3\'b110; + 8\'b0000_0001 : clz_byte1 = 3\'b111; + 8\'b0000_0000 : clz_byte1 = 3\'b111; + default : clz_byte1 = 3\'bxxx; + endcase + + always @* + case (data_i) + `def_1xxx_xxxx : clz_byte2 = 3\'b000; + `def_01xx_xxxx : clz_byte2 = 3\'b001; + `def_001x_xxxx : clz_byte2 = 3\'b010; + `def_0001_xxxx : clz_byte2 = 3\'b011; + `def_0000_1xxx : clz_byte2 = 3\'b100; + `def_0000_01xx : clz_byte2 = 3\'b101; + `def_0000_001x : clz_byte2 = 3\'b110; + 8\'b0000_0001 : clz_byte2 = 3\'b111; + 8\'b0000_0000 : clz_byte2 = 3\'b111; + default : clz_byte2 = 3\'bxxx; + endcase + always @* + case (data_i) + `def_1xxx_xxxx : clz_byte3 = 3\'b000; + `def_01xx_xxxx : clz_byte3 = 3\'b001; + `def_001x_xxxx : clz_byte3 = 3\'b010; + `def_0001_xxxx : clz_byte3 = 3\'b011; + `def_0000_1xxx : clz_byte3 = 3\'b100; + `def_0000_01xx : clz_byte3 = 3\'b101; + `def_0000_001x : clz_byte3 = 3\'b110; + 8\'b0000_0001 : clz_byte3 = 3\'b111; + 8\'b0000_0000 : clz_byte3 = 3\'b111; + default : clz_byte3 = 3\'bxxx; + endcase + + assign out = {4\'b0000, clz_byte1}; + +endmodule // clz + +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Jeremy Bennett. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + wire [19:10] bitout; + wire [29:24] short_bitout; + wire [7:0] \tallbits; + wire [15:0] \ttwobits; + + sub + i_sub1 [7:4] (.allbits (allbits), +\t\t .twobits (twobits[15:8]), +\t\t .bitout (bitout[17:14])), + i_sub2 [3:0] (.allbits (allbits), +\t\t .twobits (twobits[7:0]), +\t\t .bitout (bitout[13:10])); + + sub + i_sub3 [7:4] (.allbits (allbits), +\t\t .twobits (twobits[15:8]), +\t\t .bitout (bitout[17:14])); + + sub + i_sub4 [7:4] (.allbits (allbits), +\t\t .twobits (twobits[15:8]), +\t\t .bitout (short_bitout[27:24])); + + sub + i_sub5 [7:0] (.allbits (allbits), +\t\t .twobits (twobits), +\t\t .bitout (bitout[17:10])); + + sub + i_sub6 [7:4] (.allbits (allbits), +\t\t .twobits (twobits[15:8]), +\t\t .bitout ({bitout[18+:2],short_bitout[28+:2]})); + + integer \tcyc=0; + reg [63:0] \tcrc; + reg [63:0] \tsum; + + // Signals under test + assign allbits = crc[7:0]; + assign twobits = crc[15:0]; + wire [63:0] result = {48\'h0, short_bitout, bitout}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write(""[%0t] cyc==%0d crc=%x result=%x\ +"",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin +\t // Setup +\t crc <= 64\'h5aef0c8d_d70a4497; +\t sum <= 64\'h0; + end + else if (cyc<10) begin +\t sum <= 64\'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin +\t $write(""[%0t] cyc==%0d crc=%x sum=%x\ +"",$time, cyc, crc, sum); +\t if (crc !== 64\'hc77bb9b3784ea091) $stop; +\t // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64\'ha1da9ff8082a4ff6 +\t if (sum !== `EXPECTED_SUM) $stop; +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end + +endmodule // t + + +module sub + ( input wire [7:0] allbits, + input wire [1:0] twobits, + output wire bitout); + + assign bitout = (^ twobits) ^ (^ allbits); + +endmodule // sub +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t; + wire d1 = 1\'b1; + wire d2 = 1\'b1; + wire d3 = 1\'b1; + wire o1,o2,o3; + add1 add1 (d1,o1); + add2 add2 (d2,o2); + +`define ls left_side +`define rs right_side +`define noarg na//note extra space +`define thru(x) x +`define thruthru `ls `rs\t// Doesn\'t expand +`define msg(x,y) `""x: `\\`""y`\\`""`"" +`define left(m,left) m // The \'left\' as the variable name shouldn\'t match the ""left"" in the `"" string + initial begin + //$display(`msg( \\`, \\`)); // Illegal + $display(`msg(pre `thru(thrupre `thru(thrumid) thrupost) post,right side)); + $display(`msg(left side,right side)); + $display(`msg( left side , right side )); + $display(`msg( `ls , `rs )); + $display(`msg( `noarg , `rs )); + $display(`msg( prep ( midp1 `ls midp2 ( outp ) ) , `rs )); + $display(`msg(`noarg,`noarg`noarg)); + $display(`msg( `thruthru , `thruthru )); // Results vary between simulators + $display(`left(`msg( left side , right side ), left_replaced)); + //$display(`msg( `""tickquoted_left`"", `""tickquoted_right`"" )); // Syntax error +`ifndef VCS // Sim bug - wrong number of arguments, but we\'re right + $display(`msg(`thru(),)); // Empty +`endif + $display(`msg(`thru(left side),`thru(right side))); + $display(`msg( `thru( left side ) , `thru( right side ) )); +`ifndef NC + $display(`""standalone`""); +`endif + +`ifdef VERILATOR + // Illegal on some simulators, as the ""..."" crosses two lines +`define twoline first \\ + second + $display(`msg(twoline, `twoline)); +`endif + + $display(""Line %0d File \\""%s\\"""",`__LINE__,`__FILE__); + + //$display(`msg(left side, \\ right side \\ )); // Not sure \\{space} is legal. + $write(""*-* All Finished *-*\ +""); + $finish; + end +endmodule + +`define ADD_UP(a,c) \\ +wire tmp_``a = a; \\ +wire tmp_``c = tmp_``a + 1; \\ +assign c = tmp_``c ; + +module add1 ( input wire d1, output wire o1); + `ADD_UP(d1,o1) // expansion is OK +endmodule +module add2 ( input wire d2, output wire o2); + `ADD_UP( d2 , o2 ) // expansion is bad +endmodule +// `ADD_UP( \\d3 , \\o3 ) // This really is illegal +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +module t_embed1_wrap (/*AUTOARG*/ + // Outputs + bit_out, vec_out, wide_out, did_init_out, + // Inputs + clk, bit_in, vec_in, wide_in, is_ref + ); + + /*AUTOINOUTMODULE(""t_embed1_child"")*/ + // Beginning of automatic in/out/inouts (from specific module) + output\t\tbit_out; + output [30:0]\tvec_out; + output [123:0]\twide_out; + output\t\tdid_init_out; + input\t\tclk; + input\t\tbit_in; + input [30:0]\t\tvec_in; + input [123:0]\twide_in; + input\t\tis_ref; + // End of automatics + +`ifdef verilator + // Import $t_embed_child__initial etc as a DPI function +`endif + + //TODO would like __\'s as in {PREFIX}__initial but presently illegal for users to do this + import ""DPI-C"" context function void t_embed_child_initial(); + import ""DPI-C"" context function void t_embed_child_final(); + import ""DPI-C"" context function void t_embed_child_eval(); + import ""DPI-C"" context function void t_embed_child_io_eval + ( + //TODO we support bit, but not logic + input bit clk, + input bit bit_in, + input bit [30:0] vec_in, + input bit [123:0] wide_in, + input bit is_ref, + output bit bit_out, + output bit [30:0] vec_out, + output bit [123:0] wide_out, + output bit did_init_out); + + initial begin + // Load all values + t_embed_child_initial(); + end + + // Only if system verilog, and if a ""final"" block in the code + final begin + t_embed_child_final(); + end + + bit _temp_bit_out; + bit _temp_did_init_out; + bit [30:0] _temp_vec_out; + bit [123:0] _temp_wide_out; + always @* begin + t_embed_child_io_eval( +\t\t\t clk, +\t\t\t bit_in, +\t\t\t vec_in, +\t\t\t wide_in, +\t\t\t is_ref, +\t\t\t _temp_bit_out, +\t\t\t _temp_vec_out, +\t\t\t _temp_wide_out, +\t\t\t _temp_did_init_out +\t\t\t ); + // TODO might eliminate these temporaries + bit_out = _temp_bit_out; + did_init_out = _temp_did_init_out; + end + + + // Send all variables every cycle, + // or have a sensitivity routine for each? + // How to make sure we call eval at end of variable changes? + // #0 (though not verilator compatible!) + + // TODO for now, we know what changes when + always @ (posedge clk) begin + vec_out <= _temp_vec_out; + wide_out <= _temp_wide_out; + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +`timescale 1 ns/ 1ns + +module top (/*AUTOARG*/ + // Outputs + passed, out_small, out_quad, out_wide, + // Inputs + clk, fastclk, reset_l, in_small, in_quad, in_wide + ); + + output passed; + input clk; + input fastclk; + input reset_l; + + output [1:0] out_small; + output [39:0] out_quad; + output [69:0] out_wide; + input [1:0] \t in_small; + input [39:0] in_quad; + input [69:0] in_wide; + + wire [1:0] \t out_small = in_small | {2{reset_l}}; + wire [39:0] \t out_quad = in_quad | {40{reset_l}}; + wire [69:0] \t out_wide = in_wide | {70{reset_l}}; + + initial begin + $write(""Hello World!\ +""); + end + + // Example sub module + t t (/*AUTOINST*/ +\t// Outputs +\t.passed\t\t\t\t(passed), +\t// Inputs +\t.clk\t\t\t\t(clk), +\t.fastclk\t\t\t(fastclk), +\t.reset_l\t\t\t(reset_l)); + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + out, + // Inputs + in + ); + + input in; // inputs don\'t get flagged as undriven + output out; // outputs don\'t get flagged as unused + + sub sub (); + + // Check we don\'t warn about unused UDP signals + udp_mux2 udpsub (out, in, in, in); + + // Check ignoreds mark as used + reg \t sysused; + initial $bboxed(sysused); + + // Check file IO. The fopen is the ""driver"" all else a usage. + integer infile; + integer outfile; + initial begin + outfile = $fopen(""obj_dir/t_lint_unused_bad/open.log"", ""w""); + $fwrite(outfile, ""1\ +""); + $fclose(outfile); + infile = $fopen(""obj_dir/t_lint_unused_bad/open.log"", ""r""); + if ($fgetc(infile) != ""1"") begin end + end + + wire _unused_ok; + +endmodule + +module sub; + + wire pub /*verilator public*/; // Ignore publics + + localparam THREE = 3; + +endmodule + +primitive udp_mux2 (q, a, b, s); + output q; + input a, b, s; + table + //a b s : out + 1 ? 0 : 1 ; + 0 ? 0 : 0 ; + ? 1 1 : 1 ; + ? 0 1 : 0 ; + 0 0 x : 0 ; + 1 1 x : 1 ; + endtable +endprimitive +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005-2007 by Wilson Snyder. + +module t (/*AUTOARG*/); + + reg [3:0] value; + reg [3:0] valuex; + + // verilator lint_off CASEOVERLAP + // verilator lint_off CASEWITHX + // verilator lint_off CASEX + + // Note for Verilator Xs must become zeros, or the Xs may match. + + initial begin + value = 4\'b1001; + valuex = 4\'b1xxx; + case (value) +\t4\'b1xxx: $stop; +\t4\'b1???: $stop; +\t4\'b1001: ; +\tdefault: $stop; + endcase + case (valuex) +\t4\'b1???: $stop; +\t4\'b1xxx: ; +\t4\'b1001: ; +\t4\'b1000: ; // 1xxx is mapped to this by Verilator -x-assign 0 +\tdefault: $stop; + endcase + // + casex (value) +\t4\'b100x: ; +\tdefault: $stop; + endcase + casex (value) +\t4\'b100?: ; +\tdefault: $stop; + endcase + casex (valuex) +\t4\'b100x: ; +\tdefault: $stop; + endcase + casex (valuex) +\t4\'b100?: ; +\tdefault: $stop; + endcase + // + casez (value) +\t4\'bxxxx: $stop; +\t4\'b100?: ; +\tdefault: $stop; + endcase + casez (valuex) +\t4\'b1xx?: ; +\t4\'b100?: ; // 1xxx is mapped to this by Verilator -x-assign 0 +\tdefault: $stop; + endcase + $write(""*-* All Finished *-*\ +""); + $finish; + end + +endmodule +" +"// DESCRIPTION: Verilator: Unsupported tristate constructur error +// +// This is a compile only regression test of tristate handling for bug514 +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Jeremy Bennett. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + wire [11:0] ck; + + assign ck[1:0] = {1'bz,{1{1'b0}}}; + + test i_test (.clk (ck[1:0])); + +endmodule + + +module test (clk); + + output wire [1:0] clk; + +endmodule // test +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (clk); + input clk; + + reg [0:0] d1; + reg [2:0] d3; + reg [7:0] d8; + + wire [0:0] q1; + wire [2:0] q3; + wire [7:0] q8; + + // verilator lint_off UNOPTFLAT + reg \t ena; + // verilator lint_on UNOPTFLAT + + condff #(12) condff + (.clk(clk), .sen(1\'b0), .ena(ena), + .d({d8,d3,d1}), + .q({q8,q3,q1})); + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin +\t //$write(""%x %x %x %x\ +"", cyc, q8, q3, q1); +\t cyc <= cyc + 1; +\t if (cyc==1) begin +\t d1 <= 1\'b1; d3<=3\'h1; d8<=8\'h11; +\t ena <= 1\'b1; +\t end +\t if (cyc==2) begin +\t d1 <= 1\'b0; d3<=3\'h2; d8<=8\'h33; +\t ena <= 1\'b0; +\t end +\t if (cyc==3) begin +\t d1 <= 1\'b1; d3<=3\'h3; d8<=8\'h44; +\t ena <= 1\'b1; +\t if (q8 != 8\'h11) $stop; +\t end +\t if (cyc==4) begin +\t d1 <= 1\'b1; d3<=3\'h4; d8<=8\'h77; +\t ena <= 1\'b1; +\t if (q8 != 8\'h11) $stop; +\t end +\t if (cyc==5) begin +\t d1 <= 1\'b1; d3<=3\'h0; d8<=8\'h88; +\t ena <= 1\'b1; +\t if (q8 != 8\'h44) $stop; +\t end +\t if (cyc==6) begin +\t if (q8 != 8\'h77) $stop; +\t end +\t if (cyc==7) begin +\t if (q8 != 8\'h88) $stop; +\t end +\t // +\t if (cyc==20) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; +\t end + end + end +endmodule + +module condff (clk, sen, ena, d, q); + parameter WIDTH = 1; + input clk; + + input sen; + input ena; + input [WIDTH-1:0] d; + output [WIDTH-1:0] q; + + condffimp #(.WIDTH(WIDTH)) + imp (.clk(clk), .sen(sen), .ena(ena), .d(d), .q(q)); +endmodule + +module condffimp (clk, sen, ena, d, q); + parameter WIDTH = 1; + input clk; + input sen; + input ena; + input [WIDTH-1:0] d; + output reg [WIDTH-1:0] q; + wire gatedclk; + + clockgate clockgate (.clk(clk), .sen(sen), .ena(ena), .gatedclk(gatedclk)); + + always @(posedge gatedclk) begin + if (gatedclk === 1\'bX) begin +\t q <= {WIDTH{1\'bX}}; + end + else begin +\t q <= d; + end + end + +endmodule + +module clockgate (clk, sen, ena, gatedclk); + input\tclk; + input\tsen; + input\tena; + output\tgatedclk; + + reg\t\tena_b; + wire gatedclk = clk & ena_b; + + // verilator lint_off COMBDLY + always @(clk or ena or sen) begin + if (~clk) begin + ena_b <= ena | sen; + end + else begin +\t if ((clk^sen)===1\'bX) ena_b <= 1\'bX; + end + end + // verilator lint_on COMBDLY + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t; + real n0; initial n0 = 0.0; + real n1; initial n1 = 1.0; + real n2; initial n2 = 0.1; + real n3; initial n3 = 1.2345e-15; + real n4; initial n4 = 2.579e+15; + reg [7:0] r8; initial r8 = 3; + + initial begin + // Display formatting + $display(""[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e"", $time, n0,n0,n0,n0); + $display(""[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e"", $time, n0,n0,n0,n0); + $display(""[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e"", $time, n0,n0,n0,n0); + $display; + $display(""[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e"", $time, n1,n1,n1,n1); + $display(""[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e"", $time, n1,n1,n1,n1); + $display(""[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e"", $time, n1,n1,n1,n1); + $display; + $display(""[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e"", $time, n2,n2,n2,n2); + $display(""[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e"", $time, n2,n2,n2,n2); + $display(""[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e"", $time, n2,n2,n2,n2); + $display; + $display(""[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e"", $time, n3,n3,n3,n3); + $display(""[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e"", $time, n3,n3,n3,n3); + $display(""[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e"", $time, n3,n3,n3,n3); + $display; + $display(""[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e"", $time, n4,n4,n4,n4); + $display(""[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e"", $time, n4,n4,n4,n4); + $display(""[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e"", $time, n4,n4,n4,n4); + $display; + $display(""r8=%d n1=%g n2=%g"", r8, n1, n2); + $display(""n1=%g n2=%g r8=%d"", n1, n2, r8); + $write(""*-* All Finished *-*\ +""); + $finish; + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + reg [31:0] in_a; + reg [31:0] in_b; + + reg [31:0] e,f,g,h; + + always @ (/*AS*/in_a) begin + e = in_a; + f = {e[15:0], e[31:16]}; + g = {f[15:0], f[31:16]}; + h = {g[15:0], g[31:16]}; + end + + // verilator lint_off UNOPTFLAT + reg [31:0] e2,f2,g2,h2; + always @ (/*AS*/f2) begin + h2 = {g2[15:0], g2[31:16]}; + g2 = {f2[15:0], f2[31:16]}; + end + always @ (/*AS*/in_a) begin + f2 = {e2[15:0], e2[31:16]}; + e2 = in_a; + end + // verilator lint_on UNOPTFLAT + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin +\t cyc <= cyc + 1; +\t //$write(""%d %x %x\ +"", cyc, h, h2); +\t if (h != h2) $stop; +\t if (cyc==1) begin +\t in_a <= 32\'h89a14fab; +\t in_b <= 32\'h7ab512fa; +\t end +\t if (cyc==2) begin +\t in_a <= 32\'hf4c11a42; +\t in_b <= 32\'h359967c6; +\t if (h != 32\'h4fab89a1) $stop; +\t end +\t if (cyc==3) begin +\t if (h != 32\'h1a42f4c1) $stop; +\t end +\t if (cyc==9) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; +\t end + end + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2009 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +module t (); + + // Same name w/ different args + import ""DPI-C"" dpii_fa_bit = function int oth_f_int1(input int i); + import ""DPI-C"" pure dpii_fa_bit = function int oth_f_int2(input int i, input int bad); + + initial begin + $stop; + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +// Also check that SystemC is ordering properly +// verilator lint_on IMPERFECTSCH + +module t (/*AUTOARG*/ + // Outputs + o1, o8, o16, o32, o64, o65, o128, o513, o1a2, o94a3, obv1, obv16, + // Inputs + clk, i1, i8, i16, i32, i64, i65, i128, i513, i1a2, i94a3, ibv1, ibv16 + ); + + input clk; + + input \t i1; + input [7:0]\t i8; + input [15:0]\t i16; + input [31:0]\t i32; + input [63:0]\t i64; + input [64:0]\t i65; + input [127:0] i128; + input [512:0] i513; + input \t i1a2 [1:0]; + input [93:0] i94a3 [2:0]; + + + output \t o1; + output [7:0] o8; + output [15:0] o16; + output [31:0] o32; + output [63:0] o64; + output [64:0] o65; + output [127:0] o128; + output [512:0] o513; + output\t o1a2 [1:0]; + output [93:0] o94a3 [2:0]; + + input [0:0] \t ibv1 /*verilator sc_bv*/; + input [15:0] ibv16 /*verilator sc_bv*/; + + output [0:0] obv1 /*verilator sc_bv*/; + output [15:0] obv16 /*verilator sc_bv*/; + + always @ (posedge clk) begin + o1 <= i1; + o8 <= i8; + o16 <= i16; + o32 <= i32; + o64 <= i64; + o65 <= i65; + o128 <= i128; + o513 <= i513; + obv1 <= ibv1; + obv16 <= ibv16; + o1a2 <= i1a2; + o94a3 <= i94a3; + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer \tcyc=0; + reg [63:0] \tcrc; + reg [63:0] \tsum; + + wire [4:0] in = crc[4:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic\t\tout;\t\t\t// From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ +\t // Outputs +\t .out\t\t\t(out), +\t // Inputs +\t .clk\t\t\t(clk), +\t .in\t\t\t(in[4:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {63\'h0, out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write(""[%0t] cyc==%0d crc=%x result=%x\ +"",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin +\t // Setup +\t crc <= 64\'h5aef0c8d_d70a4497; +\t sum <= 64\'h0; + end + else if (cyc<10) begin +\t sum <= 64\'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin +\t $write(""[%0t] cyc==%0d crc=%x sum=%x\ +"",$time, cyc, crc, sum); +\t if (crc !== 64\'hc77bb9b3784ea091) $stop; +\t // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64\'h7a7bd4ee927e7cc3 +\t if (sum !== `EXPECTED_SUM) $stop; +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, + // Inputs + clk, in + ); + + //bug718 + + input clk; + + input logic [4:0] in; + + output logic out; + + always @(posedge clk) begin + out <= in inside {5\'b1_1?1?}; + end + +endmodule // t" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + outc_w30, outd_w73, + // Inputs + clk, ina_w1, inb_w61 + ); + + input clk; + + input ina_w1; + input [60:0] inb_w61; + output [29:0] outc_w30; + output [72:0] outd_w73; + + sub sub ( +\t // Outputs +\t .outy_w92\t(outc_w30),\t// .large => (small) +\t .outz_w22\t(outd_w73),\t// .small => (large) +\t // Inputs +\t .clk\t(clk), +\t .inw_w31\t(ina_w1),\t// .large <= (small) +\t .inx_w11\t(inb_w61)\t// .small <= (large) +\t ); + +endmodule + +module sub (/*AUTOARG*/ + // Outputs + outy_w92, outz_w22, + // Inputs + clk, inw_w31, inx_w11 + ); + + input \tclk; + input [30:0]\tinw_w31; + input [10:0]\tinx_w11; + output reg [91:0] outy_w92 /*verilator public*/; + output reg [21:0] outz_w22 /*verilator public*/; + + always @(posedge clk) begin + outy_w92 <= {inw_w31[29:0],inw_w31[29:0],inw_w31[29:0],2'b00}; + outz_w22 <= {inx_w11[10:0],inx_w11[10:0]}; + end + +endmodule // regfile +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc = 0; + + logic [1:0][27:0] ch01; + logic [1:0][27:0] ch02; + logic [1:0][27:0] ch03; + logic [27:0] ch04[1:0]; + + /* verilator lint_off WIDTH */ + always @ (posedge clk) begin + // LHS is a 2D packed array, RHS is 1D packed or Const. Allowed now. + ch01 <= {{2{28\'d4}}}; + ch02 <= {{2{cyc}}}; + ch03 <= 56\'d0; + // LHS is 1D packed, 1D unpacked, this should never work. + ch04 <= 56\'d0; + $display(""ch01: %0x %0x"", ch01[0], ch01[1]); + $display(""ch01: %0x %0x"", ch02[0], ch02[1]); + $display(""ch01: %0x %0x"", ch03[0], ch03[1]); + $display(""ch01: %0x %0x"", ch04[0], ch04[1]); + end + /* verilator lint_on WIDTH */ + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003-2007 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + reg [7:0] cyc; initial cyc=0; + + reg [31:0] in; + wire [31:0] out; + t_extend_class_v sub (.in(in), .out(out)); + + always @ (posedge clk) begin + cyc <= cyc+8\'d1; + if (cyc == 8\'d1) begin +\t in <= 32\'h10; + end + if (cyc == 8\'d2) begin +\t if (out != 32\'h11) $stop; + end + if (cyc == 8\'d9) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end +endmodule + +module t_extend_class_v (/*AUTOARG*/ + // Outputs + out, + // Inputs + in + ); + + input [31:0] in; + output [31:0] out; + + always @* begin + // When ""in"" changes, call my method + out = $c(""m_myobjp->my_math("",in,"")""); + end + + `systemc_header +#include ""t_extend_class_c.h""\t// Header for contained object + `systemc_interface + t_extend_class_c* m_myobjp;\t// Pointer to object we are embedding + `systemc_ctor + m_myobjp = new t_extend_class_c();\t// Construct contained object + `systemc_dtor + delete m_myobjp;\t// Destruct contained object + `verilog + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t(/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + reg \t _ranit; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [4:0]\t\tpar1;\t\t\t// From a1 of t_param_first_a.v + wire [4:0]\t\tpar2;\t\t\t// From a2 of t_param_first_a.v + wire [4:0]\t\tpar3;\t\t\t// From a3 of t_param_first_a.v + wire [4:0]\t\tpar4;\t\t\t// From a4 of t_param_first_a.v + wire [1:0]\t\tvarwidth1;\t\t// From a1 of t_param_first_a.v + wire [2:0]\t\tvarwidth2;\t\t// From a2 of t_param_first_a.v + wire [3:0]\t\tvarwidth3;\t\t// From a3 of t_param_first_a.v + wire [3:0]\t\tvarwidth4;\t\t// From a4 of t_param_first_a.v + // End of automatics + /*t_param_first_a AUTO_TEMPLATE ( +\t\t .par\t\t(par@[])); +\t\t .varwidth\t\t(varwidth@[])); + */ + + parameter XX = 2\'bXX; + + parameter THREE = 3; + + t_param_first_a #(1,5) a1 + ( + // Outputs + .varwidth\t\t(varwidth1[1:0]), + /*AUTOINST*/ + // Outputs + .par\t\t\t\t(par1[4:0]));\t\t // Templated + t_param_first_a #(2,5) a2 + ( + // Outputs + .varwidth\t\t(varwidth2[2:0]), + /*AUTOINST*/ + // Outputs + .par\t\t\t\t(par2[4:0]));\t\t // Templated + t_param_first_a #(THREE,5) a3 + ( + // Outputs + .varwidth\t\t(varwidth3[3:0]), + /*AUTOINST*/ + // Outputs + .par\t\t\t\t(par3[4:0]));\t\t // Templated + t_param_first_a #(THREE,5) a4 + ( + // Outputs + .varwidth\t\t(varwidth4[3:0]), + /*AUTOINST*/ + // Outputs + .par\t\t\t\t(par4[4:0]));\t\t // Templated + + parameter THREE_BITS_WIDE = 3\'b011; + parameter THREE_2WIDE = 2\'b11; + parameter ALSO_THREE_WIDE = THREE_BITS_WIDE; + parameter THREEPP_32_WIDE = 2*8*2+3; + parameter THREEPP_3_WIDE = 3\'d4*3\'d4*3\'d2+3\'d3; // Yes folks VCS says 3 bits wide + + // Width propagation doesn\'t care about LHS vs RHS + // But the width of a RHS/LHS on a upper node does affect lower nodes; + // Thus must double-descend in width analysis. + // VCS 7.0.1 is broken on this test! + parameter T10 = (3\'h7+3\'h7)+4\'h0;\t//initial if (T10!==4\'d14) $stop; + parameter T11 = 4\'h0+(3\'h7+3\'h7);\t//initial if (T11!==4\'d14) $stop; + + // Parameters assign LHS is affectively width zero. + parameter T12 = THREE_2WIDE + THREE_2WIDE;\tinitial if (T12!==2\'d2) $stop; + parameter T13 = THREE_2WIDE + 3;\t\tinitial if (T13!==32\'d6) $stop; + + // Must be careful about LSB\'s with extracts + parameter [39:8] T14 = 32\'h00_1234_56; initial if (T14[24:16]!==9\'h34) $stop; + + // + parameter THREEPP_32P_WIDE = 3\'d4*3\'d4*2+3\'d3; + parameter THREE_32_WIDE = 3%32; + parameter THIRTYTWO = 2;\t// Param is 32 bits + parameter [40:0] WIDEPARAM = 41\'h12_3456789a; + parameter [40:0] WIDEPARAM2 = WIDEPARAM; + + reg [7:0] eightb; + reg [3:0] fourb; + wire [7:0] eight = 8\'b00010000; + wire [1:0] eight2two = eight[THREE_32_WIDE+1:THREE_32_WIDE]; + wire [2:0] threebits = ALSO_THREE_WIDE; + + // surefire lint_off CWCCXX + + initial _ranit = 0; + + always @ (posedge clk) begin + if (!_ranit) begin +\t _ranit <= 1; +\t $write(""[%0t] t_param: Running\ +"", $time); +\t // +\t $write("" %d %d %d\ +"", par1,par2,par3); +\t if (par1!==5\'d1) $stop; +\t if (par2!==5\'d2) $stop; +\t if (par3!==5\'d3) $stop; +\t if (par4!==5\'d3) $stop; +\t if (varwidth1!==2\'d2) $stop; +\t if (varwidth2!==3\'d2) $stop; +\t if (varwidth3!==4\'d2) $stop; +\t if (varwidth4!==4\'d2) $stop; +\t if (threebits !== 3\'b011) $stop; +\t if (eight !== 8\'b00010000) $stop; +\t if (eight2two !== 2\'b10) $stop; +\t $write("" Params = %b %b\ + %b %b\ +"", +\t\tTHREEPP_32_WIDE,THREEPP_3_WIDE, +\t\tTHIRTYTWO, THREEPP_32P_WIDE); +\t if (THREEPP_32_WIDE !== 32\'h23) $stop; +\t if (THREEPP_3_WIDE !== 3\'h3) $stop; +\t if (THREEPP_32P_WIDE !== 32\'h23) $stop; +\t if (THIRTYTWO[1:0] !== 2\'h2) $stop; +\t if (THIRTYTWO !== 32\'h2) $stop; +\t if (THIRTYTWO !== 2) $stop; +\t if ((THIRTYTWO[1:0]+2\'b00) !== 2\'b10) $stop; +\t if ({1\'b1,{THIRTYTWO[1:0]+2\'b00}} !== 3\'b110) $stop; +\t if (XX===0 || XX===1 || XX===2 || XX===3) $stop; // Paradoxical but right, since 1\'bx!=0 && !=1 +\t // +\t // Example of assignment LHS affecting expression widths. +\t // verilator lint_off WIDTH +\t // surefire lint_off ASWCMB +\t // surefire lint_off ASWCBB +\t eightb = (4\'d8+4\'d8)/4\'d4;\tif (eightb!==8\'d4) $stop; +\t fourb = (4\'d8+4\'d8)/4\'d4;\tif (fourb!==4\'d0) $stop; +\t fourb = (4\'d8+8)/4\'d4;\t\tif (fourb!==4\'d4) $stop; +\t // verilator lint_on WIDTH +\t // surefire lint_on ASWCMB +\t // surefire lint_on ASWCBB +\t // +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + value + ); + input [3:0] value; + assign value = 4'h0; + sub sub (.valueSub\t(value[3:0])); +endmodule + +module sub (/*AUTOARG*/ + // Inputs + valueSub + ); + input [3:0] valueSub; + assign valueSub = 4'h0; +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // verilator lint_off GENCLK + + reg [7:0] cyc; initial cyc=0; + reg [7:0] padd; + reg \t dsp_ph1, dsp_ph2, dsp_reset; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [7:0]\t\tout;\t\t\t// From dspchip of t_dspchip.v + // End of automatics + + t_dspchip dspchip (/*AUTOINST*/ +\t\t // Outputs +\t\t .out\t\t(out[7:0]), +\t\t // Inputs +\t\t .dsp_ph1\t\t(dsp_ph1), +\t\t .dsp_ph2\t\t(dsp_ph2), +\t\t .dsp_reset\t(dsp_reset), +\t\t .padd\t\t(padd[7:0])); + + always @ (posedge clk) begin + $write(""cyc %d\ +"",cyc); + if (cyc == 8\'d0) begin +\t cyc <= 8\'d1; +\t dsp_reset <= 0;\t// Need a posedge +\t padd <= 0; + end + else if (cyc == 8\'d20) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + else begin +\t cyc <= cyc + 8\'d1; +\t dsp_ph1 <= ((cyc&8\'d3) == 8\'d0); +\t dsp_ph2 <= ((cyc&8\'d3) == 8\'d2); +\t dsp_reset <= (cyc == 8\'d1); +\t padd <= cyc; +\t //$write(""[%0t] cyc %d %x->%x\ +"", $time, cyc, padd, out); +\t case (cyc) +\t default: $stop; +\t 8\'d01: ; +\t 8\'d02: ; +\t 8\'d03: ; +\t 8\'d04: ; +\t 8\'d05: ; +\t 8\'d06: ; +\t 8\'d07: ; +\t 8\'d08: ; +\t 8\'d09: if (out!==8\'h04) $stop; +\t 8\'d10: if (out!==8\'h04) $stop; +\t 8\'d11: if (out!==8\'h08) $stop; +\t 8\'d12: if (out!==8\'h08) $stop; +\t 8\'d13: if (out!==8\'h00) $stop; +\t 8\'d14: if (out!==8\'h00) $stop; +\t 8\'d15: if (out!==8\'h00) $stop; +\t 8\'d16: if (out!==8\'h00) $stop; +\t 8\'d17: if (out!==8\'h0c) $stop; +\t 8\'d18: if (out!==8\'h0c) $stop; +\t 8\'d19: if (out!==8\'h10) $stop; +\t endcase + end + end + +endmodule + +module t_dspchip (/*AUTOARG*/ + // Outputs + out, + // Inputs + dsp_ph1, dsp_ph2, dsp_reset, padd + ); + input dsp_ph1, dsp_ph2, dsp_reset; + input [7:0] padd; + output [7:0] out; + + wire \tdsp_ph1, dsp_ph2; + wire [7:0] \tout; + wire \tpla_ph1, pla_ph2; + wire \tout1_r; + wire [7:0] \tout2_r, padd; + wire \tclk_en; + + t_dspcore t_dspcore (/*AUTOINST*/ +\t\t\t// Outputs +\t\t\t.out1_r\t\t(out1_r), +\t\t\t.pla_ph1\t(pla_ph1), +\t\t\t.pla_ph2\t(pla_ph2), +\t\t\t// Inputs +\t\t\t.dsp_ph1\t(dsp_ph1), +\t\t\t.dsp_ph2\t(dsp_ph2), +\t\t\t.dsp_reset\t(dsp_reset), +\t\t\t.clk_en\t\t(clk_en)); + t_dsppla t_dsppla (/*AUTOINST*/ +\t\t // Outputs +\t\t .out2_r\t\t(out2_r[7:0]), +\t\t // Inputs +\t\t .pla_ph1\t\t(pla_ph1), +\t\t .pla_ph2\t\t(pla_ph2), +\t\t .dsp_reset\t(dsp_reset), +\t\t .padd\t\t(padd[7:0])); + + assign \tout = out1_r ? 8\'h00 : out2_r; + assign \tclk_en = 1\'b1; + +endmodule + +module t_dspcore (/*AUTOARG*/ + // Outputs + out1_r, pla_ph1, pla_ph2, + // Inputs + dsp_ph1, dsp_ph2, dsp_reset, clk_en + ); + input dsp_ph1, dsp_ph2, dsp_reset; + input clk_en; + output out1_r, pla_ph1, pla_ph2; + + wire dsp_ph1, dsp_ph2, dsp_reset; + wire pla_ph1, pla_ph2; + reg \t out1_r; + + always @(posedge dsp_ph1 or posedge dsp_reset) begin + if (dsp_reset) +\tout1_r <= 1\'h0; + else +\tout1_r <= ~out1_r; + end + + assign pla_ph1 = dsp_ph1; + assign pla_ph2 = dsp_ph2 & clk_en; + +endmodule + +module t_dsppla (/*AUTOARG*/ + // Outputs + out2_r, + // Inputs + pla_ph1, pla_ph2, dsp_reset, padd + ); + input pla_ph1, pla_ph2, dsp_reset; + input [7:0] padd; + output [7:0] out2_r; + + wire \tpla_ph1, pla_ph2, dsp_reset; + wire [7:0] \tpadd; + reg [7:0] \tout2_r; + + reg [7:0] \tlatched_r; + + always @(posedge pla_ph1 or posedge dsp_reset) begin + if (dsp_reset) +\tlatched_r <= 8\'h00; + else +\tlatched_r <= padd; + end + + always @(posedge pla_ph2 or posedge dsp_reset) begin + if (dsp_reset) +\tout2_r <= 8\'h00; + else +\tout2_r <= latched_r; + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t; + +`define DUP fred +`define DUP barney + +`define DUPP paramed(x) (x) +`define DUPP paramed(x,z) (x*z) + + initial $stop; // Should have failed + +endmodule +" +"module t(y); + output [3:0] y; + // bug775 + // verilator lint_off WIDTH + assign y = ((0/0) ? 1 : 2) % 0; + + initial begin + $write(""*-* All Finished *-*\ +""); + $finish; + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // verilator lint_off GENCLK + + reg [7:0] cyc; initial cyc=0; + reg \t genclk; + // verilator lint_off MULTIDRIVEN + reg [7:0] set_both; + // verilator lint_on MULTIDRIVEN + + wire genthiscyc = ( (cyc % 2) == 1 ); + + always @ (posedge clk) begin + cyc <= cyc + 8\'h1; + genclk <= genthiscyc; + set_both <= cyc; + $write (""SB set_both %x <= cyc %x\ +"", set_both, cyc); + if (genthiscyc) begin +\t if (cyc>1 && set_both != (cyc - 8\'h1)) $stop; + end + else begin +\t if (cyc>1 && set_both != ~(cyc - 8\'h1)) $stop; + end + if (cyc==10) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end + + always @ (posedge genclk) begin + set_both <= ~ set_both; + $write (""SB set_both %x <= cyc %x\ +"", set_both, ~cyc); + if (cyc>1 && set_both != (cyc - 8\'h1)) $stop; + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg [255:0] \t\ti; + wire [255:0]\t\tq; + + assign q = { +\t\ti[176],i[168],i[126],i[177],i[097],i[123],i[231],i[039], +\t\ti[156],i[026],i[001],i[052],i[005],i[240],i[157],i[048], +\t\ti[111],i[088],i[133],i[225],i[046],i[038],i[004],i[234], +\t\ti[115],i[008],i[069],i[099],i[137],i[130],i[255],i[122], +\t\ti[223],i[195],i[224],i[083],i[094],i[018],i[067],i[034], +\t\ti[221],i[105],i[104],i[107],i[053],i[066],i[020],i[174], +\t\ti[010],i[196],i[003],i[041],i[071],i[194],i[154],i[110], +\t\ti[186],i[210],i[040],i[044],i[243],i[236],i[239],i[183], +\t\ti[164],i[064],i[086],i[193],i[055],i[206],i[203],i[128], +\t\ti[190],i[233],i[023],i[022],i[135],i[108],i[061],i[139], +\t\ti[180],i[043],i[109],i[090],i[229],i[238],i[095],i[173], +\t\ti[208],i[054],i[025],i[024],i[148],i[079],i[246],i[142], +\t\ti[181],i[129],i[120],i[220],i[036],i[159],i[201],i[119], +\t\ti[216],i[152],i[175],i[138],i[242],i[143],i[101],i[035], +\t\ti[228],i[082],i[211],i[062],i[076],i[124],i[150],i[149], +\t\ti[235],i[227],i[250],i[134],i[068],i[032],i[060],i[144], +\t\ti[042],i[163],i[087],i[059],i[213],i[251],i[200],i[070], +\t\ti[145],i[204],i[249],i[191],i[127],i[247],i[106],i[017], +\t\ti[028],i[045],i[215],i[162],i[205],i[073],i[065],i[084], +\t\ti[153],i[158],i[085],i[197],i[212],i[114],i[096],i[118], +\t\ti[146],i[030],i[058],i[230],i[141],i[000],i[199],i[171], +\t\ti[182],i[185],i[021],i[016],i[033],i[237],i[015],i[112], +\t\ti[222],i[253],i[244],i[031],i[248],i[092],i[226],i[179], +\t\ti[189],i[056],i[132],i[116],i[072],i[184],i[027],i[002], +\t\ti[103],i[125],i[009],i[078],i[178],i[245],i[170],i[161], +\t\ti[102],i[047],i[192],i[012],i[057],i[207],i[187],i[151], +\t\ti[218],i[254],i[214],i[037],i[131],i[165],i[011],i[098], +\t\ti[169],i[209],i[167],i[202],i[100],i[172],i[147],i[013], +\t\ti[136],i[166],i[252],i[077],i[051],i[074],i[140],i[050], +\t\ti[217],i[198],i[081],i[091],i[075],i[121],i[188],i[219], +\t\ti[160],i[241],i[080],i[155],i[019],i[006],i[014],i[029], +\t\ti[089],i[049],i[113],i[232],i[007],i[117],i[063],i[093] +\t }; + + always @ (posedge clk) begin + if (cyc!=0) begin +\t cyc <= cyc + 1; +`ifdef TEST_VERBOSE +\t $write(""%x %x\ +"", q, i); +`endif +\t if (cyc==1) begin +\t i <= 256\'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26; +\t end +\t if (cyc==2) begin +\t i <= 256\'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8; +\t if (q != 256\'h697bad4b0cf2d7fa4ad22809293710bb67d1eb3131e8eb2135f2c7bd820baa84) $stop; +\t end +\t if (cyc==3) begin +\t if (q != 256\'h320eda5078b3e942353d16dddc8b29fd773b4fcec8323612dadfb1fa483f602c) $stop; +\t end +\t if (cyc==4) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; +\t end + end + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2006 by Wilson Snyder. + +`include ""verilated.v"" + +module t_case_write2_tasks (); + + // verilator lint_off WIDTH + // verilator lint_off CASEINCOMPLETE + + `define FD_BITS 31:0 + + parameter STRLEN = 78; + task ozonerab; + input [6:0] rab; + input [`FD_BITS] fd; + // verilator no_inline_task + begin +\t case (rab[6:0]) +\t 7\'h00 : $fwrite (fd, "" 0""); +\t 7\'h01 : $fwrite (fd, "" 1""); +\t 7\'h02 : $fwrite (fd, "" 2""); +\t 7\'h03 : $fwrite (fd, "" 3""); +\t 7\'h04 : $fwrite (fd, "" 4""); +\t 7\'h05 : $fwrite (fd, "" 5""); +\t 7\'h06 : $fwrite (fd, "" 6""); +\t 7\'h07 : $fwrite (fd, "" 7""); +\t 7\'h08 : $fwrite (fd, "" 8""); +\t 7\'h09 : $fwrite (fd, "" 9""); +\t 7\'h0a : $fwrite (fd, "" 10""); +\t 7\'h0b : $fwrite (fd, "" 11""); +\t 7\'h0c : $fwrite (fd, "" 12""); +\t 7\'h0d : $fwrite (fd, "" 13""); +\t 7\'h0e : $fwrite (fd, "" 14""); +\t 7\'h0f : $fwrite (fd, "" 15""); +\t 7\'h10 : $fwrite (fd, "" 16""); +\t 7\'h11 : $fwrite (fd, "" 17""); +\t 7\'h12 : $fwrite (fd, "" 18""); +\t 7\'h13 : $fwrite (fd, "" 19""); +\t 7\'h14 : $fwrite (fd, "" 20""); +\t 7\'h15 : $fwrite (fd, "" 21""); +\t 7\'h16 : $fwrite (fd, "" 22""); +\t 7\'h17 : $fwrite (fd, "" 23""); +\t 7\'h18 : $fwrite (fd, "" 24""); +\t 7\'h19 : $fwrite (fd, "" 25""); +\t 7\'h1a : $fwrite (fd, "" 26""); +\t 7\'h1b : $fwrite (fd, "" 27""); +\t 7\'h1c : $fwrite (fd, "" 28""); +\t 7\'h1d : $fwrite (fd, "" 29""); +\t 7\'h1e : $fwrite (fd, "" 30""); +\t 7\'h1f : $fwrite (fd, "" 31""); +\t 7\'h20 : $fwrite (fd, "" 32""); +\t 7\'h21 : $fwrite (fd, "" 33""); +\t 7\'h22 : $fwrite (fd, "" 34""); +\t 7\'h23 : $fwrite (fd, "" 35""); +\t 7\'h24 : $fwrite (fd, "" 36""); +\t 7\'h25 : $fwrite (fd, "" 37""); +\t 7\'h26 : $fwrite (fd, "" 38""); +\t 7\'h27 : $fwrite (fd, "" 39""); +\t 7\'h28 : $fwrite (fd, "" 40""); +\t 7\'h29 : $fwrite (fd, "" 41""); +\t 7\'h2a : $fwrite (fd, "" 42""); +\t 7\'h2b : $fwrite (fd, "" 43""); +\t 7\'h2c : $fwrite (fd, "" 44""); +\t 7\'h2d : $fwrite (fd, "" 45""); +\t 7\'h2e : $fwrite (fd, "" 46""); +\t 7\'h2f : $fwrite (fd, "" 47""); +\t 7\'h30 : $fwrite (fd, "" 48""); +\t 7\'h31 : $fwrite (fd, "" 49""); +\t 7\'h32 : $fwrite (fd, "" 50""); +\t 7\'h33 : $fwrite (fd, "" 51""); +\t 7\'h34 : $fwrite (fd, "" 52""); +\t 7\'h35 : $fwrite (fd, "" 53""); +\t 7\'h36 : $fwrite (fd, "" 54""); +\t 7\'h37 : $fwrite (fd, "" 55""); +\t 7\'h38 : $fwrite (fd, "" 56""); +\t 7\'h39 : $fwrite (fd, "" 57""); +\t 7\'h3a : $fwrite (fd, "" 58""); +\t 7\'h3b : $fwrite (fd, "" 59""); +\t 7\'h3c : $fwrite (fd, "" 60""); +\t 7\'h3d : $fwrite (fd, "" 61""); +\t 7\'h3e : $fwrite (fd, "" 62""); +\t 7\'h3f : $fwrite (fd, "" 63""); +\t 7\'h40 : $fwrite (fd, "" 64""); +\t 7\'h41 : $fwrite (fd, "" 65""); +\t 7\'h42 : $fwrite (fd, "" 66""); +\t 7\'h43 : $fwrite (fd, "" 67""); +\t 7\'h44 : $fwrite (fd, "" 68""); +\t 7\'h45 : $fwrite (fd, "" 69""); +\t 7\'h46 : $fwrite (fd, "" 70""); +\t 7\'h47 : $fwrite (fd, "" 71""); +\t 7\'h48 : $fwrite (fd, "" 72""); +\t 7\'h49 : $fwrite (fd, "" 73""); +\t 7\'h4a : $fwrite (fd, "" 74""); +\t 7\'h4b : $fwrite (fd, "" 75""); +\t 7\'h4c : $fwrite (fd, "" 76""); +\t 7\'h4d : $fwrite (fd, "" 77""); +\t 7\'h4e : $fwrite (fd, "" 78""); +\t 7\'h4f : $fwrite (fd, "" 79""); +\t 7\'h50 : $fwrite (fd, "" 80""); +\t 7\'h51 : $fwrite (fd, "" 81""); +\t 7\'h52 : $fwrite (fd, "" 82""); +\t 7\'h53 : $fwrite (fd, "" 83""); +\t 7\'h54 : $fwrite (fd, "" 84""); +\t 7\'h55 : $fwrite (fd, "" 85""); +\t 7\'h56 : $fwrite (fd, "" 86""); +\t 7\'h57 : $fwrite (fd, "" 87""); +\t 7\'h58 : $fwrite (fd, "" 88""); +\t 7\'h59 : $fwrite (fd, "" 89""); +\t 7\'h5a : $fwrite (fd, "" 90""); +\t 7\'h5b : $fwrite (fd, "" 91""); +\t 7\'h5c : $fwrite (fd, "" 92""); +\t 7\'h5d : $fwrite (fd, "" 93""); +\t 7\'h5e : $fwrite (fd, "" 94""); +\t 7\'h5f : $fwrite (fd, "" 95""); +\t 7\'h60 : $fwrite (fd, "" 96""); +\t 7\'h61 : $fwrite (fd, "" 97""); +\t 7\'h62 : $fwrite (fd, "" 98""); +\t 7\'h63 : $fwrite (fd, "" 99""); +\t 7\'h64 : $fwrite (fd, "" 100""); +\t 7\'h65 : $fwrite (fd, "" 101""); +\t 7\'h66 : $fwrite (fd, "" 102""); +\t 7\'h67 : $fwrite (fd, "" 103""); +\t 7\'h68 : $fwrite (fd, "" 104""); +\t 7\'h69 : $fwrite (fd, "" 105""); +\t 7\'h6a : $fwrite (fd, "" 106""); +\t 7\'h6b : $fwrite (fd, "" 107""); +\t 7\'h6c : $fwrite (fd, "" 108""); +\t 7\'h6d : $fwrite (fd, "" 109""); +\t 7\'h6e : $fwrite (fd, "" 110""); +\t 7\'h6f : $fwrite (fd, "" 111""); +\t 7\'h70 : $fwrite (fd, "" 112""); +\t 7\'h71 : $fwrite (fd, "" 113""); +\t 7\'h72 : $fwrite (fd, "" 114""); +\t 7\'h73 : $fwrite (fd, "" 115""); +\t 7\'h74 : $fwrite (fd, "" 116""); +\t 7\'h75 : $fwrite (fd, "" 117""); +\t 7\'h76 : $fwrite (fd, "" 118""); +\t 7\'h77 : $fwrite (fd, "" 119""); +\t 7\'h78 : $fwrite (fd, "" 120""); +\t 7\'h79 : $fwrite (fd, "" 121""); +\t 7\'h7a : $fwrite (fd, "" 122""); +\t 7\'h7b : $fwrite (fd, "" 123""); +\t 7\'h7c : $fwrite (fd, "" 124""); +\t 7\'h7d : $fwrite (fd, "" 125""); +\t 7\'h7e : $fwrite (fd, "" 126""); +\t 7\'h7f : $fwrite (fd, "" 127""); +\t default:$fwrite (fd, "" 128""); +\t endcase + end + endtask + + task ozonerb; + input [5:0] rb; + input [`FD_BITS] fd; + // verilator no_inline_task + begin +\t case (rb[5:0]) +\t 6\'h10, +\t 6\'h17, +\t 6\'h1e, +\t 6\'h1f: $fwrite (fd, "" 129""); +\t default: ozonerab({1\'b1, rb}, fd); +\t endcase + end + endtask + + task ozonef3f4_iext; + input [1:0] foo; + input [15:0] im16; + input [`FD_BITS] fd; + // verilator no_inline_task + begin +\t case (foo) +\t 2\'h0 : + begin +\t\tskyway({4{im16[15]}}, fd); +\t\tskyway({4{im16[15]}}, fd); +\t\tskyway(im16[15:12], fd); +\t\tskyway(im16[11: 8], fd); +\t\tskyway(im16[ 7: 4], fd); +\t\tskyway(im16[ 3:0], fd); +\t\t$fwrite (fd, "" 130""); + end +\t 2\'h1 : + begin +\t\t$fwrite (fd, "" 131""); +\t\tskyway(im16[15:12], fd); +\t\tskyway(im16[11: 8], fd); +\t\tskyway(im16[ 7: 4], fd); +\t\tskyway(im16[ 3:0], fd); + end +\t 2\'h2 : + begin +\t\tskyway({4{im16[15]}}, fd); +\t\tskyway({4{im16[15]}}, fd); +\t\tskyway(im16[15:12], fd); +\t\tskyway(im16[11: 8], fd); +\t\tskyway(im16[ 7: 4], fd); +\t\tskyway(im16[ 3:0], fd); +\t\t$fwrite (fd, "" 132""); + end +\t 2\'h3 : + begin +\t\t$fwrite (fd, "" 133""); +\t\tskyway(im16[15:12], fd); +\t\tskyway(im16[11: 8], fd); +\t\tskyway(im16[ 7: 4], fd); +\t\tskyway(im16[ 3:0], fd); + end +\t endcase + end + endtask + + task skyway; + input [ 3:0] hex; + input [`FD_BITS] fd; + // verilator no_inline_task + begin +\t case (hex) +\t 4\'h0 : $fwrite (fd, "" 134""); +\t 4\'h1 : $fwrite (fd, "" 135""); +\t 4\'h2 : $fwrite (fd, "" 136""); +\t 4\'h3 : $fwrite (fd, "" 137""); +\t 4\'h4 : $fwrite (fd, "" 138""); +\t 4\'h5 : $fwrite (fd, "" 139""); +\t 4\'h6 : $fwrite (fd, "" 140""); +\t 4\'h7 : $fwrite (fd, "" 141""); +\t 4\'h8 : $fwrite (fd, "" 142""); +\t 4\'h9 : $fwrite (fd, "" 143""); +\t 4\'ha : $fwrite (fd, "" 144""); +\t 4\'hb : $fwrite (fd, "" 145""); +\t 4\'hc : $fwrite (fd, "" 146""); +\t 4\'hd : $fwrite (fd, "" 147""); +\t 4\'he : $fwrite (fd, "" 148""); +\t 4\'hf : $fwrite (fd, "" 149""); +\t endcase + end + endtask + + task ozonesr; + input [ 15:0] foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin +\t case (foo[11: 9]) +\t 3\'h0 : $fwrite (fd, "" 158""); +\t 3\'h1 : $fwrite (fd, "" 159""); +\t 3\'h2 : $fwrite (fd, "" 160""); +\t 3\'h3 : $fwrite (fd, "" 161""); +\t 3\'h4 : $fwrite (fd, "" 162""); +\t 3\'h5 : $fwrite (fd, "" 163""); +\t 3\'h6 : $fwrite (fd, "" 164""); +\t 3\'h7 : $fwrite (fd, "" 165""); +\t endcase + end + endtask + + task ozonejk; + input k; + input [`FD_BITS] fd; + // verilator no_inline_task + begin +\t if (k) +\t $fwrite (fd, "" 166""); +\t else +\t $fwrite (fd, "" 167""); + end + endtask + + task ozoneae; + input [ 2:0] ae; + input [`FD_BITS] fd; + // verilator no_inline_task + begin +\t case (ae) +\t 3\'b000 : $fwrite (fd, "" 168""); +\t 3\'b001 : $fwrite (fd, "" 169""); +\t 3\'b010 : $fwrite (fd, "" 170""); +\t 3\'b011 : $fwrite (fd, "" 171""); +\t 3\'b100 : $fwrite (fd, "" 172""); +\t 3\'b101 : $fwrite (fd, "" 173""); +\t 3\'b110 : $fwrite (fd, "" 174""); +\t 3\'b111 : $fwrite (fd, "" 175""); +\t endcase + end + endtask + + task ozoneaee; + input [ 2:0] aee; + input [`FD_BITS] \tfd; + // verilator no_inline_task + begin +\t case (aee) +\t 3\'b001, +\t 3\'b011, +\t 3\'b101, +\t 3\'b111 : $fwrite (fd, "" 176""); +\t 3\'b000 : $fwrite (fd, "" 177""); +\t 3\'b010 : $fwrite (fd, "" 178""); +\t 3\'b100 : $fwrite (fd, "" 179""); +\t 3\'b110 : $fwrite (fd, "" 180""); +\t endcase + end + endtask + + task ozoneape; + input [ 2:0] ape; + input [`FD_BITS] \tfd; + // verilator no_inline_task + begin +\t case (ape) +\t 3\'b001, +\t 3\'b011, +\t 3\'b101, +\t 3\'b111 : $fwrite (fd, "" 181""); +\t 3\'b000 : $fwrite (fd, "" 182""); +\t 3\'b010 : $fwrite (fd, "" 183""); +\t 3\'b100 : $fwrite (fd, "" 184""); +\t 3\'b110 : $fwrite (fd, "" 185""); +\t endcase + end + endtask + + task ozonef1; + input [ 31:0] foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin +\t case (foo[24:21]) +\t 4\'h0 : + if (foo[26]) + $fwrite (fd, "" 186""); + else + $fwrite (fd, "" 187""); +\t 4\'h1 : + case (foo[26:25]) + 2\'b00 : $fwrite (fd, "" 188""); + 2\'b01 : $fwrite (fd, "" 189""); + 2\'b10 : $fwrite (fd, "" 190""); + 2\'b11 : $fwrite (fd, "" 191""); + endcase +\t 4\'h2 : $fwrite (fd, "" 192""); +\t 4\'h3 : + case (foo[26:25]) + 2\'b00 : $fwrite (fd, "" 193""); + 2\'b01 : $fwrite (fd, "" 194""); + 2\'b10 : $fwrite (fd, "" 195""); + 2\'b11 : $fwrite (fd, "" 196""); + endcase +\t 4\'h4 : + if (foo[26]) + $fwrite (fd, "" 197""); + else + $fwrite (fd, "" 198""); +\t 4\'h5 : + case (foo[26:25]) + 2\'b00 : $fwrite (fd, "" 199""); + 2\'b01 : $fwrite (fd, "" 200""); + 2\'b10 : $fwrite (fd, "" 201""); + 2\'b11 : $fwrite (fd, "" 202""); + endcase +\t 4\'h6 : $fwrite (fd, "" 203""); +\t 4\'h7 : + case (foo[26:25]) + 2\'b00 : $fwrite (fd, "" 204""); + 2\'b01 : $fwrite (fd, "" 205""); + 2\'b10 : $fwrite (fd, "" 206""); + 2\'b11 : $fwrite (fd, "" 207""); + endcase +\t 4\'h8 : + case (foo[26:25]) + 2\'b00 : $fwrite (fd, "" 208""); + 2\'b01 : $fwrite (fd, "" 209""); + 2\'b10 : $fwrite (fd, "" 210""); + 2\'b11 : $fwrite (fd, "" 211""); + endcase +\t 4\'h9 : + case (foo[26:25]) + 2\'b00 : $fwrite (fd, "" 212""); + 2\'b01 : $fwrite (fd, "" 213""); + 2\'b10 : $fwrite (fd, "" 214""); + 2\'b11 : $fwrite (fd, "" 215""); + endcase +\t 4\'ha : + if (foo[25]) + $fwrite (fd, "" 216""); + else + $fwrite (fd, "" 217""); +\t 4\'hb : + if (foo[25]) + $fwrite (fd, "" 218""); + else + $fwrite (fd, "" 219""); +\t 4\'hc : + if (foo[26]) + $fwrite (fd, "" 220""); + else + $fwrite (fd, "" 221""); +\t 4\'hd : + case (foo[26:25]) + 2\'b00 : $fwrite (fd, "" 222""); + 2\'b01 : $fwrite (fd, "" 223""); + 2\'b10 : $fwrite (fd, "" 224""); + 2\'b11 : $fwrite (fd, "" 225""); + endcase +\t 4\'he : + case (foo[26:25]) + 2\'b00 : $fwrite (fd, "" 226""); + 2\'b01 : $fwrite (fd, "" 227""); + 2\'b10 : $fwrite (fd, "" 228""); + 2\'b11 : $fwrite (fd, "" 229""); + endcase +\t 4\'hf : + case (foo[26:25]) + 2\'b00 : $fwrite (fd, "" 230""); + 2\'b01 : $fwrite (fd, "" 231""); + 2\'b10 : $fwrite (fd, "" 232""); + 2\'b11 : $fwrite (fd, "" 233""); + endcase +\t endcase + end + endtask + + task ozonef1e; + input [ 31:0] foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin +\t case (foo[27:21]) +\t 7\'h00: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 234""); +\t\t$fwrite (fd, "" 235""); +\t end +\t 7\'h01: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 236""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 237""); +\t\t$fwrite (fd, "" 238""); +\t end +\t 7\'h02: +\t $fwrite (fd, "" 239""); +\t 7\'h03: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 240""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 241""); +\t\t$fwrite (fd, "" 242""); +\t end +\t 7\'h04: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 243""); +\t\t$fwrite (fd,"" 244""); +\t end +\t 7\'h05: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 245""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 246""); +\t end +\t 7\'h06: +\t $fwrite (fd, "" 247""); +\t 7\'h07: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 248""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 249""); +\t end +\t 7\'h08: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 250""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 251""); +\t end +\t 7\'h09: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 252""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 253""); +\t end +\t 7\'h0a: +\t begin +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 254""); +\t end +\t 7\'h0b: +\t begin +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 255""); +\t end +\t 7\'h0c: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 256""); +\t end +\t 7\'h0d: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 257""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 258""); +\t end +\t 7\'h0e: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 259""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 260""); +\t end +\t 7\'h0f: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 261""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 262""); +\t end +\t 7\'h10: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 263""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 264""); +\t\t$fwrite (fd, "" 265""); +\t\t$fwrite (fd, "" 266""); +\t end +\t 7\'h11: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 267""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 268""); +\t\t$fwrite (fd, "" 269""); +\t\t$fwrite (fd, "" 270""); +\t end +\t 7\'h12: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 271""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 272""); +\t\t$fwrite (fd, "" 273""); +\t\t$fwrite (fd, "" 274""); +\t end +\t 7\'h13: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 275""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 276""); +\t\t$fwrite (fd, "" 277""); +\t\t$fwrite (fd, "" 278""); +\t end +\t 7\'h14: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 279""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 280""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 281""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 282""); +\t\t$fwrite (fd, "" 283""); +\t\t$fwrite (fd, "" 284""); +\t end +\t 7\'h15: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 285""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 286""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 287""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 288""); +\t\t$fwrite (fd, "" 289""); +\t\t$fwrite (fd, "" 290""); +\t end +\t 7\'h16: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 291""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 292""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 293""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 294""); +\t\t$fwrite (fd, "" 295""); +\t\t$fwrite (fd, "" 296""); +\t end +\t 7\'h17: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 297""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 298""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 299""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 300""); +\t\t$fwrite (fd, "" 301""); +\t\t$fwrite (fd, "" 302""); +\t end +\t 7\'h18: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 303""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 304""); +\t\t$fwrite (fd, "" 305""); +\t\t$fwrite (fd, "" 306""); +\t end +\t 7\'h19: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 307""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 308""); +\t\t$fwrite (fd, "" 309""); +\t\t$fwrite (fd, "" 310""); +\t end +\t 7\'h1a: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 311""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 312""); +\t\t$fwrite (fd, "" 313""); +\t\t$fwrite (fd, "" 314""); +\t end +\t 7\'h1b: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 315""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 316""); +\t\t$fwrite (fd, "" 317""); +\t\t$fwrite (fd, "" 318""); +\t end +\t 7\'h1c: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 319""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 320""); +\t\t$fwrite (fd, "" 321""); +\t\t$fwrite (fd, "" 322""); +\t end +\t 7\'h1d: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 323""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 324""); +\t\t$fwrite (fd, "" 325""); +\t\t$fwrite (fd, "" 326""); +\t end +\t 7\'h1e: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 327""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 328""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 329""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 330""); +\t\t$fwrite (fd, "" 331""); +\t\t$fwrite (fd, "" 332""); +\t end +\t 7\'h1f: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 333""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 334""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 335""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 336""); +\t\t$fwrite (fd, "" 337""); +\t\t$fwrite (fd, "" 338""); +\t end +\t 7\'h20: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 339""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 340""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 341""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 342""); +\t\t$fwrite (fd, "" 343""); +\t\t$fwrite (fd, "" 344""); +\t end +\t 7\'h21: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 345""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 346""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 347""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 348""); +\t\t$fwrite (fd, "" 349""); +\t\t$fwrite (fd, "" 350""); +\t end +\t 7\'h22: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 351""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 352""); +\t\t$fwrite (fd, "" 353""); +\t\t$fwrite (fd, "" 354""); +\t end +\t 7\'h23: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 355""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 356""); +\t\t$fwrite (fd, "" 357""); +\t\t$fwrite (fd, "" 358""); +\t end +\t 7\'h24: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 359""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 360""); +\t\t$fwrite (fd, "" 361""); +\t\t$fwrite (fd, "" 362""); +\t end +\t 7\'h25: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 363""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 364""); +\t\t$fwrite (fd, "" 365""); +\t\t$fwrite (fd, "" 366""); +\t end +\t 7\'h26: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 367""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 368""); +\t\t$fwrite (fd, "" 369""); +\t\t$fwrite (fd, "" 370""); +\t end +\t 7\'h27: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 371""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 372""); +\t\t$fwrite (fd, "" 373""); +\t\t$fwrite (fd, "" 374""); +\t end +\t 7\'h28: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 375""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 376""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 377""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 378""); +\t\t$fwrite (fd, "" 379""); +\t\t$fwrite (fd, "" 380""); +\t end +\t 7\'h29: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 381""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 382""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 383""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 384""); +\t\t$fwrite (fd, "" 385""); +\t\t$fwrite (fd, "" 386""); +\t end +\t 7\'h2a: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 387""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 388""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 389""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 390""); +\t\t$fwrite (fd, "" 391""); +\t\t$fwrite (fd, "" 392""); +\t end +\t 7\'h2b: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 393""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 394""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 395""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 396""); +\t\t$fwrite (fd, "" 397""); +\t\t$fwrite (fd, "" 398""); +\t end +\t 7\'h2c: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 399""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 400""); +\t\t$fwrite (fd, "" 401""); +\t\t$fwrite (fd, "" 402""); +\t end +\t 7\'h2d: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 403""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 404""); +\t\t$fwrite (fd, "" 405""); +\t\t$fwrite (fd, "" 406""); +\t end +\t 7\'h2e: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 407""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 408""); +\t\t$fwrite (fd, "" 409""); +\t\t$fwrite (fd, "" 410""); +\t end +\t 7\'h2f: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 411""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 412""); +\t\t$fwrite (fd, "" 413""); +\t\t$fwrite (fd, "" 414""); +\t end +\t 7\'h30: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 415""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 416""); +\t\t$fwrite (fd, "" 417""); +\t\t$fwrite (fd, "" 418""); +\t end +\t 7\'h31: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 419""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 420""); +\t\t$fwrite (fd, "" 421""); +\t\t$fwrite (fd, "" 422""); +\t end +\t 7\'h32: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 423""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 424""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 425""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 426""); +\t\t$fwrite (fd, "" 427""); +\t\t$fwrite (fd, "" 428""); +\t end +\t 7\'h33: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 429""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 430""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 431""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 432""); +\t\t$fwrite (fd, "" 433""); +\t\t$fwrite (fd, "" 434""); +\t end +\t 7\'h34: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 435""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 436""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 437""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 438""); +\t\t$fwrite (fd, "" 439""); +\t\t$fwrite (fd, "" 440""); +\t end +\t 7\'h35: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 441""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 442""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 443""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 444""); +\t\t$fwrite (fd, "" 445""); +\t\t$fwrite (fd, "" 446""); +\t end +\t 7\'h36: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 447""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 448""); +\t\t$fwrite (fd, "" 449""); +\t\t$fwrite (fd, "" 450""); +\t end +\t 7\'h37: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 451""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 452""); +\t\t$fwrite (fd, "" 453""); +\t\t$fwrite (fd, "" 454""); +\t end +\t 7\'h38: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 455""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 456""); +\t\t$fwrite (fd, "" 457""); +\t end +\t 7\'h39: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 458""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 459""); +\t\t$fwrite (fd, "" 460""); +\t end +\t 7\'h3a: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 461""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 462""); +\t\t$fwrite (fd, "" 463""); +\t end +\t 7\'h3b: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 464""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 465""); +\t\t$fwrite (fd, "" 466""); +\t end +\t 7\'h3c: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 467""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 468""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 469""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 470""); +\t\t$fwrite (fd, "" 471""); +\t end +\t 7\'h3d: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 472""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 473""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 474""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 475""); +\t\t$fwrite (fd, "" 476""); +\t end +\t 7\'h3e: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 477""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 478""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 479""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 480""); +\t\t$fwrite (fd, "" 481""); +\t end +\t 7\'h3f: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 482""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 483""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 484""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 485""); +\t\t$fwrite (fd, "" 486""); +\t end +\t 7\'h40: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 487""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 488""); +\t\t$fwrite (fd, "" 489""); +\t\t$fwrite (fd, "" 490""); +\t end +\t 7\'h41: +\t begin +\t\t$fwrite (fd, "" 491""); +\t\t$fwrite (fd, "" 492""); +\t end +\t 7\'h42: +\t begin +\t\t$fwrite (fd, "" 493""); +\t\t$fwrite (fd, "" 494""); +\t end +\t 7\'h43: +\t begin +\t\t$fwrite (fd, "" 495""); +\t\t$fwrite (fd, "" 496""); +\t end +\t 7\'h44: +\t begin +\t\t$fwrite (fd, "" 497""); +\t\t$fwrite (fd, "" 498""); +\t end +\t 7\'h45: +\t $fwrite (fd, "" 499""); +\t 7\'h46: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 500""); +\t\t$fwrite (fd, "" 501""); +\t\t$fwrite (fd, "" 502""); +\t end +\t 7\'h47: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 503""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 504""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 505""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 506""); +\t\t$fwrite (fd, "" 507""); +\t\t$fwrite (fd, "" 508""); +\t end +\t 7\'h48: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 509""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 510""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 511""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 512""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 513""); +\t end +\t 7\'h49: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 514""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 515""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 516""); +\t end +\t 7\'h4a: + $fwrite (fd,"" 517""); +\t 7\'h4b: + $fwrite (fd, "" 518""); +\t 7\'h4c: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 519""); +\t\t$fwrite (fd, "" 520""); +\t\t$fwrite (fd, "" 521""); +\t end +\t 7\'h4d: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 522""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 523""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 524""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 525""); +\t\t$fwrite (fd, "" 526""); +\t\t$fwrite (fd, "" 527""); +\t end +\t 7\'h4e: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 528""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 529""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 530""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 531""); +\t end +\t 7\'h4f: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 532""); +\t end +\t 7\'h50: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 533""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 534""); +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 535""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 536""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 537""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 538""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 539""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 540""); +\t end +\t 7\'h51: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 541""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 542""); +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 543""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 544""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 545""); +\t end +\t 7\'h52: +\t $fwrite (fd, "" 546""); +\t 7\'h53: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd, "" 547""); +\t end +\t 7\'h54: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 548""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 549""); +\t end +\t 7\'h55: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 550""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 551""); +\t end +\t 7\'h56: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 552""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 553""); +\t\t$fwrite (fd, "" 554""); +\t end +\t 7\'h57: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 555""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 556""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 557""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 558""); +\t end +\t 7\'h58: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd, "" 559""); +\t end +\t 7\'h59: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 560""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 561""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 562""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 563""); +\t end +\t 7\'h5a: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 564""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd, "" 565""); +\t end +\t 7\'h5b: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 566""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd, "" 567""); +\t end +\t 7\'h5c: +\t begin +\t\t$fwrite (fd,"" 568""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 569""); +\t\t$fwrite (fd,"" 570""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 571""); +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 572""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd, "" 573""); +\t end +\t 7\'h5d: +\t begin +\t\t$fwrite (fd,"" 574""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 575""); +\t\t$fwrite (fd,"" 576""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 577""); +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 578""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd, "" 579""); +\t end +\t 7\'h5e: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 580""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd, "" 581""); +\t end +\t 7\'h5f: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 582""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 583""); +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 584""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 585""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 586""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 587""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 588""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 589""); +\t end +\t 7\'h60: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 590""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 591""); +\t end +\t 7\'h61: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 592""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 593""); +\t end +\t 7\'h62: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 594""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 595""); +\t end +\t 7\'h63: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 596""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 597""); +\t end +\t 7\'h64: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 598""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 599""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 600""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 601""); +\t end +\t 7\'h65: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 602""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 603""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 604""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 605""); +\t end +\t 7\'h66: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 606""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 607""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 608""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 609""); +\t end +\t 7\'h67: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 610""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 611""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 612""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 613""); +\t end +\t 7\'h68: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 614""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 615""); +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 616""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 617""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 618""); +\t\tozoneape(foo[17:15], fd); +\t end +\t 7\'h69: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 619""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 620""); +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 621""); +\t end +\t 7\'h6a: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 622""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 623""); +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 624""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 625""); +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 626""); +\t\tozoneae(foo[17:15], fd); +\t end +\t 7\'h6b: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 627""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 628""); +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 629""); +\t end +\t 7\'h6c: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 630""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 631""); +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 632""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 633""); +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 634""); +\t\tozoneae(foo[17:15], fd); +\t end +\t 7\'h6d: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 635""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 636""); +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 637""); +\t end +\t 7\'h6e: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 638""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 639""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 640""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 641""); +\t end +\t 7\'h6f: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 642""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 643""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 644""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 645""); +\t end +\t 7\'h70: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 646""); +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 647""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 648""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd, "" 649""); +\t end +\t 7\'h71: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 650""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd, "" 651""); +\t end +\t 7\'h72: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 652""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd, "" 653""); +\t end +\t 7\'h73: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 654""); +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 655""); +\t\tozoneae(foo[17:15], fd); +\t end +\t 7\'h74: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 656""); +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 657""); +\t\tozoneae(foo[17:15], fd); +\t end +\t 7\'h75: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 658""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 659""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 660""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 661""); +\t\t$fwrite (fd, "" 662""); +\t\t$fwrite (fd, "" 663""); +\t end +\t 7\'h76: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 664""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 665""); +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 666""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 667""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 668""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 669""); +\t end +\t 7\'h77: +\t begin +\t\tozoneaee(foo[20:18], fd); +\t\t$fwrite (fd,"" 670""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 671""); +\t\tozoneaee(foo[17:15], fd); +\t\t$fwrite (fd,"" 672""); +\t\tozoneape(foo[20:18], fd); +\t\t$fwrite (fd,"" 673""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 674""); +\t\tozoneape(foo[17:15], fd); +\t\t$fwrite (fd,"" 675""); +\t end +\t 7\'h78, +\t 7\'h79, +\t 7\'h7a, +\t 7\'h7b, +\t 7\'h7c, +\t 7\'h7d, +\t 7\'h7e, +\t 7\'h7f: + $fwrite (fd,"" 676""); +\t endcase + end + endtask + + task ozonef2; + input [ 31:0] foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin +\t case (foo[24:21]) +\t 4\'h0 : + case (foo[26:25]) + 2\'b00 : $fwrite (fd,"" 677""); + 2\'b01 : $fwrite (fd,"" 678""); + 2\'b10 : $fwrite (fd,"" 679""); + 2\'b11 : $fwrite (fd,"" 680""); + endcase +\t 4\'h1 : + case (foo[26:25]) + 2\'b00 : $fwrite (fd,"" 681""); + 2\'b01 : $fwrite (fd,"" 682""); + 2\'b10 : $fwrite (fd,"" 683""); + 2\'b11 : $fwrite (fd,"" 684""); + endcase +\t 4\'h2 : + case (foo[26:25]) + 2\'b00 : $fwrite (fd,"" 685""); + 2\'b01 : $fwrite (fd,"" 686""); + 2\'b10 : $fwrite (fd,"" 687""); + 2\'b11 : $fwrite (fd,"" 688""); + endcase +\t 4\'h3 : + case (foo[26:25]) + 2\'b00 : $fwrite (fd,"" 689""); + 2\'b01 : $fwrite (fd,"" 690""); + 2\'b10 : $fwrite (fd,"" 691""); + 2\'b11 : $fwrite (fd,"" 692""); + endcase +\t 4\'h4 : + case (foo[26:25]) + 2\'b00 : $fwrite (fd,"" 693""); + 2\'b01 : $fwrite (fd,"" 694""); + 2\'b10 : $fwrite (fd,"" 695""); + 2\'b11 : $fwrite (fd,"" 696""); + endcase +\t 4\'h5 : + case (foo[26:25]) + 2\'b00 : $fwrite (fd,"" 697""); + 2\'b01 : $fwrite (fd,"" 698""); + 2\'b10 : $fwrite (fd,"" 699""); + 2\'b11 : $fwrite (fd,"" 700""); + endcase +\t 4\'h6 : + case (foo[26:25]) + 2\'b00 : $fwrite (fd,"" 701""); + 2\'b01 : $fwrite (fd,"" 702""); + 2\'b10 : $fwrite (fd,"" 703""); + 2\'b11 : $fwrite (fd,"" 704""); + endcase +\t 4\'h7 : + case (foo[26:25]) + 2\'b00 : $fwrite (fd,"" 705""); + 2\'b01 : $fwrite (fd,"" 706""); + 2\'b10 : $fwrite (fd,"" 707""); + 2\'b11 : $fwrite (fd,"" 708""); + endcase +\t 4\'h8 : + if (foo[26]) + $fwrite (fd,"" 709""); + else + $fwrite (fd,"" 710""); +\t 4\'h9 : + case (foo[26:25]) + 2\'b00 : $fwrite (fd,"" 711""); + 2\'b01 : $fwrite (fd,"" 712""); + 2\'b10 : $fwrite (fd,"" 713""); + 2\'b11 : $fwrite (fd,"" 714""); + endcase +\t 4\'ha : + case (foo[26:25]) + 2\'b00 : $fwrite (fd,"" 715""); + 2\'b01 : $fwrite (fd,"" 716""); + 2\'b10 : $fwrite (fd,"" 717""); + 2\'b11 : $fwrite (fd,"" 718""); + endcase +\t 4\'hb : + case (foo[26:25]) + 2\'b00 : $fwrite (fd,"" 719""); + 2\'b01 : $fwrite (fd,"" 720""); + 2\'b10 : $fwrite (fd,"" 721""); + 2\'b11 : $fwrite (fd,"" 722""); + endcase +\t 4\'hc : + if (foo[26]) + $fwrite (fd,"" 723""); + else + $fwrite (fd,"" 724""); +\t 4\'hd : + case (foo[26:25]) + 2\'b00 : $fwrite (fd,"" 725""); + 2\'b01 : $fwrite (fd,"" 726""); + 2\'b10 : $fwrite (fd,"" 727""); + 2\'b11 : $fwrite (fd,"" 728""); + endcase +\t 4\'he : + case (foo[26:25]) + 2\'b00 : $fwrite (fd,"" 729""); + 2\'b01 : $fwrite (fd,"" 730""); + 2\'b10 : $fwrite (fd,"" 731""); + 2\'b11 : $fwrite (fd,"" 732""); + endcase +\t 4\'hf : + case (foo[26:25]) + 2\'b00 : $fwrite (fd,"" 733""); + 2\'b01 : $fwrite (fd,"" 734""); + 2\'b10 : $fwrite (fd,"" 735""); + 2\'b11 : $fwrite (fd,"" 736""); + endcase +\t endcase + end + endtask + + task ozonef2e; + input [ 31:0] foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin +\t casez (foo[25:21]) +\t 5\'h00 : +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 737""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 738""); +\t end +\t 5\'h01 : +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 739""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 740""); +\t end +\t 5\'h02 : +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 741""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 742""); +\t end +\t 5\'h03 : +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 743""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 744""); +\t end +\t 5\'h04 : +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 745""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 746""); +\t end +\t 5\'h05 : +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 747""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 748""); +\t end +\t 5\'h06 : +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 749""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 750""); +\t end +\t 5\'h07 : +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 751""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 752""); +\t end +\t 5\'h08 : +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 753""); +\t\tif (foo[ 6]) +\t\t $fwrite (fd,"" 754""); +\t\telse +\t\t $fwrite (fd,"" 755""); +\t end +\t 5\'h09 : +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 756""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 757""); +\t end +\t 5\'h0a : +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 758""); +\t\tozoneae(foo[17:15], fd); +\t end +\t 5\'h0b : +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 759""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 760""); +\t end +\t 5\'h0c : +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 761""); +\t end +\t 5\'h0d : +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 762""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 763""); +\t end +\t 5\'h0e : +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 764""); +\t\tozoneae(foo[17:15], fd); +\t end +\t 5\'h0f : +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 765""); +\t\tozoneae(foo[17:15], fd); +\t end +\t 5\'h10 : +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 766""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 767""); +\t end +\t 5\'h11 : +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 768""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 769""); +\t end +\t 5\'h18 : +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 770""); +\t\tif (foo[ 6]) +\t\t $fwrite (fd,"" 771""); +\t\telse +\t\t $fwrite (fd,"" 772""); +\t end +\t 5\'h1a : +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 773""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 774""); +\t end +\t 5\'h1b : +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 775""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 776""); +\t\tif (foo[ 6]) +\t\t $fwrite (fd,"" 777""); +\t\telse +\t\t $fwrite (fd,"" 778""); +\t\t$fwrite (fd,"" 779""); +\t end +\t 5\'h1c : +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 780""); +\t end +\t 5\'h1d : +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 781""); +\t\tif (foo[ 6]) +\t\t $fwrite (fd,"" 782""); +\t\telse +\t\t $fwrite (fd,"" 783""); +\t\t$fwrite (fd,"" 784""); +\t end +\t 5\'h1e : +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 785""); +\t\tif (foo[ 6]) +\t\t $fwrite (fd,"" 786""); +\t\telse +\t\t $fwrite (fd,"" 787""); +\t\t$fwrite (fd,"" 788""); +\t end +\t 5\'h1f : +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 789""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 790""); +\t\tif (foo[ 6]) +\t\t $fwrite (fd,"" 791""); +\t\telse +\t\t $fwrite (fd,"" 792""); +\t\t$fwrite (fd,"" 793""); +\t end +\t default : + $fwrite (fd,"" 794""); +\t endcase + end + endtask + + task ozonef3e; + input [ 31:0] foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin +\t case (foo[25:21]) +\t 5\'h00, +\t 5\'h01, +\t 5\'h02: +\t begin +\t\t ozoneae(foo[20:18], fd); +\t\t case (foo[22:21]) +\t\t 2\'h0: $fwrite (fd,"" 795""); +\t\t 2\'h1: $fwrite (fd,"" 796""); +\t\t 2\'h2: $fwrite (fd,"" 797""); +\t\t endcase +\t\t ozoneae(foo[17:15], fd); +\t\t $fwrite (fd,"" 798""); +\t\t if (foo[ 9]) +\t\t ozoneae(foo[ 8: 6], fd); +\t\t else +\t\t ozonef3e_te(foo[ 8: 6], fd); +\t\t $fwrite (fd,"" 799""); +\t end +\t 5\'h08, +\t 5\'h09, +\t 5\'h0d, +\t 5\'h0e, +\t 5\'h0f: +\t begin +\t\t ozoneae(foo[20:18], fd); +\t\t $fwrite (fd,"" 800""); +\t\t ozoneae(foo[17:15], fd); +\t\t case (foo[23:21]) +\t\t 3\'h0: $fwrite (fd,"" 801""); +\t\t 3\'h1: $fwrite (fd,"" 802""); +\t\t 3\'h5: $fwrite (fd,"" 803""); +\t\t 3\'h6: $fwrite (fd,"" 804""); +\t\t 3\'h7: $fwrite (fd,"" 805""); +\t\t endcase +\t\t if (foo[ 9]) +\t\t ozoneae(foo[ 8: 6], fd); +\t\t else +\t\t ozonef3e_te(foo[ 8: 6], fd); +\t end +\t 5\'h0a, +\t 5\'h0b: +\t begin +\t\t ozoneae(foo[17:15], fd); +\t\t if (foo[21]) +\t\t $fwrite (fd,"" 806""); +\t\t else +\t\t $fwrite (fd,"" 807""); +\t\t if (foo[ 9]) +\t\t ozoneae(foo[ 8: 6], fd); +\t\t else +\t\t ozonef3e_te(foo[ 8: 6], fd); +\t end +\t 5\'h0c: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 808""); +\t\tif (foo[ 9]) +\t\t ozoneae(foo[ 8: 6], fd); +\t\telse +\t\t ozonef3e_te(foo[ 8: 6], fd); +\t\t$fwrite (fd,"" 809""); +\t\tozoneae(foo[17:15], fd); +\t end +\t 5\'h10, +\t 5\'h11, +\t 5\'h12, +\t 5\'h13: +\t begin +\t\t ozoneae(foo[20:18], fd); +\t\t $fwrite (fd,"" 810""); +\t\t ozoneae(foo[17:15], fd); +\t\t case (foo[22:21]) +\t\t 2\'h0, +\t\t 2\'h2: +\t\t\t$fwrite (fd,"" 811""); +\t\t 2\'h1, +\t\t 2\'h3: +\t\t\t$fwrite (fd,"" 812""); +\t\t endcase +\t\t ozoneae(foo[ 8: 6], fd); +\t\t $fwrite (fd,"" 813""); +\t\t ozoneae((foo[20:18]+1), fd); +\t\t $fwrite (fd,"" 814""); +\t\t ozoneae((foo[17:15]+1), fd); +\t\t case (foo[22:21]) +\t\t 2\'h0, +\t\t 2\'h3: +\t\t\t$fwrite (fd,"" 815""); +\t\t 2\'h1, +\t\t 2\'h2: +\t\t\t$fwrite (fd,"" 816""); +\t\t endcase +\t\t ozoneae((foo[ 8: 6]+1), fd); +\t end +\t 5\'h18: +\t begin +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 817""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 818""); +\t\tozoneae(foo[ 8: 6], fd); +\t\t$fwrite (fd,"" 819""); +\t\tozoneae(foo[20:18], fd); +\t\t$fwrite (fd,"" 820""); +\t\tozoneae(foo[17:15], fd); +\t\t$fwrite (fd,"" 821""); +\t\tozoneae(foo[ 8: 6], fd); +\t end +\t default : + $fwrite (fd,"" 822""); +\t endcase + end + endtask + task ozonef3e_te; + input [ 2:0] te; + input [`FD_BITS] \tfd; + // verilator no_inline_task + begin +\t case (te) +\t 3\'b100 : $fwrite (fd, "" 823""); +\t 3\'b101 : $fwrite (fd, "" 824""); +\t 3\'b110 : $fwrite (fd, "" 825""); +\t default: $fwrite (fd, "" 826""); +\t endcase + end + endtask + task ozonearm; + input [ 2:0] ate; + input [`FD_BITS] \tfd; + // verilator no_inline_task + begin +\t case (ate) +\t 3\'b000 : $fwrite (fd, "" 827""); +\t 3\'b001 : $fwrite (fd, "" 828""); +\t 3\'b010 : $fwrite (fd, "" 829""); +\t 3\'b011 : $fwrite (fd, "" 830""); +\t 3\'b100 : $fwrite (fd, "" 831""); +\t 3\'b101 : $fwrite (fd, "" 832""); +\t 3\'b110 : $fwrite (fd, "" 833""); +\t 3\'b111 : $fwrite (fd, "" 834""); +\t endcase + end + endtask + task ozonebmuop; + input [ 4:0] f4; + input [`FD_BITS] fd; + // verilator no_inline_task + begin +\t case (f4[ 4:0]) +\t 5\'h00, +\t 5\'h04 : + $fwrite (fd, "" 835""); +\t 5\'h01, +\t 5\'h05 : + $fwrite (fd, "" 836""); +\t 5\'h02, +\t 5\'h06 : + $fwrite (fd, "" 837""); +\t 5\'h03, +\t 5\'h07 : + $fwrite (fd, "" 838""); +\t 5\'h08, +\t 5\'h18 : + $fwrite (fd, "" 839""); +\t 5\'h09, +\t 5\'h19 : + $fwrite (fd, "" 840""); +\t 5\'h0a, +\t 5\'h1a : + $fwrite (fd, "" 841""); +\t 5\'h0b : + $fwrite (fd, "" 842""); +\t 5\'h1b : + $fwrite (fd, "" 843""); +\t 5\'h0c, +\t 5\'h1c : + $fwrite (fd, "" 844""); +\t 5\'h0d, +\t 5\'h1d : + $fwrite (fd, "" 845""); +\t 5\'h1e : + $fwrite (fd, "" 846""); +\t endcase + end + endtask + task ozonef3; + input [ 31:0] foo; + input [`FD_BITS] fd; + reg \t\t nacho; + // verilator no_inline_task + begin : f3_body +\t nacho = 1\'b0; +\t case (foo[24:21]) +\t 4\'h0: + case (foo[26:25]) + 2\'b00 : $fwrite (fd, "" 847""); + 2\'b01 : $fwrite (fd, "" 848""); + 2\'b10 : $fwrite (fd, "" 849""); + 2\'b11 : $fwrite (fd, "" 850""); + endcase +\t 4\'h1: + case (foo[26:25]) + 2\'b00 : $fwrite (fd, "" 851""); + 2\'b01 : $fwrite (fd, "" 852""); + 2\'b10 : $fwrite (fd, "" 853""); + 2\'b11 : $fwrite (fd, "" 854""); + endcase +\t 4\'h2: + case (foo[26:25]) + 2\'b00 : $fwrite (fd, "" 855""); + 2\'b01 : $fwrite (fd, "" 856""); + 2\'b10 : $fwrite (fd, "" 857""); + 2\'b11 : $fwrite (fd, "" 858""); + endcase +\t 4\'h8, +\t 4\'h9, +\t 4\'hd, +\t 4\'he, +\t 4\'hf : + case (foo[26:25]) +\t\t 2\'b00 : $fwrite (fd, "" 859""); +\t\t 2\'b01 : $fwrite (fd, "" 860""); +\t\t 2\'b10 : $fwrite (fd, "" 861""); +\t\t 2\'b11 : $fwrite (fd, "" 862""); + endcase +\t 4\'ha, +\t 4\'hb : + if (foo[25]) +\t\t $fwrite (fd, "" 863""); + else +\t\t $fwrite (fd, "" 864""); +\t 4\'hc : + if (foo[26]) + $fwrite (fd, "" 865""); + else + $fwrite (fd, "" 866""); +\t default : +\t begin +\t\t$fwrite (fd, "" 867""); +\t\tnacho = 1\'b1; +\t end +\t endcase +\t if (~nacho) +\t begin +\t case (foo[24:21]) +\t\t4\'h8 : +\t\t $fwrite (fd, "" 868""); +\t\t4\'h9 : +\t\t $fwrite (fd, "" 869""); +\t\t4\'ha, +\t\t 4\'he : +\t\t $fwrite (fd, "" 870""); +\t\t4\'hb, +\t\t 4\'hf : +\t\t $fwrite (fd, "" 871""); +\t\t4\'hd : +\t\t $fwrite (fd, "" 872""); +\t endcase +\t if (foo[20]) +\t\tcase (foo[18:16]) +\t\t 3\'b000 : $fwrite (fd, "" 873""); +\t\t 3\'b100 : $fwrite (fd, "" 874""); +\t\t default: $fwrite (fd, "" 875""); +\t\tendcase +\t else +\t\tozoneae(foo[18:16], fd); +\t if (foo[24:21] === 4\'hc) +\t\tif (foo[25]) +\t\t $fwrite (fd, "" 876""); +\t\telse +\t\t $fwrite (fd, "" 877""); +\t case (foo[24:21]) +\t\t4\'h0, +\t\t 4\'h1, +\t\t 4\'h2: +\t\t $fwrite (fd, "" 878""); +\t endcase +\t end + end + endtask + task ozonerx; + input [ 31:0] foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin +\t case (foo[19:18]) +\t 2\'h0 : $fwrite (fd, "" 879""); +\t 2\'h1 : $fwrite (fd, "" 880""); +\t 2\'h2 : $fwrite (fd, "" 881""); +\t 2\'h3 : $fwrite (fd, "" 882""); +\t endcase +\t case (foo[17:16]) +\t 2\'h1 : $fwrite (fd, "" 883""); +\t 2\'h2 : $fwrite (fd, "" 884""); +\t 2\'h3 : $fwrite (fd, "" 885""); +\t endcase + end + endtask + task ozonerme; + input [ 2:0] rme; + input [`FD_BITS] fd; + // verilator no_inline_task + begin +\t case (rme) +\t 3\'h0 : $fwrite (fd, "" 886""); +\t 3\'h1 : $fwrite (fd, "" 887""); +\t 3\'h2 : $fwrite (fd, "" 888""); +\t 3\'h3 : $fwrite (fd, "" 889""); +\t 3\'h4 : $fwrite (fd, "" 890""); +\t 3\'h5 : $fwrite (fd, "" 891""); +\t 3\'h6 : $fwrite (fd, "" 892""); +\t 3\'h7 : $fwrite (fd, "" 893""); +\t endcase + end + endtask + task ozoneye; + input [5:0] ye; + input \t l; + input [`FD_BITS] fd; + // verilator no_inline_task + begin +\t $fwrite (fd, "" 894""); +\t ozonerme(ye[5:3], fd); +\t case ({ye[ 2:0], l}) +\t 4\'h2, +\t 4\'ha: $fwrite (fd, "" 895""); +\t 4\'h4, +\t 4\'hb: $fwrite (fd, "" 896""); +\t 4\'h6, +\t 4\'he: $fwrite (fd, "" 897""); +\t 4\'h8, +\t 4\'hc: $fwrite (fd, "" 898""); +\t endcase + end + endtask + task ozonef1e_ye; + input [5:0] ye; + input \t l; + input [`FD_BITS] fd; + // verilator no_inline_task + begin +\t $fwrite (fd, "" 899""); +\t ozonerme(ye[5:3], fd); +\t ozonef1e_inc_dec(ye[5:0], l , fd); + end + endtask + task ozonef1e_h; + input [ 2:0] e; + input [`FD_BITS] fd; + // verilator no_inline_task + begin +\t if (e[ 2:0] <= 3\'h4) +\t $fwrite (fd, "" 900""); + end + endtask + task ozonef1e_inc_dec; + input [5:0] ye; + input \t l; + input [`FD_BITS] fd; + // verilator no_inline_task + begin +\t case ({ye[ 2:0], l}) +\t 4\'h2, +\t 4\'h3, +\t 4\'ha: $fwrite (fd, "" 901""); +\t 4\'h4, +\t 4\'h5, +\t 4\'hb: $fwrite (fd, "" 902""); +\t 4\'h6, +\t 4\'h7, +\t 4\'he: $fwrite (fd, "" 903""); +\t 4\'h8, +\t 4\'h9, +\t 4\'hc: $fwrite (fd, "" 904""); +\t 4\'hf: $fwrite (fd, "" 905""); +\t endcase + end + endtask + task ozonef1e_hl; + input [ 2:0] e; + input l; + input [`FD_BITS] fd; + // verilator no_inline_task + begin +\t case ({e[ 2:0], l}) +\t 4\'h0, +\t 4\'h2, +\t 4\'h4, +\t 4\'h6, +\t 4\'h8: $fwrite (fd, "" 906""); +\t 4\'h1, +\t 4\'h3, +\t 4\'h5, +\t 4\'h7, +\t 4\'h9: $fwrite (fd, "" 907""); +\t endcase + end + endtask + task ozonexe; + input [ 3:0] xe; + input [`FD_BITS] fd; + // verilator no_inline_task + begin +\t case (xe[3]) +\t 1\'b0 : $fwrite (fd, "" 908""); +\t 1\'b1 : $fwrite (fd, "" 909""); +\t endcase +\t case (xe[ 2:0]) +\t 3\'h1, +\t 3\'h5: $fwrite (fd, "" 910""); +\t 3\'h2, +\t 3\'h6: $fwrite (fd, "" 911""); +\t 3\'h3, +\t 3\'h7: $fwrite (fd, "" 912""); +\t 3\'h4: $fwrite (fd, "" 913""); +\t endcase + end + endtask + task ozonerp; + input [ 2:0] rp; + input [`FD_BITS] fd; + // verilator no_inline_task + begin +\t case (rp) +\t 3\'h0 : $fwrite (fd, "" 914""); +\t 3\'h1 : $fwrite (fd, "" 915""); +\t 3\'h2 : $fwrite (fd, "" 916""); +\t 3\'h3 : $fwrite (fd, "" 917""); +\t 3\'h4 : $fwrite (fd, "" 918""); +\t 3\'h5 : $fwrite (fd, "" 919""); +\t 3\'h6 : $fwrite (fd, "" 920""); +\t 3\'h7 : $fwrite (fd, "" 921""); +\t endcase + end + endtask + task ozonery; + input [ 3:0] ry; + input [`FD_BITS] fd; + // verilator no_inline_task + begin +\t case (ry) +\t 4\'h0 : $fwrite (fd, "" 922""); +\t 4\'h1 : $fwrite (fd, "" 923""); +\t 4\'h2 : $fwrite (fd, "" 924""); +\t 4\'h3 : $fwrite (fd, "" 925""); +\t 4\'h4 : $fwrite (fd, "" 926""); +\t 4\'h5 : $fwrite (fd, "" 927""); +\t 4\'h6 : $fwrite (fd, "" 928""); +\t 4\'h7 : $fwrite (fd, "" 929""); +\t 4\'h8 : $fwrite (fd, "" 930""); +\t 4\'h9 : $fwrite (fd, "" 931""); +\t 4\'ha : $fwrite (fd, "" 932""); +\t 4\'hb : $fwrite (fd, "" 933""); +\t 4\'hc : $fwrite (fd, "" 934""); +\t 4\'hd : $fwrite (fd, "" 935""); +\t 4\'he : $fwrite (fd, "" 936""); +\t 4\'hf : $fwrite (fd, "" 937""); +\t endcase + end + endtask + task ozonearx; + input [ 15:0] foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin +\t case (foo[1:0]) +\t 2\'h0 : $fwrite (fd, "" 938""); +\t 2\'h1 : $fwrite (fd, "" 939""); +\t 2\'h2 : $fwrite (fd, "" 940""); +\t 2\'h3 : $fwrite (fd, "" 941""); +\t endcase + end + endtask + task ozonef3f4imop; + input [ 4:0] f3f4iml; + input [`FD_BITS] fd; + // verilator no_inline_task + begin +\t casez (f3f4iml) +\t 5\'b000??: $fwrite (fd, "" 942""); +\t 5\'b001??: $fwrite (fd, "" 943""); +\t 5\'b?10??: $fwrite (fd, "" 944""); +\t 5\'b0110?: $fwrite (fd, "" 945""); +\t 5\'b01110: $fwrite (fd, "" 946""); +\t 5\'b01111: $fwrite (fd, "" 947""); +\t 5\'b10???: $fwrite (fd, "" 948""); +\t 5\'b11100: $fwrite (fd, "" 949""); +\t 5\'b11101: $fwrite (fd, "" 950""); +\t 5\'b11110: $fwrite (fd, "" 951""); +\t 5\'b11111: $fwrite (fd, "" 952""); +\t endcase + end + endtask + task ozonecon; + input [ 4:0] con; + input [`FD_BITS] fd; + // verilator no_inline_task + begin +\t case (con) +\t 5\'h00 : $fwrite (fd, "" 953""); +\t 5\'h01 : $fwrite (fd, "" 954""); +\t 5\'h02 : $fwrite (fd, "" 955""); +\t 5\'h03 : $fwrite (fd, "" 956""); +\t 5\'h04 : $fwrite (fd, "" 957""); +\t 5\'h05 : $fwrite (fd, "" 958""); +\t 5\'h06 : $fwrite (fd, "" 959""); +\t 5\'h07 : $fwrite (fd, "" 960""); +\t 5\'h08 : $fwrite (fd, "" 961""); +\t 5\'h09 : $fwrite (fd, "" 962""); +\t 5\'h0a : $fwrite (fd, "" 963""); +\t 5\'h0b : $fwrite (fd, "" 964""); +\t 5\'h0c : $fwrite (fd, "" 965""); +\t 5\'h0d : $fwrite (fd, "" 966""); +\t 5\'h0e : $fwrite (fd, "" 967""); +\t 5\'h0f : $fwrite (fd, "" 968""); +\t 5\'h10 : $fwrite (fd, "" 969""); +\t 5\'h11 : $fwrite (fd, "" 970""); +\t 5\'h12 : $fwrite (fd, "" 971""); +\t 5\'h13 : $fwrite (fd, "" 972""); +\t 5\'h14 : $fwrite (fd, "" 973""); +\t 5\'h15 : $fwrite (fd, "" 974""); +\t 5\'h16 : $fwrite (fd, "" 975""); +\t 5\'h17 : $fwrite (fd, "" 976""); +\t 5\'h18 : $fwrite (fd, "" 977""); +\t 5\'h19 : $fwrite (fd, "" 978""); +\t 5\'h1a : $fwrite (fd, "" 979""); +\t 5\'h1b : $fwrite (fd, "" 980""); +\t 5\'h1c : $fwrite (fd, "" 981""); +\t 5\'h1d : $fwrite (fd, "" 982""); +\t 5\'h1e : $fwrite (fd, "" 983""); +\t 5\'h1f : $fwrite (fd, "" 984""); +\t endcase + end + endtask + task ozonedr; + input [ 15:0] foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin +\t case (foo[ 9: 6]) +\t 4\'h0 : $fwrite (fd, "" 985""); +\t 4\'h1 : $fwrite (fd, "" 986""); +\t 4\'h2 : $fwrite (fd, "" 987""); +\t 4\'h3 : $fwrite (fd, "" 988""); +\t 4\'h4 : $fwrite (fd, "" 989""); +\t 4\'h5 : $fwrite (fd, "" 990""); +\t 4\'h6 : $fwrite (fd, "" 991""); +\t 4\'h7 : $fwrite (fd, "" 992""); +\t 4\'h8 : $fwrite (fd, "" 993""); +\t 4\'h9 : $fwrite (fd, "" 994""); +\t 4\'ha : $fwrite (fd, "" 995""); +\t 4\'hb : $fwrite (fd, "" 996""); +\t 4\'hc : $fwrite (fd, "" 997""); +\t 4\'hd : $fwrite (fd, "" 998""); +\t 4\'he : $fwrite (fd, "" 999""); +\t 4\'hf : $fwrite (fd, "" 1000""); +\t endcase + end + endtask + task ozoneshift; + input [ 15:0] foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin +\t case (foo[ 4: 3]) +\t 2\'h0 : $fwrite (fd, "" 1001""); +\t 2\'h1 : $fwrite (fd, "" 1002""); +\t 2\'h2 : $fwrite (fd, "" 1003""); +\t 2\'h3 : $fwrite (fd, "" 1004""); +\t endcase + end + endtask + task ozoneacc; + input foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin +\t case (foo) +\t 2\'h0 : $fwrite (fd, "" 1005""); +\t 2\'h1 : $fwrite (fd, "" 1006""); +\t endcase + end + endtask + task ozonehl; + input foo; + input [`FD_BITS] fd; + // verilator no_inline_task + begin +\t case (foo) +\t 2\'h0 : $fwrite (fd, "" 1007""); +\t 2\'h1 : $fwrite (fd, "" 1008""); +\t endcase + end + endtask + task dude; + input [`FD_BITS] fd; + // verilator no_inline_task + $fwrite(fd,"" dude""); + endtask + + task big_case; + input [ `FD_BITS] fd; + input [ 31:0] foo; + // verilator no_inline_task + begin +\t $fwrite(fd,"" 1009""); +\t if (&foo === 1\'bx) +\t $fwrite(fd, "" 1010""); +\t else +\t casez ( {foo[31:26], foo[19:15], foo[5:0]} ) + 17\'b00_111?_?_????_??_???? : + begin +\t\t ozonef1(foo, fd); +\t\t $fwrite (fd, "" 1011""); +\t\t ozoneacc(~foo[26], fd); +\t\t ozonehl(foo[20], fd); +\t\t $fwrite (fd, "" 1012""); +\t\t ozonerx(foo, fd); +\t\t dude(fd); +\t\t $fwrite (fd, "" 1013""); + end + 17\'b01_001?_?_????_??_???? : + begin +\t\t ozonef1(foo, fd); +\t\t $fwrite (fd, "" 1014""); +\t\t ozonerx(foo, fd); +\t\t $fwrite (fd, "" 1015""); +\t\t $fwrite (fd, "" 1016:%x"", foo[20]); +\t\t ozonehl(foo[20], fd); +\t\t dude(fd); +\t\t $fwrite (fd, "" 1017""); + end + 17\'b10_100?_?_????_??_???? : + begin +\t\t ozonef1(foo, fd); +\t\t $fwrite (fd, "" 1018""); +\t\t ozonerx(foo, fd); +\t\t $fwrite (fd, "" 1019""); +\t\t $fwrite (fd, "" 1020""); +\t\t ozonehl(foo[20], fd); +\t\t dude(fd); +\t\t $fwrite (fd, "" 1021""); + end + 17\'b10_101?_?_????_??_???? : + begin +\t\t ozonef1(foo, fd); +\t\t $fwrite (fd, "" 1022""); +\t\t if (foo[20]) +\t\t begin +\t\t $fwrite (fd, "" 1023""); +\t\t ozoneacc(foo[18], fd); +\t\t $fwrite (fd, "" 1024""); +\t\t $fwrite (fd, "" 1025""); +\t\t if (foo[19]) +\t\t\t $fwrite (fd, "" 1026""); +\t\t else +\t\t\t $fwrite (fd, "" 1027""); +\t\t end +\t\t else +\t\t ozonerx(foo, fd); +\t\t dude(fd); +\t\t $fwrite (fd, "" 1028""); + end + 17\'b10_110?_?_????_??_???? : + begin +\t\t ozonef1(foo, fd); +\t\t $fwrite (fd, "" 1029""); +\t\t $fwrite (fd, "" 1030""); +\t\t ozonehl(foo[20], fd); +\t\t $fwrite (fd, "" 1031""); +\t\t ozonerx(foo, fd); +\t\t dude(fd); +\t\t $fwrite (fd, "" 1032""); + end + 17\'b10_111?_?_????_??_???? : + begin +\t\t ozonef1(foo, fd); +\t\t $fwrite (fd, "" 1033""); +\t\t $fwrite (fd, "" 1034""); +\t\t ozonehl(foo[20], fd); +\t\t $fwrite (fd, "" 1035""); +\t\t ozonerx(foo, fd); +\t\t dude(fd); +\t\t $fwrite (fd, "" 1036""); + end + 17\'b11_001?_?_????_??_???? : + begin +\t\t ozonef1(foo, fd); +\t\t $fwrite (fd, "" 1037""); +\t\t ozonerx(foo, fd); +\t\t $fwrite (fd, "" 1038""); +\t\t $fwrite (fd, "" 1039""); +\t\t ozonehl(foo[20], fd); +\t\t dude(fd); +\t\t $fwrite (fd, "" 1040""); + end + 17\'b11_111?_?_????_??_???? : + begin +\t\t ozonef1(foo, fd); +\t\t $fwrite (fd, "" 1041""); +\t\t $fwrite (fd, "" 1042""); +\t\t ozonerx(foo, fd); +\t\t $fwrite (fd, "" 1043""); +\t\t if (foo[20]) +\t\t $fwrite (fd, "" 1044""); +\t\t else +\t\t $fwrite (fd, "" 1045""); +\t\t dude(fd); +\t\t $fwrite (fd, "" 1046""); + end + 17\'b00_10??_?_????_?1_1111 : + casez (foo[11: 5]) +\t\t 7\'b??_0_010_0: +\t\t begin +\t\t $fwrite (fd, "" 1047""); +\t\t ozonecon(foo[14:10], fd); +\t\t $fwrite (fd, "" 1048""); +\t\t ozonef1e(foo, fd); +\t\t dude(fd); +\t\t $fwrite (fd, "" 1049""); +\t\t end +\t\t 7\'b00_?_110_?: +\t\t begin +\t\t ozonef1e(foo, fd); +\t\t $fwrite (fd, "" 1050""); +\t\t case ({foo[ 9],foo[ 5]}) +\t\t\t2\'b00: +\t\t\t begin +\t\t\t $fwrite (fd, "" 1051""); +\t\t\t ozoneae(foo[14:12], fd); +\t\t\t ozonehl(foo[ 5], fd); +\t\t\t end +\t\t\t2\'b01: +\t\t\t begin +\t\t\t $fwrite (fd, "" 1052""); +\t\t\t ozoneae(foo[14:12], fd); +\t\t\t ozonehl(foo[ 5], fd); +\t\t\t end +\t\t\t2\'b10: +\t\t\t begin +\t\t\t $fwrite (fd, "" 1053""); +\t\t\t ozoneae(foo[14:12], fd); +\t\t\t end +\t\t\t2\'b11: $fwrite (fd, "" 1054""); +\t\t endcase +\t\t dude(fd); +\t\t $fwrite (fd, "" 1055""); +\t\t end +\t\t 7\'b01_?_110_?: +\t\t begin +\t\t ozonef1e(foo, fd); +\t\t $fwrite (fd, "" 1056""); +\t\t case ({foo[ 9],foo[ 5]}) +\t\t\t2\'b00: +\t\t\t begin +\t\t\t ozoneae(foo[14:12], fd); +\t\t\t ozonehl(foo[ 5], fd); +\t\t\t $fwrite (fd, "" 1057""); +\t\t\t end +\t\t\t2\'b01: +\t\t\t begin +\t\t\t ozoneae(foo[14:12], fd); +\t\t\t ozonehl(foo[ 5], fd); +\t\t\t $fwrite (fd, "" 1058""); +\t\t\t end +\t\t\t2\'b10: +\t\t\t begin +\t\t\t ozoneae(foo[14:12], fd); +\t\t\t $fwrite (fd, "" 1059""); +\t\t\t end +\t\t\t2\'b11: $fwrite (fd, "" 1060""); +\t\t endcase +\t\t dude(fd); +\t\t $fwrite (fd, "" 1061""); +\t\t end +\t\t 7\'b10_0_110_0: +\t\t begin +\t\t ozonef1e(foo, fd); +\t\t $fwrite (fd, "" 1062""); +\t\t $fwrite (fd, "" 1063""); +\t\t if (foo[12]) +\t\t\t$fwrite (fd, "" 1064""); +\t\t else +\t\t\tozonerab({4\'b1001, foo[14:12]}, fd); +\t\t dude(fd); +\t\t $fwrite (fd, "" 1065""); +\t\t end +\t\t 7\'b10_0_110_1: +\t\t begin +\t\t ozonef1e(foo, fd); +\t\t $fwrite (fd, "" 1066""); +\t\t if (foo[12]) +\t\t\t$fwrite (fd, "" 1067""); +\t\t else +\t\t\tozonerab({4\'b1001, foo[14:12]}, fd); +\t\t $fwrite (fd, "" 1068""); +\t\t dude(fd); +\t\t $fwrite (fd, "" 1069""); +\t\t end +\t\t 7\'b??_?_000_?: +\t\t begin +\t\t ozonef1e(foo, fd); +\t\t $fwrite (fd, "" 1070""); +\t\t $fwrite (fd, "" 1071""); +\t\t ozonef1e_hl(foo[11:9],foo[ 5], fd); +\t\t $fwrite (fd, "" 1072""); +\t\t ozonef1e_ye(foo[14:9],foo[ 5], fd); +\t\t dude(fd); +\t\t $fwrite (fd, "" 1073""); +\t\t end +\t\t 7\'b??_?_100_?: +\t\t begin +\t\t ozonef1e(foo, fd); +\t\t $fwrite (fd, "" 1074""); +\t\t $fwrite (fd, "" 1075""); +\t\t ozonef1e_hl(foo[11:9],foo[ 5], fd); +\t\t $fwrite (fd, "" 1076""); +\t\t ozonef1e_ye(foo[14:9],foo[ 5], fd); +\t\t dude(fd); +\t\t $fwrite (fd, "" 1077""); +\t\t end +\t\t 7\'b??_?_001_?: +\t\t begin +\t\t ozonef1e(foo, fd); +\t\t $fwrite (fd, "" 1078""); +\t\t ozonef1e_ye(foo[14:9],foo[ 5], fd); +\t\t $fwrite (fd, "" 1079""); +\t\t $fwrite (fd, "" 1080""); +\t\t ozonef1e_hl(foo[11:9],foo[ 5], fd); +\t\t dude(fd); +\t\t $fwrite (fd, "" 1081""); +\t\t end +\t\t 7\'b??_?_011_?: +\t\t begin +\t\t ozonef1e(foo, fd); +\t\t $fwrite (fd, "" 1082""); +\t\t ozonef1e_ye(foo[14:9],foo[ 5], fd); +\t\t $fwrite (fd, "" 1083""); +\t\t $fwrite (fd, "" 1084""); +\t\t ozonef1e_hl(foo[11:9],foo[ 5], fd); +\t\t dude(fd); +\t\t $fwrite (fd, "" 1085""); +\t\t end +\t\t 7\'b??_?_101_?: +\t\t begin +\t\t ozonef1e(foo, fd); +\t\t $fwrite (fd, "" 1086""); +\t\t ozonef1e_ye(foo[14:9],foo[ 5], fd); +\t\t dude(fd); +\t\t $fwrite (fd, "" 1087""); +\t\t end + endcase + 17\'b00_10??_?_????_?0_0110 : + begin +\t\t ozonef1e(foo, fd); +\t\t $fwrite (fd, "" 1088""); +\t\t ozoneae(foo[ 8: 6], fd); +\t\t ozonef1e_hl(foo[11:9],foo[ 5], fd); +\t\t $fwrite (fd, "" 1089""); +\t\t ozonef1e_ye(foo[14:9],foo[ 5], fd); +\t\t dude(fd); +\t\t $fwrite (fd, "" 1090""); + end + 17\'b00_10??_?_????_00_0111 : + begin +\t\t ozonef1e(foo, fd); +\t\t $fwrite (fd, "" 1091""); +\t\t if (foo[ 6]) +\t\t $fwrite (fd, "" 1092""); +\t\t else +\t\t ozonerab({4\'b1001, foo[ 8: 6]}, fd); +\t\t $fwrite (fd, "" 1093""); +\t\t $fwrite (fd, "" 1094""); +\t\t ozonerme(foo[14:12], fd); +\t\t case (foo[11: 9]) +\t\t 3\'h2, +\t\t 3\'h5, +\t\t 3\'h6, +\t\t 3\'h7: +\t\t\tozonef1e_inc_dec(foo[14:9],1\'b0, fd); +\t\t 3\'h1, +\t\t 3\'h3, +\t\t 3\'h4: +\t\t\t$fwrite (fd, "" 1095""); +\t\t endcase +\t\t dude(fd); +\t\t $fwrite (fd, "" 1096""); + end + 17\'b00_10??_?_????_?0_0100 : + begin +\t\t ozonef1e(foo, fd); +\t\t $fwrite (fd, "" 1097""); +\t\t ozonef1e_ye(foo[14:9],foo[ 5], fd); +\t\t $fwrite (fd, "" 1098""); +\t\t ozoneae(foo[ 8: 6], fd); +\t\t ozonef1e_hl(foo[11:9],foo[ 5], fd); +\t\t dude(fd); +\t\t $fwrite (fd, "" 1099""); + end + 17\'b00_10??_?_????_10_0111 : + begin +\t\t ozonef1e(foo, fd); +\t\t $fwrite (fd, "" 1100""); +\t\t $fwrite (fd, "" 1101""); +\t\t ozonerme(foo[14:12], fd); +\t\t case (foo[11: 9]) +\t\t 3\'h2, +\t\t 3\'h5, +\t\t 3\'h6, +\t\t 3\'h7: +\t\t\tozonef1e_inc_dec(foo[14:9],1\'b0, fd); +\t\t 3\'h1, +\t\t 3\'h3, +\t\t 3\'h4: +\t\t\t$fwrite (fd, "" 1102""); +\t\t endcase +\t\t $fwrite (fd, "" 1103""); +\t\t if (foo[ 6]) +\t\t $fwrite (fd, "" 1104""); +\t\t else +\t\t ozonerab({4\'b1001, foo[ 8: 6]}, fd); +\t\t dude(fd); +\t\t $fwrite (fd, "" 1105""); + end + 17\'b00_10??_?_????_?0_1110 : + begin +\t\t ozonef1e(foo, fd); +\t\t $fwrite (fd, "" 1106""); +\t\t case (foo[11:9]) +\t\t 3\'h2: +\t\t begin +\t\t\t $fwrite (fd, "" 1107""); +\t\t\t if (foo[14:12] == 3\'h0) +\t\t\t $fwrite (fd, "" 1108""); +\t\t\t else +\t\t\t ozonerme(foo[14:12], fd); +\t\t\t $fwrite (fd, "" 1109""); +\t\t end +\t\t 3\'h6: +\t\t begin +\t\t\t $fwrite (fd, "" 1110""); +\t\t\t if (foo[14:12] == 3\'h0) +\t\t\t $fwrite (fd, "" 1111""); +\t\t\t else +\t\t\t ozonerme(foo[14:12], fd); +\t\t\t $fwrite (fd, "" 1112""); +\t\t end +\t\t 3\'h0: +\t\t begin +\t\t\t $fwrite (fd, "" 1113""); +\t\t\t if (foo[14:12] == 3\'h0) +\t\t\t $fwrite (fd, "" 1114""); +\t\t\t else +\t\t\t ozonerme(foo[14:12], fd); +\t\t\t $fwrite (fd, "" 1115""); +\t\t\t if (foo[ 7: 5] >= 3\'h5) +\t\t\t $fwrite (fd, "" 1116""); +\t\t\t else +\t\t\t ozonexe(foo[ 8: 5], fd); +\t\t end +\t\t 3\'h1: +\t\t begin +\t\t\t $fwrite (fd, "" 1117""); +\t\t\t if (foo[14:12] == 3\'h0) +\t\t\t $fwrite (fd, "" 1118""); +\t\t\t else +\t\t\t ozonerme(foo[14:12], fd); +\t\t\t $fwrite (fd, "" 1119""); +\t\t\t if (foo[ 7: 5] >= 3\'h5) +\t\t\t $fwrite (fd, "" 1120""); +\t\t\t else +\t\t\t ozonexe(foo[ 8: 5], fd); +\t\t end +\t\t 3\'h4: +\t\t begin +\t\t\t $fwrite (fd, "" 1121""); +\t\t\t if (foo[14:12] == 3\'h0) +\t\t\t $fwrite (fd, "" 1122""); +\t\t\t else +\t\t\t ozonerme(foo[14:12], fd); +\t\t\t $fwrite (fd, "" 1123""); +\t\t\t if (foo[ 7: 5] >= 3\'h5) +\t\t\t $fwrite (fd, "" 1124""); +\t\t\t else +\t\t\t ozonexe(foo[ 8: 5], fd); +\t\t end +\t\t 3\'h5: +\t\t begin +\t\t\t $fwrite (fd, "" 1125""); +\t\t\t if (foo[14:12] == 3\'h0) +\t\t\t $fwrite (fd, "" 1126""); +\t\t\t else +\t\t\t ozonerme(foo[14:12], fd); +\t\t\t $fwrite (fd, "" 1127""); +\t\t\t if (foo[ 7: 5] >= 3\'h5) +\t\t\t $fwrite (fd, "" 1128""); +\t\t\t else +\t\t\t ozonexe(foo[ 8: 5], fd); +\t\t end +\t\t endcase +\t\t dude(fd); +\t\t $fwrite (fd, "" 1129""); + end + 17\'b00_10??_?_????_?0_1111 : + casez (foo[14: 9]) +\t\t 6\'b001_10_?: +\t\t begin +\t\t ozonef1e(foo, fd); +\t\t $fwrite (fd, "" 1130""); +\t\t $fwrite (fd, "" 1131""); +\t\t ozonef1e_hl(foo[ 7: 5],foo[ 9], fd); +\t\t $fwrite (fd, "" 1132""); +\t\t ozonexe(foo[ 8: 5], fd); +\t\t dude(fd); +\t\t $fwrite (fd, "" 1133""); +\t\t end +\t\t 6\'b???_11_?: +\t\t begin +\t\t ozonef1e(foo, fd); +\t\t $fwrite (fd, "" 1134""); +\t\t ozoneae(foo[14:12], fd); +\t\t ozonef1e_hl(foo[ 7: 5],foo[ 9], fd); +\t\t $fwrite (fd, "" 1135""); +\t\t ozonexe(foo[ 8: 5], fd); +\t\t dude(fd); +\t\t $fwrite (fd, "" 1136""); +\t\t end +\t\t 6\'b000_10_1, +\t\t 6\'b010_10_1, +\t\t 6\'b100_10_1, +\t\t 6\'b110_10_1: +\t\t begin +\t\t\tozonef1e(foo, fd); +\t\t\t$fwrite (fd, "" 1137""); +\t\t\tozonerab({4\'b1001, foo[14:12]}, fd); +\t\t\t$fwrite (fd, "" 1138""); +\t\t\tif ((foo[ 7: 5] >= 3\'h1) & (foo[ 7: 5] <= 3\'h3)) +\t\t\t $fwrite (fd, "" 1139""); +\t\t\telse +\t\t\t ozonexe(foo[ 8: 5], fd); +\t\t\tdude(fd); +\t\t\t$fwrite (fd, "" 1140""); +\t\t end +\t\t 6\'b000_10_0, +\t\t 6\'b010_10_0, +\t\t 6\'b100_10_0, +\t\t 6\'b110_10_0: +\t\t begin +\t\t\tozonef1e(foo, fd); +\t\t\t$fwrite (fd, "" 1141""); +\t\t\t$fwrite (fd, "" 1142""); +\t\t\tozonerab({4\'b1001, foo[14:12]}, fd); +\t\t\t$fwrite (fd, "" 1143""); +\t\t\t$fwrite (fd, "" 1144""); +\t\t\tozonef1e_h(foo[ 7: 5], fd); +\t\t\t$fwrite (fd, "" 1145""); +\t\t\tozonexe(foo[ 8: 5], fd); +\t\t\tdude(fd); +\t\t\t$fwrite (fd, "" 1146""); +\t\t end +\t\t 6\'b???_00_?: +\t\t begin +\t\t ozonef1e(foo, fd); +\t\t $fwrite (fd, "" 1147""); +\t\t if (foo[ 9]) +\t\t\tbegin +\t\t\t $fwrite (fd, "" 1148""); +\t\t\t ozoneae(foo[14:12], fd); +\t\t\tend +\t\t else +\t\t\tbegin +\t\t\t $fwrite (fd, "" 1149""); +\t\t\t ozoneae(foo[14:12], fd); +\t\t\t $fwrite (fd, "" 1150""); +\t\t\tend +\t\t $fwrite (fd, "" 1151""); +\t\t $fwrite (fd, "" 1152""); +\t\t ozonef1e_h(foo[ 7: 5], fd); +\t\t $fwrite (fd, "" 1153""); +\t\t ozonexe(foo[ 8: 5], fd); +\t\t dude(fd); +\t\t $fwrite (fd, "" 1154""); +\t\t end +\t\t 6\'b???_01_?: +\t\t begin +\t\t ozonef1e(foo, fd); +\t\t $fwrite (fd, "" 1155""); +\t\t ozoneae(foo[14:12], fd); +\t\t if (foo[ 9]) +\t\t\t$fwrite (fd, "" 1156""); +\t\t else +\t\t\t$fwrite (fd, "" 1157""); +\t\t $fwrite (fd, "" 1158""); +\t\t $fwrite (fd, "" 1159""); +\t\t ozonef1e_h(foo[ 7: 5], fd); +\t\t $fwrite (fd, "" 1160""); +\t\t ozonexe(foo[ 8: 5], fd); +\t\t dude(fd); +\t\t $fwrite (fd, "" 1161""); +\t\t end +\t\t 6\'b011_'b'10_0: +\t\t begin +\t\t ozonef1e(foo, fd); +\t\t $fwrite (fd, "" 1162""); +\t\t case (foo[ 8: 5]) +\t\t\t4\'h0: $fwrite (fd, "" 1163""); +\t\t\t4\'h1: $fwrite (fd, "" 1164""); +\t\t\t4\'h2: $fwrite (fd, "" 1165""); +\t\t\t4\'h3: $fwrite (fd, "" 1166""); +\t\t\t4\'h4: $fwrite (fd, "" 1167""); +\t\t\t4\'h5: $fwrite (fd, "" 1168""); +\t\t\t4\'h8: $fwrite (fd, "" 1169""); +\t\t\t4\'h9: $fwrite (fd, "" 1170""); +\t\t\t4\'ha: $fwrite (fd, "" 1171""); +\t\t\t4\'hb: $fwrite (fd, "" 1172""); +\t\t\t4\'hc: $fwrite (fd, "" 1173""); +\t\t\t4\'hd: $fwrite (fd, "" 1174""); +\t\t\tdefault: $fwrite (fd, "" 1175""); +\t\t endcase +\t\t dude(fd); +\t\t $fwrite (fd, "" 1176""); +\t\t end +\t\t default: $fwrite (fd, "" 1177""); + endcase + 17\'b00_10??_?_????_?0_110? : + begin +\t\t ozonef1e(foo, fd); +\t\t $fwrite (fd, "" 1178""); +\t\t $fwrite (fd, "" 1179""); +\t\t ozonef1e_hl(foo[11:9], foo[0], fd); +\t\t $fwrite (fd, "" 1180""); +\t\t ozonef1e_ye(foo[14:9],1\'b0, fd); +\t\t $fwrite (fd, "" 1181""); +\t\t ozonef1e_h(foo[ 7: 5], fd); +\t\t $fwrite (fd, "" 1182""); +\t\t ozonexe(foo[ 8: 5], fd); +\t\t dude(fd); +\t\t $fwrite (fd, "" 1183""); + end + 17\'b00_10??_?_????_?1_110? : + begin +\t\t ozonef1e(foo, fd); +\t\t $fwrite (fd, "" 1184""); +\t\t $fwrite (fd, "" 1185""); +\t\t ozonef1e_hl(foo[11:9],foo[0], fd); +\t\t $fwrite (fd, "" 1186""); +\t\t ozonef1e_ye(foo[14:9],foo[ 0], fd); +\t\t $fwrite (fd, "" 1187""); +\t\t $fwrite (fd, "" 1188""); +\t\t ozonef1e_h(foo[ 7: 5], fd); +\t\t $fwrite (fd, "" 1189""); +\t\t ozonexe(foo[ 8: 5], fd); +\t\t dude(fd); +\t\t $fwrite (fd, "" 1190""); + end + 17\'b00_10??_?_????_?0_101? : + begin +\t\t ozonef1e(foo, fd); +\t\t $fwrite (fd, "" 1191""); +\t\t ozonef1e_ye(foo[14:9],foo[ 0], fd); +\t\t $fwrite (fd, "" 1192""); +\t\t $fwrite (fd, "" 1193""); +\t\t ozonef1e_hl(foo[11:9],foo[0], fd); +\t\t $fwrite (fd, "" 1194""); +\t\t $fwrite (fd, "" 1195""); +\t\t ozonef1e_h(foo[ 7: 5], fd); +\t\t $fwrite (fd, "" 1196""); +\t\t ozonexe(foo[ 8: 5], fd); +\t\t dude(fd); +\t\t $fwrite (fd, "" 1197""); + end + 17\'b00_10??_?_????_?0_1001 : + begin +\t\t ozonef1e(foo, fd); +\t\t $fwrite (fd, "" 1198""); +\t\t $fwrite (fd, "" 1199""); +\t\t ozonef1e_h(foo[11:9], fd); +\t\t $fwrite (fd, "" 1200""); +\t\t ozonef1e_ye(foo[14:9],1\'b0, fd); +\t\t $fwrite (fd, "" 1201""); +\t\t case (foo[ 7: 5]) +\t\t 3\'h1, +\t\t 3\'h2, +\t\t 3\'h3: +\t\t\t$fwrite (fd, "" 1202""); +\t\t default: +\t\t begin +\t\t\t $fwrite (fd, "" 1203""); +\t\t\t $fwrite (fd, "" 1204""); +\t\t\t ozonexe(foo[ 8: 5], fd); +\t\t end +\t\t endcase +\t\t dude(fd); +\t\t $fwrite (fd, "" 1205""); + end + 17\'b00_10??_?_????_?0_0101 : + begin +\t\t ozonef1e(foo, fd); +\t\t $fwrite (fd, "" 1206""); +\t\t case (foo[11: 9]) +\t\t 3\'h1, +\t\t 3\'h3, +\t\t 3\'h4: +\t\t\t$fwrite (fd, "" 1207""); +\t\t default: +\t\t begin +\t\t\t ozonef1e_ye(foo[14:9],1\'b0, fd); +\t\t\t $fwrite (fd, "" 1208""); +\t\t\t $fwrite (fd, "" 1209""); +\t\t end +\t\t endcase +\t\t $fwrite (fd, "" 1210""); +\t\t $fwrite (fd, "" 1211""); +\t\t ozonef1e_h(foo[ 7: 5], fd); +\t\t $fwrite (fd, "" 1212""); +\t\t ozonexe(foo[ 8: 5], fd); +\t\t dude(fd); +\t\t $fwrite (fd, "" 1213""); + end + 17\'b00_10??_?_????_?1_1110 : + begin +\t\t ozonef1e(foo, fd); +\t\t $fwrite (fd, "" 1214""); +\t\t ozonef1e_ye(foo[14:9],1\'b0, fd); +\t\t $fwrite (fd, "" 1215""); +\t\t $fwrite (fd, "" 1216""); +\t\t ozonef1e_h(foo[11: 9], fd); +\t\t $fwrite (fd, "" 1217""); +\t\t $fwrite (fd, "" 1218""); +\t\t ozonef1e_h(foo[ 7: 5], fd); +\t\t $fwrite (fd, "" 1219""); +\t\t ozonexe(foo[ 8: 5], fd); +\t\t dude(fd); +\t\t $fwrite (fd, "" 1220""); + end + 17\'b00_10??_?_????_?0_1000 : + begin +\t\t ozonef1e(foo, fd); +\t\t $fwrite (fd, "" 1221""); +\t\t ozonef1e_ye(foo[14:9],1\'b0, fd); +\t\t $fwrite (fd, "" 1222""); +\t\t $fwrite (fd, "" 1223""); +\t\t ozonef1e_h(foo[11: 9], fd); +\t\t $fwrite (fd, "" 1224""); +\t\t $fwrite (fd, "" 1225""); +\t\t ozonef1e_h(foo[ 7: 5], fd); +\t\t $fwrite (fd, "" 1226""); +\t\t ozonexe(foo[ 8: 5], fd); +\t\t dude(fd); +\t\t $fwrite (fd, "" 1227""); + end + 17\'b10_01??_?_????_??_???? : + begin +\t\t if (foo[27]) +\t\t $fwrite (fd,"" 1228""); +\t\t else +\t\t $fwrite (fd,"" 1229""); +\t\t ozonecon(foo[20:16], fd); +\t\t $fwrite (fd, "" 1230""); +\t\t ozonef2(foo[31:0], fd); +\t\t dude(fd); +\t\t $fwrite (fd, "" 1231""); + end + 17\'b00_1000_?_????_01_0011 : + if (~|foo[ 9: 8]) +\t\t begin +\t\t if (foo[ 7]) +\t\t $fwrite (fd,"" 1232""); +\t\t else +\t\t $fwrite (fd,"" 1233""); +\t\t ozonecon(foo[14:10], fd); +\t\t $fwrite (fd, "" 1234""); +\t\t ozonef2e(foo[31:0], fd); +\t\t dude(fd); +\t\t $fwrite (fd, "" 1235""); +\t\t end + else +\t\t begin +\t\t $fwrite (fd, "" 1236""); +\t\t ozonecon(foo[14:10], fd); +\t\t $fwrite (fd, "" 1237""); +\t\t ozonef3e(foo[31:0], fd); +\t\t dude(fd); +\t\t $fwrite (fd, "" 1238""); +\t\t end + 17\'b11_110?_1_????_??_???? : + begin +\t\t ozonef3(foo[31:0], fd); +\t\t dude(fd); +\t\t $fwrite(fd, "" 1239""); + end + 17\'b11_110?_0_????_??_???? : + begin : f4_body +\t\t casez (foo[24:20]) +\t\t 5\'b0_1110, +\t\t 5\'b1_0???, +\t\t 5\'b1_1111: +\t\t\tbegin +\t\t\t $fwrite (fd, "" 1240""); +\t\t\tend +\t\t 5\'b0_00??: +\t\t begin +\t\t\t ozoneacc(foo[26], fd); +\t\t\t $fwrite (fd, "" 1241""); +\t\t\t ozoneacc(foo[25], fd); +\t\t\t ozonebmuop(foo[24:20], fd); +\t\t\t ozoneae(foo[18:16], fd); +\t\t\t $fwrite (fd, "" 1242""); +\t\t\t dude(fd); +\t\t\t $fwrite(fd, "" 1243""); +\t\t end +\t\t 5\'b0_01??: +\t\t begin +\t\t\t ozoneacc(foo[26], fd); +\t\t\t $fwrite (fd, "" 1244""); +\t\t\t ozoneacc(foo[25], fd); +\t\t\t ozonebmuop(foo[24:20], fd); +\t\t\t ozonearm(foo[18:16], fd); +\t\t\t dude(fd); +\t\t\t $fwrite(fd, "" 1245""); +\t\t end +\t\t 5\'b0_1011: +\t\t begin +\t\t\t ozoneacc(foo[26], fd); +\t\t\t $fwrite (fd, "" 1246""); +\t\t\t ozonebmuop(foo[24:20], fd); +\t\t\t $fwrite (fd, "" 1247""); +\t\t\t ozoneae(foo[18:16], fd); +\t\t\t $fwrite (fd, "" 1248""); +\t\t\t dude(fd); +\t\t\t $fwrite(fd, "" 1249""); +\t\t end +\t\t 5\'b0_100?, +\t\t 5\'b0_1010, +\t\t 5\'b0_110? : +\t\t\tbegin +\t\t\t ozoneacc(foo[26], fd); +\t\t\t $fwrite (fd, "" 1250""); +\t\t\t ozonebmuop(foo[24:20], fd); +\t\t\t $fwrite (fd, "" 1251""); +\t\t\t ozoneacc(foo[25], fd); +\t\t\t $fwrite (fd, "" 1252""); +\t\t\t ozoneae(foo[18:16], fd); +\t\t\t $fwrite (fd, "" 1253""); +\t\t\t dude(fd); +\t\t\t $fwrite(fd, "" 1254""); +\t\t\tend +\t\t 5\'b0_1111 : +\t\t begin +\t\t\t ozoneacc(foo[26], fd); +\t\t\t $fwrite (fd, "" 1255""); +\t\t\t ozoneacc(foo[25], fd); +\t\t\t $fwrite (fd, "" 1256""); +\t\t\t ozoneae(foo[18:16], fd); +\t\t\t dude(fd); +\t\t\t $fwrite(fd, "" 1257""); +\t\t end +\t\t 5\'b1_10??, +\t\t 5\'b1_110?, +\t\t 5\'b1_1110 : +\t\t\tbegin +\t\t\t ozoneacc(foo[26], fd); +\t\t\t $fwrite (fd, "" 1258""); +\t\t\t ozonebmuop(foo[24:20], fd); +\t\t\t $fwrite (fd, "" 1259""); +\t\t\t ozoneacc(foo[25], fd); +\t\t\t $fwrite (fd, "" 1260""); +\t\t\t ozonearm(foo[18:16], fd); +\t\t\t $fwrite (fd, "" 1261""); +\t\t\t dude(fd); +\t\t\t $fwrite(fd, "" 1262""); +\t\t\tend +\t\t endcase + end + 17\'b11_100?_?_????_??_???? : + casez (foo[23:19]) +\t\t 5\'b111??, +\t\t 5\'b0111?: +\t\t begin +\t\t\tozoneae(foo[26:24], fd); +\t\t\t$fwrite (fd, "" 1263""); +\t\t\tozonef3f4imop(foo[23:19], fd); +\t\t\t$fwrite (fd, "" 1264""); +\t\t\tozoneae(foo[18:16], fd); +\t\t\t$fwrite (fd, "" 1265""); +\t\t\tskyway(foo[15:12], fd); +\t\t\tskyway(foo[11: 8], fd); +\t\t\tskyway(foo[ 7: 4], fd); +\t\t\tskyway(foo[ 3:0], fd); +\t\t\t$fwrite (fd, "" 1266""); +\t\t\tdude(fd); +\t\t\t$fwrite(fd, "" 1267""); +\t\t end +\t\t 5\'b?0???, +\t\t 5\'b110??: +\t\t begin +\t\t\tozoneae(foo[26:24], fd); +\t\t\t$fwrite (fd, "" 1268""); +\t\t\tif (foo[23:21] == 3\'b100) +\t\t\t $fwrite (fd, "" 1269""); +\t\t\tozoneae(foo[18:16], fd); +\t\t\tif (foo[19]) +\t\t\t $fwrite (fd, "" 1270""); +\t\t\telse +\t\t\t $fwrite (fd, "" 1271""); +\t\t\tozonef3f4imop(foo[23:19], fd); +\t\t\t$fwrite (fd, "" 1272""); +\t\t\tozonef3f4_iext(foo[20:19], foo[15:0], fd); +\t\t\tdude(fd); +\t\t\t$fwrite(fd, "" 1273""); +\t\t end +\t\t 5\'b010??, +\t\t 5\'b0110?: +\t\t begin +\t\t\tozoneae(foo[18:16], fd); +\t\t\tif (foo[19]) +\t\t\t $fwrite (fd, "" 1274""); +\t\t\telse +\t\t\t $fwrite (fd, "" 1275""); +\t\t\tozonef3f4imop(foo[23:19], fd); +\t\t\t$fwrite (fd, "" 1276""); +\t\t\tozonef3f4_iext(foo[20:19], foo[15:0], fd); +\t\t\tdude(fd); +\t\t\t$fwrite(fd, "" 1277""); +\t\t end + endcase + 17\'b00_1000_?_????_11_0011 : + begin +\t\t $fwrite (fd,"" 1278""); +\t\t ozonecon(foo[14:10], fd); +\t\t $fwrite (fd, "" 1279""); +\t\t casez (foo[25:21]) +\t\t 5\'b0_1110, +\t\t 5\'b1_0???, +\t\t 5\'b1_1111: +\t\t\tbegin +\t\t\t $fwrite(fd, "" 1280""); +\t\t\tend +\t\t 5\'b0_00??: +\t\t begin +\t\t\t ozoneae(foo[20:18], fd); +\t\t\t $fwrite (fd, "" 1281""); +\t\t\t ozoneae(foo[17:15], fd); +\t\t\t ozonebmuop(foo[25:21], fd); +\t\t\t ozoneae(foo[ 8: 6], fd); +\t\t\t $fwrite (fd, "" 1282""); +\t\t\t dude(fd); +\t\t\t $fwrite(fd, "" 1283""); +\t\t end +\t\t 5\'b0_01??: +\t\t begin +\t\t\t ozoneae(foo[20:18], fd); +\t\t\t $fwrite (fd, "" 1284""); +\t\t\t ozoneae(foo[17:15], fd); +\t\t\t ozonebmuop(foo[25:21], fd); +\t\t\t ozonearm(foo[ 8: 6], fd); +\t\t\t dude(fd); +\t\t\t $fwrite(fd, "" 1285""); +\t\t end +\t\t 5\'b0_1011: +\t\t begin +\t\t\t ozoneae(foo[20:18], fd); +\t\t\t $fwrite (fd, "" 1286""); +\t\t\t ozonebmuop(foo[25:21], fd); +\t\t\t $fwrite (fd, "" 1287""); +\t\t\t ozoneae(foo[ 8: 6], fd); +\t\t\t $fwrite (fd, "" 1288""); +\t\t\t dude(fd); +\t\t\t $fwrite(fd, "" 1289""); +\t\t end +\t\t 5\'b0_100?, +\t\t 5\'b0_1010, +\t\t 5\'b0_110? : +\t\t\tbegin +\t\t\t ozoneae(foo[20:18], fd); +\t\t\t $fwrite (fd, "" 1290""); +\t\t\t ozonebmuop(foo[25:21], fd); +\t\t\t $fwrite (fd, "" 1291""); +\t\t\t ozoneae(foo[17:15], fd); +\t\t\t $fwrite (fd, "" 1292""); +\t\t\t ozoneae(foo[ 8: 6], fd); +\t\t\t $fwrite (fd, "" 1293""); +\t\t\t dude(fd); +\t\t\t $fwrite(fd, "" 1294""); +\t\t\tend +\t\t 5\'b0_1111 : +\t\t begin +\t\t\t ozoneae(foo[20:18], fd); +\t\t\t $fwrite (fd, "" 1295""); +\t\t\t ozoneae(foo[17:15], fd); +\t\t\t $fwrite (fd, "" 1296""); +\t\t\t ozoneae(foo[ 8: 6], fd); +\t\t\t dude(fd); +\t\t\t $fwrite(fd, "" 1297""); +\t\t end +\t\t 5\'b1_10??, +\t\t 5\'b1_110?, +\t\t 5\'b1_1110 : +\t\t\tbegin +\t\t\t ozoneae(foo[20:18], fd); +\t\t\t $fwrite (fd, "" 1298""); +\t\t\t ozonebmuop(foo[25:21], fd); +\t\t\t $fwrite (fd, "" 1299""); +\t\t\t ozoneae(foo[17:15], fd); +\t\t\t $fwrite (fd, "" 1300""); +\t\t\t ozonearm(foo[ 8: 6], fd); +\t\t\t $fwrite (fd, "" 1301""); +\t\t\t dude(fd); +\t\t\t $fwrite(fd, "" 1302""); +\t\t\tend +\t\t endcase + end + 17\'b00_0010_?_????_??_???? : + begin +\t\t ozonerab({1\'b0, foo[25:20]}, fd); +\t\t $fwrite (fd, "" 1303""); +\t\t skyway(foo[19:16], fd); +\t\t dude(fd); +\t\t $fwrite(fd, "" 1304""); + end + 17\'b00_01??_?_????_??_???? : + begin +\t\t if (foo[27]) +\t\t begin +\t\t $fwrite (fd, "" 1305""); +\t\t if (foo[26]) +\t\t\t $fwrite (fd, "" 1306""); +\t\t else +\t\t\t $fwrite (fd, "" 1307""); +\t\t skyway(foo[19:16], fd); +\t\t $fwrite (fd, "" 1308""); +\t\t ozonerab({1\'b0, foo[25:20]}, fd); +\t\t end +\t\t else +\t\t begin +\t\t ozonerab({1\'b0, foo[25:20]}, fd); +\t\t $fwrite (fd, "" 1309""); +\t\t if (foo[26]) +\t\t\t $fwrite (fd, "" 1310""); +\t\t else +\t\t\t $fwrite (fd, "" 1311""); +\t\t skyway(foo[19:16], fd); +\t\t $fwrite (fd, "" 1312""); +\t\t end +\t\t dude(fd); +\t\t $fwrite(fd, "" 1313""); + end + 17\'b01_000?_?_????_??_???? : + begin +\t\t if (foo[26]) +\t\t begin +\t\t ozonerb(foo[25:20], fd); +\t\t $fwrite (fd, "" 1314""); +\t\t ozoneae(foo[18:16], fd); +\t\t ozonehl(foo[19], fd); +\t\t end +\t\t else +\t\t begin +\t\t ozoneae(foo[18:16], fd); +\t\t ozonehl(foo[19], fd); +\t\t $fwrite (fd, "" 1315""); +\t\t ozonerb(foo[25:20], fd); +\t\t end +\t\t dude(fd); +\t\t $fwrite(fd, "" 1316""); + end + 17\'b01_10??_?_????_??_???? : + begin +\t\t if (foo[27]) +\t\t begin +\t\t ozonerab({1\'b0, foo[25:20]}, fd); +\t\t $fwrite (fd, "" 1317""); +\t\t ozonerx(foo, fd); +\t\t end +\t\t else +\t\t begin +\t\t ozonerx(foo, fd); +\t\t $fwrite (fd, "" 1318""); +\t\t ozonerab({1\'b0, foo[25:20]}, fd); +\t\t end +\t\t dude(fd); +\t\t $fwrite(fd, "" 1319""); + end + 17\'b11_101?_?_????_??_???? : + begin +\t\t ozonerab (foo[26:20], fd); +\t\t $fwrite (fd, "" 1320""); +\t\t skyway(foo[19:16], fd); +\t\t skyway(foo[15:12], fd); +\t\t skyway(foo[11: 8], fd); +\t\t skyway(foo[ 7: 4], fd); +\t\t skyway(foo[ 3: 0], fd); +\t\t dude(fd); +\t\t $fwrite(fd, "" 1321""); + end + 17\'b11_0000_?_????_??_???? : + begin +\t\t casez (foo[25:23]) +\t\t 3\'b00?: +\t\t begin +\t\t\t ozonerab(foo[22:16], fd); +\t\t\t $fwrite (fd, "" 1322""); +\t\t end +\t\t 3\'b01?: +\t\t begin +\t\t\t $fwrite (fd, "" 1323""); +\t\t\t if (foo[22:16]>=7\'h60) +\t\t\t $fwrite (fd, "" 1324""); +\t\t\t else +\t\t\t ozonerab(foo[22:16], fd); +\t\t end +\t\t 3\'b110: +\t\t $fwrite (fd, "" 1325""); +\t\t 3\'b10?: +\t\t begin +\t\t\t $fwrite (fd, "" 1326""); +\t\t\t if (foo[22:16]>=7\'h60) +\t\t\t $fwrite (fd, "" 1327""); +\t\t\t else +\t\t\t ozonerab(foo[22:16], fd); +\t\t end +\t\t 3\'b111: +\t\t begin +\t\t\t $fwrite (fd, "" 1328""); +\t\t\t ozonerab(foo[22:16], fd); +\t\t\t $fwrite (fd, "" 1329""); +\t\t end +\t\t endcase +\t\t dude(fd); +\t\t $fwrite(fd, "" 1330""); + end + 17\'b00_10??_?_????_?1_0000 : + begin +\t\t if (foo[27]) +\t\t begin +\t\t $fwrite (fd, "" 1331""); +\t\t ozonerp(foo[14:12], fd); +\t\t $fwrite (fd, "" 1332""); +\t\t skyway(foo[19:16], fd); +\t\t skyway({foo[15],foo[11: 9]}, fd); +\t\t skyway(foo[ 8: 5], fd); +\t\t $fwrite (fd, "" 1333""); +\t\t if (foo[26:20]>=7\'h60) +\t\t\t $fwrite (fd, "" 1334""); +\t\t else +\t\t\t ozonerab(foo[26:20], fd); +\t\t end +\t\t else +\t\t begin +\t\t ozonerab(foo[26:20], fd); +\t\t $fwrite (fd, "" 1335""); +\t\t $fwrite (fd, "" 1336""); +\t\t ozonerp(foo[14:12], fd); +\t\t $fwrite (fd, "" 1337""); +\t\t skyway(foo[19:16], fd); +\t\t skyway({foo[15],foo[11: 9]}, fd); +\t\t skyway(foo[ 8: 5], fd); +\t\t $fwrite (fd, "" 1338""); +\t\t end +\t\t dude(fd); +\t\t $fwrite(fd, "" 1339""); + end + 17\'b00_101?_1_0000_?1_0010 : + if (~|foo[11: 7]) +\t\t begin +\t\t if (foo[ 6]) +\t\t begin +\t\t\t $fwrite (fd, "" 1340""); +\t\t\t ozonerp(foo[14:12], fd); +\t\t\t $fwrite (fd, "" 1341""); +\t\t\t ozonejk(foo[ 5], fd); +\t\t\t $fwrite (fd, "" 1342""); +\t\t\t if (foo[26:20]>=7\'h60) +\t\t\t $fwrite (fd, "" 1343""); +\t\t\t else +\t\t\t ozonerab(foo[26:20], fd); +\t\t end +\t\t else +\t\t begin +\t\t\t ozonerab(foo[26:20], fd); +\t\t\t $fwrite (fd, "" 1344""); +\t\t\t $fwrite (fd, "" 1345""); +\t\t\t ozonerp(foo[14:12], fd); +\t\t\t $fwrite (fd, "" 1346""); +\t\t\t ozonejk(foo[ 5], fd); +\t\t\t $fwrite (fd, "" 1347""); +\t\t end +\t\t dude(fd); +\t\t $fwrite(fd, "" 1348""); +\t\t end + else +\t\t $fwrite(fd, "" 1349""); + 17\'b00_100?_0_0011_?1_0101 : + if (~|foo[ 8: 7]) +\t\t begin +\t\t if (foo[6]) +\t\t begin +\t\t\t ozonerab(foo[26:20], fd); +\t\t\t $fwrite (fd, "" 1350""); +\t\t\t ozoneye(foo[14: 9],foo[ 5], fd); +\t\t end +\t\t else +\t\t begin +\t\t\t ozoneye(foo[14: 9],foo[ 5], fd); +\t\t\t $fwrite (fd, "" 1351""); +\t\t\t if (foo[26:20]>=7\'h60) +\t\t\t $fwrite (fd, "" 1352""); +\t\t\t else +\t\t\t ozonerab(foo[26:20], fd); +\t\t end +\t\t dude(fd); +\t\t $fwrite(fd, "" 1353""); +\t\t end + else +\t\t $fwrite(fd, "" 1354""); + 17\'b00_1001_0_0000_?1_0010 : + if (~|foo[25:20]) +\t\t begin +\t\t ozoneye(foo[14: 9],1\'b0, fd); +\t\t $fwrite (fd, "" 1355""); +\t\t ozonef1e_h(foo[11: 9], fd); +\t\t $fwrite (fd, "" 1356""); +\t\t ozonef1e_h(foo[ 7: 5], fd); +\t\t $fwrite (fd, "" 1357""); +\t\t ozonexe(foo[ 8: 5], fd); +\t\t dude(fd); +\t\t $fwrite(fd, "" 1358""); +\t\t end + else +\t\t $fwrite(fd, "" 1359""); + 17\'b00_101?_0_????_?1_0010 : + if (~foo[13]) +\t\t begin +\t\t if (foo[12]) +\t\t begin +\t\t\t $fwrite (fd, "" 1360""); +\t\t\t if (foo[26:20]>=7\'h60) +\t\t\t $fwrite (fd, "" 1361""); +\t\t\t else +\t\t\t ozonerab(foo[26:20], fd); +\t\t\t $fwrite (fd, "" 1362""); +\t\t\t $fwrite (fd, "" 1363""); +\t\t\t skyway({1\'b0,foo[18:16]}, fd); +\t\t\t skyway({foo[15],foo[11: 9]}, fd); +\t\t\t skyway(foo[ 8: 5], fd); +\t\t\t dude(fd); +\t\t\t $fwrite(fd, "" 1364""); +\t\t end +\t\t else +\t\t begin +\t\t\t ozonerab(foo[26:20], fd); +\t\t\t $fwrite (fd, "" 1365""); +\t\t\t $fwrite (fd, "" 1366""); +\t\t\t skyway({1\'b0,foo[18:16]}, fd); +\t\t\t skyway({foo[15],foo[11: 9]}, fd); +\t\t\t skyway(foo[ 8: 5], fd); +\t\t\t dude(fd); +\t\t\t $fwrite(fd, "" 1367""); +\t\t end +\t\t end + else +\t\t $fwrite(fd, "" 1368""); + 17\'b01_01??_?_????_??_???? : + begin +\t\t ozonerab({1\'b0,foo[27:26],foo[19:16]}, fd); +\t\t $fwrite (fd, "" 1369""); +\t\t ozonerab({1\'b0,foo[25:20]}, fd); +\t\t dude(fd); +\t\t $fwrite(fd, "" 1370""); + end + 17\'b00_100?_?_???0_11_0101 : + if (~foo[6]) +\t\t begin +\t\t $fwrite (fd,"" 1371""); +\t\t ozonecon(foo[14:10], fd); +\t\t $fwrite (fd, "" 1372""); +\t\t ozonerab({foo[ 9: 7],foo[19:16]}, fd); +\t\t $fwrite (fd, "" 1373""); +\t\t ozonerab({foo[26:20]}, fd); +\t\t dude(fd); +\t\t $fwrite(fd, "" 1374""); +\t\t end + else +\t\t $fwrite(fd, "" 1375""); + 17\'b00_1000_?_????_?1_0010 : + if (~|foo[25:24]) +\t\t begin +\t\t ozonery(foo[23:20], fd); +\t\t $fwrite (fd, "" 1376""); +\t\t ozonerp(foo[14:12], fd); +\t\t $fwrite (fd, "" 1377""); +\t\t skyway(foo[19:16], fd); +\t\t skyway({foo[15],foo[11: 9]}, fd); +\t\t skyway(foo[ 8: 5], fd); +\t\t dude(fd); +\t\t $fwrite(fd, "" 1378""); +\t\t end + else if ((foo[25:24] == 2\'b10) & ~|foo[19:15] & ~|foo[11: 6]) +\t\t begin +\t\t ozonery(foo[23:20], fd); +\t\t $fwrite (fd, "" 1379""); +\t\t ozonerp(foo[14:12], fd); +\t\t $fwrite (fd, "" 1380""); +\t\t ozonejk(foo[ 5], fd); +\t\t dude(fd); +\t\t $fwrite(fd, "" 1381""); +\t\t end + else +\t\t $fwrite(fd, "" 1382""); + 17\'b11_01??_?_????_??_????, + 17\'b10_00??_?_????_??_???? : +\t\t if (foo[30]) +\t\t $fwrite(fd, "" 1383:%x"", foo[27:16]); +\t\t else +\t\t $fwrite(fd, "" 1384:%x"", foo[27:16]); + 17\'b00_10??_?_????_01_1000 : + if (~foo[6]) +\t\t begin +\t\t if (foo[7]) +\t\t $fwrite(fd, "" 1385:%x"", foo[27: 8]); +\t\t else +\t\t $fwrite(fd, "" 1386:%x"", foo[27: 8]); +\t\t end + else +\t\t $fwrite(fd, "" 1387""); + 17\'b00_10??_?_????_11_1000 : + begin +\t\t $fwrite (fd,"" 1388""); +\t\t ozonecon(foo[14:10], fd); +\t\t $fwrite (fd, "" 1389""); +\t\t if (foo[15]) +\t\t $fwrite (fd, "" 1390""); +\t\t else +\t\t $fwrite (fd, "" 1391""); +\t\t skyway(foo[27:24], fd); +\t\t skyway(foo[23:20], fd); +\t\t skyway(foo[19:16], fd); +\t\t skyway(foo[ 9: 6], fd); +\t\t dude(fd); +\t\t $fwrite(fd, "" 1392""); + end + 17\'b11_0001_?_????_??_???? : + casez (foo[25:22]) +\t\t 4\'b01?? : +\t\t begin +\t\t $fwrite (fd,"" 1393""); +\t\t ozonecon(foo[20:16], fd); +\t\t case (foo[23:21]) +\t\t\t3\'h0 : $fwrite (fd, "" 1394""); +\t\t\t3\'h1 : $fwrite (fd, "" 1395""); +\t\t\t3\'h2 : $fwrite (fd, "" 1396""); +\t\t\t3\'h3 : $fwrite (fd, "" 1397""); +\t\t\t3\'h4 : $fwrite (fd, "" 1398""); +\t\t\t3\'h5 : $fwrite (fd, "" 1399""); +\t\t\t3\'h6 : $fwrite (fd, "" 1400""); +\t\t\t3\'h7 : $fwrite (fd, "" 1401""); +\t\t endcase +\t\t dude(fd); +\t\t $fwrite(fd, "" 1402""); +\t\t end +\t\t 4\'b0000 : +\t\t $fwrite(fd, "" 1403:%x"", foo[21:16]); +\t\t 4\'b0010 : +\t\t if (~|foo[21:16]) + $fwrite(fd, "" 1404""); +\t\t 4\'b1010 : +\t\t if (~|foo[21:17]) +\t\t begin +\t\t\tif (foo[16]) +\t\t\t $fwrite(fd, "" 1405""); +\t\t\telse +\t\t\t $fwrite(fd, "" 1406""); +\t\t end +\t\t default : +\t\t $fwrite(fd, "" 1407""); + endcase + 17\'b01_11??_?_????_??_???? : + if (foo[27:23] === 5\'h00) +\t\t $fwrite(fd, "" 1408:%x"", foo[22:16]); + else +\t\t $fwrite(fd, "" 1409:%x"", foo[22:16]); + default: $fwrite(fd, "" 1410""); +\t endcase + end + endtask + + //(query-replace-regexp ""\\\\([a-z0-9_]+\\\\) *( *\\\\([][a-z0-9_~\': ]+\\\\) *, *\\\\([][a-z0-9\'~: ]+\\\\) *, *\\\\([][a-z0-9\'~: ]+\\\\) *);"" ""$c(\\""\\\\1(\\"",\\\\2,\\"",\\"",\\\\3,\\"",\\"",\\\\4,\\"");\\"");"" nil nil nil) + //(query-replace-regexp ""\\\\([a-z0-9_]+\\\\) *( *\\\\([][a-z0-9_~\': ]+\\\\) *, *\\\\([][a-z0-9\'~: ]+\\\\) *);"" ""$c(\\""\\\\1(\\"",\\\\2,\\"",\\"",\\\\3,\\"");\\"");"" nil nil nil) + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +module t + ( + input wire reset_l, + input wire clk + ); + + sub sub_I + ( + .clk(clk), + .reset_l(reset_l), + .cpu_if_timeout(1'b0) + ); +endmodule + +module sub + ( + input wire\tclk, reset_l, + output reg\tcpu_if_timeout + ); + + always @(posedge clk) begin + if (!reset_l) begin +\t cpu_if_timeout <= 1'b0; + end + else begin +\t cpu_if_timeout <= 1'b0; + end + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t (/*AUTOARG*/); + + reg [72:1] in; + initial begin + if (in[( (1'h0 / 1'b0) )+:71] != 71'h0) $stop; + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +module t (/*AUTOARG*/); + + wire d, en, nc, pc; + + // verilator lint_off IMPLICIT + cmos (cm0, d, nc, pc); + rcmos (rc0, d, nc, pc); + + nmos (nm0, d, en); + pmos (pm0, d, en); + rnmos (rn0, d, en); + rpmos (rp0, d, en); + + rtran (rt0, d); + tran (tr0, d); + + rtranif0 (r00, d, en); + rtranif1 (r10, d, en); + tranif0 (t00, d, en); + tranif1 (t10, d, en); + // verilator lint_on IMPLICIT + + initial begin + $write(""*-* All Finished *-*\ +""); + $finish; + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // Check empty blocks + task EmptyFor; + /* verilator public */ + integer i; + begin + for (i = 0; i < 2; i = i+1) + begin + end + end + endtask + + // Check look unroller + reg signed\t signed_tests_only = 1\'sb1; + integer \t total; + + integer\t i; + reg [31:0] \t iu; + reg [31:0]\t dly_to_insure_was_unrolled [1:0]; + reg [2:0] \t i3; + + integer cyc; initial cyc=0; + always @ (posedge clk) begin + cyc <= cyc + 1; + case (cyc) +\t1: begin +\t // >= signed +\t total = 0; +\t for (i=5; i>=0; i=i-1) begin +\t total = total - i -1; +\t dly_to_insure_was_unrolled[i] <= i; +\t end +\t if (total != -21) $stop; +\tend +\t2: begin +\t // > signed +\t total = 0; +\t for (i=5; i>0; i=i-1) begin +\t total = total - i -1; +\t dly_to_insure_was_unrolled[i] <= i; +\t end +\t if (total != -20) $stop; +\tend +\t3: begin +\t // < signed +\t total = 0; +\t for (i=1; i<5; i=i+1) begin +\t total = total - i -1; +\t dly_to_insure_was_unrolled[i] <= i; +\t end +\t if (total != -14) $stop; +\tend +\t4: begin +\t // <= signed +\t total = 0; +\t for (i=1; i<=5; i=i+1) begin +\t total = total - i -1; +\t dly_to_insure_was_unrolled[i] <= i; +\t end +\t if (total != -20) $stop; +\tend +\t// UNSIGNED +\t5: begin +\t // >= unsigned +\t total = 0; +\t for (iu=5; iu>=1; iu=iu-1) begin +\t total = total - iu -1; +\t dly_to_insure_was_unrolled[iu] <= iu; +\t end +\t if (total != -20) $stop; +\tend +\t6: begin +\t // > unsigned +\t total = 0; +\t for (iu=5; iu>1; iu=iu-1) begin +\t total = total - iu -1; +\t dly_to_insure_was_unrolled[iu] <= iu; +\t end +\t if (total != -18) $stop; +\tend +\t7: begin +\t // < unsigned +\t total = 0; +\t for (iu=1; iu<5; iu=iu+1) begin +\t total = total - iu -1; +\t dly_to_insure_was_unrolled[iu] <= iu; +\t end +\t if (total != -14) $stop; +\tend +\t8: begin +\t // <= unsigned +\t total = 0; +\t for (iu=1; iu<=5; iu=iu+1) begin +\t total = total - iu -1; +\t dly_to_insure_was_unrolled[iu] <= iu; +\t end +\t if (total != -20) $stop; +\tend +\t//=== +\t9: begin +\t // mostly cover a small index +\t total = 0; +\t for (i3=3\'d0; i3<3\'d7; i3=i3+3\'d1) begin +\t total = total - {29\'d0,i3} -1; +\t dly_to_insure_was_unrolled[i3[0]] <= 0; +\t end +\t if (total != -28) $stop; +\tend +\t//=== +\t10: begin +\t // mostly cover a small index +\t total = 0; +\t for (i3=0; i3<3\'d7; i3=i3+3\'d1) begin +\t total = total - {29\'d0,i3} -1; +\t dly_to_insure_was_unrolled[i3[0]] <= 0; +\t end +\t if (total != -28) $stop; +\tend +\t//=== +\t11: begin +\t // width violation on <, causes extend +\t total = 0; +\t for (i3=3\'d0; i3<7; i3=i3+1) begin +\t total = total - {29\'d0,i3} -1; +\t dly_to_insure_was_unrolled[i3[0]] <= 0; +\t end +\t if (total != -28) $stop; +\tend +\t//=== +\t// width violation on <, causes extend signed +\t// Unsupported as yet +\t//=== +\t19: begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; +\tend +\tdefault: ; + endcase + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder + +`define STRINGIFY(x) `""x`"" + +module t; + initial begin +`ifdef D1A + if (`STRINGIFY(`D4B) !== """") $stop; +`else + $write(""%%Error: Missing define\ +""); $stop; +`endif + +`ifdef D2A + if (`STRINGIFY(`D2A) !== ""VALA"") $stop; +`else + $write(""%%Error: Missing define\ +""); $stop; +`endif + +`ifdef D3A + if (`STRINGIFY(`D4B) !== """") $stop; +`else + $write(""%%Error: Missing define\ +""); $stop; +`endif + +`ifdef D3B + if (`STRINGIFY(`D4B) !== """") $stop; +`else + $write(""%%Error: Missing define\ +""); $stop; +`endif + +`ifdef D4A + if (`STRINGIFY(`D4A) !== ""VALA"") $stop; +`else + $write(""%%Error: Missing define\ +""); $stop; +`endif + +`ifdef D4B + if (`STRINGIFY(`D4B) !== """") $stop; +`else + $write(""%%Error: Missing define\ +""); $stop; +`endif + +`ifdef D5A + if (`STRINGIFY(`D5A) !== ""VALA"") $stop; +`else + $write(""%%Error: Missing define\ +""); $stop; +`endif + +`ifdef D5A + if (`STRINGIFY(`D5B) !== ""VALB"") $stop; +`else + $write(""%%Error: Missing define\ +""); $stop; +`endif + + $write(""*-* All Finished *-*\ +""); + $finish; + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer \tcyc=0; + reg [63:0] \tcrc; + reg [63:0] \tsum; + + // Take CRC data and apply to testblock inputs + wire [3:0] l_stop = crc[3:0]; + wire [3:0] l_break = crc[7:4]; + wire [3:0] l_continue = crc[11:8]; + + /*AUTOWIRE*/ + + wire [15:0] out0 = Test0(l_stop, l_break, l_continue); + wire [15:0] out1 = Test1(l_stop, l_break, l_continue); + wire [15:0] out2 = Test2(l_stop, l_break, l_continue); + wire [15:0] out3 = Test3(l_stop, l_break, l_continue); + + // Aggregate outputs into a single result vector + wire [63:0] result = {out3,out2,out1,out0}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write(""[%0t] cyc==%0d crc=%x result=%x\ +"",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin +\t // Setup +\t crc <= 64\'h5aef0c8d_d70a4497; +\t sum <= 64\'h0; + end + else if (cyc<10) begin +\t sum <= 64\'h0; + end + else if (cyc<90) begin +\t if (out0!==out1) $stop; +\t if (out0!==out2) $stop; +\t if (out0!==out3) $stop; + end + else if (cyc==99) begin +\t $write(""[%0t] cyc==%0d crc=%x sum=%x\ +"",$time, cyc, crc, sum); +\t if (crc !== 64\'hc77bb9b3784ea091) $stop; +\t // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64\'h293e9f9798e97da0 +\t if (sum !== `EXPECTED_SUM) $stop; +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end + + function [15:0] Test0; + input [3:0] loop_stop; + input [3:0] loop_break; + input [3:0] loop_continue; + integer \t i; + reg \t broken; + + Test0 = 0; + broken = 0; + begin +\t for (i=1; i<20; i=i+1) begin +\t if (!broken) begin +\t Test0 = Test0 + 1; +\t if (i[3:0] != loop_continue) begin // continue +\t\t if (i[3:0] == loop_break) begin +\t\t broken = 1\'b1; +\t\t end +\t\t if (!broken) begin +\t\t Test0 = Test0 + i[15:0]; +\t\t end +\t end +\t end +\t end + end + endfunction + + function [15:0] Test1; + input [3:0] loop_stop; + input [3:0] loop_break; + input [3:0] loop_continue; + integer \t i; + + Test1 = 0; + begin : outer_block + for (i=1; i<20; i=i+1) begin : inner_block + \t Test1 = Test1 + 1; +\t // continue, IE jump to end-of-inner_block. Must be inside inner_block. + if (i[3:0] == loop_continue) disable inner_block; +\t // break, IE jump to end-of-outer_block. Must be inside outer_block. + \t if (i[3:0] == loop_break) disable outer_block; + \t Test1 = Test1 + i[15:0]; + end : inner_block + end : outer_block + endfunction + + function [15:0] Test2; + input [3:0] loop_stop; + input [3:0] loop_break; + input [3:0] loop_continue; + integer \t i; + + Test2 = 0; + begin + for (i=1; i<20; i=i+1) begin + \t Test2 = Test2 + 1; + \t if (i[3:0] == loop_continue) continue; + \t if (i[3:0] == loop_break) break; + \t Test2 = Test2 + i[15:0]; + end + end + endfunction + + function [15:0] Test3; + input [3:0] loop_stop; + input [3:0] loop_break; + input [3:0] loop_continue; + integer \t i; + + Test3 = 0; + begin + for (i=1; i<20; i=i+1) begin + \t Test3 = Test3 + 1; + \t if (i[3:0] == loop_continue) continue; +\t // return, IE jump to end-of-function optionally setting return value + \t if (i[3:0] == loop_break) return Test3; + \t Test3 = Test3 + i[15:0]; + end + end + endfunction + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +module t (/*AUTOARG*/); + + function int f( int j = 1, int s = 0 ); + return (j<<16) | s; + endfunction + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write(""%%Error: %s:%0d: got=\'h%x exp=\'h%x\ +"", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); + + initial begin + `checkh( f(.j(2), .s(1))\t, 32\'h2_0001 ); + `checkh( f(.s(1))\t\t, 32\'h1_0001 ); + `checkh( f(, 1)\t\t, 32\'h1_0001 ); + `checkh( f(.j(2))\t\t, 32\'h2_0000 ); + `checkh( f(.s(1), .j(2))\t, 32\'h2_0001 ); + `checkh( f(.s(), .j())\t, 32\'h1_0000 ); + `checkh( f(2)\t\t, 32\'h2_0000 ); + `checkh( f()\t\t, 32\'h1_0000 ); + + $write(""*-* All Finished *-*\ +""); + $finish; + end + +endmodule +" +"// DESCRIPTION: Verilator: Simple static elaboration case +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Todd Strader. + +module t (/*AUTOARG*/); + + typedef struct packed { + logic [ 31 : 0 ] _five; + } five_t; + + function five_t gimme_five (); + automatic five_t result; + + result._five = 5; + + return result; + endfunction + + localparam five_t FIVE = gimme_five(); + + initial begin + if (FIVE._five != 5) begin + $display(""%%Error: Got 0b%b instead of 5"", FIVE._five); + $stop; + end + + $write(""*-* All Finished *-*\ +""); + $finish; + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +// bug475 + +module t(); + + function real get_real_one; + input \t ignored; + get_real_one = 1.1; + endfunction + + localparam R_PARAM = get_real_one(1\'b0); + localparam R_PARAM_2 = (R_PARAM > 0); + + generate + initial begin +\t if (R_PARAM != 1.1) $stop; +\t if (R_PARAM_2 != 1\'b1) $stop; +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + endgenerate + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2009 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + parameter integer BLKS = 3; + + generate + for (genvar blkIdx=0; blkIdx < BLKS; blkIdx=blkIdx+1 ) begin : slice + +\t import ""DPI-C"" context function void dpi_genvarTest (); + + initial begin +\t dpi_genvarTest(); +\t $display(""slice = %0d : %m"", blkIdx); +\t end + end + endgenerate + + always @ (posedge clk) begin + $write(""*-* All Finished *-*\ +""); + $finish; + end + +endmodule +" +"// DESCRIPTION: Verilator: System Verilog test of case and if +// +// This code instantiates and runs a simple CPU written in System Verilog. +// +// This file ONLY is placed into the Public Domain, for any use, without +// warranty. + +// Contributed 2012 by M W Lund, Atmel Corporation and Jeremy Bennett, Embecosm. + + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + /*AUTOWIRE*/ + + // ************************************************************************** + // Regs and Wires + // ************************************************************************** + + reg \t rst; + integer rst_count; + + + st3_testbench st3_testbench_i (/*AUTOINST*/ +\t\t\t\t // Inputs +\t\t\t\t .clk\t\t\t(clk), +\t\t\t\t .rst\t\t\t(rst)); + + // ************************************************************************** + // Reset Generation + // ************************************************************************** + + initial begin + rst = 1\'b1; + rst_count = 0; + end + + always @( posedge clk ) begin + if (rst_count < 2) begin +\t rst_count++; + end + else begin +\t rst = 1\'b0; + end + end + + // ************************************************************************** + // Closing message + // ************************************************************************** + + final begin + $write(""*-* All Finished *-*\ +""); + end + +endmodule + + +module st3_testbench (/*AUTOARG*/ + // Inputs + clk, rst + ); + + input clk; + input rst; + + logic clk; + logic rst; + logic [8*16-1:0] wide_input_bus; + logic \t decrementA; // 0=Up-counting, 1=down-counting + logic \t dual_countA; // Advance counter by 2 steps at a time + logic \t cntA_en; // Enable Counter A + logic \t decrementB; // 0=Up-counting, 1=down-counting + logic \t dual_countB; // Advance counter by 2 steps at a time + logic \t cntB_en; // Enable counter B + logic [47:0] selected_out; + integer \t i; + + + initial begin + decrementA = 1\'b0; + dual_countA = 1\'b0; + cntA_en = 1\'b1; + decrementB = 1\'b0; + dual_countB = 1\'b0; + cntB_en = 1\'b1; + wide_input_bus = {8\'hf5, + 8\'hef, + 8\'hd5, + 8\'hc5, + 8\'hb5, + 8\'ha5, + 8\'h95, + 8\'h85, + 8\'ha7, + 8\'ha6, + 8\'ha5, + 8\'ha4, + 8\'ha3, + 8\'ha2, + 8\'ha1, + 8\'ha0}; + i = 0; + end + + + simple_test_3 + simple_test_3_i + (// Outputs +\t.selected_out (selected_out[47:0]), +\t// Inputs +\t.wide_input_bus (wide_input_bus[8*16-1:0]), +\t.rst (rst), +\t.clk (clk), +\t.decrementA (decrementA), +\t.dual_countA (dual_countA), +\t.cntA_en (cntA_en), +\t.decrementB (decrementB), +\t.dual_countB (dual_countB), +\t.cntB_en (cntB_en)); + + + // Logic to print outputs and then finish. + always @(posedge clk) begin + if (i < 50) begin +`ifdef TEST_VERBOSE +\t $display(""%x"", simple_test_3_i.cntA_reg ,""%x"", +\t\t simple_test_3_i.cntB_reg ,"" "", ""%x"", selected_out); +`endif +\t i <= i + 1; + end + else begin +\t $finish(); + end + end // always @ (posedge clk) + +endmodule + + +// Module testing: +// - Unique case +// - Priority case +// - Unique if +// - ++, --, =- and =+ operands. + +module simple_test_3 + (input logic [8*16-1:0] wide_input_bus, + input logic \t rst, + input logic \t clk, + // Counter A + input logic \t decrementA, // 0=Up-counting, 1=down-counting + input logic \t dual_countA, // Advance counter by 2 steps at a time + input logic \t cntA_en, // Enable Counter A + // Counter B + input logic \t decrementB, // 0=Up-counting, 1=down-counting + input logic \t dual_countB, // Advance counter by 2 steps at a time + input logic \t cntB_en, // Enable counter B + + // Outputs + output logic [47:0] selected_out); + + // Declarations + logic [3:0] \t cntA_reg; // Registered version of cntA + logic [3:0] \t cntB_reg; // Registered version of cntA + + + counterA + counterA_inst + (/*AUTOINST*/ +\t// Outputs +\t.cntA_reg\t\t\t(cntA_reg[3:0]), +\t// Inputs +\t.decrementA\t\t\t(decrementA), +\t.dual_countA\t\t\t(dual_countA), +\t.cntA_en\t\t\t(cntA_en), +\t.clk\t\t\t\t(clk), +\t.rst\t\t\t\t(rst)); + + counterB + counterB_inst + (/*AUTOINST*/ +\t// Outputs +\t.cntB_reg\t\t\t(cntB_reg[3:0]), +\t// Inputs +\t.decrementB\t\t\t(decrementB), +\t.dual_countB\t\t\t(dual_countB), +\t.cntB_en\t\t\t(cntB_en), +\t.clk\t\t\t\t(clk), +\t.rst\t\t\t\t(rst)); + + simple_test_3a + sta + (.wide_input_bus (wide_input_bus), +\t.selector (cntA_reg), +\t.selected_out (selected_out[7:0])); + + simple_test_3b + stb + (.wide_input_bus (wide_input_bus), +\t.selector (cntA_reg), +\t.selected_out (selected_out[15:8])); + + simple_test_3c + stc + (.wide_input_bus (wide_input_bus), +\t.selector (cntB_reg), +\t.selected_out (selected_out[23:16])); + + simple_test_3d + std + (.wide_input_bus (wide_input_bus), +\t.selector (cntB_reg), +\t.selected_out (selected_out[31:24])); + + simple_test_3e + ste + (.wide_input_bus (wide_input_bus), +\t.selector (cntB_reg), +\t.selected_out (selected_out[39:32])); + + simple_test_3f + stf + (.wide_input_bus (wide_input_bus), +\t.selector (cntB_reg), +\t.selected_out (selected_out[47:40])); + + +endmodule // simple_test_3 + + +module counterA + (output logic [3:0] cntA_reg, // Registered version of cntA + input logic decrementA, // 0=Up-counting, 1=down-counting + input logic dual_countA, // Advance counter by 2 steps at a time + input logic cntA_en, // Enable Counter A + input logic clk, // Clock + input logic rst); // Synchronous reset + + + + logic [3:0] cntA; // combinational count variable. + + // Counter A + // Sequential part of counter CntA + always_ff @(posedge clk) + begin +\tcntA_reg <= cntA; + end + + // Combinational part of counter + // Had to be split up to test C-style update, as there are no + // non-blocking version like -<= + always_comb + if (rst) + cntA = 0; + else begin + cntA = cntA_reg; // Necessary to avoid latch + if (cntA_en) begin + if (decrementA) + if (dual_countA) + //cntA = cntA - 2; + cntA -= 2; + else + //cntA = cntA - 1; + cntA--; + else + if (dual_countA) + //cntA = cntA + 2; + cntA += 2; + else + //cntA = cntA + 1; + cntA++; + end // if (cntA_en) + end +endmodule // counterA + + +module counterB + (output logic [3:0] cntB_reg, // Registered version of cntA + input logic decrementB, // 0=Up-counting, 1=down-counting + input logic dual_countB, // Advance counter by 2 steps at a time + input logic cntB_en, // Enable counter B + input logic clk, // Clock + input logic rst); // Synchronous reset + + // Counter B - tried to write sequential only, but ended up without + // SystemVerilog. + + always_ff @(posedge clk) begin + if (rst) + cntB_reg <= 0; + else + if (cntB_en) begin + if (decrementB) + if (dual_countB) + cntB_reg <= cntB_reg - 2; + else + cntB_reg <= cntB_reg - 1; + // Attempts to write in SystemVerilog: + else + if (dual_countB) + cntB_reg <= cntB_reg + 2; + else + cntB_reg <= cntB_reg + 1; + // Attempts to write in SystemVerilog: + end + end // always_ff @ +endmodule + + +// A multiplexor in terms of look-up +module simple_test_3a + (input logic [8*16-1:0] wide_input_bus, + input logic [3:0] selector, + output logic [7:0] selected_out); + + + always_comb + selected_out = {wide_input_bus[selector*8+7], + wide_input_bus[selector*8+6], + wide_input_bus[selector*8+5], + wide_input_bus[selector*8+4], + wide_input_bus[selector*8+3], + wide_input_bus[selector*8+2], + wide_input_bus[selector*8+1], + wide_input_bus[selector*8]}; + +endmodule // simple_test_3a + + +// A multiplexer in terms of standard case +module simple_test_3b + (input logic [8*16-1:0] wide_input_bus, + input logic [3:0] selector, + output logic [7:0] selected_out); + + + always_comb begin + case (selector) + 4\'h0: selected_out = wide_input_bus[ 7: 0]; + 4\'h1: selected_out = wide_input_bus[ 15: 8]; + 4\'h2: selected_out = wide_input_bus[ 23: 16]; + 4\'h3: selected_out = wide_input_bus[ 31: 24]; + 4\'h4: selected_out = wide_input_bus[ 39: 32]; + 4\'h5: selected_out = wide_input_bus[ 47: 40]; + 4\'h6: selected_out = wide_input_bus[ 55: 48]; + 4\'h7: selected_out = wide_input_bus[ 63: 56]; + 4\'h8: selected_out = wide_input_bus[ 71: 64]; + 4\'h9: selected_out = wide_input_bus[ 79: 72]; + 4\'ha: selected_out = wide_input_bus[ 87: 80]; + 4\'hb: selected_out = wide_input_bus[ 95: 88]; + 4\'hc: selected_out = wide_input_bus[103: 96]; + 4\'hd: selected_out = wide_input_bus[111:104]; + 4\'he: selected_out = wide_input_bus[119:112]; + 4\'hf: selected_out = wide_input_bus[127:120]; + endcase // case (selector) + + end + +endmodule // simple_test_3b + + +// A multiplexer in terms of unique case +module simple_test_3c + (input logic [8*16-1:0] wide_input_bus, + input logic [3:0] selector, + output logic [7:0] selected_out); + + + always_comb begin + unique case (selector) + 4\'h0: selected_out = wide_input_bus[ 7: 0]; + 4\'h1: selected_out = wide_input_bus[ 15: 8]; + 4\'h2: selected_out = wide_input_bus[ 23: 16]; + 4\'h3: selected_out = wide_input_bus[ 31: 24]; + 4\'h4: selected_out = wide_input_bus[ 39: 32]; + 4\'h5: selected_out = wide_input_bus[ 47: 40]; + 4\'h6: selected_out = wide_input_bus[ 55: 48]; + 4\'h7: selected_out = wide_input_bus[ 63: 56]; + 4\'h8: selected_out = wide_input_bus[ 71: 64]; + 4\'h9: selected_out = wide_input_bus[ 79: 72]; + 4\'ha: selected_out = wide_input_bus[ 87: 80]; + 4\'hb: selected_out = wide_input_bus[ 95: 88]; + 4\'hc: selected_out = wide_input_bus[103: 96]; + 4\'hd: selected_out = wide_input_bus[111:104]; + 4\'he: selected_out = wide_input_bus[119:112]; + 4\'hf: selected_out = wide_input_bus[127:120]; + endcase // case (selector) + + end + +endmodule // simple_test_3c + + +// A multiplexer in terms of unique if +module simple_test_3d + (input logic [8*16-1:0] wide_input_bus, + input logic [3:0] selector, + output logic [7:0] selected_out); + + + always_comb begin + unique if (selector == 4\'h0) selected_out = wide_input_bus[ 7: 0]; + else if (selector == 4\'h1) selected_out = wide_input_bus[ 15: 8]; + else if (selector == 4\'h2) selected_out = wide_input_bus[ 23: 16]; + else if (selector == 4\'h3) selected_out = wide_input_bus[ 31: 24]; + else if (selector == 4\'h4) selected_out = wide_input_bus[ 39: 32]; + else if (selector == 4\'h5) selected_out = wide_input_bus[ 47: 40]; + else if (selector == 4\'h6) selected_out = wide_input_bus[ 55: 48]; + else if (selector == 4\'h7) selected_out = wide_input_bus[ 63: 56]; + else if (selector == 4\'h8) selected_out = wide_input_bus[ 71: 64]; + else if (selector == 4\'h9) selected_out = wide_input_bus[ 79: 72]; + else if (selector == 4\'ha) selected_out = wide_input_bus[ 87: 80]; + else if (selector == 4\'hb) selected_out = wide_input_bus[ 95: 88]; + else if (selector == 4\'hc) selected_out = wide_input_bus[103: 96]; + else if (selector == 4\'hd) selected_out = wide_input_bus[111:104]; + else if (selector == 4\'he) selected_out = wide_input_bus[119:112]; + else if (selector == 4\'hf) selected_out = wide_input_bus[127:120]; + end + +endmodule // simple_test_3d + + +// Test of priority case +// Note: This does NOT try to implement the same function as above. +module simple_test_3e + (input logic [8*16-1:0] wide_input_bus, + input logic [3:0] selector, + output logic [7:0] selected_out); + + + always_comb begin + priority case (1\'b1) + selector[0]: selected_out = wide_input_bus[ 7: 0]; // Bit 0 has highets priority + selector[2]: selected_out = wide_input_bus[ 39: 32]; // Note 2 higher priority than 1 + selector[1]: selected_out = wide_input_bus[ 23: 16]; // Note 1 lower priority than 2 + selector[3]: selected_out = wide_input_bus[ 71: 64]; // Bit 3 has lowest priority + default: selected_out = wide_input_bus[127:120]; // for selector = 0. + endcase // case (selector) + + end + +endmodule // simple_test_3e + + +// Test of ""inside"" +// Note: This does NOT try to implement the same function as above. +// Note: Support for ""inside"" is a separate Verilator feature request, so is +// not used inside a this version of the test. +module simple_test_3f + (input logic [8*16-1:0] wide_input_bus, + input logic [3:0] selector, + output logic [7:0] selected_out); + + + always_comb begin +/* -----\\/----- EXCLUDED -----\\/----- + if ( selector[3:0] inside { 4\'b?00?, 4\'b1100}) // Matching 0000, 0001, 1000, 1100, 1001 +\t// if ( selector[3:2] inside { 2\'b?0, selector[1:0]}) + selected_out = wide_input_bus[ 7: 0]; + else + -----/\\----- EXCLUDED -----/\\----- */ + /* verilator lint_off CASEOVERLAP */ + priority casez (selector[3:0]) + 4\'b0?10: selected_out = wide_input_bus[ 15: 8]; // Matching 0010 and 0110 + 4\'b0??0: selected_out = wide_input_bus[ 23: 16]; // Overlap: only 0100 remains (0000 in ""if"" above) + 4\'b0100: selected_out = wide_input_bus[ 31: 24]; // Overlap: Will never occur + default: selected_out = wide_input_bus[127:120]; // Remaining 0011,0100,0101,0111,1010,1011,1101,1110,1111 +\tendcase // case (selector) + /* verilator lint_on CASEOVERLAP */ + end + +endmodule // simple_test_3f +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2006 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer j; + integer hit_count; + reg [63:0] cam_lookup_hit_vector; + + strings strings (); + + task show; + input [8*8-1:0] str; + reg [7:0] char; + integer \t loc; + begin +\t $write(""[%0t] "",$time); +\t strings.stringStart(8*8-1); +\t for (char = strings.stringByte(str); !strings.isNull(char); char = strings.stringByte(str)) begin +\t $write(""%c"",char); +\t end +\t $write(""\ +""); + end + endtask + + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin +\t cyc <= cyc + 1; +\t if (cyc==1) begin +\t show(""hello\\000xx""); +\t end +\t if (cyc==2) begin +\t show(""world\\000xx""); +\t end +\t if (cyc==4) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; +\t end + end + end + +endmodule + +module strings; + // **NOT** reentrant, just a test! + integer index; + task stringStart; + input [31:0] bits; + begin +\t index = (bits-1)/8; + end + endtask + + function isNull; + input [7:0] chr; + isNull = (chr == 8\'h0); + endfunction + + function [7:0] stringByte; + input [8*8-1:0] str; + begin +\t if (index<=0) stringByte=8\'h0; +\t else stringByte = str[index*8 +: 8]; +\t index = index - 1; + end + endfunction +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2007 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer \tcyc=0; + + Testit testit (/*AUTOINST*/ +\t\t // Inputs +\t\t .clk\t\t\t(clk)); + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==0) begin + end + else if (cyc<10) begin + end + else if (cyc<90) begin + end + else if (cyc==99) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end + +endmodule + +module Testit (clk); + input clk; + + genvar igen; + generate + for (igen=0; igen<0; igen=igen+1) begin : test_gen +\t always @ (posedge clk) begin +\t $display(""igen1 = %d"", igen); +\t $stop; +\t end + end + endgenerate + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t; + + // Check that the lint_on is obeyed. + // verilator lint_off VARHIDDEN + // verilator lint_on VARHIDDEN + + integer top; + + task x; + output top; + begin end + endtask + + initial begin + begin: lower +\t integer top; + end + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + logic use_AnB; + logic [1:0] active_command [8:0]; + logic [1:0] command_A [8:0]; + logic [1:0] command_B [8:0]; + + logic [1:0] active_command2 [8:0]; + logic [1:0] command_A2 [8:0]; + logic [1:0] command_B2 [8:0]; + + logic [1:0] active_command3 [1:0][2:0][3:0]; + logic [1:0] command_A3 [1:0][2:0][3:0]; + logic [1:0] command_B3 [1:0][2:0][3:0]; + + logic [2:0] use_A4nB4; + logic [8:0][1:0] active_command4; + logic [8:0][1:0] command_A4; + logic [8:0][1:0] command_B4; + + logic [8:0] pipe1\t [7:0]; + logic [8:0] pipe1_input; + + integer cyc; + + assign active_command[8:0] = (use_AnB) ? command_A[8:0] : command_B[8:0]; + assign active_command2 = (use_AnB) ? command_A2 : command_B2; + // Illegal to have [1:0][x:y] here - IEEE only allows single dimension slicing + assign active_command3[1:0] = (use_AnB) ? command_A3[1:0] : command_B3[1:0]; + + // Check we can cope with things other than packed arrays + assign active_command4 = (use_A4nB4[0]) ? command_A4 : command_B4; + + always @ (posedge clk) begin + pipe1_input <= pipe1_input + 1; + pipe1[0] <= pipe1_input; + pipe1[7:1] <= pipe1[6:0]; + end + + logic [3:0][13:0] iq_read_data [15:0]; + logic [3:0][13:0] iq_data; + logic [3:0] sel; + + assign iq_data = iq_read_data[sel]; + + always @ (posedge clk) begin + sel = sel + 1; + end + + initial begin + cyc = 0; + use_AnB = 0; + for (int i = 0; i < 7; ++i) begin +\t command_A[i] = 2\'b00; +\t command_B[i] = 2\'b11; +\t command_A2[i] = 2\'b00; +\t command_B2[i] = 2\'b11; +\t pipe1_input = 9\'b0; + end + for (int i = 0; i < 2; ++i) begin +\t for (int j = 0; j < 3; ++j) begin +\t for (int k = 0; k < 4; ++k) begin +\t command_A3[i][j][k] = 2\'b00; +\t command_B3[i][j][k] = 2\'b11; +\t end +\t end + end + end + + always @ (posedge clk) begin + use_AnB <= ~use_AnB; + cyc <= cyc + 1; + if (use_AnB) begin +\t if (active_command[3] != 2\'b00) begin +\t $stop; +\t end +\t if (active_command2[3] != 2\'b00) begin +\t $stop; +\t end +\t if (active_command3[0][1][2] != 2\'b00) begin +\t $stop; +\t end + end + if (!use_AnB) begin +\t if (active_command[3] != 2\'b11) begin +\t $stop; +\t end +\t if (active_command2[3] != 2\'b11) begin +\t $stop; +\t end + end + end + + logic [8:0] last_pipe; + always @(posedge clk) begin + if (cyc < 3) begin +\t last_pipe <= pipe1[0]; + end + else begin +\t if (last_pipe + 1 != pipe1[0]) begin +\t $stop; +\t end +\t else begin +\t last_pipe <= pipe1[0]; +\t end + end + if (cyc > 10) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end + +endmodule : t +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg [7:0] crc; + + // Build up assignments + wire [7:0] bitrev; + assign bitrev[7] = crc[0]; + assign bitrev[6] = crc[1]; + assign bitrev[5] = crc[2]; + assign bitrev[4] = crc[3]; + assign bitrev[0] = crc[7]; + assign bitrev[1] = crc[6]; + assign bitrev[2] = crc[5]; + assign bitrev[3] = crc[4]; + + // Build up always assignments + reg [7:0] bitrevb; + always @ (/*AS*/crc) begin + bitrevb[7] = crc[0]; + bitrevb[6] = crc[1]; + bitrevb[5] = crc[2]; + bitrevb[4] = crc[3]; + bitrevb[0] = crc[7]; + bitrevb[1] = crc[6]; + bitrevb[2] = crc[5]; + bitrevb[3] = crc[4]; + end + + // Build up always assignments + reg [7:0] bitrevr; + always @ (posedge clk) begin + bitrevr[7] <= crc[0]; + bitrevr[6] <= crc[1]; + bitrevr[5] <= crc[2]; + bitrevr[4] <= crc[3]; + bitrevr[0] <= crc[7]; + bitrevr[1] <= crc[6]; + bitrevr[2] <= crc[5]; + bitrevr[3] <= crc[4]; + end + + always @ (posedge clk) begin + if (cyc!=0) begin +\t cyc<=cyc+1; +\t //$write(""cyc=%0d crc=%x r=%x\ +"", cyc, crc, bitrev); +\t crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; +\t if (cyc==1) begin +\t crc <= 8\'hed; +\t end +\t if (cyc==2 && bitrev!=8\'hb7) $stop; +\t if (cyc==3 && bitrev!=8\'h5b) $stop; +\t if (cyc==4 && bitrev!=8\'h2d) $stop; +\t if (cyc==5 && bitrev!=8\'h16) $stop; +\t if (cyc==6 && bitrev!=8\'h8b) $stop; +\t if (cyc==7 && bitrev!=8\'hc5) $stop; +\t if (cyc==8 && bitrev!=8\'he2) $stop; +\t if (cyc==9 && bitrev!=8\'hf1) $stop; +\t if (bitrevb != bitrev) $stop; +\t if (cyc==3 && bitrevr!=8\'hb7) $stop; +\t if (cyc==4 && bitrevr!=8\'h5b) $stop; +\t if (cyc==5 && bitrevr!=8\'h2d) $stop; +\t if (cyc==6 && bitrevr!=8\'h16) $stop; +\t if (cyc==7 && bitrevr!=8\'h8b) $stop; +\t if (cyc==8 && bitrevr!=8\'hc5) $stop; +\t if (cyc==9) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; +\t end + end + end +endmodule +" +"// DESCRIPTION: Verilator: Simple test of unoptflat +// +// Simple demonstration of an UNOPTFLAT combinatorial loop, using 3 bits. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Jeremy Bennett. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + wire [2:0] x; + + initial begin + x = 3\'b000; + end + + assign x[1:0] = { x[0], clk }; + assign x[2:1] = { clk, x[1] }; + + always @(posedge clk or negedge clk) begin + +`ifdef TEST_VERBOSE + $write(""x = %x\ +"", x); +`endif + + if (x[1] != 0) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end + +endmodule // t +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + // surefire lint_off ASWEBB + // surefire lint_off ASWEMB + // surefire lint_off STMINI + // surefire lint_off CSEBEQ + + input clk; + + reg [7:0] a_to_clk_levm3; + reg [7:0] b_to_clk_levm1; + reg [7:0] c_com_levs10; + reg [7:0] d_to_clk_levm2; + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [7:0]\t\tm_from_clk_lev1_r;\t// From a of t_order_a.v + wire [7:0]\t\tn_from_clk_lev2;\t// From a of t_order_a.v + wire [7:0]\t\to_from_com_levs11;\t// From a of t_order_a.v + wire [7:0]\t\to_from_comandclk_levs12;// From a of t_order_a.v + wire [7:0]\t\to_subfrom_clk_lev2;\t// From b of t_order_b.v + // End of automatics + + reg [7:0] cyc; initial cyc=0; + + t_order_a a ( +\t\t.one\t\t\t(8\'h1), +\t\t/*AUTOINST*/ +\t\t// Outputs +\t\t.m_from_clk_lev1_r\t(m_from_clk_lev1_r[7:0]), +\t\t.n_from_clk_lev2\t(n_from_clk_lev2[7:0]), +\t\t.o_from_com_levs11\t(o_from_com_levs11[7:0]), +\t\t.o_from_comandclk_levs12(o_from_comandclk_levs12[7:0]), +\t\t// Inputs +\t\t.clk\t\t\t(clk), +\t\t.a_to_clk_levm3\t\t(a_to_clk_levm3[7:0]), +\t\t.b_to_clk_levm1\t\t(b_to_clk_levm1[7:0]), +\t\t.c_com_levs10\t\t(c_com_levs10[7:0]), +\t\t.d_to_clk_levm2\t\t(d_to_clk_levm2[7:0])); + + t_order_b b ( +\t\t/*AUTOINST*/ +\t\t// Outputs +\t\t.o_subfrom_clk_lev2\t(o_subfrom_clk_lev2[7:0]), +\t\t// Inputs +\t\t.m_from_clk_lev1_r\t(m_from_clk_lev1_r[7:0])); + + reg [7:0] o_from_com_levs12; + reg [7:0] o_from_com_levs13; + always @ (/*AS*/o_from_com_levs11) begin + o_from_com_levs12 = o_from_com_levs11 + 8\'h1; + o_from_com_levs12 = o_from_com_levs12 + 8\'h1; // Test we can add to self and optimize + o_from_com_levs13 = o_from_com_levs12; + end + + reg \tsepassign_in; + // verilator lint_off UNOPTFLAT + wire [3:0] \tsepassign; + // verilator lint_on UNOPTFLAT + + // verilator lint_off UNOPT + assign #0.1\tsepassign[0]\t= 0, + \t \tsepassign[1]\t= sepassign[2], + \t \tsepassign[2]\t= sepassign[3], + \t \tsepassign[3]\t= sepassign_in; + wire [7:0] \to_subfrom_clk_lev3 = o_subfrom_clk_lev2; + // verilator lint_on UNOPT + + always @ (posedge clk) begin + cyc <= cyc+8\'d1; + sepassign_in <= 0; + if (cyc == 8\'d1) begin +\t a_to_clk_levm3 <= 0; +\t d_to_clk_levm2 <= 1; +\t b_to_clk_levm1 <= 1; +\t c_com_levs10 <= 2; +\t sepassign_in <= 1; + end + if (cyc == 8\'d2) begin +\t if (sepassign !== 4\'b1110) $stop; + end + if (cyc == 8\'d3) begin + +\t $display(""%d %d %d %d"",m_from_clk_lev1_r, +\t\t n_from_clk_lev2, +\t\t o_from_com_levs11, +\t\t o_from_comandclk_levs12); + +\t if (m_from_clk_lev1_r !== 8\'h2) $stop; +\t if (o_subfrom_clk_lev3 !== 8\'h2) $stop; +\t if (n_from_clk_lev2 !== 8\'h2) $stop; +\t if (o_from_com_levs11 !== 8\'h3) $stop; +\t if (o_from_com_levs13 !== 8\'h5) $stop; +\t if (o_from_comandclk_levs12 !== 8\'h5) $stop; +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2007 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer \tcyc=0; + reg [63:0] \tcrc; + reg [63:0] \tsum; + + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; + wire \tnoswap = crc[32]; + wire \tnibble = crc[33]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] \t\tout;\t\t\t// From test of Test.v + wire [31:0] \t\tswapped;\t\t// From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ +\t // Outputs +\t .out\t\t\t(out[31:0]), +\t .swapped\t\t\t(swapped[31:0]), +\t // Inputs +\t .clk\t\t\t(clk), +\t .noswap\t\t\t(noswap), +\t .nibble\t\t\t(nibble), +\t .in\t\t\t(in[31:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {32\'h0, out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write(""[%0t] cyc==%0d crc=%x result=%x\ +"",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin +\t // Setup +\t crc <= 64\'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin +\t sum <= 64\'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin +\t $write(""*-* All Finished *-*\ +""); +\t $write(""[%0t] cyc==%0d crc=%x sum=%x\ +"",$time, cyc, crc, sum); +\t if (crc !== 64\'hc77bb9b3784ea091) $stop; +\t if (sum !== 64\'h89522c3f5e5ca324) $stop; +\t $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, swapped, + // Inputs + clk, noswap, nibble, in + ); + input clk; + + input noswap; + input nibble; + + input [31:0] in; + output [31:0] out; + output [31:0] swapped; + + function [7:0] EndianSwap; + input Nibble; + input [7:0] Data; + begin + EndianSwap = (Nibble ? { Data[0], Data[1], Data[2], Data[3], +\t\t\t\t Data[4], Data[5], Data[6], Data[7] } + : { 4\'h0, Data[0], Data[1], Data[2], Data[3] }); + end + endfunction + + assign out[31:24] = (noswap ? in[31:24] +\t\t\t: EndianSwap(nibble, in[31:24])); + assign out[23:16] = (noswap ? in[23:16] +\t\t\t: EndianSwap(nibble, in[23:16])); + assign out[15:8] = (noswap ? in[15:8] +\t\t\t: EndianSwap(nibble, in[15:8])); + assign out[7:0] = (noswap ? in[7:0] +\t\t\t: EndianSwap(nibble, in[7:0])); + + reg [31:0] swapped; + always @(posedge clk) begin + swapped[31:24] <= EndianSwap(nibble, in[31:24]); + swapped[23:16] <= EndianSwap(nibble, in[23:16]); + swapped[15:8] <= EndianSwap(nibble, in[15:8] ); + swapped[7:0] <= EndianSwap(nibble, in[7:0] ); + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// A test of the +verilog1995ext+ and +verilog2001ext+ flags. +// +// This source code contains constructs that are valid in Verilog 2001 and +// SystemVerilog 2005/2009, but not in Verilog 1995. So it should fail if we +// set the language to be 1995, but not 2001. +// +// Compile only test, so no need for ""All Finished"" output. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Jeremy Bennett. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + reg [1:0] \tres; + + // Instantiate the test + test test_i (/*AUTOINST*/ +\t // Outputs +\t .res\t\t\t(res), +\t // Inputs +\t .clk\t\t\t(clk), +\t .in\t\t\t(1\'b1)); + +endmodule + +module test (// Outputs +\t res, +\t // Inputs +\t clk, +\t in + ); + output [1:0] res; + input \t clk; + input \t in; + + // This is a Verilog 2001 test + generate + genvar i; + for (i=0; i<2; i=i+1) begin +\t always @(posedge clk) begin +\t res[i:i] <= in; +\t end + end + endgenerate +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +interface ifc; + integer value; +endinterface + +module t (/*AUTOARG*/ + // Inputs + clk + ); +`ifdef INLINE_A //verilator inline_module +`else //verilator no_inline_module +`endif + input clk; + integer cyc=1; + + ifc itop1a(); + ifc itop1b(); + ifc itop2a(); + ifc itop2b(); + + wrapper c1 (.isuba(itop1a), +\t\t.isubb(itop1b), +\t\t.i_valuea(14), +\t\t.i_valueb(15)); + wrapper c2 (.isuba(itop2a), +\t\t.isubb(itop2b), +\t\t.i_valuea(24), +\t\t.i_valueb(25)); + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==20) begin +\t if (itop1a.value != 14) $stop; +\t if (itop1b.value != 15) $stop; +\t if (itop2a.value != 24) $stop; +\t if (itop2b.value != 25) $stop; +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end +endmodule + +module wrapper + ( + ifc isuba, + ifc isubb, + input integer i_valuea, + input integer i_valueb + ); +`ifdef INLINE_B //verilator inline_module +`else //verilator no_inline_module +`endif + lower subsuba (.isub(isuba), .i_value(i_valuea)); + lower subsubb (.isub(isubb), .i_value(i_valueb)); +endmodule + +module lower + ( + ifc isub, + input integer i_value + ); +`ifdef INLINE_C //verilator inline_module +`else //verilator no_inline_module +`endif + always @* begin + isub.value = i_value; + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +module t (/*AUTOARG*/); + sub sub (); +endmodule + +module sub #(parameter WIDTH=X, parameter X=WIDTH) + (); +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + reg [3:0] counter = 0; + integer l2; + function log2 (input [3:0] x); + integer log2 = (x < 2) ? 1 : (x < 4) ? 2 : (x < 8) ? 3 : 4; + endfunction + always @(posedge clk) begin + counter <= counter + 1; + l2 <= log2(counter); + // bug589: This failed with (%Error: Internal Error: Function not underneath a statement): + $display(""log2(%d) == %d"", counter, log2(counter)); + // + $write(""*-* All Finished *-*\ +""); + $finish; + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003-2007 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg [15:0] m_din; + + // OK + reg [15:0] c_split_1, c_split_2, c_split_3, c_split_4, c_split_5; + always @ (posedge clk) begin + if (cyc==0) begin +\t /*AUTORESET*/ +\t // Beginning of autoreset for uninitialized flops +\t c_split_1 <= 16\'h0; +\t c_split_2 <= 16\'h0; +\t c_split_3 <= 16\'h0; +\t c_split_4 <= 0; +\t c_split_5 <= 0; +\t // End of automatics + end + else begin +\t c_split_1 <= m_din; +\t c_split_2 <= c_split_1; +\t c_split_3 <= c_split_2 & {16{(cyc!=0)}}; +\t if (cyc==1) begin +\t c_split_4 <= 16\'h4; +\t c_split_5 <= 16\'h5; +\t end +\t else begin +\t c_split_4 <= c_split_3; +\t c_split_5 <= c_split_4; +\t end + end + end + + // OK + reg [15:0] d_split_1, d_split_2; + always @ (posedge clk) begin + if (cyc==0) begin +\t /*AUTORESET*/ +\t // Beginning of autoreset for uninitialized flops +\t d_split_1 <= 16\'h0; +\t d_split_2 <= 16\'h0; +\t // End of automatics + end + else begin +\t d_split_1 <= m_din; +\t d_split_2 <= d_split_1; +\t d_split_1 <= ~m_din; + end + end + + // Not OK + always @ (posedge clk) begin + if (cyc==0) begin +\t /*AUTORESET*/ +\t // Beginning of autoreset for uninitialized flops +\t // End of automatics + end + else begin +\t $write("" foo %x"", m_din); +\t $write("" bar %x\ +"", m_din); + end + end + + // Not OK + reg [15:0] e_split_1, e_split_2; + always @ (posedge clk) begin + if (cyc==0) begin +\t /*AUTORESET*/ +\t // Beginning of autoreset for uninitialized flops +\t e_split_1 = 16\'h0; +\t e_split_2 = 16\'h0; +\t // End of automatics + end + else begin +\t e_split_1 = m_din; +\t e_split_2 = e_split_1; + end + end + + // Not OK + reg [15:0] f_split_1, f_split_2; + always @ (posedge clk) begin + if (cyc==0) begin +\t /*AUTORESET*/ +\t // Beginning of autoreset for uninitialized flops +\t f_split_1 = 16\'h0; +\t f_split_2 = 16\'h0; +\t // End of automatics + end + else begin +\t f_split_2 = f_split_1; +\t f_split_1 = m_din; + end + end + + always @ (posedge clk) begin + if (cyc!=0) begin +\t //$write("" C %d %x %x\ +"", cyc, c_split_1, c_split_2); +\t cyc<=cyc+1; +\t if (cyc==1) begin +\t m_din <= 16\'hfeed; +\t end +\t if (cyc==3) begin +\t end +\t if (cyc==4) begin +\t m_din <= 16\'he11e; +\t if (!(d_split_1==16\'h0112 && d_split_2==16\'h0112)) $stop; +\t if (!(e_split_1==16\'hfeed && e_split_2==16\'hfeed)) $stop; +\t if (!(f_split_1==16\'hfeed && f_split_2==16\'hfeed)) $stop; +\t end +\t if (cyc==5) begin +\t m_din <= 16\'he22e; +\t if (!(d_split_1==16\'h0112 && d_split_2==16\'h0112)) $stop; +\t // Two valid orderings, as we don\'t know which posedge clk gets evaled first +\t if (!(e_split_1==16\'hfeed && e_split_2==16\'hfeed) && !(e_split_1==16\'he11e && e_split_2==16\'he11e)) $stop; +\t if (!(f_split_1==16\'hfeed && f_split_2==16\'hfeed) && !(f_split_1==16\'he11e && f_split_2==16\'hfeed)) $stop; +\t end +\t if (cyc==6) begin +\t m_din <= 16\'he33e; +\t if (!(c_split_1==16\'he11e && c_split_2==16\'hfeed && c_split_3==16\'hfeed)) $stop; +\t if (!(d_split_1==16\'h1ee1 && d_split_2==16\'h0112)) $stop; +\t // Two valid orderings, as we don\'t know which posedge clk gets evaled first +\t if (!(e_split_1==16\'he11e && e_split_2==16\'he11e) && !(e_split_1==16\'he22e && e_split_2==16\'he22e)) $stop; +\t if (!(f_split_1==16\'he11e && f_split_2==16\'hfeed) && !(f_split_1==16\'he22e && f_split_2==16\'he11e)) $stop; +\t end +\t if (cyc==7) begin +\t m_din <= 16\'he44e; +\t if (!(c_split_1==16\'he22e && c_split_2==16\'he11e && c_split_3==16\'hfeed)) $stop; +\t end +\t if (cyc==8) begin +\t m_din <= 16\'he55e; +\t if (!(c_split_1==16\'he33e && c_split_2==16\'he22e && c_split_3==16\'he11e +\t\t && c_split_4==16\'hfeed && c_split_5==16\'hfeed)) $stop; +\t end +\t if (cyc==9) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; +\t end + end + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +package pkg; + typedef enum bit [1:0] + { + E__NOT = 2\'b00, + E__VAL = 2\'b11 + } E_t; +endpackage + +module t; + reg [1:0] ttype; + reg \t m; + + enum bit [1:0] { LOCAL } l; + + always @ (m or 1\'b0 or LOCAL) begin + // Don\'t complain about constants in sensitivity lists + end + + initial begin + ttype = pkg::E__NOT; + m = (ttype == pkg::E__VAL); + if (m != 1\'b0) $stop; + + ttype = pkg::E__VAL; + m = (ttype == pkg::E__VAL); + if (m != 1\'b1) $stop; + + $write(""*-* All Finished *-*\ +""); + $finish; + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2009 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +`ifdef VCS + `define NO_SHORTREAL +`endif +`ifdef NC + `define NO_SHORTREAL +`endif +`ifdef VERILATOR // Unsupported + `define NO_SHORTREAL +`endif + +module t (/*AUTOARG*/); + + // Note these are NOT pure. + import ""DPI-C"" function int dpii_clear (); + import ""DPI-C"" function int dpii_count (input int ctr); + import ""DPI-C"" function bit dpii_inc0 (input int ctr); + import ""DPI-C"" function bit dpii_inc1 (input int ctr); + import ""DPI-C"" function bit dpii_incx (input int ctr, input bit value); + + integer i; + integer j; + integer k; + bit \t b; + integer errors; + + task check1(integer line, bit got, bit ex); + if (got != ex) begin +\t $display(""%%Error: Line %0d: Bad result, got=%0d expect=%0d"",line,got,ex); +\t errors++; + end + endtask + task check(integer line, int got, int ex); + if (got != ex) begin +\t $display(""%%Error: Line %0d: Bad result, got=%0d expect=%0d"",line,got,ex); +\t errors++; + end + endtask + + // Test loop + initial begin + // bug963 + dpii_clear(); + j = 0; + for (i=0; i<64; i++) begin +\t if (i[0]) +\t j = 0; +\t else +\t j = {31\'b0, dpii_inc1(0)}; +\t k = k + j; + end + $write(""%x\ +"",k); + check (`__LINE__, dpii_count(0), 32); + + if (|errors) $stop; + $write(""*-* All Finished *-*\ +""); + $finish; + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2011 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +`define is_near_real(a,b) ($abs((a)-(b)) < (((a)/(b))*0.0001)) + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer i; + reg [63:0] b; + real r, r2; + integer \tcyc=0; + + realtime uninit; + initial if (uninit != 0.0) $stop; + + sub_cast_bug374 sub (.cyc5(cyc[4:0]), .*); + + initial begin + if (1_00_0.0_1 != 1000.01) $stop; + // rtoi truncates + if ($rtoi(36.7) != 36) $stop; + if ($rtoi(36.5) != 36) $stop; + if ($rtoi(36.4) != 36) $stop; + // casting rounds + if ((integer \'(36.7)) != 37) $stop; + if ((integer \'(36.5)) != 37) $stop; + if ((integer \'(36.4)) != 36) $stop; + // assignment rounds + // verilator lint_off REALCVT + i = 36.7; if (i != 37) $stop; + i = 36.5; if (i != 37) $stop; + i = 36.4; if (i != 36) $stop; + r = 10\'d38; if (r!=38.0) $stop; + // verilator lint_on REALCVT + // operators + if ((-(1.5)) != -1.5) $stop; + if ((+(1.5)) != 1.5) $stop; + if (((1.5)+(1.25)) != 2.75) $stop; + if (((1.5)-(1.25)) != 0.25) $stop; + if (((1.5)*(1.25)) != 1.875) $stop; + if (((1.5)/(1.25)) != 1.2) $stop; + // + if (((1.5)==(2)) != 1\'b0) $stop; // note 2 becomes real 2.0 + if (((1.5)!=(2)) != 1\'b1) $stop; + if (((1.5)> (2)) != 1\'b0) $stop; + if (((1.5)>=(2)) != 1\'b0) $stop; + if (((1.5)< (2)) != 1\'b1) $stop; + if (((1.5)<=(2)) != 1\'b1) $stop; + if (((1.5)==(1.5)) != 1\'b1) $stop; + if (((1.5)!=(1.5)) != 1\'b0) $stop; + if (((1.5)> (1.5)) != 1\'b0) $stop; + if (((1.5)>=(1.5)) != 1\'b1) $stop; + if (((1.5)< (1.5)) != 1\'b0) $stop; + if (((1.5)<=(1.5)) != 1\'b1) $stop; + if (((1.6)==(1.5)) != 1\'b0) $stop; + if (((1.6)!=(1.5)) != 1\'b1) $stop; + if (((1.6)> (1.5)) != 1\'b1) $stop; + if (((1.6)>=(1.5)) != 1\'b1) $stop; + if (((1.6)< (1.5)) != 1\'b0) $stop; + if (((1.6)<=(1.5)) != 1\'b0) $stop; + // + if (((0.0)?(2.0):(1.1)) != 1.1) $stop; + if (((1.5)?(2.0):(1.1)) != 2.0) $stop; + // + if (!1.7) $stop; + if (!(!0.0)) $stop; + if (1.8 && 0.0) $stop; + if (!(1.8 || 0.0)) $stop; + // + i=0; + for (r=1.0; r<2.0; r=r+0.1) i++; + if (i!=10) $stop; + end + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write(""[%0t] cyc==%0d crc=%x result=%x\ +"",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + if (cyc==0) begin +\t // Setup + end + else if (cyc<90) begin +\t if ($time != {32\'h0, $rtoi($realtime)}) $stop; +\t if ($itor(cyc) != cyc) $stop; +\t //Unsup: if ((real `($time)) != $realtime) $stop; +\t r = $itor(cyc*2); +\t i = $rtoi(r); +\t if (i!=cyc*2) $stop; +\t // +\t r = $itor(cyc)/1.5; +\t b = $realtobits(r); +\t r2 = $bitstoreal(b); +\t if (r != r2) $stop; +\t // +\t // Trust the integer math as a comparison +\t r = $itor(cyc); +\t if ($rtoi(-r) != -cyc) $stop; +\t if ($rtoi(+r) != cyc) $stop; +\t if ($rtoi(r+2.0) != (cyc+2)) $stop; +\t if ($rtoi(r-2.0) != (cyc-2)) $stop; +\t if ($rtoi(r*2.0) != (cyc*2)) $stop; +\t if ($rtoi(r/2.0) != (cyc/2)) $stop; +\t r2 = (2.0/(r-60)); // When zero, result indeterminate, but no crash +\t // +\t r2 = $itor(cyc); +\t case (r) +\t (r2-1.0): $stop; +\t r2: ; +\t default: $stop; +\t endcase +\t // +\t r = $itor(cyc); +\t if ((r==50.0) != (cyc==50)) $stop; +\t if ((r!=50.0) != (cyc!=50)) $stop; +\t if ((r> 50.0) != (cyc> 50)) $stop; +\t if ((r>=50.0) != (cyc>=50)) $stop; +\t if ((r< 50.0) != (cyc< 50)) $stop; +\t if ((r<=50.0) != (cyc<=50)) $stop; +\t // +\t if ($rtoi((r-50.0) ? 10.0 : 20.0) +\t != (((cyc-50)!=0) ? 10 : 20)) $stop; +\t // +\t if ((!(r-50.0)) != (!((cyc-50) != 0))) $stop; + end + else if (cyc==99) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end +endmodule + +module sub_cast_bug374(input clk, input [4:0] cyc5); + integer i; + + always @(posedge clk) begin + i <= integer\'(cyc5); + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer \tcyc=0; + reg [63:0] \tcrc; + reg [63:0] \tsum; + + // Aggregate outputs into a single result vector + //wire [31:0] \tpow32b = {24\'h0,crc[15:8]}**crc[7:0]; // Overflows + wire [3:0] \tpow4b = crc[7:4]**crc[3:0]; + wire [63:0] \tresult = {60\'h0, pow4b}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write(""[%0t] cyc==%0d crc=%x result=%x\ +"",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin +\t // Setup +\t crc <= 64\'h5aef0c8d_d70a4497; +\t sum <= 64\'h0; + end + else if (cyc<10) begin +\t sum <= 64\'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin +\t $write(""[%0t] cyc==%0d crc=%x sum=%x\ +"",$time, cyc, crc, sum); +\t if (crc !== 64\'hc77bb9b3784ea091) $stop; +\t // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64\'h1fec4b2b71cf8024 +\t if (sum !== `EXPECTED_SUM) $stop; +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + passed, + // Inputs + clk, fastclk, reset_l + ); + + input clk /*verilator sc_clock*/; + input fastclk /*verilator sc_clock*/; + input reset_l; + output passed; + + reg [31:0] count_c; + reg [31:0] count_f; + + always @ (posedge clk) begin + if (!reset_l) begin +\t /*AUTORESET*/ +\t // Beginning of autoreset for uninitialized flops +\t count_c <= 32'h0; +\t // End of automatics + end else begin +\t count_c <= count_c + 1; + end + end + + always @ (posedge fastclk) begin + if (!reset_l) begin +\t /*AUTORESET*/ +\t // Beginning of autoreset for uninitialized flops +\t count_f <= 32'h0; +\t passed <= 1'h0; +\t // End of automatics + end else begin +\t count_f <= count_f + 1; +\t if (count_f == 5) passed <= 1'b1; + end + end + +endmodule +" +"// DESCRIPTION: Verilator: Simple test of unoptflat +// +// Trigger the DETECTARRAY error on packed structure. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Jie Xu. + +localparam ID_MSB = 1; + + +module t (/*AUTOARG*/ + // Inputs + clk, + res + ); + input clk; + output [8:0][8:0] res; + + logic a = 1\'b1; + logic [8:0] b [8:0]; // where the error is reported + logic [8:0][8:0] c; // where the error is reported + + // following just to make c as circular + assign c[0] = c[0] | a << 1; + assign b[0] = b[0] | a << 2; + + assign res[0] = c[0]; + assign res[1] = b[0]; + + + always @(posedge clk or negedge clk) begin + + if (res != 0) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t; + + integer p_i; + reg [7*8:1] p_str; + + initial begin + if ($test$plusargs(""PLUS"")!==1) $stop; + if ($test$plusargs(""PLUSNOT"")!==0) $stop; + if ($test$plusargs(""PL"")!==1) $stop; + //if ($test$plusargs("""")!==1) $stop; // Simulators differ in this answer + if ($test$plusargs(""NOTTHERE"")!==0) $stop; + + p_i = 10; + if ($value$plusargs(""NOTTHERE%d"", p_i)!==0) $stop; + if (p_i !== 10) $stop; + + if ($value$plusargs(""INT=%d"", p_i)!==1) $stop; + if (p_i !== 32\'d1234) $stop; + + if ($value$plusargs(""INT=%H"", p_i)!==1) $stop; // tests uppercase % also + if (p_i !== 32\'h1234) $stop; + + if ($value$plusargs(""INT=%o"", p_i)!==1) $stop; + if (p_i !== 32\'o1234) $stop; + + if ($value$plusargs(""IN%s"", p_str)!==1) $stop; + $display(""str=\'%s\'"",p_str); + if (p_str !== ""T=1234"") $stop; + + $write(""*-* All Finished *-*\ +""); + $finish; + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + integer \tcyc=0; + + reg [7:0] crc; + genvar g; + + wire [7:0] \tout_p1; + wire [15:0] \tout_p2; + wire [7:0] \tout_p3; + wire [7:0] \tout_p4; + + paramed #(.WIDTH(8), .MODE(0)) p1 (.in(crc), .out(out_p1)); + paramed #(.WIDTH(16), .MODE(1)) p2 (.in({crc,crc}), .out(out_p2)); + paramed #(.WIDTH(8), .MODE(2)) p3 (.in(crc), .out(out_p3)); + gencase #(.MODE(3)) \t p4 (.in(crc), .out(out_p4)); + + wire [7:0] \tout_ef; + enflop #(.WIDTH(8)) enf (.a(crc), .q(out_ef), .oe_e1(1\'b1), .clk(clk)); + + always @ (posedge clk) begin + //$write(""[%0t] cyc==%0d crc=%b %x %x %x %x %x\ +"",$time, cyc, crc, out_p1, out_p2, out_p3, out_p4, out_ef); + cyc <= cyc + 1; + crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; + if (cyc==0) begin +\t // Setup +\t crc <= 8\'hed; + end + else if (cyc==1) begin + end + else if (cyc==3) begin +\t if (out_p1 !== 8\'h2d) $stop; +\t if (out_p2 !== 16\'h2d2d) $stop; +\t if (out_p3 !== 8\'h78) $stop; +\t if (out_p4 !== 8\'h44) $stop; +\t if (out_ef !== 8\'hda) $stop; + end + else if (cyc==9) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end + +endmodule + +module gencase (/*AUTOARG*/ + // Outputs + out, + // Inputs + in + ); + parameter MODE = 0; + input [7:0] in; + output [7:0] out; + generate // : genblk1 + begin +\t case (MODE) +\t 2: mbuf mc [7:0] (.q(out[7:0]), .a({in[5:0],in[7:6]})); +\t default: mbuf mc [7:0] (.q(out[7:0]), .a({in[3:0],in[3:0]})); +\t endcase + end + endgenerate + +endmodule + +module paramed (/*AUTOARG*/ + // Outputs + out, + // Inputs + in + ); + parameter WIDTH = 1; + parameter MODE = 0; + input [WIDTH-1:0] in; + output [WIDTH-1:0] out; + + generate + if (MODE==0) initial $write(""Mode=0\ +""); + // No else + endgenerate + +`ifndef NC // for(genvar) unsupported + `ifndef ATSIM // for(genvar) unsupported + generate + // Empty loop body, local genvar + for (genvar j=0; j<3; j=j+1) begin end + // Ditto to make sure j has new scope + for (genvar j=0; j<5; j=j+1) begin end + endgenerate + `endif +`endif + + generate + endgenerate + + genvar \t i; + generate + if (MODE==0) begin +\t // Flip bitorder, direct assign method +\t for (i=0; i> ((`MUX1_SIZE*`MUX2_SIZE*j)+addr); +\t /* verilator lint_on WIDTH */ + end + end + + // Run the test loop. This just increments the address + integer i, result; + always @ (posedge clk) begin + // initial the input data with random values + if (addr == 0) begin +\t result = 1; +\t datai = 0; +\t for(i=0; i<`MUX1_SIZE*`MUX2_SIZE; i=i+1) begin +\t /* verilator lint_off WIDTH */ +\t datai = (datai << `DATA_WIDTH) | ($random & {`DATA_WIDTH{1\'b1}}); +\t /* verilator lint_on WIDTH */ +\t end + end + + addr <= addr + 1; + if (datao_check != datao) begin +\t result = 0; +\t $stop; + end + + $write(""Addr=%d datao_check=%d datao=%d\ +"", addr, datao_check, datao); + // only run the first 10 addresses for now + if (addr > 10) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end + +endmodule + +module mux4096 + (input [`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0] datai, + input [`ADDR_WIDTH-1:0] addr, + output [`DATA_WIDTH-1:0] datao + ); + + // DATA_WIDTH instantiations of mux4096_1bit + mux4096_1bit mux4096_1bit[`DATA_WIDTH-1:0] + (.addr(addr), + .datai(datai), + .datao(datao) + ); +endmodule + +module mux4096_1bit + (input [`MUX1_SIZE*`MUX2_SIZE-1:0] datai, + input [`ADDR_WIDTH-1:0] addr, + output datao + ); + + // address decoding + wire [3:0] A = (4\'b1) << addr[1:0]; + wire [3:0] B = (4\'b1) << addr[3:2]; + wire [3:0] C = (4\'b1) << addr[5:4]; + wire [3:0] D = (4\'b1) << addr[7:6]; + wire [3:0] E = (4\'b1) << addr[9:8]; + wire [3:0] F = (4\'b1) << addr[11:10]; + + wire [`MUX2_SIZE-1:0] data0; + + // DATA_WIDTH*(MUX2_SIZE)*MUX1_SIZE instantiations of mux64 + // first stage of 64:1 muxing + mux64 #(.MUX_SIZE(`MUX1_SIZE)) mux1[`MUX2_SIZE-1:0] + (.A(A), + .B(B), + .C(C), + .datai(datai), + .datao(data0)); + + // DATA_WIDTH*MUX2_SIZE instantiations of mux64 + // second stage of 64:1 muxing + mux64 #(.MUX_SIZE(`MUX2_SIZE)) mux2 + (.A(D), + .B(E), + .C(F), + .datai(data0), + .datao(datao)); + +endmodule + +module mux64 + #(parameter MUX_SIZE=64) + (input [3:0] A, + input [3:0] B, + input [3:0] C, + input [MUX_SIZE-1:0] datai, + output datao + ); + + wire [63:0] colSelA = { 16{ A[3:0] }}; + wire [63:0] colSelB = { 4{ {4{B[3]}}, {4{B[2]}}, {4{B[1]}}, {4{B[0]}}}}; + wire [63:0] colSelC = { {16{C[3]}}, {16{C[2]}}, {16{C[1]}}, {16{C[0]}}}; + + wire [MUX_SIZE-1:0] data_bus; + + // Note each of these becomes a separate wire. + //.colSelA(colSelA[MUX_SIZE-1:0]), + //.colSelB(colSelB[MUX_SIZE-1:0]), + //.colSelC(colSelC[MUX_SIZE-1:0]), + + drv drv[MUX_SIZE-1:0] + (.colSelA(colSelA[MUX_SIZE-1:0]), + .colSelB(colSelB[MUX_SIZE-1:0]), + .colSelC(colSelC[MUX_SIZE-1:0]), + .datai(datai), + .datao(data_bus) + ); + + assign datao = |data_bus; + +endmodule + +module drv + (input colSelA, + input colSelB, + input colSelC, + input datai, + output datao + ); + assign datao = colSelC & colSelB & colSelA & datai; + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer \tcyc=0; + reg [63:0] \tcrc; + reg [63:0] \tsum; + + // verilator lint_off LITENDIAN + wire [10:41] sel2 = crc[31:0]; + wire [10:100] sel3 = {crc[26:0],crc}; + + wire\t\t out20 = sel2[{1\'b0,crc[3:0]} + 11]; + wire [3:0] \t out21 = sel2[13 : 16]; + wire [3:0] \t out22 = sel2[{1\'b0,crc[3:0]} + 20 +: 4]; + wire [3:0] \t out23 = sel2[{1\'b0,crc[3:0]} + 20 -: 4]; + + wire\t\t out30 = sel3[{2\'b0,crc[3:0]} + 11]; + wire [3:0] \t out31 = sel3[13 : 16]; + wire [3:0] \t out32 = sel3[crc[5:0] + 20 +: 4]; + wire [3:0] \t out33 = sel3[crc[5:0] + 20 -: 4]; + + // Aggregate outputs into a single result vector + wire [63:0] \t result = {38\'h0, out20, out21, out22, out23, out30, out31, out32, out33}; + + reg [19:50] sel1; + initial begin + // Path clearing + // 122333445 + // 826048260 + sel1 = 32\'h12345678; + if (sel1 != 32\'h12345678) $stop; + if (sel1[47 : 50] != 4\'h8) $stop; + if (sel1[31 : 34] != 4\'h4) $stop; + if (sel1[27 +: 4] != 4\'h3) $stop; //==[27:30], in memory as [23:20] + if (sel1[26 -: 4] != 4\'h2) $stop; //==[23:26], in memory as [27:24] + end + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write(""[%0t] sels=%x,%x,%x,%x %x,%x,%x,%x\ +"",$time, out20,out21,out22,out23, out30,out31,out32,out33); + $write(""[%0t] cyc==%0d crc=%x result=%x\ +"",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin +\t // Setup +\t crc <= 64\'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin +\t sum <= 64\'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin +\t $write(""[%0t] cyc==%0d crc=%x sum=%x\ +"",$time, cyc, crc, sum); +\t if (crc !== 64\'hc77bb9b3784ea091) $stop; +`define EXPECTED_SUM 64\'h28bf65439eb12c00 +\t if (sum !== `EXPECTED_SUM) $stop; +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end + +endmodule +" +"// DESCRIPTION: Verilator: Test for using DPI as general accessors +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012. +// +// Contributed by Jeremy Bennett and Jie Xul +// +// This test exercises the use of DPI to access signals and registers in a +// module hierarchy in a uniform fashion. See the discussion at +// +// http://www.veripool.org/boards/3/topics/show/752-Verilator-Command-line-specification-of-public-access-to-variables +// +// We need to test read and write access to: +// - scalars +// - vectors +// - array elements +// - slices of vectors or array elements +// +// We need to test that writing to non-writable elements generates an error. +// +// This Verilog would run forever. It will be stopped externally by the C++ +// instantiating program. + + +// Define the width of registers and size of memory we use +`define REG_WIDTH 8 +`define MEM_SIZE 256 + + +// Top module defines the accessors and instantiates a sub-module with +// substantive content. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + `include ""t_dpi_accessors_macros_inc.vh"" + `include ""t_dpi_accessors_inc.vh"" + + // Put the serious stuff in a sub-module, so we can check hierarchical + // access works OK. + test_sub i_test_sub (.clk (clk)); + +endmodule // t + + +// A sub-module with all sorts of goodies we would like to access + +module test_sub (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer i;\t\t// General counter + + // Elements we would like to access from outside + reg \t a; + reg [`REG_WIDTH - 1:0] b; + reg [`REG_WIDTH - 1:0] mem [`MEM_SIZE - 1:0]; + wire \t\t c; + wire [`REG_WIDTH - 1:0] d; + reg [`REG_WIDTH - 1:0] e; + reg [`REG_WIDTH - 1:0] f; + + // Drive our wires from our registers + assign c = ~a; + assign d = ~b; + + // Initial values for registers and array + initial begin + a = 0; + b = `REG_WIDTH\'h0; + + for (i = 0; i < `MEM_SIZE; i++) begin +\t mem[i] = i [`REG_WIDTH - 1:0]; + end + + e = 0; + f = 0; + end + + // Wipe out one memory cell in turn on the positive clock edge, restoring + // the previous element. We toggle the wipeout value. + always @(posedge clk) begin + mem[b] <= {`REG_WIDTH {a}}; + mem[b - 1] <= b - 1; + a <= ~a; + b <= b + 1; + end + +endmodule // test_sub +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +typedef struct packed { + bit \t b9; + byte\t b1; + bit \t b0; +} pack_t; + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer \tcyc=0; + reg [63:0] \tcrc; + reg [63:0] \tsum; + + // Take CRC data and apply to testblock inputs + pack_t in; + always @* in = crc[9:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + pack_t\t\tout;\t\t\t// From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ +\t // Outputs +\t .out\t\t\t(out), +\t // Inputs +\t .in\t\t\t(in)); + + // Aggregate outputs into a single result vector + wire [63:0] result = {54\'h0, out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write(""[%0t] cyc==%0d crc=%x in=%x result=%x\ +"",$time, cyc, crc, in, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin +\t // Setup +\t crc <= 64\'h5aef0c8d_d70a4497; +\t sum <= 64\'h0; + end + else if (cyc<10) begin +\t sum <= 64\'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin +\t $write(""[%0t] cyc==%0d crc=%x sum=%x\ +"",$time, cyc, crc, sum); +\t if (crc !== 64\'hc77bb9b3784ea091) $stop; +\t // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64\'h99c434d9b08c2a8a +\t if (sum !== `EXPECTED_SUM) $stop; +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end + +endmodule + +module Test ( +\t input pack_t in, +\t output pack_t out); + + always @* begin + out = in; + out.b1 = in.b1 + 1; + out.b0 = 1\'b1; + end +endmodule + +// Local Variables: +// verilog-typedef-regexp: ""_t$"" +// End: +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +interface ifc; + integer value; + modport i (output value); + modport o (input value); +endinterface + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + integer cyc=1; + + ifc itop1a(), + itop1b(); + + wrapper c1 (.isuba(itop1a), +\t\t.isubb(itop1b), +\t\t.i_valuea(14), +\t\t.i_valueb(15)); + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==20) begin +\t if (itop1a.value != 14) $stop; +\t if (itop1b.value != 15) $stop; +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end +endmodule + +module wrapper + ( + ifc.i isuba, isubb, + input integer i_valuea, i_valueb + ); + always @* begin + isuba.value = i_valuea; + isubb.value = i_valueb; + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write(""%%Error: %s:%0d: got=\'h%x exp=\'h%x\ +"", `__FILE__,`__LINE__, (gotv), (expv)); fail=\'1; end while(0) +`define checkf(gotv,expv) do if ((gotv) !== (expv)) begin $write(""%%Error: %s:%0d: got=%f exp=%f\ +"", `__FILE__,`__LINE__, (gotv), (expv)); fail=\'1; end while(0) +`ifdef VERILATOR + `define c(v,vs) ($c(vs)) // Don\'t constify a value +`else + `define c(v,vs) (v) +`endif + + module t (/*AUTOARG*/ + // Outputs + ow4_u + ); + + bit fail; + + reg signed [3:0] w4_s; + reg signed [4:0] w5_s; + reg [2:0] \t w3_u; + reg [3:0] \t w4_u; + reg [4:0] \t w5_u; + reg [5:0] \t w6_u; + reg [15:0] \t w16a_u; + reg [15:0] \t w16_u; + reg [31:0] \t w32_u; + real \t r; + + reg signed [4:0] bug754_a; + + integer \t i; + + //verilator lint_off WIDTH + wire a = (5\'b0 == (5\'sb11111 >>> 3\'d7)); + wire b = (5\'sb11111 == (5\'sb11111 >>> 3\'d7)); + wire c = (1\'b0+(5\'sb11111 >>> 3\'d7)); + wire d = (1\'sb0+(5\'sb11111 >>> 3\'d7)); + wire e = (5\'b0 == (5\'sb11111 / 5\'sd3)); + wire f = (5\'sb0 == (5\'sb11111 / 5\'sd3)); + wire g = (5\'b01010 == (5\'b11111 / 5\'sd3)); + initial begin + // verilator lint_off STMTDLY + #1; +`ifdef VCS // I-2014.03 + `checkh({a, b, c, d, e, f, g}, 7\'b1101111); +`else + `checkh({a, b, c, d, e, f, g}, 7\'b1101011); +`endif + + //====================================================================== + + if ((-1 >>> 3) != -1) $stop;\t// Decimals are signed + + i = 3\'sb111 >>> 3; + `checkh(i, -1); + i = -1 >>> 3; + `checkh(i, -1); + + bug754_a = -1; + w4_u = |0 != (bug754_a >>> 3\'d7); + `checkh(w4_u, 4\'b0); + + // Sanity check: -1>>7 == -1 + w5_u = (5\'sb11111 >>> 3\'d7); + `checkh(w5_u, 5\'b11111); + + // bug756 + w4_u = (5\'b0 == (5\'sb11111 >>> 3\'d7)); + `checkh(w4_u, 4\'b0001); + w4_u = ((5\'b0 == (5\'sb11111 >>> 3\'d7))); // Exp 0 Vlt 0 + `checkh(w4_u, 4\'b0001); + w4_u = ((5\'b01111 == (5\'sb11111 / 5\'sd2))); // Strength-reduces to >>> +`ifdef VCS // I-2014.03 + `checkh(w4_u, 4\'b0000); // Wrong, gets 5\'b0==..., unsigned does not propagate +`else + `checkh(w4_u, 4\'b0001); // NC-Verilog, Modelsim, XSim, ... +`endif + + // Does == sign propagate from lhs to rhs? Yes, but not in VCS + w4_u = ((5\'b01010 == (5\'sb11111 / 5\'sd3))); // Exp 0 Vlt 0 // Must be signed result (-1/3) to make this result zero +`ifdef VCS // I-2014.03 + `checkh(w4_u, 4\'b0000); // Wrong, gets 5\'b0==..., unsigned does not propagate +`else + `checkh(w4_u, 4\'b0001); // NC-Verilog, Modelsim, XSim, ... +`endif + + w4_u = (1\'b0+(5\'sb11111 >>> 3\'d7)); // Exp 00000 Vlt 000000 Actually the signedness of result does NOT matter + `checkh(w4_u, 4\'b0000); + + w4_u = (5\'sb0 == (5\'sb11111 / 5\'sd3)); // Must be signed result (-1/3) to make this result zero + `checkh(w4_u, 4\'b0001); + // Does == width propagate from lhs to rhs? Yes + w4_u = (3\'b100==(3\'b111 << 2)); + `checkh(w4_u, 4\'b0001); + w4_u = (4\'b100==(3\'b111 << 2)); + `checkh(w4_u, 4\'b0000); + w4_u = (4\'b1100==(3\'b111 << 2)); + `checkh(w4_u, 4\'b0001); + + // Does >>> sign propagate from input same as for +? Yes + w4_u = (1\'b0+(5\'sb11111 >>> 3\'d7)); + `checkh(w4_u, 4\'b0000); + w4_u = (1\'sb0+(5\'sb11111 >>> 3\'d7)); + `checkh(w4_u, 4\'b1111); + + // Does << width propagate from input same as for +? Yes + w4_u = (3\'b0+(3\'b111 << 2)); + `checkh(w4_u, 4\'b1100); // width 4 ==\'s LHS + w4_u = (4\'b0+(3\'b111 << 2)); + `checkh(w4_u, 4\'b1100); + + w4_u = (5\'sb11111 == (5\'sb11111 >>> 3\'d7)); // WHAT? Signedness does propagate across ==????? + `checkh(w4_u, 4\'b0001); + w4_u = ((5\'b0 == (5\'sb11111 >>> 3\'d7))); + `checkh(w4_u, 4\'b0001); + + // bug756 + w5_s = -1; + w3_u = 7; + w4_u = |0 != (w5_s >>> w3_u); + `checkh(w4_u, 4\'b0000); + + // bug763 + w3_u = 2; + w4_u = (w3_u >> 2\'b11) >> 1; + `checkh(w4_u, 4\'b0000); + + // bug766 + w16a_u = 16\'h1234; + w16_u = (w16a_u >> 16) >>> 32\'h7ffffff1; + `checkh(w16_u, 16\'h0000); + + // bug768 + w4_s = 4\'sd4; + w4_u = $signed(5\'d1 > w4_s-w4_s); + `checkh(w4_u, 4\'b1111); + w4_s = `c(4,""4""); // Eval at runtime + w4_u = $signed(5\'d1 > w4_s-w4_s); + `checkh(w4_u, 4\'b1111); + + // bug772 + w4_s = w4_u << 1 <<< 0/0; +`ifndef VERILATOR // In v4 can\'t check value as not 4-state + `checkh(w4_s, 4\'bxxxx); +`endif + + // bug773 + w5_u = `c(31, 31); + w5_s = w5_u >> ((w5_u ? 1 : 2) << w5_u); + `checkh(w5_s, 5\'b0); + + // bug774 + w4_u = `c(4, 5); + w6_u = `c(6, 35); + w4_u = 64\'d0 | (w4_u << w6_u); + `checkh(w4_u, 0); + + // bug776 + w4_u = `c(4, 1); + w4_u = (w4_u >> w4_u) ^~ (w4_u >> w4_u); + `checkh(w4_u, 4\'b1111); + + // bug828 + // verilator lint_off WIDTH + w32_u = 32\'(signed\'({4\'b0001,5\'b10000}) << 3); + `checkh(w32_u, 32\'h0000_0180); + w32_u = 32\'(signed\'({4\'b0011,5\'b10000}) << 3); + `checkh(w32_u, 32\'h0000_0380); + w32_u = signed\'(32\'({4\'b0001,5\'b10000}) << 3); + `checkh(w32_u, 32\'h0000_0180); + w32_u = signed\'(32\'({4\'b0011,5\'b10000}) << 3); + `checkh(w32_u, 32\'h0000_0380); + // verilator lint_on WIDTH + w32_u = 32\'(signed\'({4\'b0011,5\'b10000})) << 3; // Check no width warning + `checkh(w32_u, 32\'h0000_0380); + + if (fail) $stop; + $write(""*-* All Finished *-*\ +""); + $finish; + end + + // bug775 + output [3:0] ow4_u; // Must be consumed + assign ow4_u = ((0/0) ? 1 : 2) % 0; + +endmodule +" +"// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Lane Brooks + +`define WIDTH 2 + +module top ( + input OE1, + input OE2, + input [`WIDTH-1:0] A1, + input [`WIDTH-1:0] A2, + output [`WIDTH-1:0] Y1, + output [`WIDTH-1:0] Y2, + output [`WIDTH-1:0] Y3, + output [`WIDTH**2-1:0] W); + + assign W[A1] = (OE2) ? A2[0] : 1'bz; + assign W[A2] = (OE1) ? A2[1] : 1'bz; + + // have 2 different 'chips' drive the PAD to act like a bi-directional bus + wire [`WIDTH-1:0] PAD; + io_ring io_ring1 (.OE(OE1), .A(A1), .O(Y1), .PAD(PAD)); + io_ring io_ring2 (.OE(OE2), .A(A2), .O(Y2), .PAD(PAD)); + + assign Y3 = PAD; + + pullup p1(PAD); +// pulldown p1(PAD); + + + wire [5:0] \t fill = { 4'b0, A1 }; + +endmodule + +module io_ring (input OE, input [`WIDTH-1:0] A, output [`WIDTH-1:0] O, inout [`WIDTH-1:0] PAD); + io io[`WIDTH-1:0] (.OE(OE), .I(A), .O(O), .PAD(PAD)); +endmodule + +module io (input OE, input I, output O, inout PAD); + assign O = PAD; + assign PAD = OE ? I : 1'bz; +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer \tcyc=0; + reg [63:0] \tcrc; + reg [63:0] \tsum; + + // Take CRC data and apply to testblock inputs + wire [31:0] Operand1 = crc[31:0]; + wire [15:0] Operand2 = crc[47:32]; + wire \tUnsigned = crc[48]; + reg \t\trst; + + parameter wl = 16; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [wl-1:0]\tQuotient;\t\t// From test of Test.v + wire [wl-1:0]\tRemainder;\t\t// From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ +\t // Outputs +\t .Quotient\t\t\t(Quotient[wl-1:0]), +\t .Remainder\t\t(Remainder[wl-1:0]), +\t // Inputs +\t .Operand1\t\t\t(Operand1[wl*2-1:0]), +\t .Operand2\t\t\t(Operand2[wl-1:0]), +\t .clk\t\t\t(clk), +\t .rst\t\t\t(rst), +\t .Unsigned\t\t\t(Unsigned)); + + // Aggregate outputs into a single result vector + wire [63:0] result = {32\'h0, Quotient, Remainder}; + + // What checksum will we end up with +`define EXPECTED_SUM 64\'h98d41f89a8be5693 + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write(""[%0t] cyc==%0d crc=%x result=%x it=%x\ +"",$time, cyc, crc, result, test.Iteration); +`endif + cyc <= cyc + 1; + if (cyc < 20 || test.Iteration==4\'d15) begin +\t crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + end + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin +\t // Setup +\t crc <= 64\'h5aef0c8d_d70a4497; +\t rst <= 1\'b1; + end + else if (cyc<20) begin +\t sum <= 64\'h0; +\t rst <= 1\'b0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin +\t $write(""[%0t] cyc==%0d crc=%x sum=%x\ +"",$time, cyc, crc, sum); +\t if (crc !== 64\'h8dd70a44972ad809) $stop; +\t if (sum !== `EXPECTED_SUM) $stop; +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end + +endmodule + +module Test(clk, rst, Operand1, Operand2, Unsigned, Quotient, Remainder); + + parameter wl = 16; + + input [wl*2-1:0] Operand1; + input [wl-1:0] Operand2; + input clk, rst, Unsigned; + output [wl-1:0] Quotient, Remainder; + + reg Cy, Overflow, Sign1, Sign2, Zero, Negative; + reg [wl-1:0] ah,al,Quotient, Remainder; + reg [3:0] \tIteration; + reg [wl-1:0] sub_quot,op; + reg \t\tah_ext; + + reg [1:0]\ta,b,c,d,e; + + always @(posedge clk) begin + if (!rst) begin +\t {a,b,c,d,e} = Operand1[9:0]; +\t {a,b,c,d,e} = {e,d,c,b,a}; +\t if (a != Operand1[1:0]) $stop; +\t if (b != Operand1[3:2]) $stop; +\t if (c != Operand1[5:4]) $stop; +\t if (d != Operand1[7:6]) $stop; +\t if (e != Operand1[9:8]) $stop; + end + end + + always @(posedge clk) begin + if (rst) begin +\t Iteration <= 0; + Quotient <= 0; + Remainder <= 0; + end + else begin +\t if (Iteration == 0) begin + {ah,al} = Operand1; + op = Operand2; + Cy = 0; + Overflow = 0; + Sign1 = (~Unsigned)&ah[wl-1]; + Sign2 = (~Unsigned)&(ah[wl-1]^op[wl-1]); + if (Sign1) {ah,al} = -{ah,al}; +\t end +`define BUG1 +`ifdef BUG1 +\t {ah_ext,ah,al} = {ah,al,Cy}; +`else +\t ah_ext = ah[15]; +\t ah[15:1] = ah[14:0]; +\t ah[0] = al[15]; +\t al[15:1] = al[14:0]; +\t al[0] = Cy; +`endif +`ifdef TEST_VERBOSE +\t $display(""%x %x %x %x %x %x %x %x %x"", +\t\t Iteration, ah, al, Quotient, Remainder, Overflow, ah_ext, sub_quot, Cy); +`endif +\t {Cy,sub_quot} = (~Unsigned)&op[wl-1]? {ah_ext,ah}+op : {ah_ext,ah} - {1\'b1,op}; +\t if (Cy) +\t begin + {ah_ext,ah} = {1\'b0,sub_quot}; +\t end +\t if (Iteration != 15 ) +\t begin + if (ah_ext) Overflow = 1; +\t end +\t else +\t begin + if (al[14] && ~Unsigned) Overflow = 1; + Quotient <= Sign2 ? -{al[14:0],Cy} : {al[14:0],Cy}; + Remainder <= Sign1 ? -ah : ah; + if (Overflow) +\t\tbegin +\t Quotient <= Sign2 ? 16\'h8001 : {Unsigned,{15{1\'b1}}}; +\t Remainder <= Unsigned ? 16\'hffff : 16\'h8000; +\t Zero = 1; +\t Negative = 1; +\t\tend +\t end +\t Iteration <= Iteration + 1; // Count number of times this instruction is repeated + end + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013. + +// bug648 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer \tcyc=0; + reg [63:0] \tcrc; + reg [63:0] \tsum; + + // Take CRC data and apply to testblock inputs + wire [7:0] datai = crc[7:0]; + wire enable = crc[8]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic [7:0]\t\tdatao;\t\t\t// From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ +\t // Outputs +\t .datao\t\t\t(datao[7:0]), +\t // Inputs +\t .clk\t\t\t(clk), +\t .datai\t\t\t(datai[7:0]), +\t .enable\t\t\t(enable)); + + // Aggregate outputs into a single result vector + wire [63:0] result = {56\'h0, datao}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write(""[%0t] cyc==%0d crc=%x result=%x\ +"",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin +\t // Setup +\t crc <= 64\'h5aef0c8d_d70a4497; +\t sum <= 64\'h0; + end + else if (cyc<10) begin +\t sum <= 64\'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin +\t $write(""[%0t] cyc==%0d crc=%x sum=%x\ +"",$time, cyc, crc, sum); +\t if (crc !== 64\'hc77bb9b3784ea091) $stop; +\t // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64\'h9d550d82d38926fa +\t if (sum !== `EXPECTED_SUM) $stop; +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end + +endmodule + +`define FAIL 1 + +module Nested + ( + input logic \tclk, + input logic \tx, + output logic y + ); + logic \t\t t; + always_comb t = x ^ 1\'b1; + + always_ff @(posedge clk) begin + if (clk) + y <= t; + end +endmodule + +module Test + ( + input logic \t clk, + input logic [7:0] datai, + input logic \t enable, + output logic [7:0] datao + ); + + // verilator lint_off BLKANDNBLK + logic [7:0] \t datat; + // verilator lint_on BLKANDNBLK + + for (genvar i = 0; i < 8; i++) begin + if (i%4 != 3) begin +`ifndef FAIL + logic t; + always_comb begin +\t t = datai[i] ^ 1\'b1; +\t end + always_ff @(posedge clk) begin +\t if (clk) + datat[i] <= t; +\t end +`else + Nested nested_i +\t ( +\t .clk(clk), +\t .x(datai[i]), +\t .y(datat[i]) //<== via Vcellout wire +\t ); +`endif + + always_comb begin +\t casez (enable) +\t 1\'b1: datao[i] = datat[i]; +\t 1\'b0: datao[i] = \'0; +\t default: datao[i] = \'x; +\t endcase +\t end + end + else begin + always_ff @(posedge clk) begin +\t if (clk) + datat[i] <= 0; //<== assign delayed + end + always_comb begin +\t casez (enable) +\t 1\'b1: datao[i] = datat[i] ^ 1\'b1; +\t 1\'b0: datao[i] = \'1; +\t default: datao[i] = \'x; +\t endcase +\t end + end + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2009 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +module t; + + wire [39:0] out; + sub a(.value(out)); + + import ""DPI-C"" context function void poke_value(input int i); + + + initial begin + poke_value(32\'hdeadbeef); + if (out !== 40\'hdeadbeef) begin +\t $display(""[%0t] %%Error: t_dpi_qw: failed"", $time); +\t $stop; + end + + $write(""*-* All Finished *-*\ +""); + $finish; + end + +endmodule + +module sub(value); + parameter WIDTH = 40; + + output [WIDTH-1:0] value; + + reg [WIDTH-1:0] value; + + task set_value(input bit [WIDTH-1:0] v); + value = v; + endtask + + export ""DPI-C"" task set_value; +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg [31:0] a; + reg [31:0] b; + + wire [2:0] bf; buf BF0 (bf[0], a[0]), +\t\t BF1 (bf[1], a[1]), +\t\t BF2 (bf[2], a[2]); + + // verilator lint_off IMPLICIT + not #(0.108) NT0 (nt0, a[0]); + and #1 AN0 (an0, a[0], b[0]); + nand #(2,3) ND0 (nd0, a[0], b[0], b[1]); + or OR0 (or0, a[0], b[0]); + nor NR0 (nr0, a[0], b[0], b[2]); + xor (xo0, a[0], b[0]); + xnor (xn0, a[0], b[0], b[2]); + // verilator lint_on IMPLICIT + + parameter BITS=32; + wire [BITS-1:0] ba; + buf BARRAY [BITS-1:0] (ba, a); + +`ifdef verilator + specify + specparam CDS_LIBNAME = ""foobar""; + (nt0 *> nt0) = (0, 0); + endspecify + + specify + // delay parameters + specparam + a$A1$Y = 1.0, + b$A0$Z = 1.0; + + // path delays + (A1 *> Q) = (a$A1$Y, a$A1$Y); + (A0 *> Q) = (b$A0$Y, a$A0$Z); + endspecify +`endif + + always @ (posedge clk) begin + if (cyc!=0) begin +\t cyc <= cyc + 1; +\t if (cyc==1) begin +\t a <= 32\'h18f6b034; +\t b <= 32\'h834bf892; +\t end +\t if (cyc==2) begin +\t a <= 32\'h529ab56f; +\t b <= 32\'h7835a237; +\t if (bf !== 3\'b100) $stop; +\t if (nt0 !== 1\'b1) $stop; +\t if (an0 !== 1\'b0) $stop; +\t if (nd0 !== 1\'b1) $stop; +\t if (or0 !== 1\'b0) $stop; +\t if (nr0 !== 1\'b1) $stop; +\t if (xo0 !== 1\'b0) $stop; +\t if (xn0 !== 1\'b1) $stop; +\t if (ba != 32\'h18f6b034) $stop; +\t end +\t if (cyc==3) begin +\t if (bf !== 3\'b111) $stop; +\t if (nt0 !== 1\'b0) $stop; +\t if (an0 !== 1\'b1) $stop; +\t if (nd0 !== 1\'b0) $stop; +\t if (or0 !== 1\'b1) $stop; +\t if (nr0 !== 1\'b0) $stop; +\t if (xo0 !== 1\'b0) $stop; +\t if (xn0 !== 1\'b0) $stop; +\t end +\t if (cyc==4) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; +\t end + end + end + +endmodule +" +"// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Lane Brooks. + +module t (clk); + input clk; + + wire A; + + pullup p1(A); + pulldown p2(A); + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +// verilator lint_off UNUSED +// verilator lint_off UNDRIVEN + +//bug858 + +typedef struct packed { + logic m_1; + logic m_2; +} struct_t; + +typedef struct packed { + logic [94:0] m_1; + logic m_2; +} struct96_t; + +module t + ( + input struct_t test_input, + input struct96_t t96 + ); +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +// bug598 + +module t (/*AUTOARG*/ + // Outputs + val, + // Inputs + clk + ); + + input \t clk; + output integer val; + integer \t dbg_addr = 0; + + function func1; + input en; + input [31:0] a; + func1 = en && (a == 1); + endfunction + + function func2; + input \t en; + input [31:0] a; + func2 = en && (a == 2); + endfunction + + always @(posedge clk) begin + case( 1\'b1 ) + // This line is OK: + func1(1\'b1, dbg_addr) : val = 1; + // This fails: + // %Error: Internal Error: test.v:23: ../V3Task.cpp:993: Function not underneath a statement + // %Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance. + func2(1\'b1, dbg_addr) : val = 2; + default : val = 0; + endcase + // + $write(""*-* All Finished *-*\ +""); + $finish; + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2006 by Wilson Snyder. + +`include ""verilated.v"" + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + reg [63:0] crc; + `verilator_file_descriptor\t fd; + + t_case_write1_tasks tasks (); + + integer cyc; initial cyc=0; + + always @ (posedge clk) begin + $fwrite(fd, ""[%0d] crc=%x "", cyc, crc); + tasks.big_case(fd, crc[31:0]); + $fwrite(fd, ""\ +""); + end + + always @ (posedge clk) begin + //$write(""[%0t] cyc==%0d crc=%x\ +"",$time, cyc, crc); + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + if (cyc==1) begin +\t crc <= 64\'h00000000_00000097; +\t $write(""Open obj_dir/t_case_write1/t_case_write1_logger.log\ +""); +\t fd = $fopen(""obj_dir/t_case_write1/t_case_write1_logger.log"", ""w""); + end + if (cyc==90) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. +// +// -------------------------------------------------------- +// Bug Description: +// +// Issue: The gated clock gclk_vld[0] toggles but dvld[0] +// input to the flop does not propagate to the output +// signal entry_vld[0] correctly. The value that propagates +// is the new value of dvld[0] not the one just before the +// posedge of gclk_vld[0]. +// -------------------------------------------------------- + +// Define to see the bug with test failing with gated clock \'gclk_vld\' +// Comment out the define to see the test passing with ungated clock \'clk\' +`define GATED_CLK_TESTCASE 1 + +// A side effect of the problem is this warning, disabled by default +//verilator lint_on IMPERFECTSCH + +// Test Bench +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer \tcyc=0; + reg [63:0] \tcrc; + + // Take CRC data and apply to testblock inputs + wire [7:0] dvld = crc[7:0]; + wire [7:0] ff_en_e1 = crc[15:8]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [7:0]\t\tentry_vld;\t\t// From test of Test.v + wire [7:0]\t\tff_en_vld;\t\t// From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ +\t // Outputs +\t .ff_en_vld\t\t(ff_en_vld[7:0]), +\t .entry_vld\t\t(entry_vld[7:0]), +\t // Inputs +\t .clk\t\t\t(clk), +\t .dvld\t\t\t(dvld[7:0]), +\t .ff_en_e1\t\t\t(ff_en_e1[7:0])); + + reg err_code; + reg ffq_clk_active; + reg [7:0] prv_dvld; + + initial begin + err_code = 0; + ffq_clk_active = 0; + end + always @ (posedge clk) begin + prv_dvld = test.dvld; + end + always @ (negedge test.ff_entry_dvld_0.clk) begin + ffq_clk_active = 1; + if (test.entry_vld[0] !== prv_dvld[0]) err_code = 1; + end + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write(""[%0t] cyc==%0d crc=%x "",$time, cyc, crc); + $display("" en=%b fen=%b d=%b ev=%b"", +\t test.flop_en_vld[0], test.ff_en_vld[0], +\t test.dvld[0], test.entry_vld[0]); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + if (cyc<3) begin +\t crc <= 64\'h5aef0c8d_d70a4497; + end + else if (cyc==99) begin +\t $write(""[%0t] cyc==%0d crc=%x\ +"",$time, cyc, crc); + if (ffq_clk_active == 0) begin + $display (""----""); + $display (""%%Error: TESTCASE FAILED with no Clock arriving at FFQs""); + $display (""----""); + $stop; + end + else if (err_code) begin + $display (""----""); + $display (""%%Error: TESTCASE FAILED with invalid propagation of \'d\' to \'q\' of FFQs""); + $display (""----""); + $stop; + end + else begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end + end + +endmodule + +module llq (clk, d, q); + parameter WIDTH = 32; + input clk; + input [WIDTH-1:0] d; + output [WIDTH-1:0] q; + + reg [WIDTH-1:0] qr; + + /* verilator lint_off COMBDLY */ + + always @(clk or d) + if (clk == 1\'b0) + qr <= d; + + /* verilator lint_on COMBDLY */ + + assign q = qr; +endmodule + +module ffq (clk, d, q); + parameter WIDTH = 32; + input clk; + input [WIDTH-1:0] d; + output [WIDTH-1:0] q; + + reg [WIDTH-1:0] qr; + + always @(posedge clk) + qr <= d; + + assign q = qr; +endmodule + +// DUT module +module Test (/*AUTOARG*/ + // Outputs + ff_en_vld, entry_vld, + // Inputs + clk, dvld, ff_en_e1 + ); + input clk; + + input [7:0] dvld; + input [7:0] ff_en_e1; + + output [7:0] ff_en_vld; + output wire [7:0] entry_vld; + + wire [7:0] gclk_vld; + wire [7:0] ff_en_vld /*verilator clock_enable*/; + reg [7:0] flop_en_vld; + + always @(posedge clk) flop_en_vld <= ff_en_e1; + + // clock gating +`ifdef GATED_CLK_TESTCASE + assign gclk_vld = {8{clk}} & ff_en_vld; +`else + assign gclk_vld = {8{clk}}; +`endif + + // latch for avoiding glitch on the clock gating control + llq #(8) dp_ff_en_vld (.clk(clk), .d(flop_en_vld), .q(ff_en_vld)); + + // flops that use the gated clock signal + ffq #(1) ff_entry_dvld_0 (.clk(gclk_vld[0]), .d(dvld[0]), .q(entry_vld[0])); + ffq #(1) ff_entry_dvld_1 (.clk(gclk_vld[1]), .d(dvld[1]), .q(entry_vld[1])); + ffq #(1) ff_entry_dvld_2 (.clk(gclk_vld[2]), .d(dvld[2]), .q(entry_vld[2])); + ffq #(1) ff_entry_dvld_3 (.clk(gclk_vld[3]), .d(dvld[3]), .q(entry_vld[3])); + ffq #(1) ff_entry_dvld_4 (.clk(gclk_vld[4]), .d(dvld[4]), .q(entry_vld[4])); + ffq #(1) ff_entry_dvld_5 (.clk(gclk_vld[5]), .d(dvld[5]), .q(entry_vld[5])); + ffq #(1) ff_entry_dvld_6 (.clk(gclk_vld[6]), .d(dvld[6]), .q(entry_vld[6])); + ffq #(1) ff_entry_dvld_7 (.clk(gclk_vld[7]), .d(dvld[7]), .q(entry_vld[7])); + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t_case_huge_sub2 (/*AUTOARG*/ + // Outputs + outa, + // Inputs + index + ); + + input [9:0] index; + output [9:0] outa; + + // ============================= + /*AUTOREG*/ + // Beginning of automatic regs (for this module\'s undeclared outputs) + reg [9:0]\t\touta; + // End of automatics + + // ============================= + // Created from perl + // for $i (0..1023) { printf ""\\t10\'h%03x: begin outa = 10\'h%03x; outb = 2\'b%02b; outc = 1\'b%d; end\ +"", $i, rand(1024),rand(4),rand(2); }; + + always @(/*AS*/index) begin + case (index[7:0]) +`ifdef VERILATOR // Harder test +\t8\'h00: begin outa = $c(""0""); end // Makes whole table non-optimizable +`else +\t8\'h00: begin outa = 10\'h0; end +`endif +\t8\'h01: begin outa = 10\'h318; end +\t8\'h02: begin outa = 10\'h29f; end +\t8\'h03: begin outa = 10\'h392; end +\t8\'h04: begin outa = 10\'h1ef; end +\t8\'h05: begin outa = 10\'h06c; end +\t8\'h06: begin outa = 10\'h29f; end +\t8\'h07: begin outa = 10\'h29a; end +\t8\'h08: begin outa = 10\'h3ce; end +\t8\'h09: begin outa = 10\'h37c; end +\t8\'h0a: begin outa = 10\'h058; end +\t8\'h0b: begin outa = 10\'h3b2; end +\t8\'h0c: begin outa = 10\'h36f; end +\t8\'h0d: begin outa = 10\'h2c5; end +\t8\'h0e: begin outa = 10\'h23a; end +\t8\'h0f: begin outa = 10\'h222; end +\t8\'h10: begin outa = 10\'h328; end +\t8\'h11: begin outa = 10\'h3c3; end +\t8\'h12: begin outa = 10\'h12c; end +\t8\'h13: begin outa = 10\'h1d0; end +\t8\'h14: begin outa = 10\'h3ff; end +\t8\'h15: begin outa = 10\'h115; end +\t8\'h16: begin outa = 10\'h3ba; end +\t8\'h17: begin outa = 10\'h3ba; end +\t8\'h18: begin outa = 10\'h10d; end +\t8\'h19: begin outa = 10\'h13b; end +\t8\'h1a: begin outa = 10\'h0a0; end +\t8\'h1b: begin outa = 10\'h264; end +\t8\'h1c: begin outa = 10\'h3a2; end +\t8\'h1d: begin outa = 10\'h07c; end +\t8\'h1e: begin outa = 10\'h291; end +\t8\'h1f: begin outa = 10\'h1d1; end +\t8\'h20: begin outa = 10\'h354; end +\t8\'h21: begin outa = 10\'h0c0; end +\t8\'h22: begin outa = 10\'h191; end +\t8\'h23: begin outa = 10\'h379; end +\t8\'h24: begin outa = 10\'h073; end +\t8\'h25: begin outa = 10\'h2fd; end +\t8\'h26: begin outa = 10\'h2e0; end +\t8\'h27: begin outa = 10\'h337; end +\t8\'h28: begin outa = 10\'h2c7; end +\t8\'h29: begin outa = 10\'h19e; end +\t8\'h2a: begin outa = 10\'h107; end +\t8\'h2b: begin outa = 10\'h06a; end +\t8\'h2c: begin outa = 10\'h1c7; end +\t8\'h2d: begin outa = 10\'h107; end +\t8\'h2e: begin outa = 10\'h0cf; end +\t8\'h2f: begin outa = 10\'h009; end +\t8\'h30: begin outa = 10\'h09d; end +\t8\'h31: begin outa = 10\'h28e; end +\t8\'h32: begin outa = 10\'h010; end +\t8\'h33: begin outa = 10\'h1e0; end +\t8\'h34: begin outa = 10\'h079; end +\t8\'h35: begin outa = 10\'h13e; end +\t8\'h36: begin outa = 10\'h282; end +\t8\'h37: begin outa = 10\'h21c; end +\t8\'h38: begin outa = 10\'h148; end +\t8\'h39: begin outa = 10\'h3c0; end +\t8\'h3a: begin outa = 10\'h176; end +\t8\'h3b: begin outa = 10\'h3fc; end +\t8\'h3c: begin outa = 10\'h295; end +\t8\'h3d: begin outa = 10\'h113; end +\t8\'h3e: begin outa = 10\'h354; end +\t8\'h3f: begin outa = 10\'h0db; end +\t8\'h40: begin outa = 10\'h238; end +\t8\'h41: begin outa = 10\'h12b; end +\t8\'h42: begin outa = 10\'h1dc; end +\t8\'h43: begin outa = 10\'h137; end +\t8\'h44: begin outa = 10\'h1e2; end +\t8\'h45: begin outa = 10\'h3d5; end +\t8\'h46: begin outa = 10\'h30c; end +\t8\'h47: begin outa = 10\'h298; end +\t8\'h48: begin outa = 10\'h080; end +\t8\'h49: begin outa = 10\'h35a; end +\t8\'h4a: begin outa = 10\'h01b; end +\t8\'h4b: begin outa = 10\'h0a3; end +\t8\'h4c: begin outa = 10\'h0b3; end +\t8\'h4d: begin outa = 10\'h17a; end +\t8\'h4e: begin outa = 10\'h3ae; end +\t8\'h4f: begin outa = 10\'h078; end +\t8\'h50: begin outa = 10\'h322; end +\t8\'h51: begin outa = 10\'h213; end +\t8\'h52: begin outa = 10\'h11a; end +\t8\'h53: begin outa = 10\'h1a7; end +\t8\'h54: begin outa = 10\'h35a; end +\t8\'h55: begin outa = 10\'h233; end +\t8\'h56: begin outa = 10\'h01d; end +\t8\'h57: begin outa = 10\'h2d5; end +\t8\'h58: begin outa = 10\'h1a0; end +\t8\'h59: begin outa = 10\'h3d0; end +\t8\'h5a: begin outa = 10\'h181; end +\t8\'h5b: begin outa = 10\'h219; end +\t8\'h5c: begin outa = 10\'h26a; end +\t8\'h5d: begin outa = 10\'h050; end +\t8\'h5e: begin outa = 10\'h189; end +\t8\'h5f: begin outa = 10\'h1eb; end +\t8\'h60: begin outa = 10\'h224; end +\t8\'h61: begin outa = 10\'h2fe; end +\t8\'h62: begin outa = 10\'h0ae; end +\t8\'h63: begin outa = 10\'h1cd; end +\t8\'h64: begin outa = 10\'h273; end +\t8\'h65: begin outa = 10\'h268; end +\t8\'h66: begin outa = 10\'h111; end +\t8\'h67: begin outa = 10\'h1f9; end +\t8\'h68: begin outa = 10\'h232; end +\t8\'h69: begin outa = 10\'h255; end +\t8\'h6a: begin outa = 10\'h34c; end +\t8\'h6b: begin outa = 10\'h049; end +\t8\'h6c: begin outa = 10\'h197; end +\t8\'h6d: begin outa = 10\'h0fe; end +\t8\'h6e: begin outa = 10\'h253; end +\t8\'h6f: begin outa = 10\'h2de; end +\t8\'h70: begin outa = 10\'h13b; end +\t8\'h71: begin outa = 10\'h040; end +\t8\'h72: begin outa = 10\'h0b4; end +\t8\'h73: begin outa = 10\'h233; end +\t8\'h74: begin outa = 10\'h198; end +\t8\'h75: begin outa = 10\'h018; end +\t8\'h76: begin outa = 10\'h2f7; end +\t8\'h77: begin outa = 10\'h134; end +\t8\'h78: begin outa = 10\'h1ca; end +\t8\'h79: begin outa = 10\'h286; end +\t8\'h7a: begin outa = 10\'h0e6; end +\t8\'h7b: begin outa = 10\'h064; end +\t8\'h7c: begin outa = 10\'h257; end +\t8\'h7d: begin outa = 10\'h31a; end +\t8\'h7e: begin outa = 10\'h247; end +\t8\'h7f: begin outa = 10\'h299; end +\t8\'h80: begin outa = 10\'h02c; end +\t8\'h81: begin outa = 10\'h2bb; end +\t8\'h82: begin outa = 10\'h180; end +\t8\'h83: begin outa = 10\'h245; end +\t8\'h84: begin outa = 10\'h0da; end +\t8\'h85: begin outa = 10\'h367; end +\t8\'h86: begin outa = 10\'h304; end +\t8\'h87: begin outa = 10\'h38b; end +\t8\'h88: begin outa = 10\'h09f; end +\t8\'h89: begin outa = 10\'h1f0; end +\t8\'h8a: begin outa = 10\'h281; end +\t8\'h8b: begin outa = 10\'h019; end +\t8\'h8c: begin outa = 10\'h1f2; end +\t8\'h8d: begin outa = 10\'h0b1; end +\t8\'h8e: begin outa = 10\'h058; end +\t8\'h8f: begin outa = 10\'h39b; end +\t8\'h90: begin outa = 10\'h2ec; end +\t8\'h91: begin outa = 10\'h250; end +\t8\'h92: begin outa = 10\'h3f4; end +\t8\'h93: begin outa = 10\'h057; end +\t8\'h94: begin outa = 10\'h18f; end +\t8\'h95: begin outa = 10\'h105; end +\t8\'h96: begin outa = 10\'h1ae; end +\t8\'h97: begin outa = 10\'h04e; end +\t8\'h98: begin outa = 10\'h240; end +\t8\'h99: begin outa = 10\'h3e4; end +\t8\'h9a: begin outa = 10\'h3c6; end +\t8\'h9b: begin outa = 10\'h109; end +\t8\'h9c: begin outa = 10\'h073; end +\t8\'h9d: begin outa = 10\'h19f; end +\t8\'h9e: begin outa = 10\'h3b8; end +\t8\'h9f: begin outa = 10\'h00e; end +\t8\'ha0: begin outa = 10\'h1b3; end +\t8\'ha1: begin outa = 10\'h2bd; end +\t8\'ha2: begin outa = 10\'h324; end +\t8\'ha3: begin outa = 10\'h343; end +\t8\'ha4: begin outa = 10\'h1c9; end +\t8\'ha5: begin outa = 10\'h185; end +\t8\'ha6: begin outa = 10\'h37a; end +\t8\'ha7: begin outa = 10\'h0e0; end +\t8\'ha8: begin outa = 10\'h0a3; end +\t8\'ha9: begin outa = 10\'h019; end +\t8\'haa: begin outa = 10\'h099; end +\t8\'hab: begin outa = 10\'h376; end +\t8\'hac: begin outa = 10\'h077; end +\t8\'had: begin outa = 10\'h2b1; end +\t8\'hae: begin outa = 10\'h27f; end +\t8\'haf: begin outa = 10\'h265; end +\t8\'hb0: begin outa = 10\'h156; end +\t8\'hb1: begin outa = 10\'h1ce; end +\t8\'hb2: begin outa = 10\'h008; end +\t8\'hb3: begin outa = 10\'h12e; end +\t8\'hb4: begin outa = 10\'h199; end +\t8\'hb5: begin outa = 10\'h330; end +\t8\'hb6: begin outa = 10\'h1ab; end +\t8\'hb7: begin outa = 10\'h3bd; end +\t8\'hb8: begin outa = 10\'h0ca; end +\t8\'hb9: begin outa = 10\'h367; end +\t8\'hba: begin outa = 10\'h334; end +\t8\'hbb: begin outa = 10\'h040; end +\t8\'hbc: begin outa = 10\'h1a7; end +\t8\'hbd: begin outa = 10\'h036; end +\t8\'hbe: begin outa = 10\'h223; end +\t8\'hbf: begin outa = 10\'h075; end +\t8\'hc0: begin outa = 10\'h3c4; end +\t8\'hc1: begin outa = 10\'h2cc; end +\t8\'hc2: begin outa = 10\'h123; end +\t8\'hc3: begin outa = 10\'h3fd; end +\t8\'hc4: begin outa = 10\'h11e; end +\t8\'hc5: begin outa = 10\'h27c; end +\t8\'hc6: begin outa = 10\'h1e2; end +\t8\'hc7: begin outa = 10\'h377; end +\t8\'hc8: begin outa = 10\'h33a; end +\t8\'hc9: begin outa = 10\'h32d; end +\t8\'hca: begin outa = 10\'h014; end +\t8\'hcb: begin outa = 10\'h332; end +\t8\'hcc: begin outa = 10\'h359; end +\t8\'hcd: begin outa = 10\'h0a4; end +\t8\'hce: begin outa = 10\'h348; end +\t8\'hcf: begin outa = 10\'h04b; end +\t8\'hd0: begin outa = 10\'h147; end +\t8\'hd1: begin outa = 10\'h026; end +\t8\'hd2: begin outa = 10\'h103; end +\t8\'hd3: begin outa = 10\'h106; end +\t8\'hd4: begin outa = 10\'h35a; end +\t8\'hd5: begin outa = 10\'h254; end +\t8\'hd6: begin outa = 10\'h0cd; end +\t8\'hd7: begin outa = 10\'h17c; end +\t8\'hd8: begin outa = 10\'h37e; end +\t8\'hd9: begin outa = 10\'h0a9; end +\t8\'hda: begin outa = 10\'h0fe; end +\t8\'hdb: begin outa = 10\'h3c0; end +\t8\'hdc: begin outa = 10\'h1d9; end +\t8\'hdd: begin outa = 10\'h10e; end +\t8\'hde: begin outa = 10\'h394; end +\t8\'hdf: begin outa = 10\'h316; end +\t8\'he0: begin outa = 10\'h05b; end +\t8\'he1: begin outa = 10\'h126; end +\t8\'he2: begin outa = 10\'h369; end +\t8\'he3: begin outa = 10\'h291; end +\t8\'he4: begin outa = 10\'h2ca; end +\t8\'he5: begin outa = 10\'h25b; end +\t8\'he6: begin outa = 10\'h106; end +\t8\'he7: begin outa = 10\'h172; end +\t8\'he8: begin outa = 10\'h2f7; end +\t8\'he9: begin outa = 10\'h2d3; end +\t8\'hea: begin outa = 10\'h182; end +\t8\'heb: begin outa = 10\'h327; end +\t8\'hec: begin outa = 10\'h1d0; end +\t8\'hed: begin outa = 10\'h204; end +\t8\'hee: begin outa = 10\'h11f; end +\t8\'hef: begin outa = 10\'h365; end +\t8\'hf0: begin outa = 10\'h2c2; end +\t8\'hf1: begin outa = 10\'h2b5; end +\t8\'hf2: begin outa = 10\'h1f8; end +\t8\'hf3: begin outa = 10\'h2a7; end +\t8\'hf4: begin outa = 10\'h1be; end +\t8\'hf5: begin outa = 10\'h25e; end +\t8\'hf6: begin outa = 10\'h032; end +\t8\'hf7: begin outa = 10\'h2ef; end +\t8\'hf8: begin outa = 10\'h02f; end +\t8\'hf9: begin outa = 10\'h201; end +\t8\'hfa: begin outa = 10\'h054; end +\t8\'hfb: begin outa = 10\'h013; end +\t8\'hfc: begin outa = 10\'h249; end +\t8\'hfd: begin outa = 10\'h09a; end +\t8\'hfe: begin outa = 10\'h012; end +\t8\'hff: begin outa = 10\'h114; end + endcase + end +endmodule +" +"`define GOT_DEF3 1 +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +`define INT_RANGE 31:0 +`define INT_RANGE 31:0\t// Duplicate identical defs are OK +`define INT_RANGE_MAX 31 +`define VECTOR_RANGE 511:0 + +module t (clk); + + // verilator lint_off WIDTH + + parameter WIDTH = 16; // Must be a power of 2 + parameter WIDTH_LOG2 = 4; // set to log2(WIDTH) + parameter USE_BS = 1; // set to 1 for enable + + input clk; + + function [`VECTOR_RANGE] func_tree_left; + input [`VECTOR_RANGE] x; // x[width-1:0] is the input vector + reg [`VECTOR_RANGE] flip; + begin +\t flip = \'d0; +\t func_tree_left = flip; + end + endfunction + + reg [WIDTH-1:0] a; // value to be shifted + reg [WIDTH-1:0] \ttree_left; + always @(a) begin : barrel_shift + tree_left = func_tree_left (a); + end // barrel_shift + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin +\t cyc <= cyc + 1; +\t if (cyc==1) begin +\t a = 5; +\t end +\t if (cyc==2) begin +\t $display (""%x\ +"",tree_left); +\t //if (tree_left != \'d15) $stop; +\t $write(""*-* All Finished *-*\ +""); +\t $finish; +\t end + end + end + + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +`include ""t_pp_lib_inc.vh"" +module t(); + wire [`WIDTH-1:0] a; + library_cell n1(a); +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (clk); + input clk; + + // verilator lint_off WIDTH + +`define INT_RANGE 31:0 +`define INT_RANGE_MAX 31 +`define VECTOR_RANGE 63:0 + + reg [`INT_RANGE] stashb, stasha, stashn, stashm; + + function [`VECTOR_RANGE] copy_range; + input [`VECTOR_RANGE] y; + input [`INT_RANGE] b; + input [`INT_RANGE] a; + + input [`VECTOR_RANGE] x; + input [`INT_RANGE] n; + input [`INT_RANGE] m; + + begin +\t copy_range = y; +\t stashb = b; +\t stasha = a; +\t stashn = n; +\t stashm = m; + end + endfunction + + parameter DATA_SIZE = 16; + parameter NUM_OF_REGS = 32; + + reg [NUM_OF_REGS*DATA_SIZE-1 : 0] memread_rf; + reg [DATA_SIZE-1:0] \t\t memread_rf_reg; + always @(memread_rf) begin : memread_convert + memread_rf_reg = copy_range(\'d0, DATA_SIZE-\'d1, DATA_SIZE-\'d1, memread_rf, +\t\t\t\t DATA_SIZE-\'d1, DATA_SIZE-\'d1); + end + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin +\t cyc <= cyc + 1; +\t if (cyc==1) begin +\t memread_rf = 512\'haa; +\t end +\t if (cyc==3) begin +\t if (stashb != \'d15) $stop; +\t if (stasha != \'d15) $stop; +\t if (stashn != \'d15) $stop; +\t if (stashm != \'d15) $stop; +\t $write(""*-* All Finished *-*\ +""); +\t $finish; +\t end + end + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + // verilator lint_off COMBDLY + // verilator lint_off UNOPT + // verilator lint_off UNOPTFLAT + + reg \t c1_start; initial c1_start = 0; + wire [31:0] c1_count; + comb_loop c1 (.count(c1_count), .start(c1_start)); + + wire s2_start = (c1_count==0 && c1_start); + wire [31:0] s2_count; + seq_loop s2 (.count(s2_count), .start(s2_start)); + + wire c3_start = (s2_count[0]); + wire [31:0] c3_count; + comb_loop c3 (.count(c3_count), .start(c3_start)); + + reg [7:0] cyc; initial cyc=0; + always @ (posedge clk) begin + //$write(""[%0t] %x counts %x %x %x\ +"",$time,cyc,c1_count,s2_count,c3_count); + cyc <= cyc + 8\'d1; + case (cyc) +\t8\'d00: begin +\t c1_start <= 1\'b0; +\tend +\t8\'d01: begin +\t c1_start <= 1\'b1; +\tend +\tdefault: ; + endcase + case (cyc) +\t8\'d02: begin +\t if (c1_count!=32\'h3) $stop; +\t if (s2_count!=32\'h3) $stop; +\t if (c3_count!=32\'h6) $stop; +\tend +\t8\'d03: begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; +\tend +\tdefault: ; + endcase + end +endmodule + +module comb_loop (/*AUTOARG*/ + // Outputs + count, + // Inputs + start + ); + input start; + output reg [31:0] count; initial count = 0; + + reg [31:0] \t runnerm1, runner; initial runner = 0; + + always @ (start) begin + if (start) begin +\t runner = 3; + end + end + + always @ (/*AS*/runner) begin + runnerm1 = runner - 32\'d1; + end + + always @ (/*AS*/runnerm1) begin + if (runner > 0) begin +\t count = count + 1; +\t runner = runnerm1; +\t $write (""%m count=%d runner =%x\ +"",count, runnerm1); + end + end + +endmodule + +module seq_loop (/*AUTOARG*/ + // Outputs + count, + // Inputs + start + ); + input start; + output reg [31:0] count; initial count = 0; + + reg [31:0] \t runnerm1, runner; initial runner = 0; + + always @ (start) begin + if (start) begin +\t runner <= 3; + end + end + + always @ (/*AS*/runner) begin + runnerm1 = runner - 32\'d1; + end + + always @ (/*AS*/runnerm1) begin + if (runner > 0) begin +\t count = count + 1; +\t runner <= runnerm1; +\t $write (""%m count=%d runner<=%x\ +"",count, runnerm1); + end + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + integer \tcyc=0; + + reg [6:0] mem1d; + reg [6:0] mem2d [5:0]; + reg [6:0] mem3d [4:0][5:0]; + + integer i,j,k; + + // Four different test cases for out of bounds + //\t= + //\t<= + // Continuous assigns + //\tOutput pin interconnect (also covers cont assigns) + // Each with both bit selects and array selects + + initial begin + mem1d[0] = 1\'b0; + i=7; + mem1d[i] = 1\'b1; + if (mem1d[0] !== 1\'b0) $stop; + // + for (i=0; i<8; i=i+1) begin +\t for (j=0; j<8; j=j+1) begin +\t for (k=0; k<8; k=k+1) begin +\t mem1d[k] = k[0]; +\t mem2d[j][k] = j[0]+k[0]; +\t mem3d[i][j][k] = i[0]+j[0]+k[0]; +\t end +\t end + end + for (i=0; i<5; i=i+1) begin +\t for (j=0; j<6; j=j+1) begin +\t for (k=0; k<7; k=k+1) begin +\t if (mem1d[k] !== k[0]) $stop; +\t if (mem2d[j][k] !== j[0]+k[0]) $stop; +\t if (mem3d[i][j][k] !== i[0]+j[0]+k[0]) $stop; +\t end +\t end + end + end + + integer wi; + wire [31:0] wd = cyc; + reg [31:0] reg2d[6:0]; + always @ (posedge clk) reg2d[wi[2:0]] <= wd; + + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write(""[%0t] cyc==%0d reg2d[%0d]=%0x wd=%0x\ +"",$time, cyc, wi[2:0], reg2d[wi[2:0]], wd); +`endif + cyc <= cyc + 1; + if (cyc<10) begin +\t wi <= 0; + end + else if (cyc==10) begin +\t wi <= 1; + end + else if (cyc==11) begin +\t if (reg2d[0] !== 10) $stop; +\t wi <= 6; + end + else if (cyc==12) begin +\t if (reg2d[0] !== 10) $stop; +\t if (reg2d[1] !== 11) $stop; +\t wi <= 7; // Will be ignored + end + else if (cyc==13) begin +\t if (reg2d[0] !== 10) $stop; +\t if (reg2d[1] !== 11) $stop; +\t if (reg2d[6] !== 12) $stop; + end + else if (cyc==14) begin +\t if (reg2d[0] !== 10) $stop; +\t if (reg2d[1] !== 11) $stop; +\t if (reg2d[6] !== 12) $stop; + end + else if (cyc==99) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +module t (); + + // This isn't a width violation, as +/- 1'b1 is a common idiom + // that's fairly harmless + wire [4:0] five = 5'd5; + wire [4:0] suma = five + 1'b1; + wire [4:0] sumb = 1'b1 + five; + wire [4:0] sumc = five - 1'b1; + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008-2008 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer \tcyc=0; + reg [63:0] \tcrc; + reg [63:0] \tsum; + + wire [9:0] I1 = crc[9:0]; + wire [9:0] I2 = crc[19:10]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [9:0]\t\tS;\t\t\t// From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ +\t // Outputs +\t .S\t\t\t(S[9:0]), +\t // Inputs +\t .I1\t\t\t(I1[9:0]), +\t .I2\t\t\t(I2[9:0])); + + wire [63:0] result = {32\'h0, 22\'h0, S}; + +`define EXPECTED_SUM 64\'h24c38b77b0fcc2e7 + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write(""[%0t] cyc==%0d crc=%x result=%x\ +"",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin +\t // Setup +\t crc <= 64\'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin +\t sum <= 64\'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin +\t $write(""[%0t] cyc==%0d crc=%x sum=%x\ +"",$time, cyc, crc, sum); +\t if (crc !== 64\'hc77bb9b3784ea091) $stop; +\t if (sum !== `EXPECTED_SUM) $stop; +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + S, + // Inputs + I1, I2 + ); + + input [9:0] I1/*verilator public*/; + input [9:0] I2/*verilator public*/; + output reg [9:0] S/*verilator public*/; + + always @(I1 or I2) + t2(I1,I2,S); + + task t1; + input In1,In2; + output Sum; + Sum = In1 ^ In2; + endtask + + task t2; + input[9:0] In1,In2; + output [9:0] Sum; + integer \t I; + begin +\t for (I=0;I<10;I=I+1) +\t t1(In1[I],In2[I],Sum[I]); + end + endtask +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003-2007 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + integer \tcyc=0; + + wire \tout; + reg \t\tin; + + Genit g (.clk(clk), .value(in), .result(out)); + + always @ (posedge clk) begin + //$write(""[%0t] cyc==%0d %x %x\ +"",$time, cyc, in, out); + cyc <= cyc + 1; + if (cyc==0) begin +\t // Setup +\t in <= 1\'b1; + end + else if (cyc==1) begin +\t in <= 1\'b0; + end + else if (cyc==2) begin +\t if (out != 1\'b1) $stop; + end + else if (cyc==3) begin +\t if (out != 1\'b0) $stop; + end + else if (cyc==9) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end + +//`define WAVES +`ifdef WAVES + initial begin + $dumpfile(""obj_dir/t_gen_intdot/t_gen_intdot.vcd""); + $dumpvars(12, t); + end +`endif + +endmodule + +module Generate (clk, value, result); + input clk; + input value; + output result; + + reg Internal; + + assign result = Internal ^ clk; + + always @(posedge clk) + Internal <= #1 value; +endmodule + +module Checker (clk, value); + input clk, value; + + always @(posedge clk) begin + $write (""[%0t] value=%h\ +"", $time, value); + end + +endmodule + +module Test (clk, value, result); + input clk; + input value; + output result; + + Generate gen (clk, value, result); + Checker chk (clk, gen.Internal); + +endmodule + +module Genit (clk, value, result); + input clk; + input value; + output result; + +`ifndef ATSIM // else unsupported + `ifndef NC // else unsupported + `define WITH_FOR_GENVAR + `endif +`endif + +`define WITH_GENERATE +`ifdef WITH_GENERATE + `ifndef WITH_FOR_GENVAR + genvar i; + `endif + generate + for ( + `ifdef WITH_FOR_GENVAR +\t genvar + `endif +\t i = 0; i < 1; i = i + 1) +\tbegin : foo +\t Test tt (clk, value, result); +\tend + endgenerate +`else + Test tt (clk, value, result); +`endif + + wire Result2 = t.g.foo[0].tt.gen.Internal; // Works - Do not change! + always @ (posedge clk) begin + $write(""[%0t] Result2 = %x\ +"", $time, Result2); + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + const logic [2:0] five = 3\'d5; + + always @ (posedge clk) begin + five = 3\'d4; + if (five !== 3\'d5) $stop; + $write(""*-* All Finished *-*\ +""); + $finish; + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// simplistic example, should choose 1st conditional generate and assign straight through +// the tool also compiles the special case and determines an error (replication value is 0) +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. +`timescale 1ns / 1ps + +module t(data_i, data_o, single); + parameter op_bits = 32; + input [op_bits -1:0] data_i; + output [31:0] data_o; + input single; + + //simplistic example, should choose 1st conditional generate and assign straight through + //the tool also compiles the special case and determines an error (replication value is 0 + generate + if (op_bits == 32) begin : general_case + assign data_o = data_i; +\t // Test implicit signals +\t /* verilator lint_off IMPLICIT */ +\t assign imp = single; +\t /* verilator lint_on IMPLICIT */ + end + else begin : special_case + assign data_o = {{(32 -op_bits){1'b0}},data_i}; +\t /* verilator lint_off IMPLICIT */ +\t assign imp = single; +\t /* verilator lint_on IMPLICIT */ + end + endgenerate +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t_inst_first_a (/*AUTOARG*/ + // Outputs + o_w5, o_w5_d1r, o_w40, o_w104, + // Inputs + clk, i_w5, i_w40, i_w104 + ); + + input clk; + + input [4:0] \t\ti_w5; + output [4:0] \to_w5; + output [4:0] \to_w5_d1r; + input [39:0] \ti_w40; + output [39:0] \to_w40; + input [104:0] \ti_w104; + output [104:0] \to_w104; + + wire [4:0] o_w5 = i_w5; + wire [39:0] o_w40 = i_w40; + wire [104:0] o_w104 = i_w104; + + /*AUTOREG*/ + // Beginning of automatic regs (for this module's undeclared outputs) + reg [4:0]\t\to_w5_d1r; + // End of automatics + + always @ (posedge clk) begin + o_w5_d1r <= i_w5; + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +module t; + + integer i; + + initial begin +`ifndef VERILATOR + `ifndef VCS + `ifndef NC + $system(); // Legal per spec, but not supported everywhere and nonsensical + `endif + `endif +`endif + $system(""exit 0""); + $system(""echo hello""); +`ifndef VCS + i = $system(""exit 0""); + if (i!==0) $stop; + i = $system(""exit 10""); + if (i!==10) $stop; +`endif + + $write(""*-* All Finished *-*\ +""); + $finish; + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +`begin_keywords ""VAMS-2.3"" + +module t (/*autoarg*/ + // Outputs + aout, + // Inputs + in + ); + + input [15:0] in; + output \taout; + wreal aout; + + parameter real lsb = 1; + // verilator lint_off WIDTH + assign aout = $itor(in) * lsb; + + initial begin + $write(""*-* All Finished *-*\ +""); + $finish; + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + tri z0; + tri z1; + + updown #(0) updown0 (.z(z0)); + updown #(1) updown1 (.z(z1)); + + always @ (posedge clk) begin + if (z0 !== 0) $stop; + if (z1 !== 1) $stop; + $write(""*-* All Finished *-*\ +""); + $finish; + end + +endmodule + +module updown #(parameter UP=0) + (inout z); + generate + if (UP) begin +\t t_up sub (.z); + end + else begin +\t t_down sub (.z); + end + endgenerate +endmodule + +module t_up (inout tri1 z); +endmodule + +module t_down (inout tri0 z); +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg [31:0] a, b, c, d, e, f, g, h; + + always @ (*) begin // Test Verilog 2001 (*) + // verilator lint_off COMBDLY + c <= a | b; + // verilator lint_on COMBDLY + end + + always @ (posedge (clk)) begin // always bug 2008/4/18 + d <= a | b; + end + always @ ((d)) begin // always bug 2008/4/18 + e = d; + end + + parameter CONSTANT = 1; + always @ (e, 1\'b0, CONSTANT) begin // not technically legal, see bug412 + f = e; + end + always @ (1\'b0, CONSTANT, f) begin // not technically legal, see bug412 + g = f; + end + always @ ({CONSTANT, g}) begin // bug745 + h = g; + end + //always @ ((posedge b) or (a or b)) begin // note both illegal + + always @ (posedge clk) begin + if (cyc!=0) begin +\t cyc<=cyc+1; +\t if (cyc==1) begin +\t a <= 32\'hfeed0000; +\t b <= 32\'h0000face; +\t end +\t if (cyc==2) begin +\t if (c != 32\'hfeedface) $stop; +\t end +\t if (cyc==3) begin +\t if (h != 32\'hfeedface) $stop; +\t end +\t if (cyc==7) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; +\t end + end + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module a(); +endmodule + +module test(); + a a(); +endmodule + +module a(); +endmodule + +module b(); +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +module t (/*AUTOARG*/); + + typedef struct packed { + logic [3:2] a; + logic [5:4][3:2] b; + } ab_t; + typedef ab_t [7:6] c_t; // array of structs + typedef struct packed { + c_t [17:16] d; + } e_t; + +`define checkb(gotv,expv) do if ((gotv) !== (expv)) begin $write(""%%Error: %s:%0d: got=\'b%x exp=\'b%x\ +"", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write(""%%Error: %s:%0d: got=\'h%x exp=\'h%x\ +"", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); + + initial begin + e_t e; + `checkh($bits(ab_t),6); + `checkh($bits(c_t),12); + `checkh($bits(e_t),24); + `checkh($bits(e), 24); + `checkh($bits(e.d[17]),12); + `checkh($bits(e.d[16][6]),6); + `checkh($bits(e.d[16][6].b[5]),2); + `checkh($bits(e.d[16][6].b[5][2]), 1); + // + e = 24\'b101101010111010110101010; + `checkb(e, 24\'b101101010111010110101010); + e.d[17] = 12\'b111110011011; + `checkb(e, 24\'b111110011011010110101010); + e.d[16][6] = 6\'b010101; + `checkb(e, 24\'b111110011011010110010101); + e.d[16][6].b[5] = 2\'b10; + `checkb(e, 24\'b111110011011010110011001); + e.d[16][6].b[5][2] = 1\'b1; + // + $write(""*-* All Finished *-*\ +""); + $finish; + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (); + + // See also t_math_width + + // This shows the uglyness in width warnings across param modules + // TODO: Would be nice to also show relevant parameter settings + p #(.WIDTH(4)) p4 (.in(4'd0)); + p #(.WIDTH(5)) p5 (.in(5'd0)); + + //==== + localparam [3:0]\tXS = 'hx; // User presumably intended to use 'x + + //==== + wire [4:0] c = 1'b1 << 2; // No width warning, as is common syntax + wire [4:0] d = (1'b1 << 2) + 5'b1; // Has warning as not obvious what expression width is + + //==== + localparam\t\tWIDTH = 6; + wire \t\tone_bit; + wire\t[2:0]\t\tshifter = 1; + wire [WIDTH-1:0] \tmasked = (({{(WIDTH){1'b0}}, one_bit}) << shifter); + + //==== + // We presently warn here, in theory we could detect if the number of one bit additions could overflow the LHS + wire \t\tone = 1; + wire [2:0] \t\tcnt = (one + one + one + one); + +endmodule + +module p + #(parameter WIDTH=64) + (input [WIDTH-1:0] in); + wire [4:0] out = in; +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008-2008 by Wilson Snyder. + +module t (/*AUTOARG*/); + + reg [4*8:1] strg; + + initial begin + strg = ""CHK""; + if (strg != ""CHK"") $stop; + if (strg == ""JOE"") $stop; + $write(""String = %s = %x\ +"", strg, strg); + $write(""*-* All Finished *-*\ +""); + $finish; + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg [255:0] \t\ta; + reg [255:0] \t\tq; + reg [63:0] \t\tqq; + + integer \t\ti; + always @* begin + for (i=0; i<256; i=i+1) begin +\t q[255-i] = a[i]; + end + q[27:16] = 12\'hfed; + for (i=0; i<64; i=i+1) begin +\t qq[63-i] = a[i]; + end + qq[27:16] = 12\'hfed; + end + + always @ (posedge clk) begin + if (cyc!=0) begin +\t cyc <= cyc + 1; +`ifdef TEST_VERBOSE +\t $write(""%x/%x %x\ +"", q, qq, a); +`endif +\t if (cyc==1) begin +\t a = 256\'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26; +\t end +\t if (cyc==2) begin +\t a = 256\'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8; +\t if (q != 256\'h64fe7e285bcf892eca128d426ed707a20eebc824d5d9127bacbc21362fed1cb7) $stop; +\t if (qq != 64\'h64fe7e285fed892e) $stop; +\t end +\t if (cyc==3) begin +\t if (q != 256\'h1da9cf939c0712504b5bdbbbbfbb6c47c316bd471362641958a7fabcffede870) $stop; +\t if (qq != 64\'h1da9cf939fed1250) $stop; +\t end +\t if (cyc==4) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; +\t end + end + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +package defs; + function automatic integer max; + input integer a; + input integer b; + max = (a > b) ? a : b; + endfunction + + function automatic integer log2; + input integer value; + value = value >> 1; + for (log2 = 0; value > 0; log2 = log2 + 1) + value = value >> 1; + endfunction + + function automatic integer ceil_log2; + input integer value; + value = value - 1; + for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1) + value = value >> 1; + endfunction +endpackage + +module sub(); + + import defs::*; + + parameter RAND_NUM_MAX = """"; + + localparam DATA_RANGE = RAND_NUM_MAX + 1; + localparam DATA_WIDTH = ceil_log2(DATA_RANGE); + localparam WIDTH = max(4, ceil_log2(DATA_RANGE + 1)); + +endmodule + +module t(/*AUTOARG*/ + // Inputs + clk + ); + + import defs::*; + + parameter WHICH = 0; + parameter MAX_COUNT = 10; + + localparam MAX_EXPONENT = log2(MAX_COUNT); + localparam EXPONENT_WIDTH = ceil_log2(MAX_EXPONENT + 1); + + input clk; + + generate + if (WHICH == 1) +\tbegin : which_true + sub sub_true(); + defparam sub_true.RAND_NUM_MAX = MAX_EXPONENT; +\tend + else +\tbegin : which_false + sub sub_false(); + defparam sub_false.RAND_NUM_MAX = MAX_COUNT; +\tend + endgenerate + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2009 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +`ifdef VCS + `define NO_SHORTREAL +`endif +`ifdef NC + `define NO_SHORTREAL +`endif +`ifdef VERILATOR // Unsupported + `define NO_SHORTREAL +`endif + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + // Allowed import return types: + // void, byte, shortint, int, longint, real, shortreal, chandle, and string + // Scalar bit and logic + // + // Allowed argument types: + //\t Same as above plus packed arrays + + import ""DPI-C"" pure function bit dpii_f_bit (input bit i); + import ""DPI-C"" pure function bit [8-1:0] dpii_f_bit8 (input bit [8-1:0] i); + import ""DPI-C"" pure function bit [9-1:0] dpii_f_bit9 (input bit [9-1:0] i); + import ""DPI-C"" pure function bit [16-1:0] dpii_f_bit16 (input bit [16-1:0] i); + import ""DPI-C"" pure function bit [17-1:0] dpii_f_bit17 (input bit [17-1:0] i); + import ""DPI-C"" pure function bit [32-1:0] dpii_f_bit32 (input bit [32-1:0] i); + // Illegal to return > 32 bits, so we use longint + import ""DPI-C"" pure function longint dpii_f_bit33 (input bit [33-1:0] i); + import ""DPI-C"" pure function longint\t dpii_f_bit64 (input bit [64-1:0] i); + import ""DPI-C"" pure function int dpii_f_int (input int i); + import ""DPI-C"" pure function byte dpii_f_byte (input byte i); + import ""DPI-C"" pure function shortint dpii_f_shortint (input shortint i); + import ""DPI-C"" pure function longint dpii_f_longint (input longint i); + import ""DPI-C"" pure function chandle dpii_f_chandle (input chandle i); + import ""DPI-C"" pure function string dpii_f_string (input string i); + import ""DPI-C"" pure function real dpii_f_real (input real i); +`ifndef NO_SHORTREAL + import ""DPI-C"" pure function shortreal dpii_f_shortreal(input shortreal i); +`endif + + import ""DPI-C"" pure function void dpii_v_bit (input bit i, output bit o); + import ""DPI-C"" pure function void dpii_v_int (input int i, output int o); + import ""DPI-C"" pure function void dpii_v_byte (input byte i, output byte o); + import ""DPI-C"" pure function void dpii_v_shortint (input shortint i, output shortint o); + import ""DPI-C"" pure function void dpii_v_longint (input longint i, output longint o); + import ""DPI-C"" pure function void dpii_v_chandle (input chandle i, output chandle o); + import ""DPI-C"" pure function void dpii_v_string (input string i, output string o); + import ""DPI-C"" pure function void dpii_v_real (input real i, output real o); + + import ""DPI-C"" pure function void dpii_v_uint (input int unsigned i, output int unsigned o); + import ""DPI-C"" pure function void dpii_v_ushort (input shortint unsigned i, output shortint unsigned o); + import ""DPI-C"" pure function void dpii_v_ulong (input longint unsigned i, output longint unsigned o); +`ifndef NO_SHORTREAL + import ""DPI-C"" pure function void dpii_v_shortreal(input shortreal i, output shortreal o); +`endif + import ""DPI-C"" pure function void dpii_v_bit64 (input bit [64-1:0] i, output bit [64-1:0] o); + import ""DPI-C"" pure function void dpii_v_bit95 (input bit [95-1:0] i, output bit [95-1:0] o); + import ""DPI-C"" pure function void dpii_v_bit96 (input bit [96-1:0] i, output bit [96-1:0] o); + + import ""DPI-C"" pure function int dpii_f_strlen (input string i); + + import ""DPI-C"" function void dpii_f_void (); + + // Try a task + import ""DPI-C"" task dpii_t_void (); + import ""DPI-C"" context task dpii_t_void_context (); + + import ""DPI-C"" task dpii_t_int (input int i, output int o); + + // Try non-pure, aliasing with name + import ""DPI-C"" dpii_fa_bit = function int oth_f_int1(input int i); + import ""DPI-C"" dpii_fa_bit = function int oth_f_int2(input int i); + + bit \ti_b,\to_b; + bit [7:0] i_b8; + bit [8:0]\ti_b9; + bit [15:0]\ti_b16; + bit [16:0] i_b17; + bit [31:0]\ti_b32; + bit [32:0]\ti_b33,\to_b33; + bit [63:0]\ti_b64,\to_b64; + bit [94:0]\ti_b95,\to_b95; + bit [95:0]\ti_b96,\to_b96; + + int\t\ti_i,\to_i; + byte\t\ti_y,\to_y; + shortint\ti_s,\to_s; + longint\ti_l,\to_l; + int unsigned\t\ti_iu,\to_iu; + shortint unsigned\ti_su,\to_su; + longint unsigned\ti_lu,\to_lu; + // verilator lint_off UNDRIVEN + chandle\ti_c,\to_c; + string \ti_n,\to_n; + // verilator lint_on UNDRIVEN + real \ti_d,\to_d; +`ifndef NO_SHORTREAL + shortreal \ti_f,\to_f; +`endif + + bit [94:0] wide; + + bit [6*8:1] string6; + + initial begin + wide = 95\'h15caff7a73c48afee4ffcb57; + + i_b = 1\'b1; + i_b8 = {1\'b1,wide[8-2:0]}; + i_b9 = {1\'b1,wide[9-2:0]}; + i_b16 = {1\'b1,wide[16-2:0]}; + i_b17 = {1\'b1,wide[17-2:0]}; + i_b32 = {1\'b1,wide[32-2:0]}; + i_b33 = {1\'b1,wide[33-2:0]}; + i_b64 = {1\'b1,wide[64-2:0]}; + i_b95 = {1\'b1,wide[95-2:0]}; + i_b96 = {1\'b1,wide[96-2:0]}; + + i_i = {1\'b1,wide[32-2:0]}; + i_iu= {1\'b1,wide[32-2:0]}; + i_y = {1\'b1,wide[8-2:0]}; + i_s = {1\'b1,wide[16-2:0]}; + i_su= {1\'b1,wide[16-2:0]}; + i_l = {1\'b1,wide[64-2:0]}; + i_lu= {1\'b1,wide[64-2:0]}; + i_d = 32.1; +`ifndef NO_SHORTREAL + i_f = 30.2; +`endif + + if (dpii_f_bit (i_b) !== ~i_b) $stop; + if (dpii_f_bit8 (i_b8) !== ~i_b8) $stop; + if (dpii_f_bit9 (i_b9) !== ~i_b9) $stop; + if (dpii_f_bit16 (i_b16) !== ~i_b16) $stop; + if (dpii_f_bit17 (i_b17) !== ~i_b17) $stop; + if (dpii_f_bit32 (i_b32) !== ~i_b32) $stop; + + // These return different sizes, so we need to truncate + // verilator lint_off WIDTH + o_b33 = dpii_f_bit33 (i_b33); + o_b64 = dpii_f_bit64 (i_b64); + // verilator lint_on WIDTH + if (o_b33 !== ~i_b33) $stop; + if (o_b64 !== ~i_b64) $stop; + + if (dpii_f_bit (i_b) !== ~i_b) $stop; + if (dpii_f_int (i_i) !== ~i_i) $stop; + if (dpii_f_byte (i_y) !== ~i_y) $stop; + if (dpii_f_shortint (i_s) !== ~i_s) $stop; + if (dpii_f_longint (i_l) !== ~i_l) $stop; + if (dpii_f_chandle (i_c) !== i_c) $stop; + if (dpii_f_string (i_n) != i_n) $stop; + if (dpii_f_real (i_d) != i_d+1.5) $stop; +`ifndef NO_SHORTREAL + if (dpii_f_shortreal(i_f) != i_f+1.5) $stop; +`endif + + dpii_v_bit (i_b,o_b); if (o_b !== ~i_b) $stop; + dpii_v_int (i_i,o_i); if (o_i !== ~i_i) $stop; + dpii_v_byte (i_y,o_y); if (o_y !== ~i_y) $stop; + dpii_v_shortint (i_s,o_s); if (o_s !== ~i_s) $stop; + dpii_v_longint (i_l,o_l); if (o_l !== ~i_l) $stop; + dpii_v_uint (i_iu,o_iu); if (o_iu !== ~i_iu) $stop; + dpii_v_ushort (i_su,o_su); if (o_su !== ~i_su) $stop; + dpii_v_ulong (i_lu,o_lu); if (o_lu !== ~i_lu) $stop; + dpii_v_chandle (i_c,o_c); if (o_c !== i_c) $stop; + dpii_v_string (i_n,o_n); if (o_n != i_n) $stop; + dpii_v_real (i_d,o_d); if (o_d != i_d+1.5) $stop; +`ifndef NO_SHORTREAL + dpii_v_shortreal(i_f,o_f); if (o_f != i_f+1.5) $stop; +`endif + dpii_v_bit64 (i_b64,o_b64); if (o_b64 !== ~i_b64) $stop; + dpii_v_bit95 (i_b95,o_b95); if (o_b95 !== ~i_b95) $stop; + dpii_v_bit96 (i_b96,o_b96); if (o_b96 !== ~i_b96) $stop; + + if (dpii_f_strlen ("""")!=0) $stop; + if (dpii_f_strlen (""s"")!=1) $stop; + if (dpii_f_strlen (""st"")!=2) $stop; + if (dpii_f_strlen (""str"")!=3) $stop; + if (dpii_f_strlen (""stri"")!=4) $stop; + if (dpii_f_strlen (""string_l"")!=8) $stop; + if (dpii_f_strlen (""string_len"")!=10) $stop; + string6 = ""hello6""; +`ifdef VERILATOR + string6 = $c48(string6); // Don\'t optimize away - want to see the constant conversion function +`endif + if (dpii_f_strlen (string6) != 6) $stop; + + dpii_f_void(); + dpii_t_void(); + dpii_t_void_context(); + + i_i = 32\'h456789ab; + dpii_t_int (i_i,o_i); if (o_b !== ~i_b) $stop; + + // Check alias + if (oth_f_int1(32\'d123) !== ~32\'d123) $stop; + if (oth_f_int2(32\'d124) !== ~32\'d124) $stop; + + $write(""*-* All Finished *-*\ +""); + $finish; + end + + always @ (posedge clk) begin + i_b <= ~i_b; + // This once mis-threw a BLKSEQ warning + dpii_v_bit (i_b,o_b); if (o_b !== ~i_b) $stop; + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + function int f_no_no (); + int st = 2; st++; return st; + endfunction + function int f_no_st (); + static int st = 2; st++; return st; + endfunction + function int f_no_au (); + automatic int st = 2; st++; return st; + endfunction + + function static int f_st_no (); + int st = 2; st++; return st; + endfunction + function static int f_st_st (); + static int st = 2; st++; return st; + endfunction + function static int f_st_au (); + automatic int st = 2; st++; return st; + endfunction + + function automatic int f_au_no (); + int st = 2; st++; return st; + endfunction + function automatic int f_au_st (); + static int st = 2; st++; return st; + endfunction + function automatic int f_au_au (); + automatic int st = 2; st++; return st; + endfunction + + initial begin + if (f_no_no() != 3) $stop; + if (f_no_no() != 4) $stop; + if (f_no_st() != 3) $stop; + if (f_no_st() != 4) $stop; + if (f_no_au() != 3) $stop; + if (f_no_au() != 3) $stop; + // + if (f_st_no() != 3) $stop; + if (f_st_no() != 4) $stop; + if (f_st_st() != 3) $stop; + if (f_st_st() != 4) $stop; + if (f_st_au() != 3) $stop; + if (f_st_au() != 3) $stop; + // + if (f_au_no() != 3) $stop; + if (f_au_no() != 3) $stop; + if (f_au_st() != 3) $stop; + if (f_au_st() != 4) $stop; + if (f_au_au() != 3) $stop; + if (f_au_au() != 3) $stop; + // + $write(""*-* All Finished *-*\ +""); + $finish; + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2007 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + reg \t toggle; + integer cyc; initial cyc=1; + + Test suba (/*AUTOINST*/ +\t // Inputs +\t .clk\t\t\t(clk), +\t .toggle\t\t\t(toggle), +\t .cyc\t\t\t(cyc[31:0])); + Test subb (/*AUTOINST*/ +\t // Inputs +\t .clk\t\t\t(clk), +\t .toggle\t\t\t(toggle), +\t .cyc\t\t\t(cyc[31:0])); + Test subc (/*AUTOINST*/ +\t // Inputs +\t .clk\t\t\t(clk), +\t .toggle\t\t\t(toggle), +\t .cyc\t\t\t(cyc[31:0])); + + always @ (posedge clk) begin + if (cyc!=0) begin +\t cyc <= cyc + 1; +\t toggle <= !cyc[0]; +\t if (cyc==9) begin +\t end +\t if (cyc==10) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; +\t end + end + end + +endmodule + +module Test + ( + input clk, + input toggle, + input [31:0] cyc + ); + + // Don\'t flatten out these modules please: + // verilator no_inline_module + + // Labeled cover + cyc_eq_5: cover property (@(posedge clk) cyc==5) $display(""*COVER: Cyc==5""); + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (clk); + + input clk; + + reg [7:0] \ta,b; + wire [7:0] \tz; + + mytop u0 ( a, b, clk, z ); + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin +\t cyc <= cyc + 1; +\t //$write(""%d %x\ +"", cyc, z); +\t if (cyc==1) begin +\t a <= 8\'h07; +\t b <= 8\'h20; +\t end +\t if (cyc==2) begin +\t a <= 8\'h8a; +\t b <= 8\'h12; +\t end +\t if (cyc==3) begin +\t if (z !== 8\'hdf) $stop; +\t a <= 8\'h71; +\t b <= 8\'hb2; +\t end +\t if (cyc==4) begin +\t if (z !== 8\'hed) $stop; +\t end +\t if (cyc==5) begin +\t if (z !== 8\'h4d) $stop; +\t end +\t if (cyc==9) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; +\t end + end + end + +endmodule // mytop + +module inv( + input [ 7:0 ] a, + output [ 7:0 ] z + ); + wire [7:0] \t\t z = ~a; +endmodule + + +module ftest( + input [ 7:0 ] a, + b, // Test legal syntax + input clk, + output [ 7:0 ] z + ); + + wire [7:0] \t\t zi; + reg [7:0] \t\t z; + + inv u1 (.a(myadd(a,b)), +\t .z(zi)); + + + always @ ( posedge clk ) begin + z <= myadd( a, zi ); + end + + function [ 7:0 ] myadd; + input [7:0] ina; + input [7:0] inb; + + begin + myadd = ina + inb; + end + endfunction // myadd + +endmodule // ftest + +module mytop ( + input [ 7:0 ] a, + b, + input clk, + output [ 7:0 ] z + ); + + ftest u0( a, b, clk, z ); + +endmodule // mytop +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + reg [125:0] a; + wire q; + + sub sub ( +\t .q\t\t\t\t(q), +\t .a\t\t\t\t(a), +\t .clk\t\t\t(clk)); + + always @ (posedge clk) begin + if (cyc!=0) begin +\t cyc <= cyc + 1; +\t if (cyc==1) begin +\t a <= 126\'b1000; +\t end +\t if (cyc==2) begin +\t a <= 126\'h1001; +\t end +\t if (cyc==3) begin +\t a <= 126\'h1010; +\t end +\t if (cyc==4) begin +\t a <= 126\'h1111; +\t if (q !== 1\'b0) $stop; +\t end +\t if (cyc==5) begin +\t if (q !== 1\'b1) $stop; +\t end +\t if (cyc==6) begin +\t if (q !== 1\'b0) $stop; +\t end +\t if (cyc==7) begin +\t if (q !== 1\'b0) $stop; +\t end +\t if (cyc==8) begin +\t if (q !== 1\'b0) $stop; +\t $write(""*-* All Finished *-*\ +""); +\t $finish; +\t end + end + end + +endmodule + +module sub ( + input clk, + input [125:0] a, + output reg q + ); + + // verilator public_module + + reg [125:0] g_r; + + wire [127:0] g_extend = { g_r, 1\'b1, 1\'b0 }; + + reg [6:0] sel; + wire g_sel = g_extend[sel]; + + always @ (posedge clk) begin + g_r <= a; + sel <= a[6:0]; + q <= g_sel; + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +module t (clk); + input clk; + integer \tcyc=0; + + // Trace would overflow at 256KB which is 256 kb dump, 16 kb in a chunk + + typedef struct packed { + logic [1024*1024:0] d; + } s1_t; // 128 b + + s1_t biggie; + + always @ (posedge clk) begin + cyc <= cyc + 1; + biggie [ cyc +: 32 ] <= 32\'hfeedface; + if (cyc == 5) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write(""%%Error: %s:%0d: got=\'h%x exp=\'h%x\ +"", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer \tcyc=0; + reg [63:0] \tcrc; + reg [63:0] \tsum; + /*AUTOWIRE*/ + + generate + for (genvar width=1; width<=16; width++) begin +\t for (genvar amt=1; amt<=width; amt++) begin +\t Test #(.WIDTH(width), +\t\t .AMT(amt)) +\t test (.ins(crc[width-1:0])); +\t end + end + endgenerate + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write(""[%0t] cyc==%0d crc=%x\ +"", +\t $time, cyc, crc); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + if (cyc==0) begin +\t // Setup +\t crc <= 64\'h5aef0c8d_d70a4497; +\t sum <= 64\'h0; + end + else if (cyc<10) begin +\t sum <= 64\'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin +\t $write(""[%0t] cyc==%0d crc=%x sum=%x\ +"",$time, cyc, crc, sum); +\t if (crc !== 64\'hc77bb9b3784ea091) $stop; +\t // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64\'h0 +\t if (sum !== `EXPECTED_SUM) $stop; +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Inputs + ins + ); + + parameter WIDTH = 1; + parameter AMT = 1; + + input [WIDTH-1:0] ins; + reg [WIDTH-1:0] got; + reg [WIDTH-1:0] expec; + int \t\t istart; + int \t\t bitn; + int \t\t ostart; + + always @* begin + got = { << AMT {ins}}; + + // Note always starts with right-most bit + expec = 0; + for (istart=0; istart= 0 +\t\t&& (ostart+bitn) < WIDTH +\t\t&& (ostart+bitn) >= 0) begin +\t expec[ostart+bitn] = ins[istart+bitn]; +\t end +\t end + end + +`ifdef TEST_VERBOSE + $write(""[%0t] exp %0d\'b%b got %0d\'b%b = { << %0d { %0d\'b%b }}\ +"", $time, WIDTH, expec, WIDTH, got, AMT, WIDTH, ins); +`endif + `checkh(got, expec); + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer \tcyc=0; + reg [63:0] \tcrc; + reg [63:0] \tsum; + + // verilator lint_off MULTIDRIVEN + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0]\t\tout;\t\t\t// From test of Test.v + wire [15:0]\t\tout2;\t\t\t// From test of Test.v + // End of automatics + // verilator lint_on MULTIDRIVEN + + Test test ( +\t .en (crc[21:20]), +\t .a1 (crc[19:18]), +\t .a0 (crc[17:16]), +\t .d1 (crc[15:8]), +\t .d0 (crc[7:0]), +\t /*AUTOINST*/ +\t // Outputs +\t .out\t\t\t(out[31:0]), +\t .out2\t\t\t(out2[15:0]), +\t // Inputs +\t .clk\t\t\t(clk)); + + // Aggregate outputs into a single result vector + wire [63:0] result = {out2, 16\'h0, out}; + + // Test loop +`ifdef TEST_VERBOSE + always @ (negedge clk) begin + $write(""[%0t] cyc==%0d crc=%x result=%x\ +"",$time, cyc, crc, result); + end +`endif + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write(""[%0t] cyc==%0d crc=%x result=%x\ +"",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin +\t // Setup +\t crc <= 64\'h5aef0c8d_d70a4497; +\t sum <= 64\'h0; +\t test.clear(); + end + else if (cyc<10) begin +\t sum <= 64\'h0; +\t test.clear(); + end + else if (cyc<90) begin + end + else if (cyc==99) begin +\t $write(""[%0t] cyc==%0d crc=%x sum=%x\ +"",$time, cyc, crc, sum); +\t if (crc !== 64\'hc77bb9b3784ea091) $stop; +\t // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64\'hc68a94a34ec970aa +\t if (sum !== `EXPECTED_SUM) $stop; +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, out2, + // Inputs + clk, en, a0, a1, d0, d1 + ); + + input clk; + input [1:0] en; + input [1:0] a0; + input [1:0] a1; + input [7:0] d0; + input [7:0] d1; + output reg [31:0] out; + output reg [15:0] out2; + + // verilator lint_off MULTIDRIVEN + reg [7:0] \t mem [4]; + // verilator lint_on MULTIDRIVEN + + task clear(); + for (int i=0; i<4; ++i) mem[i] = 0; + endtask + + always @(posedge clk) begin + if (en[0]) begin +\t mem[a0] <= d0; +\t out2[7:0] <= d0; + end + end + always @(negedge clk) begin + if (en[1]) begin +\t mem[a1] <= d1; +\t out2[15:8] <= d0; + end + end + + assign out = {mem[3],mem[2],mem[1],mem[0]}; + +endmodule +" +"// DESCRIPTION: Verilator: Test of select from constant +// +// This tests issue 508, bit select of constant fails +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Jeremy Bennett. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // Note that if we declare ""wire [0:0] b"", this works just fine. + wire a; + wire b; + + assign b = 1\'b0; + assign a = b[0]; // IEEE illegal can\'t extract scalar + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +module t (/*AUTOARG*/); + wire ok = 1'b0; + sub sub (.ok(ok), , .nc()); +endmodule + +module sub (input ok, input none, input nc, input missing); + initial if (ok && none && nc && missing) begin end // No unused warning +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test for short-circuiting in generate ""if"" +// +// The given generate loops should only access valid bits of mask, since that +// is defined by SIZE. However since the loop range is larger, this only works +// if short-circuited evaluation of the generate loop is in place. + +// This file ONLY is placed into the Public Domain, for any use, without +// warranty, 2012 by Jeremy Bennett. + + +`define MAX_SIZE 4 + + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + // Set the parameters, so that we use a size less than MAX_SIZE + test_gen + #(.SIZE (2), + .MASK (2\'b11)) + i_test_gen (.clk (clk)); + + // This is only a compilation test, but for good measure we do one clock + // cycle. + integer count; + + initial begin + count = 0; + end + + always @(posedge clk) begin + if (count == 1) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + else begin +\t count = count + 1; + end + end + +endmodule // t + + +module test_gen + + #( parameter + SIZE = `MAX_SIZE, + MASK = `MAX_SIZE\'b0) + + (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // Generate blocks that rely on short-circuiting of the logic to avoid errors. + generate + genvar g; + + for (g = 0; g < `MAX_SIZE; g = g + 1) begin + if ((g < SIZE) && MASK[g]) begin +\t always @(posedge clk) begin +`ifdef TEST_VERBOSE +\t $write (""Logical AND generate if MASK [%1d] = %d\ +"", g, MASK[g]); +`endif +\t if (g >= SIZE) begin +\t\t $stop; +\t end +\t end +\t end + end + endgenerate + + generate + for (g = 0; g < `MAX_SIZE; g = g + 1) begin + if (!((g >= SIZE) || ~MASK[g])) begin +\t always @(posedge clk) begin +`ifdef TEST_VERBOSE +\t $write (""Logical OR generate if MASK [%1d] = %d\ +"", g, MASK[g]); +`endif +\t if (g >= SIZE) begin +\t\t $stop; +\t end +\t end +\t end + end + endgenerate + + generate + for (g = 0; g < `MAX_SIZE; g = g + 1) begin + if (!((g < SIZE) -> ~MASK[g])) begin +\t always @(posedge clk) begin +`ifdef TEST_VERBOSE +\t $write (""Logical infer generate if MASK [%1d] = %d\ +"", g, MASK[g]); +`endif +\t if (g >= SIZE) begin +\t\t $stop; +\t end +\t end +\t end + end + endgenerate + + generate + for (g = 0; g < `MAX_SIZE; g = g + 1) begin + if ( g < SIZE ? MASK[g] : 1\'b0) begin +\t always @(posedge clk) begin +`ifdef TEST_VERBOSE +\t $write (""Conditional generate if MASK [%1d] = %d\ +"", g, MASK[g]); +`endif +\t if (g >= SIZE) begin +\t\t $stop; +\t end +\t end +\t end + end + endgenerate + + // The other way round + generate + for (g = 0; g < `MAX_SIZE; g = g + 1) begin + if ( g >= SIZE ? 1\'b0 : MASK[g]) begin +\t always @(posedge clk) begin +`ifdef TEST_VERBOSE +\t $write (""Conditional generate if MASK [%1d] = %d\ +"", g, MASK[g]); +`endif +\t if (g >= SIZE) begin +\t\t $stop; +\t end +\t end +\t end + end + endgenerate + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +// Very simple test for interface pathclearing + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc=1; + + ifc #(2) itopa(); + ifc #(4) itopb(); + + sub ca (.isub(itopa.out_modport), +\t .clk); + sub cb (.isub(itopb.out_modport), +\t .clk); + + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write(""[%0t] cyc==%0d result=%b %b\ +"",$time, cyc, itopa.valueo, itopb.valueo); +`endif + cyc <= cyc + 1; + itopa.valuei <= cyc[1:0]; + itopb.valuei <= cyc[3:0]; + if (cyc==1) begin +\t if (itopa.WIDTH != 2) $stop; +\t if (itopb.WIDTH != 4) $stop; +\t if ($bits(itopa.valueo) != 2) $stop; +\t if ($bits(itopb.valueo) != 4) $stop; +\t if ($bits(itopa.out_modport.valueo) != 2) $stop; +\t if ($bits(itopb.out_modport.valueo) != 4) $stop; + end + if (cyc==4) begin +\t if (itopa.valueo != 2\'b11) $stop; +\t if (itopb.valueo != 4\'b0011) $stop; + end + if (cyc==5) begin +\t if (itopa.valueo != 2\'b00) $stop; +\t if (itopb.valueo != 4\'b0100) $stop; + end + if (cyc==20) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end +endmodule + +interface ifc + #(parameter WIDTH = 1); + // verilator lint_off MULTIDRIVEN + logic [WIDTH-1:0] valuei; + logic [WIDTH-1:0] valueo; + // verilator lint_on MULTIDRIVEN + modport out_modport (input valuei, output valueo); +endinterface + +// Note not parameterized +module sub + ( + ifc.out_modport isub, + input clk + ); + always @(posedge clk) isub.valueo <= isub.valuei + 1; +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +// bug511 +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + wire [7:0] au; + wire [7:0] as; + + Test1 test1 (.au); + Test2 test2 (.as); + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write(""[%0t] result=%x %x\ +"",$time, au, as); +`endif + if (au != \'h12) $stop; + if (as != \'h02) $stop; + $write(""*-* All Finished *-*\ +""); + $finish; + end + +endmodule + +module Test1 (output [7:0] au); + wire [7:0] \t\tb; + wire signed [3:0] \tc; + + // verilator lint_off WIDTH + assign c=-1; // \'hf + assign b=3; // \'h3 + assign au=b+c; // \'h12 + // verilator lint_on WIDTH +endmodule + + +module Test2 (output [7:0] as); + wire signed [7:0] \tb; + wire signed [3:0] \tc; + + // verilator lint_off WIDTH + assign c=-1; // \'hf + assign b=3; // \'h3 + assign as=b+c; // \'h12 + // verilator lint_on WIDTH +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=0; + reg [63:0] crc; + reg [63:0] sum; + +`ifdef ALLOW_UNOPT + /*verilator lint_off UNOPTFLAT*/ +`endif + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0]\t\tb;\t\t\t// From file of file.v + wire [31:0]\t\tc;\t\t\t// From file of file.v + wire [31:0]\t\td;\t\t\t// From file of file.v + // End of automatics + + file file (/*AUTOINST*/ +\t // Outputs +\t .b\t\t\t(b[31:0]), +\t .c\t\t\t(c[31:0]), +\t .d\t\t\t(d[31:0]), +\t // Inputs +\t .crc\t\t\t(crc[31:0])); + + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write(""[%0t] cyc=%0d crc=%x sum=%x b=%x d=%x\ +"",$time,cyc,crc,sum, b, d); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= {b, d} +\t ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin +\t // Setup +\t crc <= 64\'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin +\t sum <= 64\'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin +\t $write(""*-* All Finished *-*\ +""); +\t $write(""[%0t] cyc==%0d crc=%x %x\ +"",$time, cyc, crc, sum); +\t if (crc !== 64\'hc77bb9b3784ea091) $stop; +\t if (sum !== 64\'h649ee1713d624dd9) $stop; +\t $finish; + end + end + +endmodule + +module file (/*AUTOARG*/ + // Outputs + b, c, d, + // Inputs + crc + ); + + input [31:0] crc; +`ifdef ISOLATE + output reg [31:0] b /* verilator isolate_assignments*/; +`else + output reg [31:0] b; +`endif + + output reg [31:0] c; + output reg [31:0] d; + + always @* begin + // Note that while c and b depend on crc, b doesn\'t depend on c. + casez (crc[3:0]) +\t4\'b??01: begin +\t b = {crc[15:0],get_31_16(crc)}; +\t d = c; +\tend +\t4\'b??00: begin +\t b = {crc[15:0],~crc[31:16]}; +\t d = {crc[15:0],~c[31:16]}; +\tend +\tdefault: begin +\t set_b_d(crc, c); +\tend + endcase + end + + function [31:16] get_31_16\t/* verilator isolate_assignments*/; + input [31:0] t_crc\t/* verilator isolate_assignments*/; + get_31_16 = t_crc[31:16]; + endfunction + + task set_b_d; +`ifdef ISOLATE + input [31:0] t_crc\t/* verilator isolate_assignments*/; + input [31:0] t_c\t\t/* verilator isolate_assignments*/; +`else + input [31:0] t_crc; + input [31:0] t_c; +`endif + begin +\t b = {t_crc[31:16],~t_crc[23:8]}; +\t d = {t_crc[31:16], ~t_c[23:8]}; + end + endtask + + always @* begin + // Any complicated equation we can\'t optimize + casez (crc[3:0]) +\t4\'b00??: begin +\t c = {b[29:0],2\'b11}; +\tend +\t4\'b01??: begin +\t c = {b[30:1],2\'b01}; +\tend +\t4\'b10??: begin +\t c = {b[31:2],2\'b10}; +\tend +\t4\'b11??: begin +\t c = {b[31:2],2\'b00}; +\tend + endcase + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/); + + liblib_a a (); + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +// see bug 474 +package functions; + localparam LP_PACK = 512; + localparam LP_PACK_AND_MOD = 19; + task check_param; + $display(""In %m\ +""); // ""In functions::check_param"" + if (LP_PACK_AND_MOD != 19) $stop; + endtask +endpackage + +module t (); + // synthesis translate off + import functions::*; + // synthesis translate on + localparam LP_PACK_AND_MOD = 20; + initial begin + // verilator lint_off STMTDLY + #10; + // verilator lint_on STMTDLY + if (LP_PACK_AND_MOD != 20) $stop; + check_param(); + $write(""*-* All Finished *-*\ +""); + $finish; + end +endmodule + +\t\t\t\t\t\t" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + q, + // Inputs + clk, d + ); + input clk; + input d; + output wire [1:0] q; + + // This demonstrates how warning disables should be propagated across module boundaries. + + m1 m1 (/*AUTOINST*/ +\t // Outputs +\t .q\t\t\t\t(q[1:0]), +\t // Inputs +\t .clk\t\t\t\t(clk), +\t .d\t\t\t\t(d)); +endmodule + +module m1 + ( + input clk, + input d, + output wire [1:0] q + ); + + m2 m2 (/*AUTOINST*/ +\t // Outputs +\t .q\t\t\t\t(q[1:0]), +\t // Inputs +\t .clk\t\t\t\t(clk), +\t .d\t\t\t\t(d)); +endmodule + +module m2 + ( + input clk, + input d, + // Due to bug the below disable used to be ignored. + // verilator lint_off UNOPT + output reg [1:0] q + // verilator lint_on UNOPT + ); + + always @* begin + q[1] = d; + end + + always @* begin + q[0] = q[1]; + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2007 by Wilson Snyder. + +module t (/*AUTOARG*/); + integer num; + initial begin + num = 0; + +`define EMPTY_TRUE +`ifndef EMPTY_TRUE + `error ""Empty is still true"" +`endif + +`define A +`ifdef A\t$display(""1A""); num = num + 1; + `ifdef C\t$stop; + `elsif A\t$display(""2A""); num = num + 1; + `ifdef C\t$stop; + `elsif B\t$stop; + `else\t\t$display(""3A""); num = num + 1; + `endif + `else\t\t$stop; + `endif + `elsif B\t$stop; + `ifdef A\t$stop; + `elsif A\t$stop; + `else + `endif +`elsif C\t$stop; +`else\t\t$stop; +`endif + if (num == 3) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + else begin +\t $write(""%%Error: Bad count: %d\ +"", num); +\t $stop; + end + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +`begin_keywords ""VAMS-2.3"" + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + task check (integer line, real got, real expec); + real delta; + delta = got-expec; + if (delta > 0.001) begin +\t $display(""Line%d: Got %g Exp %g\ +"", line, got, expec); +\t $stop; + end + endtask + + wreal wr; + assign wr = 1.1; + + sub sub (.*); + + initial begin + check(`__LINE__, sqrt(2.0)\t, 1.414); + check(`__LINE__, pow(2.0,2.0)\t, 4.0); + check(`__LINE__, ln(2.0)\t\t, 0.693147); + check(`__LINE__, log(2.0)\t\t, 0.30103); + check(`__LINE__, floor(2.5)\t, 2.0); + check(`__LINE__, exp(2.0)\t\t, 7.38906); + check(`__LINE__, ceil(2.5)\t, 3.0); + $write(""*-* All Finished *-*\ +""); + $finish; + end +endmodule + +module sub ( +\t input wreal wr +\t ); + initial begin + if (wr != 1.1) $stop; + end +endmodule +" +"// DESCRIPTION: Verilator: Dedupe optimization test. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. + +// Contributed 2012 by Varun Koyyalagunta, Centaur Technology. + +module t(res,d,clk,en); + output res; + input d,en,clk; + wire q0,q1,q2,q3; + + flop_gated_latch f0(q0,d,clk,en); + flop_gated_latch f1(q1,d,clk,en); + flop_gated_flop f2(q2,d,clk,en); + flop_gated_flop f3(q3,d,clk,en); + assign res = (q0 + q1) * (q2 - q3); +endmodule + +module flop_gated_latch(q,d,clk,en); + input d, clk, en; + output q; + wire gated_clock; + clock_gate_latch clock_gate(gated_clock, clk, en); + always @(posedge gated_clock) begin + q <= d; + end +endmodule + +module flop_gated_flop(q,d,clk,en); + input d, clk, en; + output q; + wire gated_clock; + clock_gate_flop clock_gate(gated_clock, clk, en); + always @(posedge gated_clock) begin + q <= d; + end +endmodule + +module clock_gate_latch (gated_clk, clk, clken); + output gated_clk; + input clk, clken; + reg clken_latched /*verilator clock_enable*/; + assign gated_clk = clk & clken_latched ; + + wire clkb = ~clk; + always @(clkb or clken) + if(clkb) clken_latched = clken; + +endmodule + +module clock_gate_flop (gated_clk, clk, clken); + output gated_clk; + input clk, clken; + reg clken_r /*verilator clock_enable*/; + assign gated_clk = clk & clken_r ; + + always @(negedge clk) + clken_r <= clken; + +endmodule +" +"//////////////////////////////////////////////////////////////////////////////// +// // +// This file is placed into the Public Domain, for any use, without warranty. // +// 2012 by Iztok Jeras // +// // +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +// // +// This testbench contains a bus source and a bus drain. The source creates // +// address and data bus values, while the drain is the final destination of // +// such pairs. All source and drain transfers are logged into memories, which // +// are used at the end of simulation to check for data transfer correctness. // +// Inside the RLT wrapper there is a multiplexer and a demultiplexer, they // +// bus transfers into a 8bit data stream and back. Both stream input and // +// output are exposed, they are connected together into a loopback. // +// // +// ----------- --------------------- // +// | bso_mem | | wrap | // +// ----------- | | // +// ----------- | | ----------- | // +// | bsi src | ------------> | -> | mux | -> | -> - sto // +// ----------- | ----------- | \\ // +// | | | loopback // +// ----------- | ----------- | / // +// | bso drn | <------------ | <- | demux | <- | <- - sti // +// ----------- | | ----------- | // +// ----------- | | // +// | bso_mem | | | // +// ----------- --------------------- // +// // +// PROTOCOL: // +// // +// The \'vld\' signal is driven by the source to indicate valid data is // +// available, \'rdy\' is used by the drain to indicate is is ready to accept // +// valid data. A data transfer only happens if both \'vld\' & \'rdy\' are active. // +// // +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns/1ps + +// include RTL files +`include ""t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv"" +`include ""t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv"" +`include ""t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv"" +`include ""t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv"" + +module t (/*AUTOARG*/ + // Inputs + clk + ); + +input clk; + +parameter SIZ = 10; + +// system signals +//logic clk = 1\'b1; // clock +logic rst = 1\'b1; // reset +integer rst_cnt = 0; + +// input bus +logic bsi_vld; // valid (chip select) +logic [31:0] bsi_adr; // address +logic [31:0] bsi_dat; // data +logic bsi_rdy; // ready (acknowledge) +logic bsi_trn; // data transfer +logic [31:0] bsi_mem [SIZ]; +// output stream +logic sto_vld; // valid (chip select) +logic [7:0] sto_bus; // data bus +logic sto_rdy; // ready (acknowledge) + +// input stream +logic sti_vld; // valid (chip select) +logic [7:0] sti_bus; // data bus +logic sti_rdy; // ready (acknowledge) +// output bus +logic bso_vld; // valid (chip select) +logic [31:0] bso_adr; // address +logic [31:0] bso_dat; // data +logic bso_rdy; // ready (acknowledge) +logic bso_trn; // data transfer +logic [31:0] bso_mem [SIZ]; +integer bso_cnt = 0; + +//////////////////////////////////////////////////////////////////////////////// +// clock and reset +//////////////////////////////////////////////////////////////////////////////// + +// clock toggling +//always #5 clk = ~clk; + +// reset is removed after a delay +always @ (posedge clk) +begin + rst_cnt <= rst_cnt + 1; + rst <= rst_cnt <= 3; +end + +// reset is removed after a delay +always @ (posedge clk) +if (bso_cnt == SIZ) begin + if (bsi_mem === bso_mem) begin $write(""*-* All Finished *-*\ +""); $finish(); end + else begin $display (""FAILED""); $stop(); end +end + +//////////////////////////////////////////////////////////////////////////////// +// input data generator +//////////////////////////////////////////////////////////////////////////////// + +// input data transfer +assign bsi_trn = bsi_vld & bsi_rdy; + +// valid (for SIZ transfers) +always @ (posedge clk, posedge rst) +if (rst) bsi_vld = 1\'b0; +else bsi_vld = (bsi_adr < SIZ); + +// address (increments every transfer) +always @ (posedge clk, posedge rst) +if (rst) bsi_adr <= 32\'h00000000; +else if (bsi_trn) bsi_adr <= bsi_adr + \'d1; + +// data (new random value generated after every transfer) +always @ (posedge clk, posedge rst) +if (rst) bsi_dat <= 32\'h00000000; +else if (bsi_trn) bsi_dat <= $random(); + +// storing transferred data into memory for final check +always @ (posedge clk) +if (bsi_trn) bsi_mem [bsi_adr] <= bsi_dat; + +//////////////////////////////////////////////////////////////////////////////// +// RTL instance +//////////////////////////////////////////////////////////////////////////////// + +sv_bus_mux_demux_wrap wrap ( + // system signals + .clk (clk), + .rst (rst), + // input bus + .bsi_vld (bsi_vld), + .bsi_adr (bsi_adr), + .bsi_dat (bsi_dat), + .bsi_rdy (bsi_rdy), + // output stream + .sto_vld (sto_vld), + .sto_bus (sto_bus), + .sto_rdy (sto_rdy), + // input stream + .sti_vld (sti_vld), + .sti_bus (sti_bus), + .sti_rdy (sti_rdy), + // output bus + .bso_vld (bso_vld), + .bso_adr (bso_adr), + .bso_dat (bso_dat), + .bso_rdy (bso_rdy) +); + +// stream output from mux is looped back into stream input for demux +assign sti_vld = sto_vld; +assign sti_bus = sto_bus; +assign sto_rdy = sti_rdy; + +//////////////////////////////////////////////////////////////////////////////// +// output data monitor +//////////////////////////////////////////////////////////////////////////////// + +// input data transfer +assign bso_trn = bso_vld & bso_rdy; + +// output transfer counter used to end the test +always @ (posedge clk, posedge rst) +if (rst) bso_cnt <= 0; +else if (bso_trn) bso_cnt <= bso_cnt + 1; + +// storing transferred data into memory for final check +always @ (posedge clk) +if (bso_trn) bso_mem [bso_adr] <= bso_dat; + +// every output transfer against expected value stored in memory +always @ (posedge clk) +if (bso_trn && (bsi_mem [bso_adr] !== bso_dat)) +$display (""@%08h i:%08h o:%08h"", bso_adr, bsi_mem [bso_adr], bso_dat); + +// ready is active for SIZ transfers +always @ (posedge clk, posedge rst) +if (rst) bso_rdy = 1\'b0; +else bso_rdy = 1\'b1; + +endmodule : sv_bus_mux_demux_tb +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +// Very simple test for interface pathclearing + +interface ifc; + integer hidden_from_isub; + integer value; + modport out_modport (output value); +endinterface + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc=1; + + ifc itop(); + + sub c1 (.isub(itop), +\t .i_value(4)); + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==20) begin +\t if (itop.value != 4) $stop; +\t itop.hidden_from_isub = 20; +\t if (itop.hidden_from_isub != 20) $stop; +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end +endmodule + +module sub +`ifdef NANSI // bug868 + ( + isub, i_value + ); + ifc.out_modport isub; // Note parenthesis are not legal here + input integer i_value; +`else + ( + ifc.out_modport isub, + input integer i_value + ); +`endif + + always @* begin + isub.value = i_value; + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2007 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + x, + // Inputs + clk + ); + +`ifdef ALLOW_UNOPT + /*verilator lint_off UNOPTFLAT*/ +`endif + + input clk; + output x; // Avoid eliminating x + + reg x; + always @* begin + x = ~x; + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + reg [1:0] in; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [1:0]\t\tout10;\t\t\t// From test of Test.v + wire [1:0]\t\tout32;\t\t\t// From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ +\t // Outputs +\t .out32\t\t\t(out32[1:0]), +\t .out10\t\t\t(out10[1:0]), +\t // Inputs +\t .in\t\t\t(in[1:0])); + + // Test loop + always @ (posedge clk) begin + in <= in + 1; +`ifdef TEST_VERBOSE + $write(""[%0t] in=%d out32=%d out10=%d\ +"",$time, in, out32, out10); +`endif + if (in==3) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out32, out10, + // Inputs + in + ); + input [1:0] in; + output [1:0] out32; + output [1:0] out10; + + assign out32 = in[3:2]; + assign out10 = in[1:0]; +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Jeremy Bennett. + +module t (/*AUTOARG*/); + + typedef enum int { +\t\t PADTYPE_DEFAULT = 32\'d0, +\t\t PADTYPE_GPIO, +\t\t PADTYPE_VDD, +\t\t PADTYPE_GND +\t\t } t_padtype; + + localparam int STR_PINID [0:15] +\t\t = \'{ +\t\t ""DEF"", ""ERR"", ""ERR"", ""ERR"", ""ERR"", ""ERR"", ""ERR"", ""ERR"", +\t\t ""PA0"", ""PA1"", ""PA2"", ""PA3"", ""PA4"", ""PA5"", ""PA6"", ""PA7"" +\t\t }; + + typedef struct packed { + t_padtype padtype; + int \t aux; + } t_pin_descriptor; + + localparam t_pin_descriptor + PINOUT[ 1: 6] + = \'{ +\t \'{default:0, padtype:PADTYPE_GPIO, aux:1}, +\t \'{default:0, padtype:PADTYPE_GPIO}, +\t \'{default:0, padtype:PADTYPE_GPIO}, +\t \'{default:0, padtype:PADTYPE_GPIO}, +\t \'{default:0, padtype:PADTYPE_VDD}, +\t \'{default:0, padtype:PADTYPE_GND} +\t }; + + localparam int PINOUT_SIZE = 6; + localparam int PINOUT_WA[1:PINOUT_SIZE][3] +\t\t = \'{ +\t\t \'{0, PADTYPE_GPIO, 0}, +\t\t \'{1, PADTYPE_GPIO, 0}, +\t\t \'{2, PADTYPE_GPIO, 0}, +\t\t \'{5, PADTYPE_GPIO, 0}, +\t\t \'{6, PADTYPE_VDD, 0}, +\t\t \'{8, PADTYPE_GND , 0} +\t\t }; + + const int pinout_static_const[1:PINOUT_SIZE][3] +\t\t = \'{ +\t\t \'{0, PADTYPE_GPIO, 0}, +\t\t \'{1, PADTYPE_GPIO, 0}, +\t\t \'{2, PADTYPE_GPIO, 0}, +\t\t \'{5, PADTYPE_GPIO, 0}, +\t\t \'{6, PADTYPE_VDD, 0}, +\t\t \'{8, PADTYPE_GND , 0} +\t\t }; + + // Make sure consants propagate + checkstr #(.PINID(STR_PINID[1]), +\t .EXP(""ERR"")) + substr1 (); + checkstr #(.PINID(STR_PINID[8]), +\t .EXP(""PA0"")) + substr8 (); + + initial begin + $display(""PINID1 %s"", STR_PINID[1]); + $display(""PINID8 %s"", STR_PINID[8]); + if (STR_PINID[1] != ""ERR"") $stop; + if (STR_PINID[8] != ""PA0"") $stop; + if (pinout_static_const[1][0] != 0) $stop; + $write(""*-* All Finished *-*\ +""); + $finish; + end + +endmodule + +module checkstr; + parameter int PINID = "" ""; + parameter int EXP = "" ""; + initial begin + $display(""PID %s EXP %s"", PINID, EXP); + if (EXP != ""ERR"" && EXP != ""PA0"") $stop; + if (PINID != EXP) $stop; + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. +// See bug408 + +module top + ( + output logic [1:0] q, + input logic [1:0] d, + input logic \t clk + ); + + genvar \t i; + assign \t q[i] = d[i]; +endmodule + +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t; + reg [40:0] quad; initial quad = 41\'ha_bbbb_cccc; + reg [80:0] wide; initial wide = 81\'habc_1234_5678_1234_5678; + reg [31:0] str; initial str = ""\\000\\277\\021\ +""; + reg [47:0] str2; initial str2 = ""\\000what!""; + reg [79:0] str3; initial str3 = ""\\000hmmm!1234""; + reg [8:0] nine; + + sub sub (); + sub2 sub2 (); + + initial begin + $write(""[%0t] In %m: Hi\ +"", $time); + sub.write_m; + sub2.write_m; + + // Escapes + $display(""[%0t] Back \\\\ Quote \\"""", $time); // Old bug when \\"" last on the line. + + // Display formatting + nine = {3\'d0,quad[5:0]}; + $display(""[%0t] %%X=%X %%0X=%0X %%0O=%0O %%B=%B"", $time, +\t nine, nine, nine, nine); + $display(""[%0t] %%x=%x %%0x=%0x %%0o=%0o %%b=%b"", $time, +\t nine, nine, nine, nine); + $display(""[%0t] %%D=%D %%d=%d %%01d=%01d %%06d=%06d %%6d=%6d"", $time, +\t nine, nine, nine, nine, nine); + $display(""[%0t] %%x=%x %%0x=%0x %%o=%o %%b=%b"", $time, +\t quad, quad, quad, quad); + $display(""[%0t] %%x=%x %%0x=%0x %%o=%o %%b=%b"", $time, +\t wide, wide, wide, wide); + $display(""[%0t] %%t=%t %%03t=%03t %%0t=%0t"", $time, +\t $time, $time, $time); + $display; + // Not testing %0s, it does different things in different simulators + $display(""[%0t] %%s=%s %%s=%s %%s=%s"", $time, +\t str2[7:0], str2, str3); + + $display(""[%0t] %s%s%s"", $time, +\t ""hel"", ""lo, fr"", ""om a very long string. Percent %s are literally substituted in.""); + $write(""[%0t] Embedded \\r return\ +"", $time); + $display(""[%0t] Embedded\\ +multiline"", $time); + + // Str check +`ifndef NC\t// NC-Verilog 5.3 chokes on this test + if (str !== 32\'h00_bf_11_0a) $stop; +`endif + $write(""*-* All Finished *-*\ +""); + $finish; + end +endmodule + +module sub; + task write_m; + begin +\t $write(""[%0t] In %m\ +"", $time); +\t begin : subblock +\t $write(""[%0t] In %M\ +"", $time); // Uppercase %M test +\t end + end + endtask +endmodule + +module sub2; + // verilator no_inline_module + task write_m; + begin +\t $write(""[%0t] In %m\ +"", $time); +\t begin : subblock2 +\t $write(""[%0t] In %m\ +"", $time); +\t end + end + endtask +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + priority_mask, + // Inputs + muxed_requests + ); + + parameter ARW = 7; + + // verilator lint_off UNOPTFLAT + integer i,j; + + output reg [ARW-1:0] priority_mask; + + input [ARW-1:0] muxed_requests; + + always @* begin + for (i=ARW-1;i>0;i=i-1) begin +\t priority_mask[i]=1'b0; +\t // vvvv=== note j=j not j=i; was bug +\t for( j=j;j>=0;j=j-1) +\t priority_mask[i]=priority_mask[j] | muxed_requests[j]; + end + //Bit zero is always enabled + priority_mask[0]=1'b0; + end + +endmodule + +// Local Variables: +// verilog-auto-inst-param-value: t +// End: +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module x; + + typedef struct { + int \t a; + } notpacked_t; + + typedef struct packed { + notpacked_t b; + } ispacked_t; + + ispacked_t p; + + initial begin + p.b = 1; + if (p.b != 1) $stop; + $write(""*-* All Finished *-*\ +""); + $finish; + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (clk); + input clk; + + reg [0:0] d1; + reg [2:0] d3; + reg [7:0] d8; + + wire [0:0] q1; + wire [2:0] q3; + wire [7:0] q8; + + // verilator lint_off UNOPTFLAT + reg \t ena; + // verilator lint_on UNOPTFLAT + + condff #(12) condff + (.clk(clk), .sen(1\'b0), .ena(ena), + .d({d8,d3,d1}), + .q({q8,q3,q1})); + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin +\t //$write(""%x %x %x %x\ +"", cyc, q8, q3, q1); +\t cyc <= cyc + 1; +\t if (cyc==1) begin +\t d1 <= 1\'b1; d3<=3\'h1; d8<=8\'h11; +\t ena <= 1\'b1; +\t end +\t if (cyc==2) begin +\t d1 <= 1\'b0; d3<=3\'h2; d8<=8\'h33; +\t ena <= 1\'b0; +\t end +\t if (cyc==3) begin +\t d1 <= 1\'b1; d3<=3\'h3; d8<=8\'h44; +\t ena <= 1\'b1; +\t if (q8 != 8\'h11) $stop; +\t end +\t if (cyc==4) begin +\t d1 <= 1\'b1; d3<=3\'h4; d8<=8\'h77; +\t ena <= 1\'b1; +\t if (q8 != 8\'h11) $stop; +\t end +\t if (cyc==5) begin +\t d1 <= 1\'b1; d3<=3\'h0; d8<=8\'h88; +\t ena <= 1\'b1; +\t if (q8 != 8\'h44) $stop; +\t end +\t if (cyc==6) begin +\t if (q8 != 8\'h77) $stop; +\t end +\t if (cyc==7) begin +\t if (q8 != 8\'h88) $stop; +\t end +\t // +\t if (cyc==20) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; +\t end + end + end +endmodule + +module condff (clk, sen, ena, d, q); + parameter WIDTH = 1; + input clk; + + input sen; + input ena; + input [WIDTH-1:0] d; + output [WIDTH-1:0] q; + + condffimp #(.WIDTH(WIDTH)) + imp (.clk(clk), .sen(sen), .ena(ena), .d(d), .q(q)); +endmodule + +module condffimp (clk, sen, ena, d, q); + parameter WIDTH = 1; + input clk; + input sen; + input ena; + input [WIDTH-1:0] d; + output reg [WIDTH-1:0] q; + wire gatedclk; + + clockgate clockgate (.clk(clk), .sen(sen), .ena(ena), .gatedclk(gatedclk)); + + always @(posedge gatedclk) begin + if (gatedclk === 1\'bX) begin +\t q <= {WIDTH{1\'bX}}; + end + else begin +\t q <= d; + end + end + +endmodule + +module clockgate (clk, sen, ena, gatedclk); + input\tclk; + input\tsen; + input\tena; + output\tgatedclk; + + reg\t\tena_b; + wire gatedclk = clk & ena_b; + + // verilator lint_off COMBDLY + always @(clk or ena or sen) begin + if (~clk) begin + ena_b <= ena | sen; + end + else begin +\t if ((clk^sen)===1\'bX) ena_b <= 1\'bX; + end + end + // verilator lint_on COMBDLY + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // verilator lint_off LITENDIAN + // verilator lint_off BLKANDNBLK + // 3 3 4 + reg [71:0] memw [2:0][1:3][5:2]; + reg [7:0] memn [2:0][1:3][5:2]; + // verilator lint_on BLKANDNBLK + + integer cyc; initial cyc=0; + reg [63:0] crc; + reg [71:0] wide; + reg [7:0] narrow; + reg [1:0] index0; + reg [1:0] index1; + reg [2:0] index2; + integer i0,i1,i2; + + integer imem[2:0][1:3]; + reg [2:0] cstyle[2]; + // verilator lint_on LITENDIAN + + initial begin + for (i0=0; i0<3; i0=i0+1) begin +\t for (i1=1; i1<4; i1=i1+1) begin +\t imem[i0[1:0]] [i1[1:0]] = i1; +\t for (i2=2; i2<6; i2=i2+1) begin +\t memw[i0[1:0]] [i1[1:0]] [i2[2:0]] = {56\'hfe_fee0_fee0_fee0_,4\'b0,i0[3:0],i1[3:0],i2[3:0]}; +\t memn[i0[1:0]] [i1[1:0]] [i2[2:0]] = 8\'b1000_0001; +\t end +\t end + end + end + + reg [71:0] wread; + reg\t wreadb; + + always @ (posedge clk) begin + //$write(""cyc==%0d crc=%x i[%d][%d][%d] nar=%x wide=%x\ +"",cyc, crc, index0,index1,index2, narrow, wide); + cyc <= cyc + 1; + if (cyc==0) begin +\t // Setup +\t crc <= 64\'h5aef0c8d_d70a4497; +\t narrow <= 8\'h0; +\t wide <= 72\'h0; +\t index0 <= 2\'b0; +\t index1 <= 2\'b0; +\t index2 <= 3\'b0; + end + else if (cyc<90) begin +\t index0 <= crc[1:0]; +\t index1 <= crc[3:2]; +\t index2 <= crc[6:4]; +\t crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + +\t // We never read past bounds, or get unspecific results +\t // We also never read lowest indexes, as writing outside of range may corrupt them +\t if (index0>=0+1 && index0<=2 && index1>=1+1 /*&& index1<=3 CMPCONST*/ && index2>=2+1 && index2<=5) begin +\t narrow <= ({narrow[6:0], narrow[7]^narrow[0]} +\t\t ^ {memn[index0][index1][index2]}); +\t wread = memw[index0][index1][index2]; +\t wreadb = memw[index0][index1][index2][2]; +\t wide <= ({wide[70:0], wide[71]^wide[2]^wide[0]} ^ wread); +\t //$write(""Get memw[%d][%d][%d] -> %x\ +"",index0,index1,index2, wread); +\t end +\t // We may write past bounds of memory +\t memn[index0][index1][index2] [crc[10:8]+:3] <= crc[2:0]; +\t memn[index0][index1][index2] <= {~crc[6:0],crc[7]}; +\t memw[index0][index1][index2] <= {~crc[7:0],crc}; +\t //$write(""Set memw[%d][%d][%d] <= %x\ +"",index0,index1,index2, {~crc[7:0],crc}); +\t cstyle[cyc[0]] <= cyc[2:0]; +\t if (cyc>20) if (cstyle[~cyc[0]] != (cyc[2:0]-3\'b1)) $stop; + end + else if (cyc==90) begin +\t memn[0][1][3] <= memn[0][1][3] ^ 8\'ha8; + end + else if (cyc==91) begin + end + else if (cyc==99) begin +\t $write(""[%0t] cyc==%0d crc=%x nar=%x wide=%x\ +"",$time, cyc, crc, narrow, wide); +\t if (crc != 64\'h65e3bddcd9bc2750) $stop; +\t if (narrow != 8\'hca) $stop; +\t if (wide != 72\'h4edafed31ba6873f73) $stop; +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003-2007 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + integer \tcyc=0; + + reg \t\tcheck; + initial check = 1\'b0; + Genit g (.clk(clk), .check(check)); + + always @ (posedge clk) begin + //$write(""[%0t] cyc==%0d %x %x\ +"",$time, cyc, check, out); + cyc <= cyc + 1; + if (cyc==0) begin +\t // Setup +\t check <= 1\'b0; + end + else if (cyc==1) begin +\t check <= 1\'b1; + end + else if (cyc==9) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end + +//`define WAVES +`ifdef WAVES + initial begin + $dumpfile(""obj_dir/t_gen_intdot2/t_gen_intdot.vcd""); + $dumpvars(12, t); + end +`endif + +endmodule + +module One; + wire one = 1\'b1; +endmodule + +module Genit ( + input clk, + input check); + + // ARRAY + One cellarray1[1:0] ();\t//cellarray[0..1][0..1] + always @ (posedge clk) if (cellarray1[0].one !== 1\'b1) $stop; + always @ (posedge clk) if (cellarray1[1].one !== 1\'b1) $stop; + + // IF + generate + // genblk1 refers to the if\'s name, not the ""generate"" itself. + if (1\'b1) // IMPLIED begin: genblk1 +\tOne ifcell1(); // genblk1.ifcell1 + else +\tOne ifcell1(); // genblk1.ifcell1 + endgenerate + // On compliant simulators ""Implicit name"" not allowed here; IE we can\'t use ""genblk1"" etc +`ifdef verilator + always @ (posedge clk) if (genblk1.ifcell1.one !== 1\'b1) $stop; +//`else // NOT SUPPORTED accoring to spec - generic block references +`endif + + generate + begin : namedif2 +\t if (1\'b1) +\t One ifcell2(); // namedif2.genblk1.ifcell2 + end + endgenerate +`ifdef verilator + always @ (posedge clk) if (namedif2.genblk1.ifcell2.one !== 1\'b1) $stop; +//`else // NOT SUPPORTED accoring to spec - generic block references +`endif + + generate + if (1\'b1) +\tbegin : namedif3 +\t One ifcell3(); // namedif3.ifcell3 +\tend + endgenerate + always @ (posedge clk) if (namedif3.ifcell3.one !== 1\'b1) $stop; + + // CASE + generate + case (1\'b1) +\t1\'b1 : +\t One casecell10();\t// genblk3.casecell10 + endcase + endgenerate +`ifdef verilator + always @ (posedge clk) if (genblk3.casecell10.one !== 1\'b1) $stop; +//`else // NOT SUPPORTED accoring to spec - generic block references +`endif + + generate + case (1\'b1) +\t1\'b1 : begin : namedcase11 +\t One casecell11(); +\tend + endcase + endgenerate + always @ (posedge clk) if (namedcase11.casecell11.one !== 1\'b1) $stop; + + genvar i; + genvar j; + + // IF + generate + for (i = 0; i < 2; i = i + 1) +\tOne cellfor20 ();\t// genblk4[0..1].cellfor20 + endgenerate +`ifdef verilator + always @ (posedge clk) if (genblk4[0].cellfor20.one !== 1\'b1) $stop; + always @ (posedge clk) if (genblk4[1].cellfor20.one !== 1\'b1) $stop; +//`else // NOT SUPPORTED accoring to spec - generic block references +`endif + + // COMBO + generate + for (i = 0; i < 2; i = i + 1) +\tbegin : namedfor21 +\t One cellfor21 ();\t// namedfor21[0..1].cellfor21 +\tend + endgenerate + always @ (posedge clk) if (namedfor21[0].cellfor21.one !== 1\'b1) $stop; + always @ (posedge clk) if (namedfor21[1].cellfor21.one !== 1\'b1) $stop; + + generate + for (i = 0; i < 2; i = i + 1) +\tbegin : namedfor30 +\t for (j = 0; j < 2; j = j + 1) +\t begin : forb30 +\t\tif (j == 0) +\t\t begin : forif30 +\t\t One cellfor30a (); // namedfor30[0..1].forb30[0].forif30.cellfor30a +\t\t end +\t\telse +`ifdef verilator +\t\t begin : forif30b +`else +\t\t begin : forif30 // forif30 seems to work on some simulators, not verilator yet +`endif +\t\t One cellfor30b (); // namedfor30[0..1].forb30[1].forif30.cellfor30b +\t\t end +\t end +\tend + endgenerate + always @ (posedge clk) if (namedfor30[0].forb30[0].forif30.cellfor30a.one !== 1\'b1) $stop; + always @ (posedge clk) if (namedfor30[1].forb30[0].forif30.cellfor30a.one !== 1\'b1) $stop; +`ifdef verilator + always @ (posedge clk) if (namedfor30[0].forb30[1].forif30b.cellfor30b.one !== 1\'b1) $stop; + always @ (posedge clk) if (namedfor30[1].forb30[1].forif30b.cellfor30b.one !== 1\'b1) $stop; +`else + always @ (posedge clk) if (namedfor30[0].forb30[1].forif30.cellfor30b.one !== 1\'b1) $stop; + always @ (posedge clk) if (namedfor30[1].forb30[1].forif30.cellfor30b.one !== 1\'b1) $stop; +`endif + +endmodule +" +"// DESCRIPTION: Verilator: Test of select from constant +// +// This tests issue 509, bit select of constant fails +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Jeremy Bennett. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // a and b are arrays of length 1. + wire a[0:0]; // Array of nets + wire b[0:0]; + + assign a = 1'b0; // Only net assignment allowed + assign b = a[0]; // Only net assignment allowed + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module + +module t; + initial begin + // verilator lint_off FUTURE1 + $write(""*-* All Finished *-*\ +""); + $finish; + // verilator FUTURE2 + // verilator FUTURE2 blah blah + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk, fastclk + ); + + input clk /*verilator sc_clock*/; + input fastclk /*verilator sc_clock*/; + reg \t reset_l; + + int cyc; + initial reset_l = 0; + always @ (posedge clk) begin + if (cyc==0) reset_l <= 1\'b1; + else if (cyc==1) reset_l <= 1\'b0; + else if (cyc==10) reset_l <= 1\'b1; + end + + t_clk t (/*AUTOINST*/ +\t // Inputs +\t .clk\t\t\t(clk), +\t .fastclk\t\t\t(fastclk), +\t .reset_l\t\t\t(reset_l)); +endmodule + +module t_clk (/*AUTOARG*/ + // Inputs + clk, fastclk, reset_l + ); + + input clk /*verilator sc_clock*/; + input fastclk /*verilator sc_clock*/; + input reset_l; + + // surefire lint_off STMINI + // surefire lint_off CWECSB + // surefire lint_off NBAJAM + reg \t _ranit; initial _ranit=0; + // surefire lint_off UDDSMX + reg [7:0] clk_clocks; initial clk_clocks = 0; // surefire lint_off_line WRTWRT + wire [7:0] clk_clocks_d1r; + wire [7:0] clk_clocks_d1sr; + wire [7:0] clk_clocks_cp2_d1r; + wire [7:0] clk_clocks_cp2_d1sr; + // verilator lint_off MULTIDRIVEN + reg [7:0] int_clocks; initial int_clocks = 0; + // verilator lint_on MULTIDRIVEN + reg [7:0] int_clocks_copy; + + // verilator lint_off GENCLK + reg \t internal_clk; initial internal_clk = 0; + reg \t reset_int_; + // verilator lint_on GENCLK + + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write(""[%0t] CLK1 %x\ +"", $time, reset_l); +`endif + if (!reset_l) begin +\t clk_clocks <= 0; +\t int_clocks <= 0; +\t internal_clk <= 1\'b1; +\t reset_int_ <= 0; + end + else begin +\t internal_clk <= ~internal_clk; +\t if (!_ranit) begin +\t _ranit <= 1; +`ifdef TEST_VERBOSE +\t $write(""[%0t] t_clk: Running\ +"",$time); +`endif +\t reset_int_ <= 1; +\t end + end + end + + reg [7:0] sig_rst; + always @ (posedge clk or negedge reset_l) begin +`ifdef TEST_VERBOSE + $write(""[%0t] CLK2 %x sr=%x\ +"", $time, reset_l, sig_rst); +`endif + if (!reset_l) begin +\t sig_rst <= 0; + end + else begin +\t sig_rst <= sig_rst + 1; // surefire lint_off_line ASWIBB + end + end + + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write(""[%0t] CLK3 %x cc=%x sr=%x\ +"", $time, reset_l, clk_clocks, sig_rst); +`endif + if (!reset_l) begin +\t clk_clocks <= 0; + end + else begin +\t clk_clocks <= clk_clocks + 8\'d1; +\t if (clk_clocks == 4) begin +\t if (sig_rst !== 4) $stop; +\t if (clk_clocks_d1r !== 3) $stop; +\t if (int_clocks !== 2) $stop; +\t if (int_clocks_copy !== 2) $stop; +\t if (clk_clocks_d1r !== clk_clocks_cp2_d1r) $stop; +\t if (clk_clocks_d1sr !== clk_clocks_cp2_d1sr) $stop; +\t $write(""*-* All Finished *-*\ +""); +\t $finish; +\t end + end + end + + reg [7:0] resetted; + always @ (posedge clk or negedge reset_int_) begin +`ifdef TEST_VERBOSE + $write(""[%0t] CLK4 %x\ +"", $time, reset_l); +`endif + if (!reset_int_) begin +\t resetted <= 0; + end + else begin +\t resetted <= resetted + 8\'d1; + end + end + + always @ (int_clocks) begin + int_clocks_copy = int_clocks; + end + + always @ (negedge internal_clk) begin + int_clocks <= int_clocks + 8\'d1; + end + + t_clk_flop flopa (.clk(clk), .clk2(fastclk), .a(clk_clocks), +\t\t .q(clk_clocks_d1r), .q2(clk_clocks_d1sr)); + t_clk_flop flopb (.clk(clk), .clk2(fastclk), .a(clk_clocks), +\t\t .q(clk_clocks_cp2_d1r), .q2(clk_clocks_cp2_d1sr)); + t_clk_two two (/*AUTOINST*/ +\t\t // Inputs +\t\t .fastclk\t\t(fastclk), +\t\t .reset_l\t\t(reset_l)); + +endmodule + +module t_clk_flop (/*AUTOARG*/ + // Outputs + q, q2, + // Inputs + clk, clk2, a + ); + parameter WIDTH=8; + input clk; + input clk2; + input [(WIDTH-1):0] a; + output [(WIDTH-1):0] q; + output [(WIDTH-1):0] q2; + reg [(WIDTH-1):0] q; + reg [(WIDTH-1):0] q2; + always @ (posedge clk) q<=a; + always @ (posedge clk2) q2<=a; +endmodule + +module t_clk_two (/*AUTOARG*/ + // Inputs + fastclk, reset_l + ); + input fastclk; + input reset_l; + // verilator lint_off GENCLK + reg clk2; + // verilator lint_on GENCLK + reg [31:0] count; + + t_clk_twob tb (.*); + + wire reset_h = ~reset_l; + always @ (posedge fastclk) begin + if (reset_h) clk2 <= 0; + else clk2 <= ~clk2; + end + always @ (posedge clk2) begin + if (reset_h) count <= 0; + else count <= count + 1; + end +endmodule + +module t_clk_twob (/*AUTOARG*/ + // Inputs + fastclk, reset_l + ); + input fastclk; + input reset_l; + + always @ (posedge fastclk) begin + // Extra line coverage point, just to make sure coverage + // hierarchy under inlining lands properly + if (reset_l) ; + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2004 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + ign, + // Inputs + clk + ); + + input clk; + output [31:0] ign; + + reg [31:0] \t\tright; + reg [31:0] \t\tleft; + reg [63:0] \t\tqright; + reg [63:0] \t\tqleft; + reg [31:0] \t\tamt; + + assign ign = {31\'h0, clk} >>> 4\'bx; // bug760 + + always @* begin + right = 32\'h819b018a >> amt; + left = 32\'h819b018a << amt; + qright = 64\'hf784bf8f_12734089 >> amt; + qleft = 64\'hf784bf8f_12734089 >> amt; + end + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin +\t cyc <= cyc + 1; +`ifdef TEST_VERBOSE +\t $write(""%d %x %x %x %x\ +"", cyc, left, right, qleft, qright); +`endif +\t if (cyc==1) begin +\t amt <= 32\'d0; +\t if (5\'b10110>>2 != 5\'b00101) $stop; +\t if (5\'b10110>>>2 != 5\'b00101) $stop; // Note it cares about sign-ness +\t if (5\'b10110<<2 != 5\'b11000) $stop; +\t if (5\'b10110<<<2 != 5\'b11000) $stop; +\t if (5\'sb10110>>2 != 5\'sb00101) $stop; +\t if (5\'sb10110>>>2 != 5\'sb11101) $stop; +\t if (5\'sb10110<<2 != 5\'sb11000) $stop; +\t if (5\'sb10110<<<2 != 5\'sb11000) $stop; +\t // Allow >64 bit shifts if the shift amount is a constant +\t if ((64\'sh458c2de282e30f8b >> 68\'sh4) !== 64\'sh0458c2de282e30f8) $stop; +\t end +\t if (cyc==2) begin +\t amt <= 32\'d28; +\t if (left != 32\'h819b018a) $stop; +\t if (right != 32\'h819b018a) $stop; +\t if (qleft != 64\'hf784bf8f_12734089) $stop; +\t if (qright != 64\'hf784bf8f_12734089) $stop; +\t end +\t if (cyc==3) begin +\t amt <= 32\'d31; +\t if (left != 32\'ha0000000) $stop; +\t if (right != 32\'h8) $stop; +\t if (qleft != 64\'h0000000f784bf8f1) $stop; +\t if (qright != 64\'h0000000f784bf8f1) $stop; +\t end +\t if (cyc==4) begin +\t amt <= 32\'d32; +\t if (left != 32\'h0) $stop; +\t if (right != 32\'h1) $stop; +\t if (qleft != 64\'h00000001ef097f1e) $stop; +\t if (qright != 64\'h00000001ef097f1e) $stop; +\t end +\t if (cyc==5) begin +\t amt <= 32\'d33; +\t if (left != 32\'h0) $stop; +\t if (right != 32\'h0) $stop; +\t if (qleft != 64\'h00000000f784bf8f) $stop; +\t if (qright != 64\'h00000000f784bf8f) $stop; +\t end +\t if (cyc==6) begin +\t amt <= 32\'d64; +\t if (left != 32\'h0) $stop; +\t if (right != 32\'h0) $stop; +\t if (qleft != 64\'h000000007bc25fc7) $stop; +\t if (qright != 64\'h000000007bc25fc7) $stop; +\t end +\t if (cyc==7) begin +\t amt <= 32\'d128; +\t if (left != 32\'h0) $stop; +\t if (right != 32\'h0) $stop; +\t if (qleft != 64\'h0) $stop; +\t if (qright != 64\'h0) $stop; +\t end +\t if (cyc==8) begin +\t if (left != 32\'h0) $stop; +\t if (right != 32\'h0) $stop; +\t if (qleft != 64\'h0) $stop; +\t if (qright != 64\'h0) $stop; +\t end +\t if (cyc==9) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; +\t end + end + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +//bug485, but see t_gen_forif.v for an OK example. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + always_comb begin + integer i; + + for(i=0; i<10; i++ ) begin: COMB + end + + for(i=0; i<9; i++ ) begin: COMB + end + end +endmodule +" +"// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013. + +module t + ( + input logic \t\t\t\tclk, + input logic \t\t\t\tdaten, + input logic [8:0] \t\t\tdatval, + output logic signed [3:0][3:0][35:0] datao + ); + + logic signed [3:0][3:0][3:0][8:0] \tdatat; + + genvar \t\t\t\ti; + generate + for (i=0; i<4; i++)begin +\t testio dut(.clk(clk), .arr3d_in(datat[i]), .arr2d_out(datao[i])); + end + endgenerate + + genvar j; + generate + for (i=0; i<4; i++) begin +\t for (j=0; j<4; j++) begin +\t always_comb datat[i][j][0] = daten ? 9'h0 : datval; +\t always_comb datat[i][j][1] = daten ? 9'h1 : datval; +\t always_comb datat[i][j][2] = daten ? 9'h2 : datval; +\t always_comb datat[i][j][3] = daten ? 9'h3 : datval; +\t end + end + endgenerate +endmodule + +module testio + ( + input \t\t\t\tclk, + input logic signed [3:0] [3:0] [8:0] arr3d_in, + output logic signed [3:0] [35:0] \tarr2d_out + ); + logic signed [3:0] [35:0] \t\tar2d_out_pre; + + always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]}; + always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]}; + always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]}; + always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]}; + + always_ff @(posedge clk) begin + if (clk) +\tarr2d_out <= ar2d_out_pre; + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2010 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Outputs + data_out, + // Inputs + wr, wa, rst_l, rd, ra, data_in, clk + ); + input clk; + + /*AUTOINPUT*/ + // Beginning of automatic inputs (from unused autoinst inputs) + input [31:0]\t\tdata_in;\t\t// To sub of reg_1r1w.v + input [7:0]\t\tra;\t\t\t// To sub of reg_1r1w.v + input\t\trd;\t\t\t// To sub of reg_1r1w.v + input\t\trst_l;\t\t\t// To sub of reg_1r1w.v + input [7:0]\t\twa;\t\t\t// To sub of reg_1r1w.v + input\t\twr;\t\t\t// To sub of reg_1r1w.v + // End of automatics + /*AUTOOUTPUT*/ + // Beginning of automatic outputs (from unused autoinst outputs) + output [31:0]\tdata_out;\t\t// From sub of reg_1r1w.v + // End of automatics + + reg_1r1w #(.WIDTH(32), .DEPTH(256), .ADRWID(8)) + sub + (/*AUTOINST*/ + // Outputs + .data_out\t\t\t\t(data_out[31:0]), + // Inputs + .data_in\t\t\t\t(data_in[31:0]), + .ra\t\t\t\t(ra[7:0]), + .wa\t\t\t\t(wa[7:0]), + .wr\t\t\t\t(wr), + .rd\t\t\t\t(rd), + .clk\t\t\t\t(clk), + .rst_l\t\t\t\t(rst_l)); + +endmodule + +module reg_1r1w + #( + parameter WIDTH=32, + parameter ADRWID=10, + parameter DEPTH=1024, + parameter RST=0 + ) + (/*AUTOARG*/ + // Outputs + data_out, + // Inputs + data_in, ra, wa, wr, rd, clk, rst_l + ); + + input [WIDTH-1:0] data_in; + input [ADRWID-1:0] ra; + input [ADRWID-1:0] wa; + input wr; + input rd; + input clk; + input rst_l; + + output [WIDTH-1:0] data_out; + + reg [WIDTH-1:0] array [DEPTH-1:0]; + reg [ADRWID-1:0] ra_r, wa_r; + reg [WIDTH-1:0] data_in_r; + reg wr_r; + reg rd_r; + + integer x; + + // Message 679 + always @(posedge clk) begin + int tmp = x + 1; + if (tmp !== x + 1) $stop; + end + + always @(posedge clk or negedge rst_l) begin + if (!rst_l) begin +\t for (x=0; x1) break; + end + while (1) begin +\t out = out+1; +\t if (a>1) return 2+out; + end + f_return = 0; + endfunction +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Wilson Snyder. + +module t; + function integer bottom_4bits; + input [7:0] i; + bottom_4bits = 0; + bottom_4bits[3:0] = i[3:0]; + endfunction + + function integer bottom_2_unknown; + input [7:0] i; + // bottom_4bits = 0; \'x + bottom_2_unknown[1:0] = i[1:0]; + endfunction + + localparam p = bottom_4bits(8\'h13); + localparam bu = bottom_2_unknown(8\'h13); + + initial begin + if (p != 3) $stop; + $write(""*-* All Finished *-*\ +""); + $finish; + end +endmodule +" +"// DESCRIPTION: Verilator: Simple test of unoptflat +// +// Simple demonstration of an UNOPTFLAT combinatorial loop, using just 2 bits. +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Jeremy Bennett. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + wire [1:0] x = { x[0], clk }; + + initial begin + x = 0; + end + + always @(posedge clk or negedge clk) begin + +`ifdef TEST_VERBOSE + $write(""x = %x\ +"", x); +`endif + + if (x[1] != 0) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; + end + end + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +module t (); + + // See also t_lint_width + + parameter A_ONE = \'1; + // verilator lint_off WIDTH + parameter [3:0] A_W4 = A_ONE; + // verilator lint_on WIDTH + initial begin + if ($bits(A_ONE) != 1 || A_ONE !== 1\'b1) $stop; + if ($bits(A_W4) != 4) $stop; + if (A_W4 != 4\'b0001) $stop; + end + + b #(.B_WIDTH(48)) b (); + + reg [4:0] c; + integer c_i; + initial begin + c_i = 3; + c = 1\'b1 << c_i; // No width warning when not embedded in expression, as is common syntax + if (c != 5\'b1000) $stop; + end + + localparam D_TT = 32\'d23; + localparam D_SIX = 6; + // verilator lint_off WIDTH + localparam [5:0] D_SUB = D_TT - D_SIX; + // verilator lint_on WIDTH + initial begin + if (D_SUB != 17) $stop; + end + + initial begin + $write(""*-* All Finished *-*\ +""); + $finish; + end + +endmodule + + +module b; + parameter B_WIDTH = 1; + localparam B_VALUE0 = {B_WIDTH{1\'b0}}; + localparam B_VALUE1 = {B_WIDTH{1\'b1}}; + reg [47:0] b_val; + initial begin + b_val = B_VALUE0; + if (b_val != 48\'b0) $stop; + b_val = B_VALUE1; + if (b_val != ~48\'b0) $stop; + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test for short-circuiting in generate ""if"" +// that should not work. +// +// The given generate loops should attempt to access invalid bits of mask and +// trigger errors. +// is defined by SIZE. However since the loop range is larger, this only works +// if short-circuited evaluation of the generate loop is in place. + +// This file ONLY is placed into the Public Domain, for any use, without +// warranty, 2012 by Jeremy Bennett. + + +`define MAX_SIZE 3 + + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + // Set the parameters, so that we use a size less than MAX_SIZE + test_gen + #(.SIZE (2), + .MASK (2\'b11)) + i_test_gen (.clk (clk)); + + // This is only a compilation test, so we can immediately finish + always @(posedge clk) begin + $write(""*-* All Finished *-*\ +""); + $finish; + end + +endmodule // t + + +module test_gen + + #( parameter + SIZE = `MAX_SIZE, + MASK = `MAX_SIZE\'b0) + + (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // Generate blocks that all have errors in applying short-circuting to + // generate ""if"" conditionals. + + // Attempt to access invalid bits of MASK in different ways + generate + genvar g; + + for (g = 0; g < `MAX_SIZE; g = g + 1) begin + if ((g < (SIZE + 1)) && MASK[g]) begin +\t always @(posedge clk) begin +`ifdef TEST_VERBOSE +\t $write (""Logical AND generate if MASK [%1d] = %d\ +"", g, MASK[g]); +`endif +\t end +\t end + end + endgenerate + + generate + for (g = 0; g < `MAX_SIZE; g = g + 1) begin + if ((g < SIZE) && MASK[g + 1]) begin +\t always @(posedge clk) begin +`ifdef TEST_VERBOSE +\t $write (""Logical AND generate if MASK [%1d] = %d\ +"", g, MASK[g]); +`endif +\t end +\t end + end + endgenerate + + // Attempt to short-circuit bitwise AND + generate + for (g = 0; g < `MAX_SIZE; g = g + 1) begin + if ((g < (SIZE)) & MASK[g]) begin +\t always @(posedge clk) begin +`ifdef TEST_VERBOSE +\t $write (""Bitwise AND generate if MASK [%1d] = %d\ +"", g, MASK[g]); +`endif +\t end +\t end + end + endgenerate + + // Attempt to short-circuit bitwise OR + generate + for (g = 0; g < `MAX_SIZE; g = g + 1) begin + if (!((g >= SIZE) | ~MASK[g])) begin +\t always @(posedge clk) begin +`ifdef TEST_VERBOSE +\t $write (""Bitwise OR generate if MASK [%1d] = %d\ +"", g, MASK[g]); +`endif +\t end +\t end + end + endgenerate + +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003 by Wilson Snyder. + +module t; + reg [40:0] disp; initial disp = 41\'ha_bbbb_cccc; + initial begin + // Display formatting + $display(""%x""); // Too few + $display(""%x"",disp,disp); // Too many + $display(""%q""); // Bad escape + $write(""*-* All Finished *-*\ +""); + $finish; + end +endmodule +" +"// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + reg [11:0] in_a; + reg [31:0] sel; + wire [2:0] out_x; + + extractor #(4,3) extractor ( +\t\t\t // Outputs +\t\t\t .out\t(out_x), +\t\t\t // Inputs +\t\t\t .in\t(in_a), +\t\t\t .sel\t(sel)); + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin +\t cyc <= cyc + 1; +\t //$write(""%d %x %x %x\ +"", cyc, in_a, sel, out_x); +\t if (cyc==1) begin +\t in_a <= 12\'b001_101_111_010; +\t sel <= 32\'d0; +\t end +\t if (cyc==2) begin +\t sel <= 32\'d1; +\t if (out_x != 3\'b010) $stop; +\t end +\t if (cyc==3) begin +\t sel <= 32\'d2; +\t if (out_x != 3\'b111) $stop; +\t end +\t if (cyc==4) begin +\t sel <= 32\'d3; +\t if (out_x != 3\'b101) $stop; +\t end +\t if (cyc==9) begin +\t $write(""*-* All Finished *-*\ +""); +\t $finish; +\t end + end + end +endmodule + +module extractor (/*AUTOARG*/ + // Outputs + out, + // Inputs + in, sel + ); + parameter IN_WIDTH=8; + parameter OUT_WIDTH=2; + + input [IN_WIDTH*OUT_WIDTH-1:0] in; + output [OUT_WIDTH-1:0] out; + input [31:0] \t\t sel; + + wire [OUT_WIDTH-1:0] out = selector(in,sel); + + function [OUT_WIDTH-1:0] selector; + input [IN_WIDTH*OUT_WIDTH-1:0] inv; + input [31:0] \t\t selv; + integer i; + begin +\t selector = 0; +\t for (i=0; i