diff --git "a/shard_new_new_cleaned_v_text_17.csv" "b/shard_new_new_cleaned_v_text_17.csv"
new file mode 100644--- /dev/null
+++ "b/shard_new_new_cleaned_v_text_17.csv"
@@ -0,0 +1,109515 @@
+text
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SEDFXBP_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__SEDFXBP_PP_BLACKBOX_V
+
+/**
+ * sedfxbp: Scan delay flop, data enable, non-inverted clock,
+ *          complementary outputs.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sedfxbp (
+    Q   ,
+    Q_N ,
+    CLK ,
+    D   ,
+    DE  ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    output Q_N ;
+    input  CLK ;
+    input  D   ;
+    input  DE  ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SEDFXBP_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLRBN_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__DLRBN_PP_BLACKBOX_V
+
+/**
+ * dlrbn: Delay latch, inverted reset, inverted enable,
+ *        complementary outputs.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlrbn (
+    Q      ,
+    Q_N    ,
+    RESET_B,
+    D      ,
+    GATE_N ,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE_N ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRBN_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLXTP_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__DLXTP_PP_BLACKBOX_V
+
+/**
+ * dlxtp: Delay latch, non-inverted enable, single output.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlxtp (
+    Q   ,
+    D   ,
+    GATE,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    input  D   ;
+    input  GATE;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXTP_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A211O_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__A211O_BEHAVIORAL_V
+
+/**
+ * a211o: 2-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a211o (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , A1, A2          );
+    or  or0  (or0_out_X, and0_out, C1, B1);
+    buf buf0 (X        , or0_out_X       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A211O_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O22AI_SYMBOL_V
+`define SKY130_FD_SC_LS__O22AI_SYMBOL_V
+
+/**
+ * o22ai: 2-input OR into both inputs of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & (B1 | B2))
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o22ai (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  B1,
+    input  B2,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O22AI_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKINV_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__CLKINV_PP_BLACKBOX_V
+
+/**
+ * clkinv: Clock tree inverter.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__clkinv (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKINV_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A2BB2O_2_V
+`define SKY130_FD_SC_LS__A2BB2O_2_V
+
+/**
+ * a2bb2o: 2-input AND, both inputs inverted, into first input, and
+ *         2-input AND into 2nd input of 2-input OR.
+ *
+ *         X = ((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a2bb2o with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a2bb2o.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a2bb2o_2 (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a2bb2o base (
+        .X(X),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a2bb2o_2 (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a2bb2o base (
+        .X(X),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2BB2O_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__TAPMET1_V
+`define SKY130_FD_SC_LS__TAPMET1_V
+
+/**
+ * tapmet1: Tap cell with isolated power and ground connections.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__tapmet1.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__tapmet1.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__tapmet1.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__tapmet1.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPMET1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFRBP_2_V
+`define SKY130_FD_SC_LS__DFRBP_2_V
+
+/**
+ * dfrbp: Delay flop, inverted reset, complementary outputs.
+ *
+ * Verilog wrapper for dfrbp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dfrbp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dfrbp_2 (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_ls__dfrbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .RESET_B(RESET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dfrbp_2 (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    RESET_B
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__dfrbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .RESET_B(RESET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFRBP_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O21BAI_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__O21BAI_PP_SYMBOL_V
+
+/**
+ * o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
+ *         inverted.
+ *
+ *         Y = !((A1 | A2) & !B1_N)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o21bai (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  B1_N,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21BAI_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O21BAI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__O21BAI_BEHAVIORAL_PP_V
+
+/**
+ * o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
+ *         inverted.
+ *
+ *         Y = !((A1 | A2) & !B1_N)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__o21bai (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire b                ;
+    wire or0_out          ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (b                , B1_N                   );
+    or                                 or0         (or0_out          , A2, A1                 );
+    nand                               nand0       (nand0_out_Y      , b, or0_out             );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21BAI_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O32A_1_V
+`define SKY130_FD_SC_LS__O32A_1_V
+
+/**
+ * o32a: 3-input OR and 2-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog wrapper for o32a with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o32a.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o32a_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o32a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o32a_1 (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o32a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O32A_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFSBP_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__SDFSBP_PP_SYMBOL_V
+
+/**
+ * sdfsbp: Scan delay flop, inverted set, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sdfsbp (
+    //# {{data|Data Signals}}
+    input  D    ,
+    output Q    ,
+    output Q_N  ,
+
+    //# {{control|Control Signals}}
+    input  SET_B,
+
+    //# {{scanchain|Scan Chain}}
+    input  SCD  ,
+    input  SCE  ,
+
+    //# {{clocks|Clocking}}
+    input  CLK  ,
+
+    //# {{power|Power}}
+    input  VPB  ,
+    input  VPWR ,
+    input  VGND ,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFSBP_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__FAH_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__FAH_BEHAVIORAL_V
+
+/**
+ * fah: Full adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__fah (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CI
+);
+
+    // Module ports
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CI  ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire xor0_out_SUM;
+    wire a_b         ;
+    wire a_ci        ;
+    wire b_ci        ;
+    wire or0_out_COUT;
+
+    //  Name  Output        Other arguments
+    xor xor0 (xor0_out_SUM, A, B, CI       );
+    buf buf0 (SUM         , xor0_out_SUM   );
+    and and0 (a_b         , A, B           );
+    and and1 (a_ci        , A, CI          );
+    and and2 (b_ci        , B, CI          );
+    or  or0  (or0_out_COUT, a_b, a_ci, b_ci);
+    buf buf1 (COUT        , or0_out_COUT   );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FAH_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A2111O_2_V
+`define SKY130_FD_SC_LS__A2111O_2_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ *         X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog wrapper for a2111o with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a2111o.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a2111o_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a2111o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a2111o_2 (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a2111o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2111O_2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SDFRBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__SDFRBP_BEHAVIORAL_PP_V
+
+/**
+ * sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v""
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+
+`celldefine
+module sky130_fd_sc_ls__sdfrbp (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire buf_Q          ;
+    wire RESET          ;
+    wire mux_out        ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire SCD_delayed    ;
+    wire SCE_delayed    ;
+    wire RESET_B_delayed;
+    wire CLK_delayed    ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+    wire cond2          ;
+    wire cond3          ;
+    wire cond4          ;
+
+    //                                  Name       Output   Other arguments
+    not                                 not0      (RESET  , RESET_B_delayed                                  );
+    sky130_fd_sc_ls__udp_mux_2to1       mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed              );
+    sky130_fd_sc_ls__udp_dff$PR_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    assign cond0 = ( ( RESET_B_delayed === 1\'b1 ) && awake );
+    assign cond1 = ( ( SCE_delayed === 1\'b0 ) && cond0 );
+    assign cond2 = ( ( SCE_delayed === 1\'b1 ) && cond0 );
+    assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
+    assign cond4 = ( ( RESET_B === 1\'b1 ) && awake );
+    buf                                 buf0      (Q      , buf_Q                                            );
+    not                                 not1      (Q_N    , buf_Q                                            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFRBP_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O22AI_1_V
+`define SKY130_FD_SC_LS__O22AI_1_V
+
+/**
+ * o22ai: 2-input OR into both inputs of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o22ai with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o22ai.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o22ai_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o22ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o22ai_1 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o22ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O22AI_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLYGATE4SD1_SYMBOL_V
+`define SKY130_FD_SC_LS__DLYGATE4SD1_SYMBOL_V
+
+/**
+ * dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlygate4sd1 (
+    //# {{data|Data Signals}}
+    input  A,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYGATE4SD1_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__MUX4_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__MUX4_FUNCTIONAL_V
+
+/**
+ * mux4: 4-input multiplexer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_4to2/sky130_fd_sc_ls__udp_mux_4to2.v""
+
+`celldefine
+module sky130_fd_sc_ls__mux4 (
+    X ,
+    A0,
+    A1,
+    A2,
+    A3,
+    S0,
+    S1
+);
+
+    // Module ports
+    output X ;
+    input  A0;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  S0;
+    input  S1;
+
+    // Local signals
+    wire mux_4to20_out_X;
+
+    //                            Name       Output           Other arguments
+    sky130_fd_sc_ls__udp_mux_4to2 mux_4to20 (mux_4to20_out_X, A0, A1, A2, A3, S0, S1);
+    buf                           buf0      (X              , mux_4to20_out_X       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MUX4_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DIODE_TB_V
+`define SKY130_FD_SC_LS__DIODE_TB_V
+
+/**
+ * diode: Antenna tie-down diode.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__diode.v""
+
+module top();
+
+    // Inputs are registered
+    reg DIODE;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        DIODE = 1\'bX;
+        VGND  = 1\'bX;
+        VNB   = 1\'bX;
+        VPB   = 1\'bX;
+        VPWR  = 1\'bX;
+
+        #20   DIODE = 1\'b0;
+        #40   VGND  = 1\'b0;
+        #60   VNB   = 1\'b0;
+        #80   VPB   = 1\'b0;
+        #100  VPWR  = 1\'b0;
+        #120  DIODE = 1\'b1;
+        #140  VGND  = 1\'b1;
+        #160  VNB   = 1\'b1;
+        #180  VPB   = 1\'b1;
+        #200  VPWR  = 1\'b1;
+        #220  DIODE = 1\'b0;
+        #240  VGND  = 1\'b0;
+        #260  VNB   = 1\'b0;
+        #280  VPB   = 1\'b0;
+        #300  VPWR  = 1\'b0;
+        #320  VPWR  = 1\'b1;
+        #340  VPB   = 1\'b1;
+        #360  VNB   = 1\'b1;
+        #380  VGND  = 1\'b1;
+        #400  DIODE = 1\'b1;
+        #420  VPWR  = 1\'bx;
+        #440  VPB   = 1\'bx;
+        #460  VNB   = 1\'bx;
+        #480  VGND  = 1\'bx;
+        #500  DIODE = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__diode dut (.DIODE(DIODE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DIODE_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND3_TB_V
+`define SKY130_FD_SC_LS__NAND3_TB_V
+
+/**
+ * nand3: 3-input NAND.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nand3.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg B;
+    reg C;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        B    = 1\'bX;
+        C    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   B    = 1\'b0;
+        #60   C    = 1\'b0;
+        #80   VGND = 1\'b0;
+        #100  VNB  = 1\'b0;
+        #120  VPB  = 1\'b0;
+        #140  VPWR = 1\'b0;
+        #160  A    = 1\'b1;
+        #180  B    = 1\'b1;
+        #200  C    = 1\'b1;
+        #220  VGND = 1\'b1;
+        #240  VNB  = 1\'b1;
+        #260  VPB  = 1\'b1;
+        #280  VPWR = 1\'b1;
+        #300  A    = 1\'b0;
+        #320  B    = 1\'b0;
+        #340  C    = 1\'b0;
+        #360  VGND = 1\'b0;
+        #380  VNB  = 1\'b0;
+        #400  VPB  = 1\'b0;
+        #420  VPWR = 1\'b0;
+        #440  VPWR = 1\'b1;
+        #460  VPB  = 1\'b1;
+        #480  VNB  = 1\'b1;
+        #500  VGND = 1\'b1;
+        #520  C    = 1\'b1;
+        #540  B    = 1\'b1;
+        #560  A    = 1\'b1;
+        #580  VPWR = 1\'bx;
+        #600  VPB  = 1\'bx;
+        #620  VNB  = 1\'bx;
+        #640  VGND = 1\'bx;
+        #660  C    = 1\'bx;
+        #680  B    = 1\'bx;
+        #700  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__nand3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND3_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND4BB_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__AND4BB_PP_BLACKBOX_V
+
+/**
+ * and4bb: 4-input AND, first two inputs inverted.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__and4bb (
+    X   ,
+    A_N ,
+    B_N ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A_N ;
+    input  B_N ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND4BB_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DFF_P_V
+`define SKY130_FD_SC_LS__UDP_DFF_P_V
+
+/**
+ * udp_dff$P: Positive edge triggered D flip-flop (Q output UDP).
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`include ""./sky130_fd_sc_ls__udp_dff_p.blackbox.v""
+`else
+primitive sky130_fd_sc_ls__udp_dff$P (
+    Q  ,
+    D  ,
+    CLK
+);
+
+    output Q  ;
+    input  D  ;
+    input  CLK;
+
+    reg Q;
+
+    table
+     //  D  CLK  :  Qt : Qt+1
+         1  (01) :  ?  :  1    ; // clocked data
+         0  (01) :  ?  :  0    ;
+         1  (x1) :  1  :  1    ; // reducing pessimism
+         0  (x1) :  0  :  0    ;
+         1  (0x) :  1  :  1    ;
+         0  (0x) :  0  :  0    ;
+         ?  (1x) :  ?  :  -    ; // no change on falling edge
+         ?  (?0) :  ?  :  -    ;
+         *   ?   :  ?  :  -    ; // ignore edges on data
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DFF_P_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if ((!B&C)) (A +=> X) = (0:0:0,0:0:0);
+if ((B&!C)) (A +=> X) = (0:0:0,0:0:0);
+if ((!A&C)) (B +=> X) = (0:0:0,0:0:0);
+if ((A&!C)) (B +=> X) = (0:0:0,0:0:0);
+if ((!A&B)) (C +=> X) = (0:0:0,0:0:0);
+if ((A&!B)) (C +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O41AI_SYMBOL_V
+`define SKY130_FD_SC_LS__O41AI_SYMBOL_V
+
+/**
+ * o41ai: 4-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o41ai (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  A3,
+    input  A4,
+    input  B1,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O41AI_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if ((!A2_N&!B1&!B2)) (A1_N -=> X) = (0:0:0,0:0:0);
+if ((!A2_N&!B1&B2)) (A1_N -=> X) = (0:0:0,0:0:0);
+if ((!A2_N&B1&!B2)) (A1_N -=> X) = (0:0:0,0:0:0);
+if ((!A1_N&!B1&!B2)) (A2_N -=> X) = (0:0:0,0:0:0);
+if ((!A1_N&!B1&B2)) (A2_N -=> X) = (0:0:0,0:0:0);
+if ((!A1_N&B1&!B2)) (A2_N -=> X) = (0:0:0,0:0:0);
+if ((!A1_N&A2_N&B2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1_N&!A2_N&B2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1_N&A2_N&B2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1_N&A2_N&B1)) (B2 +=> X) = (0:0:0,0:0:0);
+if ((A1_N&!A2_N&B1)) (B2 +=> X) = (0:0:0,0:0:0);
+if ((A1_N&A2_N&B1)) (B2 +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A31O_TB_V
+`define SKY130_FD_SC_LS__A31O_TB_V
+
+/**
+ * a31o: 3-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | B1)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a31o.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg A3;
+    reg B1;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        A3   = 1\'bX;
+        B1   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   A3   = 1\'b0;
+        #80   B1   = 1\'b0;
+        #100  VGND = 1\'b0;
+        #120  VNB  = 1\'b0;
+        #140  VPB  = 1\'b0;
+        #160  VPWR = 1\'b0;
+        #180  A1   = 1\'b1;
+        #200  A2   = 1\'b1;
+        #220  A3   = 1\'b1;
+        #240  B1   = 1\'b1;
+        #260  VGND = 1\'b1;
+        #280  VNB  = 1\'b1;
+        #300  VPB  = 1\'b1;
+        #320  VPWR = 1\'b1;
+        #340  A1   = 1\'b0;
+        #360  A2   = 1\'b0;
+        #380  A3   = 1\'b0;
+        #400  B1   = 1\'b0;
+        #420  VGND = 1\'b0;
+        #440  VNB  = 1\'b0;
+        #460  VPB  = 1\'b0;
+        #480  VPWR = 1\'b0;
+        #500  VPWR = 1\'b1;
+        #520  VPB  = 1\'b1;
+        #540  VNB  = 1\'b1;
+        #560  VGND = 1\'b1;
+        #580  B1   = 1\'b1;
+        #600  A3   = 1\'b1;
+        #620  A2   = 1\'b1;
+        #640  A1   = 1\'b1;
+        #660  VPWR = 1\'bx;
+        #680  VPB  = 1\'bx;
+        #700  VNB  = 1\'bx;
+        #720  VGND = 1\'bx;
+        #740  B1   = 1\'bx;
+        #760  A3   = 1\'bx;
+        #780  A2   = 1\'bx;
+        #800  A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__a31o dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A31O_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__EINVN_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__EINVN_PP_BLACKBOX_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__einvn (
+    Z   ,
+    A   ,
+    TE_B,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EINVN_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A1 -=> Y) = (0:0:0,0:0:0);
+(A2 -=> Y) = (0:0:0,0:0:0);
+(A3 -=> Y) = (0:0:0,0:0:0);
+(A4 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&!A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&!A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2&!A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2&!A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2&A3&!A4)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2&A3&A4)) (B1 -=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SEDFXTP_2_V
+`define SKY130_FD_SC_LS__SEDFXTP_2_V
+
+/**
+ * sedfxtp: Scan delay flop, data enable, non-inverted clock,
+ *          single output.
+ *
+ * Verilog wrapper for sedfxtp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__sedfxtp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sedfxtp_2 (
+    Q   ,
+    CLK ,
+    D   ,
+    DE  ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  DE  ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__sedfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .DE(DE),
+        .SCD(SCD),
+        .SCE(SCE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sedfxtp_2 (
+    Q  ,
+    CLK,
+    D  ,
+    DE ,
+    SCD,
+    SCE
+);
+
+    output Q  ;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+    input  SCD;
+    input  SCE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__sedfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .DE(DE),
+        .SCD(SCD),
+        .SCE(SCE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SEDFXTP_2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__OR4BB_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__OR4BB_FUNCTIONAL_PP_V
+
+/**
+ * or4bb: 4-input OR, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__or4bb (
+    X   ,
+    A   ,
+    B   ,
+    C_N ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out        ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out        , D_N, C_N             );
+    or                                 or0         (or0_out_X        , B, A, nand0_out      );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR4BB_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A +=> X) = (0:0:0,0:0:0);
+(B +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DFF_PS_BLACKBOX_V
+`define SKY130_FD_SC_LS__UDP_DFF_PS_BLACKBOX_V
+
+/**
+ * udp_dff$PS: Positive edge triggered D flip-flop with active high
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__udp_dff$PS (
+    Q  ,
+    D  ,
+    CLK,
+    SET
+);
+
+    output Q  ;
+    input  D  ;
+    input  CLK;
+    input  SET;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DFF_PS_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FILL_2_V
+`define SKY130_FD_SC_LS__FILL_2_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog wrapper for fill with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__fill.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__fill_2 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+    sky130_fd_sc_ls__fill base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__fill_2 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__fill base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FILL_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_PWRGOOD_PP_PG_V
+`define SKY130_FD_SC_LS__UDP_PWRGOOD_PP_PG_V
+
+/**
+
+ *   UDP_OUT :=x when VPWR!=1 or VGND!=0
+ *   UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`include ""./sky130_fd_sc_ls__udp_pwrgood_pp_pg.blackbox.v""
+`else
+primitive sky130_fd_sc_ls__udp_pwrgood_pp$PG (
+    UDP_OUT,
+    UDP_IN ,
+    VPWR   ,
+    VGND
+);
+
+    output UDP_OUT;
+    input  UDP_IN ;
+    input  VPWR   ;
+    input  VGND   ;
+
+    table
+     // UDP_IN VPWR VGND : out
+          0     1    0   :  0   ;
+          1     1    0   :  1   ;
+          x     1    0   :  x   ;
+          ?     0    0   :  x   ;
+          ?     1    1   :  x   ;
+          ?     x    0   :  x   ;
+          ?     1    x   :  x   ;
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_PWRGOOD_PP_PG_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O41A_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__O41A_FUNCTIONAL_PP_V
+
+/**
+ * o41a: 4-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__o41a (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A4, A3, A2, A1        );
+    and                                and0        (and0_out_X       , or0_out, B1           );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O41A_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__XNOR3_2_V
+`define SKY130_FD_SC_LS__XNOR3_2_V
+
+/**
+ * xnor3: 3-input exclusive NOR.
+ *
+ * Verilog wrapper for xnor3 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__xnor3.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__xnor3_2 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__xnor3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__xnor3_2 (
+    X,
+    A,
+    B,
+    C
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__xnor3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XNOR3_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__INV_V
+`define SKY130_FD_SC_LS__INV_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__inv.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__inv.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__inv.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__inv.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__INV_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DECAPHE_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__DECAPHE_BEHAVIORAL_PP_V
+
+/**
+ * decaphe: Shielded Decoupling capacitance filler.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__decaphe (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DECAPHE_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O211A_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__O211A_PP_SYMBOL_V
+
+/**
+ * o211a: 2-input OR into first input of 3-input AND.
+ *
+ *        X = ((A1 | A2) & B1 & C1)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o211a (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  B1  ,
+    input  C1  ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O211A_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__HA_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__HA_BEHAVIORAL_PP_V
+
+/**
+ * ha: Half adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__ha (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out_COUT       ;
+    wire pwrgood_pp0_out_COUT;
+    wire xor0_out_SUM        ;
+    wire pwrgood_pp1_out_SUM ;
+
+    //                                 Name         Output                Other arguments
+    and                                and0        (and0_out_COUT       , A, B                     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, and0_out_COUT, VPWR, VGND);
+    buf                                buf0        (COUT                , pwrgood_pp0_out_COUT     );
+    xor                                xor0        (xor0_out_SUM        , B, A                     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , xor0_out_SUM, VPWR, VGND );
+    buf                                buf1        (SUM                 , pwrgood_pp1_out_SUM      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__HA_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND4_SYMBOL_V
+`define SKY130_FD_SC_LS__NAND4_SYMBOL_V
+
+/**
+ * nand4: 4-input NAND.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nand4 (
+    //# {{data|Data Signals}}
+    input  A,
+    input  B,
+    input  C,
+    input  D,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND4_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O211A_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__O211A_BEHAVIORAL_PP_V
+
+/**
+ * o211a: 2-input OR into first input of 3-input AND.
+ *
+ *        X = ((A1 | A2) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__o211a (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1                );
+    and                                and0        (and0_out_X       , or0_out, B1, C1       );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O211A_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__INV_4_V
+`define SKY130_FD_SC_LS__INV_4_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog wrapper for inv with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__inv.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__inv_4 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__inv base (
+        .Y(Y),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__inv_4 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__inv base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__INV_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFRBP_BLACKBOX_V
+`define SKY130_FD_SC_LS__DFRBP_BLACKBOX_V
+
+/**
+ * dfrbp: Delay flop, inverted reset, complementary outputs.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dfrbp (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    RESET_B
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFRBP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if ((!B&!CIN)) (A +=> COUT) = (0:0:0,0:0:0);
+if ((B&CIN)) (A +=> COUT) = (0:0:0,0:0:0);
+if ((!A&!CIN)) (B +=> COUT) = (0:0:0,0:0:0);
+if ((A&CIN)) (B +=> COUT) = (0:0:0,0:0:0);
+if ((!A&B)) (CIN -=> COUT) = (0:0:0,0:0:0);
+if ((A&!B)) (CIN -=> COUT) = (0:0:0,0:0:0);
+if ((!B&!CIN)) (A -=> SUM) = (0:0:0,0:0:0);
+if ((!B&CIN)) (A +=> SUM) = (0:0:0,0:0:0);
+if ((B&!CIN)) (A +=> SUM) = (0:0:0,0:0:0);
+if ((B&CIN)) (A -=> SUM) = (0:0:0,0:0:0);
+if ((!A&!CIN)) (B -=> SUM) = (0:0:0,0:0:0);
+if ((!A&CIN)) (B +=> SUM) = (0:0:0,0:0:0);
+if ((A&!CIN)) (B +=> SUM) = (0:0:0,0:0:0);
+if ((A&CIN)) (B -=> SUM) = (0:0:0,0:0:0);
+if ((!A&!B)) (CIN -=> SUM) = (0:0:0,0:0:0);
+if ((!A&B)) (CIN +=> SUM) = (0:0:0,0:0:0);
+if ((A&!B)) (CIN +=> SUM) = (0:0:0,0:0:0);
+if ((A&B)) (CIN -=> SUM) = (0:0:0,0:0:0);
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O221AI_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__O221AI_BEHAVIORAL_V
+
+/**
+ * o221ai: 2-input OR into first two inputs of 3-input NAND.
+ *
+ *         Y = !((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__o221ai (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out    ;
+    wire or1_out    ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    or   or0   (or0_out    , B2, B1              );
+    or   or1   (or1_out    , A2, A1              );
+    nand nand0 (nand0_out_Y, or1_out, or0_out, C1);
+    buf  buf0  (Y          , nand0_out_Y         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O221AI_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_PWRGOOD_PP_P_V
+`define SKY130_FD_SC_LS__UDP_PWRGOOD_PP_P_V
+
+/**
+
+ *   UDP_OUT :=x when VPWR!=1
+ *   UDP_OUT :=UDP_IN when VPWR==1
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`include ""./sky130_fd_sc_ls__udp_pwrgood_pp_p.blackbox.v""
+`else
+primitive sky130_fd_sc_ls__udp_pwrgood_pp$P (
+    UDP_OUT,
+    UDP_IN ,
+    VPWR
+);
+
+    output UDP_OUT;
+    input  UDP_IN ;
+    input  VPWR   ;
+
+    table
+     // UDP_IN VPWR : UDP_OUT
+          0     1   :    0     ;
+          1     1   :    1     ;
+          ?     0   :    x     ;
+          ?     x   :    x     ;
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_PWRGOOD_PP_P_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLRBN_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__DLRBN_PP_SYMBOL_V
+
+/**
+ * dlrbn: Delay latch, inverted reset, inverted enable,
+ *        complementary outputs.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlrbn (
+    //# {{data|Data Signals}}
+    input  D      ,
+    output Q      ,
+    output Q_N    ,
+
+    //# {{control|Control Signals}}
+    input  RESET_B,
+
+    //# {{clocks|Clocking}}
+    input  GATE_N ,
+
+    //# {{power|Power}}
+    input  VPB    ,
+    input  VPWR   ,
+    input  VGND   ,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRBN_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A +=> X) = (0:0:0,0:0:0);
+(B +=> X) = (0:0:0,0:0:0);
+(C +=> X) = (0:0:0,0:0:0);
+(D +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O311A_V
+`define SKY130_FD_SC_LS__O311A_V
+
+/**
+ * o311a: 3-input OR into 3-input AND.
+ *
+ *        X = ((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o311a.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o311a.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o311a.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o311a.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O311A_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NAND4BB_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__NAND4BB_FUNCTIONAL_V
+
+/**
+ * nand4bb: 4-input NAND, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__nand4bb (
+    Y  ,
+    A_N,
+    B_N,
+    C  ,
+    D
+);
+
+    // Module ports
+    output Y  ;
+    input  A_N;
+    input  B_N;
+    input  C  ;
+    input  D  ;
+
+    // Local signals
+    wire nand0_out;
+    wire or0_out_Y;
+
+    //   Name   Output     Other arguments
+    nand nand0 (nand0_out, D, C               );
+    or   or0   (or0_out_Y, B_N, A_N, nand0_out);
+    buf  buf0  (Y        , or0_out_Y          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND4BB_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLXBN_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__DLXBN_BEHAVIORAL_V
+
+/**
+ * dlxbn: Delay latch, inverted enable, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlxbn (
+    Q     ,
+    Q_N   ,
+    D     ,
+    GATE_N
+);
+
+    // Module ports
+    output Q     ;
+    output Q_N   ;
+    input  D     ;
+    input  GATE_N;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire GATE          ;
+    wire buf_Q         ;
+    wire GATE_N_delayed;
+    wire D_delayed     ;
+    reg  notifier      ;
+    wire awake         ;
+    wire 1             ;
+
+    //                                    Name     Output  Other arguments
+    not                                   not0    (GATE  , GATE_N_delayed                       );
+    sky130_fd_sc_ls__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1 );
+    buf                                   buf0    (Q     , buf_Q                                );
+    not                                   not1    (Q_N   , buf_Q                                );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXBN_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if ((!A1&!S)) (A0 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!S)) (A0 -=> Y) = (0:0:0,0:0:0);
+if ((!A0&S)) (A1 -=> Y) = (0:0:0,0:0:0);
+if ((A0&S)) (A1 -=> Y) = (0:0:0,0:0:0);
+if ((!A0&A1)) (S -=> Y) = (0:0:0,0:0:0);
+if ((A0&!A1)) (S +=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__TAPMET1_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__TAPMET1_BEHAVIORAL_V
+
+/**
+ * tapmet1: Tap cell with isolated power and ground connections.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__tapmet1 ();
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPMET1_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O21A_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__O21A_PP_BLACKBOX_V
+
+/**
+ * o21a: 2-input OR into first input of 2-input AND.
+ *
+ *       X = ((A1 | A2) & B1)
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o21a (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21A_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FILL_BLACKBOX_V
+`define SKY130_FD_SC_LS__FILL_BLACKBOX_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__fill ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FILL_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A -=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR4_4_V
+`define SKY130_FD_SC_LS__OR4_4_V
+
+/**
+ * or4: 4-input OR.
+ *
+ * Verilog wrapper for or4 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__or4.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__or4_4 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__or4 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__or4_4 (
+    X,
+    A,
+    B,
+    C,
+    D
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__or4 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR4_4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__MAJ3_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__MAJ3_FUNCTIONAL_V
+
+/**
+ * maj3: 3-input majority vote.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__maj3 (
+    X,
+    A,
+    B,
+    C
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Local signals
+    wire or0_out  ;
+    wire and0_out ;
+    wire and1_out ;
+    wire or1_out_X;
+
+    //  Name  Output     Other arguments
+    or  or0  (or0_out  , B, A              );
+    and and0 (and0_out , or0_out, C        );
+    and and1 (and1_out , A, B              );
+    or  or1  (or1_out_X, and1_out, and0_out);
+    buf buf0 (X        , or1_out_X         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MAJ3_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR2B_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__OR2B_PP_BLACKBOX_V
+
+/**
+ * or2b: 2-input OR, first input inverted.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__or2b (
+    X   ,
+    A   ,
+    B_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR2B_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NOR2B_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__NOR2B_BEHAVIORAL_PP_V
+
+/**
+ * nor2b: 2-input NOR, first input inverted.
+ *
+ *        Y = !(A | B | C | !D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__nor2b (
+    Y   ,
+    A   ,
+    B_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire and0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , A                     );
+    and                                and0        (and0_out_Y       , not0_out, B_N         );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR2B_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__OR4_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__OR4_FUNCTIONAL_PP_V
+
+/**
+ * or4: 4-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__or4 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out_X        , D, C, B, A           );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR4_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O41A_BLACKBOX_V
+`define SKY130_FD_SC_LS__O41A_BLACKBOX_V
+
+/**
+ * o41a: 4-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o41a (
+    X ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O41A_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O2111A_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__O2111A_PP_BLACKBOX_V
+
+/**
+ * o2111a: 2-input OR into first input of 4-input AND.
+ *
+ *         X = ((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o2111a (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2111A_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD1_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__CLKDLYINV3SD1_BEHAVIORAL_V
+
+/**
+ * clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
+ *                stage gate.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__clkdlyinv3sd1 (
+    Y,
+    A
+);
+
+    // Module ports
+    output Y;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out_Y, A              );
+    buf buf0 (Y         , not0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV3SD1_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A32O_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__A32O_PP_SYMBOL_V
+
+/**
+ * a32o: 3-input AND into first input, and 2-input AND into
+ *       2nd input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a32o (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  A3  ,
+    input  B1  ,
+    input  B2  ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A32O_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A21O_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__A21O_PP_BLACKBOX_V
+
+/**
+ * a21o: 2-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2) | B1)
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a21o (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21O_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__AND2_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__AND2_FUNCTIONAL_PP_V
+
+/**
+ * and2: 2-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__and2 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out_X       , A, B                  );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND2_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFSTP_V
+`define SKY130_FD_SC_LS__SDFSTP_V
+
+/**
+ * sdfstp: Scan delay flop, inverted set, non-inverted clock,
+ *         single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__sdfstp.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__sdfstp.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__sdfstp.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__sdfstp.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFSTP_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND3B_BLACKBOX_V
+`define SKY130_FD_SC_LS__AND3B_BLACKBOX_V
+
+/**
+ * and3b: 3-input AND, first input inverted.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__and3b (
+    X  ,
+    A_N,
+    B  ,
+    C
+);
+
+    output X  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND3B_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DIODE_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__DIODE_FUNCTIONAL_V
+
+/**
+ * diode: Antenna tie-down diode.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__diode (
+    DIODE
+);
+
+    // Module ports
+    input DIODE;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DIODE_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__INV_2_V
+`define SKY130_FD_SC_LS__INV_2_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog wrapper for inv with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__inv.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__inv_2 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__inv base (
+        .Y(Y),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__inv_2 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__inv base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__INV_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFSBP_BLACKBOX_V
+`define SKY130_FD_SC_LS__SDFSBP_BLACKBOX_V
+
+/**
+ * sdfsbp: Scan delay flop, inverted set, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sdfsbp (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B
+);
+
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFSBP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFSBP_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__DFSBP_PP_BLACKBOX_V
+
+/**
+ * dfsbp: Delay flop, inverted set, complementary outputs.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dfsbp (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFSBP_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFXBP_V
+`define SKY130_FD_SC_LS__SDFXBP_V
+
+/**
+ * sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__sdfxbp.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__sdfxbp.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__sdfxbp.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__sdfxbp.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFXBP_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND3B_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__AND3B_PP_BLACKBOX_V
+
+/**
+ * and3b: 3-input AND, first input inverted.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__and3b (
+    X   ,
+    A_N ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND3B_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A1 -=> Y) = (0:0:0,0:0:0);
+(A2 -=> Y) = (0:0:0,0:0:0);
+(A3 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SEDFXTP_1_V
+`define SKY130_FD_SC_LS__SEDFXTP_1_V
+
+/**
+ * sedfxtp: Scan delay flop, data enable, non-inverted clock,
+ *          single output.
+ *
+ * Verilog wrapper for sedfxtp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__sedfxtp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sedfxtp_1 (
+    Q   ,
+    CLK ,
+    D   ,
+    DE  ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  DE  ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__sedfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .DE(DE),
+        .SCD(SCD),
+        .SCE(SCE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sedfxtp_1 (
+    Q  ,
+    CLK,
+    D  ,
+    DE ,
+    SCD,
+    SCE
+);
+
+    output Q  ;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+    input  SCD;
+    input  SCE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__sedfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .DE(DE),
+        .SCD(SCD),
+        .SCE(SCE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SEDFXTP_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A -=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A221O_SYMBOL_V
+`define SKY130_FD_SC_LS__A221O_SYMBOL_V
+
+/**
+ * a221o: 2-input AND into first two inputs of 3-input OR.
+ *
+ *        X = ((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a221o (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  B1,
+    input  B2,
+    input  C1,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A221O_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A221O_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__A221O_PP_BLACKBOX_V
+
+/**
+ * a221o: 2-input AND into first two inputs of 3-input OR.
+ *
+ *        X = ((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a221o (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A221O_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O211AI_BLACKBOX_V
+`define SKY130_FD_SC_LS__O211AI_BLACKBOX_V
+
+/**
+ * o211ai: 2-input OR into first input of 3-input NAND.
+ *
+ *         Y = !((A1 | A2) & B1 & C1)
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o211ai (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O211AI_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR2_BLACKBOX_V
+`define SKY130_FD_SC_LS__NOR2_BLACKBOX_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nor2 (
+    Y,
+    A,
+    B
+);
+
+    output Y;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR2_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A222O_V
+`define SKY130_FD_SC_LS__A222O_V
+
+/**
+ * a222o: 2-input AND into all inputs of 3-input OR.
+ *
+ *        X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a222o.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a222o.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a222o.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a222o.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A222O_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__MUX4_BLACKBOX_V
+`define SKY130_FD_SC_LS__MUX4_BLACKBOX_V
+
+/**
+ * mux4: 4-input multiplexer.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__mux4 (
+    X ,
+    A0,
+    A1,
+    A2,
+    A3,
+    S0,
+    S1
+);
+
+    output X ;
+    input  A0;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  S0;
+    input  S1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MUX4_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O311AI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__O311AI_BEHAVIORAL_PP_V
+
+/**
+ * o311ai: 3-input OR into 3-input NAND.
+ *
+ *         Y = !((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__o311ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1, A3             );
+    nand                               nand0       (nand0_out_Y      , C1, or0_out, B1        );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O311AI_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+( D +=> Q ) = ( 0:0:0 , 0:0:0 ) ;  // delays are tris , tfall
+( negedge GATE_N => ( Q +: D ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall
+$width ( negedge GATE_N &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+$setuphold ( posedge GATE_N , posedge D , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , GATEN_delayed , D_delayed ) ;
+$setuphold ( posedge GATE_N , negedge D , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , GATEN_delayed , D_delayed ) ;
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND2B_2_V
+`define SKY130_FD_SC_LS__AND2B_2_V
+
+/**
+ * and2b: 2-input AND, first input inverted.
+ *
+ * Verilog wrapper for and2b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__and2b.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__and2b_2 (
+    X   ,
+    A_N ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A_N ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__and2b base (
+        .X(X),
+        .A_N(A_N),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__and2b_2 (
+    X  ,
+    A_N,
+    B
+);
+
+    output X  ;
+    input  A_N;
+    input  B  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__and2b base (
+        .X(X),
+        .A_N(A_N),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND2B_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A2111O_BLACKBOX_V
+`define SKY130_FD_SC_LS__A2111O_BLACKBOX_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ *         X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a2111o (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2111O_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__INV_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__INV_PP_BLACKBOX_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__inv (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__INV_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND3_V
+`define SKY130_FD_SC_LS__AND3_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__and3.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__and3.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__and3.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__and3.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND3_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A311O_1_V
+`define SKY130_FD_SC_LS__A311O_1_V
+
+/**
+ * a311o: 3-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog wrapper for a311o with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a311o.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a311o_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a311o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a311o_1 (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a311o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A311O_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NAND4_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__NAND4_BEHAVIORAL_PP_V
+
+/**
+ * nand4: 4-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__nand4 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out_Y      , D, C, B, A             );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND4_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DECAPHE_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__DECAPHE_PP_SYMBOL_V
+
+/**
+ * decaphe: Shielded Decoupling capacitance filler.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__decaphe (
+    //# {{power|Power}}
+    input VPB ,
+    input VPWR,
+    input VGND,
+    input VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DECAPHE_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if ((!A2&!B1&B2&C1)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((!A2&B1&!B2&C1)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((!A2&B1&B2&C1)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!B1&B2&C1)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&B1&!B2&C1)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&B1&B2&C1)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&!B2&C1)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&!B2&C1)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2&!B2&C1)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&!B1&C1)) (B2 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&!B1&C1)) (B2 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2&!B1&C1)) (B2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&!B1&B2)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&B1&B2)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&!B1&B2)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&B1&B2)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2&!B1&B2)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2&B1&!B2)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2&B1&B2)) (C1 +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O2111AI_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__O2111AI_FUNCTIONAL_V
+
+/**
+ * o2111ai: 2-input OR into first input of 4-input NAND.
+ *
+ *          Y = !((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__o2111ai (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Local signals
+    wire or0_out    ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    or   or0   (or0_out    , A2, A1             );
+    nand nand0 (nand0_out_Y, C1, B1, D1, or0_out);
+    buf  buf0  (Y          , nand0_out_Y        );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2111AI_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A2BB2OI_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__A2BB2OI_BEHAVIORAL_V
+
+/**
+ * a2bb2oi: 2-input AND, both inputs inverted, into first input, and
+ *          2-input AND into 2nd input of 2-input NOR.
+ *
+ *          Y = !((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a2bb2oi (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    // Module ports
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out  ;
+    wire nor0_out  ;
+    wire nor1_out_Y;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out  , B1, B2            );
+    nor nor0 (nor0_out  , A1_N, A2_N        );
+    nor nor1 (nor1_out_Y, nor0_out, and0_out);
+    buf buf0 (Y         , nor1_out_Y        );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2BB2OI_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__OR2_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__OR2_BEHAVIORAL_V
+
+/**
+ * or2: 2-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__or2 (
+    X,
+    A,
+    B
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    or  or0  (or0_out_X, B, A           );
+    buf buf0 (X        , or0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR2_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFXTP_V
+`define SKY130_FD_SC_LS__SDFXTP_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__sdfxtp.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__sdfxtp.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__sdfxtp.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__sdfxtp.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFXTP_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A -=> Y) = (0:0:0,0:0:0);
+(B -=> Y) = (0:0:0,0:0:0);
+(C -=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLYGATE4SD2_BLACKBOX_V
+`define SKY130_FD_SC_LS__DLYGATE4SD2_BLACKBOX_V
+
+/**
+ * dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlygate4sd2 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYGATE4SD2_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__TAPVGND_V
+`define SKY130_FD_SC_LS__TAPVGND_V
+
+/**
+ * tapvgnd: Tap cell with tap to ground, isolated power connection
+ *          1 row down.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__tapvgnd.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__tapvgnd.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__tapvgnd.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__tapvgnd.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPVGND_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A211O_SYMBOL_V
+`define SKY130_FD_SC_LS__A211O_SYMBOL_V
+
+/**
+ * a211o: 2-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2) | B1 | C1)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a211o (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  B1,
+    input  C1,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A211O_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O211AI_1_V
+`define SKY130_FD_SC_LS__O211AI_1_V
+
+/**
+ * o211ai: 2-input OR into first input of 3-input NAND.
+ *
+ *         Y = !((A1 | A2) & B1 & C1)
+ *
+ * Verilog wrapper for o211ai with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o211ai.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o211ai_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o211ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o211ai_1 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o211ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O211AI_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O2111A_BLACKBOX_V
+`define SKY130_FD_SC_LS__O2111A_BLACKBOX_V
+
+/**
+ * o2111a: 2-input OR into first input of 4-input AND.
+ *
+ *         X = ((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o2111a (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2111A_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_MUX_4TO2_V
+`define SKY130_FD_SC_LS__UDP_MUX_4TO2_V
+
+/**
+ * udp_mux_4to2: Four to one multiplexer with 2 select controls
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`include ""./sky130_fd_sc_ls__udp_mux_4to2.blackbox.v""
+`else
+primitive sky130_fd_sc_ls__udp_mux_4to2 (
+    X ,
+    A0,
+    A1,
+    A2,
+    A3,
+    S0,
+    S1
+);
+
+    output X ;
+    input  A0;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  S0;
+    input  S1;
+
+    table
+     //  A0  A1  A2  A3  S0  S1 :  X
+         0   ?   ?   ?   0   0  :  0   ;
+         1   ?   ?   ?   0   0  :  1   ;
+         ?   0   ?   ?   1   0  :  0   ;
+         ?   1   ?   ?   1   0  :  1   ;
+         ?   ?   0   ?   0   1  :  0   ;
+         ?   ?   1   ?   0   1  :  1   ;
+         ?   ?   ?   0   1   1  :  0   ;
+         ?   ?   ?   1   1   1  :  1   ;
+         0   0   0   0   ?   ?  :  0   ;
+         1   1   1   1   ?   ?  :  1   ;
+         0   0   ?   ?   ?   0  :  0   ;
+         1   1   ?   ?   ?   0  :  1   ;
+         ?   ?   0   0   ?   1  :  0   ;
+         ?   ?   1   1   ?   1  :  1   ;
+         0   ?   0   ?   0   ?  :  0   ;
+         1   ?   1   ?   0   ?  :  1   ;
+         ?   0   ?   0   1   ?  :  0   ;
+         ?   1   ?   1   1   ?  :  1   ;
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_MUX_4TO2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A221O_V
+`define SKY130_FD_SC_LS__A221O_V
+
+/**
+ * a221o: 2-input AND into first two inputs of 3-input OR.
+ *
+ *        X = ((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a221o.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a221o.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a221o.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a221o.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A221O_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFRBP_SYMBOL_V
+`define SKY130_FD_SC_LS__SDFRBP_SYMBOL_V
+
+/**
+ * sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sdfrbp (
+    //# {{data|Data Signals}}
+    input  D      ,
+    output Q      ,
+    output Q_N    ,
+
+    //# {{control|Control Signals}}
+    input  RESET_B,
+
+    //# {{scanchain|Scan Chain}}
+    input  SCD    ,
+    input  SCE    ,
+
+    //# {{clocks|Clocking}}
+    input  CLK
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFRBP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLYGATE4SD3_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__DLYGATE4SD3_PP_SYMBOL_V
+
+/**
+ * dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlygate4sd3 (
+    //# {{data|Data Signals}}
+    input  A   ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYGATE4SD3_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLRTN_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__DLRTN_PP_SYMBOL_V
+
+/**
+ * dlrtn: Delay latch, inverted reset, inverted enable, single output.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlrtn (
+    //# {{data|Data Signals}}
+    input  D      ,
+    output Q      ,
+
+    //# {{control|Control Signals}}
+    input  RESET_B,
+
+    //# {{clocks|Clocking}}
+    input  GATE_N ,
+
+    //# {{power|Power}}
+    input  VPB    ,
+    input  VPWR   ,
+    input  VGND   ,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRTN_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__TAPVPWRVGND_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__TAPVPWRVGND_FUNCTIONAL_V
+
+/**
+ * tapvpwrvgnd: Substrate and well tap cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__tapvpwrvgnd ();
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPVPWRVGND_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A21BO_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__A21BO_FUNCTIONAL_V
+
+/**
+ * a21bo: 2-input AND into first input of 2-input OR,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 & A2) | (!B1_N))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a21bo (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Local signals
+    wire nand0_out  ;
+    wire nand1_out_X;
+
+    //   Name   Output       Other arguments
+    nand nand0 (nand0_out  , A2, A1         );
+    nand nand1 (nand1_out_X, B1_N, nand0_out);
+    buf  buf0  (X          , nand1_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21BO_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DFXBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__DFXBP_BEHAVIORAL_PP_V
+
+/**
+ * dfxbp: Delay flop, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dfxbp (
+    Q   ,
+    Q_N ,
+    CLK ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    output Q_N ;
+    input  CLK ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q      ;
+    reg  notifier   ;
+    wire D_delayed  ;
+    wire CLK_delayed;
+    wire awake      ;
+
+    //                                 Name  Output  Other arguments
+    sky130_fd_sc_ls__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    buf                                buf0 (Q     , buf_Q                                       );
+    not                                not0 (Q_N   , buf_Q                                       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFXBP_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__MAJ3_V
+`define SKY130_FD_SC_LS__MAJ3_V
+
+/**
+ * maj3: 3-input majority vote.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__maj3.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__maj3.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__maj3.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__maj3.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MAJ3_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DFBBN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__DFBBN_FUNCTIONAL_PP_V
+
+/**
+ * dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ls__udp_dff_nsr_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dfbbn (
+    Q      ,
+    Q_N    ,
+    D      ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire RESET;
+    wire SET  ;
+    wire CLK  ;
+    wire buf_Q;
+
+    //                                   Delay       Name  Output  Other arguments
+    not                                              not0 (RESET , RESET_B                         );
+    not                                              not1 (SET   , SET_B                           );
+    not                                              not2 (CLK   , CLK_N                           );
+    sky130_fd_sc_ls__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D, , VPWR, VGND);
+    buf                                              buf0 (Q     , buf_Q                           );
+    not                                              not3 (Q_N   , buf_Q                           );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFBBN_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NAND4_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__NAND4_BEHAVIORAL_V
+
+/**
+ * nand4: 4-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__nand4 (
+    Y,
+    A,
+    B,
+    C,
+    D
+);
+
+    // Module ports
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    nand nand0 (nand0_out_Y, D, C, B, A     );
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND4_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DLATCH_P_V
+`define SKY130_FD_SC_LS__UDP_DLATCH_P_V
+
+/**
+ * udp_dlatch$P: D-latch, gated standard drive / active high
+ *               (Q output UDP)
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`include ""./sky130_fd_sc_ls__udp_dlatch_p.blackbox.v""
+`else
+primitive sky130_fd_sc_ls__udp_dlatch$P (
+    Q   ,
+    D   ,
+    GATE
+);
+
+    output Q   ;
+    input  D   ;
+    input  GATE;
+
+    reg Q;
+
+    table
+     //  D  GATE :  Qt : Qt+1
+         ?   0   :  ?  :  -    ; // hold
+         0   1   :  ?  :  0    ; // pass 0
+         1   1   :  ?  :  1    ; // pass 1
+         0   x   :  0  :  0    ; // reduce pessimism
+         1   x   :  1  :  1    ; // reduce pessimism
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DLATCH_P_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__BUFINV_16_V
+`define SKY130_FD_SC_LS__BUFINV_16_V
+
+/**
+ * bufinv: Buffer followed by inverter.
+ *
+ * Verilog wrapper for bufinv with size of 16 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__bufinv.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__bufinv_16 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__bufinv base (
+        .Y(Y),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__bufinv_16 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__bufinv base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__BUFINV_16_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLRBN_2_V
+`define SKY130_FD_SC_LS__DLRBN_2_V
+
+/**
+ * dlrbn: Delay latch, inverted reset, inverted enable,
+ *        complementary outputs.
+ *
+ * Verilog wrapper for dlrbn with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dlrbn.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dlrbn_2 (
+    Q      ,
+    Q_N    ,
+    RESET_B,
+    D      ,
+    GATE_N ,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE_N ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_ls__dlrbn base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .RESET_B(RESET_B),
+        .D(D),
+        .GATE_N(GATE_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dlrbn_2 (
+    Q      ,
+    Q_N    ,
+    RESET_B,
+    D      ,
+    GATE_N
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE_N ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__dlrbn base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .RESET_B(RESET_B),
+        .D(D),
+        .GATE_N(GATE_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRBN_2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__EBUFN_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__EBUFN_BEHAVIORAL_V
+
+/**
+ * ebufn: Tri-state buffer, negative enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__ebufn (
+    Z   ,
+    A   ,
+    TE_B
+);
+
+    // Module ports
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    //     Name     Output  Other arguments
+    bufif0 bufif00 (Z     , A, TE_B        );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EBUFN_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A32O_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__A32O_FUNCTIONAL_PP_V
+
+/**
+ * a32o: 3-input AND into first input, and 2-input AND into
+ *       2nd input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a32o (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire and1_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A3, A1, A2           );
+    and                                and1        (and1_out         , B1, B2               );
+    or                                 or0         (or0_out_X        , and1_out, and0_out   );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A32O_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A -=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O31A_V
+`define SKY130_FD_SC_LS__O31A_V
+
+/**
+ * o31a: 3-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o31a.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o31a.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o31a.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o31a.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O31A_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+( posedge CLK => ( Q : CLK ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall
+( posedge CLK => ( Q_N : CLK ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall
+$setuphold ( posedge CLK , posedge DE , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , CLK_delayed , DE_delayed ) ;
+$setuphold ( posedge CLK , negedge DE , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , CLK_delayed , DE_delayed ) ;
+$setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ;
+$setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ;
+$setuphold ( posedge CLK , posedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ;
+$setuphold ( posedge CLK , negedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ;
+$setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ;
+$setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ;
+$width ( posedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( negedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__TAPMET1_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__TAPMET1_BEHAVIORAL_PP_V
+
+/**
+ * tapmet1: Tap cell with isolated power and ground connections.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__tapmet1 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPMET1_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A1 +=> X) = (0:0:0,0:0:0);
+(A2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&C1)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&C1)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2&C1)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&B1)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&B1)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2&B1)) (C1 +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__MUX2I_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__MUX2I_BEHAVIORAL_V
+
+/**
+ * mux2i: 2-input multiplexer, output inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1_n/sky130_fd_sc_ls__udp_mux_2to1_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__mux2i (
+    Y ,
+    A0,
+    A1,
+    S
+);
+
+    // Module ports
+    output Y ;
+    input  A0;
+    input  A1;
+    input  S ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire mux_2to1_n0_out_Y;
+
+    //                              Name         Output             Other arguments
+    sky130_fd_sc_ls__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S        );
+    buf                             buf0        (Y                , mux_2to1_n0_out_Y);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MUX2I_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKBUF_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__CLKBUF_PP_BLACKBOX_V
+
+/**
+ * clkbuf: Clock tree buffer.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__clkbuf (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKBUF_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__XOR3_4_V
+`define SKY130_FD_SC_LS__XOR3_4_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ *       X = A ^ B ^ C
+ *
+ * Verilog wrapper for xor3 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__xor3.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__xor3_4 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__xor3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__xor3_4 (
+    X,
+    A,
+    B,
+    C
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__xor3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XOR3_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FAHCON_V
+`define SKY130_FD_SC_LS__FAHCON_V
+
+/**
+ * fahcon: Full adder, inverted carry in, inverted carry out.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__fahcon.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__fahcon.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__fahcon.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__fahcon.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FAHCON_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__TAPVPWRVGND_1_V
+`define SKY130_FD_SC_LS__TAPVPWRVGND_1_V
+
+/**
+ * tapvpwrvgnd: Substrate and well tap cell.
+ *
+ * Verilog wrapper for tapvpwrvgnd with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__tapvpwrvgnd.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__tapvpwrvgnd_1 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+    sky130_fd_sc_ls__tapvpwrvgnd base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__tapvpwrvgnd_1 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__tapvpwrvgnd base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPVPWRVGND_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A221OI_4_V
+`define SKY130_FD_SC_LS__A221OI_4_V
+
+/**
+ * a221oi: 2-input AND into first two inputs of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog wrapper for a221oi with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a221oi.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a221oi_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a221oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a221oi_4 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a221oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A221OI_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR3_V
+`define SKY130_FD_SC_LS__OR3_V
+
+/**
+ * or3: 3-input OR.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__or3.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__or3.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__or3.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__or3.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR3_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O21BA_TB_V
+`define SKY130_FD_SC_LS__O21BA_TB_V
+
+/**
+ * o21ba: 2-input OR into first input of 2-input AND,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 | A2) & !B1_N)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o21ba.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg B1_N;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        B1_N = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   B1_N = 1\'b0;
+        #80   VGND = 1\'b0;
+        #100  VNB  = 1\'b0;
+        #120  VPB  = 1\'b0;
+        #140  VPWR = 1\'b0;
+        #160  A1   = 1\'b1;
+        #180  A2   = 1\'b1;
+        #200  B1_N = 1\'b1;
+        #220  VGND = 1\'b1;
+        #240  VNB  = 1\'b1;
+        #260  VPB  = 1\'b1;
+        #280  VPWR = 1\'b1;
+        #300  A1   = 1\'b0;
+        #320  A2   = 1\'b0;
+        #340  B1_N = 1\'b0;
+        #360  VGND = 1\'b0;
+        #380  VNB  = 1\'b0;
+        #400  VPB  = 1\'b0;
+        #420  VPWR = 1\'b0;
+        #440  VPWR = 1\'b1;
+        #460  VPB  = 1\'b1;
+        #480  VNB  = 1\'b1;
+        #500  VGND = 1\'b1;
+        #520  B1_N = 1\'b1;
+        #540  A2   = 1\'b1;
+        #560  A1   = 1\'b1;
+        #580  VPWR = 1\'bx;
+        #600  VPB  = 1\'bx;
+        #620  VNB  = 1\'bx;
+        #640  VGND = 1\'bx;
+        #660  B1_N = 1\'bx;
+        #680  A2   = 1\'bx;
+        #700  A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__o21ba dut (.A1(A1), .A2(A2), .B1_N(B1_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21BA_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__OR3B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__OR3B_FUNCTIONAL_PP_V
+
+/**
+ * or3b: 3-input OR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__or3b (
+    X   ,
+    A   ,
+    B   ,
+    C_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , C_N                  );
+    or                                 or0         (or0_out_X        , B, A, not0_out       );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR3B_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_MUX_2TO1_N_V
+`define SKY130_FD_SC_LS__UDP_MUX_2TO1_N_V
+
+/**
+ * udp_mux_2to1_N: Two to one multiplexer with inverting output
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`include ""./sky130_fd_sc_ls__udp_mux_2to1_n.blackbox.v""
+`else
+primitive sky130_fd_sc_ls__udp_mux_2to1_N (
+    Y ,
+    A0,
+    A1,
+    S
+);
+
+    output Y ;
+    input  A0;
+    input  A1;
+    input  S ;
+
+    table
+     //  A0  A1  S  :  Y
+         0   ?   0  :  1   ;
+         1   ?   0  :  0   ;
+         ?   0   1  :  1   ;
+         ?   1   1  :  0   ;
+         0   0   ?  :  1   ;
+         1   1   ?  :  0   ;
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_MUX_2TO1_N_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A311O_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__A311O_PP_BLACKBOX_V
+
+/**
+ * a311o: 3-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a311o (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A311O_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A22O_BLACKBOX_V
+`define SKY130_FD_SC_LS__A22O_BLACKBOX_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ *       X = ((A1 & A2) | (B1 & B2))
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a22o (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A22O_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKBUF_TB_V
+`define SKY130_FD_SC_LS__CLKBUF_TB_V
+
+/**
+ * clkbuf: Clock tree buffer.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__clkbuf.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   VGND = 1\'b0;
+        #60   VNB  = 1\'b0;
+        #80   VPB  = 1\'b0;
+        #100  VPWR = 1\'b0;
+        #120  A    = 1\'b1;
+        #140  VGND = 1\'b1;
+        #160  VNB  = 1\'b1;
+        #180  VPB  = 1\'b1;
+        #200  VPWR = 1\'b1;
+        #220  A    = 1\'b0;
+        #240  VGND = 1\'b0;
+        #260  VNB  = 1\'b0;
+        #280  VPB  = 1\'b0;
+        #300  VPWR = 1\'b0;
+        #320  VPWR = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VNB  = 1\'b1;
+        #380  VGND = 1\'b1;
+        #400  A    = 1\'b1;
+        #420  VPWR = 1\'bx;
+        #440  VPB  = 1\'bx;
+        #460  VNB  = 1\'bx;
+        #480  VGND = 1\'bx;
+        #500  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__clkbuf dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKBUF_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLXTN_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__DLXTN_PP_BLACKBOX_V
+
+/**
+ * dlxtn: Delay latch, inverted enable, single output.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlxtn (
+    Q     ,
+    D     ,
+    GATE_N,
+    VPWR  ,
+    VGND  ,
+    VPB   ,
+    VNB
+);
+
+    output Q     ;
+    input  D     ;
+    input  GATE_N;
+    input  VPWR  ;
+    input  VGND  ;
+    input  VPB   ;
+    input  VNB   ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXTN_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__EINVN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__EINVN_FUNCTIONAL_PP_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__einvn (
+    Z   ,
+    A   ,
+    TE_B,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire pwrgood_pp0_out_A  ;
+    wire pwrgood_pp1_out_teb;
+
+    //                                 Name         Output               Other arguments
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A  , A, VPWR, VGND                         );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND                      );
+    notif0                             notif00     (Z                  , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EINVN_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SEDFXBP_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__SEDFXBP_BEHAVIORAL_V
+
+/**
+ * sedfxbp: Scan delay flop, data enable, non-inverted clock,
+ *          complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+`include ""../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__sedfxbp (
+    Q  ,
+    Q_N,
+    CLK,
+    D  ,
+    DE ,
+    SCD,
+    SCE
+);
+
+    // Module ports
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+    input  SCD;
+    input  SCE;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q      ;
+    reg  notifier   ;
+    wire D_delayed  ;
+    wire DE_delayed ;
+    wire SCD_delayed;
+    wire SCE_delayed;
+    wire CLK_delayed;
+    wire mux_out    ;
+    wire de_d       ;
+    wire awake      ;
+    wire cond1      ;
+    wire cond2      ;
+    wire cond3      ;
+
+    //                                 Name       Output   Other arguments
+    sky130_fd_sc_ls__udp_mux_2to1      mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed            );
+    sky130_fd_sc_ls__udp_mux_2to1      mux_2to11 (de_d   , buf_Q, D_delayed, DE_delayed              );
+    sky130_fd_sc_ls__udp_dff$P_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    assign cond1 = ( awake && ( SCE_delayed === 1\'b0 ) && ( DE_delayed === 1\'b1 ) );
+    assign cond2 = ( awake && ( SCE_delayed === 1\'b1 ) );
+    assign cond3 = ( awake && ( DE_delayed === 1\'b1 ) && ( D_delayed !== SCD_delayed ) );
+    buf                                buf0      (Q      , buf_Q                                     );
+    not                                not0      (Q_N    , buf_Q                                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SEDFXBP_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR4BB_SYMBOL_V
+`define SKY130_FD_SC_LS__NOR4BB_SYMBOL_V
+
+/**
+ * nor4bb: 4-input NOR, first two inputs inverted.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nor4bb (
+    //# {{data|Data Signals}}
+    input  A  ,
+    input  B  ,
+    input  C_N,
+    input  D_N,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR4BB_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__BUFINV_TB_V
+`define SKY130_FD_SC_LS__BUFINV_TB_V
+
+/**
+ * bufinv: Buffer followed by inverter.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__bufinv.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   VGND = 1\'b0;
+        #60   VNB  = 1\'b0;
+        #80   VPB  = 1\'b0;
+        #100  VPWR = 1\'b0;
+        #120  A    = 1\'b1;
+        #140  VGND = 1\'b1;
+        #160  VNB  = 1\'b1;
+        #180  VPB  = 1\'b1;
+        #200  VPWR = 1\'b1;
+        #220  A    = 1\'b0;
+        #240  VGND = 1\'b0;
+        #260  VNB  = 1\'b0;
+        #280  VPB  = 1\'b0;
+        #300  VPWR = 1\'b0;
+        #320  VPWR = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VNB  = 1\'b1;
+        #380  VGND = 1\'b1;
+        #400  A    = 1\'b1;
+        #420  VPWR = 1\'bx;
+        #440  VPB  = 1\'bx;
+        #460  VNB  = 1\'bx;
+        #480  VGND = 1\'bx;
+        #500  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__bufinv dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__BUFINV_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A22OI_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__A22OI_PP_SYMBOL_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a22oi (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  B1  ,
+    input  B2  ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A22OI_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SDFRBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__SDFRBP_FUNCTIONAL_PP_V
+
+/**
+ * sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v""
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+
+`celldefine
+module sky130_fd_sc_ls__sdfrbp (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire buf_Q  ;
+    wire RESET  ;
+    wire mux_out;
+
+    //                                  Delay       Name       Output   Other arguments
+    not                                             not0      (RESET  , RESET_B                          );
+    sky130_fd_sc_ls__udp_mux_2to1                   mux_2to10 (mux_out, D, SCD, SCE                      );
+    sky130_fd_sc_ls__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK, RESET, , VPWR, VGND);
+    buf                                             buf0      (Q      , buf_Q                            );
+    not                                             not1      (Q_N    , buf_Q                            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFRBP_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A2BB2OI_V
+`define SKY130_FD_SC_LS__A2BB2OI_V
+
+/**
+ * a2bb2oi: 2-input AND, both inputs inverted, into first input, and
+ *          2-input AND into 2nd input of 2-input NOR.
+ *
+ *          Y = !((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a2bb2oi.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a2bb2oi.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a2bb2oi.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a2bb2oi.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2BB2OI_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND2_4_V
+`define SKY130_FD_SC_LS__AND2_4_V
+
+/**
+ * and2: 2-input AND.
+ *
+ * Verilog wrapper for and2 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__and2.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__and2_4 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__and2 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__and2_4 (
+    X,
+    A,
+    B
+);
+
+    output X;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__and2 base (
+        .X(X),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND2_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD3_SYMBOL_V
+`define SKY130_FD_SC_LS__CLKDLYINV5SD3_SYMBOL_V
+
+/**
+ * clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
+ *                stage gate.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__clkdlyinv5sd3 (
+    //# {{data|Data Signals}}
+    input  A,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV5SD3_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND3B_4_V
+`define SKY130_FD_SC_LS__NAND3B_4_V
+
+/**
+ * nand3b: 3-input NAND, first input inverted.
+ *
+ * Verilog wrapper for nand3b with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nand3b.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nand3b_4 (
+    Y   ,
+    A_N ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nand3b base (
+        .Y(Y),
+        .A_N(A_N),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nand3b_4 (
+    Y  ,
+    A_N,
+    B  ,
+    C
+);
+
+    output Y  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nand3b base (
+        .Y(Y),
+        .A_N(A_N),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND3B_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFRTN_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__DFRTN_PP_BLACKBOX_V
+
+/**
+ * dfrtn: Delay flop, inverted reset, inverted clock,
+ *        complementary outputs.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dfrtn (
+    Q      ,
+    CLK_N  ,
+    D      ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    input  CLK_N  ;
+    input  D      ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFRTN_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND3B_BLACKBOX_V
+`define SKY130_FD_SC_LS__NAND3B_BLACKBOX_V
+
+/**
+ * nand3b: 3-input NAND, first input inverted.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nand3b (
+    Y  ,
+    A_N,
+    B  ,
+    C
+);
+
+    output Y  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND3B_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DECAP_TB_V
+`define SKY130_FD_SC_LS__DECAP_TB_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__decap.v""
+
+module top();
+
+    // Inputs are registered
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   VGND = 1\'b0;
+        #40   VNB  = 1\'b0;
+        #60   VPB  = 1\'b0;
+        #80   VPWR = 1\'b0;
+        #100  VGND = 1\'b1;
+        #120  VNB  = 1\'b1;
+        #140  VPB  = 1\'b1;
+        #160  VPWR = 1\'b1;
+        #180  VGND = 1\'b0;
+        #200  VNB  = 1\'b0;
+        #220  VPB  = 1\'b0;
+        #240  VPWR = 1\'b0;
+        #260  VPWR = 1\'b1;
+        #280  VPB  = 1\'b1;
+        #300  VNB  = 1\'b1;
+        #320  VGND = 1\'b1;
+        #340  VPWR = 1\'bx;
+        #360  VPB  = 1\'bx;
+        #380  VNB  = 1\'bx;
+        #400  VGND = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__decap dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DECAP_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__XNOR2_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__XNOR2_PP_SYMBOL_V
+
+/**
+ * xnor2: 2-input exclusive NOR.
+ *
+ *        Y = !(A ^ B)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__xnor2 (
+    //# {{data|Data Signals}}
+    input  A   ,
+    input  B   ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XNOR2_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND2B_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__NAND2B_PP_BLACKBOX_V
+
+/**
+ * nand2b: 2-input NAND, first input inverted.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nand2b (
+    Y   ,
+    A_N ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A_N ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND2B_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__BUF_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__BUF_BEHAVIORAL_PP_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__buf (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__BUF_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O32A_SYMBOL_V
+`define SKY130_FD_SC_LS__O32A_SYMBOL_V
+
+/**
+ * o32a: 3-input OR and 2-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o32a (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  A3,
+    input  B1,
+    input  B2,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O32A_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD3_TB_V
+`define SKY130_FD_SC_LS__CLKDLYINV5SD3_TB_V
+
+/**
+ * clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
+ *                stage gate.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__clkdlyinv5sd3.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   VGND = 1\'b0;
+        #60   VNB  = 1\'b0;
+        #80   VPB  = 1\'b0;
+        #100  VPWR = 1\'b0;
+        #120  A    = 1\'b1;
+        #140  VGND = 1\'b1;
+        #160  VNB  = 1\'b1;
+        #180  VPB  = 1\'b1;
+        #200  VPWR = 1\'b1;
+        #220  A    = 1\'b0;
+        #240  VGND = 1\'b0;
+        #260  VNB  = 1\'b0;
+        #280  VPB  = 1\'b0;
+        #300  VPWR = 1\'b0;
+        #320  VPWR = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VNB  = 1\'b1;
+        #380  VGND = 1\'b1;
+        #400  A    = 1\'b1;
+        #420  VPWR = 1\'bx;
+        #440  VPB  = 1\'bx;
+        #460  VNB  = 1\'bx;
+        #480  VGND = 1\'bx;
+        #500  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__clkdlyinv5sd3 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV5SD3_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if ((!A2&!A3&!B1&B2)) (A1 -=> Y) = (0:0:0,0:0:0);
+if ((!A2&!A3&B1&!B2)) (A1 -=> Y) = (0:0:0,0:0:0);
+if ((!A2&!A3&B1&B2)) (A1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A3&!B1&B2)) (A2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A3&B1&!B2)) (A2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A3&B1&B2)) (A2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&!B1&B2)) (A3 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&B1&!B2)) (A3 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&B1&B2)) (A3 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&!A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&!A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2&!A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2&A3&!B2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&!A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&!A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2&!A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2&A3&!B1)) (B2 -=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__XOR3_1_V
+`define SKY130_FD_SC_LS__XOR3_1_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ *       X = A ^ B ^ C
+ *
+ * Verilog wrapper for xor3 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__xor3.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__xor3_1 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__xor3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__xor3_1 (
+    X,
+    A,
+    B,
+    C
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__xor3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XOR3_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DLATCH_PR_SYMBOL_V
+`define SKY130_FD_SC_LS__UDP_DLATCH_PR_SYMBOL_V
+
+/**
+ * udp_dlatch$PR: D-latch, gated clear direct / gate active high
+ *                (Q output UDP)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__udp_dlatch$PR (
+    //# {{data|Data Signals}}
+    input  D    ,
+    output Q    ,
+
+    //# {{control|Control Signals}}
+    input  RESET,
+
+    //# {{clocks|Clocking}}
+    input  GATE
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DLATCH_PR_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+( negedge RESET_B => ( Q +: RESET_B ) ) = 0:0:0 ;   // delay is tfall
+( negedge RESET_B => ( Q_N -: RESET_B ) ) = 0:0:0 ;  // delay is tris
+( SET_B => ( Q -: SET_B ) ) = ( 0:0:0 , 0:0:0 ) ;       // delay is tris , tfall
+( SET_B => ( Q_N +: SET_B ) ) = ( 0:0:0 , 0:0:0 ) ;      // delay is tris , tfall
+( negedge CLK_N => ( Q +: D ) ) = ( 0:0:0 , 0:0:0 ) ;  // delays are tris , tfall
+( negedge CLK_N => ( Q_N -: D ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall
+$recrem ( posedge SET_B , negedge CLK_N , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , SETB_delayed , CLKN_delayed ) ;
+$recrem ( posedge RESET_B , negedge CLK_N , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , RESETB_delayed , CLKN_delayed ) ;
+$setuphold ( negedge CLK_N , posedge D , 0:0:0 , 0:0:0 , notifier , COND_D , COND_D , CLKN_delayed , D_delayed ) ;
+$setuphold ( negedge CLK_N , negedge D , 0:0:0 , 0:0:0 , notifier , COND_D , COND_D , CLKN_delayed , D_delayed ) ;
+$setuphold ( negedge CLK_N , posedge SCD , 0:0:0 , 0:0:0 , notifier , COND_SCD , COND_SCD , CLKN_delayed , SCD_delayed ) ;
+$setuphold ( negedge CLK_N , negedge SCD , 0:0:0 , 0:0:0 , notifier , COND_SCD , COND_SCD , CLKN_delayed , SCD_delayed ) ;
+$setuphold ( negedge CLK_N , posedge SCE , 0:0:0 , 0:0:0 , notifier , COND_SCE , COND_SCE , CLKN_delayed , SCE_delayed ) ;
+$setuphold ( negedge CLK_N , negedge SCE , 0:0:0 , 0:0:0 , notifier , COND_SCE , COND_SCE , CLKN_delayed , SCE_delayed ) ;
+$hold ( posedge SET_B &&& AWAKE , posedge RESET_B &&& AWAKE , 3.0:3.0:3.0 , notifier ) ; //arbitrary , uncharacterized value to
+//flag possible state error
+$hold ( posedge RESET_B &&& AWAKE , posedge SET_B &&& AWAKE , 3.0:3.0:3.0 , notifier ) ; //arbitrary , uncharacterized value to
+//flag possible state error
+$width ( negedge CLK_N &&& CONDB , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( posedge CLK_N &&& CONDB , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( negedge SET_B &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( negedge RESET_B &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DFRTN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__DFRTN_FUNCTIONAL_PP_V
+
+/**
+ * dfrtn: Delay flop, inverted reset, inverted clock,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dfrtn (
+    Q      ,
+    CLK_N  ,
+    D      ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    input  CLK_N  ;
+    input  D      ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire buf_Q ;
+    wire RESET ;
+    wire intclk;
+
+    //                                  Delay       Name  Output  Other arguments
+    not                                             not0 (RESET , RESET_B                       );
+    not                                             not1 (intclk, CLK_N                         );
+    sky130_fd_sc_ls__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, intclk, RESET, , VPWR, VGND);
+    buf                                             buf0 (Q     , buf_Q                         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFRTN_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DFBBP_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__DFBBP_FUNCTIONAL_V
+
+/**
+ * dfbbp: Delay flop, inverted set, inverted reset,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_nsr/sky130_fd_sc_ls__udp_dff_nsr.v""
+
+`celldefine
+module sky130_fd_sc_ls__dfbbp (
+    Q      ,
+    Q_N    ,
+    D      ,
+    CLK    ,
+    SET_B  ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  CLK    ;
+    input  SET_B  ;
+    input  RESET_B;
+
+    // Local signals
+    wire RESET;
+    wire SET  ;
+    wire buf_Q;
+
+    //                           Delay       Name  Output  Other arguments
+    not                                      not0 (RESET , RESET_B           );
+    not                                      not1 (SET   , SET_B             );
+    sky130_fd_sc_ls__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D);
+    buf                                      buf0 (Q     , buf_Q             );
+    not                                      not2 (Q_N   , buf_Q             );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFBBP_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFXBP_2_V
+`define SKY130_FD_SC_LS__DFXBP_2_V
+
+/**
+ * dfxbp: Delay flop, complementary outputs.
+ *
+ * Verilog wrapper for dfxbp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dfxbp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dfxbp_2 (
+    Q   ,
+    Q_N ,
+    CLK ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    output Q_N ;
+    input  CLK ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__dfxbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dfxbp_2 (
+    Q  ,
+    Q_N,
+    CLK,
+    D
+);
+
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__dfxbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFXBP_2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__EINVN_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__EINVN_BEHAVIORAL_PP_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__einvn (
+    Z   ,
+    A   ,
+    TE_B,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire pwrgood_pp0_out_A  ;
+    wire pwrgood_pp1_out_teb;
+
+    //                                 Name         Output               Other arguments
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A  , A, VPWR, VGND                         );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND                      );
+    notif0                             notif00     (Z                  , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EINVN_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DFRTN_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__DFRTN_BEHAVIORAL_V
+
+/**
+ * dfrtn: Delay flop, inverted reset, inverted clock,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dfrtn (
+    Q      ,
+    CLK_N  ,
+    D      ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    input  CLK_N  ;
+    input  D      ;
+    input  RESET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q          ;
+    wire RESET          ;
+    wire intclk         ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire RESET_B_delayed;
+    wire CLK_N_delayed  ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+
+    //                                  Name  Output  Other arguments
+    not                                 not0 (RESET , RESET_B_delayed                               );
+    not                                 not1 (intclk, CLK_N_delayed                                 );
+    sky130_fd_sc_ls__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, intclk, RESET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1\'b1 ) );
+    assign cond1 = ( awake && ( RESET_B === 1\'b1 ) );
+    buf                                 buf0 (Q     , buf_Q                                         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFRTN_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O2111A_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__O2111A_FUNCTIONAL_PP_V
+
+/**
+ * o2111a: 2-input OR into first input of 4-input AND.
+ *
+ *         X = ((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__o2111a (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1                );
+    and                                and0        (and0_out_X       , B1, C1, or0_out, D1   );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2111A_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A2BB2OI_TB_V
+`define SKY130_FD_SC_LS__A2BB2OI_TB_V
+
+/**
+ * a2bb2oi: 2-input AND, both inputs inverted, into first input, and
+ *          2-input AND into 2nd input of 2-input NOR.
+ *
+ *          Y = !((!A1 & !A2) | (B1 & B2))
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a2bb2oi.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1_N;
+    reg A2_N;
+    reg B1;
+    reg B2;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1_N = 1\'bX;
+        A2_N = 1\'bX;
+        B1   = 1\'bX;
+        B2   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1_N = 1\'b0;
+        #40   A2_N = 1\'b0;
+        #60   B1   = 1\'b0;
+        #80   B2   = 1\'b0;
+        #100  VGND = 1\'b0;
+        #120  VNB  = 1\'b0;
+        #140  VPB  = 1\'b0;
+        #160  VPWR = 1\'b0;
+        #180  A1_N = 1\'b1;
+        #200  A2_N = 1\'b1;
+        #220  B1   = 1\'b1;
+        #240  B2   = 1\'b1;
+        #260  VGND = 1\'b1;
+        #280  VNB  = 1\'b1;
+        #300  VPB  = 1\'b1;
+        #320  VPWR = 1\'b1;
+        #340  A1_N = 1\'b0;
+        #360  A2_N = 1\'b0;
+        #380  B1   = 1\'b0;
+        #400  B2   = 1\'b0;
+        #420  VGND = 1\'b0;
+        #440  VNB  = 1\'b0;
+        #460  VPB  = 1\'b0;
+        #480  VPWR = 1\'b0;
+        #500  VPWR = 1\'b1;
+        #520  VPB  = 1\'b1;
+        #540  VNB  = 1\'b1;
+        #560  VGND = 1\'b1;
+        #580  B2   = 1\'b1;
+        #600  B1   = 1\'b1;
+        #620  A2_N = 1\'b1;
+        #640  A1_N = 1\'b1;
+        #660  VPWR = 1\'bx;
+        #680  VPB  = 1\'bx;
+        #700  VNB  = 1\'bx;
+        #720  VGND = 1\'bx;
+        #740  B2   = 1\'bx;
+        #760  B1   = 1\'bx;
+        #780  A2_N = 1\'bx;
+        #800  A1_N = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__a2bb2oi dut (.A1_N(A1_N), .A2_N(A2_N), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2BB2OI_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O2111A_4_V
+`define SKY130_FD_SC_LS__O2111A_4_V
+
+/**
+ * o2111a: 2-input OR into first input of 4-input AND.
+ *
+ *         X = ((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog wrapper for o2111a with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o2111a.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o2111a_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o2111a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o2111a_4 (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o2111a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2111A_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFSTP_V
+`define SKY130_FD_SC_LS__DFSTP_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dfstp.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dfstp.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dfstp.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dfstp.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFSTP_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__TAPVGND2_SYMBOL_V
+`define SKY130_FD_SC_LS__TAPVGND2_SYMBOL_V
+
+/**
+ * tapvgnd2: Tap cell with tap to ground, isolated power connection
+ *           2 rows down.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__tapvgnd2 ();
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPVGND2_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDLCLKP_2_V
+`define SKY130_FD_SC_LS__SDLCLKP_2_V
+
+/**
+ * sdlclkp: Scan gated clock.
+ *
+ * Verilog wrapper for sdlclkp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__sdlclkp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sdlclkp_2 (
+    GCLK,
+    SCE ,
+    GATE,
+    CLK ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output GCLK;
+    input  SCE ;
+    input  GATE;
+    input  CLK ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__sdlclkp base (
+        .GCLK(GCLK),
+        .SCE(SCE),
+        .GATE(GATE),
+        .CLK(CLK),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sdlclkp_2 (
+    GCLK,
+    SCE ,
+    GATE,
+    CLK
+);
+
+    output GCLK;
+    input  SCE ;
+    input  GATE;
+    input  CLK ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__sdlclkp base (
+        .GCLK(GCLK),
+        .SCE(SCE),
+        .GATE(GATE),
+        .CLK(CLK)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDLCLKP_2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if ((A2_N&!B1&B2)) (A1_N +=> Y) = (0:0:0,0:0:0);
+if ((A2_N&B1&!B2)) (A1_N +=> Y) = (0:0:0,0:0:0);
+if ((A2_N&B1&B2)) (A1_N +=> Y) = (0:0:0,0:0:0);
+if ((A1_N&!B1&B2)) (A2_N +=> Y) = (0:0:0,0:0:0);
+if ((A1_N&B1&!B2)) (A2_N +=> Y) = (0:0:0,0:0:0);
+if ((A1_N&B1&B2)) (A2_N +=> Y) = (0:0:0,0:0:0);
+if ((!A1_N&!A2_N&!B2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1_N&A2_N&!B2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1_N&!A2_N&!B2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1_N&!A2_N&!B1)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1_N&A2_N&!B1)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((A1_N&!A2_N&!B1)) (B2 -=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A21BOI_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__A21BOI_PP_SYMBOL_V
+
+/**
+ * a21boi: 2-input AND into first input of 2-input NOR,
+ *         2nd input inverted.
+ *
+ *         Y = !((A1 & A2) | (!B1_N))
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a21boi (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  B1_N,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21BOI_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O31A_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__O31A_BEHAVIORAL_V
+
+/**
+ * o31a: 3-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__o31a (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out   ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    or  or0  (or0_out   , A2, A1, A3     );
+    and and0 (and0_out_X, or0_out, B1    );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O31A_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O311A_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__O311A_BEHAVIORAL_PP_V
+
+/**
+ * o311a: 3-input OR into 3-input AND.
+ *
+ *        X = ((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__o311a (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1, A3            );
+    and                                and0        (and0_out_X       , or0_out, B1, C1       );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O311A_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__MUX2_TB_V
+`define SKY130_FD_SC_LS__MUX2_TB_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__mux2.v""
+
+module top();
+
+    // Inputs are registered
+    reg A0;
+    reg A1;
+    reg S;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A0   = 1\'bX;
+        A1   = 1\'bX;
+        S    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A0   = 1\'b0;
+        #40   A1   = 1\'b0;
+        #60   S    = 1\'b0;
+        #80   VGND = 1\'b0;
+        #100  VNB  = 1\'b0;
+        #120  VPB  = 1\'b0;
+        #140  VPWR = 1\'b0;
+        #160  A0   = 1\'b1;
+        #180  A1   = 1\'b1;
+        #200  S    = 1\'b1;
+        #220  VGND = 1\'b1;
+        #240  VNB  = 1\'b1;
+        #260  VPB  = 1\'b1;
+        #280  VPWR = 1\'b1;
+        #300  A0   = 1\'b0;
+        #320  A1   = 1\'b0;
+        #340  S    = 1\'b0;
+        #360  VGND = 1\'b0;
+        #380  VNB  = 1\'b0;
+        #400  VPB  = 1\'b0;
+        #420  VPWR = 1\'b0;
+        #440  VPWR = 1\'b1;
+        #460  VPB  = 1\'b1;
+        #480  VNB  = 1\'b1;
+        #500  VGND = 1\'b1;
+        #520  S    = 1\'b1;
+        #540  A1   = 1\'b1;
+        #560  A0   = 1\'b1;
+        #580  VPWR = 1\'bx;
+        #600  VPB  = 1\'bx;
+        #620  VNB  = 1\'bx;
+        #640  VGND = 1\'bx;
+        #660  S    = 1\'bx;
+        #680  A1   = 1\'bx;
+        #700  A0   = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__mux2 dut (.A0(A0), .A1(A1), .S(S), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MUX2_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+( negedge RESET_B => ( Q +: RESET_B ) ) = ( 0:0:0 , 0:0:0 ) ;  // delay is tfall
+( D +=> Q ) = ( 0:0:0 , 0:0:0 ) ;  // delays are tris , tfall
+( negedge GATE_N => ( Q : GATE_N ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall
+$recrem ( posedge RESET_B , posedge GATE_N , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , RESETB_delayed , GATEN_delayed ) ;
+$setuphold ( posedge GATE_N , posedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , GATEN_delayed , D_delayed ) ;
+$setuphold ( posedge GATE_N , negedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , GATEN_delayed , D_delayed ) ;
+$width ( negedge GATE_N &&& COND1 , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( negedge RESET_B &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( posedge RESET_B &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__OR2B_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__OR2B_BEHAVIORAL_V
+
+/**
+ * or2b: 2-input OR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__or2b (
+    X  ,
+    A  ,
+    B_N
+);
+
+    // Module ports
+    output X  ;
+    input  A  ;
+    input  B_N;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    not not0 (not0_out , B_N            );
+    or  or0  (or0_out_X, not0_out, A    );
+    buf buf0 (X        , or0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR2B_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A +=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DFSTP_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__DFSTP_BEHAVIORAL_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ls__udp_dff_ps_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dfstp (
+    Q    ,
+    CLK  ,
+    D    ,
+    SET_B
+);
+
+    // Module ports
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q        ;
+    wire SET          ;
+    reg  notifier     ;
+    wire D_delayed    ;
+    wire SET_B_delayed;
+    wire CLK_delayed  ;
+    wire awake        ;
+    wire cond0        ;
+    wire cond1        ;
+
+    //                                  Name  Output  Other arguments
+    not                                 not0 (SET   , SET_B_delayed                                    );
+    sky130_fd_sc_ls__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    assign cond0 = ( SET_B_delayed === 1\'b1 );
+    assign cond1 = ( SET_B === 1\'b1 );
+    buf                                 buf0 (Q     , buf_Q                                            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFSTP_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFRTN_1_V
+`define SKY130_FD_SC_LS__SDFRTN_1_V
+
+/**
+ * sdfrtn: Scan delay flop, inverted reset, inverted clock,
+ *         single output.
+ *
+ * Verilog wrapper for sdfrtn with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__sdfrtn.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sdfrtn_1 (
+    Q      ,
+    CLK_N  ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    input  CLK_N  ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_ls__sdfrtn base (
+        .Q(Q),
+        .CLK_N(CLK_N),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .RESET_B(RESET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sdfrtn_1 (
+    Q      ,
+    CLK_N  ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B
+);
+
+    output Q      ;
+    input  CLK_N  ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__sdfrtn base (
+        .Q(Q),
+        .CLK_N(CLK_N),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .RESET_B(RESET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFRTN_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__TAPVPWRVGND_BLACKBOX_V
+`define SKY130_FD_SC_LS__TAPVPWRVGND_BLACKBOX_V
+
+/**
+ * tapvpwrvgnd: Substrate and well tap cell.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__tapvpwrvgnd ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPVPWRVGND_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A31O_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__A31O_BEHAVIORAL_PP_V
+
+/**
+ * a31o: 3-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a31o (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A3, A1, A2           );
+    or                                 or0         (or0_out_X        , and0_out, B1         );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A31O_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__OR4BB_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__OR4BB_FUNCTIONAL_V
+
+/**
+ * or4bb: 4-input OR, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__or4bb (
+    X  ,
+    A  ,
+    B  ,
+    C_N,
+    D_N
+);
+
+    // Module ports
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+    input  D_N;
+
+    // Local signals
+    wire nand0_out;
+    wire or0_out_X;
+
+    //   Name   Output     Other arguments
+    nand nand0 (nand0_out, D_N, C_N       );
+    or   or0   (or0_out_X, B, A, nand0_out);
+    buf  buf0  (X        , or0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR4BB_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A21OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__A21OI_FUNCTIONAL_PP_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a21oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A1, A2                );
+    nor                                nor0        (nor0_out_Y       , B1, and0_out          );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21OI_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLYGATE4SD2_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__DLYGATE4SD2_BEHAVIORAL_PP_V
+
+/**
+ * dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlygate4sd2 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYGATE4SD2_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O211AI_2_V
+`define SKY130_FD_SC_LS__O211AI_2_V
+
+/**
+ * o211ai: 2-input OR into first input of 3-input NAND.
+ *
+ *         Y = !((A1 | A2) & B1 & C1)
+ *
+ * Verilog wrapper for o211ai with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o211ai.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o211ai_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o211ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o211ai_2 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o211ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O211AI_2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__FAHCON_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__FAHCON_BEHAVIORAL_PP_V
+
+/**
+ * fahcon: Full adder, inverted carry in, inverted carry out.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__fahcon (
+    COUT_N,
+    SUM   ,
+    A     ,
+    B     ,
+    CI    ,
+    VPWR  ,
+    VGND  ,
+    VPB   ,
+    VNB
+);
+
+    // Module ports
+    output COUT_N;
+    output SUM   ;
+    input  A     ;
+    input  B     ;
+    input  CI    ;
+    input  VPWR  ;
+    input  VGND  ;
+    input  VPB   ;
+    input  VNB   ;
+
+    // Local signals
+    wire xor0_out_SUM         ;
+    wire pwrgood_pp0_out_SUM  ;
+    wire a_b                  ;
+    wire a_ci                 ;
+    wire b_ci                 ;
+    wire or0_out_coutn        ;
+    wire pwrgood_pp1_out_coutn;
+
+    //                                 Name         Output                 Other arguments
+    xor                                xor0        (xor0_out_SUM         , A, B, CI                 );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM  , xor0_out_SUM, VPWR, VGND );
+    buf                                buf0        (SUM                  , pwrgood_pp0_out_SUM      );
+    nor                                nor0        (a_b                  , A, B                     );
+    nor                                nor1        (a_ci                 , A, CI                    );
+    nor                                nor2        (b_ci                 , B, CI                    );
+    or                                 or0         (or0_out_coutn        , a_b, a_ci, b_ci          );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_coutn, or0_out_coutn, VPWR, VGND);
+    buf                                buf1        (COUT_N               , pwrgood_pp1_out_coutn    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FAHCON_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND4B_2_V
+`define SKY130_FD_SC_LS__NAND4B_2_V
+
+/**
+ * nand4b: 4-input NAND, first input inverted.
+ *
+ * Verilog wrapper for nand4b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nand4b.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nand4b_2 (
+    Y   ,
+    A_N ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nand4b base (
+        .Y(Y),
+        .A_N(A_N),
+        .B(B),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nand4b_2 (
+    Y  ,
+    A_N,
+    B  ,
+    C  ,
+    D
+);
+
+    output Y  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nand4b base (
+        .Y(Y),
+        .A_N(A_N),
+        .B(B),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND4B_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DFF_P_PP_PG_N_BLACKBOX_V
+`define SKY130_FD_SC_LS__UDP_DFF_P_PP_PG_N_BLACKBOX_V
+
+/**
+ * udp_dff$P_pp$PG$N: Positive edge triggered D flip-flop
+ *                    (Q output UDP).
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__udp_dff$P_pp$PG$N (
+    Q       ,
+    D       ,
+    CLK     ,
+    NOTIFIER,
+    VPWR    ,
+    VGND
+);
+
+    output Q       ;
+    input  D       ;
+    input  CLK     ;
+    input  NOTIFIER;
+    input  VPWR    ;
+    input  VGND    ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DFF_P_PP_PG_N_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__EDFXBP_V
+`define SKY130_FD_SC_LS__EDFXBP_V
+
+/**
+ * edfxbp: Delay flop with loopback enable, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__edfxbp.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__edfxbp.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__edfxbp.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__edfxbp.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EDFXBP_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKINV_16_V
+`define SKY130_FD_SC_LS__CLKINV_16_V
+
+/**
+ * clkinv: Clock tree inverter.
+ *
+ * Verilog wrapper for clkinv with size of 16 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__clkinv.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__clkinv_16 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__clkinv base (
+        .Y(Y),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__clkinv_16 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__clkinv base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKINV_16_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__EDFXBP_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__EDFXBP_FUNCTIONAL_V
+
+/**
+ * edfxbp: Delay flop with loopback enable, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+`include ""../../models/udp_dff_p/sky130_fd_sc_ls__udp_dff_p.v""
+
+`celldefine
+module sky130_fd_sc_ls__edfxbp (
+    Q  ,
+    Q_N,
+    CLK,
+    D  ,
+    DE
+);
+
+    // Module ports
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+
+    // Local signals
+    wire buf_Q  ;
+    wire mux_out;
+
+    //                            Delay       Name       Output   Other arguments
+    sky130_fd_sc_ls__udp_mux_2to1             mux_2to10 (mux_out, buf_Q, D, DE   );
+    sky130_fd_sc_ls__udp_dff$P    `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK   );
+    buf                                       buf0      (Q      , buf_Q          );
+    not                                       not0      (Q_N    , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EDFXBP_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD2_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__CLKDLYINV5SD2_FUNCTIONAL_PP_V
+
+/**
+ * clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
+ *                stage gate.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__clkdlyinv5sd2 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out_Y       , A                     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV5SD2_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__EINVN_4_V
+`define SKY130_FD_SC_LS__EINVN_4_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog wrapper for einvn with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__einvn.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__einvn_4 (
+    Z   ,
+    A   ,
+    TE_B,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__einvn base (
+        .Z(Z),
+        .A(A),
+        .TE_B(TE_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__einvn_4 (
+    Z   ,
+    A   ,
+    TE_B
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__einvn base (
+        .Z(Z),
+        .A(A),
+        .TE_B(TE_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EINVN_4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O21BA_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__O21BA_FUNCTIONAL_PP_V
+
+/**
+ * o21ba: 2-input OR into first input of 2-input AND,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 | A2) & !B1_N)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__o21ba (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nor0_out         ;
+    wire nor1_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    nor                                nor0        (nor0_out         , A1, A2                );
+    nor                                nor1        (nor1_out_X       , B1_N, nor0_out        );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nor1_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21BA_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A21BOI_TB_V
+`define SKY130_FD_SC_LS__A21BOI_TB_V
+
+/**
+ * a21boi: 2-input AND into first input of 2-input NOR,
+ *         2nd input inverted.
+ *
+ *         Y = !((A1 & A2) | (!B1_N))
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a21boi.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg B1_N;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        B1_N = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   B1_N = 1\'b0;
+        #80   VGND = 1\'b0;
+        #100  VNB  = 1\'b0;
+        #120  VPB  = 1\'b0;
+        #140  VPWR = 1\'b0;
+        #160  A1   = 1\'b1;
+        #180  A2   = 1\'b1;
+        #200  B1_N = 1\'b1;
+        #220  VGND = 1\'b1;
+        #240  VNB  = 1\'b1;
+        #260  VPB  = 1\'b1;
+        #280  VPWR = 1\'b1;
+        #300  A1   = 1\'b0;
+        #320  A2   = 1\'b0;
+        #340  B1_N = 1\'b0;
+        #360  VGND = 1\'b0;
+        #380  VNB  = 1\'b0;
+        #400  VPB  = 1\'b0;
+        #420  VPWR = 1\'b0;
+        #440  VPWR = 1\'b1;
+        #460  VPB  = 1\'b1;
+        #480  VNB  = 1\'b1;
+        #500  VGND = 1\'b1;
+        #520  B1_N = 1\'b1;
+        #540  A2   = 1\'b1;
+        #560  A1   = 1\'b1;
+        #580  VPWR = 1\'bx;
+        #600  VPB  = 1\'bx;
+        #620  VNB  = 1\'bx;
+        #640  VGND = 1\'bx;
+        #660  B1_N = 1\'bx;
+        #680  A2   = 1\'bx;
+        #700  A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__a21boi dut (.A1(A1), .A2(A2), .B1_N(B1_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21BOI_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+( negedge RESET_B => ( Q +: RESET_B ) ) = 0:0:0 ;  // delay is tris
+( posedge CLK => ( Q : CLK ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall
+$recrem ( posedge RESET_B , posedge CLK , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , RESETB_delayed , CLK_delayed ) ;
+$setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , CLK_delayed , D_delayed ) ;
+$setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , CLK_delayed , D_delayed ) ;
+$width ( posedge CLK &&& COND1 , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( negedge CLK &&& COND1 , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( negedge RESET_B &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DFRTN_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__DFRTN_FUNCTIONAL_V
+
+/**
+ * dfrtn: Delay flop, inverted reset, inverted clock,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_pr/sky130_fd_sc_ls__udp_dff_pr.v""
+
+`celldefine
+module sky130_fd_sc_ls__dfrtn (
+    Q      ,
+    CLK_N  ,
+    D      ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    input  CLK_N  ;
+    input  D      ;
+    input  RESET_B;
+
+    // Local signals
+    wire buf_Q ;
+    wire RESET ;
+    wire intclk;
+
+    //                          Delay       Name  Output  Other arguments
+    not                                     not0 (RESET , RESET_B         );
+    not                                     not1 (intclk, CLK_N           );
+    sky130_fd_sc_ls__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, intclk, RESET);
+    buf                                     buf0 (Q     , buf_Q           );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFRTN_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__MUX2_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__MUX2_FUNCTIONAL_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+
+`celldefine
+module sky130_fd_sc_ls__mux2 (
+    X ,
+    A0,
+    A1,
+    S
+);
+
+    // Module ports
+    output X ;
+    input  A0;
+    input  A1;
+    input  S ;
+
+    // Local signals
+    wire mux_2to10_out_X;
+
+    //                            Name       Output           Other arguments
+    sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_2to10_out_X, A0, A1, S      );
+    buf                           buf0      (X              , mux_2to10_out_X);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MUX2_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__XNOR2_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__XNOR2_PP_BLACKBOX_V
+
+/**
+ * xnor2: 2-input exclusive NOR.
+ *
+ *        Y = !(A ^ B)
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__xnor2 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XNOR2_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND3_2_V
+`define SKY130_FD_SC_LS__NAND3_2_V
+
+/**
+ * nand3: 3-input NAND.
+ *
+ * Verilog wrapper for nand3 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nand3.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nand3_2 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nand3 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nand3_2 (
+    Y,
+    A,
+    B,
+    C
+);
+
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nand3 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND3_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SEDFXBP_1_V
+`define SKY130_FD_SC_LS__SEDFXBP_1_V
+
+/**
+ * sedfxbp: Scan delay flop, data enable, non-inverted clock,
+ *          complementary outputs.
+ *
+ * Verilog wrapper for sedfxbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__sedfxbp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sedfxbp_1 (
+    Q   ,
+    Q_N ,
+    CLK ,
+    D   ,
+    DE  ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    output Q_N ;
+    input  CLK ;
+    input  D   ;
+    input  DE  ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__sedfxbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .DE(DE),
+        .SCD(SCD),
+        .SCE(SCE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sedfxbp_1 (
+    Q  ,
+    Q_N,
+    CLK,
+    D  ,
+    DE ,
+    SCD,
+    SCE
+);
+
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+    input  SCD;
+    input  SCE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__sedfxbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .DE(DE),
+        .SCD(SCD),
+        .SCE(SCE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SEDFXBP_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLRTN_TB_V
+`define SKY130_FD_SC_LS__DLRTN_TB_V
+
+/**
+ * dlrtn: Delay latch, inverted reset, inverted enable, single output.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dlrtn.v""
+
+module top();
+
+    // Inputs are registered
+    reg RESET_B;
+    reg D;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Q;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D       = 1\'bX;
+        RESET_B = 1\'bX;
+        VGND    = 1\'bX;
+        VNB     = 1\'bX;
+        VPB     = 1\'bX;
+        VPWR    = 1\'bX;
+
+        #20   D       = 1\'b0;
+        #40   RESET_B = 1\'b0;
+        #60   VGND    = 1\'b0;
+        #80   VNB     = 1\'b0;
+        #100  VPB     = 1\'b0;
+        #120  VPWR    = 1\'b0;
+        #140  D       = 1\'b1;
+        #160  RESET_B = 1\'b1;
+        #180  VGND    = 1\'b1;
+        #200  VNB     = 1\'b1;
+        #220  VPB     = 1\'b1;
+        #240  VPWR    = 1\'b1;
+        #260  D       = 1\'b0;
+        #280  RESET_B = 1\'b0;
+        #300  VGND    = 1\'b0;
+        #320  VNB     = 1\'b0;
+        #340  VPB     = 1\'b0;
+        #360  VPWR    = 1\'b0;
+        #380  VPWR    = 1\'b1;
+        #400  VPB     = 1\'b1;
+        #420  VNB     = 1\'b1;
+        #440  VGND    = 1\'b1;
+        #460  RESET_B = 1\'b1;
+        #480  D       = 1\'b1;
+        #500  VPWR    = 1\'bx;
+        #520  VPB     = 1\'bx;
+        #540  VNB     = 1\'bx;
+        #560  VGND    = 1\'bx;
+        #580  RESET_B = 1\'bx;
+        #600  D       = 1\'bx;
+    end
+
+    // Create a clock
+    reg GATE_N;
+    initial
+    begin
+        GATE_N = 1\'b0;
+    end
+
+    always
+    begin
+        #5 GATE_N = ~GATE_N;
+    end
+
+    sky130_fd_sc_ls__dlrtn dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .GATE_N(GATE_N));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRTN_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFBBN_BLACKBOX_V
+`define SKY130_FD_SC_LS__DFBBN_BLACKBOX_V
+
+/**
+ * dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
+ *        complementary outputs.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dfbbn (
+    Q      ,
+    Q_N    ,
+    D      ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFBBN_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLRBN_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__DLRBN_FUNCTIONAL_V
+
+/**
+ * dlrbn: Delay latch, inverted reset, inverted enable,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_pr/sky130_fd_sc_ls__udp_dlatch_pr.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlrbn (
+    Q      ,
+    Q_N    ,
+    RESET_B,
+    D      ,
+    GATE_N
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE_N ;
+
+    // Local signals
+    wire RESET  ;
+    wire intgate;
+    wire buf_Q  ;
+
+    //                             Delay       Name     Output   Other arguments
+    not                                        not0    (RESET  , RESET_B          );
+    not                                        not1    (intgate, GATE_N           );
+    sky130_fd_sc_ls__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q  , D, intgate, RESET);
+    buf                                        buf0    (Q      , buf_Q            );
+    not                                        not2    (Q_N    , buf_Q            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRBN_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLRTP_4_V
+`define SKY130_FD_SC_LS__DLRTP_4_V
+
+/**
+ * dlrtp: Delay latch, inverted reset, non-inverted enable,
+ *        single output.
+ *
+ * Verilog wrapper for dlrtp with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dlrtp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dlrtp_4 (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE   ,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_ls__dlrtp base (
+        .Q(Q),
+        .RESET_B(RESET_B),
+        .D(D),
+        .GATE(GATE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dlrtp_4 (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE
+);
+
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__dlrtp base (
+        .Q(Q),
+        .RESET_B(RESET_B),
+        .D(D),
+        .GATE(GATE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRTP_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLXBN_SYMBOL_V
+`define SKY130_FD_SC_LS__DLXBN_SYMBOL_V
+
+/**
+ * dlxbn: Delay latch, inverted enable, complementary outputs.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlxbn (
+    //# {{data|Data Signals}}
+    input  D     ,
+    output Q     ,
+    output Q_N   ,
+
+    //# {{clocks|Clocking}}
+    input  GATE_N
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXBN_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND4B_4_V
+`define SKY130_FD_SC_LS__NAND4B_4_V
+
+/**
+ * nand4b: 4-input NAND, first input inverted.
+ *
+ * Verilog wrapper for nand4b with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nand4b.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nand4b_4 (
+    Y   ,
+    A_N ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nand4b base (
+        .Y(Y),
+        .A_N(A_N),
+        .B(B),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nand4b_4 (
+    Y  ,
+    A_N,
+    B  ,
+    C  ,
+    D
+);
+
+    output Y  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nand4b base (
+        .Y(Y),
+        .A_N(A_N),
+        .B(B),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND4B_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FILL_DIODE_SYMBOL_V
+`define SKY130_FD_SC_LS__FILL_DIODE_SYMBOL_V
+
+/**
+ * fill_diode: Fill diode.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__fill_diode ();
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FILL_DIODE_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFRTP_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__DFRTP_PP_SYMBOL_V
+
+/**
+ * dfrtp: Delay flop, inverted reset, single output.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dfrtp (
+    //# {{data|Data Signals}}
+    input  D      ,
+    output Q      ,
+
+    //# {{control|Control Signals}}
+    input  RESET_B,
+
+    //# {{clocks|Clocking}}
+    input  CLK    ,
+
+    //# {{power|Power}}
+    input  VPB    ,
+    input  VPWR   ,
+    input  VGND   ,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFRTP_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD1_TB_V
+`define SKY130_FD_SC_LS__CLKDLYINV5SD1_TB_V
+
+/**
+ * clkdlyinv5sd1: Clock Delay Inverter 5-stage 0.15um length inner
+ *                stage gate.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__clkdlyinv5sd1.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   VGND = 1\'b0;
+        #60   VNB  = 1\'b0;
+        #80   VPB  = 1\'b0;
+        #100  VPWR = 1\'b0;
+        #120  A    = 1\'b1;
+        #140  VGND = 1\'b1;
+        #160  VNB  = 1\'b1;
+        #180  VPB  = 1\'b1;
+        #200  VPWR = 1\'b1;
+        #220  A    = 1\'b0;
+        #240  VGND = 1\'b0;
+        #260  VNB  = 1\'b0;
+        #280  VPB  = 1\'b0;
+        #300  VPWR = 1\'b0;
+        #320  VPWR = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VNB  = 1\'b1;
+        #380  VGND = 1\'b1;
+        #400  A    = 1\'b1;
+        #420  VPWR = 1\'bx;
+        #440  VPB  = 1\'bx;
+        #460  VNB  = 1\'bx;
+        #480  VGND = 1\'bx;
+        #500  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__clkdlyinv5sd1 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV5SD1_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A31OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__A31OI_FUNCTIONAL_PP_V
+
+/**
+ * a31oi: 3-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a31oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A3, A1, A2            );
+    nor                                nor0        (nor0_out_Y       , B1, and0_out          );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A31OI_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DECAP_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__DECAP_PP_SYMBOL_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__decap (
+    //# {{power|Power}}
+    input VPB ,
+    input VPWR,
+    input VGND,
+    input VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DECAP_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DFXTP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__DFXTP_FUNCTIONAL_PP_V
+
+/**
+ * dfxtp: Delay flop, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dfxtp (
+    Q   ,
+    CLK ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q;
+
+    //                                 Delay       Name  Output  Other arguments
+    sky130_fd_sc_ls__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND);
+    buf                                            buf0 (Q     , buf_Q               );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFXTP_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__EBUFN_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__EBUFN_BEHAVIORAL_PP_V
+
+/**
+ * ebufn: Tri-state buffer, negative enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__ebufn (
+    Z   ,
+    A   ,
+    TE_B,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire pwrgood_pp0_out_A  ;
+    wire pwrgood_pp1_out_teb;
+
+    //                                 Name         Output               Other arguments
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A  , A, VPWR, VGND                         );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND                      );
+    bufif0                             bufif00     (Z                  , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EBUFN_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__MUX2I_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__MUX2I_BEHAVIORAL_PP_V
+
+/**
+ * mux2i: 2-input multiplexer, output inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1_n/sky130_fd_sc_ls__udp_mux_2to1_n.v""
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__mux2i (
+    Y   ,
+    A0  ,
+    A1  ,
+    S   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A0  ;
+    input  A1  ;
+    input  S   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire mux_2to1_n0_out_Y;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    sky130_fd_sc_ls__udp_mux_2to1_N    mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S                    );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, mux_2to1_n0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MUX2I_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A211O_2_V
+`define SKY130_FD_SC_LS__A211O_2_V
+
+/**
+ * a211o: 2-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2) | B1 | C1)
+ *
+ * Verilog wrapper for a211o with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a211o.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a211o_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a211o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a211o_2 (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a211o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A211O_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__MUX4_V
+`define SKY130_FD_SC_LS__MUX4_V
+
+/**
+ * mux4: 4-input multiplexer.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__mux4.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__mux4.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__mux4.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__mux4.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MUX4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__TAPVGNDNOVPB_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__TAPVGNDNOVPB_FUNCTIONAL_V
+
+/**
+ * tapvgndnovpb: Substrate only tap cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__tapvgndnovpb ();
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPVGNDNOVPB_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+( posedge CLK => ( Q : CLK ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall
+$setuphold ( posedge CLK , posedge DE , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , CLK_delayed , DE_delayed ) ;
+$setuphold ( posedge CLK , negedge DE , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , CLK_delayed , DE_delayed ) ;
+$setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ;
+$setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ;
+$setuphold ( posedge CLK , posedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ;
+$setuphold ( posedge CLK , negedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ;
+$setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ;
+$setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ;
+$width ( posedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( negedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NOR2_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__NOR2_BEHAVIORAL_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__nor2 (
+    Y,
+    A,
+    B
+);
+
+    // Module ports
+    output Y;
+    input  A;
+    input  B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    nor nor0 (nor0_out_Y, A, B           );
+    buf buf0 (Y         , nor0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR2_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__MUX2I_V
+`define SKY130_FD_SC_LS__MUX2I_V
+
+/**
+ * mux2i: 2-input multiplexer, output inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__mux2i.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__mux2i.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__mux2i.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__mux2i.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MUX2I_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR4B_TB_V
+`define SKY130_FD_SC_LS__NOR4B_TB_V
+
+/**
+ * nor4b: 4-input NOR, first input inverted.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nor4b.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg B;
+    reg C;
+    reg D_N;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        B    = 1\'bX;
+        C    = 1\'bX;
+        D_N  = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   B    = 1\'b0;
+        #60   C    = 1\'b0;
+        #80   D_N  = 1\'b0;
+        #100  VGND = 1\'b0;
+        #120  VNB  = 1\'b0;
+        #140  VPB  = 1\'b0;
+        #160  VPWR = 1\'b0;
+        #180  A    = 1\'b1;
+        #200  B    = 1\'b1;
+        #220  C    = 1\'b1;
+        #240  D_N  = 1\'b1;
+        #260  VGND = 1\'b1;
+        #280  VNB  = 1\'b1;
+        #300  VPB  = 1\'b1;
+        #320  VPWR = 1\'b1;
+        #340  A    = 1\'b0;
+        #360  B    = 1\'b0;
+        #380  C    = 1\'b0;
+        #400  D_N  = 1\'b0;
+        #420  VGND = 1\'b0;
+        #440  VNB  = 1\'b0;
+        #460  VPB  = 1\'b0;
+        #480  VPWR = 1\'b0;
+        #500  VPWR = 1\'b1;
+        #520  VPB  = 1\'b1;
+        #540  VNB  = 1\'b1;
+        #560  VGND = 1\'b1;
+        #580  D_N  = 1\'b1;
+        #600  C    = 1\'b1;
+        #620  B    = 1\'b1;
+        #640  A    = 1\'b1;
+        #660  VPWR = 1\'bx;
+        #680  VPB  = 1\'bx;
+        #700  VNB  = 1\'bx;
+        #720  VGND = 1\'bx;
+        #740  D_N  = 1\'bx;
+        #760  C    = 1\'bx;
+        #780  B    = 1\'bx;
+        #800  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__nor4b dut (.A(A), .B(B), .C(C), .D_N(D_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR4B_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NOR2B_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__NOR2B_BEHAVIORAL_V
+
+/**
+ * nor2b: 2-input NOR, first input inverted.
+ *
+ *        Y = !(A | B | C | !D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__nor2b (
+    Y  ,
+    A  ,
+    B_N
+);
+
+    // Module ports
+    output Y  ;
+    input  A  ;
+    input  B_N;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out  ;
+    wire and0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out  , A              );
+    and and0 (and0_out_Y, not0_out, B_N  );
+    buf buf0 (Y         , and0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR2B_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A32OI_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__A32OI_BEHAVIORAL_V
+
+/**
+ * a32oi: 3-input AND into first input, and 2-input AND into
+ *        2nd input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a32oi (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nand0_out ;
+    wire nand1_out ;
+    wire and0_out_Y;
+
+    //   Name   Output      Other arguments
+    nand nand0 (nand0_out , A2, A1, A3          );
+    nand nand1 (nand1_out , B2, B1              );
+    and  and0  (and0_out_Y, nand0_out, nand1_out);
+    buf  buf0  (Y         , and0_out_Y          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A32OI_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O2111A_TB_V
+`define SKY130_FD_SC_LS__O2111A_TB_V
+
+/**
+ * o2111a: 2-input OR into first input of 4-input AND.
+ *
+ *         X = ((A1 | A2) & B1 & C1 & D1)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o2111a.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg B1;
+    reg C1;
+    reg D1;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        B1   = 1\'bX;
+        C1   = 1\'bX;
+        D1   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   B1   = 1\'b0;
+        #80   C1   = 1\'b0;
+        #100  D1   = 1\'b0;
+        #120  VGND = 1\'b0;
+        #140  VNB  = 1\'b0;
+        #160  VPB  = 1\'b0;
+        #180  VPWR = 1\'b0;
+        #200  A1   = 1\'b1;
+        #220  A2   = 1\'b1;
+        #240  B1   = 1\'b1;
+        #260  C1   = 1\'b1;
+        #280  D1   = 1\'b1;
+        #300  VGND = 1\'b1;
+        #320  VNB  = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VPWR = 1\'b1;
+        #380  A1   = 1\'b0;
+        #400  A2   = 1\'b0;
+        #420  B1   = 1\'b0;
+        #440  C1   = 1\'b0;
+        #460  D1   = 1\'b0;
+        #480  VGND = 1\'b0;
+        #500  VNB  = 1\'b0;
+        #520  VPB  = 1\'b0;
+        #540  VPWR = 1\'b0;
+        #560  VPWR = 1\'b1;
+        #580  VPB  = 1\'b1;
+        #600  VNB  = 1\'b1;
+        #620  VGND = 1\'b1;
+        #640  D1   = 1\'b1;
+        #660  C1   = 1\'b1;
+        #680  B1   = 1\'b1;
+        #700  A2   = 1\'b1;
+        #720  A1   = 1\'b1;
+        #740  VPWR = 1\'bx;
+        #760  VPB  = 1\'bx;
+        #780  VNB  = 1\'bx;
+        #800  VGND = 1\'bx;
+        #820  D1   = 1\'bx;
+        #840  C1   = 1\'bx;
+        #860  B1   = 1\'bx;
+        #880  A2   = 1\'bx;
+        #900  A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__o2111a dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .D1(D1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2111A_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD3_SYMBOL_V
+`define SKY130_FD_SC_LS__CLKDLYINV3SD3_SYMBOL_V
+
+/**
+ * clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
+ *                stage gate.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__clkdlyinv3sd3 (
+    //# {{data|Data Signals}}
+    input  A,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV3SD3_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O2BB2AI_4_V
+`define SKY130_FD_SC_LS__O2BB2AI_4_V
+
+/**
+ * o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
+ *
+ *          Y = !(!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o2bb2ai with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o2bb2ai.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o2bb2ai_4 (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o2bb2ai base (
+        .Y(Y),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o2bb2ai_4 (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o2bb2ai base (
+        .Y(Y),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2BB2AI_4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A221OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__A221OI_BEHAVIORAL_PP_V
+
+/**
+ * a221oi: 2-input AND into first two inputs of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a221oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire and1_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , B1, B2                );
+    and                                and1        (and1_out         , A1, A2                );
+    nor                                nor0        (nor0_out_Y       , and0_out, C1, and1_out);
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A221OI_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DFF_PR_SYMBOL_V
+`define SKY130_FD_SC_LS__UDP_DFF_PR_SYMBOL_V
+
+/**
+ * udp_dff$PR: Positive edge triggered D flip-flop with active high
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__udp_dff$PR (
+    //# {{data|Data Signals}}
+    input  D    ,
+    output Q    ,
+
+    //# {{control|Control Signals}}
+    input  RESET,
+
+    //# {{clocks|Clocking}}
+    input  CLK
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DFF_PR_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DLATCH_PR_TB_V
+`define SKY130_FD_SC_LS__UDP_DLATCH_PR_TB_V
+
+/**
+ * udp_dlatch$PR: D-latch, gated clear direct / gate active high
+ *                (Q output UDP)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__udp_dlatch_pr.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg RESET;
+
+    // Outputs are wires
+    wire Q;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D     = 1\'bX;
+        RESET = 1\'bX;
+
+        #20   D     = 1\'b0;
+        #40   RESET = 1\'b0;
+        #60   D     = 1\'b1;
+        #80   RESET = 1\'b1;
+        #100  D     = 1\'b0;
+        #120  RESET = 1\'b0;
+        #140  RESET = 1\'b1;
+        #160  D     = 1\'b1;
+        #180  RESET = 1\'bx;
+        #200  D     = 1\'bx;
+    end
+
+    // Create a clock
+    reg GATE;
+    initial
+    begin
+        GATE = 1\'b0;
+    end
+
+    always
+    begin
+        #5 GATE = ~GATE;
+    end
+
+    sky130_fd_sc_ls__udp_dlatch$PR dut (.D(D), .RESET(RESET), .Q(Q), .GATE(GATE));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DLATCH_PR_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DFF_NSR_V
+`define SKY130_FD_SC_LS__UDP_DFF_NSR_V
+
+/**
+ * udp_dff$NSR: Negative edge triggered D flip-flop (Q output UDP)
+ *              with both active high reset and set (set dominate).
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`include ""./sky130_fd_sc_ls__udp_dff_nsr.blackbox.v""
+`else
+primitive sky130_fd_sc_ls__udp_dff$NSR (
+    Q    ,
+    SET  ,
+    RESET,
+    CLK_N,
+    D
+);
+
+    output Q    ;
+    input  SET  ;
+    input  RESET;
+    input  CLK_N;
+    input  D    ;
+
+    reg Q;
+
+    table
+     // SET RESET CLK_N  D  :  Qt : Qt+1
+         0    1     ?    ?  :  ?  :  0    ; // Asserting reset
+         0    *     ?    ?  :  0  :  0    ; // Changing reset
+         1    ?     ?    ?  :  ?  :  1    ; // Asserting set (dominates reset)
+         *    0     ?    ?  :  1  :  1    ; // Changing set
+         0    ?    (01)  0  :  ?  :  0    ; // rising clock
+         ?    0    (01)  1  :  ?  :  1    ; // rising clock
+         0    ?     p    0  :  0  :  0    ; // potential rising clock
+         ?    0     p    1  :  1  :  1    ; // potential rising clock
+         0    0     n    ?  :  ?  :  -    ; // Clock falling register output does not change
+         0    0     ?    *  :  ?  :  -    ; // Changing Data
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DFF_NSR_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLCLKP_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__DLCLKP_BEHAVIORAL_V
+
+/**
+ * dlclkp: Clock gate.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlclkp (
+    GCLK,
+    GATE,
+    CLK
+);
+
+    // Module ports
+    output GCLK;
+    input  GATE;
+    input  CLK ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire m0          ;
+    wire clkn        ;
+    wire CLK_delayed ;
+    wire GATE_delayed;
+    reg  notifier    ;
+    wire awake       ;
+
+    //                                    Name     Output  Other arguments
+    not                                   not0    (clkn  , CLK_delayed                             );
+    sky130_fd_sc_ls__udp_dlatch$P_pp$PG$N dlatch0 (m0    , GATE_delayed, clkn, notifier, VPWR, VGND);
+    and                                   and0    (GCLK  , m0, CLK_delayed                         );
+    assign awake = ( VPWR === 1\'b1 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLCLKP_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NOR2B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__NOR2B_FUNCTIONAL_PP_V
+
+/**
+ * nor2b: 2-input NOR, first input inverted.
+ *
+ *        Y = !(A | B | C | !D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__nor2b (
+    Y   ,
+    A   ,
+    B_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire and0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , A                     );
+    and                                and0        (and0_out_Y       , not0_out, B_N         );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR2B_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O32AI_V
+`define SKY130_FD_SC_LS__O32AI_V
+
+/**
+ * o32ai: 3-input OR and 2-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o32ai.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o32ai.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o32ai.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o32ai.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O32AI_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND2B_1_V
+`define SKY130_FD_SC_LS__NAND2B_1_V
+
+/**
+ * nand2b: 2-input NAND, first input inverted.
+ *
+ * Verilog wrapper for nand2b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nand2b.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nand2b_1 (
+    Y   ,
+    A_N ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A_N ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nand2b base (
+        .Y(Y),
+        .A_N(A_N),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nand2b_1 (
+    Y  ,
+    A_N,
+    B
+);
+
+    output Y  ;
+    input  A_N;
+    input  B  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nand2b base (
+        .Y(Y),
+        .A_N(A_N),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND2B_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLXTP_SYMBOL_V
+`define SKY130_FD_SC_LS__DLXTP_SYMBOL_V
+
+/**
+ * dlxtp: Delay latch, non-inverted enable, single output.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlxtp (
+    //# {{data|Data Signals}}
+    input  D   ,
+    output Q   ,
+
+    //# {{clocks|Clocking}}
+    input  GATE
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXTP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFSTP_4_V
+`define SKY130_FD_SC_LS__SDFSTP_4_V
+
+/**
+ * sdfstp: Scan delay flop, inverted set, non-inverted clock,
+ *         single output.
+ *
+ * Verilog wrapper for sdfstp with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__sdfstp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sdfstp_4 (
+    Q    ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_ls__sdfstp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .SET_B(SET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sdfstp_4 (
+    Q    ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B
+);
+
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__sdfstp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .SET_B(SET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFSTP_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_MUX_2TO1_N_TB_V
+`define SKY130_FD_SC_LS__UDP_MUX_2TO1_N_TB_V
+
+/**
+ * udp_mux_2to1_N: Two to one multiplexer with inverting output
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__udp_mux_2to1_n.v""
+
+module top();
+
+    // Inputs are registered
+    reg A0;
+    reg A1;
+    reg S;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A0 = 1\'bX;
+        A1 = 1\'bX;
+        S  = 1\'bX;
+
+        #20   A0 = 1\'b0;
+        #40   A1 = 1\'b0;
+        #60   S  = 1\'b0;
+        #80   A0 = 1\'b1;
+        #100  A1 = 1\'b1;
+        #120  S  = 1\'b1;
+        #140  A0 = 1\'b0;
+        #160  A1 = 1\'b0;
+        #180  S  = 1\'b0;
+        #200  S  = 1\'b1;
+        #220  A1 = 1\'b1;
+        #240  A0 = 1\'b1;
+        #260  S  = 1\'bx;
+        #280  A1 = 1\'bx;
+        #300  A0 = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__udp_mux_2to1_N dut (.A0(A0), .A1(A1), .S(S), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_MUX_2TO1_N_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND4B_V
+`define SKY130_FD_SC_LS__NAND4B_V
+
+/**
+ * nand4b: 4-input NAND, first input inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__nand4b.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__nand4b.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__nand4b.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__nand4b.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND4B_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O2BB2A_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__O2BB2A_PP_SYMBOL_V
+
+/**
+ * o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
+ *
+ *         X = (!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o2bb2a (
+    //# {{data|Data Signals}}
+    input  A1_N,
+    input  A2_N,
+    input  B1  ,
+    input  B2  ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2BB2A_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FAHCON_BLACKBOX_V
+`define SKY130_FD_SC_LS__FAHCON_BLACKBOX_V
+
+/**
+ * fahcon: Full adder, inverted carry in, inverted carry out.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__fahcon (
+    COUT_N,
+    SUM   ,
+    A     ,
+    B     ,
+    CI
+);
+
+    output COUT_N;
+    output SUM   ;
+    input  A     ;
+    input  B     ;
+    input  CI    ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FAHCON_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A41O_BLACKBOX_V
+`define SKY130_FD_SC_LS__A41O_BLACKBOX_V
+
+/**
+ * a41o: 4-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a41o (
+    X ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A41O_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O31AI_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__O31AI_PP_SYMBOL_V
+
+/**
+ * o31ai: 3-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3) & B1)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o31ai (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  A3  ,
+    input  B1  ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O31AI_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O31A_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__O31A_BEHAVIORAL_PP_V
+
+/**
+ * o31a: 3-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__o31a (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1, A3            );
+    and                                and0        (and0_out_X       , or0_out, B1           );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O31A_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND3_V
+`define SKY130_FD_SC_LS__NAND3_V
+
+/**
+ * nand3: 3-input NAND.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__nand3.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__nand3.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__nand3.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__nand3.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND3_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O21BA_V
+`define SKY130_FD_SC_LS__O21BA_V
+
+/**
+ * o21ba: 2-input OR into first input of 2-input AND,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 | A2) & !B1_N)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o21ba.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o21ba.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o21ba.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o21ba.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21BA_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A311OI_SYMBOL_V
+`define SKY130_FD_SC_LS__A311OI_SYMBOL_V
+
+/**
+ * a311oi: 3-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a311oi (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  A3,
+    input  B1,
+    input  C1,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A311OI_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLRBN_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__DLRBN_BEHAVIORAL_V
+
+/**
+ * dlrbn: Delay latch, inverted reset, inverted enable,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_pr_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlrbn (
+    Q      ,
+    Q_N    ,
+    RESET_B,
+    D      ,
+    GATE_N
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE_N ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire RESET          ;
+    wire intgate        ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire GATE_N_delayed ;
+    wire RESET_delayed  ;
+    wire RESET_B_delayed;
+    wire buf_Q          ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+
+    //                                     Name     Output   Other arguments
+    not                                    not0    (RESET  , RESET_B_delayed                                );
+    not                                    not1    (intgate, GATE_N_delayed                                 );
+    sky130_fd_sc_ls__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q  , D_delayed, intgate, RESET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1\'b1 ) );
+    assign cond1 = ( awake && ( RESET_B === 1\'b1 ) );
+    buf                                    buf0    (Q      , buf_Q                                          );
+    not                                    not2    (Q_N    , buf_Q                                          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRBN_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__BUFINV_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__BUFINV_FUNCTIONAL_V
+
+/**
+ * bufinv: Buffer followed by inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__bufinv (
+    Y,
+    A
+);
+
+    // Module ports
+    output Y;
+    input  A;
+
+    // Local signals
+    wire not0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out_Y, A              );
+    buf buf0 (Y         , not0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__BUFINV_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__MUX2I_1_V
+`define SKY130_FD_SC_LS__MUX2I_1_V
+
+/**
+ * mux2i: 2-input multiplexer, output inverted.
+ *
+ * Verilog wrapper for mux2i with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__mux2i.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__mux2i_1 (
+    Y   ,
+    A0  ,
+    A1  ,
+    S   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A0  ;
+    input  A1  ;
+    input  S   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__mux2i base (
+        .Y(Y),
+        .A0(A0),
+        .A1(A1),
+        .S(S),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__mux2i_1 (
+    Y ,
+    A0,
+    A1,
+    S
+);
+
+    output Y ;
+    input  A0;
+    input  A1;
+    input  S ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__mux2i base (
+        .Y(Y),
+        .A0(A0),
+        .A1(A1),
+        .S(S)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MUX2I_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+( posedge CLK => ( Q : CLK ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall
+$width ( posedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( negedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+$setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , CLK_delayed , D_delayed ) ;
+$setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , CLK_delayed , D_delayed ) ;
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDLCLKP_V
+`define SKY130_FD_SC_LS__SDLCLKP_V
+
+/**
+ * sdlclkp: Scan gated clock.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__sdlclkp.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__sdlclkp.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__sdlclkp.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__sdlclkp.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDLCLKP_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__AND4_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__AND4_BEHAVIORAL_PP_V
+
+/**
+ * and4: 4-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__and4 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out_X       , A, B, C, D            );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND4_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A311OI_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__A311OI_PP_BLACKBOX_V
+
+/**
+ * a311oi: 3-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a311oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A311OI_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A1 -=> Y) = (0:0:0,0:0:0);
+(A2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2)) (B1_N +=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2)) (B1_N +=> Y) = (0:0:0,0:0:0);
+if ((A1&A2)) (B1_N +=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__TAPVGNDNOVPB_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__TAPVGNDNOVPB_PP_SYMBOL_V
+
+/**
+ * tapvgndnovpb: Substrate only tap cell.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__tapvgndnovpb (
+    //# {{power|Power}}
+    input VPB ,
+    input VPWR,
+    input VGND,
+    input VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPVGNDNOVPB_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A2111O_4_V
+`define SKY130_FD_SC_LS__A2111O_4_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ *         X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog wrapper for a2111o with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a2111o.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a2111o_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a2111o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a2111o_4 (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a2111o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2111O_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLYGATE4SD2_TB_V
+`define SKY130_FD_SC_LS__DLYGATE4SD2_TB_V
+
+/**
+ * dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dlygate4sd2.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   VGND = 1\'b0;
+        #60   VNB  = 1\'b0;
+        #80   VPB  = 1\'b0;
+        #100  VPWR = 1\'b0;
+        #120  A    = 1\'b1;
+        #140  VGND = 1\'b1;
+        #160  VNB  = 1\'b1;
+        #180  VPB  = 1\'b1;
+        #200  VPWR = 1\'b1;
+        #220  A    = 1\'b0;
+        #240  VGND = 1\'b0;
+        #260  VNB  = 1\'b0;
+        #280  VPB  = 1\'b0;
+        #300  VPWR = 1\'b0;
+        #320  VPWR = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VNB  = 1\'b1;
+        #380  VGND = 1\'b1;
+        #400  A    = 1\'b1;
+        #420  VPWR = 1\'bx;
+        #440  VPB  = 1\'bx;
+        #460  VNB  = 1\'bx;
+        #480  VGND = 1\'bx;
+        #500  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__dlygate4sd2 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYGATE4SD2_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR3_BLACKBOX_V
+`define SKY130_FD_SC_LS__NOR3_BLACKBOX_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ *       Y = !(A | B | C | !D)
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nor3 (
+    Y,
+    A,
+    B,
+    C
+);
+
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR3_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O221AI_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__O221AI_PP_SYMBOL_V
+
+/**
+ * o221ai: 2-input OR into first two inputs of 3-input NAND.
+ *
+ *         Y = !((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o221ai (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  B1  ,
+    input  B2  ,
+    input  C1  ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O221AI_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A211O_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__A211O_BEHAVIORAL_PP_V
+
+/**
+ * a211o: 2-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a211o (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A1, A2               );
+    or                                 or0         (or0_out_X        , and0_out, C1, B1     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A211O_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O211AI_SYMBOL_V
+`define SKY130_FD_SC_LS__O211AI_SYMBOL_V
+
+/**
+ * o211ai: 2-input OR into first input of 3-input NAND.
+ *
+ *         Y = !((A1 | A2) & B1 & C1)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o211ai (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  B1,
+    input  C1,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O211AI_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A311O_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__A311O_BEHAVIORAL_V
+
+/**
+ * a311o: 3-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a311o (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , A3, A1, A2      );
+    or  or0  (or0_out_X, and0_out, C1, B1);
+    buf buf0 (X        , or0_out_X       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A311O_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR4B_1_V
+`define SKY130_FD_SC_LS__NOR4B_1_V
+
+/**
+ * nor4b: 4-input NOR, first input inverted.
+ *
+ * Verilog wrapper for nor4b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nor4b.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor4b_1 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nor4b base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D_N(D_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor4b_1 (
+    Y  ,
+    A  ,
+    B  ,
+    C  ,
+    D_N
+);
+
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C  ;
+    input  D_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nor4b base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D_N(D_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR4B_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLXTN_BLACKBOX_V
+`define SKY130_FD_SC_LS__DLXTN_BLACKBOX_V
+
+/**
+ * dlxtn: Delay latch, inverted enable, single output.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlxtn (
+    Q     ,
+    D     ,
+    GATE_N
+);
+
+    output Q     ;
+    input  D     ;
+    input  GATE_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXTN_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A222OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__A222OI_FUNCTIONAL_PP_V
+
+/**
+ * a222oi: 2-input AND into all inputs of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a222oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    C2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  C2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out        ;
+    wire nand1_out        ;
+    wire nand2_out        ;
+    wire and0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out        , A2, A1                         );
+    nand                               nand1       (nand1_out        , B2, B1                         );
+    nand                               nand2       (nand2_out        , C2, C1                         );
+    and                                and0        (and0_out_Y       , nand0_out, nand1_out, nand2_out);
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND         );
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y              );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A222OI_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A21OI_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__A21OI_BEHAVIORAL_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a21oi (
+    Y ,
+    A1,
+    A2,
+    B1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out  ;
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out  , A1, A2         );
+    nor nor0 (nor0_out_Y, B1, and0_out   );
+    buf buf0 (Y         , nor0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21OI_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DFF_PS_PP_PG_N_BLACKBOX_V
+`define SKY130_FD_SC_LS__UDP_DFF_PS_PP_PG_N_BLACKBOX_V
+
+/**
+ * udp_dff$PS_pp$PG$N: Positive edge triggered D flip-flop with active
+ *                     high
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__udp_dff$PS_pp$PG$N (
+    Q       ,
+    D       ,
+    CLK     ,
+    SET     ,
+    NOTIFIER,
+    VPWR    ,
+    VGND
+);
+
+    output Q       ;
+    input  D       ;
+    input  CLK     ;
+    input  SET     ;
+    input  NOTIFIER;
+    input  VPWR    ;
+    input  VGND    ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DFF_PS_PP_PG_N_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__AND2_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__AND2_FUNCTIONAL_V
+
+/**
+ * and2: 2-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__and2 (
+    X,
+    A,
+    B
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+
+    // Local signals
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out_X, A, B           );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND2_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR2B_BLACKBOX_V
+`define SKY130_FD_SC_LS__OR2B_BLACKBOX_V
+
+/**
+ * or2b: 2-input OR, first input inverted.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__or2b (
+    X  ,
+    A  ,
+    B_N
+);
+
+    output X  ;
+    input  A  ;
+    input  B_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR2B_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFXTP_4_V
+`define SKY130_FD_SC_LS__DFXTP_4_V
+
+/**
+ * dfxtp: Delay flop, single output.
+ *
+ * Verilog wrapper for dfxtp with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dfxtp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dfxtp_4 (
+    Q   ,
+    CLK ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__dfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dfxtp_4 (
+    Q  ,
+    CLK,
+    D
+);
+
+    output Q  ;
+    input  CLK;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__dfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFXTP_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND4BB_V
+`define SKY130_FD_SC_LS__AND4BB_V
+
+/**
+ * and4bb: 4-input AND, first two inputs inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__and4bb.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__and4bb.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__and4bb.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__and4bb.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND4BB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND4B_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__NAND4B_PP_SYMBOL_V
+
+/**
+ * nand4b: 4-input NAND, first input inverted.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nand4b (
+    //# {{data|Data Signals}}
+    input  A_N ,
+    input  B   ,
+    input  C   ,
+    input  D   ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND4B_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND3B_1_V
+`define SKY130_FD_SC_LS__AND3B_1_V
+
+/**
+ * and3b: 3-input AND, first input inverted.
+ *
+ * Verilog wrapper for and3b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__and3b.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__and3b_1 (
+    X   ,
+    A_N ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__and3b base (
+        .X(X),
+        .A_N(A_N),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__and3b_1 (
+    X  ,
+    A_N,
+    B  ,
+    C
+);
+
+    output X  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__and3b base (
+        .X(X),
+        .A_N(A_N),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND3B_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR4BB_BLACKBOX_V
+`define SKY130_FD_SC_LS__NOR4BB_BLACKBOX_V
+
+/**
+ * nor4bb: 4-input NOR, first two inputs inverted.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nor4bb (
+    Y  ,
+    A  ,
+    B  ,
+    C_N,
+    D_N
+);
+
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+    input  D_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR4BB_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if ((!B&!C)) (A -=> X) = (0:0:0,0:0:0);
+if ((!B&C)) (A +=> X) = (0:0:0,0:0:0);
+if ((B&!C)) (A +=> X) = (0:0:0,0:0:0);
+if ((B&C)) (A -=> X) = (0:0:0,0:0:0);
+if ((!A&!C)) (B -=> X) = (0:0:0,0:0:0);
+if ((!A&C)) (B +=> X) = (0:0:0,0:0:0);
+if ((A&!C)) (B +=> X) = (0:0:0,0:0:0);
+if ((A&C)) (B -=> X) = (0:0:0,0:0:0);
+if ((!A&!B)) (C -=> X) = (0:0:0,0:0:0);
+if ((!A&B)) (C +=> X) = (0:0:0,0:0:0);
+if ((A&!B)) (C +=> X) = (0:0:0,0:0:0);
+if ((A&B)) (C -=> X) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD1_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__CLKDLYINV3SD1_PP_SYMBOL_V
+
+/**
+ * clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
+ *                stage gate.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__clkdlyinv3sd1 (
+    //# {{data|Data Signals}}
+    input  A   ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV3SD1_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A41OI_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__A41OI_PP_SYMBOL_V
+
+/**
+ * a41oi: 4-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a41oi (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  A3  ,
+    input  A4  ,
+    input  B1  ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A41OI_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR3B_V
+`define SKY130_FD_SC_LS__OR3B_V
+
+/**
+ * or3b: 3-input OR, first input inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__or3b.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__or3b.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__or3b.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__or3b.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR3B_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLYGATE4SD2_1_V
+`define SKY130_FD_SC_LS__DLYGATE4SD2_1_V
+
+/**
+ * dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
+ *
+ * Verilog wrapper for dlygate4sd2 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dlygate4sd2.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dlygate4sd2_1 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__dlygate4sd2 base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dlygate4sd2_1 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__dlygate4sd2 base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYGATE4SD2_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR3B_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__NOR3B_PP_SYMBOL_V
+
+/**
+ * nor3b: 3-input NOR, first input inverted.
+ *
+ *        Y = (!(A | B)) & !C)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nor3b (
+    //# {{data|Data Signals}}
+    input  A   ,
+    input  B   ,
+    input  C_N ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR3B_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A311OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__A311OI_BEHAVIORAL_PP_V
+
+/**
+ * a311oi: 3-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a311oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A3, A1, A2            );
+    nor                                nor0        (nor0_out_Y       , and0_out, B1, C1      );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A311OI_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFRTN_V
+`define SKY130_FD_SC_LS__DFRTN_V
+
+/**
+ * dfrtn: Delay flop, inverted reset, inverted clock,
+ *        complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dfrtn.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dfrtn.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dfrtn.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dfrtn.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFRTN_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__CLKINV_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__CLKINV_BEHAVIORAL_V
+
+/**
+ * clkinv: Clock tree inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__clkinv (
+    Y,
+    A
+);
+
+    // Module ports
+    output Y;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out_Y, A              );
+    buf buf0 (Y         , not0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKINV_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLRTP_BLACKBOX_V
+`define SKY130_FD_SC_LS__DLRTP_BLACKBOX_V
+
+/**
+ * dlrtp: Delay latch, inverted reset, non-inverted enable,
+ *        single output.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlrtp (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE
+);
+
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRTP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A22OI_TB_V
+`define SKY130_FD_SC_LS__A22OI_TB_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a22oi.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg B1;
+    reg B2;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        B1   = 1\'bX;
+        B2   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   B1   = 1\'b0;
+        #80   B2   = 1\'b0;
+        #100  VGND = 1\'b0;
+        #120  VNB  = 1\'b0;
+        #140  VPB  = 1\'b0;
+        #160  VPWR = 1\'b0;
+        #180  A1   = 1\'b1;
+        #200  A2   = 1\'b1;
+        #220  B1   = 1\'b1;
+        #240  B2   = 1\'b1;
+        #260  VGND = 1\'b1;
+        #280  VNB  = 1\'b1;
+        #300  VPB  = 1\'b1;
+        #320  VPWR = 1\'b1;
+        #340  A1   = 1\'b0;
+        #360  A2   = 1\'b0;
+        #380  B1   = 1\'b0;
+        #400  B2   = 1\'b0;
+        #420  VGND = 1\'b0;
+        #440  VNB  = 1\'b0;
+        #460  VPB  = 1\'b0;
+        #480  VPWR = 1\'b0;
+        #500  VPWR = 1\'b1;
+        #520  VPB  = 1\'b1;
+        #540  VNB  = 1\'b1;
+        #560  VGND = 1\'b1;
+        #580  B2   = 1\'b1;
+        #600  B1   = 1\'b1;
+        #620  A2   = 1\'b1;
+        #640  A1   = 1\'b1;
+        #660  VPWR = 1\'bx;
+        #680  VPB  = 1\'bx;
+        #700  VNB  = 1\'bx;
+        #720  VGND = 1\'bx;
+        #740  B2   = 1\'bx;
+        #760  B1   = 1\'bx;
+        #780  A2   = 1\'bx;
+        #800  A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__a22oi dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A22OI_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O21AI_4_V
+`define SKY130_FD_SC_LS__O21AI_4_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & B1)
+ *
+ * Verilog wrapper for o21ai with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o21ai.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o21ai_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o21ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o21ai_4 (
+    Y ,
+    A1,
+    A2,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o21ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21AI_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR2B_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__NOR2B_PP_BLACKBOX_V
+
+/**
+ * nor2b: 2-input NOR, first input inverted.
+ *
+ *        Y = !(A | B | C | !D)
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nor2b (
+    Y   ,
+    A   ,
+    B_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR2B_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A22O_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__A22O_FUNCTIONAL_PP_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ *       X = ((A1 & A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a22o (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire and1_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , B1, B2               );
+    and                                and1        (and1_out         , A1, A2               );
+    or                                 or0         (or0_out_X        , and1_out, and0_out   );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A22O_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A222OI_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__A222OI_BEHAVIORAL_V
+
+/**
+ * a222oi: 2-input AND into all inputs of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a222oi (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1,
+    C2
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+    input  C2;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nand0_out ;
+    wire nand1_out ;
+    wire nand2_out ;
+    wire and0_out_Y;
+
+    //   Name   Output      Other arguments
+    nand nand0 (nand0_out , A2, A1                         );
+    nand nand1 (nand1_out , B2, B1                         );
+    nand nand2 (nand2_out , C2, C1                         );
+    and  and0  (and0_out_Y, nand0_out, nand1_out, nand2_out);
+    buf  buf0  (Y         , and0_out_Y                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A222OI_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O2BB2AI_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__O2BB2AI_BEHAVIORAL_V
+
+/**
+ * o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
+ *
+ *          Y = !(!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__o2bb2ai (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    // Module ports
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nand0_out  ;
+    wire or0_out    ;
+    wire nand1_out_Y;
+
+    //   Name   Output       Other arguments
+    nand nand0 (nand0_out  , A2_N, A1_N        );
+    or   or0   (or0_out    , B2, B1            );
+    nand nand1 (nand1_out_Y, nand0_out, or0_out);
+    buf  buf0  (Y          , nand1_out_Y       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2BB2AI_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD1_SYMBOL_V
+`define SKY130_FD_SC_LS__CLKDLYINV3SD1_SYMBOL_V
+
+/**
+ * clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
+ *                stage gate.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__clkdlyinv3sd1 (
+    //# {{data|Data Signals}}
+    input  A,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV3SD1_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__BUFBUF_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__BUFBUF_BEHAVIORAL_PP_V
+
+/**
+ * bufbuf: Double buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__bufbuf (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__BUFBUF_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLXBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__DLXBP_FUNCTIONAL_PP_V
+
+/**
+ * dlxbp: Delay latch, non-inverted enable, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlxbp (
+    Q   ,
+    Q_N ,
+    D   ,
+    GATE,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    output Q_N ;
+    input  D   ;
+    input  GATE;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q;
+
+    //                                    Delay       Name     Output  Other arguments
+    sky130_fd_sc_ls__udp_dlatch$P_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
+    buf                                               buf0    (Q     , buf_Q                );
+    not                                               not0    (Q_N   , buf_Q                );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXBP_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A21O_V
+`define SKY130_FD_SC_LS__A21O_V
+
+/**
+ * a21o: 2-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2) | B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a21o.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a21o.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a21o.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a21o.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21O_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLYMETAL6S4S_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__DLYMETAL6S4S_FUNCTIONAL_V
+
+/**
+ * dlymetal6s4s: 6-inverter delay with output from 4th inverter on
+ *               horizontal route.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__dlymetal6s4s (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYMETAL6S4S_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFRTP_4_V
+`define SKY130_FD_SC_LS__DFRTP_4_V
+
+/**
+ * dfrtp: Delay flop, inverted reset, single output.
+ *
+ * Verilog wrapper for dfrtp with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dfrtp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dfrtp_4 (
+    Q      ,
+    CLK    ,
+    D      ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_ls__dfrtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .RESET_B(RESET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dfrtp_4 (
+    Q      ,
+    CLK    ,
+    D      ,
+    RESET_B
+);
+
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__dfrtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .RESET_B(RESET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFRTP_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A22O_V
+`define SKY130_FD_SC_LS__A22O_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ *       X = ((A1 & A2) | (B1 & B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a22o.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a22o.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a22o.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a22o.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A22O_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__TAPVGND_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__TAPVGND_FUNCTIONAL_V
+
+/**
+ * tapvgnd: Tap cell with tap to ground, isolated power connection 1
+ *          row down.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__tapvgnd ();
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPVGND_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if ((!A2&!B1&B2&C1)) (A1 -=> Y) = (0:0:0,0:0:0);
+if ((!A2&B1&!B2&C1)) (A1 -=> Y) = (0:0:0,0:0:0);
+if ((!A2&B1&B2&C1)) (A1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!B1&B2&C1)) (A2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&B1&!B2&C1)) (A2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&B1&B2&C1)) (A2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&!B2&C1)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&!B2&C1)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2&!B2&C1)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&!B1&C1)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&!B1&C1)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2&!B1&C1)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2&B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DECAPHE_SYMBOL_V
+`define SKY130_FD_SC_LS__DECAPHE_SYMBOL_V
+
+/**
+ * decaphe: Shielded Decoupling capacitance filler.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__decaphe ();
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DECAPHE_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR4BB_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__OR4BB_PP_SYMBOL_V
+
+/**
+ * or4bb: 4-input OR, first two inputs inverted.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__or4bb (
+    //# {{data|Data Signals}}
+    input  A   ,
+    input  B   ,
+    input  C_N ,
+    input  D_N ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR4BB_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__TAPVGNDNOVPB_TB_V
+`define SKY130_FD_SC_LS__TAPVGNDNOVPB_TB_V
+
+/**
+ * tapvgndnovpb: Substrate only tap cell.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__tapvgndnovpb.v""
+
+module top();
+
+    // Inputs are registered
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   VGND = 1\'b0;
+        #40   VNB  = 1\'b0;
+        #60   VPB  = 1\'b0;
+        #80   VPWR = 1\'b0;
+        #100  VGND = 1\'b1;
+        #120  VNB  = 1\'b1;
+        #140  VPB  = 1\'b1;
+        #160  VPWR = 1\'b1;
+        #180  VGND = 1\'b0;
+        #200  VNB  = 1\'b0;
+        #220  VPB  = 1\'b0;
+        #240  VPWR = 1\'b0;
+        #260  VPWR = 1\'b1;
+        #280  VPB  = 1\'b1;
+        #300  VNB  = 1\'b1;
+        #320  VGND = 1\'b1;
+        #340  VPWR = 1\'bx;
+        #360  VPB  = 1\'bx;
+        #380  VNB  = 1\'bx;
+        #400  VGND = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__tapvgndnovpb dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPVGNDNOVPB_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+( negedge RESET_B => ( Q +: RESET_B ) ) = 0:0:0 ;  // delay is tris
+( negedge RESET_B => ( Q_N -: RESET_B ) ) = 0:0:0 ;  // delay is tris
+( posedge CLK => ( Q : CLK ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall
+( posedge CLK => ( Q_N : CLK ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall
+$recrem ( posedge RESET_B , posedge CLK , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , RESETB_delayed , CLK_delayed ) ;
+$setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , CLK_delayed , D_delayed ) ;
+$setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , CLK_delayed , D_delayed ) ;
+$width ( posedge CLK &&& COND1 , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( negedge CLK &&& COND1 , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( negedge RESET_B &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A311O_BLACKBOX_V
+`define SKY130_FD_SC_LS__A311O_BLACKBOX_V
+
+/**
+ * a311o: 3-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a311o (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A311O_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR3B_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__NOR3B_PP_BLACKBOX_V
+
+/**
+ * nor3b: 3-input NOR, first input inverted.
+ *
+ *        Y = (!(A | B)) & !C)
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nor3b (
+    Y   ,
+    A   ,
+    B   ,
+    C_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR3B_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A1 -=> Y) = (0:0:0,0:0:0);
+(A2 -=> Y) = (0:0:0,0:0:0);
+(A3 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2&!A3)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2&A3)) (B1 -=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A2111OI_V
+`define SKY130_FD_SC_LS__A2111OI_V
+
+/**
+ * a2111oi: 2-input AND into first input of 4-input NOR.
+ *
+ *          Y = !((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a2111oi.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a2111oi.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a2111oi.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a2111oi.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2111OI_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFSTP_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__DFSTP_PP_SYMBOL_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dfstp (
+    //# {{data|Data Signals}}
+    input  D    ,
+    output Q    ,
+
+    //# {{control|Control Signals}}
+    input  SET_B,
+
+    //# {{clocks|Clocking}}
+    input  CLK  ,
+
+    //# {{power|Power}}
+    input  VPB  ,
+    input  VPWR ,
+    input  VGND ,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFSTP_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SEDFXTP_BLACKBOX_V
+`define SKY130_FD_SC_LS__SEDFXTP_BLACKBOX_V
+
+/**
+ * sedfxtp: Scan delay flop, data enable, non-inverted clock,
+ *          single output.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sedfxtp (
+    Q  ,
+    CLK,
+    D  ,
+    DE ,
+    SCD,
+    SCE
+);
+
+    output Q  ;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+    input  SCD;
+    input  SCE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SEDFXTP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A21BO_SYMBOL_V
+`define SKY130_FD_SC_LS__A21BO_SYMBOL_V
+
+/**
+ * a21bo: 2-input AND into first input of 2-input OR,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 & A2) | (!B1_N))
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a21bo (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  B1_N,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21BO_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLXBN_1_V
+`define SKY130_FD_SC_LS__DLXBN_1_V
+
+/**
+ * dlxbn: Delay latch, inverted enable, complementary outputs.
+ *
+ * Verilog wrapper for dlxbn with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dlxbn.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dlxbn_1 (
+    Q     ,
+    Q_N   ,
+    D     ,
+    GATE_N,
+    VPWR  ,
+    VGND  ,
+    VPB   ,
+    VNB
+);
+
+    output Q     ;
+    output Q_N   ;
+    input  D     ;
+    input  GATE_N;
+    input  VPWR  ;
+    input  VGND  ;
+    input  VPB   ;
+    input  VNB   ;
+    sky130_fd_sc_ls__dlxbn base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .D(D),
+        .GATE_N(GATE_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dlxbn_1 (
+    Q     ,
+    Q_N   ,
+    D     ,
+    GATE_N
+);
+
+    output Q     ;
+    output Q_N   ;
+    input  D     ;
+    input  GATE_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__dlxbn base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .D(D),
+        .GATE_N(GATE_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXBN_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O21A_V
+`define SKY130_FD_SC_LS__O21A_V
+
+/**
+ * o21a: 2-input OR into first input of 2-input AND.
+ *
+ *       X = ((A1 | A2) & B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o21a.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o21a.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o21a.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o21a.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21A_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_PWRGOOD_PP_G_TB_V
+`define SKY130_FD_SC_LS__UDP_PWRGOOD_PP_G_TB_V
+
+/**
+
+ *   UDP_OUT :=x when VPWR!=1
+ *   UDP_OUT :=UDP_IN when VPWR==1
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__udp_pwrgood_pp_g.v""
+
+module top();
+
+    // Inputs are registered
+    reg UDP_IN;
+    reg VGND;
+
+    // Outputs are wires
+    wire UDP_OUT;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        UDP_IN = 1\'bX;
+        VGND   = 1\'bX;
+
+        #20   UDP_IN = 1\'b0;
+        #40   VGND   = 1\'b0;
+        #60   UDP_IN = 1\'b1;
+        #80   VGND   = 1\'b1;
+        #100  UDP_IN = 1\'b0;
+        #120  VGND   = 1\'b0;
+        #140  VGND   = 1\'b1;
+        #160  UDP_IN = 1\'b1;
+        #180  VGND   = 1\'bx;
+        #200  UDP_IN = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__udp_pwrgood_pp$G dut (.UDP_IN(UDP_IN), .VGND(VGND), .UDP_OUT(UDP_OUT));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_PWRGOOD_PP_G_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DFXBP_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__DFXBP_BEHAVIORAL_V
+
+/**
+ * dfxbp: Delay flop, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dfxbp (
+    Q  ,
+    Q_N,
+    CLK,
+    D
+);
+
+    // Module ports
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q      ;
+    reg  notifier   ;
+    wire D_delayed  ;
+    wire CLK_delayed;
+    wire awake      ;
+
+    //                                 Name  Output  Other arguments
+    sky130_fd_sc_ls__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    buf                                buf0 (Q     , buf_Q                                       );
+    not                                not0 (Q_N   , buf_Q                                       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFXBP_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLXTN_V
+`define SKY130_FD_SC_LS__DLXTN_V
+
+/**
+ * dlxtn: Delay latch, inverted enable, single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlxtn.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlxtn.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlxtn.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlxtn.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXTN_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+( negedge RESET_B => ( Q +: RESET_B ) ) = 0:0:0 ;   // delay is tfall
+( negedge RESET_B => ( Q_N -: RESET_B ) ) = 0:0:0 ;  // delay is tris
+( SET_B => ( Q -: SET_B ) ) = ( 0:0:0 , 0:0:0 ) ;       // delay is tris , tfall
+( SET_B => ( Q_N +: SET_B ) ) = ( 0:0:0 , 0:0:0 ) ;      // delay is tris , tfall
+( posedge CLK => ( Q +: D ) ) = ( 0:0:0 , 0:0:0 ) ;  // delays are tris , tfall
+( posedge CLK => ( Q_N -: D ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall
+$recrem ( posedge SET_B , posedge CLK , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , SETB_delayed , CLK_delayed ) ;
+$recrem ( posedge RESET_B , posedge CLK , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , RESETB_delayed , CLK_delayed ) ;
+$setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND_D , COND_D , CLK_delayed , D_delayed ) ;
+$setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND_D , COND_D , CLK_delayed , D_delayed ) ;
+$setuphold ( posedge CLK , posedge SCD , 0:0:0 , 0:0:0 , notifier , COND_SCD , COND_SCD , CLK_delayed , SCD_delayed ) ;
+$setuphold ( posedge CLK , negedge SCD , 0:0:0 , 0:0:0 , notifier , COND_SCD , COND_SCD , CLK_delayed , SCD_delayed ) ;
+$setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , COND_SCE , COND_SCE , CLK_delayed , SCE_delayed ) ;
+$setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , COND_SCE , COND_SCE , CLK_delayed , SCE_delayed ) ;
+$hold ( posedge SET_B &&& AWAKE , posedge RESET_B &&& AWAKE , 3.0:3.0:3.0 , notifier ) ; //arbitrary , uncharacterized value to
+//flag possible state error
+$hold ( posedge RESET_B &&& AWAKE , posedge SET_B &&& AWAKE , 3.0:3.0:3.0 , notifier ) ; //arbitrary , uncharacterized value to
+//flag possible state error
+$width ( negedge CLK &&& CONDB , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( posedge CLK &&& CONDB , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( negedge SET_B &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( negedge RESET_B &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD1_TB_V
+`define SKY130_FD_SC_LS__CLKDLYINV3SD1_TB_V
+
+/**
+ * clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
+ *                stage gate.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__clkdlyinv3sd1.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   VGND = 1\'b0;
+        #60   VNB  = 1\'b0;
+        #80   VPB  = 1\'b0;
+        #100  VPWR = 1\'b0;
+        #120  A    = 1\'b1;
+        #140  VGND = 1\'b1;
+        #160  VNB  = 1\'b1;
+        #180  VPB  = 1\'b1;
+        #200  VPWR = 1\'b1;
+        #220  A    = 1\'b0;
+        #240  VGND = 1\'b0;
+        #260  VNB  = 1\'b0;
+        #280  VPB  = 1\'b0;
+        #300  VPWR = 1\'b0;
+        #320  VPWR = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VNB  = 1\'b1;
+        #380  VGND = 1\'b1;
+        #400  A    = 1\'b1;
+        #420  VPWR = 1\'bx;
+        #440  VPB  = 1\'bx;
+        #460  VNB  = 1\'bx;
+        #480  VGND = 1\'bx;
+        #500  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__clkdlyinv3sd1 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV3SD1_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLYGATE4SD3_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__DLYGATE4SD3_FUNCTIONAL_PP_V
+
+/**
+ * dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlygate4sd3 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYGATE4SD3_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__TAPVGNDNOVPB_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__TAPVGNDNOVPB_BEHAVIORAL_V
+
+/**
+ * tapvgndnovpb: Substrate only tap cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__tapvgndnovpb ();
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPVGNDNOVPB_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O21BA_4_V
+`define SKY130_FD_SC_LS__O21BA_4_V
+
+/**
+ * o21ba: 2-input OR into first input of 2-input AND,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 | A2) & !B1_N)
+ *
+ * Verilog wrapper for o21ba with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o21ba.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o21ba_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o21ba base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o21ba_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o21ba base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21BA_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND4BB_BLACKBOX_V
+`define SKY130_FD_SC_LS__NAND4BB_BLACKBOX_V
+
+/**
+ * nand4bb: 4-input NAND, first two inputs inverted.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nand4bb (
+    Y  ,
+    A_N,
+    B_N,
+    C  ,
+    D
+);
+
+    output Y  ;
+    input  A_N;
+    input  B_N;
+    input  C  ;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND4BB_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O221A_TB_V
+`define SKY130_FD_SC_LS__O221A_TB_V
+
+/**
+ * o221a: 2-input OR into first two inputs of 3-input AND.
+ *
+ *        X = ((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o221a.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg B1;
+    reg B2;
+    reg C1;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        B1   = 1\'bX;
+        B2   = 1\'bX;
+        C1   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   B1   = 1\'b0;
+        #80   B2   = 1\'b0;
+        #100  C1   = 1\'b0;
+        #120  VGND = 1\'b0;
+        #140  VNB  = 1\'b0;
+        #160  VPB  = 1\'b0;
+        #180  VPWR = 1\'b0;
+        #200  A1   = 1\'b1;
+        #220  A2   = 1\'b1;
+        #240  B1   = 1\'b1;
+        #260  B2   = 1\'b1;
+        #280  C1   = 1\'b1;
+        #300  VGND = 1\'b1;
+        #320  VNB  = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VPWR = 1\'b1;
+        #380  A1   = 1\'b0;
+        #400  A2   = 1\'b0;
+        #420  B1   = 1\'b0;
+        #440  B2   = 1\'b0;
+        #460  C1   = 1\'b0;
+        #480  VGND = 1\'b0;
+        #500  VNB  = 1\'b0;
+        #520  VPB  = 1\'b0;
+        #540  VPWR = 1\'b0;
+        #560  VPWR = 1\'b1;
+        #580  VPB  = 1\'b1;
+        #600  VNB  = 1\'b1;
+        #620  VGND = 1\'b1;
+        #640  C1   = 1\'b1;
+        #660  B2   = 1\'b1;
+        #680  B1   = 1\'b1;
+        #700  A2   = 1\'b1;
+        #720  A1   = 1\'b1;
+        #740  VPWR = 1\'bx;
+        #760  VPB  = 1\'bx;
+        #780  VNB  = 1\'bx;
+        #800  VGND = 1\'bx;
+        #820  C1   = 1\'bx;
+        #840  B2   = 1\'bx;
+        #860  B1   = 1\'bx;
+        #880  A2   = 1\'bx;
+        #900  A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__o221a dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O221A_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SEDFXTP_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__SEDFXTP_PP_BLACKBOX_V
+
+/**
+ * sedfxtp: Scan delay flop, data enable, non-inverted clock,
+ *          single output.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sedfxtp (
+    Q   ,
+    CLK ,
+    D   ,
+    DE  ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  DE  ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SEDFXTP_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__FILL_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__FILL_BEHAVIORAL_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__fill ();
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FILL_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NAND3_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__NAND3_FUNCTIONAL_PP_V
+
+/**
+ * nand3: 3-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__nand3 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out_Y      , B, A, C                );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND3_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND2B_4_V
+`define SKY130_FD_SC_LS__NAND2B_4_V
+
+/**
+ * nand2b: 2-input NAND, first input inverted.
+ *
+ * Verilog wrapper for nand2b with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nand2b.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nand2b_4 (
+    Y   ,
+    A_N ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A_N ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nand2b base (
+        .Y(Y),
+        .A_N(A_N),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nand2b_4 (
+    Y  ,
+    A_N,
+    B
+);
+
+    output Y  ;
+    input  A_N;
+    input  B  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nand2b base (
+        .Y(Y),
+        .A_N(A_N),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND2B_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O31A_TB_V
+`define SKY130_FD_SC_LS__O31A_TB_V
+
+/**
+ * o31a: 3-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & B1)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o31a.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg A3;
+    reg B1;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        A3   = 1\'bX;
+        B1   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   A3   = 1\'b0;
+        #80   B1   = 1\'b0;
+        #100  VGND = 1\'b0;
+        #120  VNB  = 1\'b0;
+        #140  VPB  = 1\'b0;
+        #160  VPWR = 1\'b0;
+        #180  A1   = 1\'b1;
+        #200  A2   = 1\'b1;
+        #220  A3   = 1\'b1;
+        #240  B1   = 1\'b1;
+        #260  VGND = 1\'b1;
+        #280  VNB  = 1\'b1;
+        #300  VPB  = 1\'b1;
+        #320  VPWR = 1\'b1;
+        #340  A1   = 1\'b0;
+        #360  A2   = 1\'b0;
+        #380  A3   = 1\'b0;
+        #400  B1   = 1\'b0;
+        #420  VGND = 1\'b0;
+        #440  VNB  = 1\'b0;
+        #460  VPB  = 1\'b0;
+        #480  VPWR = 1\'b0;
+        #500  VPWR = 1\'b1;
+        #520  VPB  = 1\'b1;
+        #540  VNB  = 1\'b1;
+        #560  VGND = 1\'b1;
+        #580  B1   = 1\'b1;
+        #600  A3   = 1\'b1;
+        #620  A2   = 1\'b1;
+        #640  A1   = 1\'b1;
+        #660  VPWR = 1\'bx;
+        #680  VPB  = 1\'bx;
+        #700  VNB  = 1\'bx;
+        #720  VGND = 1\'bx;
+        #740  B1   = 1\'bx;
+        #760  A3   = 1\'bx;
+        #780  A2   = 1\'bx;
+        #800  A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__o31a dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O31A_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLXBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__DLXBP_BEHAVIORAL_PP_V
+
+/**
+ * dlxbp: Delay latch, non-inverted enable, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlxbp (
+    Q   ,
+    Q_N ,
+    D   ,
+    GATE,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    output Q_N ;
+    input  D   ;
+    input  GATE;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q       ;
+    wire GATE_delayed;
+    wire D_delayed   ;
+    reg  notifier    ;
+    wire awake       ;
+
+    //                                    Name     Output  Other arguments
+    sky130_fd_sc_ls__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
+    buf                                   buf0    (Q     , buf_Q                                        );
+    not                                   not0    (Q_N   , buf_Q                                        );
+    assign awake = ( VPWR === 1\'b1 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXBP_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFBBN_2_V
+`define SKY130_FD_SC_LS__SDFBBN_2_V
+
+/**
+ * sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
+ *         clock, complementary outputs.
+ *
+ * Verilog wrapper for sdfbbn with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__sdfbbn.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sdfbbn_2 (
+    Q      ,
+    Q_N    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_ls__sdfbbn base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .CLK_N(CLK_N),
+        .SET_B(SET_B),
+        .RESET_B(RESET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sdfbbn_2 (
+    Q      ,
+    Q_N    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__sdfbbn base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .CLK_N(CLK_N),
+        .SET_B(SET_B),
+        .RESET_B(RESET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFBBN_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR2_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__NOR2_PP_BLACKBOX_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nor2 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR2_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if (~TE_B ) (A +=> Z ) = (0:0:0,0:0:0);  // delays are tris,tfall
+(TE_B => Z ) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);  // delays are t01,t10,t0Z,tZ1,t1Z,tZ0
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O221AI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__O221AI_BEHAVIORAL_PP_V
+
+/**
+ * o221ai: 2-input OR into first two inputs of 3-input NAND.
+ *
+ *         Y = !((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__o221ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire or1_out          ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , B2, B1                 );
+    or                                 or1         (or1_out          , A2, A1                 );
+    nand                               nand0       (nand0_out_Y      , or1_out, or0_out, C1   );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O221AI_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DECAPHETAP_2_V
+`define SKY130_FD_SC_LS__DECAPHETAP_2_V
+
+/**
+
+ *
+ * Verilog wrapper for decaphetap with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__decaphetap.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__decaphetap_2 (
+    VPWR,
+    VGND,
+    VPB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    sky130_fd_sc_ls__decaphetap base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__decaphetap_2 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+
+    sky130_fd_sc_ls__decaphetap base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DECAPHETAP_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A21BOI_2_V
+`define SKY130_FD_SC_LS__A21BOI_2_V
+
+/**
+ * a21boi: 2-input AND into first input of 2-input NOR,
+ *         2nd input inverted.
+ *
+ *         Y = !((A1 & A2) | (!B1_N))
+ *
+ * Verilog wrapper for a21boi with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a21boi.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a21boi_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a21boi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a21boi_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a21boi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21BOI_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFRTN_V
+`define SKY130_FD_SC_LS__SDFRTN_V
+
+/**
+ * sdfrtn: Scan delay flop, inverted reset, inverted clock,
+ *         single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__sdfrtn.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__sdfrtn.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__sdfrtn.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__sdfrtn.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFRTN_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DIODE_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__DIODE_PP_BLACKBOX_V
+
+/**
+ * diode: Antenna tie-down diode.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__diode (
+    DIODE,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    input DIODE;
+    input VPWR ;
+    input VGND ;
+    input VPB  ;
+    input VNB  ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DIODE_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A -=> Y) = (0:0:0,0:0:0);
+(B -=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A211OI_BLACKBOX_V
+`define SKY130_FD_SC_LS__A211OI_BLACKBOX_V
+
+/**
+ * a211oi: 2-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | B1 | C1)
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a211oi (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A211OI_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND2_BLACKBOX_V
+`define SKY130_FD_SC_LS__AND2_BLACKBOX_V
+
+/**
+ * and2: 2-input AND.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__and2 (
+    X,
+    A,
+    B
+);
+
+    output X;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND2_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FILL_TB_V
+`define SKY130_FD_SC_LS__FILL_TB_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__fill.v""
+
+module top();
+
+    // Inputs are registered
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   VGND = 1\'b0;
+        #40   VNB  = 1\'b0;
+        #60   VPB  = 1\'b0;
+        #80   VPWR = 1\'b0;
+        #100  VGND = 1\'b1;
+        #120  VNB  = 1\'b1;
+        #140  VPB  = 1\'b1;
+        #160  VPWR = 1\'b1;
+        #180  VGND = 1\'b0;
+        #200  VNB  = 1\'b0;
+        #220  VPB  = 1\'b0;
+        #240  VPWR = 1\'b0;
+        #260  VPWR = 1\'b1;
+        #280  VPB  = 1\'b1;
+        #300  VNB  = 1\'b1;
+        #320  VGND = 1\'b1;
+        #340  VPWR = 1\'bx;
+        #360  VPB  = 1\'bx;
+        #380  VNB  = 1\'bx;
+        #400  VGND = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__fill dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FILL_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DECAPHETAP_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__DECAPHETAP_FUNCTIONAL_V
+
+/**
+
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__decaphetap ();
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DECAPHETAP_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O32AI_BLACKBOX_V
+`define SKY130_FD_SC_LS__O32AI_BLACKBOX_V
+
+/**
+ * o32ai: 3-input OR and 2-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o32ai (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O32AI_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NAND3B_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__NAND3B_BEHAVIORAL_PP_V
+
+/**
+ * nand3b: 3-input NAND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__nand3b (
+    Y   ,
+    A_N ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , A_N                    );
+    nand                               nand0       (nand0_out_Y      , B, not0_out, C         );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND3B_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O21AI_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__O21AI_PP_SYMBOL_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & B1)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o21ai (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  B1  ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21AI_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DFSTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__DFSTP_BEHAVIORAL_PP_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ls__udp_dff_ps_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dfstp (
+    Q    ,
+    CLK  ,
+    D    ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire buf_Q        ;
+    wire SET          ;
+    reg  notifier     ;
+    wire D_delayed    ;
+    wire SET_B_delayed;
+    wire CLK_delayed  ;
+    wire awake        ;
+    wire cond0        ;
+    wire cond1        ;
+
+    //                                  Name  Output  Other arguments
+    not                                 not0 (SET   , SET_B_delayed                                    );
+    sky130_fd_sc_ls__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    assign cond0 = ( SET_B_delayed === 1\'b1 );
+    assign cond1 = ( SET_B === 1\'b1 );
+    buf                                 buf0 (Q     , buf_Q                                            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFSTP_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD3_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__CLKDLYINV3SD3_PP_BLACKBOX_V
+
+/**
+ * clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
+ *                stage gate.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__clkdlyinv3sd3 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV3SD3_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A32O_SYMBOL_V
+`define SKY130_FD_SC_LS__A32O_SYMBOL_V
+
+/**
+ * a32o: 3-input AND into first input, and 2-input AND into
+ *       2nd input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a32o (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  A3,
+    input  B1,
+    input  B2,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A32O_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O311AI_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__O311AI_PP_SYMBOL_V
+
+/**
+ * o311ai: 3-input OR into 3-input NAND.
+ *
+ *         Y = !((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o311ai (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  A3  ,
+    input  B1  ,
+    input  C1  ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O311AI_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD2_SYMBOL_V
+`define SKY130_FD_SC_LS__CLKDLYINV3SD2_SYMBOL_V
+
+/**
+ * clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
+ *                stage gate.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__clkdlyinv3sd2 (
+    //# {{data|Data Signals}}
+    input  A,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV3SD2_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DECAPHE_3_V
+`define SKY130_FD_SC_LS__DECAPHE_3_V
+
+/**
+ * decaphe: Shielded Decoupling capacitance filler.
+ *
+ * Verilog wrapper for decaphe with size of 3 units (invalid?).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__decaphe.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__decaphe_3 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+    sky130_fd_sc_ls__decaphe base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__decaphe_3 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__decaphe base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DECAPHE_3_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DECAPHETAP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__DECAPHETAP_BEHAVIORAL_PP_V
+
+/**
+
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__decaphetap (
+    VPWR,
+    VGND,
+    VPB
+);
+
+    // Module ports
+    input VPWR;
+    input VGND;
+    input VPB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DECAPHETAP_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NAND4B_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__NAND4B_BEHAVIORAL_V
+
+/**
+ * nand4b: 4-input NAND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__nand4b (
+    Y  ,
+    A_N,
+    B  ,
+    C  ,
+    D
+);
+
+    // Module ports
+    output Y  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+    input  D  ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out   ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    not  not0  (not0_out   , A_N              );
+    nand nand0 (nand0_out_Y, D, C, B, not0_out);
+    buf  buf0  (Y          , nand0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND4B_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND2_TB_V
+`define SKY130_FD_SC_LS__NAND2_TB_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nand2.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg B;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        B    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   B    = 1\'b0;
+        #60   VGND = 1\'b0;
+        #80   VNB  = 1\'b0;
+        #100  VPB  = 1\'b0;
+        #120  VPWR = 1\'b0;
+        #140  A    = 1\'b1;
+        #160  B    = 1\'b1;
+        #180  VGND = 1\'b1;
+        #200  VNB  = 1\'b1;
+        #220  VPB  = 1\'b1;
+        #240  VPWR = 1\'b1;
+        #260  A    = 1\'b0;
+        #280  B    = 1\'b0;
+        #300  VGND = 1\'b0;
+        #320  VNB  = 1\'b0;
+        #340  VPB  = 1\'b0;
+        #360  VPWR = 1\'b0;
+        #380  VPWR = 1\'b1;
+        #400  VPB  = 1\'b1;
+        #420  VNB  = 1\'b1;
+        #440  VGND = 1\'b1;
+        #460  B    = 1\'b1;
+        #480  A    = 1\'b1;
+        #500  VPWR = 1\'bx;
+        #520  VPB  = 1\'bx;
+        #540  VNB  = 1\'bx;
+        #560  VGND = 1\'bx;
+        #580  B    = 1\'bx;
+        #600  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__nand2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND2_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+( negedge SET_B => ( Q -: SET_B ) ) = 0:0:0 ;  // delay is tris
+( posedge CLK => ( Q : CLK ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall
+$recrem ( posedge SET_B , posedge CLK , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , SETB_delayed , CLK_delayed ) ;
+$setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , CLK_delayed , D_delayed ) ;
+$setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , CLK_delayed , D_delayed ) ;
+$width ( posedge CLK &&& COND1 , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( negedge CLK &&& COND1 , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( negedge SET_B &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O211AI_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__O211AI_PP_SYMBOL_V
+
+/**
+ * o211ai: 2-input OR into first input of 3-input NAND.
+ *
+ *         Y = !((A1 | A2) & B1 & C1)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o211ai (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  B1  ,
+    input  C1  ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O211AI_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A1 -=> Y) = (0:0:0,0:0:0);
+(A2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&!B1)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&!B1)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&!B1)) (C1 -=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__AND2_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__AND2_BEHAVIORAL_PP_V
+
+/**
+ * and2: 2-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__and2 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out_X       , A, B                  );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND2_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFBBN_V
+`define SKY130_FD_SC_LS__SDFBBN_V
+
+/**
+ * sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
+ *         clock, complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__sdfbbn.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__sdfbbn.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__sdfbbn.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__sdfbbn.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFBBN_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A211O_BLACKBOX_V
+`define SKY130_FD_SC_LS__A211O_BLACKBOX_V
+
+/**
+ * a211o: 2-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2) | B1 | C1)
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a211o (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A211O_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND4BB_2_V
+`define SKY130_FD_SC_LS__AND4BB_2_V
+
+/**
+ * and4bb: 4-input AND, first two inputs inverted.
+ *
+ * Verilog wrapper for and4bb with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__and4bb.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__and4bb_2 (
+    X   ,
+    A_N ,
+    B_N ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A_N ;
+    input  B_N ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__and4bb base (
+        .X(X),
+        .A_N(A_N),
+        .B_N(B_N),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__and4bb_2 (
+    X  ,
+    A_N,
+    B_N,
+    C  ,
+    D
+);
+
+    output X  ;
+    input  A_N;
+    input  B_N;
+    input  C  ;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__and4bb base (
+        .X(X),
+        .A_N(A_N),
+        .B_N(B_N),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND4BB_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__XNOR3_TB_V
+`define SKY130_FD_SC_LS__XNOR3_TB_V
+
+/**
+ * xnor3: 3-input exclusive NOR.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__xnor3.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg B;
+    reg C;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        B    = 1\'bX;
+        C    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   B    = 1\'b0;
+        #60   C    = 1\'b0;
+        #80   VGND = 1\'b0;
+        #100  VNB  = 1\'b0;
+        #120  VPB  = 1\'b0;
+        #140  VPWR = 1\'b0;
+        #160  A    = 1\'b1;
+        #180  B    = 1\'b1;
+        #200  C    = 1\'b1;
+        #220  VGND = 1\'b1;
+        #240  VNB  = 1\'b1;
+        #260  VPB  = 1\'b1;
+        #280  VPWR = 1\'b1;
+        #300  A    = 1\'b0;
+        #320  B    = 1\'b0;
+        #340  C    = 1\'b0;
+        #360  VGND = 1\'b0;
+        #380  VNB  = 1\'b0;
+        #400  VPB  = 1\'b0;
+        #420  VPWR = 1\'b0;
+        #440  VPWR = 1\'b1;
+        #460  VPB  = 1\'b1;
+        #480  VNB  = 1\'b1;
+        #500  VGND = 1\'b1;
+        #520  C    = 1\'b1;
+        #540  B    = 1\'b1;
+        #560  A    = 1\'b1;
+        #580  VPWR = 1\'bx;
+        #600  VPB  = 1\'bx;
+        #620  VNB  = 1\'bx;
+        #640  VGND = 1\'bx;
+        #660  C    = 1\'bx;
+        #680  B    = 1\'bx;
+        #700  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__xnor3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XNOR3_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLRTN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__DLRTN_FUNCTIONAL_PP_V
+
+/**
+ * dlrtn: Delay latch, inverted reset, inverted enable, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_pr_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlrtn (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE_N ,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE_N ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire RESET  ;
+    wire intgate;
+    wire buf_Q  ;
+
+    //                                     Delay       Name     Output   Other arguments
+    not                                                not0    (RESET  , RESET_B                        );
+    not                                                not1    (intgate, GATE_N                         );
+    sky130_fd_sc_ls__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q  , D, intgate, RESET, , VPWR, VGND);
+    buf                                                buf0    (Q      , buf_Q                          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRTN_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__XOR2_SYMBOL_V
+`define SKY130_FD_SC_LS__XOR2_SYMBOL_V
+
+/**
+ * xor2: 2-input exclusive OR.
+ *
+ *       X = A ^ B
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__xor2 (
+    //# {{data|Data Signals}}
+    input  A,
+    input  B,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XOR2_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFXBP_V
+`define SKY130_FD_SC_LS__DFXBP_V
+
+/**
+ * dfxbp: Delay flop, complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dfxbp.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dfxbp.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dfxbp.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dfxbp.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFXBP_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A2111O_TB_V
+`define SKY130_FD_SC_LS__A2111O_TB_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ *         X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a2111o.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg B1;
+    reg C1;
+    reg D1;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        B1   = 1\'bX;
+        C1   = 1\'bX;
+        D1   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   B1   = 1\'b0;
+        #80   C1   = 1\'b0;
+        #100  D1   = 1\'b0;
+        #120  VGND = 1\'b0;
+        #140  VNB  = 1\'b0;
+        #160  VPB  = 1\'b0;
+        #180  VPWR = 1\'b0;
+        #200  A1   = 1\'b1;
+        #220  A2   = 1\'b1;
+        #240  B1   = 1\'b1;
+        #260  C1   = 1\'b1;
+        #280  D1   = 1\'b1;
+        #300  VGND = 1\'b1;
+        #320  VNB  = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VPWR = 1\'b1;
+        #380  A1   = 1\'b0;
+        #400  A2   = 1\'b0;
+        #420  B1   = 1\'b0;
+        #440  C1   = 1\'b0;
+        #460  D1   = 1\'b0;
+        #480  VGND = 1\'b0;
+        #500  VNB  = 1\'b0;
+        #520  VPB  = 1\'b0;
+        #540  VPWR = 1\'b0;
+        #560  VPWR = 1\'b1;
+        #580  VPB  = 1\'b1;
+        #600  VNB  = 1\'b1;
+        #620  VGND = 1\'b1;
+        #640  D1   = 1\'b1;
+        #660  C1   = 1\'b1;
+        #680  B1   = 1\'b1;
+        #700  A2   = 1\'b1;
+        #720  A1   = 1\'b1;
+        #740  VPWR = 1\'bx;
+        #760  VPB  = 1\'bx;
+        #780  VNB  = 1\'bx;
+        #800  VGND = 1\'bx;
+        #820  D1   = 1\'bx;
+        #840  C1   = 1\'bx;
+        #860  B1   = 1\'bx;
+        #880  A2   = 1\'bx;
+        #900  A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__a2111o dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .D1(D1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2111O_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLRBN_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__DLRBN_BEHAVIORAL_PP_V
+
+/**
+ * dlrbn: Delay latch, inverted reset, inverted enable,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_pr_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlrbn (
+    Q      ,
+    Q_N    ,
+    RESET_B,
+    D      ,
+    GATE_N ,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE_N ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire RESET          ;
+    wire intgate        ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire GATE_N_delayed ;
+    wire RESET_delayed  ;
+    wire RESET_B_delayed;
+    wire buf_Q          ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+
+    //                                     Name     Output   Other arguments
+    not                                    not0    (RESET  , RESET_B_delayed                                );
+    not                                    not1    (intgate, GATE_N_delayed                                 );
+    sky130_fd_sc_ls__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q  , D_delayed, intgate, RESET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1\'b1 ) );
+    assign cond1 = ( awake && ( RESET_B === 1\'b1 ) );
+    buf                                    buf0    (Q      , buf_Q                                          );
+    not                                    not2    (Q_N    , buf_Q                                          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRBN_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_PWRGOOD_PP_P_SYMBOL_V
+`define SKY130_FD_SC_LS__UDP_PWRGOOD_PP_P_SYMBOL_V
+
+/**
+
+ *   UDP_OUT :=x when VPWR!=1
+ *   UDP_OUT :=UDP_IN when VPWR==1
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__udp_pwrgood_pp$P (
+    //# {{data|Data Signals}}
+    input  UDP_IN ,
+    output UDP_OUT,
+
+    //# {{power|Power}}
+    input  VPWR
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_PWRGOOD_PP_P_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__TAPVGND2_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__TAPVGND2_BEHAVIORAL_V
+
+/**
+ * tapvgnd2: Tap cell with tap to ground, isolated power connection 2
+ *           rows down.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__tapvgnd2 ();
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPVGND2_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A -=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O211AI_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__O211AI_PP_BLACKBOX_V
+
+/**
+ * o211ai: 2-input OR into first input of 3-input NAND.
+ *
+ *         Y = !((A1 | A2) & B1 & C1)
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o211ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O211AI_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__EDFXTP_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__EDFXTP_BEHAVIORAL_V
+
+/**
+ * edfxtp: Delay flop with loopback enable, non-inverted clock,
+ *         single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+`include ""../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__edfxtp (
+    Q  ,
+    CLK,
+    D  ,
+    DE
+);
+
+    // Module ports
+    output Q  ;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q      ;
+    reg  notifier   ;
+    wire D_delayed  ;
+    wire DE_delayed ;
+    wire CLK_delayed;
+    wire mux_out    ;
+    wire awake      ;
+    wire cond0      ;
+
+    //                                 Name       Output   Other arguments
+    sky130_fd_sc_ls__udp_mux_2to1      mux_2to10 (mux_out, buf_Q, D_delayed, DE_delayed              );
+    sky130_fd_sc_ls__udp_dff$P_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    assign cond0 = ( awake && ( DE_delayed === 1\'b1 ) );
+    buf                                buf0      (Q      , buf_Q                                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EDFXTP_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFXBP_2_V
+`define SKY130_FD_SC_LS__SDFXBP_2_V
+
+/**
+ * sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
+ *
+ * Verilog wrapper for sdfxbp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__sdfxbp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sdfxbp_2 (
+    Q   ,
+    Q_N ,
+    CLK ,
+    D   ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    output Q_N ;
+    input  CLK ;
+    input  D   ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__sdfxbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sdfxbp_2 (
+    Q  ,
+    Q_N,
+    CLK,
+    D  ,
+    SCD,
+    SCE
+);
+
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+    input  SCD;
+    input  SCE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__sdfxbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFXBP_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD3_TB_V
+`define SKY130_FD_SC_LS__CLKDLYINV3SD3_TB_V
+
+/**
+ * clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
+ *                stage gate.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__clkdlyinv3sd3.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   VGND = 1\'b0;
+        #60   VNB  = 1\'b0;
+        #80   VPB  = 1\'b0;
+        #100  VPWR = 1\'b0;
+        #120  A    = 1\'b1;
+        #140  VGND = 1\'b1;
+        #160  VNB  = 1\'b1;
+        #180  VPB  = 1\'b1;
+        #200  VPWR = 1\'b1;
+        #220  A    = 1\'b0;
+        #240  VGND = 1\'b0;
+        #260  VNB  = 1\'b0;
+        #280  VPB  = 1\'b0;
+        #300  VPWR = 1\'b0;
+        #320  VPWR = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VNB  = 1\'b1;
+        #380  VGND = 1\'b1;
+        #400  A    = 1\'b1;
+        #420  VPWR = 1\'bx;
+        #440  VPB  = 1\'bx;
+        #460  VNB  = 1\'bx;
+        #480  VGND = 1\'bx;
+        #500  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__clkdlyinv3sd3 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV3SD3_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if ((A2&!B1&!B2&!C1)) (A1 -=> Y) = (0:0:0,0:0:0);
+if ((A2&!B1&B2&!C1)) (A1 -=> Y) = (0:0:0,0:0:0);
+if ((A2&B1&!B2&!C1)) (A1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!B1&!B2&!C1)) (A2 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!B1&B2&!C1)) (A2 -=> Y) = (0:0:0,0:0:0);
+if ((A1&B1&!B2&!C1)) (A2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&B2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&B2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&B2&!C1)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&B1&!C1)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&B1&!C1)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&B1&!C1)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&!B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&!B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&!B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&!B1&B2)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&B1&!B2)) (C1 -=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DFBBN_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__DFBBN_BEHAVIORAL_PP_V
+
+/**
+ * dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ls__udp_dff_nsr_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dfbbn (
+    Q      ,
+    Q_N    ,
+    D      ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire RESET          ;
+    wire SET            ;
+    wire CLK            ;
+    wire buf_Q          ;
+    wire CLK_N_delayed  ;
+    wire RESET_B_delayed;
+    wire SET_B_delayed  ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+    wire condb          ;
+
+    //                                   Name  Output  Other arguments
+    not                                  not0 (RESET , RESET_B_delayed                                 );
+    not                                  not1 (SET   , SET_B_delayed                                   );
+    not                                  not2 (CLK   , CLK_N_delayed                                   );
+    sky130_fd_sc_ls__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK, D_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1\'b1 ) );
+    assign cond1 = ( awake && ( SET_B_delayed === 1\'b1 ) );
+    assign condb = ( cond0 & cond1 );
+    buf                                  buf0 (Q     , buf_Q                                           );
+    not                                  not3 (Q_N   , buf_Q                                           );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFBBN_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLXBN_TB_V
+`define SKY130_FD_SC_LS__DLXBN_TB_V
+
+/**
+ * dlxbn: Delay latch, inverted enable, complementary outputs.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dlxbn.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Q;
+    wire Q_N;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   D    = 1\'b0;
+        #40   VGND = 1\'b0;
+        #60   VNB  = 1\'b0;
+        #80   VPB  = 1\'b0;
+        #100  VPWR = 1\'b0;
+        #120  D    = 1\'b1;
+        #140  VGND = 1\'b1;
+        #160  VNB  = 1\'b1;
+        #180  VPB  = 1\'b1;
+        #200  VPWR = 1\'b1;
+        #220  D    = 1\'b0;
+        #240  VGND = 1\'b0;
+        #260  VNB  = 1\'b0;
+        #280  VPB  = 1\'b0;
+        #300  VPWR = 1\'b0;
+        #320  VPWR = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VNB  = 1\'b1;
+        #380  VGND = 1\'b1;
+        #400  D    = 1\'b1;
+        #420  VPWR = 1\'bx;
+        #440  VPB  = 1\'bx;
+        #460  VNB  = 1\'bx;
+        #480  VGND = 1\'bx;
+        #500  D    = 1\'bx;
+    end
+
+    // Create a clock
+    reg GATE_N;
+    initial
+    begin
+        GATE_N = 1\'b0;
+    end
+
+    always
+    begin
+        #5 GATE_N = ~GATE_N;
+    end
+
+    sky130_fd_sc_ls__dlxbn dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .GATE_N(GATE_N));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXBN_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O2BB2AI_2_V
+`define SKY130_FD_SC_LS__O2BB2AI_2_V
+
+/**
+ * o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
+ *
+ *          Y = !(!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o2bb2ai with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o2bb2ai.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o2bb2ai_2 (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o2bb2ai base (
+        .Y(Y),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o2bb2ai_2 (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o2bb2ai base (
+        .Y(Y),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2BB2AI_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__EBUFN_4_V
+`define SKY130_FD_SC_LS__EBUFN_4_V
+
+/**
+ * ebufn: Tri-state buffer, negative enable.
+ *
+ * Verilog wrapper for ebufn with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__ebufn.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__ebufn_4 (
+    Z   ,
+    A   ,
+    TE_B,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__ebufn base (
+        .Z(Z),
+        .A(A),
+        .TE_B(TE_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__ebufn_4 (
+    Z   ,
+    A   ,
+    TE_B
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__ebufn base (
+        .Z(Z),
+        .A(A),
+        .TE_B(TE_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EBUFN_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O311A_SYMBOL_V
+`define SKY130_FD_SC_LS__O311A_SYMBOL_V
+
+/**
+ * o311a: 3-input OR into 3-input AND.
+ *
+ *        X = ((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o311a (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  A3,
+    input  B1,
+    input  C1,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O311A_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A1 +=> X) = (0:0:0,0:0:0);
+(A2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2)) (B1 +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A32O_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__A32O_BEHAVIORAL_V
+
+/**
+ * a32o: 3-input AND into first input, and 2-input AND into
+ *       2nd input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a32o (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out ;
+    wire and1_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , A3, A1, A2        );
+    and and1 (and1_out , B1, B2            );
+    or  or0  (or0_out_X, and1_out, and0_out);
+    buf buf0 (X        , or0_out_X         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A32O_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR3_BLACKBOX_V
+`define SKY130_FD_SC_LS__OR3_BLACKBOX_V
+
+/**
+ * or3: 3-input OR.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__or3 (
+    X,
+    A,
+    B,
+    C
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR3_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O22AI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__O22AI_BEHAVIORAL_PP_V
+
+/**
+ * o22ai: 2-input OR into both inputs of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__o22ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nor0_out         ;
+    wire nor1_out         ;
+    wire or0_out_Y        ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nor                                nor0        (nor0_out         , B1, B2               );
+    nor                                nor1        (nor1_out         , A1, A2               );
+    or                                 or0         (or0_out_Y        , nor1_out, nor0_out   );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O22AI_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A211OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__A211OI_FUNCTIONAL_PP_V
+
+/**
+ * a211oi: 2-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a211oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A1, A2                );
+    nor                                nor0        (nor0_out_Y       , and0_out, B1, C1      );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A211OI_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A222O_1_V
+`define SKY130_FD_SC_LS__A222O_1_V
+
+/**
+ * a222o: 2-input AND into all inputs of 3-input OR.
+ *
+ *        X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
+ *
+ * Verilog wrapper for a222o with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a222o.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a222o_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    C2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  C2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a222o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1),
+        .C2(C2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a222o_1 (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1,
+    C2
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+    input  C2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a222o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1),
+        .C2(C2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A222O_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND3B_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__AND3B_PP_SYMBOL_V
+
+/**
+ * and3b: 3-input AND, first input inverted.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__and3b (
+    //# {{data|Data Signals}}
+    input  A_N ,
+    input  B   ,
+    input  C   ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND3B_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FA_4_V
+`define SKY130_FD_SC_LS__FA_4_V
+
+/**
+ * fa: Full adder.
+ *
+ * Verilog wrapper for fa with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__fa.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__fa_4 (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CIN ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CIN ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__fa base (
+        .COUT(COUT),
+        .SUM(SUM),
+        .A(A),
+        .B(B),
+        .CIN(CIN),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__fa_4 (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CIN
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CIN ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__fa base (
+        .COUT(COUT),
+        .SUM(SUM),
+        .A(A),
+        .B(B),
+        .CIN(CIN)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FA_4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SDFBBP_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__SDFBBP_BEHAVIORAL_V
+
+/**
+ * sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
+ *         clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+`include ""../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ls__udp_dff_nsr_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__sdfbbp (
+    Q      ,
+    Q_N    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    CLK    ,
+    SET_B  ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  CLK    ;
+    input  SET_B  ;
+    input  RESET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire RESET          ;
+    wire SET            ;
+    wire buf_Q          ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire SCD_delayed    ;
+    wire SCE_delayed    ;
+    wire CLK_delayed    ;
+    wire SET_B_delayed  ;
+    wire RESET_B_delayed;
+    wire mux_out        ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+    wire condb          ;
+    wire cond_D         ;
+    wire cond_SCD       ;
+    wire cond_SCE       ;
+
+    //                                   Name       Output   Other arguments
+    not                                  not0      (RESET  , RESET_B_delayed                                       );
+    not                                  not1      (SET    , SET_B_delayed                                         );
+    sky130_fd_sc_ls__udp_mux_2to1        mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed                   );
+    sky130_fd_sc_ls__udp_dff$NSR_pp$PG$N dff0      (buf_Q  , SET, RESET, CLK_delayed, mux_out, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1\'b1 ) );
+    assign cond1 = ( awake && ( SET_B_delayed === 1\'b1 ) );
+    assign condb = ( cond0 & cond1 );
+    assign cond_D = ( ( SCE_delayed === 1\'b0 ) && condb );
+    assign cond_SCD = ( ( SCE_delayed === 1\'b1 ) && condb );
+    assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
+    buf                                  buf0      (Q      , buf_Q                                                 );
+    not                                  not2      (Q_N    , buf_Q                                                 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFBBP_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLCLKP_SYMBOL_V
+`define SKY130_FD_SC_LS__DLCLKP_SYMBOL_V
+
+/**
+ * dlclkp: Clock gate.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlclkp (
+    //# {{clocks|Clocking}}
+    input  CLK ,
+    input  GATE,
+    output GCLK
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLCLKP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A1 -=> Y) = (0:0:0,0:0:0);
+(A2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2)) (B1 -=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLXBP_SYMBOL_V
+`define SKY130_FD_SC_LS__DLXBP_SYMBOL_V
+
+/**
+ * dlxbp: Delay latch, non-inverted enable, complementary outputs.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlxbp (
+    //# {{data|Data Signals}}
+    input  D   ,
+    output Q   ,
+    output Q_N ,
+
+    //# {{clocks|Clocking}}
+    input  GATE
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXBP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O21BA_BLACKBOX_V
+`define SKY130_FD_SC_LS__O21BA_BLACKBOX_V
+
+/**
+ * o21ba: 2-input OR into first input of 2-input AND,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 | A2) & !B1_N)
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o21ba (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21BA_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FILL_1_V
+`define SKY130_FD_SC_LS__FILL_1_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog wrapper for fill with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__fill.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__fill_1 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+    sky130_fd_sc_ls__fill base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__fill_1 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__fill base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FILL_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NOR4_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__NOR4_FUNCTIONAL_V
+
+/**
+ * nor4: 4-input NOR.
+ *
+ *       Y = !(A | B | C | D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__nor4 (
+    Y,
+    A,
+    B,
+    C,
+    D
+);
+
+    // Module ports
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Local signals
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    nor nor0 (nor0_out_Y, A, B, C, D     );
+    buf buf0 (Y         , nor0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR4_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if ((!A1&!A2&!A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&!A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&!A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2&!A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2&A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0);
+if ((!A0&!A2&!A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((!A0&!A2&A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((!A0&A2&!A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((!A0&A2&A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((A0&!A2&!A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((A0&!A2&A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((A0&A2&!A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((A0&A2&A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((!A0&!A1&!A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((!A0&!A1&A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((!A0&A1&!A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((!A0&A1&A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((A0&!A1&!A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((A0&!A1&A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((A0&A1&!A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((A0&A1&A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((!A0&!A1&!A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0);
+if ((!A0&!A1&A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0);
+if ((!A0&A1&!A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0);
+if ((!A0&A1&A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0);
+if ((A0&!A1&!A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0);
+if ((A0&!A1&A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0);
+if ((A0&A1&!A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0);
+if ((A0&A1&A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0);
+if ((!A0&!A1&!A2&A3&S1)) (S0 +=> X) = (0:0:0,0:0:0);
+if ((!A0&!A1&A2&!A3&S1)) (S0 -=> X) = (0:0:0,0:0:0);
+if ((!A0&A1&!A2&!A3&!S1)) (S0 +=> X) = (0:0:0,0:0:0);
+if ((!A0&A1&!A2&A3&!S1)) (S0 +=> X) = (0:0:0,0:0:0);
+if ((!A0&A1&!A2&A3&S1)) (S0 +=> X) = (0:0:0,0:0:0);
+if ((!A0&A1&A2&!A3&!S1)) (S0 +=> X) = (0:0:0,0:0:0);
+if ((!A0&A1&A2&!A3&S1)) (S0 -=> X) = (0:0:0,0:0:0);
+if ((!A0&A1&A2&A3&!S1)) (S0 +=> X) = (0:0:0,0:0:0);
+if ((A0&!A1&!A2&!A3&!S1)) (S0 -=> X) = (0:0:0,0:0:0);
+if ((A0&!A1&!A2&A3&!S1)) (S0 -=> X) = (0:0:0,0:0:0);
+if ((A0&!A1&!A2&A3&S1)) (S0 +=> X) = (0:0:0,0:0:0);
+if ((A0&!A1&A2&!A3&!S1)) (S0 -=> X) = (0:0:0,0:0:0);
+if ((A0&!A1&A2&!A3&S1)) (S0 -=> X) = (0:0:0,0:0:0);
+if ((A0&!A1&A2&A3&!S1)) (S0 -=> X) = (0:0:0,0:0:0);
+if ((A0&A1&!A2&A3&S1)) (S0 +=> X) = (0:0:0,0:0:0);
+if ((A0&A1&A2&!A3&S1)) (S0 -=> X) = (0:0:0,0:0:0);
+if ((!A0&!A1&!A2&A3&S0)) (S1 +=> X) = (0:0:0,0:0:0);
+if ((!A0&!A1&A2&!A3&!S0)) (S1 +=> X) = (0:0:0,0:0:0);
+if ((!A0&!A1&A2&A3&!S0)) (S1 +=> X) = (0:0:0,0:0:0);
+if ((!A0&!A1&A2&A3&S0)) (S1 +=> X) = (0:0:0,0:0:0);
+if ((!A0&A1&!A2&!A3&S0)) (S1 -=> X) = (0:0:0,0:0:0);
+if ((!A0&A1&A2&!A3&!S0)) (S1 +=> X) = (0:0:0,0:0:0);
+if ((!A0&A1&A2&!A3&S0)) (S1 -=> X) = (0:0:0,0:0:0);
+if ((!A0&A1&A2&A3&!S0)) (S1 +=> X) = (0:0:0,0:0:0);
+if ((A0&!A1&!A2&!A3&!S0)) (S1 -=> X) = (0:0:0,0:0:0);
+if ((A0&!A1&!A2&A3&!S0)) (S1 -=> X) = (0:0:0,0:0:0);
+if ((A0&!A1&!A2&A3&S0)) (S1 +=> X) = (0:0:0,0:0:0);
+if ((A0&!A1&A2&A3&S0)) (S1 +=> X) = (0:0:0,0:0:0);
+if ((A0&A1&!A2&!A3&!S0)) (S1 -=> X) = (0:0:0,0:0:0);
+if ((A0&A1&!A2&!A3&S0)) (S1 -=> X) = (0:0:0,0:0:0);
+if ((A0&A1&!A2&A3&!S0)) (S1 -=> X) = (0:0:0,0:0:0);
+if ((A0&A1&A2&!A3&S0)) (S1 -=> X) = (0:0:0,0:0:0);
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A1 +=> X) = (0:0:0,0:0:0);
+(A2 +=> X) = (0:0:0,0:0:0);
+(A3 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&A3)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&A3)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&A3)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2&A3)) (B1 +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A22OI_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__A22OI_PP_BLACKBOX_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a22oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A22OI_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A21BO_1_V
+`define SKY130_FD_SC_LS__A21BO_1_V
+
+/**
+ * a21bo: 2-input AND into first input of 2-input OR,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 & A2) | (!B1_N))
+ *
+ * Verilog wrapper for a21bo with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a21bo.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a21bo_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a21bo base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a21bo_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a21bo base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21BO_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A21OI_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__A21OI_PP_SYMBOL_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | B1)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a21oi (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  B1  ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21OI_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DFSBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__DFSBP_BEHAVIORAL_PP_V
+
+/**
+ * dfsbp: Delay flop, inverted set, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ls__udp_dff_ps_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dfsbp (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire buf_Q        ;
+    wire SET          ;
+    reg  notifier     ;
+    wire D_delayed    ;
+    wire SET_B_delayed;
+    wire CLK_delayed  ;
+    wire awake        ;
+    wire cond0        ;
+    wire cond1        ;
+
+    //                                  Name  Output  Other arguments
+    not                                 not0 (SET   , SET_B_delayed                                    );
+    sky130_fd_sc_ls__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    assign cond0 = ( SET_B_delayed === 1\'b1 );
+    assign cond1 = ( SET_B === 1\'b1 );
+    buf                                 buf0 (Q     , buf_Q                                            );
+    not                                 not1 (Q_N   , buf_Q                                            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFSBP_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A41OI_2_V
+`define SKY130_FD_SC_LS__A41OI_2_V
+
+/**
+ * a41oi: 4-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog wrapper for a41oi with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a41oi.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a41oi_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a41oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a41oi_2 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a41oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A41OI_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O41AI_TB_V
+`define SKY130_FD_SC_LS__O41AI_TB_V
+
+/**
+ * o41ai: 4-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3 | A4) & B1)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o41ai.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg A3;
+    reg A4;
+    reg B1;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        A3   = 1\'bX;
+        A4   = 1\'bX;
+        B1   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   A3   = 1\'b0;
+        #80   A4   = 1\'b0;
+        #100  B1   = 1\'b0;
+        #120  VGND = 1\'b0;
+        #140  VNB  = 1\'b0;
+        #160  VPB  = 1\'b0;
+        #180  VPWR = 1\'b0;
+        #200  A1   = 1\'b1;
+        #220  A2   = 1\'b1;
+        #240  A3   = 1\'b1;
+        #260  A4   = 1\'b1;
+        #280  B1   = 1\'b1;
+        #300  VGND = 1\'b1;
+        #320  VNB  = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VPWR = 1\'b1;
+        #380  A1   = 1\'b0;
+        #400  A2   = 1\'b0;
+        #420  A3   = 1\'b0;
+        #440  A4   = 1\'b0;
+        #460  B1   = 1\'b0;
+        #480  VGND = 1\'b0;
+        #500  VNB  = 1\'b0;
+        #520  VPB  = 1\'b0;
+        #540  VPWR = 1\'b0;
+        #560  VPWR = 1\'b1;
+        #580  VPB  = 1\'b1;
+        #600  VNB  = 1\'b1;
+        #620  VGND = 1\'b1;
+        #640  B1   = 1\'b1;
+        #660  A4   = 1\'b1;
+        #680  A3   = 1\'b1;
+        #700  A2   = 1\'b1;
+        #720  A1   = 1\'b1;
+        #740  VPWR = 1\'bx;
+        #760  VPB  = 1\'bx;
+        #780  VNB  = 1\'bx;
+        #800  VGND = 1\'bx;
+        #820  B1   = 1\'bx;
+        #840  A4   = 1\'bx;
+        #860  A3   = 1\'bx;
+        #880  A2   = 1\'bx;
+        #900  A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__o41ai dut (.A1(A1), .A2(A2), .A3(A3), .A4(A4), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O41AI_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O21BA_SYMBOL_V
+`define SKY130_FD_SC_LS__O21BA_SYMBOL_V
+
+/**
+ * o21ba: 2-input OR into first input of 2-input AND,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 | A2) & !B1_N)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o21ba (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  B1_N,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21BA_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O31AI_TB_V
+`define SKY130_FD_SC_LS__O31AI_TB_V
+
+/**
+ * o31ai: 3-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3) & B1)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o31ai.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg A3;
+    reg B1;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        A3   = 1\'bX;
+        B1   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   A3   = 1\'b0;
+        #80   B1   = 1\'b0;
+        #100  VGND = 1\'b0;
+        #120  VNB  = 1\'b0;
+        #140  VPB  = 1\'b0;
+        #160  VPWR = 1\'b0;
+        #180  A1   = 1\'b1;
+        #200  A2   = 1\'b1;
+        #220  A3   = 1\'b1;
+        #240  B1   = 1\'b1;
+        #260  VGND = 1\'b1;
+        #280  VNB  = 1\'b1;
+        #300  VPB  = 1\'b1;
+        #320  VPWR = 1\'b1;
+        #340  A1   = 1\'b0;
+        #360  A2   = 1\'b0;
+        #380  A3   = 1\'b0;
+        #400  B1   = 1\'b0;
+        #420  VGND = 1\'b0;
+        #440  VNB  = 1\'b0;
+        #460  VPB  = 1\'b0;
+        #480  VPWR = 1\'b0;
+        #500  VPWR = 1\'b1;
+        #520  VPB  = 1\'b1;
+        #540  VNB  = 1\'b1;
+        #560  VGND = 1\'b1;
+        #580  B1   = 1\'b1;
+        #600  A3   = 1\'b1;
+        #620  A2   = 1\'b1;
+        #640  A1   = 1\'b1;
+        #660  VPWR = 1\'bx;
+        #680  VPB  = 1\'bx;
+        #700  VNB  = 1\'bx;
+        #720  VGND = 1\'bx;
+        #740  B1   = 1\'bx;
+        #760  A3   = 1\'bx;
+        #780  A2   = 1\'bx;
+        #800  A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__o31ai dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O31AI_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A32O_4_V
+`define SKY130_FD_SC_LS__A32O_4_V
+
+/**
+ * a32o: 3-input AND into first input, and 2-input AND into
+ *       2nd input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog wrapper for a32o with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a32o.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a32o_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a32o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a32o_4 (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a32o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A32O_4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SDFSTP_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__SDFSTP_FUNCTIONAL_V
+
+/**
+ * sdfstp: Scan delay flop, inverted set, non-inverted clock,
+ *         single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+`include ""../../models/udp_dff_ps/sky130_fd_sc_ls__udp_dff_ps.v""
+
+`celldefine
+module sky130_fd_sc_ls__sdfstp (
+    Q    ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B
+);
+
+    // Module ports
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+
+    // Local signals
+    wire buf_Q  ;
+    wire SET    ;
+    wire mux_out;
+
+    //                            Delay       Name       Output   Other arguments
+    not                                       not0      (SET    , SET_B            );
+    sky130_fd_sc_ls__udp_mux_2to1             mux_2to10 (mux_out, D, SCD, SCE      );
+    sky130_fd_sc_ls__udp_dff$PS   `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK, SET);
+    buf                                       buf0      (Q      , buf_Q            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFSTP_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__EINVN_1_V
+`define SKY130_FD_SC_LS__EINVN_1_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog wrapper for einvn with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__einvn.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__einvn_1 (
+    Z   ,
+    A   ,
+    TE_B,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__einvn base (
+        .Z(Z),
+        .A(A),
+        .TE_B(TE_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__einvn_1 (
+    Z   ,
+    A   ,
+    TE_B
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__einvn base (
+        .Z(Z),
+        .A(A),
+        .TE_B(TE_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EINVN_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLYMETAL6S6S_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__DLYMETAL6S6S_FUNCTIONAL_V
+
+/**
+ * dlymetal6s6s: 6-inverter delay with output from 6th inverter on
+ *               horizontal route.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__dlymetal6s6s (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYMETAL6S6S_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O41AI_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__O41AI_BEHAVIORAL_V
+
+/**
+ * o41ai: 4-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__o41ai (
+    Y ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out    ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    or   or0   (or0_out    , A4, A3, A2, A1 );
+    nand nand0 (nand0_out_Y, B1, or0_out    );
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O41AI_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__AND2_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__AND2_BEHAVIORAL_V
+
+/**
+ * and2: 2-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__and2 (
+    X,
+    A,
+    B
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out_X, A, B           );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND2_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DECAPHETAP_SYMBOL_V
+`define SKY130_FD_SC_LS__DECAPHETAP_SYMBOL_V
+
+/**
+
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__decaphetap ();
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DECAPHETAP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__EDFXBP_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__EDFXBP_PP_SYMBOL_V
+
+/**
+ * edfxbp: Delay flop with loopback enable, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__edfxbp (
+    //# {{data|Data Signals}}
+    input  D   ,
+    output Q   ,
+    output Q_N ,
+
+    //# {{control|Control Signals}}
+    input  DE  ,
+
+    //# {{clocks|Clocking}}
+    input  CLK ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EDFXBP_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__INV_1_V
+`define SKY130_FD_SC_LS__INV_1_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog wrapper for inv with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__inv.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__inv_1 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__inv base (
+        .Y(Y),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__inv_1 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__inv base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__INV_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND3_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__NAND3_PP_SYMBOL_V
+
+/**
+ * nand3: 3-input NAND.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nand3 (
+    //# {{data|Data Signals}}
+    input  A   ,
+    input  B   ,
+    input  C   ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND3_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR3B_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__OR3B_PP_SYMBOL_V
+
+/**
+ * or3b: 3-input OR, first input inverted.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__or3b (
+    //# {{data|Data Signals}}
+    input  A   ,
+    input  B   ,
+    input  C_N ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR3B_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD2_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__CLKDLYINV5SD2_BEHAVIORAL_PP_V
+
+/**
+ * clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
+ *                stage gate.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__clkdlyinv5sd2 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out_Y       , A                     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV5SD2_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND2B_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__AND2B_PP_BLACKBOX_V
+
+/**
+ * and2b: 2-input AND, first input inverted.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__and2b (
+    X   ,
+    A_N ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A_N ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND2B_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O2111A_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__O2111A_FUNCTIONAL_V
+
+/**
+ * o2111a: 2-input OR into first input of 4-input AND.
+ *
+ *         X = ((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__o2111a (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Local signals
+    wire or0_out   ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    or  or0  (or0_out   , A2, A1             );
+    and and0 (and0_out_X, B1, C1, or0_out, D1);
+    buf buf0 (X         , and0_out_X         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2111A_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR2_2_V
+`define SKY130_FD_SC_LS__OR2_2_V
+
+/**
+ * or2: 2-input OR.
+ *
+ * Verilog wrapper for or2 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__or2.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__or2_2 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__or2 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__or2_2 (
+    X,
+    A,
+    B
+);
+
+    output X;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__or2 base (
+        .X(X),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR2_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A31OI_TB_V
+`define SKY130_FD_SC_LS__A31OI_TB_V
+
+/**
+ * a31oi: 3-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | B1)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a31oi.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg A3;
+    reg B1;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        A3   = 1\'bX;
+        B1   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   A3   = 1\'b0;
+        #80   B1   = 1\'b0;
+        #100  VGND = 1\'b0;
+        #120  VNB  = 1\'b0;
+        #140  VPB  = 1\'b0;
+        #160  VPWR = 1\'b0;
+        #180  A1   = 1\'b1;
+        #200  A2   = 1\'b1;
+        #220  A3   = 1\'b1;
+        #240  B1   = 1\'b1;
+        #260  VGND = 1\'b1;
+        #280  VNB  = 1\'b1;
+        #300  VPB  = 1\'b1;
+        #320  VPWR = 1\'b1;
+        #340  A1   = 1\'b0;
+        #360  A2   = 1\'b0;
+        #380  A3   = 1\'b0;
+        #400  B1   = 1\'b0;
+        #420  VGND = 1\'b0;
+        #440  VNB  = 1\'b0;
+        #460  VPB  = 1\'b0;
+        #480  VPWR = 1\'b0;
+        #500  VPWR = 1\'b1;
+        #520  VPB  = 1\'b1;
+        #540  VNB  = 1\'b1;
+        #560  VGND = 1\'b1;
+        #580  B1   = 1\'b1;
+        #600  A3   = 1\'b1;
+        #620  A2   = 1\'b1;
+        #640  A1   = 1\'b1;
+        #660  VPWR = 1\'bx;
+        #680  VPB  = 1\'bx;
+        #700  VNB  = 1\'bx;
+        #720  VGND = 1\'bx;
+        #740  B1   = 1\'bx;
+        #760  A3   = 1\'bx;
+        #780  A2   = 1\'bx;
+        #800  A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__a31oi dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A31OI_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLRTP_1_V
+`define SKY130_FD_SC_LS__DLRTP_1_V
+
+/**
+ * dlrtp: Delay latch, inverted reset, non-inverted enable,
+ *        single output.
+ *
+ * Verilog wrapper for dlrtp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dlrtp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dlrtp_1 (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE   ,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_ls__dlrtp base (
+        .Q(Q),
+        .RESET_B(RESET_B),
+        .D(D),
+        .GATE(GATE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dlrtp_1 (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE
+);
+
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__dlrtp base (
+        .Q(Q),
+        .RESET_B(RESET_B),
+        .D(D),
+        .GATE(GATE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRTP_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND4_V
+`define SKY130_FD_SC_LS__AND4_V
+
+/**
+ * and4: 4-input AND.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__and4.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__and4.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__and4.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__and4.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SDFXBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__SDFXBP_FUNCTIONAL_PP_V
+
+/**
+ * sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+`include ""../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__sdfxbp (
+    Q   ,
+    Q_N ,
+    CLK ,
+    D   ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    output Q_N ;
+    input  CLK ;
+    input  D   ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q  ;
+    wire mux_out;
+
+    //                                 Delay       Name       Output   Other arguments
+    sky130_fd_sc_ls__udp_mux_2to1                  mux_2to10 (mux_out, D, SCD, SCE               );
+    sky130_fd_sc_ls__udp_dff$P_pp$PG$N `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK, , VPWR, VGND);
+    buf                                            buf0      (Q      , buf_Q                     );
+    not                                            not0      (Q_N    , buf_Q                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFXBP_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A -=> Y) = (0:0:0,0:0:0);
+(B -=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NOR2_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__NOR2_FUNCTIONAL_PP_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__nor2 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nor                                nor0        (nor0_out_Y       , A, B                  );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR2_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__FAHCON_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__FAHCON_BEHAVIORAL_V
+
+/**
+ * fahcon: Full adder, inverted carry in, inverted carry out.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__fahcon (
+    COUT_N,
+    SUM   ,
+    A     ,
+    B     ,
+    CI
+);
+
+    // Module ports
+    output COUT_N;
+    output SUM   ;
+    input  A     ;
+    input  B     ;
+    input  CI    ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire xor0_out_SUM ;
+    wire a_b          ;
+    wire a_ci         ;
+    wire b_ci         ;
+    wire or0_out_coutn;
+
+    //  Name  Output         Other arguments
+    xor xor0 (xor0_out_SUM , A, B, CI       );
+    buf buf0 (SUM          , xor0_out_SUM   );
+    nor nor0 (a_b          , A, B           );
+    nor nor1 (a_ci         , A, CI          );
+    nor nor2 (b_ci         , B, CI          );
+    or  or0  (or0_out_coutn, a_b, a_ci, b_ci);
+    buf buf1 (COUT_N       , or0_out_coutn  );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FAHCON_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR4BB_V
+`define SKY130_FD_SC_LS__NOR4BB_V
+
+/**
+ * nor4bb: 4-input NOR, first two inputs inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__nor4bb.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__nor4bb.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__nor4bb.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__nor4bb.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR4BB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A21O_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__A21O_BEHAVIORAL_V
+
+/**
+ * a21o: 2-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a21o (
+    X ,
+    A1,
+    A2,
+    B1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , A1, A2         );
+    or  or0  (or0_out_X, and0_out, B1   );
+    buf buf0 (X        , or0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21O_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD1_BLACKBOX_V
+`define SKY130_FD_SC_LS__CLKDLYINV3SD1_BLACKBOX_V
+
+/**
+ * clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
+ *                stage gate.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__clkdlyinv3sd1 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV3SD1_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A1 -=> Y) = (0:0:0,0:0:0);
+(A2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2)) (B1_N +=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2)) (B1_N +=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2)) (B1_N +=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLYGATE4SD1_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__DLYGATE4SD1_FUNCTIONAL_PP_V
+
+/**
+ * dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlygate4sd1 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYGATE4SD1_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLRBP_SYMBOL_V
+`define SKY130_FD_SC_LS__DLRBP_SYMBOL_V
+
+/**
+ * dlrbp: Delay latch, inverted reset, non-inverted enable,
+ *        complementary outputs.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlrbp (
+    //# {{data|Data Signals}}
+    input  D      ,
+    output Q      ,
+    output Q_N    ,
+
+    //# {{control|Control Signals}}
+    input  RESET_B,
+
+    //# {{clocks|Clocking}}
+    input  GATE
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRBP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A2111OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__A2111OI_BEHAVIORAL_PP_V
+
+/**
+ * a2111oi: 2-input AND into first input of 4-input NOR.
+ *
+ *          Y = !((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a2111oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A1, A2                );
+    nor                                nor0        (nor0_out_Y       , B1, C1, D1, and0_out  );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2111OI_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFXTP_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__DFXTP_PP_BLACKBOX_V
+
+/**
+ * dfxtp: Delay flop, single output.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dfxtp (
+    Q   ,
+    CLK ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFXTP_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND4B_BLACKBOX_V
+`define SKY130_FD_SC_LS__NAND4B_BLACKBOX_V
+
+/**
+ * nand4b: 4-input NAND, first input inverted.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nand4b (
+    Y  ,
+    A_N,
+    B  ,
+    C  ,
+    D
+);
+
+    output Y  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND4B_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__EDFXTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__EDFXTP_BEHAVIORAL_PP_V
+
+/**
+ * edfxtp: Delay flop with loopback enable, non-inverted clock,
+ *         single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+`include ""../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__edfxtp (
+    Q   ,
+    CLK ,
+    D   ,
+    DE  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  DE  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q      ;
+    reg  notifier   ;
+    wire D_delayed  ;
+    wire DE_delayed ;
+    wire CLK_delayed;
+    wire mux_out    ;
+    wire awake      ;
+    wire cond0      ;
+
+    //                                 Name       Output   Other arguments
+    sky130_fd_sc_ls__udp_mux_2to1      mux_2to10 (mux_out, buf_Q, D_delayed, DE_delayed              );
+    sky130_fd_sc_ls__udp_dff$P_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    assign cond0 = ( awake && ( DE_delayed === 1\'b1 ) );
+    buf                                buf0      (Q      , buf_Q                                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EDFXTP_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SDFXBP_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__SDFXBP_FUNCTIONAL_V
+
+/**
+ * sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+`include ""../../models/udp_dff_p/sky130_fd_sc_ls__udp_dff_p.v""
+
+`celldefine
+module sky130_fd_sc_ls__sdfxbp (
+    Q  ,
+    Q_N,
+    CLK,
+    D  ,
+    SCD,
+    SCE
+);
+
+    // Module ports
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+    input  SCD;
+    input  SCE;
+
+    // Local signals
+    wire buf_Q  ;
+    wire mux_out;
+
+    //                            Delay       Name       Output   Other arguments
+    sky130_fd_sc_ls__udp_mux_2to1             mux_2to10 (mux_out, D, SCD, SCE    );
+    sky130_fd_sc_ls__udp_dff$P    `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK   );
+    buf                                       buf0      (Q      , buf_Q          );
+    not                                       not0      (Q_N    , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFXBP_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND2B_V
+`define SKY130_FD_SC_LS__AND2B_V
+
+/**
+ * and2b: 2-input AND, first input inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__and2b.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__and2b.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__and2b.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__and2b.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND2B_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A41OI_1_V
+`define SKY130_FD_SC_LS__A41OI_1_V
+
+/**
+ * a41oi: 4-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog wrapper for a41oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a41oi.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a41oi_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a41oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a41oi_1 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a41oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A41OI_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O22AI_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__O22AI_FUNCTIONAL_V
+
+/**
+ * o22ai: 2-input OR into both inputs of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__o22ai (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Local signals
+    wire nor0_out ;
+    wire nor1_out ;
+    wire or0_out_Y;
+
+    //  Name  Output     Other arguments
+    nor nor0 (nor0_out , B1, B2            );
+    nor nor1 (nor1_out , A1, A2            );
+    or  or0  (or0_out_Y, nor1_out, nor0_out);
+    buf buf0 (Y        , or0_out_Y         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O22AI_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR3_1_V
+`define SKY130_FD_SC_LS__OR3_1_V
+
+/**
+ * or3: 3-input OR.
+ *
+ * Verilog wrapper for or3 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__or3.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__or3_1 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__or3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__or3_1 (
+    X,
+    A,
+    B,
+    C
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__or3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR3_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A2111O_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__A2111O_FUNCTIONAL_PP_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ *         X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a2111o (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A1, A2               );
+    or                                 or0         (or0_out_X        , C1, B1, and0_out, D1 );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2111O_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A21BOI_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__A21BOI_FUNCTIONAL_V
+
+/**
+ * a21boi: 2-input AND into first input of 2-input NOR,
+ *         2nd input inverted.
+ *
+ *         Y = !((A1 & A2) | (!B1_N))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a21boi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Local signals
+    wire b         ;
+    wire and0_out  ;
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (b         , B1_N           );
+    and and0 (and0_out  , A1, A2         );
+    nor nor0 (nor0_out_Y, b, and0_out    );
+    buf buf0 (Y         , nor0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21BOI_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NAND2_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__NAND2_BEHAVIORAL_PP_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__nand2 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out_Y      , B, A                   );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND2_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__BUF_4_V
+`define SKY130_FD_SC_LS__BUF_4_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog wrapper for buf with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__buf.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__buf_4 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__buf base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__buf_4 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__buf base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__BUF_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SEDFXBP_BLACKBOX_V
+`define SKY130_FD_SC_LS__SEDFXBP_BLACKBOX_V
+
+/**
+ * sedfxbp: Scan delay flop, data enable, non-inverted clock,
+ *          complementary outputs.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sedfxbp (
+    Q  ,
+    Q_N,
+    CLK,
+    D  ,
+    DE ,
+    SCD,
+    SCE
+);
+
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+    input  SCD;
+    input  SCE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SEDFXBP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A31OI_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__A31OI_PP_SYMBOL_V
+
+/**
+ * a31oi: 3-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | B1)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a31oi (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  A3  ,
+    input  B1  ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A31OI_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SDFBBN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__SDFBBN_FUNCTIONAL_PP_V
+
+/**
+ * sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
+ *         clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+`include ""../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ls__udp_dff_nsr_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__sdfbbn (
+    Q      ,
+    Q_N    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire RESET  ;
+    wire SET    ;
+    wire CLK    ;
+    wire buf_Q  ;
+    wire mux_out;
+
+    //                                   Delay       Name       Output   Other arguments
+    not                                              not0      (RESET  , RESET_B                               );
+    not                                              not1      (SET    , SET_B                                 );
+    not                                              not2      (CLK    , CLK_N                                 );
+    sky130_fd_sc_ls__udp_mux_2to1                    mux_2to10 (mux_out, D, SCD, SCE                           );
+    sky130_fd_sc_ls__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0      (buf_Q  , SET, RESET, CLK, mux_out, , VPWR, VGND);
+    buf                                              buf0      (Q      , buf_Q                                 );
+    not                                              not3      (Q_N    , buf_Q                                 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFBBN_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__BUFBUF_TB_V
+`define SKY130_FD_SC_LS__BUFBUF_TB_V
+
+/**
+ * bufbuf: Double buffer.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__bufbuf.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   VGND = 1\'b0;
+        #60   VNB  = 1\'b0;
+        #80   VPB  = 1\'b0;
+        #100  VPWR = 1\'b0;
+        #120  A    = 1\'b1;
+        #140  VGND = 1\'b1;
+        #160  VNB  = 1\'b1;
+        #180  VPB  = 1\'b1;
+        #200  VPWR = 1\'b1;
+        #220  A    = 1\'b0;
+        #240  VGND = 1\'b0;
+        #260  VNB  = 1\'b0;
+        #280  VPB  = 1\'b0;
+        #300  VPWR = 1\'b0;
+        #320  VPWR = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VNB  = 1\'b1;
+        #380  VGND = 1\'b1;
+        #400  A    = 1\'b1;
+        #420  VPWR = 1\'bx;
+        #440  VPB  = 1\'bx;
+        #460  VNB  = 1\'bx;
+        #480  VGND = 1\'bx;
+        #500  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__bufbuf dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__BUFBUF_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A211OI_4_V
+`define SKY130_FD_SC_LS__A211OI_4_V
+
+/**
+ * a211oi: 2-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | B1 | C1)
+ *
+ * Verilog wrapper for a211oi with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a211oi.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a211oi_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a211oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a211oi_4 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a211oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A211OI_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__XOR2_4_V
+`define SKY130_FD_SC_LS__XOR2_4_V
+
+/**
+ * xor2: 2-input exclusive OR.
+ *
+ *       X = A ^ B
+ *
+ * Verilog wrapper for xor2 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__xor2.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__xor2_4 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__xor2 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__xor2_4 (
+    X,
+    A,
+    B
+);
+
+    output X;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__xor2 base (
+        .X(X),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XOR2_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A2111O_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__A2111O_PP_BLACKBOX_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ *         X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a2111o (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2111O_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A21BOI_SYMBOL_V
+`define SKY130_FD_SC_LS__A21BOI_SYMBOL_V
+
+/**
+ * a21boi: 2-input AND into first input of 2-input NOR,
+ *         2nd input inverted.
+ *
+ *         Y = !((A1 & A2) | (!B1_N))
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a21boi (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  B1_N,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21BOI_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD3_BLACKBOX_V
+`define SKY130_FD_SC_LS__CLKDLYINV5SD3_BLACKBOX_V
+
+/**
+ * clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
+ *                stage gate.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__clkdlyinv5sd3 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV5SD3_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND3_BLACKBOX_V
+`define SKY130_FD_SC_LS__AND3_BLACKBOX_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__and3 (
+    X,
+    A,
+    B,
+    C
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND3_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__MUX2I_TB_V
+`define SKY130_FD_SC_LS__MUX2I_TB_V
+
+/**
+ * mux2i: 2-input multiplexer, output inverted.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__mux2i.v""
+
+module top();
+
+    // Inputs are registered
+    reg A0;
+    reg A1;
+    reg S;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A0   = 1\'bX;
+        A1   = 1\'bX;
+        S    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A0   = 1\'b0;
+        #40   A1   = 1\'b0;
+        #60   S    = 1\'b0;
+        #80   VGND = 1\'b0;
+        #100  VNB  = 1\'b0;
+        #120  VPB  = 1\'b0;
+        #140  VPWR = 1\'b0;
+        #160  A0   = 1\'b1;
+        #180  A1   = 1\'b1;
+        #200  S    = 1\'b1;
+        #220  VGND = 1\'b1;
+        #240  VNB  = 1\'b1;
+        #260  VPB  = 1\'b1;
+        #280  VPWR = 1\'b1;
+        #300  A0   = 1\'b0;
+        #320  A1   = 1\'b0;
+        #340  S    = 1\'b0;
+        #360  VGND = 1\'b0;
+        #380  VNB  = 1\'b0;
+        #400  VPB  = 1\'b0;
+        #420  VPWR = 1\'b0;
+        #440  VPWR = 1\'b1;
+        #460  VPB  = 1\'b1;
+        #480  VNB  = 1\'b1;
+        #500  VGND = 1\'b1;
+        #520  S    = 1\'b1;
+        #540  A1   = 1\'b1;
+        #560  A0   = 1\'b1;
+        #580  VPWR = 1\'bx;
+        #600  VPB  = 1\'bx;
+        #620  VNB  = 1\'bx;
+        #640  VGND = 1\'bx;
+        #660  S    = 1\'bx;
+        #680  A1   = 1\'bx;
+        #700  A0   = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__mux2i dut (.A0(A0), .A1(A1), .S(S), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MUX2I_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__FAHCIN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__FAHCIN_FUNCTIONAL_PP_V
+
+/**
+ * fahcin: Full adder, inverted carry in.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__fahcin (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CIN ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CIN ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire ci                  ;
+    wire xor0_out_SUM        ;
+    wire pwrgood_pp0_out_SUM ;
+    wire a_b                 ;
+    wire a_ci                ;
+    wire b_ci                ;
+    wire or0_out_COUT        ;
+    wire pwrgood_pp1_out_COUT;
+
+    //                                 Name         Output                Other arguments
+    not                                not0        (ci                  , CIN                     );
+    xor                                xor0        (xor0_out_SUM        , A, B, ci                );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
+    buf                                buf0        (SUM                 , pwrgood_pp0_out_SUM     );
+    and                                and0        (a_b                 , A, B                    );
+    and                                and1        (a_ci                , A, ci                   );
+    and                                and2        (b_ci                , B, ci                   );
+    or                                 or0         (or0_out_COUT        , a_b, a_ci, b_ci         );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
+    buf                                buf1        (COUT                , pwrgood_pp1_out_COUT    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FAHCIN_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A2BB2OI_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__A2BB2OI_PP_SYMBOL_V
+
+/**
+ * a2bb2oi: 2-input AND, both inputs inverted, into first input, and
+ *          2-input AND into 2nd input of 2-input NOR.
+ *
+ *          Y = !((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a2bb2oi (
+    //# {{data|Data Signals}}
+    input  A1_N,
+    input  A2_N,
+    input  B1  ,
+    input  B2  ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2BB2OI_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A31O_BLACKBOX_V
+`define SKY130_FD_SC_LS__A31O_BLACKBOX_V
+
+/**
+ * a31o: 3-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | B1)
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a31o (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A31O_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O2111AI_1_V
+`define SKY130_FD_SC_LS__O2111AI_1_V
+
+/**
+ * o2111ai: 2-input OR into first input of 4-input NAND.
+ *
+ *          Y = !((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog wrapper for o2111ai with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o2111ai.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o2111ai_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o2111ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o2111ai_1 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o2111ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2111AI_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A +=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O22AI_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__O22AI_PP_BLACKBOX_V
+
+/**
+ * o22ai: 2-input OR into both inputs of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & (B1 | B2))
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o22ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O22AI_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if ((A2&!B1&!B2&!C1&!C2)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((A2&!B1&!B2&!C1&C2)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((A2&!B1&!B2&C1&!C2)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((A2&!B1&B2&!C1&!C2)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((A2&!B1&B2&!C1&C2)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((A2&!B1&B2&C1&!C2)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((A2&B1&!B2&!C1&!C2)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((A2&B1&!B2&!C1&C2)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((A2&B1&!B2&C1&!C2)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!B1&!B2&!C1&!C2)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((A1&!B1&!B2&!C1&C2)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((A1&!B1&!B2&C1&!C2)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((A1&!B1&B2&!C1&!C2)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((A1&!B1&B2&!C1&C2)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((A1&!B1&B2&C1&!C2)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((A1&B1&!B2&!C1&!C2)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((A1&B1&!B2&!C1&C2)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((A1&B1&!B2&C1&!C2)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&B2&!C1&!C2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&B2&!C1&C2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&B2&C1&!C2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&B2&!C1&!C2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&B2&!C1&C2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&B2&C1&!C2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&B2&!C1&!C2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&B2&!C1&C2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&B2&C1&!C2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&B1&!C1&!C2)) (B2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&B1&!C1&C2)) (B2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&B1&C1&!C2)) (B2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&B1&!C1&!C2)) (B2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&B1&!C1&C2)) (B2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&B1&C1&!C2)) (B2 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&B1&!C1&!C2)) (B2 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&B1&!C1&C2)) (B2 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&B1&C1&!C2)) (B2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&!B1&!B2&C2)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&!B1&B2&C2)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&B1&!B2&C2)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&!B1&!B2&C2)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&!B1&B2&C2)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&B1&!B2&C2)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&!B1&!B2&C2)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&!B1&B2&C2)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&B1&!B2&C2)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&!B1&!B2&C1)) (C2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&!B1&B2&C1)) (C2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&B1&!B2&C1)) (C2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&!B1&!B2&C1)) (C2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&!B1&B2&C1)) (C2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&B1&!B2&C1)) (C2 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&!B1&!B2&C1)) (C2 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&!B1&B2&C1)) (C2 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&B1&!B2&C1)) (C2 +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__BUFBUF_16_V
+`define SKY130_FD_SC_LS__BUFBUF_16_V
+
+/**
+ * bufbuf: Double buffer.
+ *
+ * Verilog wrapper for bufbuf with size of 16 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__bufbuf.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__bufbuf_16 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__bufbuf base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__bufbuf_16 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__bufbuf base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__BUFBUF_16_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLRBP_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__DLRBP_PP_BLACKBOX_V
+
+/**
+ * dlrbp: Delay latch, inverted reset, non-inverted enable,
+ *        complementary outputs.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlrbp (
+    Q      ,
+    Q_N    ,
+    RESET_B,
+    D      ,
+    GATE   ,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRBP_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFRBP_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__DFRBP_PP_BLACKBOX_V
+
+/**
+ * dfrbp: Delay flop, inverted reset, complementary outputs.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dfrbp (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFRBP_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__AND3B_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__AND3B_BEHAVIORAL_V
+
+/**
+ * and3b: 3-input AND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__and3b (
+    X  ,
+    A_N,
+    B  ,
+    C
+);
+
+    // Module ports
+    output X  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out  ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out  , A_N            );
+    and and0 (and0_out_X, C, not0_out, B );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND3B_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DFBBP_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__DFBBP_BEHAVIORAL_V
+
+/**
+ * dfbbp: Delay flop, inverted set, inverted reset,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ls__udp_dff_nsr_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dfbbp (
+    Q      ,
+    Q_N    ,
+    D      ,
+    CLK    ,
+    SET_B  ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  CLK    ;
+    input  SET_B  ;
+    input  RESET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire RESET          ;
+    wire SET            ;
+    wire buf_Q          ;
+    wire CLK_delayed    ;
+    wire RESET_B_delayed;
+    wire SET_B_delayed  ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+    wire condb          ;
+
+    //                                   Name  Output  Other arguments
+    not                                  not0 (RESET , RESET_B_delayed                                         );
+    not                                  not1 (SET   , SET_B_delayed                                           );
+    sky130_fd_sc_ls__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, D_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1\'b1 ) );
+    assign cond1 = ( awake && ( SET_B_delayed === 1\'b1 ) );
+    assign condb = ( cond0 & cond1 );
+    buf                                  buf0 (Q     , buf_Q                                                   );
+    not                                  not2 (Q_N   , buf_Q                                                   );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFBBP_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKBUF_BLACKBOX_V
+`define SKY130_FD_SC_LS__CLKBUF_BLACKBOX_V
+
+/**
+ * clkbuf: Clock tree buffer.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__clkbuf (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKBUF_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLXBN_BLACKBOX_V
+`define SKY130_FD_SC_LS__DLXBN_BLACKBOX_V
+
+/**
+ * dlxbn: Delay latch, inverted enable, complementary outputs.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlxbn (
+    Q     ,
+    Q_N   ,
+    D     ,
+    GATE_N
+);
+
+    output Q     ;
+    output Q_N   ;
+    input  D     ;
+    input  GATE_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXBN_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR3_2_V
+`define SKY130_FD_SC_LS__NOR3_2_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ *       Y = !(A | B | C | !D)
+ *
+ * Verilog wrapper for nor3 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nor3.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor3_2 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nor3 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor3_2 (
+    Y,
+    A,
+    B,
+    C
+);
+
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nor3 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR3_2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A221O_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__A221O_FUNCTIONAL_V
+
+/**
+ * a221o: 2-input AND into first two inputs of 3-input OR.
+ *
+ *        X = ((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a221o (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Local signals
+    wire and0_out ;
+    wire and1_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , B1, B2                );
+    and and1 (and1_out , A1, A2                );
+    or  or0  (or0_out_X, and1_out, and0_out, C1);
+    buf buf0 (X        , or0_out_X             );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A221O_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__XOR3_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__XOR3_BEHAVIORAL_PP_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ *       X = A ^ B ^ C
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__xor3 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire xor0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    xor                                xor0        (xor0_out_X       , A, B, C               );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XOR3_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O41A_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__O41A_PP_SYMBOL_V
+
+/**
+ * o41a: 4-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o41a (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  A3  ,
+    input  A4  ,
+    input  B1  ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O41A_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O21AI_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__O21AI_FUNCTIONAL_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__o21ai (
+    Y ,
+    A1,
+    A2,
+    B1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Local signals
+    wire or0_out    ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    or   or0   (or0_out    , A2, A1         );
+    nand nand0 (nand0_out_Y, B1, or0_out    );
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21AI_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A31OI_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__A31OI_FUNCTIONAL_V
+
+/**
+ * a31oi: 3-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a31oi (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Local signals
+    wire and0_out  ;
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out  , A3, A1, A2     );
+    nor nor0 (nor0_out_Y, B1, and0_out   );
+    buf buf0 (Y         , nor0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A31OI_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A211O_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__A211O_FUNCTIONAL_PP_V
+
+/**
+ * a211o: 2-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a211o (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A1, A2               );
+    or                                 or0         (or0_out_X        , and0_out, C1, B1     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A211O_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__HA_TB_V
+`define SKY130_FD_SC_LS__HA_TB_V
+
+/**
+ * ha: Half adder.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__ha.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg B;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire COUT;
+    wire SUM;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        B    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   B    = 1\'b0;
+        #60   VGND = 1\'b0;
+        #80   VNB  = 1\'b0;
+        #100  VPB  = 1\'b0;
+        #120  VPWR = 1\'b0;
+        #140  A    = 1\'b1;
+        #160  B    = 1\'b1;
+        #180  VGND = 1\'b1;
+        #200  VNB  = 1\'b1;
+        #220  VPB  = 1\'b1;
+        #240  VPWR = 1\'b1;
+        #260  A    = 1\'b0;
+        #280  B    = 1\'b0;
+        #300  VGND = 1\'b0;
+        #320  VNB  = 1\'b0;
+        #340  VPB  = 1\'b0;
+        #360  VPWR = 1\'b0;
+        #380  VPWR = 1\'b1;
+        #400  VPB  = 1\'b1;
+        #420  VNB  = 1\'b1;
+        #440  VGND = 1\'b1;
+        #460  B    = 1\'b1;
+        #480  A    = 1\'b1;
+        #500  VPWR = 1\'bx;
+        #520  VPB  = 1\'bx;
+        #540  VNB  = 1\'bx;
+        #560  VGND = 1\'bx;
+        #580  B    = 1\'bx;
+        #600  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__ha dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .COUT(COUT), .SUM(SUM));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__HA_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLXBP_TB_V
+`define SKY130_FD_SC_LS__DLXBP_TB_V
+
+/**
+ * dlxbp: Delay latch, non-inverted enable, complementary outputs.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dlxbp.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Q;
+    wire Q_N;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   D    = 1\'b0;
+        #40   VGND = 1\'b0;
+        #60   VNB  = 1\'b0;
+        #80   VPB  = 1\'b0;
+        #100  VPWR = 1\'b0;
+        #120  D    = 1\'b1;
+        #140  VGND = 1\'b1;
+        #160  VNB  = 1\'b1;
+        #180  VPB  = 1\'b1;
+        #200  VPWR = 1\'b1;
+        #220  D    = 1\'b0;
+        #240  VGND = 1\'b0;
+        #260  VNB  = 1\'b0;
+        #280  VPB  = 1\'b0;
+        #300  VPWR = 1\'b0;
+        #320  VPWR = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VNB  = 1\'b1;
+        #380  VGND = 1\'b1;
+        #400  D    = 1\'b1;
+        #420  VPWR = 1\'bx;
+        #440  VPB  = 1\'bx;
+        #460  VNB  = 1\'bx;
+        #480  VGND = 1\'bx;
+        #500  D    = 1\'bx;
+    end
+
+    // Create a clock
+    reg GATE;
+    initial
+    begin
+        GATE = 1\'b0;
+    end
+
+    always
+    begin
+        #5 GATE = ~GATE;
+    end
+
+    sky130_fd_sc_ls__dlxbp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .GATE(GATE));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXBP_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O22AI_2_V
+`define SKY130_FD_SC_LS__O22AI_2_V
+
+/**
+ * o22ai: 2-input OR into both inputs of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o22ai with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o22ai.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o22ai_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o22ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o22ai_2 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o22ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O22AI_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR4_BLACKBOX_V
+`define SKY130_FD_SC_LS__NOR4_BLACKBOX_V
+
+/**
+ * nor4: 4-input NOR.
+ *
+ *       Y = !(A | B | C | D)
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nor4 (
+    Y,
+    A,
+    B,
+    C,
+    D
+);
+
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR4_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if ((!B)) (A +=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
+if ((B)) (A -=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
+if ((!A)) (B +=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
+if ((A)) (B -=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+( posedge CLK => ( Q : CLK ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall
+$setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ;
+$setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ;
+$setuphold ( posedge CLK , posedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ;
+$setuphold ( posedge CLK , negedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ;
+$setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ;
+$setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ;
+$width ( posedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( negedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FAH_V
+`define SKY130_FD_SC_LS__FAH_V
+
+/**
+ * fah: Full adder.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__fah.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__fah.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__fah.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__fah.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FAH_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFRBP_1_V
+`define SKY130_FD_SC_LS__DFRBP_1_V
+
+/**
+ * dfrbp: Delay flop, inverted reset, complementary outputs.
+ *
+ * Verilog wrapper for dfrbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dfrbp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dfrbp_1 (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_ls__dfrbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .RESET_B(RESET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dfrbp_1 (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    RESET_B
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__dfrbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .RESET_B(RESET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFRBP_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND4B_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__AND4B_PP_SYMBOL_V
+
+/**
+ * and4b: 4-input AND, first input inverted.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__and4b (
+    //# {{data|Data Signals}}
+    input  A_N ,
+    input  B   ,
+    input  C   ,
+    input  D   ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND4B_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLRTP_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__DLRTP_FUNCTIONAL_V
+
+/**
+ * dlrtp: Delay latch, inverted reset, non-inverted enable,
+ *        single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_pr/sky130_fd_sc_ls__udp_dlatch_pr.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlrtp (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE
+);
+
+    // Module ports
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+
+    // Local signals
+    wire RESET;
+    wire buf_Q;
+
+    //                             Delay       Name     Output  Other arguments
+    not                                        not0    (RESET , RESET_B        );
+    sky130_fd_sc_ls__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET );
+    buf                                        buf0    (Q     , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRTP_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLXBP_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__DLXBP_BEHAVIORAL_V
+
+/**
+ * dlxbp: Delay latch, non-inverted enable, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlxbp (
+    Q   ,
+    Q_N ,
+    D   ,
+    GATE
+);
+
+    // Module ports
+    output Q   ;
+    output Q_N ;
+    input  D   ;
+    input  GATE;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q       ;
+    wire GATE_delayed;
+    wire D_delayed   ;
+    reg  notifier    ;
+    wire awake       ;
+
+    //                                    Name     Output  Other arguments
+    sky130_fd_sc_ls__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
+    buf                                   buf0    (Q     , buf_Q                                        );
+    not                                   not0    (Q_N   , buf_Q                                        );
+    assign awake = ( VPWR === 1\'b1 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXBP_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR3_SYMBOL_V
+`define SKY130_FD_SC_LS__OR3_SYMBOL_V
+
+/**
+ * or3: 3-input OR.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__or3 (
+    //# {{data|Data Signals}}
+    input  A,
+    input  B,
+    input  C,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR3_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__EINVN_2_V
+`define SKY130_FD_SC_LS__EINVN_2_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog wrapper for einvn with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__einvn.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__einvn_2 (
+    Z   ,
+    A   ,
+    TE_B,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__einvn base (
+        .Z(Z),
+        .A(A),
+        .TE_B(TE_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__einvn_2 (
+    Z   ,
+    A   ,
+    TE_B
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__einvn base (
+        .Z(Z),
+        .A(A),
+        .TE_B(TE_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EINVN_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD3_V
+`define SKY130_FD_SC_LS__CLKDLYINV5SD3_V
+
+/**
+ * clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
+ *                stage gate.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__clkdlyinv5sd3.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__clkdlyinv5sd3.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__clkdlyinv5sd3.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__clkdlyinv5sd3.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV5SD3_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_PWRGOOD_PP_PG_BLACKBOX_V
+`define SKY130_FD_SC_LS__UDP_PWRGOOD_PP_PG_BLACKBOX_V
+
+/**
+
+ *   UDP_OUT :=x when VPWR!=1 or VGND!=0
+ *   UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__udp_pwrgood_pp$PG (
+    UDP_OUT,
+    UDP_IN ,
+    VPWR   ,
+    VGND
+);
+
+    output UDP_OUT;
+    input  UDP_IN ;
+    input  VPWR   ;
+    input  VGND   ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_PWRGOOD_PP_PG_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__FA_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__FA_BEHAVIORAL_V
+
+/**
+ * fa: Full adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__fa (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CIN
+);
+
+    // Module ports
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CIN ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out     ;
+    wire and0_out    ;
+    wire and1_out    ;
+    wire and2_out    ;
+    wire nor0_out    ;
+    wire nor1_out    ;
+    wire or1_out_COUT;
+    wire or2_out_SUM ;
+
+    //  Name  Output        Other arguments
+    or  or0  (or0_out     , CIN, B            );
+    and and0 (and0_out    , or0_out, A        );
+    and and1 (and1_out    , B, CIN            );
+    or  or1  (or1_out_COUT, and1_out, and0_out);
+    buf buf0 (COUT        , or1_out_COUT      );
+    and and2 (and2_out    , CIN, A, B         );
+    nor nor0 (nor0_out    , A, or0_out        );
+    nor nor1 (nor1_out    , nor0_out, COUT    );
+    or  or2  (or2_out_SUM , nor1_out, and2_out);
+    buf buf1 (SUM         , or2_out_SUM       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FA_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR2_V
+`define SKY130_FD_SC_LS__NOR2_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__nor2.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__nor2.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__nor2.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__nor2.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O311AI_4_V
+`define SKY130_FD_SC_LS__O311AI_4_V
+
+/**
+ * o311ai: 3-input OR into 3-input NAND.
+ *
+ *         Y = !((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog wrapper for o311ai with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o311ai.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o311ai_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o311ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o311ai_4 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o311ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O311AI_4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SDFSBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__SDFSBP_FUNCTIONAL_PP_V
+
+/**
+ * sdfsbp: Scan delay flop, inverted set, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ls__udp_dff_ps_pp_pg_n.v""
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+
+`celldefine
+module sky130_fd_sc_ls__sdfsbp (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire buf_Q  ;
+    wire SET    ;
+    wire mux_out;
+
+    //                                  Delay       Name       Output   Other arguments
+    not                                             not0      (SET    , SET_B                          );
+    sky130_fd_sc_ls__udp_mux_2to1                   mux_2to10 (mux_out, D, SCD, SCE                    );
+    sky130_fd_sc_ls__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK, SET, , VPWR, VGND);
+    buf                                             buf0      (Q      , buf_Q                          );
+    not                                             not1      (Q_N    , buf_Q                          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFSBP_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DFF_PS_PP_PG_N_TB_V
+`define SKY130_FD_SC_LS__UDP_DFF_PS_PP_PG_N_TB_V
+
+/**
+ * udp_dff$PS_pp$PG$N: Positive edge triggered D flip-flop with active
+ *                     high
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__udp_dff_ps_pp_pg_n.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg SET;
+    reg NOTIFIER;
+    reg VPWR;
+    reg VGND;
+
+    // Outputs are wires
+    wire Q;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D        = 1\'bX;
+        NOTIFIER = 1\'bX;
+        SET      = 1\'bX;
+        VGND     = 1\'bX;
+        VPWR     = 1\'bX;
+
+        #20   D        = 1\'b0;
+        #40   NOTIFIER = 1\'b0;
+        #60   SET      = 1\'b0;
+        #80   VGND     = 1\'b0;
+        #100  VPWR     = 1\'b0;
+        #120  D        = 1\'b1;
+        #140  NOTIFIER = 1\'b1;
+        #160  SET      = 1\'b1;
+        #180  VGND     = 1\'b1;
+        #200  VPWR     = 1\'b1;
+        #220  D        = 1\'b0;
+        #240  NOTIFIER = 1\'b0;
+        #260  SET      = 1\'b0;
+        #280  VGND     = 1\'b0;
+        #300  VPWR     = 1\'b0;
+        #320  VPWR     = 1\'b1;
+        #340  VGND     = 1\'b1;
+        #360  SET      = 1\'b1;
+        #380  NOTIFIER = 1\'b1;
+        #400  D        = 1\'b1;
+        #420  VPWR     = 1\'bx;
+        #440  VGND     = 1\'bx;
+        #460  SET      = 1\'bx;
+        #480  NOTIFIER = 1\'bx;
+        #500  D        = 1\'bx;
+    end
+
+    // Create a clock
+    reg CLK;
+    initial
+    begin
+        CLK = 1\'b0;
+    end
+
+    always
+    begin
+        #5 CLK = ~CLK;
+    end
+
+    sky130_fd_sc_ls__udp_dff$PS_pp$PG$N dut (.D(D), .SET(SET), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DFF_PS_PP_PG_N_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__EBUFN_8_V
+`define SKY130_FD_SC_LS__EBUFN_8_V
+
+/**
+ * ebufn: Tri-state buffer, negative enable.
+ *
+ * Verilog wrapper for ebufn with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__ebufn.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__ebufn_8 (
+    Z   ,
+    A   ,
+    TE_B,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__ebufn base (
+        .Z(Z),
+        .A(A),
+        .TE_B(TE_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__ebufn_8 (
+    Z   ,
+    A   ,
+    TE_B
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__ebufn base (
+        .Z(Z),
+        .A(A),
+        .TE_B(TE_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EBUFN_8_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFBBN_SYMBOL_V
+`define SKY130_FD_SC_LS__SDFBBN_SYMBOL_V
+
+/**
+ * sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
+ *         clock, complementary outputs.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sdfbbn (
+    //# {{data|Data Signals}}
+    input  D      ,
+    output Q      ,
+    output Q_N    ,
+
+    //# {{control|Control Signals}}
+    input  RESET_B,
+    input  SET_B  ,
+
+    //# {{scanchain|Scan Chain}}
+    input  SCD    ,
+    input  SCE    ,
+
+    //# {{clocks|Clocking}}
+    input  CLK_N
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFBBN_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__MUX4_SYMBOL_V
+`define SKY130_FD_SC_LS__MUX4_SYMBOL_V
+
+/**
+ * mux4: 4-input multiplexer.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__mux4 (
+    //# {{data|Data Signals}}
+    input  A0,
+    input  A1,
+    input  A2,
+    input  A3,
+    output X ,
+
+    //# {{control|Control Signals}}
+    input  S0,
+    input  S1
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MUX4_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLCLKP_1_V
+`define SKY130_FD_SC_LS__DLCLKP_1_V
+
+/**
+ * dlclkp: Clock gate.
+ *
+ * Verilog wrapper for dlclkp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dlclkp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dlclkp_1 (
+    GCLK,
+    GATE,
+    CLK ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output GCLK;
+    input  GATE;
+    input  CLK ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__dlclkp base (
+        .GCLK(GCLK),
+        .GATE(GATE),
+        .CLK(CLK),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dlclkp_1 (
+    GCLK,
+    GATE,
+    CLK
+);
+
+    output GCLK;
+    input  GATE;
+    input  CLK ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__dlclkp base (
+        .GCLK(GCLK),
+        .GATE(GATE),
+        .CLK(CLK)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLCLKP_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CONB_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__CONB_PP_SYMBOL_V
+
+/**
+ * conb: Constant value, low, high outputs.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__conb (
+    //# {{data|Data Signals}}
+    output HI  ,
+    output LO  ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CONB_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O2BB2A_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__O2BB2A_BEHAVIORAL_V
+
+/**
+ * o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
+ *
+ *         X = (!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__o2bb2a (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    // Module ports
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nand0_out ;
+    wire or0_out   ;
+    wire and0_out_X;
+
+    //   Name   Output      Other arguments
+    nand nand0 (nand0_out , A2_N, A1_N        );
+    or   or0   (or0_out   , B2, B1            );
+    and  and0  (and0_out_X, nand0_out, or0_out);
+    buf  buf0  (X         , and0_out_X        );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2BB2A_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR3B_2_V
+`define SKY130_FD_SC_LS__NOR3B_2_V
+
+/**
+ * nor3b: 3-input NOR, first input inverted.
+ *
+ *        Y = (!(A | B)) & !C)
+ *
+ * Verilog wrapper for nor3b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nor3b.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor3b_2 (
+    Y   ,
+    A   ,
+    B   ,
+    C_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nor3b base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C_N(C_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor3b_2 (
+    Y  ,
+    A  ,
+    B  ,
+    C_N
+);
+
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nor3b base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C_N(C_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR3B_2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__OR3_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__OR3_FUNCTIONAL_V
+
+/**
+ * or3: 3-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__or3 (
+    X,
+    A,
+    B,
+    C
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Local signals
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    or  or0  (or0_out_X, B, A, C        );
+    buf buf0 (X        , or0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR3_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A22O_TB_V
+`define SKY130_FD_SC_LS__A22O_TB_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ *       X = ((A1 & A2) | (B1 & B2))
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a22o.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg B1;
+    reg B2;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        B1   = 1\'bX;
+        B2   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   B1   = 1\'b0;
+        #80   B2   = 1\'b0;
+        #100  VGND = 1\'b0;
+        #120  VNB  = 1\'b0;
+        #140  VPB  = 1\'b0;
+        #160  VPWR = 1\'b0;
+        #180  A1   = 1\'b1;
+        #200  A2   = 1\'b1;
+        #220  B1   = 1\'b1;
+        #240  B2   = 1\'b1;
+        #260  VGND = 1\'b1;
+        #280  VNB  = 1\'b1;
+        #300  VPB  = 1\'b1;
+        #320  VPWR = 1\'b1;
+        #340  A1   = 1\'b0;
+        #360  A2   = 1\'b0;
+        #380  B1   = 1\'b0;
+        #400  B2   = 1\'b0;
+        #420  VGND = 1\'b0;
+        #440  VNB  = 1\'b0;
+        #460  VPB  = 1\'b0;
+        #480  VPWR = 1\'b0;
+        #500  VPWR = 1\'b1;
+        #520  VPB  = 1\'b1;
+        #540  VNB  = 1\'b1;
+        #560  VGND = 1\'b1;
+        #580  B2   = 1\'b1;
+        #600  B1   = 1\'b1;
+        #620  A2   = 1\'b1;
+        #640  A1   = 1\'b1;
+        #660  VPWR = 1\'bx;
+        #680  VPB  = 1\'bx;
+        #700  VNB  = 1\'bx;
+        #720  VGND = 1\'bx;
+        #740  B2   = 1\'bx;
+        #760  B1   = 1\'bx;
+        #780  A2   = 1\'bx;
+        #800  A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__a22o dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A22O_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR3B_TB_V
+`define SKY130_FD_SC_LS__OR3B_TB_V
+
+/**
+ * or3b: 3-input OR, first input inverted.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__or3b.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg B;
+    reg C_N;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        B    = 1\'bX;
+        C_N  = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   B    = 1\'b0;
+        #60   C_N  = 1\'b0;
+        #80   VGND = 1\'b0;
+        #100  VNB  = 1\'b0;
+        #120  VPB  = 1\'b0;
+        #140  VPWR = 1\'b0;
+        #160  A    = 1\'b1;
+        #180  B    = 1\'b1;
+        #200  C_N  = 1\'b1;
+        #220  VGND = 1\'b1;
+        #240  VNB  = 1\'b1;
+        #260  VPB  = 1\'b1;
+        #280  VPWR = 1\'b1;
+        #300  A    = 1\'b0;
+        #320  B    = 1\'b0;
+        #340  C_N  = 1\'b0;
+        #360  VGND = 1\'b0;
+        #380  VNB  = 1\'b0;
+        #400  VPB  = 1\'b0;
+        #420  VPWR = 1\'b0;
+        #440  VPWR = 1\'b1;
+        #460  VPB  = 1\'b1;
+        #480  VNB  = 1\'b1;
+        #500  VGND = 1\'b1;
+        #520  C_N  = 1\'b1;
+        #540  B    = 1\'b1;
+        #560  A    = 1\'b1;
+        #580  VPWR = 1\'bx;
+        #600  VPB  = 1\'bx;
+        #620  VNB  = 1\'bx;
+        #640  VGND = 1\'bx;
+        #660  C_N  = 1\'bx;
+        #680  B    = 1\'bx;
+        #700  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__or3b dut (.A(A), .B(B), .C_N(C_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR3B_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFRBP_SYMBOL_V
+`define SKY130_FD_SC_LS__DFRBP_SYMBOL_V
+
+/**
+ * dfrbp: Delay flop, inverted reset, complementary outputs.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dfrbp (
+    //# {{data|Data Signals}}
+    input  D      ,
+    output Q      ,
+    output Q_N    ,
+
+    //# {{control|Control Signals}}
+    input  RESET_B,
+
+    //# {{clocks|Clocking}}
+    input  CLK
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFRBP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND4_4_V
+`define SKY130_FD_SC_LS__AND4_4_V
+
+/**
+ * and4: 4-input AND.
+ *
+ * Verilog wrapper for and4 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__and4.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__and4_4 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__and4 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__and4_4 (
+    X,
+    A,
+    B,
+    C,
+    D
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__and4 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND4_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__TAPVPWRVGND_SYMBOL_V
+`define SKY130_FD_SC_LS__TAPVPWRVGND_SYMBOL_V
+
+/**
+ * tapvpwrvgnd: Substrate and well tap cell.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__tapvpwrvgnd ();
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPVPWRVGND_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR2_2_V
+`define SKY130_FD_SC_LS__NOR2_2_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog wrapper for nor2 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nor2.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor2_2 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nor2 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor2_2 (
+    Y,
+    A,
+    B
+);
+
+    output Y;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nor2 base (
+        .Y(Y),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR2_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O2111AI_V
+`define SKY130_FD_SC_LS__O2111AI_V
+
+/**
+ * o2111ai: 2-input OR into first input of 4-input NAND.
+ *
+ *          Y = !((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o2111ai.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o2111ai.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o2111ai.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o2111ai.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2111AI_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if ((!A2&!A3&!B1&B2)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((!A2&!A3&B1&!B2)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((!A2&!A3&B1&B2)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A3&!B1&B2)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A3&B1&!B2)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A3&B1&B2)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&!B1&B2)) (A3 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&B1&!B2)) (A3 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&B1&B2)) (A3 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&!A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&!A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2&!A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2&A3&!B2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&!A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&!A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2&!A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2&A3&!B1)) (B2 +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DFF_PS_PP_PG_N_V
+`define SKY130_FD_SC_LS__UDP_DFF_PS_PP_PG_N_V
+
+/**
+ * udp_dff$PS_pp$PG$N: Positive edge triggered D flip-flop with active
+ *                     high
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`include ""./sky130_fd_sc_ls__udp_dff_ps_pp_pg_n.blackbox.v""
+`else
+primitive sky130_fd_sc_ls__udp_dff$PS_pp$PG$N (
+    Q       ,
+    D       ,
+    CLK     ,
+    SET     ,
+    NOTIFIER,
+    VPWR    ,
+    VGND
+);
+
+    output Q       ;
+    input  D       ;
+    input  CLK     ;
+    input  SET     ;
+    input  NOTIFIER;
+    input  VPWR    ;
+    input  VGND    ;
+
+    reg Q;
+
+    table
+     //          D           CLK  SET  NOTIFIER VPWR VGND :  Qt : Qt+1
+                 *            b    0      ?      1    0   :  ?  :  -    ; // data event, hold unless CP==x
+                 ?           (?0)  0      ?      1    0   :  ?  :  -    ; // CP => 0, hold
+                 ?            b   (?0)    ?      1    0   :  ?  :  -    ; // S => 0, hold unless CP==x
+                 ?            ?    1      ?      1    0   :  ?  :  1    ; // async set
+                 0            r    0      ?      1    0   :  ?  :  0    ; // clock data on CP
+                 1            r    ?      ?      1    0   :  ?  :  1    ; // clock data on CP
+                 0           (x1)  0      ?      1    0   :  0  :  0    ; // possible CP, hold when D==Q==0
+                 1           (x1)  ?      ?      1    0   :  1  :  1    ; // possible CP, hold when D==Q==1
+                 0            x    0      ?      1    0   :  0  :  0    ; // unkown CP, hold when D==Q==0
+                 1            x    ?      ?      1    0   :  1  :  1    ; // unkown CP, hold when D==Q==1
+                 ?            b   (?x)    ?      1    0   :  1  :  1    ; // S=>x, hold when Q==1 unless CP==x
+                 ?           (?0)  x      ?      1    0   :  1  :  1    ;
+        // [\'IfDef(functional)\', \'\']                 ?            ?    ?      *      1    0   :  ?  :  -    ; // Q => - on any change on notifier
+        // [\'Else\', \'\']                 ?            ?    ?      *      1    0   :  ?  :  x    ; // Q => X on any change on notifier
+        // [\'EndIfDef(functional)\', \'\']                 ?            ?    ?      ?      *    ?   :  ?  :  x    ; // Q => X on any change on vpwr
+                 ?            ?    ?      ?      ?    *   :  ?  :  x    ; // Q => X on any change on vgnd
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DFF_PS_PP_PG_N_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A41OI_SYMBOL_V
+`define SKY130_FD_SC_LS__A41OI_SYMBOL_V
+
+/**
+ * a41oi: 4-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a41oi (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  A3,
+    input  A4,
+    input  B1,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A41OI_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+( posedge CLK => ( Q : CLK ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall
+$width ( posedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( negedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+$setuphold ( posedge CLK , posedge DE , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , CLK_delayed , DE_delayed ) ;
+$setuphold ( posedge CLK , negedge DE , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , CLK_delayed , DE_delayed ) ;
+$setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND0 ,  COND0 , CLK_delayed , D_delayed ) ;
+$setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND0 ,  COND0 , CLK_delayed , D_delayed ) ;
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O221AI_V
+`define SKY130_FD_SC_LS__O221AI_V
+
+/**
+ * o221ai: 2-input OR into first two inputs of 3-input NAND.
+ *
+ *         Y = !((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o221ai.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o221ai.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o221ai.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o221ai.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O221AI_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLYGATE4SD3_V
+`define SKY130_FD_SC_LS__DLYGATE4SD3_V
+
+/**
+ * dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlygate4sd3.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlygate4sd3.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlygate4sd3.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlygate4sd3.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYGATE4SD3_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLCLKP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__DLCLKP_FUNCTIONAL_PP_V
+
+/**
+ * dlclkp: Clock gate.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlclkp (
+    GCLK,
+    GATE,
+    CLK ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output GCLK;
+    input  GATE;
+    input  CLK ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire m0  ;
+    wire clkn;
+
+    //                                    Name     Output  Other arguments
+    not                                   not0    (clkn  , CLK                     );
+    sky130_fd_sc_ls__udp_dlatch$P_pp$PG$N dlatch0 (m0    , GATE, clkn, , VPWR, VGND);
+    and                                   and0    (GCLK  , m0, CLK                 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLCLKP_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A31O_2_V
+`define SKY130_FD_SC_LS__A31O_2_V
+
+/**
+ * a31o: 3-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | B1)
+ *
+ * Verilog wrapper for a31o with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a31o.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a31o_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a31o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a31o_2 (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a31o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A31O_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND3_4_V
+`define SKY130_FD_SC_LS__NAND3_4_V
+
+/**
+ * nand3: 3-input NAND.
+ *
+ * Verilog wrapper for nand3 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nand3.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nand3_4 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nand3 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nand3_4 (
+    Y,
+    A,
+    B,
+    C
+);
+
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nand3 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND3_4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLRBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__DLRBP_FUNCTIONAL_PP_V
+
+/**
+ * dlrbp: Delay latch, inverted reset, non-inverted enable,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_pr_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlrbp (
+    Q      ,
+    Q_N    ,
+    RESET_B,
+    D      ,
+    GATE   ,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire RESET;
+    wire buf_Q;
+
+    //                                     Delay       Name     Output  Other arguments
+    not                                                not0    (RESET , RESET_B                     );
+    sky130_fd_sc_ls__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET, , VPWR, VGND);
+    buf                                                buf0    (Q     , buf_Q                       );
+    not                                                not1    (Q_N   , buf_Q                       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRBP_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__EINVP_V
+`define SKY130_FD_SC_LS__EINVP_V
+
+/**
+ * einvp: Tri-state inverter, positive enable.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__einvp.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__einvp.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__einvp.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__einvp.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EINVP_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__BUF_V
+`define SKY130_FD_SC_LS__BUF_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__buf.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__buf.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__buf.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__buf.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__BUF_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFXTP_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__SDFXTP_PP_BLACKBOX_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sdfxtp (
+    Q   ,
+    CLK ,
+    D   ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFXTP_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR4B_4_V
+`define SKY130_FD_SC_LS__NOR4B_4_V
+
+/**
+ * nor4b: 4-input NOR, first input inverted.
+ *
+ * Verilog wrapper for nor4b with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nor4b.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor4b_4 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nor4b base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D_N(D_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor4b_4 (
+    Y  ,
+    A  ,
+    B  ,
+    C  ,
+    D_N
+);
+
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C  ;
+    input  D_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nor4b base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D_N(D_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR4B_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FAH_2_V
+`define SKY130_FD_SC_LS__FAH_2_V
+
+/**
+ * fah: Full adder.
+ *
+ * Verilog wrapper for fah with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__fah.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__fah_2 (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CI  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CI  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__fah base (
+        .COUT(COUT),
+        .SUM(SUM),
+        .A(A),
+        .B(B),
+        .CI(CI),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__fah_2 (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CI
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CI  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__fah base (
+        .COUT(COUT),
+        .SUM(SUM),
+        .A(A),
+        .B(B),
+        .CI(CI)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FAH_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__BUFBUF_8_V
+`define SKY130_FD_SC_LS__BUFBUF_8_V
+
+/**
+ * bufbuf: Double buffer.
+ *
+ * Verilog wrapper for bufbuf with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__bufbuf.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__bufbuf_8 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__bufbuf base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__bufbuf_8 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__bufbuf base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__BUFBUF_8_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NOR3B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__NOR3B_FUNCTIONAL_PP_V
+
+/**
+ * nor3b: 3-input NOR, first input inverted.
+ *
+ *        Y = (!(A | B)) & !C)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__nor3b (
+    Y   ,
+    A   ,
+    B   ,
+    C_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nor0_out         ;
+    wire and0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nor                                nor0        (nor0_out         , A, B                  );
+    and                                and0        (and0_out_Y       , C_N, nor0_out         );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR3B_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD2_V
+`define SKY130_FD_SC_LS__CLKDLYINV5SD2_V
+
+/**
+ * clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
+ *                stage gate.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__clkdlyinv5sd2.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__clkdlyinv5sd2.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__clkdlyinv5sd2.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__clkdlyinv5sd2.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV5SD2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR4_V
+`define SKY130_FD_SC_LS__OR4_V
+
+/**
+ * or4: 4-input OR.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__or4.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__or4.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__or4.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__or4.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__FILL_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__FILL_BEHAVIORAL_PP_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__fill (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FILL_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR2B_SYMBOL_V
+`define SKY130_FD_SC_LS__OR2B_SYMBOL_V
+
+/**
+ * or2b: 2-input OR, first input inverted.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__or2b (
+    //# {{data|Data Signals}}
+    input  A  ,
+    input  B_N,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR2B_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O32AI_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__O32AI_FUNCTIONAL_V
+
+/**
+ * o32ai: 3-input OR and 2-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__o32ai (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Local signals
+    wire nor0_out ;
+    wire nor1_out ;
+    wire or0_out_Y;
+
+    //  Name  Output     Other arguments
+    nor nor0 (nor0_out , A3, A1, A2        );
+    nor nor1 (nor1_out , B1, B2            );
+    or  or0  (or0_out_Y, nor1_out, nor0_out);
+    buf buf0 (Y        , or0_out_Y         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O32AI_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__XNOR3_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__XNOR3_BEHAVIORAL_PP_V
+
+/**
+ * xnor3: 3-input exclusive NOR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__xnor3 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire xnor0_out_X      ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    xnor                               xnor0       (xnor0_out_X      , A, B, C                );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xnor0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XNOR3_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__MUX2_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__MUX2_FUNCTIONAL_PP_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+
+`celldefine
+module sky130_fd_sc_ls__mux2 (
+    X   ,
+    A0  ,
+    A1  ,
+    S   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A0  ;
+    input  A1  ;
+    input  S   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire mux_2to10_out_X  ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    sky130_fd_sc_ls__udp_mux_2to1      mux_2to10   (mux_2to10_out_X  , A0, A1, S                  );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_2to10_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MUX2_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND2_TB_V
+`define SKY130_FD_SC_LS__AND2_TB_V
+
+/**
+ * and2: 2-input AND.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__and2.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg B;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        B    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   B    = 1\'b0;
+        #60   VGND = 1\'b0;
+        #80   VNB  = 1\'b0;
+        #100  VPB  = 1\'b0;
+        #120  VPWR = 1\'b0;
+        #140  A    = 1\'b1;
+        #160  B    = 1\'b1;
+        #180  VGND = 1\'b1;
+        #200  VNB  = 1\'b1;
+        #220  VPB  = 1\'b1;
+        #240  VPWR = 1\'b1;
+        #260  A    = 1\'b0;
+        #280  B    = 1\'b0;
+        #300  VGND = 1\'b0;
+        #320  VNB  = 1\'b0;
+        #340  VPB  = 1\'b0;
+        #360  VPWR = 1\'b0;
+        #380  VPWR = 1\'b1;
+        #400  VPB  = 1\'b1;
+        #420  VNB  = 1\'b1;
+        #440  VGND = 1\'b1;
+        #460  B    = 1\'b1;
+        #480  A    = 1\'b1;
+        #500  VPWR = 1\'bx;
+        #520  VPB  = 1\'bx;
+        #540  VNB  = 1\'bx;
+        #560  VGND = 1\'bx;
+        #580  B    = 1\'bx;
+        #600  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__and2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND2_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O2111AI_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__O2111AI_BEHAVIORAL_V
+
+/**
+ * o2111ai: 2-input OR into first input of 4-input NAND.
+ *
+ *          Y = !((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__o2111ai (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out    ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    or   or0   (or0_out    , A2, A1             );
+    nand nand0 (nand0_out_Y, C1, B1, D1, or0_out);
+    buf  buf0  (Y          , nand0_out_Y        );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2111AI_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR4B_SYMBOL_V
+`define SKY130_FD_SC_LS__NOR4B_SYMBOL_V
+
+/**
+ * nor4b: 4-input NOR, first input inverted.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nor4b (
+    //# {{data|Data Signals}}
+    input  A  ,
+    input  B  ,
+    input  C  ,
+    input  D_N,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR4B_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DIODE_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__DIODE_BEHAVIORAL_V
+
+/**
+ * diode: Antenna tie-down diode.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__diode (
+    DIODE
+);
+
+    // Module ports
+    input DIODE;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DIODE_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O2BB2A_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__O2BB2A_PP_BLACKBOX_V
+
+/**
+ * o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
+ *
+ *         X = (!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o2bb2a (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2BB2A_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A32OI_1_V
+`define SKY130_FD_SC_LS__A32OI_1_V
+
+/**
+ * a32oi: 3-input AND into first input, and 2-input AND into
+ *        2nd input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog wrapper for a32oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a32oi.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a32oi_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a32oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a32oi_1 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a32oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A32OI_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DECAPHETAP_TB_V
+`define SKY130_FD_SC_LS__DECAPHETAP_TB_V
+
+/**
+
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__decaphetap.v""
+
+module top();
+
+    // Inputs are registered
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+
+    // Outputs are wires
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        VGND = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   VGND = 1\'b0;
+        #40   VPB  = 1\'b0;
+        #60   VPWR = 1\'b0;
+        #80   VGND = 1\'b1;
+        #100  VPB  = 1\'b1;
+        #120  VPWR = 1\'b1;
+        #140  VGND = 1\'b0;
+        #160  VPB  = 1\'b0;
+        #180  VPWR = 1\'b0;
+        #200  VPWR = 1\'b1;
+        #220  VPB  = 1\'b1;
+        #240  VGND = 1\'b1;
+        #260  VPWR = 1\'bx;
+        #280  VPB  = 1\'bx;
+        #300  VGND = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__decaphetap dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DECAPHETAP_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O311AI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__O311AI_FUNCTIONAL_PP_V
+
+/**
+ * o311ai: 3-input OR into 3-input NAND.
+ *
+ *         Y = !((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__o311ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1, A3             );
+    nand                               nand0       (nand0_out_Y      , C1, or0_out, B1        );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O311AI_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A31OI_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__A31OI_PP_BLACKBOX_V
+
+/**
+ * a31oi: 3-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | B1)
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a31oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A31OI_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DFXTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__DFXTP_BEHAVIORAL_PP_V
+
+/**
+ * dfxtp: Delay flop, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dfxtp (
+    Q   ,
+    CLK ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q      ;
+    reg  notifier   ;
+    wire D_delayed  ;
+    wire CLK_delayed;
+    wire awake      ;
+
+    //                                 Name  Output  Other arguments
+    sky130_fd_sc_ls__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    buf                                buf0 (Q     , buf_Q                                       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFXTP_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A32OI_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__A32OI_PP_BLACKBOX_V
+
+/**
+ * a32oi: 3-input AND into first input, and 2-input AND into
+ *        2nd input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a32oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A32OI_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD2_V
+`define SKY130_FD_SC_LS__CLKDLYINV3SD2_V
+
+/**
+ * clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
+ *                stage gate.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__clkdlyinv3sd2.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__clkdlyinv3sd2.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__clkdlyinv3sd2.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__clkdlyinv3sd2.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV3SD2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DLATCH_P_SYMBOL_V
+`define SKY130_FD_SC_LS__UDP_DLATCH_P_SYMBOL_V
+
+/**
+ * udp_dlatch$P: D-latch, gated standard drive / active high
+ *               (Q output UDP)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__udp_dlatch$P (
+    //# {{data|Data Signals}}
+    input  D   ,
+    output Q   ,
+
+    //# {{clocks|Clocking}}
+    input  GATE
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DLATCH_P_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A1 +=> X) = (0:0:0,0:0:0);
+(A2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2)) (B1_N -=> X) = (0:0:0,0:0:0);
+if ((!A1&A2)) (B1_N -=> X) = (0:0:0,0:0:0);
+if ((A1&!A2)) (B1_N -=> X) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFXTP_TB_V
+`define SKY130_FD_SC_LS__SDFXTP_TB_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__sdfxtp.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg SCD;
+    reg SCE;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Q;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D    = 1\'bX;
+        SCD  = 1\'bX;
+        SCE  = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   D    = 1\'b0;
+        #40   SCD  = 1\'b0;
+        #60   SCE  = 1\'b0;
+        #80   VGND = 1\'b0;
+        #100  VNB  = 1\'b0;
+        #120  VPB  = 1\'b0;
+        #140  VPWR = 1\'b0;
+        #160  D    = 1\'b1;
+        #180  SCD  = 1\'b1;
+        #200  SCE  = 1\'b1;
+        #220  VGND = 1\'b1;
+        #240  VNB  = 1\'b1;
+        #260  VPB  = 1\'b1;
+        #280  VPWR = 1\'b1;
+        #300  D    = 1\'b0;
+        #320  SCD  = 1\'b0;
+        #340  SCE  = 1\'b0;
+        #360  VGND = 1\'b0;
+        #380  VNB  = 1\'b0;
+        #400  VPB  = 1\'b0;
+        #420  VPWR = 1\'b0;
+        #440  VPWR = 1\'b1;
+        #460  VPB  = 1\'b1;
+        #480  VNB  = 1\'b1;
+        #500  VGND = 1\'b1;
+        #520  SCE  = 1\'b1;
+        #540  SCD  = 1\'b1;
+        #560  D    = 1\'b1;
+        #580  VPWR = 1\'bx;
+        #600  VPB  = 1\'bx;
+        #620  VNB  = 1\'bx;
+        #640  VGND = 1\'bx;
+        #660  SCE  = 1\'bx;
+        #680  SCD  = 1\'bx;
+        #700  D    = 1\'bx;
+    end
+
+    // Create a clock
+    reg CLK;
+    initial
+    begin
+        CLK = 1\'b0;
+    end
+
+    always
+    begin
+        #5 CLK = ~CLK;
+    end
+
+    sky130_fd_sc_ls__sdfxtp dut (.D(D), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFXTP_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__BUFINV_8_V
+`define SKY130_FD_SC_LS__BUFINV_8_V
+
+/**
+ * bufinv: Buffer followed by inverter.
+ *
+ * Verilog wrapper for bufinv with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__bufinv.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__bufinv_8 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__bufinv base (
+        .Y(Y),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__bufinv_8 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__bufinv base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__BUFINV_8_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O32AI_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__O32AI_PP_SYMBOL_V
+
+/**
+ * o32ai: 3-input OR and 2-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o32ai (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  A3  ,
+    input  B1  ,
+    input  B2  ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O32AI_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A2BB2O_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__A2BB2O_PP_BLACKBOX_V
+
+/**
+ * a2bb2o: 2-input AND, both inputs inverted, into first input, and
+ *         2-input AND into 2nd input of 2-input OR.
+ *
+ *         X = ((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a2bb2o (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2BB2O_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A222O_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__A222O_PP_BLACKBOX_V
+
+/**
+ * a222o: 2-input AND into all inputs of 3-input OR.
+ *
+ *        X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a222o (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    C2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  C2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A222O_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__HA_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__HA_FUNCTIONAL_V
+
+/**
+ * ha: Half adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__ha (
+    COUT,
+    SUM ,
+    A   ,
+    B
+);
+
+    // Module ports
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+
+    // Local signals
+    wire and0_out_COUT;
+    wire xor0_out_SUM ;
+
+    //  Name  Output         Other arguments
+    and and0 (and0_out_COUT, A, B           );
+    buf buf0 (COUT         , and0_out_COUT  );
+    xor xor0 (xor0_out_SUM , B, A           );
+    buf buf1 (SUM          , xor0_out_SUM   );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__HA_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A21BO_BLACKBOX_V
+`define SKY130_FD_SC_LS__A21BO_BLACKBOX_V
+
+/**
+ * a21bo: 2-input AND into first input of 2-input OR,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 & A2) | (!B1_N))
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a21bo (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21BO_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A311O_2_V
+`define SKY130_FD_SC_LS__A311O_2_V
+
+/**
+ * a311o: 3-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog wrapper for a311o with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a311o.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a311o_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a311o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a311o_2 (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a311o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A311O_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR4_V
+`define SKY130_FD_SC_LS__NOR4_V
+
+/**
+ * nor4: 4-input NOR.
+ *
+ *       Y = !(A | B | C | D)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__nor4.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__nor4.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__nor4.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__nor4.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FAHCON_1_V
+`define SKY130_FD_SC_LS__FAHCON_1_V
+
+/**
+ * fahcon: Full adder, inverted carry in, inverted carry out.
+ *
+ * Verilog wrapper for fahcon with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__fahcon.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__fahcon_1 (
+    COUT_N,
+    SUM   ,
+    A     ,
+    B     ,
+    CI    ,
+    VPWR  ,
+    VGND  ,
+    VPB   ,
+    VNB
+);
+
+    output COUT_N;
+    output SUM   ;
+    input  A     ;
+    input  B     ;
+    input  CI    ;
+    input  VPWR  ;
+    input  VGND  ;
+    input  VPB   ;
+    input  VNB   ;
+    sky130_fd_sc_ls__fahcon base (
+        .COUT_N(COUT_N),
+        .SUM(SUM),
+        .A(A),
+        .B(B),
+        .CI(CI),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__fahcon_1 (
+    COUT_N,
+    SUM   ,
+    A     ,
+    B     ,
+    CI
+);
+
+    output COUT_N;
+    output SUM   ;
+    input  A     ;
+    input  B     ;
+    input  CI    ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__fahcon base (
+        .COUT_N(COUT_N),
+        .SUM(SUM),
+        .A(A),
+        .B(B),
+        .CI(CI)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FAHCON_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A +=> X) = (0:0:0,0:0:0);
+(B +=> X) = (0:0:0,0:0:0);
+(C +=> X) = (0:0:0,0:0:0);
+(D +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O211A_SYMBOL_V
+`define SKY130_FD_SC_LS__O211A_SYMBOL_V
+
+/**
+ * o211a: 2-input OR into first input of 3-input AND.
+ *
+ *        X = ((A1 | A2) & B1 & C1)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o211a (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  B1,
+    input  C1,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O211A_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLRBP_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__DLRBP_PP_SYMBOL_V
+
+/**
+ * dlrbp: Delay latch, inverted reset, non-inverted enable,
+ *        complementary outputs.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlrbp (
+    //# {{data|Data Signals}}
+    input  D      ,
+    output Q      ,
+    output Q_N    ,
+
+    //# {{control|Control Signals}}
+    input  RESET_B,
+
+    //# {{clocks|Clocking}}
+    input  GATE   ,
+
+    //# {{power|Power}}
+    input  VPB    ,
+    input  VPWR   ,
+    input  VGND   ,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRBP_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O21BA_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__O21BA_BEHAVIORAL_V
+
+/**
+ * o21ba: 2-input OR into first input of 2-input AND,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 | A2) & !B1_N)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__o21ba (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nor0_out  ;
+    wire nor1_out_X;
+
+    //  Name  Output      Other arguments
+    nor nor0 (nor0_out  , A1, A2         );
+    nor nor1 (nor1_out_X, B1_N, nor0_out );
+    buf buf0 (X         , nor1_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21BA_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FILL_8_V
+`define SKY130_FD_SC_LS__FILL_8_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog wrapper for fill with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__fill.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__fill_8 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+    sky130_fd_sc_ls__fill base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__fill_8 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__fill base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FILL_8_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND2_4_V
+`define SKY130_FD_SC_LS__NAND2_4_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog wrapper for nand2 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nand2.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nand2_4 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nand2 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nand2_4 (
+    Y,
+    A,
+    B
+);
+
+    output Y;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nand2 base (
+        .Y(Y),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND2_4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if ((!B&!C)) (A +=> X) = (0:0:0,0:0:0);
+if ((!B&C)) (A -=> X) = (0:0:0,0:0:0);
+if ((B&!C)) (A -=> X) = (0:0:0,0:0:0);
+if ((B&C)) (A +=> X) = (0:0:0,0:0:0);
+if ((!A&!C)) (B +=> X) = (0:0:0,0:0:0);
+if ((!A&C)) (B -=> X) = (0:0:0,0:0:0);
+if ((A&!C)) (B -=> X) = (0:0:0,0:0:0);
+if ((A&C)) (B +=> X) = (0:0:0,0:0:0);
+if ((!A&!B)) (C +=> X) = (0:0:0,0:0:0);
+if ((!A&B)) (C -=> X) = (0:0:0,0:0:0);
+if ((A&!B)) (C -=> X) = (0:0:0,0:0:0);
+if ((A&B)) (C +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A221O_2_V
+`define SKY130_FD_SC_LS__A221O_2_V
+
+/**
+ * a221o: 2-input AND into first two inputs of 3-input OR.
+ *
+ *        X = ((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog wrapper for a221o with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a221o.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a221o_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a221o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a221o_2 (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a221o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A221O_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FILL_DIODE_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__FILL_DIODE_PP_SYMBOL_V
+
+/**
+ * fill_diode: Fill diode.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__fill_diode (
+    //# {{power|Power}}
+    input VPB ,
+    input VPWR,
+    input VGND,
+    input VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FILL_DIODE_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKBUF_1_V
+`define SKY130_FD_SC_LS__CLKBUF_1_V
+
+/**
+ * clkbuf: Clock tree buffer.
+ *
+ * Verilog wrapper for clkbuf with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__clkbuf.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__clkbuf_1 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__clkbuf base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__clkbuf_1 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__clkbuf base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKBUF_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SDFXTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__SDFXTP_BEHAVIORAL_PP_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+`include ""../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__sdfxtp (
+    Q   ,
+    CLK ,
+    D   ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q      ;
+    wire mux_out    ;
+    reg  notifier   ;
+    wire D_delayed  ;
+    wire SCD_delayed;
+    wire SCE_delayed;
+    wire CLK_delayed;
+    wire awake      ;
+    wire cond1      ;
+    wire cond2      ;
+    wire cond3      ;
+
+    //                                 Name       Output   Other arguments
+    sky130_fd_sc_ls__udp_mux_2to1      mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed       );
+    sky130_fd_sc_ls__udp_dff$P_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    assign cond1 = ( ( SCE_delayed === 1\'b0 ) && awake );
+    assign cond2 = ( ( SCE_delayed === 1\'b1 ) && awake );
+    assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
+    buf                                buf0      (Q      , buf_Q                                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFXTP_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__MUX4_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__MUX4_FUNCTIONAL_PP_V
+
+/**
+ * mux4: 4-input multiplexer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+`include ""../../models/udp_mux_4to2/sky130_fd_sc_ls__udp_mux_4to2.v""
+
+`celldefine
+module sky130_fd_sc_ls__mux4 (
+    X   ,
+    A0  ,
+    A1  ,
+    A2  ,
+    A3  ,
+    S0  ,
+    S1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A0  ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  S0  ;
+    input  S1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire mux_4to20_out_X  ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    sky130_fd_sc_ls__udp_mux_4to2      mux_4to20   (mux_4to20_out_X  , A0, A1, A2, A3, S0, S1     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_4to20_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MUX4_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLYMETAL6S6S_TB_V
+`define SKY130_FD_SC_LS__DLYMETAL6S6S_TB_V
+
+/**
+ * dlymetal6s6s: 6-inverter delay with output from 6th inverter on
+ *               horizontal route.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dlymetal6s6s.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   VGND = 1\'b0;
+        #60   VNB  = 1\'b0;
+        #80   VPB  = 1\'b0;
+        #100  VPWR = 1\'b0;
+        #120  A    = 1\'b1;
+        #140  VGND = 1\'b1;
+        #160  VNB  = 1\'b1;
+        #180  VPB  = 1\'b1;
+        #200  VPWR = 1\'b1;
+        #220  A    = 1\'b0;
+        #240  VGND = 1\'b0;
+        #260  VNB  = 1\'b0;
+        #280  VPB  = 1\'b0;
+        #300  VPWR = 1\'b0;
+        #320  VPWR = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VNB  = 1\'b1;
+        #380  VGND = 1\'b1;
+        #400  A    = 1\'b1;
+        #420  VPWR = 1\'bx;
+        #440  VPB  = 1\'bx;
+        #460  VNB  = 1\'bx;
+        #480  VGND = 1\'bx;
+        #500  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__dlymetal6s6s dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYMETAL6S6S_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLYMETAL6S6S_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__DLYMETAL6S6S_PP_BLACKBOX_V
+
+/**
+ * dlymetal6s6s: 6-inverter delay with output from 6th inverter on
+ *               horizontal route.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlymetal6s6s (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYMETAL6S6S_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A22OI_2_V
+`define SKY130_FD_SC_LS__A22OI_2_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a22oi with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a22oi.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a22oi_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a22oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a22oi_2 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a22oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A22OI_2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NAND4B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__NAND4B_FUNCTIONAL_PP_V
+
+/**
+ * nand4b: 4-input NAND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__nand4b (
+    Y   ,
+    A_N ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , A_N                    );
+    nand                               nand0       (nand0_out_Y      , D, C, B, not0_out      );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND4B_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A32O_V
+`define SKY130_FD_SC_LS__A32O_V
+
+/**
+ * a32o: 3-input AND into first input, and 2-input AND into
+ *       2nd input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a32o.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a32o.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a32o.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a32o.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A32O_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O2BB2AI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__O2BB2AI_BEHAVIORAL_PP_V
+
+/**
+ * o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
+ *
+ *          Y = !(!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__o2bb2ai (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out        ;
+    wire or0_out          ;
+    wire nand1_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out        , A2_N, A1_N             );
+    or                                 or0         (or0_out          , B2, B1                 );
+    nand                               nand1       (nand1_out_Y      , nand0_out, or0_out     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand1_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2BB2AI_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__BUF_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__BUF_FUNCTIONAL_PP_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__buf (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__BUF_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND3B_V
+`define SKY130_FD_SC_LS__AND3B_V
+
+/**
+ * and3b: 3-input AND, first input inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__and3b.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__and3b.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__and3b.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__and3b.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND3B_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR4_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__OR4_PP_SYMBOL_V
+
+/**
+ * or4: 4-input OR.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__or4 (
+    //# {{data|Data Signals}}
+    input  A   ,
+    input  B   ,
+    input  C   ,
+    input  D   ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR4_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__MAJ3_TB_V
+`define SKY130_FD_SC_LS__MAJ3_TB_V
+
+/**
+ * maj3: 3-input majority vote.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__maj3.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg B;
+    reg C;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        B    = 1\'bX;
+        C    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   B    = 1\'b0;
+        #60   C    = 1\'b0;
+        #80   VGND = 1\'b0;
+        #100  VNB  = 1\'b0;
+        #120  VPB  = 1\'b0;
+        #140  VPWR = 1\'b0;
+        #160  A    = 1\'b1;
+        #180  B    = 1\'b1;
+        #200  C    = 1\'b1;
+        #220  VGND = 1\'b1;
+        #240  VNB  = 1\'b1;
+        #260  VPB  = 1\'b1;
+        #280  VPWR = 1\'b1;
+        #300  A    = 1\'b0;
+        #320  B    = 1\'b0;
+        #340  C    = 1\'b0;
+        #360  VGND = 1\'b0;
+        #380  VNB  = 1\'b0;
+        #400  VPB  = 1\'b0;
+        #420  VPWR = 1\'b0;
+        #440  VPWR = 1\'b1;
+        #460  VPB  = 1\'b1;
+        #480  VNB  = 1\'b1;
+        #500  VGND = 1\'b1;
+        #520  C    = 1\'b1;
+        #540  B    = 1\'b1;
+        #560  A    = 1\'b1;
+        #580  VPWR = 1\'bx;
+        #600  VPB  = 1\'bx;
+        #620  VNB  = 1\'bx;
+        #640  VGND = 1\'bx;
+        #660  C    = 1\'bx;
+        #680  B    = 1\'bx;
+        #700  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__maj3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MAJ3_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__EBUFN_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__EBUFN_FUNCTIONAL_V
+
+/**
+ * ebufn: Tri-state buffer, negative enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__ebufn (
+    Z   ,
+    A   ,
+    TE_B
+);
+
+    // Module ports
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+
+    //     Name     Output  Other arguments
+    bufif0 bufif00 (Z     , A, TE_B        );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EBUFN_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A21BO_2_V
+`define SKY130_FD_SC_LS__A21BO_2_V
+
+/**
+ * a21bo: 2-input AND into first input of 2-input OR,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 & A2) | (!B1_N))
+ *
+ * Verilog wrapper for a21bo with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a21bo.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a21bo_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a21bo base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a21bo_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a21bo base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21BO_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__MUX2_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__MUX2_PP_BLACKBOX_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__mux2 (
+    X   ,
+    A0  ,
+    A1  ,
+    S   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A0  ;
+    input  A1  ;
+    input  S   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MUX2_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__CONB_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__CONB_FUNCTIONAL_V
+
+/**
+ * conb: Constant value, low, high outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__conb (
+    HI,
+    LO
+);
+
+    // Module ports
+    output HI;
+    output LO;
+
+    //       Name       Output
+    pullup   pullup0   (HI    );
+    pulldown pulldown0 (LO    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CONB_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O32A_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__O32A_FUNCTIONAL_PP_V
+
+/**
+ * o32a: 3-input OR and 2-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__o32a (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire or1_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1, A3            );
+    or                                 or1         (or1_out          , B2, B1                );
+    and                                and0        (and0_out_X       , or0_out, or1_out      );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O32A_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O211A_4_V
+`define SKY130_FD_SC_LS__O211A_4_V
+
+/**
+ * o211a: 2-input OR into first input of 3-input AND.
+ *
+ *        X = ((A1 | A2) & B1 & C1)
+ *
+ * Verilog wrapper for o211a with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o211a.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o211a_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o211a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o211a_4 (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o211a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O211A_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__EDFXBP_1_V
+`define SKY130_FD_SC_LS__EDFXBP_1_V
+
+/**
+ * edfxbp: Delay flop with loopback enable, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog wrapper for edfxbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__edfxbp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__edfxbp_1 (
+    Q   ,
+    Q_N ,
+    CLK ,
+    D   ,
+    DE  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    output Q_N ;
+    input  CLK ;
+    input  D   ;
+    input  DE  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__edfxbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .DE(DE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__edfxbp_1 (
+    Q  ,
+    Q_N,
+    CLK,
+    D  ,
+    DE
+);
+
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__edfxbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .DE(DE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EDFXBP_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__MAJ3_4_V
+`define SKY130_FD_SC_LS__MAJ3_4_V
+
+/**
+ * maj3: 3-input majority vote.
+ *
+ * Verilog wrapper for maj3 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__maj3.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__maj3_4 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__maj3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__maj3_4 (
+    X,
+    A,
+    B,
+    C
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__maj3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MAJ3_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O21BA_1_V
+`define SKY130_FD_SC_LS__O21BA_1_V
+
+/**
+ * o21ba: 2-input OR into first input of 2-input AND,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 | A2) & !B1_N)
+ *
+ * Verilog wrapper for o21ba with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o21ba.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o21ba_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o21ba base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o21ba_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o21ba base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21BA_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O2111A_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__O2111A_BEHAVIORAL_PP_V
+
+/**
+ * o2111a: 2-input OR into first input of 4-input AND.
+ *
+ *         X = ((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__o2111a (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1                );
+    and                                and0        (and0_out_X       , B1, C1, or0_out, D1   );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2111A_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__EDFXBP_BLACKBOX_V
+`define SKY130_FD_SC_LS__EDFXBP_BLACKBOX_V
+
+/**
+ * edfxbp: Delay flop with loopback enable, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__edfxbp (
+    Q  ,
+    Q_N,
+    CLK,
+    D  ,
+    DE
+);
+
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EDFXBP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if ((!A2&!B1&B2)) (A1 -=> Y) = (0:0:0,0:0:0);
+if ((!A2&B1&!B2)) (A1 -=> Y) = (0:0:0,0:0:0);
+if ((!A2&B1&B2)) (A1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!B1&B2)) (A2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&B1&!B2)) (A2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&B1&B2)) (A2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&!B2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&!B2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2&!B2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&!B1)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&!B1)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2&!B1)) (B2 -=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DFF_NRS_V
+`define SKY130_FD_SC_LS__UDP_DFF_NRS_V
+
+/**
+ * udp_dff$NRS: Negative edge triggered D flip-flop (Q output UDP)
+ *              with both active high reset and set (reset dominate).
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`include ""./sky130_fd_sc_ls__udp_dff_nrs.blackbox.v""
+`else
+primitive sky130_fd_sc_ls__udp_dff$NRS (
+    Q    ,
+    SET  ,
+    RESET,
+    CLK_N,
+    D
+);
+
+    output Q    ;
+    input  SET  ;
+    input  RESET;
+    input  CLK_N;
+    input  D    ;
+
+    reg Q;
+
+    table
+     // SET RESET CLK_N  D  :  Qt : Qt+1
+         1    0     ?    ?  :  ?  :  1    ; // Asserting preset
+         *    0     ?    ?  :  1  :  1    ; // Changing preset
+         ?    1     ?    ?  :  ?  :  0    ; // Asserting reset (dominates preset)
+         0    *     ?    ?  :  0  :  0    ; // Changing reset
+         0    ?    (01)  0  :  ?  :  0    ; // rising clock
+         ?    0    (01)  1  :  ?  :  1    ; // rising clock
+         0    ?     p    0  :  0  :  0    ; // potential rising clock
+         ?    0     p    1  :  1  :  1    ; // potential rising clock
+         0    0     n    ?  :  ?  :  -    ; // Clock falling register output does not change
+         0    0     ?    *  :  ?  :  -    ; // Changing Data
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DFF_NRS_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NAND2B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__NAND2B_FUNCTIONAL_PP_V
+
+/**
+ * nand2b: 2-input NAND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__nand2b (
+    Y   ,
+    A_N ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A_N ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire or0_out_Y        ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , B                    );
+    or                                 or0         (or0_out_Y        , not0_out, A_N        );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND2B_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NOR4BB_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__NOR4BB_FUNCTIONAL_V
+
+/**
+ * nor4bb: 4-input NOR, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__nor4bb (
+    Y  ,
+    A  ,
+    B  ,
+    C_N,
+    D_N
+);
+
+    // Module ports
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+    input  D_N;
+
+    // Local signals
+    wire nor0_out  ;
+    wire and0_out_Y;
+
+    //  Name  Output      Other arguments
+    nor nor0 (nor0_out  , A, B              );
+    and and0 (and0_out_Y, nor0_out, C_N, D_N);
+    buf buf0 (Y         , and0_out_Y        );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR4BB_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFXTP_TB_V
+`define SKY130_FD_SC_LS__DFXTP_TB_V
+
+/**
+ * dfxtp: Delay flop, single output.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dfxtp.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Q;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   D    = 1\'b0;
+        #40   VGND = 1\'b0;
+        #60   VNB  = 1\'b0;
+        #80   VPB  = 1\'b0;
+        #100  VPWR = 1\'b0;
+        #120  D    = 1\'b1;
+        #140  VGND = 1\'b1;
+        #160  VNB  = 1\'b1;
+        #180  VPB  = 1\'b1;
+        #200  VPWR = 1\'b1;
+        #220  D    = 1\'b0;
+        #240  VGND = 1\'b0;
+        #260  VNB  = 1\'b0;
+        #280  VPB  = 1\'b0;
+        #300  VPWR = 1\'b0;
+        #320  VPWR = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VNB  = 1\'b1;
+        #380  VGND = 1\'b1;
+        #400  D    = 1\'b1;
+        #420  VPWR = 1\'bx;
+        #440  VPB  = 1\'bx;
+        #460  VNB  = 1\'bx;
+        #480  VGND = 1\'bx;
+        #500  D    = 1\'bx;
+    end
+
+    // Create a clock
+    reg CLK;
+    initial
+    begin
+        CLK = 1\'b0;
+    end
+
+    always
+    begin
+        #5 CLK = ~CLK;
+    end
+
+    sky130_fd_sc_ls__dfxtp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFXTP_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR4BB_V
+`define SKY130_FD_SC_LS__OR4BB_V
+
+/**
+ * or4bb: 4-input OR, first two inputs inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__or4bb.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__or4bb.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__or4bb.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__or4bb.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR4BB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND4BB_TB_V
+`define SKY130_FD_SC_LS__NAND4BB_TB_V
+
+/**
+ * nand4bb: 4-input NAND, first two inputs inverted.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nand4bb.v""
+
+module top();
+
+    // Inputs are registered
+    reg A_N;
+    reg B_N;
+    reg C;
+    reg D;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A_N  = 1\'bX;
+        B_N  = 1\'bX;
+        C    = 1\'bX;
+        D    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A_N  = 1\'b0;
+        #40   B_N  = 1\'b0;
+        #60   C    = 1\'b0;
+        #80   D    = 1\'b0;
+        #100  VGND = 1\'b0;
+        #120  VNB  = 1\'b0;
+        #140  VPB  = 1\'b0;
+        #160  VPWR = 1\'b0;
+        #180  A_N  = 1\'b1;
+        #200  B_N  = 1\'b1;
+        #220  C    = 1\'b1;
+        #240  D    = 1\'b1;
+        #260  VGND = 1\'b1;
+        #280  VNB  = 1\'b1;
+        #300  VPB  = 1\'b1;
+        #320  VPWR = 1\'b1;
+        #340  A_N  = 1\'b0;
+        #360  B_N  = 1\'b0;
+        #380  C    = 1\'b0;
+        #400  D    = 1\'b0;
+        #420  VGND = 1\'b0;
+        #440  VNB  = 1\'b0;
+        #460  VPB  = 1\'b0;
+        #480  VPWR = 1\'b0;
+        #500  VPWR = 1\'b1;
+        #520  VPB  = 1\'b1;
+        #540  VNB  = 1\'b1;
+        #560  VGND = 1\'b1;
+        #580  D    = 1\'b1;
+        #600  C    = 1\'b1;
+        #620  B_N  = 1\'b1;
+        #640  A_N  = 1\'b1;
+        #660  VPWR = 1\'bx;
+        #680  VPB  = 1\'bx;
+        #700  VNB  = 1\'bx;
+        #720  VGND = 1\'bx;
+        #740  D    = 1\'bx;
+        #760  C    = 1\'bx;
+        #780  B_N  = 1\'bx;
+        #800  A_N  = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__nand4bb dut (.A_N(A_N), .B_N(B_N), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND4BB_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLYGATE4SD2_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__DLYGATE4SD2_FUNCTIONAL_V
+
+/**
+ * dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__dlygate4sd2 (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYGATE4SD2_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O21A_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__O21A_FUNCTIONAL_PP_V
+
+/**
+ * o21a: 2-input OR into first input of 2-input AND.
+ *
+ *       X = ((A1 | A2) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__o21a (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1                );
+    and                                and0        (and0_out_X       , or0_out, B1           );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21A_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFBBN_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__DFBBN_PP_BLACKBOX_V
+
+/**
+ * dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
+ *        complementary outputs.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dfbbn (
+    Q      ,
+    Q_N    ,
+    D      ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFBBN_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SDFRTN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__SDFRTN_FUNCTIONAL_PP_V
+
+/**
+ * sdfrtn: Scan delay flop, inverted reset, inverted clock,
+ *         single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v""
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+
+`celldefine
+module sky130_fd_sc_ls__sdfrtn (
+    Q      ,
+    CLK_N  ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    input  CLK_N  ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire buf_Q  ;
+    wire RESET  ;
+    wire intclk ;
+    wire mux_out;
+
+    //                                  Delay       Name       Output   Other arguments
+    not                                             not0      (RESET  , RESET_B                             );
+    not                                             not1      (intclk , CLK_N                               );
+    sky130_fd_sc_ls__udp_mux_2to1                   mux_2to10 (mux_out, D, SCD, SCE                         );
+    sky130_fd_sc_ls__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0      (buf_Q  , mux_out, intclk, RESET, , VPWR, VGND);
+    buf                                             buf0      (Q      , buf_Q                               );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFRTN_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FILL_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__FILL_PP_BLACKBOX_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__fill (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FILL_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A222OI_SYMBOL_V
+`define SKY130_FD_SC_LS__A222OI_SYMBOL_V
+
+/**
+ * a222oi: 2-input AND into all inputs of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a222oi (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  B1,
+    input  B2,
+    input  C1,
+    input  C2,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A222OI_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NAND2B_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__NAND2B_BEHAVIORAL_V
+
+/**
+ * nand2b: 2-input NAND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__nand2b (
+    Y  ,
+    A_N,
+    B
+);
+
+    // Module ports
+    output Y  ;
+    input  A_N;
+    input  B  ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out ;
+    wire or0_out_Y;
+
+    //  Name  Output     Other arguments
+    not not0 (not0_out , B              );
+    or  or0  (or0_out_Y, not0_out, A_N  );
+    buf buf0 (Y        , or0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND2B_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A2111OI_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__A2111OI_BEHAVIORAL_V
+
+/**
+ * a2111oi: 2-input AND into first input of 4-input NOR.
+ *
+ *          Y = !((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a2111oi (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out  ;
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out  , A1, A2              );
+    nor nor0 (nor0_out_Y, B1, C1, D1, and0_out);
+    buf buf0 (Y         , nor0_out_Y          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2111OI_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLRTP_V
+`define SKY130_FD_SC_LS__DLRTP_V
+
+/**
+ * dlrtp: Delay latch, inverted reset, non-inverted enable,
+ *        single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlrtp.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlrtp.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlrtp.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlrtp.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRTP_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O2111AI_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__O2111AI_PP_BLACKBOX_V
+
+/**
+ * o2111ai: 2-input OR into first input of 4-input NAND.
+ *
+ *          Y = !((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o2111ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2111AI_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD2_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__CLKDLYINV5SD2_PP_SYMBOL_V
+
+/**
+ * clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
+ *                stage gate.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__clkdlyinv5sd2 (
+    //# {{data|Data Signals}}
+    input  A   ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV5SD2_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLRTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__DLRTP_BEHAVIORAL_PP_V
+
+/**
+ * dlrtp: Delay latch, inverted reset, non-inverted enable,
+ *        single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_pr_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlrtp (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE   ,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire RESET          ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire GATE_delayed   ;
+    wire RESET_delayed  ;
+    wire RESET_B_delayed;
+    wire buf_Q          ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+
+    //                                     Name     Output  Other arguments
+    not                                    not0    (RESET , RESET_B_delayed                                     );
+    sky130_fd_sc_ls__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1\'b1 ) );
+    assign cond1 = ( awake && ( RESET_B === 1\'b1 ) );
+    buf                                    buf0    (Q     , buf_Q                                               );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRTP_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKBUF_V
+`define SKY130_FD_SC_LS__CLKBUF_V
+
+/**
+ * clkbuf: Clock tree buffer.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__clkbuf.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__clkbuf.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__clkbuf.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__clkbuf.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKBUF_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_PWRGOOD_PP_P_BLACKBOX_V
+`define SKY130_FD_SC_LS__UDP_PWRGOOD_PP_P_BLACKBOX_V
+
+/**
+
+ *   UDP_OUT :=x when VPWR!=1
+ *   UDP_OUT :=UDP_IN when VPWR==1
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__udp_pwrgood_pp$P (
+    UDP_OUT,
+    UDP_IN ,
+    VPWR
+);
+
+    output UDP_OUT;
+    input  UDP_IN ;
+    input  VPWR   ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_PWRGOOD_PP_P_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__AND3B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__AND3B_FUNCTIONAL_PP_V
+
+/**
+ * and3b: 3-input AND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__and3b (
+    X   ,
+    A_N ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , A_N                   );
+    and                                and0        (and0_out_X       , C, not0_out, B        );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND3B_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FAH_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__FAH_PP_BLACKBOX_V
+
+/**
+ * fah: Full adder.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__fah (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CI  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CI  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FAH_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A211OI_V
+`define SKY130_FD_SC_LS__A211OI_V
+
+/**
+ * a211oi: 2-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | B1 | C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a211oi.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a211oi.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a211oi.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a211oi.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A211OI_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O311A_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__O311A_PP_SYMBOL_V
+
+/**
+ * o311a: 3-input OR into 3-input AND.
+ *
+ *        X = ((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o311a (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  A3  ,
+    input  B1  ,
+    input  C1  ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O311A_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__BUFINV_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__BUFINV_PP_SYMBOL_V
+
+/**
+ * bufinv: Buffer followed by inverter.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__bufinv (
+    //# {{data|Data Signals}}
+    input  A   ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__BUFINV_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__EINVP_4_V
+`define SKY130_FD_SC_LS__EINVP_4_V
+
+/**
+ * einvp: Tri-state inverter, positive enable.
+ *
+ * Verilog wrapper for einvp with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__einvp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__einvp_4 (
+    Z   ,
+    A   ,
+    TE  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__einvp base (
+        .Z(Z),
+        .A(A),
+        .TE(TE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__einvp_4 (
+    Z ,
+    A ,
+    TE
+);
+
+    output Z ;
+    input  A ;
+    input  TE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__einvp base (
+        .Z(Z),
+        .A(A),
+        .TE(TE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EINVP_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O31A_BLACKBOX_V
+`define SKY130_FD_SC_LS__O31A_BLACKBOX_V
+
+/**
+ * o31a: 3-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & B1)
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o31a (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O31A_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O22AI_4_V
+`define SKY130_FD_SC_LS__O22AI_4_V
+
+/**
+ * o22ai: 2-input OR into both inputs of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o22ai with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o22ai.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o22ai_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o22ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o22ai_4 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o22ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O22AI_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A222O_SYMBOL_V
+`define SKY130_FD_SC_LS__A222O_SYMBOL_V
+
+/**
+ * a222o: 2-input AND into all inputs of 3-input OR.
+ *
+ *        X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a222o (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  B1,
+    input  B2,
+    input  C1,
+    input  C2,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A222O_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR2B_2_V
+`define SKY130_FD_SC_LS__OR2B_2_V
+
+/**
+ * or2b: 2-input OR, first input inverted.
+ *
+ * Verilog wrapper for or2b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__or2b.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__or2b_2 (
+    X   ,
+    A   ,
+    B_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__or2b base (
+        .X(X),
+        .A(A),
+        .B_N(B_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__or2b_2 (
+    X  ,
+    A  ,
+    B_N
+);
+
+    output X  ;
+    input  A  ;
+    input  B_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__or2b base (
+        .X(X),
+        .A(A),
+        .B_N(B_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR2B_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR4B_4_V
+`define SKY130_FD_SC_LS__OR4B_4_V
+
+/**
+ * or4b: 4-input OR, first input inverted.
+ *
+ * Verilog wrapper for or4b with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__or4b.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__or4b_4 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__or4b base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D_N(D_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__or4b_4 (
+    X  ,
+    A  ,
+    B  ,
+    C  ,
+    D_N
+);
+
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C  ;
+    input  D_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__or4b base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D_N(D_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR4B_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FAH_1_V
+`define SKY130_FD_SC_LS__FAH_1_V
+
+/**
+ * fah: Full adder.
+ *
+ * Verilog wrapper for fah with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__fah.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__fah_1 (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CI  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CI  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__fah base (
+        .COUT(COUT),
+        .SUM(SUM),
+        .A(A),
+        .B(B),
+        .CI(CI),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__fah_1 (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CI
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CI  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__fah base (
+        .COUT(COUT),
+        .SUM(SUM),
+        .A(A),
+        .B(B),
+        .CI(CI)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FAH_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NOR4B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__NOR4B_FUNCTIONAL_PP_V
+
+/**
+ * nor4b: 4-input NOR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__nor4b (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , D_N                   );
+    nor                                nor0        (nor0_out_Y       , A, B, C, not0_out     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR4B_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__EINVP_BLACKBOX_V
+`define SKY130_FD_SC_LS__EINVP_BLACKBOX_V
+
+/**
+ * einvp: Tri-state inverter, positive enable.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__einvp (
+    Z ,
+    A ,
+    TE
+);
+
+    output Z ;
+    input  A ;
+    input  TE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EINVP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A2BB2O_V
+`define SKY130_FD_SC_LS__A2BB2O_V
+
+/**
+ * a2bb2o: 2-input AND, both inputs inverted, into first input, and
+ *         2-input AND into 2nd input of 2-input OR.
+ *
+ *         X = ((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a2bb2o.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a2bb2o.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a2bb2o.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a2bb2o.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2BB2O_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DFSBP_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__DFSBP_BEHAVIORAL_V
+
+/**
+ * dfsbp: Delay flop, inverted set, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ls__udp_dff_ps_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dfsbp (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SET_B
+);
+
+    // Module ports
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q        ;
+    wire SET          ;
+    reg  notifier     ;
+    wire D_delayed    ;
+    wire SET_B_delayed;
+    wire CLK_delayed  ;
+    wire awake        ;
+    wire cond0        ;
+    wire cond1        ;
+
+    //                                  Name  Output  Other arguments
+    not                                 not0 (SET   , SET_B_delayed                                    );
+    sky130_fd_sc_ls__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    assign cond0 = ( SET_B_delayed === 1\'b1 );
+    assign cond1 = ( SET_B === 1\'b1 );
+    buf                                 buf0 (Q     , buf_Q                                            );
+    not                                 not1 (Q_N   , buf_Q                                            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFSBP_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__CLKINV_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__CLKINV_FUNCTIONAL_V
+
+/**
+ * clkinv: Clock tree inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__clkinv (
+    Y,
+    A
+);
+
+    // Module ports
+    output Y;
+    input  A;
+
+    // Local signals
+    wire not0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out_Y, A              );
+    buf buf0 (Y         , not0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKINV_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND3_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__AND3_PP_BLACKBOX_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__and3 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND3_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__FILL_DIODE_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__FILL_DIODE_BEHAVIORAL_V
+
+/**
+ * fill_diode: Fill diode.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__fill_diode ();
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FILL_DIODE_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__AND4B_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__AND4B_BEHAVIORAL_V
+
+/**
+ * and4b: 4-input AND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__and4b (
+    X  ,
+    A_N,
+    B  ,
+    C  ,
+    D
+);
+
+    // Module ports
+    output X  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+    input  D  ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out  ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out  , A_N              );
+    and and0 (and0_out_X, not0_out, B, C, D);
+    buf buf0 (X         , and0_out_X       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND4B_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+( D +=> Q ) = ( 0:0:0 , 0:0:0 ) ;  // delays are tris , tfall
+( D -=> Q_N ) = ( 0:0:0 , 0:0:0 ) ;  // delays are tris , tfall
+( negedge GATE_N => ( Q +: D ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall
+( negedge GATE_N => ( Q_N -: D ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are  tris , tfall
+$width ( negedge GATE_N &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+$setuphold ( posedge GATE_N , posedge D , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , GATEN_delayed , D_delayed ) ;
+$setuphold ( posedge GATE_N , negedge D , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , GATEN_delayed , D_delayed ) ;
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A311OI_V
+`define SKY130_FD_SC_LS__A311OI_V
+
+/**
+ * a311oi: 3-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a311oi.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a311oi.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a311oi.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a311oi.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A311OI_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLYGATE4SD1_V
+`define SKY130_FD_SC_LS__DLYGATE4SD1_V
+
+/**
+ * dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlygate4sd1.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlygate4sd1.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlygate4sd1.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlygate4sd1.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYGATE4SD1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A2BB2O_1_V
+`define SKY130_FD_SC_LS__A2BB2O_1_V
+
+/**
+ * a2bb2o: 2-input AND, both inputs inverted, into first input, and
+ *         2-input AND into 2nd input of 2-input OR.
+ *
+ *         X = ((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a2bb2o with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a2bb2o.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a2bb2o_1 (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a2bb2o base (
+        .X(X),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a2bb2o_1 (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a2bb2o base (
+        .X(X),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2BB2O_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A211OI_TB_V
+`define SKY130_FD_SC_LS__A211OI_TB_V
+
+/**
+ * a211oi: 2-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | B1 | C1)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a211oi.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg B1;
+    reg C1;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        B1   = 1\'bX;
+        C1   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   B1   = 1\'b0;
+        #80   C1   = 1\'b0;
+        #100  VGND = 1\'b0;
+        #120  VNB  = 1\'b0;
+        #140  VPB  = 1\'b0;
+        #160  VPWR = 1\'b0;
+        #180  A1   = 1\'b1;
+        #200  A2   = 1\'b1;
+        #220  B1   = 1\'b1;
+        #240  C1   = 1\'b1;
+        #260  VGND = 1\'b1;
+        #280  VNB  = 1\'b1;
+        #300  VPB  = 1\'b1;
+        #320  VPWR = 1\'b1;
+        #340  A1   = 1\'b0;
+        #360  A2   = 1\'b0;
+        #380  B1   = 1\'b0;
+        #400  C1   = 1\'b0;
+        #420  VGND = 1\'b0;
+        #440  VNB  = 1\'b0;
+        #460  VPB  = 1\'b0;
+        #480  VPWR = 1\'b0;
+        #500  VPWR = 1\'b1;
+        #520  VPB  = 1\'b1;
+        #540  VNB  = 1\'b1;
+        #560  VGND = 1\'b1;
+        #580  C1   = 1\'b1;
+        #600  B1   = 1\'b1;
+        #620  A2   = 1\'b1;
+        #640  A1   = 1\'b1;
+        #660  VPWR = 1\'bx;
+        #680  VPB  = 1\'bx;
+        #700  VNB  = 1\'bx;
+        #720  VGND = 1\'bx;
+        #740  C1   = 1\'bx;
+        #760  B1   = 1\'bx;
+        #780  A2   = 1\'bx;
+        #800  A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__a211oi dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A211OI_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKINV_V
+`define SKY130_FD_SC_LS__CLKINV_V
+
+/**
+ * clkinv: Clock tree inverter.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__clkinv.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__clkinv.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__clkinv.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__clkinv.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKINV_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A1 -=> Y) = (0:0:0,0:0:0);
+(A2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&C1&D1)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&C1&D1)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2&C1&D1)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&B1&D1)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&B1&D1)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2&B1&D1)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&B1&C1)) (D1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&B1&C1)) (D1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2&B1&C1)) (D1 -=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFRTP_1_V
+`define SKY130_FD_SC_LS__SDFRTP_1_V
+
+/**
+ * sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
+ *         single output.
+ *
+ * Verilog wrapper for sdfrtp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__sdfrtp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sdfrtp_1 (
+    Q      ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_ls__sdfrtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .RESET_B(RESET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sdfrtp_1 (
+    Q      ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B
+);
+
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__sdfrtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .RESET_B(RESET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFRTP_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFXTP_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__DFXTP_PP_SYMBOL_V
+
+/**
+ * dfxtp: Delay flop, single output.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dfxtp (
+    //# {{data|Data Signals}}
+    input  D   ,
+    output Q   ,
+
+    //# {{clocks|Clocking}}
+    input  CLK ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFXTP_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SEDFXTP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__SEDFXTP_FUNCTIONAL_PP_V
+
+/**
+ * sedfxtp: Scan delay flop, data enable, non-inverted clock,
+ *          single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+`include ""../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__sedfxtp (
+    Q   ,
+    CLK ,
+    D   ,
+    DE  ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  DE  ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q  ;
+    wire mux_out;
+    wire de_d   ;
+
+    //                                 Delay       Name       Output   Other arguments
+    sky130_fd_sc_ls__udp_mux_2to1                  mux_2to10 (mux_out, de_d, SCD, SCE            );
+    sky130_fd_sc_ls__udp_mux_2to1                  mux_2to11 (de_d   , buf_Q, D, DE              );
+    sky130_fd_sc_ls__udp_dff$P_pp$PG$N `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK, , VPWR, VGND);
+    buf                                            buf0      (Q      , buf_Q                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SEDFXTP_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__TAP_BLACKBOX_V
+`define SKY130_FD_SC_LS__TAP_BLACKBOX_V
+
+/**
+ * tap: Tap cell with no tap connections (no contacts on metal1).
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__tap ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A22OI_SYMBOL_V
+`define SKY130_FD_SC_LS__A22OI_SYMBOL_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a22oi (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  B1,
+    input  B2,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A22OI_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLCLKP_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__DLCLKP_FUNCTIONAL_V
+
+/**
+ * dlclkp: Clock gate.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_p/sky130_fd_sc_ls__udp_dlatch_p.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlclkp (
+    GCLK,
+    GATE,
+    CLK
+);
+
+    // Module ports
+    output GCLK;
+    input  GATE;
+    input  CLK ;
+
+    // Local signals
+    wire m0  ;
+    wire clkn;
+
+    //                            Name     Output  Other arguments
+    not                           not0    (clkn  , CLK            );
+    sky130_fd_sc_ls__udp_dlatch$P dlatch0 (m0    , GATE, clkn     );
+    and                           and0    (GCLK  , m0, CLK        );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLCLKP_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD2_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__CLKDLYINV3SD2_BEHAVIORAL_PP_V
+
+/**
+ * clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
+ *                stage gate.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__clkdlyinv3sd2 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out_Y       , A                     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV3SD2_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLYMETAL6S6S_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__DLYMETAL6S6S_PP_SYMBOL_V
+
+/**
+ * dlymetal6s6s: 6-inverter delay with output from 6th inverter on
+ *               horizontal route.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlymetal6s6s (
+    //# {{data|Data Signals}}
+    input  A   ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYMETAL6S6S_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__MUX2_2_V
+`define SKY130_FD_SC_LS__MUX2_2_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Verilog wrapper for mux2 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__mux2.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__mux2_2 (
+    X   ,
+    A0  ,
+    A1  ,
+    S   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A0  ;
+    input  A1  ;
+    input  S   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__mux2 base (
+        .X(X),
+        .A0(A0),
+        .A1(A1),
+        .S(S),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__mux2_2 (
+    X ,
+    A0,
+    A1,
+    S
+);
+
+    output X ;
+    input  A0;
+    input  A1;
+    input  S ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__mux2 base (
+        .X(X),
+        .A0(A0),
+        .A1(A1),
+        .S(S)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MUX2_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O2111AI_BLACKBOX_V
+`define SKY130_FD_SC_LS__O2111AI_BLACKBOX_V
+
+/**
+ * o2111ai: 2-input OR into first input of 4-input NAND.
+ *
+ *          Y = !((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o2111ai (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2111AI_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A222O_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__A222O_FUNCTIONAL_V
+
+/**
+ * a222o: 2-input AND into all inputs of 3-input OR.
+ *
+ *        X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a222o (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1,
+    C2
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+    input  C2;
+
+    // Local signals
+    wire and0_out ;
+    wire and1_out ;
+    wire and2_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , B1, B2                      );
+    and and1 (and1_out , A1, A2                      );
+    and and2 (and2_out , C1, C2                      );
+    or  or0  (or0_out_X, and1_out, and0_out, and2_out);
+    buf buf0 (X        , or0_out_X                   );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A222O_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_MUX_2TO1_N_BLACKBOX_V
+`define SKY130_FD_SC_LS__UDP_MUX_2TO1_N_BLACKBOX_V
+
+/**
+ * udp_mux_2to1_N: Two to one multiplexer with inverting output
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__udp_mux_2to1_N (
+    Y ,
+    A0,
+    A1,
+    S
+);
+
+    output Y ;
+    input  A0;
+    input  A1;
+    input  S ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_MUX_2TO1_N_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR2_SYMBOL_V
+`define SKY130_FD_SC_LS__OR2_SYMBOL_V
+
+/**
+ * or2: 2-input OR.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__or2 (
+    //# {{data|Data Signals}}
+    input  A,
+    input  B,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR2_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND4B_TB_V
+`define SKY130_FD_SC_LS__AND4B_TB_V
+
+/**
+ * and4b: 4-input AND, first input inverted.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__and4b.v""
+
+module top();
+
+    // Inputs are registered
+    reg A_N;
+    reg B;
+    reg C;
+    reg D;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A_N  = 1\'bX;
+        B    = 1\'bX;
+        C    = 1\'bX;
+        D    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A_N  = 1\'b0;
+        #40   B    = 1\'b0;
+        #60   C    = 1\'b0;
+        #80   D    = 1\'b0;
+        #100  VGND = 1\'b0;
+        #120  VNB  = 1\'b0;
+        #140  VPB  = 1\'b0;
+        #160  VPWR = 1\'b0;
+        #180  A_N  = 1\'b1;
+        #200  B    = 1\'b1;
+        #220  C    = 1\'b1;
+        #240  D    = 1\'b1;
+        #260  VGND = 1\'b1;
+        #280  VNB  = 1\'b1;
+        #300  VPB  = 1\'b1;
+        #320  VPWR = 1\'b1;
+        #340  A_N  = 1\'b0;
+        #360  B    = 1\'b0;
+        #380  C    = 1\'b0;
+        #400  D    = 1\'b0;
+        #420  VGND = 1\'b0;
+        #440  VNB  = 1\'b0;
+        #460  VPB  = 1\'b0;
+        #480  VPWR = 1\'b0;
+        #500  VPWR = 1\'b1;
+        #520  VPB  = 1\'b1;
+        #540  VNB  = 1\'b1;
+        #560  VGND = 1\'b1;
+        #580  D    = 1\'b1;
+        #600  C    = 1\'b1;
+        #620  B    = 1\'b1;
+        #640  A_N  = 1\'b1;
+        #660  VPWR = 1\'bx;
+        #680  VPB  = 1\'bx;
+        #700  VNB  = 1\'bx;
+        #720  VGND = 1\'bx;
+        #740  D    = 1\'bx;
+        #760  C    = 1\'bx;
+        #780  B    = 1\'bx;
+        #800  A_N  = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__and4b dut (.A_N(A_N), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND4B_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__BUFBUF_V
+`define SKY130_FD_SC_LS__BUFBUF_V
+
+/**
+ * bufbuf: Double buffer.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__bufbuf.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__bufbuf.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__bufbuf.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__bufbuf.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__BUFBUF_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__MAJ3_1_V
+`define SKY130_FD_SC_LS__MAJ3_1_V
+
+/**
+ * maj3: 3-input majority vote.
+ *
+ * Verilog wrapper for maj3 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__maj3.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__maj3_1 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__maj3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__maj3_1 (
+    X,
+    A,
+    B,
+    C
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__maj3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MAJ3_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND4_4_V
+`define SKY130_FD_SC_LS__NAND4_4_V
+
+/**
+ * nand4: 4-input NAND.
+ *
+ * Verilog wrapper for nand4 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nand4.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nand4_4 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nand4 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nand4_4 (
+    Y,
+    A,
+    B,
+    C,
+    D
+);
+
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nand4 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND4_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKINV_2_V
+`define SKY130_FD_SC_LS__CLKINV_2_V
+
+/**
+ * clkinv: Clock tree inverter.
+ *
+ * Verilog wrapper for clkinv with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__clkinv.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__clkinv_2 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__clkinv base (
+        .Y(Y),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__clkinv_2 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__clkinv base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKINV_2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DECAPHETAP_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__DECAPHETAP_BEHAVIORAL_V
+
+/**
+
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__decaphetap ();
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DECAPHETAP_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLRTN_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__DLRTN_PP_BLACKBOX_V
+
+/**
+ * dlrtn: Delay latch, inverted reset, inverted enable, single output.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlrtn (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE_N ,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE_N ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRTN_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__MUX2I_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__MUX2I_FUNCTIONAL_PP_V
+
+/**
+ * mux2i: 2-input multiplexer, output inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1_n/sky130_fd_sc_ls__udp_mux_2to1_n.v""
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__mux2i (
+    Y   ,
+    A0  ,
+    A1  ,
+    S   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A0  ;
+    input  A1  ;
+    input  S   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire mux_2to1_n0_out_Y;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    sky130_fd_sc_ls__udp_mux_2to1_N    mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S                    );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, mux_2to1_n0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MUX2I_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD2_TB_V
+`define SKY130_FD_SC_LS__CLKDLYINV3SD2_TB_V
+
+/**
+ * clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
+ *                stage gate.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__clkdlyinv3sd2.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   VGND = 1\'b0;
+        #60   VNB  = 1\'b0;
+        #80   VPB  = 1\'b0;
+        #100  VPWR = 1\'b0;
+        #120  A    = 1\'b1;
+        #140  VGND = 1\'b1;
+        #160  VNB  = 1\'b1;
+        #180  VPB  = 1\'b1;
+        #200  VPWR = 1\'b1;
+        #220  A    = 1\'b0;
+        #240  VGND = 1\'b0;
+        #260  VNB  = 1\'b0;
+        #280  VPB  = 1\'b0;
+        #300  VPWR = 1\'b0;
+        #320  VPWR = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VNB  = 1\'b1;
+        #380  VGND = 1\'b1;
+        #400  A    = 1\'b1;
+        #420  VPWR = 1\'bx;
+        #440  VPB  = 1\'bx;
+        #460  VNB  = 1\'bx;
+        #480  VGND = 1\'bx;
+        #500  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__clkdlyinv3sd2 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV3SD2_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR4BB_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__NOR4BB_PP_BLACKBOX_V
+
+/**
+ * nor4bb: 4-input NOR, first two inputs inverted.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nor4bb (
+    Y   ,
+    A   ,
+    B   ,
+    C_N ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR4BB_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLXBN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__DLXBN_FUNCTIONAL_PP_V
+
+/**
+ * dlxbn: Delay latch, inverted enable, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlxbn (
+    Q     ,
+    Q_N   ,
+    D     ,
+    GATE_N,
+    VPWR  ,
+    VGND  ,
+    VPB   ,
+    VNB
+);
+
+    // Module ports
+    output Q     ;
+    output Q_N   ;
+    input  D     ;
+    input  GATE_N;
+    input  VPWR  ;
+    input  VGND  ;
+    input  VPB   ;
+    input  VNB   ;
+
+    // Local signals
+    wire GATE ;
+    wire buf_Q;
+
+    //                                    Delay       Name     Output  Other arguments
+    not                                               not0    (GATE  , GATE_N               );
+    sky130_fd_sc_ls__udp_dlatch$P_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
+    buf                                               buf0    (Q     , buf_Q                );
+    not                                               not1    (Q_N   , buf_Q                );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXBN_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR3B_BLACKBOX_V
+`define SKY130_FD_SC_LS__NOR3B_BLACKBOX_V
+
+/**
+ * nor3b: 3-input NOR, first input inverted.
+ *
+ *        Y = (!(A | B)) & !C)
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nor3b (
+    Y  ,
+    A  ,
+    B  ,
+    C_N
+);
+
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR3B_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O41A_2_V
+`define SKY130_FD_SC_LS__O41A_2_V
+
+/**
+ * o41a: 4-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog wrapper for o41a with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o41a.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o41a_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o41a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o41a_2 (
+    X ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o41a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O41A_2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A22OI_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__A22OI_BEHAVIORAL_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a22oi (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nand0_out ;
+    wire nand1_out ;
+    wire and0_out_Y;
+
+    //   Name   Output      Other arguments
+    nand nand0 (nand0_out , A2, A1              );
+    nand nand1 (nand1_out , B2, B1              );
+    and  and0  (and0_out_Y, nand0_out, nand1_out);
+    buf  buf0  (Y         , and0_out_Y          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A22OI_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SEDFXTP_TB_V
+`define SKY130_FD_SC_LS__SEDFXTP_TB_V
+
+/**
+ * sedfxtp: Scan delay flop, data enable, non-inverted clock,
+ *          single output.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__sedfxtp.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg DE;
+    reg SCD;
+    reg SCE;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Q;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D    = 1\'bX;
+        DE   = 1\'bX;
+        SCD  = 1\'bX;
+        SCE  = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   D    = 1\'b0;
+        #40   DE   = 1\'b0;
+        #60   SCD  = 1\'b0;
+        #80   SCE  = 1\'b0;
+        #100  VGND = 1\'b0;
+        #120  VNB  = 1\'b0;
+        #140  VPB  = 1\'b0;
+        #160  VPWR = 1\'b0;
+        #180  D    = 1\'b1;
+        #200  DE   = 1\'b1;
+        #220  SCD  = 1\'b1;
+        #240  SCE  = 1\'b1;
+        #260  VGND = 1\'b1;
+        #280  VNB  = 1\'b1;
+        #300  VPB  = 1\'b1;
+        #320  VPWR = 1\'b1;
+        #340  D    = 1\'b0;
+        #360  DE   = 1\'b0;
+        #380  SCD  = 1\'b0;
+        #400  SCE  = 1\'b0;
+        #420  VGND = 1\'b0;
+        #440  VNB  = 1\'b0;
+        #460  VPB  = 1\'b0;
+        #480  VPWR = 1\'b0;
+        #500  VPWR = 1\'b1;
+        #520  VPB  = 1\'b1;
+        #540  VNB  = 1\'b1;
+        #560  VGND = 1\'b1;
+        #580  SCE  = 1\'b1;
+        #600  SCD  = 1\'b1;
+        #620  DE   = 1\'b1;
+        #640  D    = 1\'b1;
+        #660  VPWR = 1\'bx;
+        #680  VPB  = 1\'bx;
+        #700  VNB  = 1\'bx;
+        #720  VGND = 1\'bx;
+        #740  SCE  = 1\'bx;
+        #760  SCD  = 1\'bx;
+        #780  DE   = 1\'bx;
+        #800  D    = 1\'bx;
+    end
+
+    // Create a clock
+    reg CLK;
+    initial
+    begin
+        CLK = 1\'b0;
+    end
+
+    always
+    begin
+        #5 CLK = ~CLK;
+    end
+
+    sky130_fd_sc_ls__sedfxtp dut (.D(D), .DE(DE), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SEDFXTP_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A31O_SYMBOL_V
+`define SKY130_FD_SC_LS__A31O_SYMBOL_V
+
+/**
+ * a31o: 3-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | B1)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a31o (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  A3,
+    input  B1,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A31O_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND3B_2_V
+`define SKY130_FD_SC_LS__AND3B_2_V
+
+/**
+ * and3b: 3-input AND, first input inverted.
+ *
+ * Verilog wrapper for and3b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__and3b.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__and3b_2 (
+    X   ,
+    A_N ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__and3b base (
+        .X(X),
+        .A_N(A_N),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__and3b_2 (
+    X  ,
+    A_N,
+    B  ,
+    C
+);
+
+    output X  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__and3b base (
+        .X(X),
+        .A_N(A_N),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND3B_2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A +=> X) = (0:0:0,0:0:0);
+(B +=> X) = (0:0:0,0:0:0);
+(C +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A +=> X) = (0:0:0,0:0:0);
+(B +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFSTP_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__SDFSTP_PP_BLACKBOX_V
+
+/**
+ * sdfstp: Scan delay flop, inverted set, non-inverted clock,
+ *         single output.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sdfstp (
+    Q    ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFSTP_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A22O_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__A22O_FUNCTIONAL_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ *       X = ((A1 & A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a22o (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Local signals
+    wire and0_out ;
+    wire and1_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , B1, B2            );
+    and and1 (and1_out , A1, A2            );
+    or  or0  (or0_out_X, and1_out, and0_out);
+    buf buf0 (X        , or0_out_X         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A22O_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O221AI_SYMBOL_V
+`define SKY130_FD_SC_LS__O221AI_SYMBOL_V
+
+/**
+ * o221ai: 2-input OR into first two inputs of 3-input NAND.
+ *
+ *         Y = !((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o221ai (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  B1,
+    input  B2,
+    input  C1,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O221AI_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLXTN_4_V
+`define SKY130_FD_SC_LS__DLXTN_4_V
+
+/**
+ * dlxtn: Delay latch, inverted enable, single output.
+ *
+ * Verilog wrapper for dlxtn with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dlxtn.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dlxtn_4 (
+    Q     ,
+    D     ,
+    GATE_N,
+    VPWR  ,
+    VGND  ,
+    VPB   ,
+    VNB
+);
+
+    output Q     ;
+    input  D     ;
+    input  GATE_N;
+    input  VPWR  ;
+    input  VGND  ;
+    input  VPB   ;
+    input  VNB   ;
+    sky130_fd_sc_ls__dlxtn base (
+        .Q(Q),
+        .D(D),
+        .GATE_N(GATE_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dlxtn_4 (
+    Q     ,
+    D     ,
+    GATE_N
+);
+
+    output Q     ;
+    input  D     ;
+    input  GATE_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__dlxtn base (
+        .Q(Q),
+        .D(D),
+        .GATE_N(GATE_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXTN_4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__CLKINV_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__CLKINV_BEHAVIORAL_PP_V
+
+/**
+ * clkinv: Clock tree inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__clkinv (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out_Y       , A                     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKINV_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A2BB2OI_BLACKBOX_V
+`define SKY130_FD_SC_LS__A2BB2OI_BLACKBOX_V
+
+/**
+ * a2bb2oi: 2-input AND, both inputs inverted, into first input, and
+ *          2-input AND into 2nd input of 2-input NOR.
+ *
+ *          Y = !((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a2bb2oi (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2BB2OI_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NAND2B_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__NAND2B_FUNCTIONAL_V
+
+/**
+ * nand2b: 2-input NAND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__nand2b (
+    Y  ,
+    A_N,
+    B
+);
+
+    // Module ports
+    output Y  ;
+    input  A_N;
+    input  B  ;
+
+    // Local signals
+    wire not0_out ;
+    wire or0_out_Y;
+
+    //  Name  Output     Other arguments
+    not not0 (not0_out , B              );
+    or  or0  (or0_out_Y, not0_out, A_N  );
+    buf buf0 (Y        , or0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND2B_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLYMETAL6S6S_BLACKBOX_V
+`define SKY130_FD_SC_LS__DLYMETAL6S6S_BLACKBOX_V
+
+/**
+ * dlymetal6s6s: 6-inverter delay with output from 6th inverter on
+ *               horizontal route.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlymetal6s6s (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYMETAL6S6S_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DFRTP_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__DFRTP_FUNCTIONAL_V
+
+/**
+ * dfrtp: Delay flop, inverted reset, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_pr/sky130_fd_sc_ls__udp_dff_pr.v""
+
+`celldefine
+module sky130_fd_sc_ls__dfrtp (
+    Q      ,
+    CLK    ,
+    D      ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+
+    // Local signals
+    wire buf_Q;
+    wire RESET;
+
+    //                          Delay       Name  Output  Other arguments
+    not                                     not0 (RESET , RESET_B        );
+    sky130_fd_sc_ls__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET  );
+    buf                                     buf0 (Q     , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFRTP_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if ((A2_N&!B1&B2)) (A1_N -=> X) = (0:0:0,0:0:0);
+if ((A2_N&B1&!B2)) (A1_N -=> X) = (0:0:0,0:0:0);
+if ((A2_N&B1&B2)) (A1_N -=> X) = (0:0:0,0:0:0);
+if ((A1_N&!B1&B2)) (A2_N -=> X) = (0:0:0,0:0:0);
+if ((A1_N&B1&!B2)) (A2_N -=> X) = (0:0:0,0:0:0);
+if ((A1_N&B1&B2)) (A2_N -=> X) = (0:0:0,0:0:0);
+if ((!A1_N&!A2_N&!B2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1_N&A2_N&!B2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1_N&!A2_N&!B2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1_N&!A2_N&!B1)) (B2 +=> X) = (0:0:0,0:0:0);
+if ((!A1_N&A2_N&!B1)) (B2 +=> X) = (0:0:0,0:0:0);
+if ((A1_N&!A2_N&!B1)) (B2 +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFXTP_BLACKBOX_V
+`define SKY130_FD_SC_LS__DFXTP_BLACKBOX_V
+
+/**
+ * dfxtp: Delay flop, single output.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dfxtp (
+    Q  ,
+    CLK,
+    D
+);
+
+    output Q  ;
+    input  CLK;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFXTP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O41A_1_V
+`define SKY130_FD_SC_LS__O41A_1_V
+
+/**
+ * o41a: 4-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog wrapper for o41a with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o41a.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o41a_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o41a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o41a_1 (
+    X ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o41a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O41A_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A2111O_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__A2111O_PP_SYMBOL_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ *         X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a2111o (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  B1  ,
+    input  C1  ,
+    input  D1  ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2111O_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NAND4B_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__NAND4B_BEHAVIORAL_PP_V
+
+/**
+ * nand4b: 4-input NAND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__nand4b (
+    Y   ,
+    A_N ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , A_N                    );
+    nand                               nand0       (nand0_out_Y      , D, C, B, not0_out      );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND4B_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O2111AI_4_V
+`define SKY130_FD_SC_LS__O2111AI_4_V
+
+/**
+ * o2111ai: 2-input OR into first input of 4-input NAND.
+ *
+ *          Y = !((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog wrapper for o2111ai with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o2111ai.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o2111ai_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o2111ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o2111ai_4 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o2111ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2111AI_4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__EINVP_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__EINVP_BEHAVIORAL_V
+
+/**
+ * einvp: Tri-state inverter, positive enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__einvp (
+    Z ,
+    A ,
+    TE
+);
+
+    // Module ports
+    output Z ;
+    input  A ;
+    input  TE;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    //     Name     Output  Other arguments
+    notif1 notif10 (Z     , A, TE          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EINVP_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A2BB2O_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__A2BB2O_FUNCTIONAL_V
+
+/**
+ * a2bb2o: 2-input AND, both inputs inverted, into first input, and
+ *         2-input AND into 2nd input of 2-input OR.
+ *
+ *         X = ((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a2bb2o (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    // Module ports
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Local signals
+    wire and0_out ;
+    wire nor0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , B1, B2            );
+    nor nor0 (nor0_out , A1_N, A2_N        );
+    or  or0  (or0_out_X, nor0_out, and0_out);
+    buf buf0 (X        , or0_out_X         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2BB2O_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_MUX_2TO1_SYMBOL_V
+`define SKY130_FD_SC_LS__UDP_MUX_2TO1_SYMBOL_V
+
+/**
+ * udp_mux_2to1: Two to one multiplexer
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__udp_mux_2to1 (
+    //# {{data|Data Signals}}
+    input  A0,
+    input  A1,
+    output X ,
+
+    //# {{control|Control Signals}}
+    input  S
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_MUX_2TO1_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLYMETAL6S6S_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__DLYMETAL6S6S_BEHAVIORAL_PP_V
+
+/**
+ * dlymetal6s6s: 6-inverter delay with output from 6th inverter on
+ *               horizontal route.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlymetal6s6s (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYMETAL6S6S_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__BUFINV_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__BUFINV_PP_BLACKBOX_V
+
+/**
+ * bufinv: Buffer followed by inverter.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__bufinv (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__BUFINV_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLCLKP_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__DLCLKP_PP_BLACKBOX_V
+
+/**
+ * dlclkp: Clock gate.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlclkp (
+    GCLK,
+    GATE,
+    CLK ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output GCLK;
+    input  GATE;
+    input  CLK ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLCLKP_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A -=> Y) = (0:0:0,0:0:0);
+(B -=> Y) = (0:0:0,0:0:0);
+(C_N +=> Y) = (0:0:0,0:0:0);
+(D_N +=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__EBUFN_1_V
+`define SKY130_FD_SC_LS__EBUFN_1_V
+
+/**
+ * ebufn: Tri-state buffer, negative enable.
+ *
+ * Verilog wrapper for ebufn with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__ebufn.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__ebufn_1 (
+    Z   ,
+    A   ,
+    TE_B,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__ebufn base (
+        .Z(Z),
+        .A(A),
+        .TE_B(TE_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__ebufn_1 (
+    Z   ,
+    A   ,
+    TE_B
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__ebufn base (
+        .Z(Z),
+        .A(A),
+        .TE_B(TE_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EBUFN_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD2_BLACKBOX_V
+`define SKY130_FD_SC_LS__CLKDLYINV5SD2_BLACKBOX_V
+
+/**
+ * clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
+ *                stage gate.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__clkdlyinv5sd2 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV5SD2_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND4BB_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__AND4BB_PP_SYMBOL_V
+
+/**
+ * and4bb: 4-input AND, first two inputs inverted.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__and4bb (
+    //# {{data|Data Signals}}
+    input  A_N ,
+    input  B_N ,
+    input  C   ,
+    input  D   ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND4BB_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A311OI_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__A311OI_PP_SYMBOL_V
+
+/**
+ * a311oi: 3-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a311oi (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  A3  ,
+    input  B1  ,
+    input  C1  ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A311OI_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__MUX4_2_V
+`define SKY130_FD_SC_LS__MUX4_2_V
+
+/**
+ * mux4: 4-input multiplexer.
+ *
+ * Verilog wrapper for mux4 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__mux4.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__mux4_2 (
+    X   ,
+    A0  ,
+    A1  ,
+    A2  ,
+    A3  ,
+    S0  ,
+    S1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A0  ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  S0  ;
+    input  S1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__mux4 base (
+        .X(X),
+        .A0(A0),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .S0(S0),
+        .S1(S1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__mux4_2 (
+    X ,
+    A0,
+    A1,
+    A2,
+    A3,
+    S0,
+    S1
+);
+
+    output X ;
+    input  A0;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  S0;
+    input  S1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__mux4 base (
+        .X(X),
+        .A0(A0),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .S0(S0),
+        .S1(S1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MUX4_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLRBP_2_V
+`define SKY130_FD_SC_LS__DLRBP_2_V
+
+/**
+ * dlrbp: Delay latch, inverted reset, non-inverted enable,
+ *        complementary outputs.
+ *
+ * Verilog wrapper for dlrbp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dlrbp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dlrbp_2 (
+    Q      ,
+    Q_N    ,
+    RESET_B,
+    D      ,
+    GATE   ,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_ls__dlrbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .RESET_B(RESET_B),
+        .D(D),
+        .GATE(GATE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dlrbp_2 (
+    Q      ,
+    Q_N    ,
+    RESET_B,
+    D      ,
+    GATE
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__dlrbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .RESET_B(RESET_B),
+        .D(D),
+        .GATE(GATE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRBP_2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A +=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O21AI_1_V
+`define SKY130_FD_SC_LS__O21AI_1_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & B1)
+ *
+ * Verilog wrapper for o21ai with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o21ai.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o21ai_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o21ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o21ai_1 (
+    Y ,
+    A1,
+    A2,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o21ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21AI_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLXBP_BLACKBOX_V
+`define SKY130_FD_SC_LS__DLXBP_BLACKBOX_V
+
+/**
+ * dlxbp: Delay latch, non-inverted enable, complementary outputs.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlxbp (
+    Q   ,
+    Q_N ,
+    D   ,
+    GATE
+);
+
+    output Q   ;
+    output Q_N ;
+    input  D   ;
+    input  GATE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXBP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DFXTP_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__DFXTP_BEHAVIORAL_V
+
+/**
+ * dfxtp: Delay flop, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dfxtp (
+    Q  ,
+    CLK,
+    D
+);
+
+    // Module ports
+    output Q  ;
+    input  CLK;
+    input  D  ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q      ;
+    reg  notifier   ;
+    wire D_delayed  ;
+    wire CLK_delayed;
+    wire awake      ;
+
+    //                                 Name  Output  Other arguments
+    sky130_fd_sc_ls__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    buf                                buf0 (Q     , buf_Q                                       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFXTP_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR4BB_TB_V
+`define SKY130_FD_SC_LS__NOR4BB_TB_V
+
+/**
+ * nor4bb: 4-input NOR, first two inputs inverted.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nor4bb.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg B;
+    reg C_N;
+    reg D_N;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        B    = 1\'bX;
+        C_N  = 1\'bX;
+        D_N  = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   B    = 1\'b0;
+        #60   C_N  = 1\'b0;
+        #80   D_N  = 1\'b0;
+        #100  VGND = 1\'b0;
+        #120  VNB  = 1\'b0;
+        #140  VPB  = 1\'b0;
+        #160  VPWR = 1\'b0;
+        #180  A    = 1\'b1;
+        #200  B    = 1\'b1;
+        #220  C_N  = 1\'b1;
+        #240  D_N  = 1\'b1;
+        #260  VGND = 1\'b1;
+        #280  VNB  = 1\'b1;
+        #300  VPB  = 1\'b1;
+        #320  VPWR = 1\'b1;
+        #340  A    = 1\'b0;
+        #360  B    = 1\'b0;
+        #380  C_N  = 1\'b0;
+        #400  D_N  = 1\'b0;
+        #420  VGND = 1\'b0;
+        #440  VNB  = 1\'b0;
+        #460  VPB  = 1\'b0;
+        #480  VPWR = 1\'b0;
+        #500  VPWR = 1\'b1;
+        #520  VPB  = 1\'b1;
+        #540  VNB  = 1\'b1;
+        #560  VGND = 1\'b1;
+        #580  D_N  = 1\'b1;
+        #600  C_N  = 1\'b1;
+        #620  B    = 1\'b1;
+        #640  A    = 1\'b1;
+        #660  VPWR = 1\'bx;
+        #680  VPB  = 1\'bx;
+        #700  VNB  = 1\'bx;
+        #720  VGND = 1\'bx;
+        #740  D_N  = 1\'bx;
+        #760  C_N  = 1\'bx;
+        #780  B    = 1\'bx;
+        #800  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__nor4bb dut (.A(A), .B(B), .C_N(C_N), .D_N(D_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR4BB_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__EINVN_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__EINVN_FUNCTIONAL_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__einvn (
+    Z   ,
+    A   ,
+    TE_B
+);
+
+    // Module ports
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+
+    //     Name     Output  Other arguments
+    notif0 notif00 (Z     , A, TE_B        );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EINVN_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A41OI_BLACKBOX_V
+`define SKY130_FD_SC_LS__A41OI_BLACKBOX_V
+
+/**
+ * a41oi: 4-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a41oi (
+    Y ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A41OI_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DLATCH_P_BLACKBOX_V
+`define SKY130_FD_SC_LS__UDP_DLATCH_P_BLACKBOX_V
+
+/**
+ * udp_dlatch$P: D-latch, gated standard drive / active high
+ *               (Q output UDP)
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__udp_dlatch$P (
+    Q   ,
+    D   ,
+    GATE
+);
+
+    output Q   ;
+    input  D   ;
+    input  GATE;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DLATCH_P_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DFF_NSR_PP_PG_N_BLACKBOX_V
+`define SKY130_FD_SC_LS__UDP_DFF_NSR_PP_PG_N_BLACKBOX_V
+
+/**
+ * udp_dff$NSR_pp$PG$N: Negative edge triggered D flip-flop
+ *                      (Q output UDP) with both active high reset and
+ *                      set (set dominate). Includes VPWR and VGND
+ *                      power pins and notifier pin.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__udp_dff$NSR_pp$PG$N (
+    Q       ,
+    SET     ,
+    RESET   ,
+    CLK_N   ,
+    D       ,
+    NOTIFIER,
+    VPWR    ,
+    VGND
+);
+
+    output Q       ;
+    input  SET     ;
+    input  RESET   ;
+    input  CLK_N   ;
+    input  D       ;
+    input  NOTIFIER;
+    input  VPWR    ;
+    input  VGND    ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DFF_NSR_PP_PG_N_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SEDFXBP_V
+`define SKY130_FD_SC_LS__SEDFXBP_V
+
+/**
+ * sedfxbp: Scan delay flop, data enable, non-inverted clock,
+ *          complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__sedfxbp.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__sedfxbp.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__sedfxbp.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__sedfxbp.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SEDFXBP_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NAND4_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__NAND4_FUNCTIONAL_PP_V
+
+/**
+ * nand4: 4-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__nand4 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out_Y      , D, C, B, A             );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND4_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FA_2_V
+`define SKY130_FD_SC_LS__FA_2_V
+
+/**
+ * fa: Full adder.
+ *
+ * Verilog wrapper for fa with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__fa.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__fa_2 (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CIN ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CIN ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__fa base (
+        .COUT(COUT),
+        .SUM(SUM),
+        .A(A),
+        .B(B),
+        .CIN(CIN),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__fa_2 (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CIN
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CIN ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__fa base (
+        .COUT(COUT),
+        .SUM(SUM),
+        .A(A),
+        .B(B),
+        .CIN(CIN)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FA_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DECAPHE_V
+`define SKY130_FD_SC_LS__DECAPHE_V
+
+/**
+ * decaphe: Shielded Decoupling capacitance filler.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__decaphe.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__decaphe.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__decaphe.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__decaphe.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DECAPHE_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLXTN_2_V
+`define SKY130_FD_SC_LS__DLXTN_2_V
+
+/**
+ * dlxtn: Delay latch, inverted enable, single output.
+ *
+ * Verilog wrapper for dlxtn with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dlxtn.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dlxtn_2 (
+    Q     ,
+    D     ,
+    GATE_N,
+    VPWR  ,
+    VGND  ,
+    VPB   ,
+    VNB
+);
+
+    output Q     ;
+    input  D     ;
+    input  GATE_N;
+    input  VPWR  ;
+    input  VGND  ;
+    input  VPB   ;
+    input  VNB   ;
+    sky130_fd_sc_ls__dlxtn base (
+        .Q(Q),
+        .D(D),
+        .GATE_N(GATE_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dlxtn_2 (
+    Q     ,
+    D     ,
+    GATE_N
+);
+
+    output Q     ;
+    input  D     ;
+    input  GATE_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__dlxtn base (
+        .Q(Q),
+        .D(D),
+        .GATE_N(GATE_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXTN_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__MUX2_1_V
+`define SKY130_FD_SC_LS__MUX2_1_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Verilog wrapper for mux2 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__mux2.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__mux2_1 (
+    X   ,
+    A0  ,
+    A1  ,
+    S   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A0  ;
+    input  A1  ;
+    input  S   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__mux2 base (
+        .X(X),
+        .A0(A0),
+        .A1(A1),
+        .S(S),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__mux2_1 (
+    X ,
+    A0,
+    A1,
+    S
+);
+
+    output X ;
+    input  A0;
+    input  A1;
+    input  S ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__mux2 base (
+        .X(X),
+        .A0(A0),
+        .A1(A1),
+        .S(S)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MUX2_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFBBN_1_V
+`define SKY130_FD_SC_LS__SDFBBN_1_V
+
+/**
+ * sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
+ *         clock, complementary outputs.
+ *
+ * Verilog wrapper for sdfbbn with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__sdfbbn.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sdfbbn_1 (
+    Q      ,
+    Q_N    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_ls__sdfbbn base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .CLK_N(CLK_N),
+        .SET_B(SET_B),
+        .RESET_B(RESET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sdfbbn_1 (
+    Q      ,
+    Q_N    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__sdfbbn base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .CLK_N(CLK_N),
+        .SET_B(SET_B),
+        .RESET_B(RESET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFBBN_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND4_TB_V
+`define SKY130_FD_SC_LS__NAND4_TB_V
+
+/**
+ * nand4: 4-input NAND.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nand4.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg B;
+    reg C;
+    reg D;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        B    = 1\'bX;
+        C    = 1\'bX;
+        D    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   B    = 1\'b0;
+        #60   C    = 1\'b0;
+        #80   D    = 1\'b0;
+        #100  VGND = 1\'b0;
+        #120  VNB  = 1\'b0;
+        #140  VPB  = 1\'b0;
+        #160  VPWR = 1\'b0;
+        #180  A    = 1\'b1;
+        #200  B    = 1\'b1;
+        #220  C    = 1\'b1;
+        #240  D    = 1\'b1;
+        #260  VGND = 1\'b1;
+        #280  VNB  = 1\'b1;
+        #300  VPB  = 1\'b1;
+        #320  VPWR = 1\'b1;
+        #340  A    = 1\'b0;
+        #360  B    = 1\'b0;
+        #380  C    = 1\'b0;
+        #400  D    = 1\'b0;
+        #420  VGND = 1\'b0;
+        #440  VNB  = 1\'b0;
+        #460  VPB  = 1\'b0;
+        #480  VPWR = 1\'b0;
+        #500  VPWR = 1\'b1;
+        #520  VPB  = 1\'b1;
+        #540  VNB  = 1\'b1;
+        #560  VGND = 1\'b1;
+        #580  D    = 1\'b1;
+        #600  C    = 1\'b1;
+        #620  B    = 1\'b1;
+        #640  A    = 1\'b1;
+        #660  VPWR = 1\'bx;
+        #680  VPB  = 1\'bx;
+        #700  VNB  = 1\'bx;
+        #720  VGND = 1\'bx;
+        #740  D    = 1\'bx;
+        #760  C    = 1\'bx;
+        #780  B    = 1\'bx;
+        #800  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__nand4 dut (.A(A), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND4_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A21BO_V
+`define SKY130_FD_SC_LS__A21BO_V
+
+/**
+ * a21bo: 2-input AND into first input of 2-input OR,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 & A2) | (!B1_N))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a21bo.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a21bo.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a21bo.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a21bo.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21BO_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A31O_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__A31O_FUNCTIONAL_V
+
+/**
+ * a31o: 3-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a31o (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Local signals
+    wire and0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , A3, A1, A2     );
+    or  or0  (or0_out_X, and0_out, B1   );
+    buf buf0 (X        , or0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A31O_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O2BB2AI_1_V
+`define SKY130_FD_SC_LS__O2BB2AI_1_V
+
+/**
+ * o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
+ *
+ *          Y = !(!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o2bb2ai with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o2bb2ai.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o2bb2ai_1 (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o2bb2ai base (
+        .Y(Y),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o2bb2ai_1 (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o2bb2ai base (
+        .Y(Y),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2BB2AI_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A_N -=> X) = (0:0:0,0:0:0);
+(B +=> X) = (0:0:0,0:0:0);
+(C +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A31O_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__A31O_PP_SYMBOL_V
+
+/**
+ * a31o: 3-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | B1)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a31o (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  A3  ,
+    input  B1  ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A31O_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND4BB_2_V
+`define SKY130_FD_SC_LS__NAND4BB_2_V
+
+/**
+ * nand4bb: 4-input NAND, first two inputs inverted.
+ *
+ * Verilog wrapper for nand4bb with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nand4bb.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nand4bb_2 (
+    Y   ,
+    A_N ,
+    B_N ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A_N ;
+    input  B_N ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nand4bb base (
+        .Y(Y),
+        .A_N(A_N),
+        .B_N(B_N),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nand4bb_2 (
+    Y  ,
+    A_N,
+    B_N,
+    C  ,
+    D
+);
+
+    output Y  ;
+    input  A_N;
+    input  B_N;
+    input  C  ;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nand4bb base (
+        .Y(Y),
+        .A_N(A_N),
+        .B_N(B_N),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND4BB_2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SEDFXTP_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__SEDFXTP_FUNCTIONAL_V
+
+/**
+ * sedfxtp: Scan delay flop, data enable, non-inverted clock,
+ *          single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+`include ""../../models/udp_dff_p/sky130_fd_sc_ls__udp_dff_p.v""
+
+`celldefine
+module sky130_fd_sc_ls__sedfxtp (
+    Q  ,
+    CLK,
+    D  ,
+    DE ,
+    SCD,
+    SCE
+);
+
+    // Module ports
+    output Q  ;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+    input  SCD;
+    input  SCE;
+
+    // Local signals
+    wire buf_Q  ;
+    wire mux_out;
+    wire de_d   ;
+
+    //                            Delay       Name       Output   Other arguments
+    sky130_fd_sc_ls__udp_mux_2to1             mux_2to10 (mux_out, de_d, SCD, SCE );
+    sky130_fd_sc_ls__udp_mux_2to1             mux_2to11 (de_d   , buf_Q, D, DE   );
+    sky130_fd_sc_ls__udp_dff$P    `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK   );
+    buf                                       buf0      (Q      , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SEDFXTP_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A -=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FILL_SYMBOL_V
+`define SKY130_FD_SC_LS__FILL_SYMBOL_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__fill ();
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FILL_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SDFXTP_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__SDFXTP_BEHAVIORAL_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+`include ""../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__sdfxtp (
+    Q  ,
+    CLK,
+    D  ,
+    SCD,
+    SCE
+);
+
+    // Module ports
+    output Q  ;
+    input  CLK;
+    input  D  ;
+    input  SCD;
+    input  SCE;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q      ;
+    wire mux_out    ;
+    reg  notifier   ;
+    wire D_delayed  ;
+    wire SCD_delayed;
+    wire SCE_delayed;
+    wire CLK_delayed;
+    wire awake      ;
+    wire cond1      ;
+    wire cond2      ;
+    wire cond3      ;
+
+    //                                 Name       Output   Other arguments
+    sky130_fd_sc_ls__udp_mux_2to1      mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed       );
+    sky130_fd_sc_ls__udp_dff$P_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    assign cond1 = ( ( SCE_delayed === 1\'b0 ) && awake );
+    assign cond2 = ( ( SCE_delayed === 1\'b1 ) && awake );
+    assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
+    buf                                buf0      (Q      , buf_Q                                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFXTP_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O2BB2AI_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__O2BB2AI_PP_SYMBOL_V
+
+/**
+ * o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
+ *
+ *          Y = !(!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o2bb2ai (
+    //# {{data|Data Signals}}
+    input  A1_N,
+    input  A2_N,
+    input  B1  ,
+    input  B2  ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2BB2AI_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND4B_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__NAND4B_PP_BLACKBOX_V
+
+/**
+ * nand4b: 4-input NAND, first input inverted.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nand4b (
+    Y   ,
+    A_N ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND4B_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR3_TB_V
+`define SKY130_FD_SC_LS__NOR3_TB_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ *       Y = !(A | B | C | !D)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nor3.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg B;
+    reg C;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        B    = 1\'bX;
+        C    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   B    = 1\'b0;
+        #60   C    = 1\'b0;
+        #80   VGND = 1\'b0;
+        #100  VNB  = 1\'b0;
+        #120  VPB  = 1\'b0;
+        #140  VPWR = 1\'b0;
+        #160  A    = 1\'b1;
+        #180  B    = 1\'b1;
+        #200  C    = 1\'b1;
+        #220  VGND = 1\'b1;
+        #240  VNB  = 1\'b1;
+        #260  VPB  = 1\'b1;
+        #280  VPWR = 1\'b1;
+        #300  A    = 1\'b0;
+        #320  B    = 1\'b0;
+        #340  C    = 1\'b0;
+        #360  VGND = 1\'b0;
+        #380  VNB  = 1\'b0;
+        #400  VPB  = 1\'b0;
+        #420  VPWR = 1\'b0;
+        #440  VPWR = 1\'b1;
+        #460  VPB  = 1\'b1;
+        #480  VNB  = 1\'b1;
+        #500  VGND = 1\'b1;
+        #520  C    = 1\'b1;
+        #540  B    = 1\'b1;
+        #560  A    = 1\'b1;
+        #580  VPWR = 1\'bx;
+        #600  VPB  = 1\'bx;
+        #620  VNB  = 1\'bx;
+        #640  VGND = 1\'bx;
+        #660  C    = 1\'bx;
+        #680  B    = 1\'bx;
+        #700  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__nor3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR3_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLYMETAL6S2S_BLACKBOX_V
+`define SKY130_FD_SC_LS__DLYMETAL6S2S_BLACKBOX_V
+
+/**
+ * dlymetal6s2s: 6-inverter delay with output from 2nd stage on
+ *               horizontal route.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlymetal6s2s (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYMETAL6S2S_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NOR2B_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__NOR2B_FUNCTIONAL_V
+
+/**
+ * nor2b: 2-input NOR, first input inverted.
+ *
+ *        Y = !(A | B | C | !D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__nor2b (
+    Y  ,
+    A  ,
+    B_N
+);
+
+    // Module ports
+    output Y  ;
+    input  A  ;
+    input  B_N;
+
+    // Local signals
+    wire not0_out  ;
+    wire and0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out  , A              );
+    and and0 (and0_out_Y, not0_out, B_N  );
+    buf buf0 (Y         , and0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR2B_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DFRTP_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__DFRTP_BEHAVIORAL_V
+
+/**
+ * dfrtp: Delay flop, inverted reset, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dfrtp (
+    Q      ,
+    CLK    ,
+    D      ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q          ;
+    wire RESET          ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire RESET_B_delayed;
+    wire CLK_delayed    ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+
+    //                                  Name  Output  Other arguments
+    not                                 not0 (RESET , RESET_B_delayed                                    );
+    sky130_fd_sc_ls__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1\'b1 ) );
+    assign cond1 = ( awake && ( RESET_B === 1\'b1 ) );
+    buf                                 buf0 (Q     , buf_Q                                              );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFRTP_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__TAPVGND_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__TAPVGND_PP_BLACKBOX_V
+
+/**
+ * tapvgnd: Tap cell with tap to ground, isolated power connection
+ *          1 row down.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__tapvgnd (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPVGND_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__XNOR2_1_V
+`define SKY130_FD_SC_LS__XNOR2_1_V
+
+/**
+ * xnor2: 2-input exclusive NOR.
+ *
+ *        Y = !(A ^ B)
+ *
+ * Verilog wrapper for xnor2 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__xnor2.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__xnor2_1 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__xnor2 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__xnor2_1 (
+    Y,
+    A,
+    B
+);
+
+    output Y;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__xnor2 base (
+        .Y(Y),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XNOR2_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_PWRGOOD_PP_PG_TB_V
+`define SKY130_FD_SC_LS__UDP_PWRGOOD_PP_PG_TB_V
+
+/**
+
+ *   UDP_OUT :=x when VPWR!=1 or VGND!=0
+ *   UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+module top();
+
+    // Inputs are registered
+    reg UDP_IN;
+    reg VPWR;
+    reg VGND;
+
+    // Outputs are wires
+    wire UDP_OUT;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        UDP_IN = 1\'bX;
+        VGND   = 1\'bX;
+        VPWR   = 1\'bX;
+
+        #20   UDP_IN = 1\'b0;
+        #40   VGND   = 1\'b0;
+        #60   VPWR   = 1\'b0;
+        #80   UDP_IN = 1\'b1;
+        #100  VGND   = 1\'b1;
+        #120  VPWR   = 1\'b1;
+        #140  UDP_IN = 1\'b0;
+        #160  VGND   = 1\'b0;
+        #180  VPWR   = 1\'b0;
+        #200  VPWR   = 1\'b1;
+        #220  VGND   = 1\'b1;
+        #240  UDP_IN = 1\'b1;
+        #260  VPWR   = 1\'bx;
+        #280  VGND   = 1\'bx;
+        #300  UDP_IN = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG dut (.UDP_IN(UDP_IN), .VPWR(VPWR), .VGND(VGND), .UDP_OUT(UDP_OUT));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_PWRGOOD_PP_PG_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKINV_BLACKBOX_V
+`define SKY130_FD_SC_LS__CLKINV_BLACKBOX_V
+
+/**
+ * clkinv: Clock tree inverter.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__clkinv (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKINV_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NAND3B_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__NAND3B_BEHAVIORAL_V
+
+/**
+ * nand3b: 3-input NAND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__nand3b (
+    Y  ,
+    A_N,
+    B  ,
+    C
+);
+
+    // Module ports
+    output Y  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out   ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    not  not0  (not0_out   , A_N            );
+    nand nand0 (nand0_out_Y, B, not0_out, C );
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND3B_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SDFXTP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__SDFXTP_FUNCTIONAL_PP_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+`include ""../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__sdfxtp (
+    Q   ,
+    CLK ,
+    D   ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q  ;
+    wire mux_out;
+
+    //                                 Delay       Name       Output   Other arguments
+    sky130_fd_sc_ls__udp_mux_2to1                  mux_2to10 (mux_out, D, SCD, SCE               );
+    sky130_fd_sc_ls__udp_dff$P_pp$PG$N `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK, , VPWR, VGND);
+    buf                                            buf0      (Q      , buf_Q                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFXTP_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND4BB_BLACKBOX_V
+`define SKY130_FD_SC_LS__AND4BB_BLACKBOX_V
+
+/**
+ * and4bb: 4-input AND, first two inputs inverted.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__and4bb (
+    X  ,
+    A_N,
+    B_N,
+    C  ,
+    D
+);
+
+    output X  ;
+    input  A_N;
+    input  B_N;
+    input  C  ;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND4BB_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A22OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__A22OI_BEHAVIORAL_PP_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a22oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out        ;
+    wire nand1_out        ;
+    wire and0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out        , A2, A1                );
+    nand                               nand1       (nand1_out        , B2, B1                );
+    and                                and0        (and0_out_Y       , nand0_out, nand1_out  );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A22OI_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__TAP_V
+`define SKY130_FD_SC_LS__TAP_V
+
+/**
+ * tap: Tap cell with no tap connections (no contacts on metal1).
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__tap.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__tap.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__tap.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__tap.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAP_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SDFBBP_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__SDFBBP_FUNCTIONAL_V
+
+/**
+ * sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
+ *         clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_nsr/sky130_fd_sc_ls__udp_dff_nsr.v""
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+
+`celldefine
+module sky130_fd_sc_ls__sdfbbp (
+    Q      ,
+    Q_N    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    CLK    ,
+    SET_B  ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  CLK    ;
+    input  SET_B  ;
+    input  RESET_B;
+
+    // Local signals
+    wire RESET  ;
+    wire SET    ;
+    wire buf_Q  ;
+    wire mux_out;
+
+    //                            Delay       Name       Output   Other arguments
+    not                                       not0      (RESET  , RESET_B                 );
+    not                                       not1      (SET    , SET_B                   );
+    sky130_fd_sc_ls__udp_mux_2to1             mux_2to10 (mux_out, D, SCD, SCE             );
+    sky130_fd_sc_ls__udp_dff$NSR  `UNIT_DELAY dff0      (buf_Q  , SET, RESET, CLK, mux_out);
+    buf                                       buf0      (Q      , buf_Q                   );
+    not                                       not2      (Q_N    , buf_Q                   );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFBBP_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFSTP_1_V
+`define SKY130_FD_SC_LS__DFSTP_1_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Verilog wrapper for dfstp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dfstp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dfstp_1 (
+    Q    ,
+    CLK  ,
+    D    ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_ls__dfstp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SET_B(SET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dfstp_1 (
+    Q    ,
+    CLK  ,
+    D    ,
+    SET_B
+);
+
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__dfstp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SET_B(SET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFSTP_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if ((A2&!B1&!B2&!C1&!C2)) (A1 -=> Y) = (0:0:0,0:0:0);
+if ((A2&!B1&!B2&!C1&C2)) (A1 -=> Y) = (0:0:0,0:0:0);
+if ((A2&!B1&!B2&C1&!C2)) (A1 -=> Y) = (0:0:0,0:0:0);
+if ((A2&!B1&B2&!C1&!C2)) (A1 -=> Y) = (0:0:0,0:0:0);
+if ((A2&!B1&B2&!C1&C2)) (A1 -=> Y) = (0:0:0,0:0:0);
+if ((A2&!B1&B2&C1&!C2)) (A1 -=> Y) = (0:0:0,0:0:0);
+if ((A2&B1&!B2&!C1&!C2)) (A1 -=> Y) = (0:0:0,0:0:0);
+if ((A2&B1&!B2&!C1&C2)) (A1 -=> Y) = (0:0:0,0:0:0);
+if ((A2&B1&!B2&C1&!C2)) (A1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!B1&!B2&!C1&!C2)) (A2 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!B1&!B2&!C1&C2)) (A2 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!B1&!B2&C1&!C2)) (A2 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!B1&B2&!C1&!C2)) (A2 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!B1&B2&!C1&C2)) (A2 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!B1&B2&C1&!C2)) (A2 -=> Y) = (0:0:0,0:0:0);
+if ((A1&B1&!B2&!C1&!C2)) (A2 -=> Y) = (0:0:0,0:0:0);
+if ((A1&B1&!B2&!C1&C2)) (A2 -=> Y) = (0:0:0,0:0:0);
+if ((A1&B1&!B2&C1&!C2)) (A2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&B2&!C1&!C2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&B2&!C1&C2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&B2&C1&!C2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&B2&!C1&!C2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&B2&!C1&C2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&B2&C1&!C2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&B2&!C1&!C2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&B2&!C1&C2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&B2&C1&!C2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&B1&!C1&!C2)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&B1&!C1&C2)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&B1&C1&!C2)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&B1&!C1&!C2)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&B1&!C1&C2)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&B1&C1&!C2)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&B1&!C1&!C2)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&B1&!C1&C2)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&B1&C1&!C2)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&!B1&!B2&C2)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&!B1&B2&C2)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&B1&!B2&C2)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&!B1&!B2&C2)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&!B1&B2&C2)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&B1&!B2&C2)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&!B1&!B2&C2)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&!B1&B2&C2)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&B1&!B2&C2)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&!B1&!B2&C1)) (C2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&!B1&B2&C1)) (C2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&B1&!B2&C1)) (C2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&!B1&!B2&C1)) (C2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&!B1&B2&C1)) (C2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&B1&!B2&C1)) (C2 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&!B1&!B2&C1)) (C2 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&!B1&B2&C1)) (C2 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&B1&!B2&C1)) (C2 -=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR4B_2_V
+`define SKY130_FD_SC_LS__NOR4B_2_V
+
+/**
+ * nor4b: 4-input NOR, first input inverted.
+ *
+ * Verilog wrapper for nor4b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nor4b.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor4b_2 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nor4b base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D_N(D_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor4b_2 (
+    Y  ,
+    A  ,
+    B  ,
+    C  ,
+    D_N
+);
+
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C  ;
+    input  D_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nor4b base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D_N(D_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR4B_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DECAP_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__DECAP_PP_BLACKBOX_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__decap (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DECAP_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__XOR3_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__XOR3_PP_BLACKBOX_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ *       X = A ^ B ^ C
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__xor3 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XOR3_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__XNOR2_V
+`define SKY130_FD_SC_LS__XNOR2_V
+
+/**
+ * xnor2: 2-input exclusive NOR.
+ *
+ *        Y = !(A ^ B)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__xnor2.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__xnor2.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__xnor2.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__xnor2.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XNOR2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__BUF_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__BUF_BEHAVIORAL_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__buf (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__BUF_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_MUX_4TO2_TB_V
+`define SKY130_FD_SC_LS__UDP_MUX_4TO2_TB_V
+
+/**
+ * udp_mux_4to2: Four to one multiplexer with 2 select controls
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__udp_mux_4to2.v""
+
+module top();
+
+    // Inputs are registered
+    reg A0;
+    reg A1;
+    reg A2;
+    reg A3;
+    reg S0;
+    reg S1;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A0 = 1\'bX;
+        A1 = 1\'bX;
+        A2 = 1\'bX;
+        A3 = 1\'bX;
+        S0 = 1\'bX;
+        S1 = 1\'bX;
+
+        #20   A0 = 1\'b0;
+        #40   A1 = 1\'b0;
+        #60   A2 = 1\'b0;
+        #80   A3 = 1\'b0;
+        #100  S0 = 1\'b0;
+        #120  S1 = 1\'b0;
+        #140  A0 = 1\'b1;
+        #160  A1 = 1\'b1;
+        #180  A2 = 1\'b1;
+        #200  A3 = 1\'b1;
+        #220  S0 = 1\'b1;
+        #240  S1 = 1\'b1;
+        #260  A0 = 1\'b0;
+        #280  A1 = 1\'b0;
+        #300  A2 = 1\'b0;
+        #320  A3 = 1\'b0;
+        #340  S0 = 1\'b0;
+        #360  S1 = 1\'b0;
+        #380  S1 = 1\'b1;
+        #400  S0 = 1\'b1;
+        #420  A3 = 1\'b1;
+        #440  A2 = 1\'b1;
+        #460  A1 = 1\'b1;
+        #480  A0 = 1\'b1;
+        #500  S1 = 1\'bx;
+        #520  S0 = 1\'bx;
+        #540  A3 = 1\'bx;
+        #560  A2 = 1\'bx;
+        #580  A1 = 1\'bx;
+        #600  A0 = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__udp_mux_4to2 dut (.A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S0), .S1(S1), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_MUX_4TO2_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NAND4BB_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__NAND4BB_FUNCTIONAL_PP_V
+
+/**
+ * nand4bb: 4-input NAND, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__nand4bb (
+    Y   ,
+    A_N ,
+    B_N ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A_N ;
+    input  B_N ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out        ;
+    wire or0_out_Y        ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out        , D, C                 );
+    or                                 or0         (or0_out_Y        , B_N, A_N, nand0_out  );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND4BB_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A_N +=> Y) = (0:0:0,0:0:0);
+(B -=> Y) = (0:0:0,0:0:0);
+(C -=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O2BB2AI_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__O2BB2AI_PP_BLACKBOX_V
+
+/**
+ * o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
+ *
+ *          Y = !(!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o2bb2ai (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2BB2AI_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__AND3_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__AND3_FUNCTIONAL_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__and3 (
+    X,
+    A,
+    B,
+    C
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Local signals
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out_X, C, A, B        );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND3_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__INV_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__INV_BEHAVIORAL_PP_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__inv (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out_Y       , A                     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__INV_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__EDFXTP_SYMBOL_V
+`define SKY130_FD_SC_LS__EDFXTP_SYMBOL_V
+
+/**
+ * edfxtp: Delay flop with loopback enable, non-inverted clock,
+ *         single output.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__edfxtp (
+    //# {{data|Data Signals}}
+    input  D  ,
+    output Q  ,
+
+    //# {{control|Control Signals}}
+    input  DE ,
+
+    //# {{clocks|Clocking}}
+    input  CLK
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EDFXTP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O221A_V
+`define SKY130_FD_SC_LS__O221A_V
+
+/**
+ * o221a: 2-input OR into first two inputs of 3-input AND.
+ *
+ *        X = ((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o221a.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o221a.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o221a.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o221a.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O221A_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A21O_SYMBOL_V
+`define SKY130_FD_SC_LS__A21O_SYMBOL_V
+
+/**
+ * a21o: 2-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2) | B1)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a21o (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  B1,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21O_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A222O_TB_V
+`define SKY130_FD_SC_LS__A222O_TB_V
+
+/**
+ * a222o: 2-input AND into all inputs of 3-input OR.
+ *
+ *        X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a222o.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg B1;
+    reg B2;
+    reg C1;
+    reg C2;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        B1   = 1\'bX;
+        B2   = 1\'bX;
+        C1   = 1\'bX;
+        C2   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   B1   = 1\'b0;
+        #80   B2   = 1\'b0;
+        #100  C1   = 1\'b0;
+        #120  C2   = 1\'b0;
+        #140  VGND = 1\'b0;
+        #160  VNB  = 1\'b0;
+        #180  VPB  = 1\'b0;
+        #200  VPWR = 1\'b0;
+        #220  A1   = 1\'b1;
+        #240  A2   = 1\'b1;
+        #260  B1   = 1\'b1;
+        #280  B2   = 1\'b1;
+        #300  C1   = 1\'b1;
+        #320  C2   = 1\'b1;
+        #340  VGND = 1\'b1;
+        #360  VNB  = 1\'b1;
+        #380  VPB  = 1\'b1;
+        #400  VPWR = 1\'b1;
+        #420  A1   = 1\'b0;
+        #440  A2   = 1\'b0;
+        #460  B1   = 1\'b0;
+        #480  B2   = 1\'b0;
+        #500  C1   = 1\'b0;
+        #520  C2   = 1\'b0;
+        #540  VGND = 1\'b0;
+        #560  VNB  = 1\'b0;
+        #580  VPB  = 1\'b0;
+        #600  VPWR = 1\'b0;
+        #620  VPWR = 1\'b1;
+        #640  VPB  = 1\'b1;
+        #660  VNB  = 1\'b1;
+        #680  VGND = 1\'b1;
+        #700  C2   = 1\'b1;
+        #720  C1   = 1\'b1;
+        #740  B2   = 1\'b1;
+        #760  B1   = 1\'b1;
+        #780  A2   = 1\'b1;
+        #800  A1   = 1\'b1;
+        #820  VPWR = 1\'bx;
+        #840  VPB  = 1\'bx;
+        #860  VNB  = 1\'bx;
+        #880  VGND = 1\'bx;
+        #900  C2   = 1\'bx;
+        #920  C1   = 1\'bx;
+        #940  B2   = 1\'bx;
+        #960  B1   = 1\'bx;
+        #980  A2   = 1\'bx;
+        #1000 A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__a222o dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .C2(C2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A222O_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLXBP_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__DLXBP_PP_SYMBOL_V
+
+/**
+ * dlxbp: Delay latch, non-inverted enable, complementary outputs.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlxbp (
+    //# {{data|Data Signals}}
+    input  D   ,
+    output Q   ,
+    output Q_N ,
+
+    //# {{clocks|Clocking}}
+    input  GATE,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXBP_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A22O_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__A22O_BEHAVIORAL_PP_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ *       X = ((A1 & A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a22o (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire and1_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , B1, B2               );
+    and                                and1        (and1_out         , A1, A2               );
+    or                                 or0         (or0_out_X        , and1_out, and0_out   );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A22O_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A -=> Y) = (0:0:0,0:0:0);
+(B -=> Y) = (0:0:0,0:0:0);
+(C -=> Y) = (0:0:0,0:0:0);
+(D -=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O21BAI_TB_V
+`define SKY130_FD_SC_LS__O21BAI_TB_V
+
+/**
+ * o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
+ *         inverted.
+ *
+ *         Y = !((A1 | A2) & !B1_N)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o21bai.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg B1_N;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        B1_N = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   B1_N = 1\'b0;
+        #80   VGND = 1\'b0;
+        #100  VNB  = 1\'b0;
+        #120  VPB  = 1\'b0;
+        #140  VPWR = 1\'b0;
+        #160  A1   = 1\'b1;
+        #180  A2   = 1\'b1;
+        #200  B1_N = 1\'b1;
+        #220  VGND = 1\'b1;
+        #240  VNB  = 1\'b1;
+        #260  VPB  = 1\'b1;
+        #280  VPWR = 1\'b1;
+        #300  A1   = 1\'b0;
+        #320  A2   = 1\'b0;
+        #340  B1_N = 1\'b0;
+        #360  VGND = 1\'b0;
+        #380  VNB  = 1\'b0;
+        #400  VPB  = 1\'b0;
+        #420  VPWR = 1\'b0;
+        #440  VPWR = 1\'b1;
+        #460  VPB  = 1\'b1;
+        #480  VNB  = 1\'b1;
+        #500  VGND = 1\'b1;
+        #520  B1_N = 1\'b1;
+        #540  A2   = 1\'b1;
+        #560  A1   = 1\'b1;
+        #580  VPWR = 1\'bx;
+        #600  VPB  = 1\'bx;
+        #620  VNB  = 1\'bx;
+        #640  VGND = 1\'bx;
+        #660  B1_N = 1\'bx;
+        #680  A2   = 1\'bx;
+        #700  A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__o21bai dut (.A1(A1), .A2(A2), .B1_N(B1_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21BAI_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SDFRTP_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__SDFRTP_BEHAVIORAL_V
+
+/**
+ * sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
+ *         single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v""
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+
+`celldefine
+module sky130_fd_sc_ls__sdfrtp (
+    Q      ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q          ;
+    wire RESET          ;
+    wire mux_out        ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire SCD_delayed    ;
+    wire SCE_delayed    ;
+    wire RESET_B_delayed;
+    wire CLK_delayed    ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+    wire cond2          ;
+    wire cond3          ;
+    wire cond4          ;
+
+    //                                  Name       Output   Other arguments
+    not                                 not0      (RESET  , RESET_B_delayed                                  );
+    sky130_fd_sc_ls__udp_mux_2to1       mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed              );
+    sky130_fd_sc_ls__udp_dff$PR_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    assign cond0 = ( ( RESET_B_delayed === 1\'b1 ) && awake );
+    assign cond1 = ( ( SCE_delayed === 1\'b0 ) && cond0 );
+    assign cond2 = ( ( SCE_delayed === 1\'b1 ) && cond0 );
+    assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
+    assign cond4 = ( ( RESET_B === 1\'b1 ) && awake );
+    buf                                 buf0      (Q      , buf_Q                                            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFRTP_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__BUFBUF_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__BUFBUF_FUNCTIONAL_V
+
+/**
+ * bufbuf: Double buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__bufbuf (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__BUFBUF_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFSBP_SYMBOL_V
+`define SKY130_FD_SC_LS__SDFSBP_SYMBOL_V
+
+/**
+ * sdfsbp: Scan delay flop, inverted set, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sdfsbp (
+    //# {{data|Data Signals}}
+    input  D    ,
+    output Q    ,
+    output Q_N  ,
+
+    //# {{control|Control Signals}}
+    input  SET_B,
+
+    //# {{scanchain|Scan Chain}}
+    input  SCD  ,
+    input  SCE  ,
+
+    //# {{clocks|Clocking}}
+    input  CLK
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFSBP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND2_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__AND2_PP_SYMBOL_V
+
+/**
+ * and2: 2-input AND.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__and2 (
+    //# {{data|Data Signals}}
+    input  A   ,
+    input  B   ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND2_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLRBP_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__DLRBP_BEHAVIORAL_V
+
+/**
+ * dlrbp: Delay latch, inverted reset, non-inverted enable,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_pr_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlrbp (
+    Q      ,
+    Q_N    ,
+    RESET_B,
+    D      ,
+    GATE
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire RESET          ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire GATE_delayed   ;
+    wire RESET_delayed  ;
+    wire RESET_B_delayed;
+    wire buf_Q          ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+
+    //                                     Name     Output  Other arguments
+    not                                    not0    (RESET , RESET_B_delayed                                     );
+    sky130_fd_sc_ls__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1\'b1 ) );
+    assign cond1 = ( awake && ( RESET_B === 1\'b1 ) );
+    buf                                    buf0    (Q     , buf_Q                                               );
+    not                                    not1    (Q_N   , buf_Q                                               );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRBP_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__TAPMET1_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__TAPMET1_FUNCTIONAL_V
+
+/**
+ * tapmet1: Tap cell with isolated power and ground connections.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__tapmet1 ();
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPMET1_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A211O_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__A211O_PP_BLACKBOX_V
+
+/**
+ * a211o: 2-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2) | B1 | C1)
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a211o (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A211O_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FILL_V
+`define SKY130_FD_SC_LS__FILL_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__fill.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__fill.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__fill.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__fill.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FILL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLYMETAL6S6S_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__DLYMETAL6S6S_FUNCTIONAL_PP_V
+
+/**
+ * dlymetal6s6s: 6-inverter delay with output from 6th inverter on
+ *               horizontal route.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlymetal6s6s (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYMETAL6S6S_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND4BB_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__NAND4BB_PP_BLACKBOX_V
+
+/**
+ * nand4bb: 4-input NAND, first two inputs inverted.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nand4bb (
+    Y   ,
+    A_N ,
+    B_N ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A_N ;
+    input  B_N ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND4BB_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SEDFXBP_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__SEDFXBP_FUNCTIONAL_V
+
+/**
+ * sedfxbp: Scan delay flop, data enable, non-inverted clock,
+ *          complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+`include ""../../models/udp_dff_p/sky130_fd_sc_ls__udp_dff_p.v""
+
+`celldefine
+module sky130_fd_sc_ls__sedfxbp (
+    Q  ,
+    Q_N,
+    CLK,
+    D  ,
+    DE ,
+    SCD,
+    SCE
+);
+
+    // Module ports
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+    input  SCD;
+    input  SCE;
+
+    // Local signals
+    wire buf_Q  ;
+    wire mux_out;
+    wire de_d   ;
+
+    //                            Delay       Name       Output   Other arguments
+    sky130_fd_sc_ls__udp_mux_2to1             mux_2to10 (mux_out, de_d, SCD, SCE );
+    sky130_fd_sc_ls__udp_mux_2to1             mux_2to11 (de_d   , buf_Q, D, DE   );
+    sky130_fd_sc_ls__udp_dff$P    `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK   );
+    buf                                       buf0      (Q      , buf_Q          );
+    not                                       not0      (Q_N    , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SEDFXBP_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O32AI_1_V
+`define SKY130_FD_SC_LS__O32AI_1_V
+
+/**
+ * o32ai: 3-input OR and 2-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog wrapper for o32ai with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o32ai.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o32ai_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o32ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o32ai_1 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o32ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O32AI_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A41O_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__A41O_PP_SYMBOL_V
+
+/**
+ * a41o: 4-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a41o (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  A3  ,
+    input  A4  ,
+    input  B1  ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A41O_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR4B_V
+`define SKY130_FD_SC_LS__NOR4B_V
+
+/**
+ * nor4b: 4-input NOR, first input inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__nor4b.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__nor4b.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__nor4b.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__nor4b.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR4B_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O31AI_SYMBOL_V
+`define SKY130_FD_SC_LS__O31AI_SYMBOL_V
+
+/**
+ * o31ai: 3-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3) & B1)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o31ai (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  A3,
+    input  B1,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O31AI_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O41AI_1_V
+`define SKY130_FD_SC_LS__O41AI_1_V
+
+/**
+ * o41ai: 4-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog wrapper for o41ai with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o41ai.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o41ai_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o41ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o41ai_1 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o41ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O41AI_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR2B_4_V
+`define SKY130_FD_SC_LS__NOR2B_4_V
+
+/**
+ * nor2b: 2-input NOR, first input inverted.
+ *
+ *        Y = !(A | B | C | !D)
+ *
+ * Verilog wrapper for nor2b with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nor2b.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor2b_4 (
+    Y   ,
+    A   ,
+    B_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nor2b base (
+        .Y(Y),
+        .A(A),
+        .B_N(B_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor2b_4 (
+    Y  ,
+    A  ,
+    B_N
+);
+
+    output Y  ;
+    input  A  ;
+    input  B_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nor2b base (
+        .Y(Y),
+        .A(A),
+        .B_N(B_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR2B_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFSBP_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__SDFSBP_PP_BLACKBOX_V
+
+/**
+ * sdfsbp: Scan delay flop, inverted set, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sdfsbp (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFSBP_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DIODE_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__DIODE_FUNCTIONAL_PP_V
+
+/**
+ * diode: Antenna tie-down diode.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__diode (
+    DIODE,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    input DIODE;
+    input VPWR ;
+    input VGND ;
+    input VPB  ;
+    input VNB  ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DIODE_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FILL_DIODE_4_V
+`define SKY130_FD_SC_LS__FILL_DIODE_4_V
+
+/**
+ * fill_diode: Fill diode.
+ *
+ * Verilog wrapper for fill_diode with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__fill_diode.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__fill_diode_4 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+    sky130_fd_sc_ls__fill_diode base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__fill_diode_4 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__fill_diode base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FILL_DIODE_4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SDFRTP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__SDFRTP_FUNCTIONAL_PP_V
+
+/**
+ * sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
+ *         single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v""
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+
+`celldefine
+module sky130_fd_sc_ls__sdfrtp (
+    Q      ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire buf_Q  ;
+    wire RESET  ;
+    wire mux_out;
+
+    //                                  Delay       Name       Output   Other arguments
+    not                                             not0      (RESET  , RESET_B                          );
+    sky130_fd_sc_ls__udp_mux_2to1                   mux_2to10 (mux_out, D, SCD, SCE                      );
+    sky130_fd_sc_ls__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK, RESET, , VPWR, VGND);
+    buf                                             buf0      (Q      , buf_Q                            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFRTP_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__OR4B_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__OR4B_FUNCTIONAL_V
+
+/**
+ * or4b: 4-input OR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__or4b (
+    X  ,
+    A  ,
+    B  ,
+    C  ,
+    D_N
+);
+
+    // Module ports
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C  ;
+    input  D_N;
+
+    // Local signals
+    wire not0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    not not0 (not0_out , D_N              );
+    or  or0  (or0_out_X, not0_out, C, B, A);
+    buf buf0 (X        , or0_out_X        );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR4B_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A21O_TB_V
+`define SKY130_FD_SC_LS__A21O_TB_V
+
+/**
+ * a21o: 2-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2) | B1)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a21o.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg B1;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        B1   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   B1   = 1\'b0;
+        #80   VGND = 1\'b0;
+        #100  VNB  = 1\'b0;
+        #120  VPB  = 1\'b0;
+        #140  VPWR = 1\'b0;
+        #160  A1   = 1\'b1;
+        #180  A2   = 1\'b1;
+        #200  B1   = 1\'b1;
+        #220  VGND = 1\'b1;
+        #240  VNB  = 1\'b1;
+        #260  VPB  = 1\'b1;
+        #280  VPWR = 1\'b1;
+        #300  A1   = 1\'b0;
+        #320  A2   = 1\'b0;
+        #340  B1   = 1\'b0;
+        #360  VGND = 1\'b0;
+        #380  VNB  = 1\'b0;
+        #400  VPB  = 1\'b0;
+        #420  VPWR = 1\'b0;
+        #440  VPWR = 1\'b1;
+        #460  VPB  = 1\'b1;
+        #480  VNB  = 1\'b1;
+        #500  VGND = 1\'b1;
+        #520  B1   = 1\'b1;
+        #540  A2   = 1\'b1;
+        #560  A1   = 1\'b1;
+        #580  VPWR = 1\'bx;
+        #600  VPB  = 1\'bx;
+        #620  VNB  = 1\'bx;
+        #640  VGND = 1\'bx;
+        #660  B1   = 1\'bx;
+        #680  A2   = 1\'bx;
+        #700  A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__a21o dut (.A1(A1), .A2(A2), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21O_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A21OI_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__A21OI_PP_BLACKBOX_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | B1)
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a21oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21OI_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__AND4B_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__AND4B_FUNCTIONAL_V
+
+/**
+ * and4b: 4-input AND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__and4b (
+    X  ,
+    A_N,
+    B  ,
+    C  ,
+    D
+);
+
+    // Module ports
+    output X  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+    input  D  ;
+
+    // Local signals
+    wire not0_out  ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out  , A_N              );
+    and and0 (and0_out_X, not0_out, B, C, D);
+    buf buf0 (X         , and0_out_X       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND4B_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND4B_1_V
+`define SKY130_FD_SC_LS__NAND4B_1_V
+
+/**
+ * nand4b: 4-input NAND, first input inverted.
+ *
+ * Verilog wrapper for nand4b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nand4b.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nand4b_1 (
+    Y   ,
+    A_N ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nand4b base (
+        .Y(Y),
+        .A_N(A_N),
+        .B(B),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nand4b_1 (
+    Y  ,
+    A_N,
+    B  ,
+    C  ,
+    D
+);
+
+    output Y  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nand4b base (
+        .Y(Y),
+        .A_N(A_N),
+        .B(B),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND4B_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A -=> Y) = (0:0:0,0:0:0);
+(B -=> Y) = (0:0:0,0:0:0);
+(C_N +=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLYGATE4SD1_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__DLYGATE4SD1_BEHAVIORAL_V
+
+/**
+ * dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__dlygate4sd1 (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYGATE4SD1_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DECAPHE_BLACKBOX_V
+`define SKY130_FD_SC_LS__DECAPHE_BLACKBOX_V
+
+/**
+ * decaphe: Shielded Decoupling capacitance filler.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__decaphe ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DECAPHE_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_MUX_4TO2_BLACKBOX_V
+`define SKY130_FD_SC_LS__UDP_MUX_4TO2_BLACKBOX_V
+
+/**
+ * udp_mux_4to2: Four to one multiplexer with 2 select controls
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__udp_mux_4to2 (
+    X ,
+    A0,
+    A1,
+    A2,
+    A3,
+    S0,
+    S1
+);
+
+    output X ;
+    input  A0;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  S0;
+    input  S1;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_MUX_4TO2_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O21A_2_V
+`define SKY130_FD_SC_LS__O21A_2_V
+
+/**
+ * o21a: 2-input OR into first input of 2-input AND.
+ *
+ *       X = ((A1 | A2) & B1)
+ *
+ * Verilog wrapper for o21a with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o21a.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o21a_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o21a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o21a_2 (
+    X ,
+    A1,
+    A2,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o21a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21A_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SEDFXBP_2_V
+`define SKY130_FD_SC_LS__SEDFXBP_2_V
+
+/**
+ * sedfxbp: Scan delay flop, data enable, non-inverted clock,
+ *          complementary outputs.
+ *
+ * Verilog wrapper for sedfxbp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__sedfxbp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sedfxbp_2 (
+    Q   ,
+    Q_N ,
+    CLK ,
+    D   ,
+    DE  ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    output Q_N ;
+    input  CLK ;
+    input  D   ;
+    input  DE  ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__sedfxbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .DE(DE),
+        .SCD(SCD),
+        .SCE(SCE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sedfxbp_2 (
+    Q  ,
+    Q_N,
+    CLK,
+    D  ,
+    DE ,
+    SCD,
+    SCE
+);
+
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+    input  SCD;
+    input  SCE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__sedfxbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .DE(DE),
+        .SCD(SCD),
+        .SCE(SCE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SEDFXBP_2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__OR4B_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__OR4B_BEHAVIORAL_V
+
+/**
+ * or4b: 4-input OR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__or4b (
+    X  ,
+    A  ,
+    B  ,
+    C  ,
+    D_N
+);
+
+    // Module ports
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C  ;
+    input  D_N;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    not not0 (not0_out , D_N              );
+    or  or0  (or0_out_X, not0_out, C, B, A);
+    buf buf0 (X        , or0_out_X        );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR4B_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND4BB_1_V
+`define SKY130_FD_SC_LS__AND4BB_1_V
+
+/**
+ * and4bb: 4-input AND, first two inputs inverted.
+ *
+ * Verilog wrapper for and4bb with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__and4bb.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__and4bb_1 (
+    X   ,
+    A_N ,
+    B_N ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A_N ;
+    input  B_N ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__and4bb base (
+        .X(X),
+        .A_N(A_N),
+        .B_N(B_N),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__and4bb_1 (
+    X  ,
+    A_N,
+    B_N,
+    C  ,
+    D
+);
+
+    output X  ;
+    input  A_N;
+    input  B_N;
+    input  C  ;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__and4bb base (
+        .X(X),
+        .A_N(A_N),
+        .B_N(B_N),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND4BB_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O211AI_V
+`define SKY130_FD_SC_LS__O211AI_V
+
+/**
+ * o211ai: 2-input OR into first input of 3-input NAND.
+ *
+ *         Y = !((A1 | A2) & B1 & C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o211ai.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o211ai.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o211ai.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o211ai.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O211AI_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A21BO_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__A21BO_PP_SYMBOL_V
+
+/**
+ * a21bo: 2-input AND into first input of 2-input OR,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 & A2) | (!B1_N))
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a21bo (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  B1_N,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21BO_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD3_1_V
+`define SKY130_FD_SC_LS__CLKDLYINV3SD3_1_V
+
+/**
+ * clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
+ *                stage gate.
+ *
+ * Verilog wrapper for clkdlyinv3sd3 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__clkdlyinv3sd3.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__clkdlyinv3sd3_1 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__clkdlyinv3sd3 base (
+        .Y(Y),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__clkdlyinv3sd3_1 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__clkdlyinv3sd3 base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV3SD3_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+( negedge SET_B => ( Q -: SET_B ) ) = 0:0:0 ;  // delay is tris
+( negedge SET_B => ( Q_N +: SET_B ) ) = 0:0:0 ;  // delay is tris
+( posedge CLK => ( Q : CLK ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall
+( posedge CLK => ( Q_N : CLK ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall
+$recrem ( posedge SET_B , posedge CLK , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , SETB_delayed , CLK_delayed ) ;
+$setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ;
+$setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ;
+$setuphold ( posedge CLK , posedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ;
+$setuphold ( posedge CLK , negedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ;
+$setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ;
+$setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ;
+$width ( posedge CLK &&& COND4 , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( negedge CLK &&& COND4 , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( negedge SET_B &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A2BB2O_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__A2BB2O_PP_SYMBOL_V
+
+/**
+ * a2bb2o: 2-input AND, both inputs inverted, into first input, and
+ *         2-input AND into 2nd input of 2-input OR.
+ *
+ *         X = ((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a2bb2o (
+    //# {{data|Data Signals}}
+    input  A1_N,
+    input  A2_N,
+    input  B1  ,
+    input  B2  ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2BB2O_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFXTP_1_V
+`define SKY130_FD_SC_LS__DFXTP_1_V
+
+/**
+ * dfxtp: Delay flop, single output.
+ *
+ * Verilog wrapper for dfxtp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dfxtp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dfxtp_1 (
+    Q   ,
+    CLK ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__dfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dfxtp_1 (
+    Q  ,
+    CLK,
+    D
+);
+
+    output Q  ;
+    input  CLK;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__dfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFXTP_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLXBN_V
+`define SKY130_FD_SC_LS__DLXBN_V
+
+/**
+ * dlxbn: Delay latch, inverted enable, complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlxbn.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlxbn.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlxbn.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlxbn.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXBN_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLCLKP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__DLCLKP_BEHAVIORAL_PP_V
+
+/**
+ * dlclkp: Clock gate.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlclkp (
+    GCLK,
+    GATE,
+    CLK ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output GCLK;
+    input  GATE;
+    input  CLK ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire m0          ;
+    wire clkn        ;
+    wire CLK_delayed ;
+    wire GATE_delayed;
+    reg  notifier    ;
+    wire awake       ;
+
+    //                                    Name     Output  Other arguments
+    not                                   not0    (clkn  , CLK_delayed                             );
+    sky130_fd_sc_ls__udp_dlatch$P_pp$PG$N dlatch0 (m0    , GATE_delayed, clkn, notifier, VPWR, VGND);
+    and                                   and0    (GCLK  , m0, CLK_delayed                         );
+    assign awake = ( VPWR === 1\'b1 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLCLKP_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FA_1_V
+`define SKY130_FD_SC_LS__FA_1_V
+
+/**
+ * fa: Full adder.
+ *
+ * Verilog wrapper for fa with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__fa.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__fa_1 (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CIN ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CIN ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__fa base (
+        .COUT(COUT),
+        .SUM(SUM),
+        .A(A),
+        .B(B),
+        .CIN(CIN),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__fa_1 (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CIN
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CIN ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__fa base (
+        .COUT(COUT),
+        .SUM(SUM),
+        .A(A),
+        .B(B),
+        .CIN(CIN)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FA_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A +=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__AND2B_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__AND2B_FUNCTIONAL_V
+
+/**
+ * and2b: 2-input AND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__and2b (
+    X  ,
+    A_N,
+    B
+);
+
+    // Module ports
+    output X  ;
+    input  A_N;
+    input  B  ;
+
+    // Local signals
+    wire not0_out  ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out  , A_N            );
+    and and0 (and0_out_X, not0_out, B    );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND2B_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND4B_1_V
+`define SKY130_FD_SC_LS__AND4B_1_V
+
+/**
+ * and4b: 4-input AND, first input inverted.
+ *
+ * Verilog wrapper for and4b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__and4b.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__and4b_1 (
+    X   ,
+    A_N ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__and4b base (
+        .X(X),
+        .A_N(A_N),
+        .B(B),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__and4b_1 (
+    X  ,
+    A_N,
+    B  ,
+    C  ,
+    D
+);
+
+    output X  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__and4b base (
+        .X(X),
+        .A_N(A_N),
+        .B(B),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND4B_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O311AI_1_V
+`define SKY130_FD_SC_LS__O311AI_1_V
+
+/**
+ * o311ai: 3-input OR into 3-input NAND.
+ *
+ *         Y = !((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog wrapper for o311ai with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o311ai.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o311ai_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o311ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o311ai_1 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o311ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O311AI_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DFBBN_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__DFBBN_FUNCTIONAL_V
+
+/**
+ * dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_nsr/sky130_fd_sc_ls__udp_dff_nsr.v""
+
+`celldefine
+module sky130_fd_sc_ls__dfbbn (
+    Q      ,
+    Q_N    ,
+    D      ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+
+    // Local signals
+    wire RESET;
+    wire SET  ;
+    wire CLK  ;
+    wire buf_Q;
+
+    //                           Delay       Name  Output  Other arguments
+    not                                      not0 (RESET , RESET_B           );
+    not                                      not1 (SET   , SET_B             );
+    not                                      not2 (CLK   , CLK_N             );
+    sky130_fd_sc_ls__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D);
+    buf                                      buf0 (Q     , buf_Q             );
+    not                                      not3 (Q_N   , buf_Q             );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFBBN_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__XNOR2_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__XNOR2_BEHAVIORAL_PP_V
+
+/**
+ * xnor2: 2-input exclusive NOR.
+ *
+ *        Y = !(A ^ B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__xnor2 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire xnor0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    xnor                               xnor0       (xnor0_out_Y      , A, B                   );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, xnor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XNOR2_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DIODE_2_V
+`define SKY130_FD_SC_LS__DIODE_2_V
+
+/**
+ * diode: Antenna tie-down diode.
+ *
+ * Verilog wrapper for diode with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__diode.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__diode_2 (
+    DIODE,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    input DIODE;
+    input VPWR ;
+    input VGND ;
+    input VPB  ;
+    input VNB  ;
+    sky130_fd_sc_ls__diode base (
+        .DIODE(DIODE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__diode_2 (
+    DIODE
+);
+
+    input DIODE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__diode base (
+        .DIODE(DIODE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DIODE_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A41OI_V
+`define SKY130_FD_SC_LS__A41OI_V
+
+/**
+ * a41oi: 4-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a41oi.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a41oi.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a41oi.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a41oi.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A41OI_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__TAPVGND2_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__TAPVGND2_PP_SYMBOL_V
+
+/**
+ * tapvgnd2: Tap cell with tap to ground, isolated power connection
+ *           2 rows down.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__tapvgnd2 (
+    //# {{power|Power}}
+    input VPB ,
+    input VPWR,
+    input VGND,
+    input VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPVGND2_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLRBP_TB_V
+`define SKY130_FD_SC_LS__DLRBP_TB_V
+
+/**
+ * dlrbp: Delay latch, inverted reset, non-inverted enable,
+ *        complementary outputs.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dlrbp.v""
+
+module top();
+
+    // Inputs are registered
+    reg RESET_B;
+    reg D;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Q;
+    wire Q_N;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D       = 1\'bX;
+        RESET_B = 1\'bX;
+        VGND    = 1\'bX;
+        VNB     = 1\'bX;
+        VPB     = 1\'bX;
+        VPWR    = 1\'bX;
+
+        #20   D       = 1\'b0;
+        #40   RESET_B = 1\'b0;
+        #60   VGND    = 1\'b0;
+        #80   VNB     = 1\'b0;
+        #100  VPB     = 1\'b0;
+        #120  VPWR    = 1\'b0;
+        #140  D       = 1\'b1;
+        #160  RESET_B = 1\'b1;
+        #180  VGND    = 1\'b1;
+        #200  VNB     = 1\'b1;
+        #220  VPB     = 1\'b1;
+        #240  VPWR    = 1\'b1;
+        #260  D       = 1\'b0;
+        #280  RESET_B = 1\'b0;
+        #300  VGND    = 1\'b0;
+        #320  VNB     = 1\'b0;
+        #340  VPB     = 1\'b0;
+        #360  VPWR    = 1\'b0;
+        #380  VPWR    = 1\'b1;
+        #400  VPB     = 1\'b1;
+        #420  VNB     = 1\'b1;
+        #440  VGND    = 1\'b1;
+        #460  RESET_B = 1\'b1;
+        #480  D       = 1\'b1;
+        #500  VPWR    = 1\'bx;
+        #520  VPB     = 1\'bx;
+        #540  VNB     = 1\'bx;
+        #560  VGND    = 1\'bx;
+        #580  RESET_B = 1\'bx;
+        #600  D       = 1\'bx;
+    end
+
+    // Create a clock
+    reg GATE;
+    initial
+    begin
+        GATE = 1\'b0;
+    end
+
+    always
+    begin
+        #5 GATE = ~GATE;
+    end
+
+    sky130_fd_sc_ls__dlrbp dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .GATE(GATE));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRBP_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O2BB2AI_TB_V
+`define SKY130_FD_SC_LS__O2BB2AI_TB_V
+
+/**
+ * o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
+ *
+ *          Y = !(!(A1 & A2) & (B1 | B2))
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o2bb2ai.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1_N;
+    reg A2_N;
+    reg B1;
+    reg B2;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1_N = 1\'bX;
+        A2_N = 1\'bX;
+        B1   = 1\'bX;
+        B2   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1_N = 1\'b0;
+        #40   A2_N = 1\'b0;
+        #60   B1   = 1\'b0;
+        #80   B2   = 1\'b0;
+        #100  VGND = 1\'b0;
+        #120  VNB  = 1\'b0;
+        #140  VPB  = 1\'b0;
+        #160  VPWR = 1\'b0;
+        #180  A1_N = 1\'b1;
+        #200  A2_N = 1\'b1;
+        #220  B1   = 1\'b1;
+        #240  B2   = 1\'b1;
+        #260  VGND = 1\'b1;
+        #280  VNB  = 1\'b1;
+        #300  VPB  = 1\'b1;
+        #320  VPWR = 1\'b1;
+        #340  A1_N = 1\'b0;
+        #360  A2_N = 1\'b0;
+        #380  B1   = 1\'b0;
+        #400  B2   = 1\'b0;
+        #420  VGND = 1\'b0;
+        #440  VNB  = 1\'b0;
+        #460  VPB  = 1\'b0;
+        #480  VPWR = 1\'b0;
+        #500  VPWR = 1\'b1;
+        #520  VPB  = 1\'b1;
+        #540  VNB  = 1\'b1;
+        #560  VGND = 1\'b1;
+        #580  B2   = 1\'b1;
+        #600  B1   = 1\'b1;
+        #620  A2_N = 1\'b1;
+        #640  A1_N = 1\'b1;
+        #660  VPWR = 1\'bx;
+        #680  VPB  = 1\'bx;
+        #700  VNB  = 1\'bx;
+        #720  VGND = 1\'bx;
+        #740  B2   = 1\'bx;
+        #760  B1   = 1\'bx;
+        #780  A2_N = 1\'bx;
+        #800  A1_N = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__o2bb2ai dut (.A1_N(A1_N), .A2_N(A2_N), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2BB2AI_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O21BAI_V
+`define SKY130_FD_SC_LS__O21BAI_V
+
+/**
+ * o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
+ *         inverted.
+ *
+ *         Y = !((A1 | A2) & !B1_N)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o21bai.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o21bai.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o21bai.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o21bai.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21BAI_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND2B_V
+`define SKY130_FD_SC_LS__NAND2B_V
+
+/**
+ * nand2b: 2-input NAND, first input inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__nand2b.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__nand2b.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__nand2b.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__nand2b.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND2B_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A311OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__A311OI_FUNCTIONAL_PP_V
+
+/**
+ * a311oi: 3-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a311oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A3, A1, A2            );
+    nor                                nor0        (nor0_out_Y       , and0_out, B1, C1      );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A311OI_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFRTN_BLACKBOX_V
+`define SKY130_FD_SC_LS__SDFRTN_BLACKBOX_V
+
+/**
+ * sdfrtn: Scan delay flop, inverted reset, inverted clock,
+ *         single output.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sdfrtn (
+    Q      ,
+    CLK_N  ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B
+);
+
+    output Q      ;
+    input  CLK_N  ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFRTN_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR3B_BLACKBOX_V
+`define SKY130_FD_SC_LS__OR3B_BLACKBOX_V
+
+/**
+ * or3b: 3-input OR, first input inverted.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__or3b (
+    X  ,
+    A  ,
+    B  ,
+    C_N
+);
+
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR3B_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A31OI_4_V
+`define SKY130_FD_SC_LS__A31OI_4_V
+
+/**
+ * a31oi: 3-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | B1)
+ *
+ * Verilog wrapper for a31oi with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a31oi.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a31oi_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a31oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a31oi_4 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a31oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A31OI_4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD2_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__CLKDLYINV3SD2_BEHAVIORAL_V
+
+/**
+ * clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
+ *                stage gate.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__clkdlyinv3sd2 (
+    Y,
+    A
+);
+
+    // Module ports
+    output Y;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out_Y, A              );
+    buf buf0 (Y         , not0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV3SD2_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A -=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A21OI_2_V
+`define SKY130_FD_SC_LS__A21OI_2_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | B1)
+ *
+ * Verilog wrapper for a21oi with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a21oi.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a21oi_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a21oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a21oi_2 (
+    Y ,
+    A1,
+    A2,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a21oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21OI_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__HA_V
+`define SKY130_FD_SC_LS__HA_V
+
+/**
+ * ha: Half adder.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__ha.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__ha.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__ha.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__ha.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__HA_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKBUF_16_V
+`define SKY130_FD_SC_LS__CLKBUF_16_V
+
+/**
+ * clkbuf: Clock tree buffer.
+ *
+ * Verilog wrapper for clkbuf with size of 16 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__clkbuf.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__clkbuf_16 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__clkbuf base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__clkbuf_16 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__clkbuf base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKBUF_16_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR3B_2_V
+`define SKY130_FD_SC_LS__OR3B_2_V
+
+/**
+ * or3b: 3-input OR, first input inverted.
+ *
+ * Verilog wrapper for or3b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__or3b.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__or3b_2 (
+    X   ,
+    A   ,
+    B   ,
+    C_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__or3b base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C_N(C_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__or3b_2 (
+    X  ,
+    A  ,
+    B  ,
+    C_N
+);
+
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__or3b base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C_N(C_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR3B_2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O22A_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__O22A_BEHAVIORAL_PP_V
+
+/**
+ * o22a: 2-input OR into both inputs of 2-input AND.
+ *
+ *       X = ((A1 | A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__o22a (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire or1_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1                );
+    or                                 or1         (or1_out          , B2, B1                );
+    and                                and0        (and0_out_X       , or0_out, or1_out      );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O22A_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O311AI_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__O311AI_FUNCTIONAL_V
+
+/**
+ * o311ai: 3-input OR into 3-input NAND.
+ *
+ *         Y = !((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__o311ai (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Local signals
+    wire or0_out    ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    or   or0   (or0_out    , A2, A1, A3     );
+    nand nand0 (nand0_out_Y, C1, or0_out, B1);
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O311AI_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A31OI_SYMBOL_V
+`define SKY130_FD_SC_LS__A31OI_SYMBOL_V
+
+/**
+ * a31oi: 3-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | B1)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a31oi (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  A3,
+    input  B1,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A31OI_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+( negedge RESET_B => ( Q +: RESET_B ) ) = 0:0:0 ;  // delay is tris
+( negedge CLK_N => ( Q : CLK_N ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall
+$recrem ( posedge RESET_B , negedge CLK_N , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , RESETB_delayed , CLKN_delayed ) ;
+$setuphold ( negedge CLK_N , posedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , CLKN_delayed , D_delayed ) ;
+$setuphold ( negedge CLK_N , negedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , CLKN_delayed , D_delayed ) ;
+$width ( posedge CLK_N &&& COND1 , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( negedge CLK_N &&& COND1 , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( negedge RESET_B &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR2_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__OR2_PP_BLACKBOX_V
+
+/**
+ * or2: 2-input OR.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__or2 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR2_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLXBN_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__DLXBN_BEHAVIORAL_PP_V
+
+/**
+ * dlxbn: Delay latch, inverted enable, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlxbn (
+    Q     ,
+    Q_N   ,
+    D     ,
+    GATE_N,
+    VPWR  ,
+    VGND  ,
+    VPB   ,
+    VNB
+);
+
+    // Module ports
+    output Q     ;
+    output Q_N   ;
+    input  D     ;
+    input  GATE_N;
+    input  VPWR  ;
+    input  VGND  ;
+    input  VPB   ;
+    input  VNB   ;
+
+    // Local signals
+    wire GATE          ;
+    wire buf_Q         ;
+    wire GATE_N_delayed;
+    wire D_delayed     ;
+    reg  notifier      ;
+    wire awake         ;
+    wire 1             ;
+
+    //                                    Name     Output  Other arguments
+    not                                   not0    (GATE  , GATE_N_delayed                       );
+    sky130_fd_sc_ls__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1 );
+    buf                                   buf0    (Q     , buf_Q                                );
+    not                                   not1    (Q_N   , buf_Q                                );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXBN_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND4BB_SYMBOL_V
+`define SKY130_FD_SC_LS__NAND4BB_SYMBOL_V
+
+/**
+ * nand4bb: 4-input NAND, first two inputs inverted.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nand4bb (
+    //# {{data|Data Signals}}
+    input  A_N,
+    input  B_N,
+    input  C  ,
+    input  D  ,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND4BB_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SDFBBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__SDFBBP_BEHAVIORAL_PP_V
+
+/**
+ * sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
+ *         clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+`include ""../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ls__udp_dff_nsr_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__sdfbbp (
+    Q      ,
+    Q_N    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    CLK    ,
+    SET_B  ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  CLK    ;
+    input  SET_B  ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire RESET          ;
+    wire SET            ;
+    wire buf_Q          ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire SCD_delayed    ;
+    wire SCE_delayed    ;
+    wire CLK_delayed    ;
+    wire SET_B_delayed  ;
+    wire RESET_B_delayed;
+    wire mux_out        ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+    wire condb          ;
+    wire cond_D         ;
+    wire cond_SCD       ;
+    wire cond_SCE       ;
+
+    //                                   Name       Output   Other arguments
+    not                                  not0      (RESET  , RESET_B_delayed                                       );
+    not                                  not1      (SET    , SET_B_delayed                                         );
+    sky130_fd_sc_ls__udp_mux_2to1        mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed                   );
+    sky130_fd_sc_ls__udp_dff$NSR_pp$PG$N dff0      (buf_Q  , SET, RESET, CLK_delayed, mux_out, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1\'b1 ) );
+    assign cond1 = ( awake && ( SET_B_delayed === 1\'b1 ) );
+    assign condb = ( cond0 & cond1 );
+    assign cond_D = ( ( SCE_delayed === 1\'b0 ) && condb );
+    assign cond_SCD = ( ( SCE_delayed === 1\'b1 ) && condb );
+    assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
+    buf                                  buf0      (Q      , buf_Q                                                 );
+    not                                  not2      (Q_N    , buf_Q                                                 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFBBP_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+( negedge RESET_B => ( Q +: RESET_B ) ) = 0:0:0 ;   // delay is tfall
+( negedge RESET_B => ( Q_N -: RESET_B ) ) = 0:0:0 ;  // delay is tris
+( SET_B => ( Q -: SET_B ) ) = ( 0:0:0 , 0:0:0 ) ;       // delay is tris , tfall
+( SET_B => ( Q_N +: SET_B ) ) = ( 0:0:0 , 0:0:0 ) ;      // delay is tris , tfall
+( posedge CLK => ( Q +: D ) ) = ( 0:0:0 , 0:0:0 ) ;  // delays are tris , tfall
+( posedge CLK => ( Q_N -: D ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall
+$recrem ( posedge SET_B , posedge CLK , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , SETB_delayed , CLK_delayed ) ;
+$recrem ( posedge RESET_B , posedge CLK , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , RESETB_delayed , CLK_delayed ) ;
+$setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , CONDB , CONDB , CLK_delayed , D_delayed ) ;
+$setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , CONDB , CONDB , CLK_delayed , D_delayed ) ;
+$hold ( posedge SET_B &&& AWAKE , posedge RESET_B &&& AWAKE , 3.0:3.0:3.0 , notifier ) ; //arbitrary , uncharacterized value to
+//flag possible state error
+$hold ( posedge RESET_B &&& AWAKE , posedge SET_B &&& AWAKE , 3.0:3.0:3.0 , notifier ) ; //arbitrary , uncharacterized value to
+//flag possible state error
+$width ( negedge CLK &&& CONDB , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( posedge CLK &&& CONDB , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( negedge SET_B &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( negedge RESET_B &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+( negedge RESET_B => ( Q +: RESET_B ) ) = ( 0:0:0 , 0:0:0 ) ;  // delay is tfall
+( D +=> Q ) = ( 0:0:0 , 0:0:0 ) ;  // delays are tris , tfall
+( posedge GATE => ( Q : GATE ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall
+( negedge RESET_B => ( Q_N -: RESET_B ) ) = ( 0:0:0 , 0:0:0 ) ;  // delay is tfall
+( D -=> Q_N ) = ( 0:0:0 , 0:0:0 ) ;  // delays are tris , tfall
+( posedge GATE => ( Q_N : GATE ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall
+$recrem ( posedge RESET_B , negedge GATE , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , RESETB_delayed , GATE_delayed ) ;
+$setuphold ( negedge GATE , posedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , GATE_delayed , D_delayed ) ;
+$setuphold ( negedge GATE , negedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , GATE_delayed , D_delayed ) ;
+$width ( posedge GATE &&& COND1 , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( negedge RESET_B &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( posedge RESET_B &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR3B_SYMBOL_V
+`define SKY130_FD_SC_LS__NOR3B_SYMBOL_V
+
+/**
+ * nor3b: 3-input NOR, first input inverted.
+ *
+ *        Y = (!(A | B)) & !C)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nor3b (
+    //# {{data|Data Signals}}
+    input  A  ,
+    input  B  ,
+    input  C_N,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR3B_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A2BB2OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__A2BB2OI_BEHAVIORAL_PP_V
+
+/**
+ * a2bb2oi: 2-input AND, both inputs inverted, into first input, and
+ *          2-input AND into 2nd input of 2-input NOR.
+ *
+ *          Y = !((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a2bb2oi (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire nor0_out         ;
+    wire nor1_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , B1, B2                );
+    nor                                nor0        (nor0_out         , A1_N, A2_N            );
+    nor                                nor1        (nor1_out_Y       , nor0_out, and0_out    );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor1_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2BB2OI_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SEDFXTP_4_V
+`define SKY130_FD_SC_LS__SEDFXTP_4_V
+
+/**
+ * sedfxtp: Scan delay flop, data enable, non-inverted clock,
+ *          single output.
+ *
+ * Verilog wrapper for sedfxtp with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__sedfxtp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sedfxtp_4 (
+    Q   ,
+    CLK ,
+    D   ,
+    DE  ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  DE  ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__sedfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .DE(DE),
+        .SCD(SCD),
+        .SCE(SCE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sedfxtp_4 (
+    Q  ,
+    CLK,
+    D  ,
+    DE ,
+    SCD,
+    SCE
+);
+
+    output Q  ;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+    input  SCD;
+    input  SCE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__sedfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .DE(DE),
+        .SCD(SCD),
+        .SCE(SCE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SEDFXTP_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O21BAI_4_V
+`define SKY130_FD_SC_LS__O21BAI_4_V
+
+/**
+ * o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
+ *         inverted.
+ *
+ *         Y = !((A1 | A2) & !B1_N)
+ *
+ * Verilog wrapper for o21bai with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o21bai.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o21bai_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o21bai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o21bai_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o21bai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21BAI_4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O2BB2AI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__O2BB2AI_FUNCTIONAL_PP_V
+
+/**
+ * o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
+ *
+ *          Y = !(!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__o2bb2ai (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out        ;
+    wire or0_out          ;
+    wire nand1_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out        , A2_N, A1_N             );
+    or                                 or0         (or0_out          , B2, B1                 );
+    nand                               nand1       (nand1_out_Y      , nand0_out, or0_out     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand1_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2BB2AI_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O221AI_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__O221AI_FUNCTIONAL_V
+
+/**
+ * o221ai: 2-input OR into first two inputs of 3-input NAND.
+ *
+ *         Y = !((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__o221ai (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Local signals
+    wire or0_out    ;
+    wire or1_out    ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    or   or0   (or0_out    , B2, B1              );
+    or   or1   (or1_out    , A2, A1              );
+    nand nand0 (nand0_out_Y, or1_out, or0_out, C1);
+    buf  buf0  (Y          , nand0_out_Y         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O221AI_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD3_BLACKBOX_V
+`define SKY130_FD_SC_LS__CLKDLYINV3SD3_BLACKBOX_V
+
+/**
+ * clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
+ *                stage gate.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__clkdlyinv3sd3 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV3SD3_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A2BB2OI_4_V
+`define SKY130_FD_SC_LS__A2BB2OI_4_V
+
+/**
+ * a2bb2oi: 2-input AND, both inputs inverted, into first input, and
+ *          2-input AND into 2nd input of 2-input NOR.
+ *
+ *          Y = !((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a2bb2oi with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a2bb2oi.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a2bb2oi_4 (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a2bb2oi base (
+        .Y(Y),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a2bb2oi_4 (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a2bb2oi base (
+        .Y(Y),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2BB2OI_4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O22A_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__O22A_FUNCTIONAL_V
+
+/**
+ * o22a: 2-input OR into both inputs of 2-input AND.
+ *
+ *       X = ((A1 | A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__o22a (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Local signals
+    wire or0_out   ;
+    wire or1_out   ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    or  or0  (or0_out   , A2, A1          );
+    or  or1  (or1_out   , B2, B1          );
+    and and0 (and0_out_X, or0_out, or1_out);
+    buf buf0 (X         , and0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O22A_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND3_SYMBOL_V
+`define SKY130_FD_SC_LS__AND3_SYMBOL_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__and3 (
+    //# {{data|Data Signals}}
+    input  A,
+    input  B,
+    input  C,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND3_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O41AI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__O41AI_BEHAVIORAL_PP_V
+
+/**
+ * o41ai: 4-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__o41ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A4, A3, A2, A1         );
+    nand                               nand0       (nand0_out_Y      , B1, or0_out            );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O41AI_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if ((A2&A3&!B1&!B2)) (A1 -=> Y) = (0:0:0,0:0:0);
+if ((A2&A3&!B1&B2)) (A1 -=> Y) = (0:0:0,0:0:0);
+if ((A2&A3&B1&!B2)) (A1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A3&!B1&!B2)) (A2 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A3&!B1&B2)) (A2 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A3&B1&!B2)) (A2 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2&!B1&!B2)) (A3 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2&!B1&B2)) (A3 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2&B1&!B2)) (A3 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&!A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&!A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&!A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2&!A3&B2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&!A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&!A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&!A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2&!A3&B1)) (B2 -=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__XNOR3_4_V
+`define SKY130_FD_SC_LS__XNOR3_4_V
+
+/**
+ * xnor3: 3-input exclusive NOR.
+ *
+ * Verilog wrapper for xnor3 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__xnor3.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__xnor3_4 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__xnor3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__xnor3_4 (
+    X,
+    A,
+    B,
+    C
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__xnor3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XNOR3_4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A221OI_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__A221OI_BEHAVIORAL_V
+
+/**
+ * a221oi: 2-input AND into first two inputs of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a221oi (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out  ;
+    wire and1_out  ;
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out  , B1, B2                );
+    and and1 (and1_out  , A1, A2                );
+    nor nor0 (nor0_out_Y, and0_out, C1, and1_out);
+    buf buf0 (Y         , nor0_out_Y            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A221OI_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SDFBBN_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__SDFBBN_FUNCTIONAL_V
+
+/**
+ * sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
+ *         clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_nsr/sky130_fd_sc_ls__udp_dff_nsr.v""
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+
+`celldefine
+module sky130_fd_sc_ls__sdfbbn (
+    Q      ,
+    Q_N    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+
+    // Local signals
+    wire RESET  ;
+    wire SET    ;
+    wire CLK    ;
+    wire buf_Q  ;
+    wire mux_out;
+
+    //                            Delay       Name       Output   Other arguments
+    not                                       not0      (RESET  , RESET_B                 );
+    not                                       not1      (SET    , SET_B                   );
+    not                                       not2      (CLK    , CLK_N                   );
+    sky130_fd_sc_ls__udp_mux_2to1             mux_2to10 (mux_out, D, SCD, SCE             );
+    sky130_fd_sc_ls__udp_dff$NSR  `UNIT_DELAY dff0      (buf_Q  , SET, RESET, CLK, mux_out);
+    buf                                       buf0      (Q      , buf_Q                   );
+    not                                       not3      (Q_N    , buf_Q                   );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFBBN_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A211O_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__A211O_PP_SYMBOL_V
+
+/**
+ * a211o: 2-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2) | B1 | C1)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a211o (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  B1  ,
+    input  C1  ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A211O_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FAHCIN_TB_V
+`define SKY130_FD_SC_LS__FAHCIN_TB_V
+
+/**
+ * fahcin: Full adder, inverted carry in.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__fahcin.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg B;
+    reg CIN;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire COUT;
+    wire SUM;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        B    = 1\'bX;
+        CIN  = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   B    = 1\'b0;
+        #60   CIN  = 1\'b0;
+        #80   VGND = 1\'b0;
+        #100  VNB  = 1\'b0;
+        #120  VPB  = 1\'b0;
+        #140  VPWR = 1\'b0;
+        #160  A    = 1\'b1;
+        #180  B    = 1\'b1;
+        #200  CIN  = 1\'b1;
+        #220  VGND = 1\'b1;
+        #240  VNB  = 1\'b1;
+        #260  VPB  = 1\'b1;
+        #280  VPWR = 1\'b1;
+        #300  A    = 1\'b0;
+        #320  B    = 1\'b0;
+        #340  CIN  = 1\'b0;
+        #360  VGND = 1\'b0;
+        #380  VNB  = 1\'b0;
+        #400  VPB  = 1\'b0;
+        #420  VPWR = 1\'b0;
+        #440  VPWR = 1\'b1;
+        #460  VPB  = 1\'b1;
+        #480  VNB  = 1\'b1;
+        #500  VGND = 1\'b1;
+        #520  CIN  = 1\'b1;
+        #540  B    = 1\'b1;
+        #560  A    = 1\'b1;
+        #580  VPWR = 1\'bx;
+        #600  VPB  = 1\'bx;
+        #620  VNB  = 1\'bx;
+        #640  VGND = 1\'bx;
+        #660  CIN  = 1\'bx;
+        #680  B    = 1\'bx;
+        #700  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__fahcin dut (.A(A), .B(B), .CIN(CIN), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .COUT(COUT), .SUM(SUM));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FAHCIN_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR2B_TB_V
+`define SKY130_FD_SC_LS__OR2B_TB_V
+
+/**
+ * or2b: 2-input OR, first input inverted.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__or2b.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg B_N;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        B_N  = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   B_N  = 1\'b0;
+        #60   VGND = 1\'b0;
+        #80   VNB  = 1\'b0;
+        #100  VPB  = 1\'b0;
+        #120  VPWR = 1\'b0;
+        #140  A    = 1\'b1;
+        #160  B_N  = 1\'b1;
+        #180  VGND = 1\'b1;
+        #200  VNB  = 1\'b1;
+        #220  VPB  = 1\'b1;
+        #240  VPWR = 1\'b1;
+        #260  A    = 1\'b0;
+        #280  B_N  = 1\'b0;
+        #300  VGND = 1\'b0;
+        #320  VNB  = 1\'b0;
+        #340  VPB  = 1\'b0;
+        #360  VPWR = 1\'b0;
+        #380  VPWR = 1\'b1;
+        #400  VPB  = 1\'b1;
+        #420  VNB  = 1\'b1;
+        #440  VGND = 1\'b1;
+        #460  B_N  = 1\'b1;
+        #480  A    = 1\'b1;
+        #500  VPWR = 1\'bx;
+        #520  VPB  = 1\'bx;
+        #540  VNB  = 1\'bx;
+        #560  VGND = 1\'bx;
+        #580  B_N  = 1\'bx;
+        #600  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__or2b dut (.A(A), .B_N(B_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR2B_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLYMETAL6S6S_V
+`define SKY130_FD_SC_LS__DLYMETAL6S6S_V
+
+/**
+ * dlymetal6s6s: 6-inverter delay with output from 6th inverter on
+ *               horizontal route.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlymetal6s6s.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlymetal6s6s.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlymetal6s6s.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlymetal6s6s.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYMETAL6S6S_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDLCLKP_BLACKBOX_V
+`define SKY130_FD_SC_LS__SDLCLKP_BLACKBOX_V
+
+/**
+ * sdlclkp: Scan gated clock.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sdlclkp (
+    GCLK,
+    SCE ,
+    GATE,
+    CLK
+);
+
+    output GCLK;
+    input  SCE ;
+    input  GATE;
+    input  CLK ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDLCLKP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__TAPMET1_BLACKBOX_V
+`define SKY130_FD_SC_LS__TAPMET1_BLACKBOX_V
+
+/**
+ * tapmet1: Tap cell with isolated power and ground connections.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__tapmet1 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPMET1_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A +=> X) = (0:0:0,0:0:0);
+(B +=> X) = (0:0:0,0:0:0);
+(C +=> X) = (0:0:0,0:0:0);
+(D_N -=> X) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O31A_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__O31A_PP_SYMBOL_V
+
+/**
+ * o31a: 3-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & B1)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o31a (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  A3  ,
+    input  B1  ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O31A_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFRTN_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__SDFRTN_PP_SYMBOL_V
+
+/**
+ * sdfrtn: Scan delay flop, inverted reset, inverted clock,
+ *         single output.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sdfrtn (
+    //# {{data|Data Signals}}
+    input  D      ,
+    output Q      ,
+
+    //# {{control|Control Signals}}
+    input  RESET_B,
+
+    //# {{scanchain|Scan Chain}}
+    input  SCD    ,
+    input  SCE    ,
+
+    //# {{clocks|Clocking}}
+    input  CLK_N  ,
+
+    //# {{power|Power}}
+    input  VPB    ,
+    input  VPWR   ,
+    input  VGND   ,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFRTN_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O31A_4_V
+`define SKY130_FD_SC_LS__O31A_4_V
+
+/**
+ * o31a: 3-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & B1)
+ *
+ * Verilog wrapper for o31a with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o31a.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o31a_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o31a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o31a_4 (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o31a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O31A_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O2111AI_2_V
+`define SKY130_FD_SC_LS__O2111AI_2_V
+
+/**
+ * o2111ai: 2-input OR into first input of 4-input NAND.
+ *
+ *          Y = !((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog wrapper for o2111ai with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o2111ai.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o2111ai_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o2111ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o2111ai_2 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o2111ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2111AI_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O311AI_2_V
+`define SKY130_FD_SC_LS__O311AI_2_V
+
+/**
+ * o311ai: 3-input OR into 3-input NAND.
+ *
+ *         Y = !((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog wrapper for o311ai with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o311ai.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o311ai_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o311ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o311ai_2 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o311ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O311AI_2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD3_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__CLKDLYINV3SD3_BEHAVIORAL_PP_V
+
+/**
+ * clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
+ *                stage gate.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__clkdlyinv3sd3 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out_Y       , A                     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV3SD3_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_MUX_2TO1_TB_V
+`define SKY130_FD_SC_LS__UDP_MUX_2TO1_TB_V
+
+/**
+ * udp_mux_2to1: Two to one multiplexer
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__udp_mux_2to1.v""
+
+module top();
+
+    // Inputs are registered
+    reg A0;
+    reg A1;
+    reg S;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A0 = 1\'bX;
+        A1 = 1\'bX;
+        S  = 1\'bX;
+
+        #20   A0 = 1\'b0;
+        #40   A1 = 1\'b0;
+        #60   S  = 1\'b0;
+        #80   A0 = 1\'b1;
+        #100  A1 = 1\'b1;
+        #120  S  = 1\'b1;
+        #140  A0 = 1\'b0;
+        #160  A1 = 1\'b0;
+        #180  S  = 1\'b0;
+        #200  S  = 1\'b1;
+        #220  A1 = 1\'b1;
+        #240  A0 = 1\'b1;
+        #260  S  = 1\'bx;
+        #280  A1 = 1\'bx;
+        #300  A0 = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__udp_mux_2to1 dut (.A0(A0), .A1(A1), .S(S), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_MUX_2TO1_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A221O_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__A221O_PP_SYMBOL_V
+
+/**
+ * a221o: 2-input AND into first two inputs of 3-input OR.
+ *
+ *        X = ((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a221o (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  B1  ,
+    input  B2  ,
+    input  C1  ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A221O_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__BUFINV_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__BUFINV_FUNCTIONAL_PP_V
+
+/**
+ * bufinv: Buffer followed by inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__bufinv (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out_Y       , A                     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__BUFINV_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__MAJ3_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__MAJ3_BEHAVIORAL_PP_V
+
+/**
+ * maj3: 3-input majority vote.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__maj3 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire and0_out         ;
+    wire and1_out         ;
+    wire or1_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , B, A                 );
+    and                                and0        (and0_out         , or0_out, C           );
+    and                                and1        (and1_out         , A, B                 );
+    or                                 or1         (or1_out_X        , and1_out, and0_out   );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or1_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MAJ3_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND2_BLACKBOX_V
+`define SKY130_FD_SC_LS__NAND2_BLACKBOX_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nand2 (
+    Y,
+    A,
+    B
+);
+
+    output Y;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND2_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DECAPHE_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__DECAPHE_FUNCTIONAL_V
+
+/**
+ * decaphe: Shielded Decoupling capacitance filler.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__decaphe ();
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DECAPHE_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O31AI_BLACKBOX_V
+`define SKY130_FD_SC_LS__O31AI_BLACKBOX_V
+
+/**
+ * o31ai: 3-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3) & B1)
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o31ai (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O31AI_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CONB_1_V
+`define SKY130_FD_SC_LS__CONB_1_V
+
+/**
+ * conb: Constant value, low, high outputs.
+ *
+ * Verilog wrapper for conb with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__conb.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__conb_1 (
+    HI  ,
+    LO  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output HI  ;
+    output LO  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__conb base (
+        .HI(HI),
+        .LO(LO),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__conb_1 (
+    HI,
+    LO
+);
+
+    output HI;
+    output LO;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__conb base (
+        .HI(HI),
+        .LO(LO)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CONB_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLYMETAL6S2S_1_V
+`define SKY130_FD_SC_LS__DLYMETAL6S2S_1_V
+
+/**
+ * dlymetal6s2s: 6-inverter delay with output from 2nd stage on
+ *               horizontal route.
+ *
+ * Verilog wrapper for dlymetal6s2s with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dlymetal6s2s.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dlymetal6s2s_1 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__dlymetal6s2s base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dlymetal6s2s_1 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__dlymetal6s2s base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYMETAL6S2S_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A21BO_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__A21BO_PP_BLACKBOX_V
+
+/**
+ * a21bo: 2-input AND into first input of 2-input OR,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 & A2) | (!B1_N))
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a21bo (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21BO_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR4B_2_V
+`define SKY130_FD_SC_LS__OR4B_2_V
+
+/**
+ * or4b: 4-input OR, first input inverted.
+ *
+ * Verilog wrapper for or4b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__or4b.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__or4b_2 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__or4b base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D_N(D_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__or4b_2 (
+    X  ,
+    A  ,
+    B  ,
+    C  ,
+    D_N
+);
+
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C  ;
+    input  D_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__or4b base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D_N(D_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR4B_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__EBUFN_V
+`define SKY130_FD_SC_LS__EBUFN_V
+
+/**
+ * ebufn: Tri-state buffer, negative enable.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__ebufn.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__ebufn.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__ebufn.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__ebufn.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EBUFN_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O2BB2A_4_V
+`define SKY130_FD_SC_LS__O2BB2A_4_V
+
+/**
+ * o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
+ *
+ *         X = (!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o2bb2a with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o2bb2a.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o2bb2a_4 (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o2bb2a base (
+        .X(X),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o2bb2a_4 (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o2bb2a base (
+        .X(X),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2BB2A_4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD2_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__CLKDLYINV3SD2_FUNCTIONAL_PP_V
+
+/**
+ * clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
+ *                stage gate.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__clkdlyinv3sd2 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out_Y       , A                     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV3SD2_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A21OI_SYMBOL_V
+`define SKY130_FD_SC_LS__A21OI_SYMBOL_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | B1)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a21oi (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  B1,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21OI_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SDFSTP_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__SDFSTP_BEHAVIORAL_V
+
+/**
+ * sdfstp: Scan delay flop, inverted set, non-inverted clock,
+ *         single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ls__udp_dff_ps_pp_pg_n.v""
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+
+`celldefine
+module sky130_fd_sc_ls__sdfstp (
+    Q    ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B
+);
+
+    // Module ports
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q        ;
+    wire SET          ;
+    wire mux_out      ;
+    reg  notifier     ;
+    wire D_delayed    ;
+    wire SCD_delayed  ;
+    wire SCE_delayed  ;
+    wire SET_B_delayed;
+    wire CLK_delayed  ;
+    wire awake        ;
+    wire cond0        ;
+    wire cond1        ;
+    wire cond2        ;
+    wire cond3        ;
+    wire cond4        ;
+
+    //                                  Name       Output   Other arguments
+    not                                 not0      (SET    , SET_B_delayed                                  );
+    sky130_fd_sc_ls__udp_mux_2to1       mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed            );
+    sky130_fd_sc_ls__udp_dff$PS_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    assign cond0 = ( ( SET_B_delayed === 1\'b1 ) && awake );
+    assign cond1 = ( ( SCE_delayed === 1\'b0 ) && cond0 );
+    assign cond2 = ( ( SCE_delayed === 1\'b1 ) && cond0 );
+    assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
+    assign cond4 = ( ( SET_B === 1\'b1 ) && awake );
+    buf                                 buf0      (Q      , buf_Q                                          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFSTP_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND3_2_V
+`define SKY130_FD_SC_LS__AND3_2_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog wrapper for and3 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__and3.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__and3_2 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__and3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__and3_2 (
+    X,
+    A,
+    B,
+    C
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__and3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND3_2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__FILL_DIODE_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__FILL_DIODE_BEHAVIORAL_PP_V
+
+/**
+ * fill_diode: Fill diode.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__fill_diode (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FILL_DIODE_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFXBP_TB_V
+`define SKY130_FD_SC_LS__DFXBP_TB_V
+
+/**
+ * dfxbp: Delay flop, complementary outputs.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dfxbp.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Q;
+    wire Q_N;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   D    = 1\'b0;
+        #40   VGND = 1\'b0;
+        #60   VNB  = 1\'b0;
+        #80   VPB  = 1\'b0;
+        #100  VPWR = 1\'b0;
+        #120  D    = 1\'b1;
+        #140  VGND = 1\'b1;
+        #160  VNB  = 1\'b1;
+        #180  VPB  = 1\'b1;
+        #200  VPWR = 1\'b1;
+        #220  D    = 1\'b0;
+        #240  VGND = 1\'b0;
+        #260  VNB  = 1\'b0;
+        #280  VPB  = 1\'b0;
+        #300  VPWR = 1\'b0;
+        #320  VPWR = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VNB  = 1\'b1;
+        #380  VGND = 1\'b1;
+        #400  D    = 1\'b1;
+        #420  VPWR = 1\'bx;
+        #440  VPB  = 1\'bx;
+        #460  VNB  = 1\'bx;
+        #480  VGND = 1\'bx;
+        #500  D    = 1\'bx;
+    end
+
+    // Create a clock
+    reg CLK;
+    initial
+    begin
+        CLK = 1\'b0;
+    end
+
+    always
+    begin
+        #5 CLK = ~CLK;
+    end
+
+    sky130_fd_sc_ls__dfxbp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFXBP_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLCLKP_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__DLCLKP_PP_SYMBOL_V
+
+/**
+ * dlclkp: Clock gate.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlclkp (
+    //# {{clocks|Clocking}}
+    input  CLK ,
+    input  GATE,
+    output GCLK,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLCLKP_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__OR2B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__OR2B_FUNCTIONAL_PP_V
+
+/**
+ * or2b: 2-input OR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__or2b (
+    X   ,
+    A   ,
+    B_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , B_N                  );
+    or                                 or0         (or0_out_X        , not0_out, A          );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR2B_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A +=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O31A_2_V
+`define SKY130_FD_SC_LS__O31A_2_V
+
+/**
+ * o31a: 3-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & B1)
+ *
+ * Verilog wrapper for o31a with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o31a.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o31a_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o31a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o31a_2 (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o31a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O31A_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O41AI_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__O41AI_PP_BLACKBOX_V
+
+/**
+ * o41ai: 4-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o41ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O41AI_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DFF_P_PP_PG_N_TB_V
+`define SKY130_FD_SC_LS__UDP_DFF_P_PP_PG_N_TB_V
+
+/**
+ * udp_dff$P_pp$PG$N: Positive edge triggered D flip-flop
+ *                    (Q output UDP).
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg NOTIFIER;
+    reg VPWR;
+    reg VGND;
+
+    // Outputs are wires
+    wire Q;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D        = 1\'bX;
+        NOTIFIER = 1\'bX;
+        VGND     = 1\'bX;
+        VPWR     = 1\'bX;
+
+        #20   D        = 1\'b0;
+        #40   NOTIFIER = 1\'b0;
+        #60   VGND     = 1\'b0;
+        #80   VPWR     = 1\'b0;
+        #100  D        = 1\'b1;
+        #120  NOTIFIER = 1\'b1;
+        #140  VGND     = 1\'b1;
+        #160  VPWR     = 1\'b1;
+        #180  D        = 1\'b0;
+        #200  NOTIFIER = 1\'b0;
+        #220  VGND     = 1\'b0;
+        #240  VPWR     = 1\'b0;
+        #260  VPWR     = 1\'b1;
+        #280  VGND     = 1\'b1;
+        #300  NOTIFIER = 1\'b1;
+        #320  D        = 1\'b1;
+        #340  VPWR     = 1\'bx;
+        #360  VGND     = 1\'bx;
+        #380  NOTIFIER = 1\'bx;
+        #400  D        = 1\'bx;
+    end
+
+    // Create a clock
+    reg CLK;
+    initial
+    begin
+        CLK = 1\'b0;
+    end
+
+    always
+    begin
+        #5 CLK = ~CLK;
+    end
+
+    sky130_fd_sc_ls__udp_dff$P_pp$PG$N dut (.D(D), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DFF_P_PP_PG_N_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DFF_PS_PP_PG_N_SYMBOL_V
+`define SKY130_FD_SC_LS__UDP_DFF_PS_PP_PG_N_SYMBOL_V
+
+/**
+ * udp_dff$PS_pp$PG$N: Positive edge triggered D flip-flop with active
+ *                     high
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__udp_dff$PS_pp$PG$N (
+    //# {{data|Data Signals}}
+    input  D       ,
+    output Q       ,
+
+    //# {{control|Control Signals}}
+    input  SET     ,
+
+    //# {{clocks|Clocking}}
+    input  CLK     ,
+
+    //# {{power|Power}}
+    input  NOTIFIER,
+    input  VPWR    ,
+    input  VGND
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DFF_PS_PP_PG_N_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__CLKBUF_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__CLKBUF_FUNCTIONAL_PP_V
+
+/**
+ * clkbuf: Clock tree buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__clkbuf (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKBUF_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__TAPMET1_TB_V
+`define SKY130_FD_SC_LS__TAPMET1_TB_V
+
+/**
+ * tapmet1: Tap cell with isolated power and ground connections.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__tapmet1.v""
+
+module top();
+
+    // Inputs are registered
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   VGND = 1\'b0;
+        #40   VNB  = 1\'b0;
+        #60   VPB  = 1\'b0;
+        #80   VPWR = 1\'b0;
+        #100  VGND = 1\'b1;
+        #120  VNB  = 1\'b1;
+        #140  VPB  = 1\'b1;
+        #160  VPWR = 1\'b1;
+        #180  VGND = 1\'b0;
+        #200  VNB  = 1\'b0;
+        #220  VPB  = 1\'b0;
+        #240  VPWR = 1\'b0;
+        #260  VPWR = 1\'b1;
+        #280  VPB  = 1\'b1;
+        #300  VNB  = 1\'b1;
+        #320  VGND = 1\'b1;
+        #340  VPWR = 1\'bx;
+        #360  VPB  = 1\'bx;
+        #380  VNB  = 1\'bx;
+        #400  VGND = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__tapmet1 dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPMET1_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O21AI_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__O21AI_BEHAVIORAL_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__o21ai (
+    Y ,
+    A1,
+    A2,
+    B1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out    ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    or   or0   (or0_out    , A2, A1         );
+    nand nand0 (nand0_out_Y, B1, or0_out    );
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21AI_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__AND3_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__AND3_FUNCTIONAL_PP_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__and3 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out_X       , C, A, B               );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND3_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__TAPVGND2_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__TAPVGND2_FUNCTIONAL_V
+
+/**
+ * tapvgnd2: Tap cell with tap to ground, isolated power connection 2
+ *           rows down.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__tapvgnd2 ();
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPVGND2_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A1 +=> X) = (0:0:0,0:0:0);
+(A2 +=> X) = (0:0:0,0:0:0);
+(A3 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&A3)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&A3)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&A3)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2&!A3)) (B1 +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O2111A_SYMBOL_V
+`define SKY130_FD_SC_LS__O2111A_SYMBOL_V
+
+/**
+ * o2111a: 2-input OR into first input of 4-input AND.
+ *
+ *         X = ((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o2111a (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  B1,
+    input  C1,
+    input  D1,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2111A_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND2_1_V
+`define SKY130_FD_SC_LS__NAND2_1_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog wrapper for nand2 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nand2.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nand2_1 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nand2 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nand2_1 (
+    Y,
+    A,
+    B
+);
+
+    output Y;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nand2 base (
+        .Y(Y),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND2_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FA_TB_V
+`define SKY130_FD_SC_LS__FA_TB_V
+
+/**
+ * fa: Full adder.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__fa.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg B;
+    reg CIN;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire COUT;
+    wire SUM;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        B    = 1\'bX;
+        CIN  = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   B    = 1\'b0;
+        #60   CIN  = 1\'b0;
+        #80   VGND = 1\'b0;
+        #100  VNB  = 1\'b0;
+        #120  VPB  = 1\'b0;
+        #140  VPWR = 1\'b0;
+        #160  A    = 1\'b1;
+        #180  B    = 1\'b1;
+        #200  CIN  = 1\'b1;
+        #220  VGND = 1\'b1;
+        #240  VNB  = 1\'b1;
+        #260  VPB  = 1\'b1;
+        #280  VPWR = 1\'b1;
+        #300  A    = 1\'b0;
+        #320  B    = 1\'b0;
+        #340  CIN  = 1\'b0;
+        #360  VGND = 1\'b0;
+        #380  VNB  = 1\'b0;
+        #400  VPB  = 1\'b0;
+        #420  VPWR = 1\'b0;
+        #440  VPWR = 1\'b1;
+        #460  VPB  = 1\'b1;
+        #480  VNB  = 1\'b1;
+        #500  VGND = 1\'b1;
+        #520  CIN  = 1\'b1;
+        #540  B    = 1\'b1;
+        #560  A    = 1\'b1;
+        #580  VPWR = 1\'bx;
+        #600  VPB  = 1\'bx;
+        #620  VNB  = 1\'bx;
+        #640  VGND = 1\'bx;
+        #660  CIN  = 1\'bx;
+        #680  B    = 1\'bx;
+        #700  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__fa dut (.A(A), .B(B), .CIN(CIN), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .COUT(COUT), .SUM(SUM));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FA_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD3_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__CLKDLYINV3SD3_BEHAVIORAL_V
+
+/**
+ * clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
+ *                stage gate.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__clkdlyinv3sd3 (
+    Y,
+    A
+);
+
+    // Module ports
+    output Y;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out_Y, A              );
+    buf buf0 (Y         , not0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV3SD3_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__TAPVGND2_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__TAPVGND2_FUNCTIONAL_PP_V
+
+/**
+ * tapvgnd2: Tap cell with tap to ground, isolated power connection 2
+ *           rows down.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__tapvgnd2 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPVGND2_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O211A_BLACKBOX_V
+`define SKY130_FD_SC_LS__O211A_BLACKBOX_V
+
+/**
+ * o211a: 2-input OR into first input of 3-input AND.
+ *
+ *        X = ((A1 | A2) & B1 & C1)
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o211a (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O211A_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLYMETAL6S6S_SYMBOL_V
+`define SKY130_FD_SC_LS__DLYMETAL6S6S_SYMBOL_V
+
+/**
+ * dlymetal6s6s: 6-inverter delay with output from 6th inverter on
+ *               horizontal route.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlymetal6s6s (
+    //# {{data|Data Signals}}
+    input  A,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYMETAL6S6S_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLXTP_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__DLXTP_FUNCTIONAL_V
+
+/**
+ * dlxtp: Delay latch, non-inverted enable, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_p/sky130_fd_sc_ls__udp_dlatch_p.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlxtp (
+    Q   ,
+    D   ,
+    GATE
+);
+
+    // Module ports
+    output Q   ;
+    input  D   ;
+    input  GATE;
+
+    // Local signals
+    wire buf_Q;
+
+    //                            Name     Output  Other arguments
+    sky130_fd_sc_ls__udp_dlatch$P dlatch0 (buf_Q , D, GATE        );
+    buf                           buf0    (Q     , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXTP_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__BUFINV_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__BUFINV_BEHAVIORAL_V
+
+/**
+ * bufinv: Buffer followed by inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__bufinv (
+    Y,
+    A
+);
+
+    // Module ports
+    output Y;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out_Y, A              );
+    buf buf0 (Y         , not0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__BUFINV_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND4BB_SYMBOL_V
+`define SKY130_FD_SC_LS__AND4BB_SYMBOL_V
+
+/**
+ * and4bb: 4-input AND, first two inputs inverted.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__and4bb (
+    //# {{data|Data Signals}}
+    input  A_N,
+    input  B_N,
+    input  C  ,
+    input  D  ,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND4BB_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NAND2_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__NAND2_BEHAVIORAL_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__nand2 (
+    Y,
+    A,
+    B
+);
+
+    // Module ports
+    output Y;
+    input  A;
+    input  B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    nand nand0 (nand0_out_Y, B, A           );
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND2_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DFF_PR_V
+`define SKY130_FD_SC_LS__UDP_DFF_PR_V
+
+/**
+ * udp_dff$PR: Positive edge triggered D flip-flop with active high
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`include ""./sky130_fd_sc_ls__udp_dff_pr.blackbox.v""
+`else
+primitive sky130_fd_sc_ls__udp_dff$PR (
+    Q    ,
+    D    ,
+    CLK  ,
+    RESET
+);
+
+    output Q    ;
+    input  D    ;
+    input  CLK  ;
+    input  RESET;
+
+    reg Q;
+
+    table
+     //  D  CLK  RESET :  Qt : Qt+1
+         *   b     0   :  ?  :  -    ; // data event, hold unless CP==x
+         ?  (?0)   0   :  ?  :  -    ; // CP => 0, hold
+         ?   b    (?0) :  ?  :  -    ; // R => 0, hold unless CP==x
+         ?   ?     1   :  ?  :  0    ; // async reset
+         0   r     ?   :  ?  :  0    ; // clock data on CP
+         1   r     0   :  ?  :  1    ; // clock data on CP
+         0  (x1)   ?   :  0  :  0    ; // possible CP, hold when D==Q==0
+         1  (x1)   0   :  1  :  1    ; // possible CP, hold when D==Q==1
+         0   x     ?   :  0  :  0    ; // unkown CP, hold when D==Q==0
+         1   x     0   :  1  :  1    ; // unkown CP, hold when D==Q==1
+         ?   b    (?x) :  0  :  0    ; // R=>x, hold when Q==0 unless CP==x
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DFF_PR_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLXTN_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__DLXTN_BEHAVIORAL_V
+
+/**
+ * dlxtn: Delay latch, inverted enable, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlxtn (
+    Q     ,
+    D     ,
+    GATE_N
+);
+
+    // Module ports
+    output Q     ;
+    input  D     ;
+    input  GATE_N;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire GATE          ;
+    wire buf_Q         ;
+    wire GATE_N_delayed;
+    wire D_delayed     ;
+    reg  notifier      ;
+    wire awake         ;
+
+    //                                    Name     Output  Other arguments
+    not                                   not0    (GATE  , GATE_N_delayed                       );
+    sky130_fd_sc_ls__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
+    buf                                   buf0    (Q     , buf_Q                                );
+    assign awake = ( VPWR === 1\'b1 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXTN_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A_N +=> Y) = (0:0:0,0:0:0);
+(B_N +=> Y) = (0:0:0,0:0:0);
+(C -=> Y) = (0:0:0,0:0:0);
+(D -=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+( CLK +=> GCLK ) = ( 0:0:0 , 0:0:0 ) ;                         // delays are tris , tfall
+$setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , SCE_AWAKE , SCE_AWAKE , CLK_delayed , SCE_delayed ) ;
+$setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , SCE_AWAKE , SCE_AWAKE , CLK_delayed , SCE_delayed ) ;
+$setuphold ( posedge CLK , posedge GATE , 0:0:0 , 0:0:0 , notifier , GATE_AWAKE , GATE_AWAKE , CLK_delayed , GATE_delayed ) ;
+$setuphold ( posedge CLK , negedge GATE , 0:0:0 , 0:0:0 , notifier , GATE_AWAKE , GATE_AWAKE , CLK_delayed , GATE_delayed ) ;
+$width ( negedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD1_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__CLKDLYINV3SD1_BEHAVIORAL_PP_V
+
+/**
+ * clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
+ *                stage gate.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__clkdlyinv3sd1 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out_Y       , A                     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV3SD1_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NOR3B_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__NOR3B_BEHAVIORAL_V
+
+/**
+ * nor3b: 3-input NOR, first input inverted.
+ *
+ *        Y = (!(A | B)) & !C)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__nor3b (
+    Y  ,
+    A  ,
+    B  ,
+    C_N
+);
+
+    // Module ports
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nor0_out  ;
+    wire and0_out_Y;
+
+    //  Name  Output      Other arguments
+    nor nor0 (nor0_out  , A, B           );
+    and and0 (and0_out_Y, C_N, nor0_out  );
+    buf buf0 (Y         , and0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR3B_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O2BB2AI_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__O2BB2AI_FUNCTIONAL_V
+
+/**
+ * o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
+ *
+ *          Y = !(!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__o2bb2ai (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    // Module ports
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Local signals
+    wire nand0_out  ;
+    wire or0_out    ;
+    wire nand1_out_Y;
+
+    //   Name   Output       Other arguments
+    nand nand0 (nand0_out  , A2_N, A1_N        );
+    or   or0   (or0_out    , B2, B1            );
+    nand nand1 (nand1_out_Y, nand0_out, or0_out);
+    buf  buf0  (Y          , nand1_out_Y       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2BB2AI_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__XNOR3_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__XNOR3_BEHAVIORAL_V
+
+/**
+ * xnor3: 3-input exclusive NOR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__xnor3 (
+    X,
+    A,
+    B,
+    C
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire xnor0_out_X;
+
+    //   Name   Output       Other arguments
+    xnor xnor0 (xnor0_out_X, A, B, C        );
+    buf  buf0  (X          , xnor0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XNOR3_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD3_1_V
+`define SKY130_FD_SC_LS__CLKDLYINV5SD3_1_V
+
+/**
+ * clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
+ *                stage gate.
+ *
+ * Verilog wrapper for clkdlyinv5sd3 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__clkdlyinv5sd3.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__clkdlyinv5sd3_1 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__clkdlyinv5sd3 base (
+        .Y(Y),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__clkdlyinv5sd3_1 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__clkdlyinv5sd3 base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV5SD3_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD3_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__CLKDLYINV5SD3_PP_BLACKBOX_V
+
+/**
+ * clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
+ *                stage gate.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__clkdlyinv5sd3 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV5SD3_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A +=> X) = (0:0:0,0:0:0);
+(B +=> X) = (0:0:0,0:0:0);
+(C_N -=> X) = (0:0:0,0:0:0);
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__EDFXTP_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__EDFXTP_FUNCTIONAL_V
+
+/**
+ * edfxtp: Delay flop with loopback enable, non-inverted clock,
+ *         single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+`include ""../../models/udp_dff_p/sky130_fd_sc_ls__udp_dff_p.v""
+
+`celldefine
+module sky130_fd_sc_ls__edfxtp (
+    Q  ,
+    CLK,
+    D  ,
+    DE
+);
+
+    // Module ports
+    output Q  ;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+
+    // Local signals
+    wire buf_Q  ;
+    wire mux_out;
+
+    //                            Delay       Name       Output   Other arguments
+    sky130_fd_sc_ls__udp_mux_2to1             mux_2to10 (mux_out, buf_Q, D, DE   );
+    sky130_fd_sc_ls__udp_dff$P    `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK   );
+    buf                                       buf0      (Q      , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EDFXTP_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND4BB_4_V
+`define SKY130_FD_SC_LS__AND4BB_4_V
+
+/**
+ * and4bb: 4-input AND, first two inputs inverted.
+ *
+ * Verilog wrapper for and4bb with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__and4bb.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__and4bb_4 (
+    X   ,
+    A_N ,
+    B_N ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A_N ;
+    input  B_N ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__and4bb base (
+        .X(X),
+        .A_N(A_N),
+        .B_N(B_N),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__and4bb_4 (
+    X  ,
+    A_N,
+    B_N,
+    C  ,
+    D
+);
+
+    output X  ;
+    input  A_N;
+    input  B_N;
+    input  C  ;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__and4bb base (
+        .X(X),
+        .A_N(A_N),
+        .B_N(B_N),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND4BB_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR4BB_1_V
+`define SKY130_FD_SC_LS__NOR4BB_1_V
+
+/**
+ * nor4bb: 4-input NOR, first two inputs inverted.
+ *
+ * Verilog wrapper for nor4bb with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nor4bb.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor4bb_1 (
+    Y   ,
+    A   ,
+    B   ,
+    C_N ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nor4bb base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C_N(C_N),
+        .D_N(D_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor4bb_1 (
+    Y  ,
+    A  ,
+    B  ,
+    C_N,
+    D_N
+);
+
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+    input  D_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nor4bb base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C_N(C_N),
+        .D_N(D_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR4BB_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__EDFXBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__EDFXBP_FUNCTIONAL_PP_V
+
+/**
+ * edfxbp: Delay flop with loopback enable, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+`include ""../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__edfxbp (
+    Q   ,
+    Q_N ,
+    CLK ,
+    D   ,
+    DE  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    output Q_N ;
+    input  CLK ;
+    input  D   ;
+    input  DE  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q  ;
+    wire mux_out;
+
+    //                                 Delay       Name       Output   Other arguments
+    sky130_fd_sc_ls__udp_mux_2to1                  mux_2to10 (mux_out, buf_Q, D, DE              );
+    sky130_fd_sc_ls__udp_dff$P_pp$PG$N `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK, , VPWR, VGND);
+    buf                                            buf0      (Q      , buf_Q                     );
+    not                                            not0      (Q_N    , buf_Q                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EDFXBP_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLXBN_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__DLXBN_PP_BLACKBOX_V
+
+/**
+ * dlxbn: Delay latch, inverted enable, complementary outputs.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlxbn (
+    Q     ,
+    Q_N   ,
+    D     ,
+    GATE_N,
+    VPWR  ,
+    VGND  ,
+    VPB   ,
+    VNB
+);
+
+    output Q     ;
+    output Q_N   ;
+    input  D     ;
+    input  GATE_N;
+    input  VPWR  ;
+    input  VGND  ;
+    input  VPB   ;
+    input  VNB   ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXBN_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O2BB2A_V
+`define SKY130_FD_SC_LS__O2BB2A_V
+
+/**
+ * o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
+ *
+ *         X = (!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o2bb2a.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o2bb2a.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o2bb2a.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o2bb2a.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2BB2A_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFSTP_2_V
+`define SKY130_FD_SC_LS__SDFSTP_2_V
+
+/**
+ * sdfstp: Scan delay flop, inverted set, non-inverted clock,
+ *         single output.
+ *
+ * Verilog wrapper for sdfstp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__sdfstp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sdfstp_2 (
+    Q    ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_ls__sdfstp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .SET_B(SET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sdfstp_2 (
+    Q    ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B
+);
+
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__sdfstp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .SET_B(SET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFSTP_2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__FAHCIN_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__FAHCIN_BEHAVIORAL_V
+
+/**
+ * fahcin: Full adder, inverted carry in.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__fahcin (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CIN
+);
+
+    // Module ports
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CIN ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire ci          ;
+    wire xor0_out_SUM;
+    wire a_b         ;
+    wire a_ci        ;
+    wire b_ci        ;
+    wire or0_out_COUT;
+
+    //  Name  Output        Other arguments
+    not not0 (ci          , CIN            );
+    xor xor0 (xor0_out_SUM, A, B, ci       );
+    buf buf0 (SUM         , xor0_out_SUM   );
+    and and0 (a_b         , A, B           );
+    and and1 (a_ci        , A, ci          );
+    and and2 (b_ci        , B, ci          );
+    or  or0  (or0_out_COUT, a_b, a_ci, b_ci);
+    buf buf1 (COUT        , or0_out_COUT   );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FAHCIN_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR2_TB_V
+`define SKY130_FD_SC_LS__OR2_TB_V
+
+/**
+ * or2: 2-input OR.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__or2.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg B;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        B    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   B    = 1\'b0;
+        #60   VGND = 1\'b0;
+        #80   VNB  = 1\'b0;
+        #100  VPB  = 1\'b0;
+        #120  VPWR = 1\'b0;
+        #140  A    = 1\'b1;
+        #160  B    = 1\'b1;
+        #180  VGND = 1\'b1;
+        #200  VNB  = 1\'b1;
+        #220  VPB  = 1\'b1;
+        #240  VPWR = 1\'b1;
+        #260  A    = 1\'b0;
+        #280  B    = 1\'b0;
+        #300  VGND = 1\'b0;
+        #320  VNB  = 1\'b0;
+        #340  VPB  = 1\'b0;
+        #360  VPWR = 1\'b0;
+        #380  VPWR = 1\'b1;
+        #400  VPB  = 1\'b1;
+        #420  VNB  = 1\'b1;
+        #440  VGND = 1\'b1;
+        #460  B    = 1\'b1;
+        #480  A    = 1\'b1;
+        #500  VPWR = 1\'bx;
+        #520  VPB  = 1\'bx;
+        #540  VNB  = 1\'bx;
+        #560  VGND = 1\'bx;
+        #580  B    = 1\'bx;
+        #600  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__or2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR2_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFRTN_SYMBOL_V
+`define SKY130_FD_SC_LS__SDFRTN_SYMBOL_V
+
+/**
+ * sdfrtn: Scan delay flop, inverted reset, inverted clock,
+ *         single output.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sdfrtn (
+    //# {{data|Data Signals}}
+    input  D      ,
+    output Q      ,
+
+    //# {{control|Control Signals}}
+    input  RESET_B,
+
+    //# {{scanchain|Scan Chain}}
+    input  SCD    ,
+    input  SCE    ,
+
+    //# {{clocks|Clocking}}
+    input  CLK_N
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFRTN_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A2111O_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__A2111O_FUNCTIONAL_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ *         X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a2111o (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Local signals
+    wire and0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , A1, A2              );
+    or  or0  (or0_out_X, C1, B1, and0_out, D1);
+    buf buf0 (X        , or0_out_X           );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2111O_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O311AI_V
+`define SKY130_FD_SC_LS__O311AI_V
+
+/**
+ * o311ai: 3-input OR into 3-input NAND.
+ *
+ *         Y = !((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o311ai.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o311ai.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o311ai.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o311ai.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O311AI_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_PWRGOOD_PP_P_TB_V
+`define SKY130_FD_SC_LS__UDP_PWRGOOD_PP_P_TB_V
+
+/**
+
+ *   UDP_OUT :=x when VPWR!=1
+ *   UDP_OUT :=UDP_IN when VPWR==1
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__udp_pwrgood_pp_p.v""
+
+module top();
+
+    // Inputs are registered
+    reg UDP_IN;
+    reg VPWR;
+
+    // Outputs are wires
+    wire UDP_OUT;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        UDP_IN = 1\'bX;
+        VPWR   = 1\'bX;
+
+        #20   UDP_IN = 1\'b0;
+        #40   VPWR   = 1\'b0;
+        #60   UDP_IN = 1\'b1;
+        #80   VPWR   = 1\'b1;
+        #100  UDP_IN = 1\'b0;
+        #120  VPWR   = 1\'b0;
+        #140  VPWR   = 1\'b1;
+        #160  UDP_IN = 1\'b1;
+        #180  VPWR   = 1\'bx;
+        #200  UDP_IN = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__udp_pwrgood_pp$P dut (.UDP_IN(UDP_IN), .VPWR(VPWR), .UDP_OUT(UDP_OUT));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_PWRGOOD_PP_P_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O32AI_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__O32AI_BEHAVIORAL_V
+
+/**
+ * o32ai: 3-input OR and 2-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__o32ai (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nor0_out ;
+    wire nor1_out ;
+    wire or0_out_Y;
+
+    //  Name  Output     Other arguments
+    nor nor0 (nor0_out , A3, A1, A2        );
+    nor nor1 (nor1_out , B1, B2            );
+    or  or0  (or0_out_Y, nor1_out, nor0_out);
+    buf buf0 (Y        , or0_out_Y         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O32AI_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR3_4_V
+`define SKY130_FD_SC_LS__NOR3_4_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ *       Y = !(A | B | C | !D)
+ *
+ * Verilog wrapper for nor3 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nor3.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor3_4 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nor3 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor3_4 (
+    Y,
+    A,
+    B,
+    C
+);
+
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nor3 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR3_4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A1 +=> X) = (0:0:0,0:0:0);
+(A2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2)) (B1 +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__MUX2I_2_V
+`define SKY130_FD_SC_LS__MUX2I_2_V
+
+/**
+ * mux2i: 2-input multiplexer, output inverted.
+ *
+ * Verilog wrapper for mux2i with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__mux2i.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__mux2i_2 (
+    Y   ,
+    A0  ,
+    A1  ,
+    S   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A0  ;
+    input  A1  ;
+    input  S   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__mux2i base (
+        .Y(Y),
+        .A0(A0),
+        .A1(A1),
+        .S(S),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__mux2i_2 (
+    Y ,
+    A0,
+    A1,
+    S
+);
+
+    output Y ;
+    input  A0;
+    input  A1;
+    input  S ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__mux2i base (
+        .Y(Y),
+        .A0(A0),
+        .A1(A1),
+        .S(S)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MUX2I_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFBBN_2_V
+`define SKY130_FD_SC_LS__DFBBN_2_V
+
+/**
+ * dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
+ *        complementary outputs.
+ *
+ * Verilog wrapper for dfbbn with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dfbbn.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dfbbn_2 (
+    Q      ,
+    Q_N    ,
+    D      ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_ls__dfbbn base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .D(D),
+        .CLK_N(CLK_N),
+        .SET_B(SET_B),
+        .RESET_B(RESET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dfbbn_2 (
+    Q      ,
+    Q_N    ,
+    D      ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__dfbbn base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .D(D),
+        .CLK_N(CLK_N),
+        .SET_B(SET_B),
+        .RESET_B(RESET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFBBN_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFRBP_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__SDFRBP_PP_BLACKBOX_V
+
+/**
+ * sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sdfrbp (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFRBP_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SDLCLKP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__SDLCLKP_FUNCTIONAL_PP_V
+
+/**
+ * sdlclkp: Scan gated clock.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__sdlclkp (
+    GCLK,
+    SCE ,
+    GATE,
+    CLK ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output GCLK;
+    input  SCE ;
+    input  GATE;
+    input  CLK ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire m0      ;
+    wire m0n     ;
+    wire clkn    ;
+    wire SCE_GATE;
+
+    //                                    Name     Output    Other arguments
+    not                                   not0    (m0n     , m0                          );
+    not                                   not1    (clkn    , CLK                         );
+    nor                                   nor0    (SCE_GATE, GATE, SCE                   );
+    sky130_fd_sc_ls__udp_dlatch$P_pp$PG$N dlatch0 (m0      , SCE_GATE, clkn, , VPWR, VGND);
+    and                                   and0    (GCLK    , m0n, CLK                    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDLCLKP_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O2111AI_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__O2111AI_PP_SYMBOL_V
+
+/**
+ * o2111ai: 2-input OR into first input of 4-input NAND.
+ *
+ *          Y = !((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o2111ai (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  B1  ,
+    input  C1  ,
+    input  D1  ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2111AI_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFSTP_BLACKBOX_V
+`define SKY130_FD_SC_LS__SDFSTP_BLACKBOX_V
+
+/**
+ * sdfstp: Scan delay flop, inverted set, non-inverted clock,
+ *         single output.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sdfstp (
+    Q    ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B
+);
+
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFSTP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFRTP_2_V
+`define SKY130_FD_SC_LS__DFRTP_2_V
+
+/**
+ * dfrtp: Delay flop, inverted reset, single output.
+ *
+ * Verilog wrapper for dfrtp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dfrtp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dfrtp_2 (
+    Q      ,
+    CLK    ,
+    D      ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_ls__dfrtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .RESET_B(RESET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dfrtp_2 (
+    Q      ,
+    CLK    ,
+    D      ,
+    RESET_B
+);
+
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__dfrtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .RESET_B(RESET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFRTP_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFSBP_V
+`define SKY130_FD_SC_LS__DFSBP_V
+
+/**
+ * dfsbp: Delay flop, inverted set, complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dfsbp.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dfsbp.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dfsbp.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dfsbp.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFSBP_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__MUX4_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__MUX4_PP_SYMBOL_V
+
+/**
+ * mux4: 4-input multiplexer.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__mux4 (
+    //# {{data|Data Signals}}
+    input  A0  ,
+    input  A1  ,
+    input  A2  ,
+    input  A3  ,
+    output X   ,
+
+    //# {{control|Control Signals}}
+    input  S0  ,
+    input  S1  ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MUX4_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_MUX_2TO1_V
+`define SKY130_FD_SC_LS__UDP_MUX_2TO1_V
+
+/**
+ * udp_mux_2to1: Two to one multiplexer
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`include ""./sky130_fd_sc_ls__udp_mux_2to1.blackbox.v""
+`else
+primitive sky130_fd_sc_ls__udp_mux_2to1 (
+    X ,
+    A0,
+    A1,
+    S
+);
+
+    output X ;
+    input  A0;
+    input  A1;
+    input  S ;
+
+    table
+     //  A0  A1  S  :  X
+         0   0   ?  :  0   ;
+         1   1   ?  :  1   ;
+         0   ?   0  :  0   ;
+         1   ?   0  :  1   ;
+         ?   0   1  :  0   ;
+         ?   1   1  :  1   ;
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_MUX_2TO1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A21BO_TB_V
+`define SKY130_FD_SC_LS__A21BO_TB_V
+
+/**
+ * a21bo: 2-input AND into first input of 2-input OR,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 & A2) | (!B1_N))
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a21bo.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg B1_N;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        B1_N = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   B1_N = 1\'b0;
+        #80   VGND = 1\'b0;
+        #100  VNB  = 1\'b0;
+        #120  VPB  = 1\'b0;
+        #140  VPWR = 1\'b0;
+        #160  A1   = 1\'b1;
+        #180  A2   = 1\'b1;
+        #200  B1_N = 1\'b1;
+        #220  VGND = 1\'b1;
+        #240  VNB  = 1\'b1;
+        #260  VPB  = 1\'b1;
+        #280  VPWR = 1\'b1;
+        #300  A1   = 1\'b0;
+        #320  A2   = 1\'b0;
+        #340  B1_N = 1\'b0;
+        #360  VGND = 1\'b0;
+        #380  VNB  = 1\'b0;
+        #400  VPB  = 1\'b0;
+        #420  VPWR = 1\'b0;
+        #440  VPWR = 1\'b1;
+        #460  VPB  = 1\'b1;
+        #480  VNB  = 1\'b1;
+        #500  VGND = 1\'b1;
+        #520  B1_N = 1\'b1;
+        #540  A2   = 1\'b1;
+        #560  A1   = 1\'b1;
+        #580  VPWR = 1\'bx;
+        #600  VPB  = 1\'bx;
+        #620  VNB  = 1\'bx;
+        #640  VGND = 1\'bx;
+        #660  B1_N = 1\'bx;
+        #680  A2   = 1\'bx;
+        #700  A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__a21bo dut (.A1(A1), .A2(A2), .B1_N(B1_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21BO_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SEDFXBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__SEDFXBP_FUNCTIONAL_PP_V
+
+/**
+ * sedfxbp: Scan delay flop, data enable, non-inverted clock,
+ *          complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+`include ""../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__sedfxbp (
+    Q   ,
+    Q_N ,
+    CLK ,
+    D   ,
+    DE  ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    output Q_N ;
+    input  CLK ;
+    input  D   ;
+    input  DE  ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q  ;
+    wire mux_out;
+    wire de_d   ;
+
+    //                                 Delay       Name       Output   Other arguments
+    sky130_fd_sc_ls__udp_mux_2to1                  mux_2to10 (mux_out, de_d, SCD, SCE            );
+    sky130_fd_sc_ls__udp_mux_2to1                  mux_2to11 (de_d   , buf_Q, D, DE              );
+    sky130_fd_sc_ls__udp_dff$P_pp$PG$N `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK, , VPWR, VGND);
+    buf                                            buf0      (Q      , buf_Q                     );
+    not                                            not0      (Q_N    , buf_Q                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SEDFXBP_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFRTN_SYMBOL_V
+`define SKY130_FD_SC_LS__DFRTN_SYMBOL_V
+
+/**
+ * dfrtn: Delay flop, inverted reset, inverted clock,
+ *        complementary outputs.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dfrtn (
+    //# {{data|Data Signals}}
+    input  D      ,
+    output Q      ,
+
+    //# {{control|Control Signals}}
+    input  RESET_B,
+
+    //# {{clocks|Clocking}}
+    input  CLK_N
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFRTN_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A211O_TB_V
+`define SKY130_FD_SC_LS__A211O_TB_V
+
+/**
+ * a211o: 2-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2) | B1 | C1)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a211o.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg B1;
+    reg C1;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        B1   = 1\'bX;
+        C1   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   B1   = 1\'b0;
+        #80   C1   = 1\'b0;
+        #100  VGND = 1\'b0;
+        #120  VNB  = 1\'b0;
+        #140  VPB  = 1\'b0;
+        #160  VPWR = 1\'b0;
+        #180  A1   = 1\'b1;
+        #200  A2   = 1\'b1;
+        #220  B1   = 1\'b1;
+        #240  C1   = 1\'b1;
+        #260  VGND = 1\'b1;
+        #280  VNB  = 1\'b1;
+        #300  VPB  = 1\'b1;
+        #320  VPWR = 1\'b1;
+        #340  A1   = 1\'b0;
+        #360  A2   = 1\'b0;
+        #380  B1   = 1\'b0;
+        #400  C1   = 1\'b0;
+        #420  VGND = 1\'b0;
+        #440  VNB  = 1\'b0;
+        #460  VPB  = 1\'b0;
+        #480  VPWR = 1\'b0;
+        #500  VPWR = 1\'b1;
+        #520  VPB  = 1\'b1;
+        #540  VNB  = 1\'b1;
+        #560  VGND = 1\'b1;
+        #580  C1   = 1\'b1;
+        #600  B1   = 1\'b1;
+        #620  A2   = 1\'b1;
+        #640  A1   = 1\'b1;
+        #660  VPWR = 1\'bx;
+        #680  VPB  = 1\'bx;
+        #700  VNB  = 1\'bx;
+        #720  VGND = 1\'bx;
+        #740  C1   = 1\'bx;
+        #760  B1   = 1\'bx;
+        #780  A2   = 1\'bx;
+        #800  A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__a211o dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A211O_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A41O_4_V
+`define SKY130_FD_SC_LS__A41O_4_V
+
+/**
+ * a41o: 4-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog wrapper for a41o with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a41o.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a41o_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a41o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a41o_4 (
+    X ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a41o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A41O_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND3_TB_V
+`define SKY130_FD_SC_LS__AND3_TB_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__and3.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg B;
+    reg C;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        B    = 1\'bX;
+        C    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   B    = 1\'b0;
+        #60   C    = 1\'b0;
+        #80   VGND = 1\'b0;
+        #100  VNB  = 1\'b0;
+        #120  VPB  = 1\'b0;
+        #140  VPWR = 1\'b0;
+        #160  A    = 1\'b1;
+        #180  B    = 1\'b1;
+        #200  C    = 1\'b1;
+        #220  VGND = 1\'b1;
+        #240  VNB  = 1\'b1;
+        #260  VPB  = 1\'b1;
+        #280  VPWR = 1\'b1;
+        #300  A    = 1\'b0;
+        #320  B    = 1\'b0;
+        #340  C    = 1\'b0;
+        #360  VGND = 1\'b0;
+        #380  VNB  = 1\'b0;
+        #400  VPB  = 1\'b0;
+        #420  VPWR = 1\'b0;
+        #440  VPWR = 1\'b1;
+        #460  VPB  = 1\'b1;
+        #480  VNB  = 1\'b1;
+        #500  VGND = 1\'b1;
+        #520  C    = 1\'b1;
+        #540  B    = 1\'b1;
+        #560  A    = 1\'b1;
+        #580  VPWR = 1\'bx;
+        #600  VPB  = 1\'bx;
+        #620  VNB  = 1\'bx;
+        #640  VGND = 1\'bx;
+        #660  C    = 1\'bx;
+        #680  B    = 1\'bx;
+        #700  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__and3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND3_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O21BA_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__O21BA_FUNCTIONAL_V
+
+/**
+ * o21ba: 2-input OR into first input of 2-input AND,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 | A2) & !B1_N)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__o21ba (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Local signals
+    wire nor0_out  ;
+    wire nor1_out_X;
+
+    //  Name  Output      Other arguments
+    nor nor0 (nor0_out  , A1, A2         );
+    nor nor1 (nor1_out_X, B1_N, nor0_out );
+    buf buf0 (X         , nor1_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21BA_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A2111OI_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__A2111OI_FUNCTIONAL_V
+
+/**
+ * a2111oi: 2-input AND into first input of 4-input NOR.
+ *
+ *          Y = !((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a2111oi (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Local signals
+    wire and0_out  ;
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out  , A1, A2              );
+    nor nor0 (nor0_out_Y, B1, C1, D1, and0_out);
+    buf buf0 (Y         , nor0_out_Y          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2111OI_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD2_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__CLKDLYINV5SD2_BEHAVIORAL_V
+
+/**
+ * clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
+ *                stage gate.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__clkdlyinv5sd2 (
+    Y,
+    A
+);
+
+    // Module ports
+    output Y;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out_Y, A              );
+    buf buf0 (Y         , not0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV5SD2_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__TAPMET1_2_V
+`define SKY130_FD_SC_LS__TAPMET1_2_V
+
+/**
+ * tapmet1: Tap cell with isolated power and ground connections.
+ *
+ * Verilog wrapper for tapmet1 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__tapmet1.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__tapmet1_2 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+    sky130_fd_sc_ls__tapmet1 base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__tapmet1_2 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__tapmet1 base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPMET1_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_PWRGOOD_PP_PG_SYMBOL_V
+`define SKY130_FD_SC_LS__UDP_PWRGOOD_PP_PG_SYMBOL_V
+
+/**
+
+ *   UDP_OUT :=x when VPWR!=1 or VGND!=0
+ *   UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__udp_pwrgood_pp$PG (
+    //# {{data|Data Signals}}
+    input  UDP_IN ,
+    output UDP_OUT,
+
+    //# {{power|Power}}
+    input  VPWR   ,
+    input  VGND
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_PWRGOOD_PP_PG_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A41OI_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__A41OI_PP_BLACKBOX_V
+
+/**
+ * a41oi: 4-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a41oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A41OI_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__XOR3_V
+`define SKY130_FD_SC_LS__XOR3_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ *       X = A ^ B ^ C
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__xor3.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__xor3.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__xor3.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__xor3.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XOR3_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A21OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__A21OI_BEHAVIORAL_PP_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a21oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A1, A2                );
+    nor                                nor0        (nor0_out_Y       , B1, and0_out          );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21OI_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__MAJ3_SYMBOL_V
+`define SKY130_FD_SC_LS__MAJ3_SYMBOL_V
+
+/**
+ * maj3: 3-input majority vote.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__maj3 (
+    //# {{data|Data Signals}}
+    input  A,
+    input  B,
+    input  C,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MAJ3_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DFBBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__DFBBP_FUNCTIONAL_PP_V
+
+/**
+ * dfbbp: Delay flop, inverted set, inverted reset,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ls__udp_dff_nsr_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dfbbp (
+    Q      ,
+    Q_N    ,
+    D      ,
+    CLK    ,
+    SET_B  ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  CLK    ;
+    input  SET_B  ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire RESET;
+    wire SET  ;
+    wire buf_Q;
+
+    //                                   Delay       Name  Output  Other arguments
+    not                                              not0 (RESET , RESET_B                         );
+    not                                              not1 (SET   , SET_B                           );
+    sky130_fd_sc_ls__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D, , VPWR, VGND);
+    buf                                              buf0 (Q     , buf_Q                           );
+    not                                              not2 (Q_N   , buf_Q                           );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFBBP_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__XOR3_SYMBOL_V
+`define SKY130_FD_SC_LS__XOR3_SYMBOL_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ *       X = A ^ B ^ C
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__xor3 (
+    //# {{data|Data Signals}}
+    input  A,
+    input  B,
+    input  C,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XOR3_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O32A_2_V
+`define SKY130_FD_SC_LS__O32A_2_V
+
+/**
+ * o32a: 3-input OR and 2-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog wrapper for o32a with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o32a.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o32a_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o32a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o32a_2 (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o32a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O32A_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A211OI_1_V
+`define SKY130_FD_SC_LS__A211OI_1_V
+
+/**
+ * a211oi: 2-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | B1 | C1)
+ *
+ * Verilog wrapper for a211oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a211oi.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a211oi_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a211oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a211oi_1 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a211oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A211OI_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DECAPHE_4_V
+`define SKY130_FD_SC_LS__DECAPHE_4_V
+
+/**
+ * decaphe: Shielded Decoupling capacitance filler.
+ *
+ * Verilog wrapper for decaphe with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__decaphe.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__decaphe_4 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+    sky130_fd_sc_ls__decaphe base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__decaphe_4 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__decaphe base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DECAPHE_4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+( negedge SET_B => ( Q -: SET_B ) ) = 0:0:0 ;  // delay is tris
+( negedge SET_B => ( Q_N +: SET_B ) ) = 0:0:0 ;  // delay is tris
+( posedge CLK => ( Q : CLK ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall
+( posedge CLK => ( Q_N : CLK ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall
+$recrem ( posedge SET_B , posedge CLK , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , SETB_delayed , CLK_delayed ) ;
+$setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , CLK_delayed , D_delayed ) ;
+$setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , CLK_delayed , D_delayed ) ;
+$width ( posedge CLK &&& COND1 , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( negedge CLK &&& COND1 , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( negedge SET_B &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__XNOR3_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__XNOR3_FUNCTIONAL_PP_V
+
+/**
+ * xnor3: 3-input exclusive NOR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__xnor3 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire xnor0_out_X      ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    xnor                               xnor0       (xnor0_out_X      , A, B, C                );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xnor0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XNOR3_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A211OI_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__A211OI_PP_BLACKBOX_V
+
+/**
+ * a211oi: 2-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | B1 | C1)
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a211oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A211OI_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLRTP_SYMBOL_V
+`define SKY130_FD_SC_LS__DLRTP_SYMBOL_V
+
+/**
+ * dlrtp: Delay latch, inverted reset, non-inverted enable,
+ *        single output.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlrtp (
+    //# {{data|Data Signals}}
+    input  D      ,
+    output Q      ,
+
+    //# {{control|Control Signals}}
+    input  RESET_B,
+
+    //# {{clocks|Clocking}}
+    input  GATE
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRTP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SDFRBP_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__SDFRBP_BEHAVIORAL_V
+
+/**
+ * sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v""
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+
+`celldefine
+module sky130_fd_sc_ls__sdfrbp (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q          ;
+    wire RESET          ;
+    wire mux_out        ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire SCD_delayed    ;
+    wire SCE_delayed    ;
+    wire RESET_B_delayed;
+    wire CLK_delayed    ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+    wire cond2          ;
+    wire cond3          ;
+    wire cond4          ;
+
+    //                                  Name       Output   Other arguments
+    not                                 not0      (RESET  , RESET_B_delayed                                  );
+    sky130_fd_sc_ls__udp_mux_2to1       mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed              );
+    sky130_fd_sc_ls__udp_dff$PR_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    assign cond0 = ( ( RESET_B_delayed === 1\'b1 ) && awake );
+    assign cond1 = ( ( SCE_delayed === 1\'b0 ) && cond0 );
+    assign cond2 = ( ( SCE_delayed === 1\'b1 ) && cond0 );
+    assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
+    assign cond4 = ( ( RESET_B === 1\'b1 ) && awake );
+    buf                                 buf0      (Q      , buf_Q                                            );
+    not                                 not1      (Q_N    , buf_Q                                            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFRBP_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFBBN_TB_V
+`define SKY130_FD_SC_LS__SDFBBN_TB_V
+
+/**
+ * sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
+ *         clock, complementary outputs.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__sdfbbn.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg SCD;
+    reg SCE;
+    reg SET_B;
+    reg RESET_B;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Q;
+    wire Q_N;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D       = 1\'bX;
+        RESET_B = 1\'bX;
+        SCD     = 1\'bX;
+        SCE     = 1\'bX;
+        SET_B   = 1\'bX;
+        VGND    = 1\'bX;
+        VNB     = 1\'bX;
+        VPB     = 1\'bX;
+        VPWR    = 1\'bX;
+
+        #20   D       = 1\'b0;
+        #40   RESET_B = 1\'b0;
+        #60   SCD     = 1\'b0;
+        #80   SCE     = 1\'b0;
+        #100  SET_B   = 1\'b0;
+        #120  VGND    = 1\'b0;
+        #140  VNB     = 1\'b0;
+        #160  VPB     = 1\'b0;
+        #180  VPWR    = 1\'b0;
+        #200  D       = 1\'b1;
+        #220  RESET_B = 1\'b1;
+        #240  SCD     = 1\'b1;
+        #260  SCE     = 1\'b1;
+        #280  SET_B   = 1\'b1;
+        #300  VGND    = 1\'b1;
+        #320  VNB     = 1\'b1;
+        #340  VPB     = 1\'b1;
+        #360  VPWR    = 1\'b1;
+        #380  D       = 1\'b0;
+        #400  RESET_B = 1\'b0;
+        #420  SCD     = 1\'b0;
+        #440  SCE     = 1\'b0;
+        #460  SET_B   = 1\'b0;
+        #480  VGND    = 1\'b0;
+        #500  VNB     = 1\'b0;
+        #520  VPB     = 1\'b0;
+        #540  VPWR    = 1\'b0;
+        #560  VPWR    = 1\'b1;
+        #580  VPB     = 1\'b1;
+        #600  VNB     = 1\'b1;
+        #620  VGND    = 1\'b1;
+        #640  SET_B   = 1\'b1;
+        #660  SCE     = 1\'b1;
+        #680  SCD     = 1\'b1;
+        #700  RESET_B = 1\'b1;
+        #720  D       = 1\'b1;
+        #740  VPWR    = 1\'bx;
+        #760  VPB     = 1\'bx;
+        #780  VNB     = 1\'bx;
+        #800  VGND    = 1\'bx;
+        #820  SET_B   = 1\'bx;
+        #840  SCE     = 1\'bx;
+        #860  SCD     = 1\'bx;
+        #880  RESET_B = 1\'bx;
+        #900  D       = 1\'bx;
+    end
+
+    // Create a clock
+    reg CLK_N;
+    initial
+    begin
+        CLK_N = 1\'b0;
+    end
+
+    always
+    begin
+        #5 CLK_N = ~CLK_N;
+    end
+
+    sky130_fd_sc_ls__sdfbbn dut (.D(D), .SCD(SCD), .SCE(SCE), .SET_B(SET_B), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK_N(CLK_N));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFBBN_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__INV_TB_V
+`define SKY130_FD_SC_LS__INV_TB_V
+
+/**
+ * inv: Inverter.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__inv.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   VGND = 1\'b0;
+        #60   VNB  = 1\'b0;
+        #80   VPB  = 1\'b0;
+        #100  VPWR = 1\'b0;
+        #120  A    = 1\'b1;
+        #140  VGND = 1\'b1;
+        #160  VNB  = 1\'b1;
+        #180  VPB  = 1\'b1;
+        #200  VPWR = 1\'b1;
+        #220  A    = 1\'b0;
+        #240  VGND = 1\'b0;
+        #260  VNB  = 1\'b0;
+        #280  VPB  = 1\'b0;
+        #300  VPWR = 1\'b0;
+        #320  VPWR = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VNB  = 1\'b1;
+        #380  VGND = 1\'b1;
+        #400  A    = 1\'b1;
+        #420  VPWR = 1\'bx;
+        #440  VPB  = 1\'bx;
+        #460  VNB  = 1\'bx;
+        #480  VGND = 1\'bx;
+        #500  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__inv dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__INV_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND4_V
+`define SKY130_FD_SC_LS__NAND4_V
+
+/**
+ * nand4: 4-input NAND.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__nand4.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__nand4.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__nand4.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__nand4.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O311A_1_V
+`define SKY130_FD_SC_LS__O311A_1_V
+
+/**
+ * o311a: 3-input OR into 3-input AND.
+ *
+ *        X = ((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog wrapper for o311a with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o311a.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o311a_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o311a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o311a_1 (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o311a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O311A_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O2BB2AI_V
+`define SKY130_FD_SC_LS__O2BB2AI_V
+
+/**
+ * o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
+ *
+ *          Y = !(!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o2bb2ai.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o2bb2ai.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o2bb2ai.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o2bb2ai.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2BB2AI_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__XNOR2_TB_V
+`define SKY130_FD_SC_LS__XNOR2_TB_V
+
+/**
+ * xnor2: 2-input exclusive NOR.
+ *
+ *        Y = !(A ^ B)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__xnor2.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg B;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        B    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   B    = 1\'b0;
+        #60   VGND = 1\'b0;
+        #80   VNB  = 1\'b0;
+        #100  VPB  = 1\'b0;
+        #120  VPWR = 1\'b0;
+        #140  A    = 1\'b1;
+        #160  B    = 1\'b1;
+        #180  VGND = 1\'b1;
+        #200  VNB  = 1\'b1;
+        #220  VPB  = 1\'b1;
+        #240  VPWR = 1\'b1;
+        #260  A    = 1\'b0;
+        #280  B    = 1\'b0;
+        #300  VGND = 1\'b0;
+        #320  VNB  = 1\'b0;
+        #340  VPB  = 1\'b0;
+        #360  VPWR = 1\'b0;
+        #380  VPWR = 1\'b1;
+        #400  VPB  = 1\'b1;
+        #420  VNB  = 1\'b1;
+        #440  VGND = 1\'b1;
+        #460  B    = 1\'b1;
+        #480  A    = 1\'b1;
+        #500  VPWR = 1\'bx;
+        #520  VPB  = 1\'bx;
+        #540  VNB  = 1\'bx;
+        #560  VGND = 1\'bx;
+        #580  B    = 1\'bx;
+        #600  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__xnor2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XNOR2_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A2111OI_4_V
+`define SKY130_FD_SC_LS__A2111OI_4_V
+
+/**
+ * a2111oi: 2-input AND into first input of 4-input NOR.
+ *
+ *          Y = !((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog wrapper for a2111oi with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a2111oi.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a2111oi_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a2111oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a2111oi_4 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a2111oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2111OI_4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__TAP_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__TAP_BEHAVIORAL_V
+
+/**
+ * tap: Tap cell with no tap connections (no contacts on metal1).
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__tap ();
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAP_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFRTP_TB_V
+`define SKY130_FD_SC_LS__SDFRTP_TB_V
+
+/**
+ * sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
+ *         single output.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__sdfrtp.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg SCD;
+    reg SCE;
+    reg RESET_B;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Q;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D       = 1\'bX;
+        RESET_B = 1\'bX;
+        SCD     = 1\'bX;
+        SCE     = 1\'bX;
+        VGND    = 1\'bX;
+        VNB     = 1\'bX;
+        VPB     = 1\'bX;
+        VPWR    = 1\'bX;
+
+        #20   D       = 1\'b0;
+        #40   RESET_B = 1\'b0;
+        #60   SCD     = 1\'b0;
+        #80   SCE     = 1\'b0;
+        #100  VGND    = 1\'b0;
+        #120  VNB     = 1\'b0;
+        #140  VPB     = 1\'b0;
+        #160  VPWR    = 1\'b0;
+        #180  D       = 1\'b1;
+        #200  RESET_B = 1\'b1;
+        #220  SCD     = 1\'b1;
+        #240  SCE     = 1\'b1;
+        #260  VGND    = 1\'b1;
+        #280  VNB     = 1\'b1;
+        #300  VPB     = 1\'b1;
+        #320  VPWR    = 1\'b1;
+        #340  D       = 1\'b0;
+        #360  RESET_B = 1\'b0;
+        #380  SCD     = 1\'b0;
+        #400  SCE     = 1\'b0;
+        #420  VGND    = 1\'b0;
+        #440  VNB     = 1\'b0;
+        #460  VPB     = 1\'b0;
+        #480  VPWR    = 1\'b0;
+        #500  VPWR    = 1\'b1;
+        #520  VPB     = 1\'b1;
+        #540  VNB     = 1\'b1;
+        #560  VGND    = 1\'b1;
+        #580  SCE     = 1\'b1;
+        #600  SCD     = 1\'b1;
+        #620  RESET_B = 1\'b1;
+        #640  D       = 1\'b1;
+        #660  VPWR    = 1\'bx;
+        #680  VPB     = 1\'bx;
+        #700  VNB     = 1\'bx;
+        #720  VGND    = 1\'bx;
+        #740  SCE     = 1\'bx;
+        #760  SCD     = 1\'bx;
+        #780  RESET_B = 1\'bx;
+        #800  D       = 1\'bx;
+    end
+
+    // Create a clock
+    reg CLK;
+    initial
+    begin
+        CLK = 1\'b0;
+    end
+
+    always
+    begin
+        #5 CLK = ~CLK;
+    end
+
+    sky130_fd_sc_ls__sdfrtp dut (.D(D), .SCD(SCD), .SCE(SCE), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFRTP_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A41O_SYMBOL_V
+`define SKY130_FD_SC_LS__A41O_SYMBOL_V
+
+/**
+ * a41o: 4-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a41o (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  A3,
+    input  A4,
+    input  B1,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A41O_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__BUF_8_V
+`define SKY130_FD_SC_LS__BUF_8_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog wrapper for buf with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__buf.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__buf_8 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__buf base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__buf_8 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__buf base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__BUF_8_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLCLKP_2_V
+`define SKY130_FD_SC_LS__DLCLKP_2_V
+
+/**
+ * dlclkp: Clock gate.
+ *
+ * Verilog wrapper for dlclkp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dlclkp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dlclkp_2 (
+    GCLK,
+    GATE,
+    CLK ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output GCLK;
+    input  GATE;
+    input  CLK ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__dlclkp base (
+        .GCLK(GCLK),
+        .GATE(GATE),
+        .CLK(CLK),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dlclkp_2 (
+    GCLK,
+    GATE,
+    CLK
+);
+
+    output GCLK;
+    input  GATE;
+    input  CLK ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__dlclkp base (
+        .GCLK(GCLK),
+        .GATE(GATE),
+        .CLK(CLK)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLCLKP_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__BUF_SYMBOL_V
+`define SKY130_FD_SC_LS__BUF_SYMBOL_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__buf (
+    //# {{data|Data Signals}}
+    input  A,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__BUF_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD1_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__CLKDLYINV3SD1_PP_BLACKBOX_V
+
+/**
+ * clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
+ *                stage gate.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__clkdlyinv3sd1 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV3SD1_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NAND4_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__NAND4_FUNCTIONAL_V
+
+/**
+ * nand4: 4-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__nand4 (
+    Y,
+    A,
+    B,
+    C,
+    D
+);
+
+    // Module ports
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Local signals
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    nand nand0 (nand0_out_Y, D, C, B, A     );
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND4_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NOR4BB_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__NOR4BB_BEHAVIORAL_PP_V
+
+/**
+ * nor4bb: 4-input NOR, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__nor4bb (
+    Y   ,
+    A   ,
+    B   ,
+    C_N ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nor0_out         ;
+    wire and0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nor                                nor0        (nor0_out         , A, B                  );
+    and                                and0        (and0_out_Y       , nor0_out, C_N, D_N    );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR4BB_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O32AI_4_V
+`define SKY130_FD_SC_LS__O32AI_4_V
+
+/**
+ * o32ai: 3-input OR and 2-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog wrapper for o32ai with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o32ai.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o32ai_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o32ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o32ai_4 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o32ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O32AI_4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O21BAI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__O21BAI_FUNCTIONAL_PP_V
+
+/**
+ * o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
+ *         inverted.
+ *
+ *         Y = !((A1 | A2) & !B1_N)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__o21bai (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire b                ;
+    wire or0_out          ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (b                , B1_N                   );
+    or                                 or0         (or0_out          , A2, A1                 );
+    nand                               nand0       (nand0_out_Y      , b, or0_out             );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21BAI_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__AND4B_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__AND4B_BEHAVIORAL_PP_V
+
+/**
+ * and4b: 4-input AND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__and4b (
+    X   ,
+    A_N ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , A_N                   );
+    and                                and0        (and0_out_X       , not0_out, B, C, D     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND4B_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLYGATE4SD2_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__DLYGATE4SD2_BEHAVIORAL_V
+
+/**
+ * dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__dlygate4sd2 (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYGATE4SD2_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A311O_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__A311O_BEHAVIORAL_PP_V
+
+/**
+ * a311o: 3-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a311o (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A3, A1, A2           );
+    or                                 or0         (or0_out_X        , and0_out, C1, B1     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A311O_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A2111O_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__A2111O_BEHAVIORAL_PP_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ *         X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a2111o (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A1, A2               );
+    or                                 or0         (or0_out_X        , C1, B1, and0_out, D1 );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2111O_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR2_4_V
+`define SKY130_FD_SC_LS__NOR2_4_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog wrapper for nor2 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nor2.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor2_4 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nor2 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor2_4 (
+    Y,
+    A,
+    B
+);
+
+    output Y;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nor2 base (
+        .Y(Y),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR2_4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__CLKINV_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__CLKINV_FUNCTIONAL_PP_V
+
+/**
+ * clkinv: Clock tree inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__clkinv (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out_Y       , A                     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKINV_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DFF_P_TB_V
+`define SKY130_FD_SC_LS__UDP_DFF_P_TB_V
+
+/**
+ * udp_dff$P: Positive edge triggered D flip-flop (Q output UDP).
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__udp_dff_p.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+
+    // Outputs are wires
+    wire Q;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D = 1\'bX;
+
+        #20   D = 1\'b0;
+        #40   D = 1\'b1;
+        #60   D = 1\'b0;
+        #80   D = 1\'b1;
+        #100  D = 1\'bx;
+    end
+
+    // Create a clock
+    reg CLK;
+    initial
+    begin
+        CLK = 1\'b0;
+    end
+
+    always
+    begin
+        #5 CLK = ~CLK;
+    end
+
+    sky130_fd_sc_ls__udp_dff$P dut (.D(D), .Q(Q), .CLK(CLK));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DFF_P_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND3B_SYMBOL_V
+`define SKY130_FD_SC_LS__NAND3B_SYMBOL_V
+
+/**
+ * nand3b: 3-input NAND, first input inverted.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nand3b (
+    //# {{data|Data Signals}}
+    input  A_N,
+    input  B  ,
+    input  C  ,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND3B_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__BUFBUF_BLACKBOX_V
+`define SKY130_FD_SC_LS__BUFBUF_BLACKBOX_V
+
+/**
+ * bufbuf: Double buffer.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__bufbuf (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__BUFBUF_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLYMETAL6S2S_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__DLYMETAL6S2S_BEHAVIORAL_V
+
+/**
+ * dlymetal6s2s: 6-inverter delay with output from 2nd stage on
+ *               horizontal route.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__dlymetal6s2s (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYMETAL6S2S_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A32OI_SYMBOL_V
+`define SKY130_FD_SC_LS__A32OI_SYMBOL_V
+
+/**
+ * a32oi: 3-input AND into first input, and 2-input AND into
+ *        2nd input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a32oi (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  A3,
+    input  B1,
+    input  B2,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A32OI_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__TAP_SYMBOL_V
+`define SKY130_FD_SC_LS__TAP_SYMBOL_V
+
+/**
+ * tap: Tap cell with no tap connections (no contacts on metal1).
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__tap ();
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFBBP_1_V
+`define SKY130_FD_SC_LS__DFBBP_1_V
+
+/**
+ * dfbbp: Delay flop, inverted set, inverted reset,
+ *        complementary outputs.
+ *
+ * Verilog wrapper for dfbbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dfbbp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dfbbp_1 (
+    Q      ,
+    Q_N    ,
+    D      ,
+    CLK    ,
+    SET_B  ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  CLK    ;
+    input  SET_B  ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_ls__dfbbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .D(D),
+        .CLK(CLK),
+        .SET_B(SET_B),
+        .RESET_B(RESET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dfbbp_1 (
+    Q      ,
+    Q_N    ,
+    D      ,
+    CLK    ,
+    SET_B  ,
+    RESET_B
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  CLK    ;
+    input  SET_B  ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__dfbbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .D(D),
+        .CLK(CLK),
+        .SET_B(SET_B),
+        .RESET_B(RESET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFBBP_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND4BB_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__NAND4BB_PP_SYMBOL_V
+
+/**
+ * nand4bb: 4-input NAND, first two inputs inverted.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nand4bb (
+    //# {{data|Data Signals}}
+    input  A_N ,
+    input  B_N ,
+    input  C   ,
+    input  D   ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND4BB_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O311AI_TB_V
+`define SKY130_FD_SC_LS__O311AI_TB_V
+
+/**
+ * o311ai: 3-input OR into 3-input NAND.
+ *
+ *         Y = !((A1 | A2 | A3) & B1 & C1)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o311ai.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg A3;
+    reg B1;
+    reg C1;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        A3   = 1\'bX;
+        B1   = 1\'bX;
+        C1   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   A3   = 1\'b0;
+        #80   B1   = 1\'b0;
+        #100  C1   = 1\'b0;
+        #120  VGND = 1\'b0;
+        #140  VNB  = 1\'b0;
+        #160  VPB  = 1\'b0;
+        #180  VPWR = 1\'b0;
+        #200  A1   = 1\'b1;
+        #220  A2   = 1\'b1;
+        #240  A3   = 1\'b1;
+        #260  B1   = 1\'b1;
+        #280  C1   = 1\'b1;
+        #300  VGND = 1\'b1;
+        #320  VNB  = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VPWR = 1\'b1;
+        #380  A1   = 1\'b0;
+        #400  A2   = 1\'b0;
+        #420  A3   = 1\'b0;
+        #440  B1   = 1\'b0;
+        #460  C1   = 1\'b0;
+        #480  VGND = 1\'b0;
+        #500  VNB  = 1\'b0;
+        #520  VPB  = 1\'b0;
+        #540  VPWR = 1\'b0;
+        #560  VPWR = 1\'b1;
+        #580  VPB  = 1\'b1;
+        #600  VNB  = 1\'b1;
+        #620  VGND = 1\'b1;
+        #640  C1   = 1\'b1;
+        #660  B1   = 1\'b1;
+        #680  A3   = 1\'b1;
+        #700  A2   = 1\'b1;
+        #720  A1   = 1\'b1;
+        #740  VPWR = 1\'bx;
+        #760  VPB  = 1\'bx;
+        #780  VNB  = 1\'bx;
+        #800  VGND = 1\'bx;
+        #820  C1   = 1\'bx;
+        #840  B1   = 1\'bx;
+        #860  A3   = 1\'bx;
+        #880  A2   = 1\'bx;
+        #900  A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__o311ai dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O311AI_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND3_1_V
+`define SKY130_FD_SC_LS__AND3_1_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog wrapper for and3 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__and3.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__and3_1 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__and3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__and3_1 (
+    X,
+    A,
+    B,
+    C
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__and3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND3_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__CLKBUF_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__CLKBUF_BEHAVIORAL_V
+
+/**
+ * clkbuf: Clock tree buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__clkbuf (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKBUF_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DIODE_BLACKBOX_V
+`define SKY130_FD_SC_LS__DIODE_BLACKBOX_V
+
+/**
+ * diode: Antenna tie-down diode.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__diode (
+    DIODE
+);
+
+    input DIODE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DIODE_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFSTP_SYMBOL_V
+`define SKY130_FD_SC_LS__DFSTP_SYMBOL_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dfstp (
+    //# {{data|Data Signals}}
+    input  D    ,
+    output Q    ,
+
+    //# {{control|Control Signals}}
+    input  SET_B,
+
+    //# {{clocks|Clocking}}
+    input  CLK
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFSTP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A41OI_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__A41OI_FUNCTIONAL_V
+
+/**
+ * a41oi: 4-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a41oi (
+    Y ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Local signals
+    wire and0_out  ;
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out  , A1, A2, A3, A4 );
+    nor nor0 (nor0_out_Y, B1, and0_out   );
+    buf buf0 (Y         , nor0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A41OI_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NOR3B_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__NOR3B_FUNCTIONAL_V
+
+/**
+ * nor3b: 3-input NOR, first input inverted.
+ *
+ *        Y = (!(A | B)) & !C)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__nor3b (
+    Y  ,
+    A  ,
+    B  ,
+    C_N
+);
+
+    // Module ports
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+
+    // Local signals
+    wire nor0_out  ;
+    wire and0_out_Y;
+
+    //  Name  Output      Other arguments
+    nor nor0 (nor0_out  , A, B           );
+    and and0 (and0_out_Y, C_N, nor0_out  );
+    buf buf0 (Y         , and0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR3B_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A1 -=> Y) = (0:0:0,0:0:0);
+(A2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&!C1&!D1)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&!C1&!D1)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&!C1&!D1)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&!B1&!D1)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&!B1&!D1)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&!B1&!D1)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&!B1&!C1)) (D1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&!B1&!C1)) (D1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&!B1&!C1)) (D1 -=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A +=> X) = (0:0:0,0:0:0);
+(B +=> X) = (0:0:0,0:0:0);
+(C_N -=> X) = (0:0:0,0:0:0);
+(D_N -=> X) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__HA_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__HA_PP_BLACKBOX_V
+
+/**
+ * ha: Half adder.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__ha (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__HA_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A32OI_4_V
+`define SKY130_FD_SC_LS__A32OI_4_V
+
+/**
+ * a32oi: 3-input AND into first input, and 2-input AND into
+ *        2nd input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog wrapper for a32oi with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a32oi.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a32oi_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a32oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a32oi_4 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a32oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A32OI_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFRBP_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__SDFRBP_PP_SYMBOL_V
+
+/**
+ * sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sdfrbp (
+    //# {{data|Data Signals}}
+    input  D      ,
+    output Q      ,
+    output Q_N    ,
+
+    //# {{control|Control Signals}}
+    input  RESET_B,
+
+    //# {{scanchain|Scan Chain}}
+    input  SCD    ,
+    input  SCE    ,
+
+    //# {{clocks|Clocking}}
+    input  CLK    ,
+
+    //# {{power|Power}}
+    input  VPB    ,
+    input  VPWR   ,
+    input  VGND   ,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFRBP_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__FAHCIN_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__FAHCIN_FUNCTIONAL_V
+
+/**
+ * fahcin: Full adder, inverted carry in.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__fahcin (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CIN
+);
+
+    // Module ports
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CIN ;
+
+    // Local signals
+    wire ci          ;
+    wire xor0_out_SUM;
+    wire a_b         ;
+    wire a_ci        ;
+    wire b_ci        ;
+    wire or0_out_COUT;
+
+    //  Name  Output        Other arguments
+    not not0 (ci          , CIN            );
+    xor xor0 (xor0_out_SUM, A, B, ci       );
+    buf buf0 (SUM         , xor0_out_SUM   );
+    and and0 (a_b         , A, B           );
+    and and1 (a_ci        , A, ci          );
+    and and2 (b_ci        , B, ci          );
+    or  or0  (or0_out_COUT, a_b, a_ci, b_ci);
+    buf buf1 (COUT        , or0_out_COUT   );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FAHCIN_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A22OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__A22OI_FUNCTIONAL_PP_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a22oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out        ;
+    wire nand1_out        ;
+    wire and0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out        , A2, A1                );
+    nand                               nand1       (nand1_out        , B2, B1                );
+    and                                and0        (and0_out_Y       , nand0_out, nand1_out  );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A22OI_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLYGATE4SD2_V
+`define SKY130_FD_SC_LS__DLYGATE4SD2_V
+
+/**
+ * dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlygate4sd2.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlygate4sd2.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlygate4sd2.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlygate4sd2.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYGATE4SD2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A32OI_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__A32OI_FUNCTIONAL_V
+
+/**
+ * a32oi: 3-input AND into first input, and 2-input AND into
+ *        2nd input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a32oi (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Local signals
+    wire nand0_out ;
+    wire nand1_out ;
+    wire and0_out_Y;
+
+    //   Name   Output      Other arguments
+    nand nand0 (nand0_out , A2, A1, A3          );
+    nand nand1 (nand1_out , B2, B1              );
+    and  and0  (and0_out_Y, nand0_out, nand1_out);
+    buf  buf0  (Y         , and0_out_Y          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A32OI_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__TAPVGND_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__TAPVGND_BEHAVIORAL_V
+
+/**
+ * tapvgnd: Tap cell with tap to ground, isolated power connection 1
+ *          row down.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__tapvgnd ();
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPVGND_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLRTN_SYMBOL_V
+`define SKY130_FD_SC_LS__DLRTN_SYMBOL_V
+
+/**
+ * dlrtn: Delay latch, inverted reset, inverted enable, single output.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlrtn (
+    //# {{data|Data Signals}}
+    input  D      ,
+    output Q      ,
+
+    //# {{control|Control Signals}}
+    input  RESET_B,
+
+    //# {{clocks|Clocking}}
+    input  GATE_N
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRTN_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NOR3_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__NOR3_BEHAVIORAL_PP_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ *       Y = !(A | B | C | !D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__nor3 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nor                                nor0        (nor0_out_Y       , C, A, B               );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR3_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__OR4B_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__OR4B_BEHAVIORAL_PP_V
+
+/**
+ * or4b: 4-input OR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__or4b (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , D_N                  );
+    or                                 or0         (or0_out_X        , not0_out, C, B, A    );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR4B_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A21OI_1_V
+`define SKY130_FD_SC_LS__A21OI_1_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | B1)
+ *
+ * Verilog wrapper for a21oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a21oi.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a21oi_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a21oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a21oi_1 (
+    Y ,
+    A1,
+    A2,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a21oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21OI_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O311A_BLACKBOX_V
+`define SKY130_FD_SC_LS__O311A_BLACKBOX_V
+
+/**
+ * o311a: 3-input OR into 3-input AND.
+ *
+ *        X = ((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o311a (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O311A_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A2111O_V
+`define SKY130_FD_SC_LS__A2111O_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ *         X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a2111o.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a2111o.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a2111o.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a2111o.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2111O_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A22O_2_V
+`define SKY130_FD_SC_LS__A22O_2_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ *       X = ((A1 & A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a22o with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a22o.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a22o_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a22o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a22o_2 (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a22o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A22O_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFBBN_V
+`define SKY130_FD_SC_LS__DFBBN_V
+
+/**
+ * dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
+ *        complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dfbbn.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dfbbn.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dfbbn.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dfbbn.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFBBN_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKBUF_SYMBOL_V
+`define SKY130_FD_SC_LS__CLKBUF_SYMBOL_V
+
+/**
+ * clkbuf: Clock tree buffer.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__clkbuf (
+    //# {{data|Data Signals}}
+    input  A,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKBUF_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A222OI_V
+`define SKY130_FD_SC_LS__A222OI_V
+
+/**
+ * a222oi: 2-input AND into all inputs of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a222oi.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a222oi.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a222oi.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a222oi.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A222OI_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLXTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__DLXTP_BEHAVIORAL_PP_V
+
+/**
+ * dlxtp: Delay latch, non-inverted enable, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlxtp (
+    Q   ,
+    D   ,
+    GATE,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    input  D   ;
+    input  GATE;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q       ;
+    wire GATE_delayed;
+    wire D_delayed   ;
+    reg  notifier    ;
+    wire awake       ;
+
+    //                                    Name     Output  Other arguments
+    sky130_fd_sc_ls__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
+    buf                                   buf0    (Q     , buf_Q                                        );
+    assign awake = ( VPWR === 1\'b1 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXTP_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__OR3_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__OR3_BEHAVIORAL_V
+
+/**
+ * or3: 3-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__or3 (
+    X,
+    A,
+    B,
+    C
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    or  or0  (or0_out_X, B, A, C        );
+    buf buf0 (X        , or0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR3_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O31AI_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__O31AI_FUNCTIONAL_V
+
+/**
+ * o31ai: 3-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__o31ai (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Local signals
+    wire or0_out    ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    or   or0   (or0_out    , A2, A1, A3     );
+    nand nand0 (nand0_out_Y, B1, or0_out    );
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O31AI_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLRBP_V
+`define SKY130_FD_SC_LS__DLRBP_V
+
+/**
+ * dlrbp: Delay latch, inverted reset, non-inverted enable,
+ *        complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlrbp.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlrbp.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlrbp.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlrbp.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRBP_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD1_SYMBOL_V
+`define SKY130_FD_SC_LS__CLKDLYINV5SD1_SYMBOL_V
+
+/**
+ * clkdlyinv5sd1: Clock Delay Inverter 5-stage 0.15um length inner
+ *                stage gate.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__clkdlyinv5sd1 (
+    //# {{data|Data Signals}}
+    input  A,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV5SD1_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NOR2_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__NOR2_FUNCTIONAL_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__nor2 (
+    Y,
+    A,
+    B
+);
+
+    // Module ports
+    output Y;
+    input  A;
+    input  B;
+
+    // Local signals
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    nor nor0 (nor0_out_Y, A, B           );
+    buf buf0 (Y         , nor0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR2_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFSTP_BLACKBOX_V
+`define SKY130_FD_SC_LS__DFSTP_BLACKBOX_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dfstp (
+    Q    ,
+    CLK  ,
+    D    ,
+    SET_B
+);
+
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFSTP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLXTN_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__DLXTN_BEHAVIORAL_PP_V
+
+/**
+ * dlxtn: Delay latch, inverted enable, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlxtn (
+    Q     ,
+    D     ,
+    GATE_N,
+    VPWR  ,
+    VGND  ,
+    VPB   ,
+    VNB
+);
+
+    // Module ports
+    output Q     ;
+    input  D     ;
+    input  GATE_N;
+    input  VPWR  ;
+    input  VGND  ;
+    input  VPB   ;
+    input  VNB   ;
+
+    // Local signals
+    wire GATE          ;
+    wire buf_Q         ;
+    wire GATE_N_delayed;
+    wire D_delayed     ;
+    reg  notifier      ;
+    wire awake         ;
+
+    //                                    Name     Output  Other arguments
+    not                                   not0    (GATE  , GATE_N_delayed                       );
+    sky130_fd_sc_ls__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
+    buf                                   buf0    (Q     , buf_Q                                );
+    assign awake = ( VPWR === 1\'b1 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXTN_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DECAPHE_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__DECAPHE_PP_BLACKBOX_V
+
+/**
+ * decaphe: Shielded Decoupling capacitance filler.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__decaphe (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DECAPHE_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLYMETAL6S4S_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__DLYMETAL6S4S_PP_SYMBOL_V
+
+/**
+ * dlymetal6s4s: 6-inverter delay with output from 4th inverter on
+ *               horizontal route.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlymetal6s4s (
+    //# {{data|Data Signals}}
+    input  A   ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYMETAL6S4S_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR2B_BLACKBOX_V
+`define SKY130_FD_SC_LS__NOR2B_BLACKBOX_V
+
+/**
+ * nor2b: 2-input NOR, first input inverted.
+ *
+ *        Y = !(A | B | C | !D)
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nor2b (
+    Y  ,
+    A  ,
+    B_N
+);
+
+    output Y  ;
+    input  A  ;
+    input  B_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR2B_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A +=> COUT) = (0:0:0,0:0:0);
+(B +=> COUT) = (0:0:0,0:0:0);
+if ((!B)) (A +=> SUM) = (0:0:0,0:0:0);
+if ((B)) (A -=> SUM) = (0:0:0,0:0:0);
+if ((!A)) (B +=> SUM) = (0:0:0,0:0:0);
+if ((A)) (B -=> SUM) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFRTN_BLACKBOX_V
+`define SKY130_FD_SC_LS__DFRTN_BLACKBOX_V
+
+/**
+ * dfrtn: Delay flop, inverted reset, inverted clock,
+ *        complementary outputs.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dfrtn (
+    Q      ,
+    CLK_N  ,
+    D      ,
+    RESET_B
+);
+
+    output Q      ;
+    input  CLK_N  ;
+    input  D      ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFRTN_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A41O_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__A41O_FUNCTIONAL_PP_V
+
+/**
+ * a41o: 4-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a41o (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A1, A2, A3, A4       );
+    or                                 or0         (or0_out_X        , and0_out, B1         );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A41O_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__XOR3_2_V
+`define SKY130_FD_SC_LS__XOR3_2_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ *       X = A ^ B ^ C
+ *
+ * Verilog wrapper for xor3 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__xor3.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__xor3_2 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__xor3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__xor3_2 (
+    X,
+    A,
+    B,
+    C
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__xor3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XOR3_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__INV_BLACKBOX_V
+`define SKY130_FD_SC_LS__INV_BLACKBOX_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__inv (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__INV_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__FAHCIN_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__FAHCIN_BEHAVIORAL_PP_V
+
+/**
+ * fahcin: Full adder, inverted carry in.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__fahcin (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CIN ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CIN ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire ci                  ;
+    wire xor0_out_SUM        ;
+    wire pwrgood_pp0_out_SUM ;
+    wire a_b                 ;
+    wire a_ci                ;
+    wire b_ci                ;
+    wire or0_out_COUT        ;
+    wire pwrgood_pp1_out_COUT;
+
+    //                                 Name         Output                Other arguments
+    not                                not0        (ci                  , CIN                     );
+    xor                                xor0        (xor0_out_SUM        , A, B, ci                );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
+    buf                                buf0        (SUM                 , pwrgood_pp0_out_SUM     );
+    and                                and0        (a_b                 , A, B                    );
+    and                                and1        (a_ci                , A, ci                   );
+    and                                and2        (b_ci                , B, ci                   );
+    or                                 or0         (or0_out_COUT        , a_b, a_ci, b_ci         );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
+    buf                                buf1        (COUT                , pwrgood_pp1_out_COUT    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FAHCIN_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__FA_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__FA_FUNCTIONAL_PP_V
+
+/**
+ * fa: Full adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__fa (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CIN ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CIN ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out             ;
+    wire and0_out            ;
+    wire and1_out            ;
+    wire and2_out            ;
+    wire nor0_out            ;
+    wire nor1_out            ;
+    wire or1_out_COUT        ;
+    wire pwrgood_pp0_out_COUT;
+    wire or2_out_SUM         ;
+    wire pwrgood_pp1_out_SUM ;
+
+    //                                 Name         Output                Other arguments
+    or                                 or0         (or0_out             , CIN, B                  );
+    and                                and0        (and0_out            , or0_out, A              );
+    and                                and1        (and1_out            , B, CIN                  );
+    or                                 or1         (or1_out_COUT        , and1_out, and0_out      );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, or1_out_COUT, VPWR, VGND);
+    buf                                buf0        (COUT                , pwrgood_pp0_out_COUT    );
+    and                                and2        (and2_out            , CIN, A, B               );
+    nor                                nor0        (nor0_out            , A, or0_out              );
+    nor                                nor1        (nor1_out            , nor0_out, COUT          );
+    or                                 or2         (or2_out_SUM         , nor1_out, and2_out      );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , or2_out_SUM, VPWR, VGND );
+    buf                                buf1        (SUM                 , pwrgood_pp1_out_SUM     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FA_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A2BB2OI_SYMBOL_V
+`define SKY130_FD_SC_LS__A2BB2OI_SYMBOL_V
+
+/**
+ * a2bb2oi: 2-input AND, both inputs inverted, into first input, and
+ *          2-input AND into 2nd input of 2-input NOR.
+ *
+ *          Y = !((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a2bb2oi (
+    //# {{data|Data Signals}}
+    input  A1_N,
+    input  A2_N,
+    input  B1  ,
+    input  B2  ,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2BB2OI_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A22OI_BLACKBOX_V
+`define SKY130_FD_SC_LS__A22OI_BLACKBOX_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a22oi (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A22OI_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR3B_V
+`define SKY130_FD_SC_LS__NOR3B_V
+
+/**
+ * nor3b: 3-input NOR, first input inverted.
+ *
+ *        Y = (!(A | B)) & !C)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__nor3b.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__nor3b.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__nor3b.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__nor3b.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR3B_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLRTP_TB_V
+`define SKY130_FD_SC_LS__DLRTP_TB_V
+
+/**
+ * dlrtp: Delay latch, inverted reset, non-inverted enable,
+ *        single output.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dlrtp.v""
+
+module top();
+
+    // Inputs are registered
+    reg RESET_B;
+    reg D;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Q;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D       = 1\'bX;
+        RESET_B = 1\'bX;
+        VGND    = 1\'bX;
+        VNB     = 1\'bX;
+        VPB     = 1\'bX;
+        VPWR    = 1\'bX;
+
+        #20   D       = 1\'b0;
+        #40   RESET_B = 1\'b0;
+        #60   VGND    = 1\'b0;
+        #80   VNB     = 1\'b0;
+        #100  VPB     = 1\'b0;
+        #120  VPWR    = 1\'b0;
+        #140  D       = 1\'b1;
+        #160  RESET_B = 1\'b1;
+        #180  VGND    = 1\'b1;
+        #200  VNB     = 1\'b1;
+        #220  VPB     = 1\'b1;
+        #240  VPWR    = 1\'b1;
+        #260  D       = 1\'b0;
+        #280  RESET_B = 1\'b0;
+        #300  VGND    = 1\'b0;
+        #320  VNB     = 1\'b0;
+        #340  VPB     = 1\'b0;
+        #360  VPWR    = 1\'b0;
+        #380  VPWR    = 1\'b1;
+        #400  VPB     = 1\'b1;
+        #420  VNB     = 1\'b1;
+        #440  VGND    = 1\'b1;
+        #460  RESET_B = 1\'b1;
+        #480  D       = 1\'b1;
+        #500  VPWR    = 1\'bx;
+        #520  VPB     = 1\'bx;
+        #540  VNB     = 1\'bx;
+        #560  VGND    = 1\'bx;
+        #580  RESET_B = 1\'bx;
+        #600  D       = 1\'bx;
+    end
+
+    // Create a clock
+    reg GATE;
+    initial
+    begin
+        GATE = 1\'b0;
+    end
+
+    always
+    begin
+        #5 GATE = ~GATE;
+    end
+
+    sky130_fd_sc_ls__dlrtp dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .GATE(GATE));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRTP_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NAND3_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__NAND3_BEHAVIORAL_V
+
+/**
+ * nand3: 3-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__nand3 (
+    Y,
+    A,
+    B,
+    C
+);
+
+    // Module ports
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    nand nand0 (nand0_out_Y, B, A, C        );
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND3_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__TAPMET1_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__TAPMET1_PP_SYMBOL_V
+
+/**
+ * tapmet1: Tap cell with isolated power and ground connections.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__tapmet1 (
+    //# {{power|Power}}
+    input VPB ,
+    input VPWR,
+    input VGND,
+    input VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPMET1_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A21OI_TB_V
+`define SKY130_FD_SC_LS__A21OI_TB_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | B1)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a21oi.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg B1;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        B1   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   B1   = 1\'b0;
+        #80   VGND = 1\'b0;
+        #100  VNB  = 1\'b0;
+        #120  VPB  = 1\'b0;
+        #140  VPWR = 1\'b0;
+        #160  A1   = 1\'b1;
+        #180  A2   = 1\'b1;
+        #200  B1   = 1\'b1;
+        #220  VGND = 1\'b1;
+        #240  VNB  = 1\'b1;
+        #260  VPB  = 1\'b1;
+        #280  VPWR = 1\'b1;
+        #300  A1   = 1\'b0;
+        #320  A2   = 1\'b0;
+        #340  B1   = 1\'b0;
+        #360  VGND = 1\'b0;
+        #380  VNB  = 1\'b0;
+        #400  VPB  = 1\'b0;
+        #420  VPWR = 1\'b0;
+        #440  VPWR = 1\'b1;
+        #460  VPB  = 1\'b1;
+        #480  VNB  = 1\'b1;
+        #500  VGND = 1\'b1;
+        #520  B1   = 1\'b1;
+        #540  A2   = 1\'b1;
+        #560  A1   = 1\'b1;
+        #580  VPWR = 1\'bx;
+        #600  VPB  = 1\'bx;
+        #620  VNB  = 1\'bx;
+        #640  VGND = 1\'bx;
+        #660  B1   = 1\'bx;
+        #680  A2   = 1\'bx;
+        #700  A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__a21oi dut (.A1(A1), .A2(A2), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21OI_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFXTP_BLACKBOX_V
+`define SKY130_FD_SC_LS__SDFXTP_BLACKBOX_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sdfxtp (
+    Q  ,
+    CLK,
+    D  ,
+    SCD,
+    SCE
+);
+
+    output Q  ;
+    input  CLK;
+    input  D  ;
+    input  SCD;
+    input  SCE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFXTP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__MUX2_V
+`define SKY130_FD_SC_LS__MUX2_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__mux2.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__mux2.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__mux2.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__mux2.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MUX2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD1_V
+`define SKY130_FD_SC_LS__CLKDLYINV3SD1_V
+
+/**
+ * clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
+ *                stage gate.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__clkdlyinv3sd1.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__clkdlyinv3sd1.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__clkdlyinv3sd1.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__clkdlyinv3sd1.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV3SD1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__XNOR2_BLACKBOX_V
+`define SKY130_FD_SC_LS__XNOR2_BLACKBOX_V
+
+/**
+ * xnor2: 2-input exclusive NOR.
+ *
+ *        Y = !(A ^ B)
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__xnor2 (
+    Y,
+    A,
+    B
+);
+
+    output Y;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XNOR2_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NOR4B_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__NOR4B_BEHAVIORAL_PP_V
+
+/**
+ * nor4b: 4-input NOR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__nor4b (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , D_N                   );
+    nor                                nor0        (nor0_out_Y       , A, B, C, not0_out     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR4B_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__AND3_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__AND3_BEHAVIORAL_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__and3 (
+    X,
+    A,
+    B,
+    C
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out_X, C, A, B        );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND3_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__OR3_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__OR3_BEHAVIORAL_PP_V
+
+/**
+ * or3: 3-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__or3 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out_X        , B, A, C              );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR3_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O311A_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__O311A_FUNCTIONAL_PP_V
+
+/**
+ * o311a: 3-input OR into 3-input AND.
+ *
+ *        X = ((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__o311a (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1, A3            );
+    and                                and0        (and0_out_X       , or0_out, B1, C1       );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O311A_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if ((!A2_N&!B1&!B2)) (A1_N +=> Y) = (0:0:0,0:0:0);
+if ((!A2_N&!B1&B2)) (A1_N +=> Y) = (0:0:0,0:0:0);
+if ((!A2_N&B1&!B2)) (A1_N +=> Y) = (0:0:0,0:0:0);
+if ((!A1_N&!B1&!B2)) (A2_N +=> Y) = (0:0:0,0:0:0);
+if ((!A1_N&!B1&B2)) (A2_N +=> Y) = (0:0:0,0:0:0);
+if ((!A1_N&B1&!B2)) (A2_N +=> Y) = (0:0:0,0:0:0);
+if ((!A1_N&A2_N&B2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1_N&!A2_N&B2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1_N&A2_N&B2)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1_N&A2_N&B1)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((A1_N&!A2_N&B1)) (B2 -=> Y) = (0:0:0,0:0:0);
+if ((A1_N&A2_N&B1)) (B2 -=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKINV_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__CLKINV_PP_SYMBOL_V
+
+/**
+ * clkinv: Clock tree inverter.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__clkinv (
+    //# {{data|Data Signals}}
+    input  A   ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKINV_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NOR3_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__NOR3_BEHAVIORAL_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ *       Y = !(A | B | C | !D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__nor3 (
+    Y,
+    A,
+    B,
+    C
+);
+
+    // Module ports
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    nor nor0 (nor0_out_Y, C, A, B        );
+    buf buf0 (Y         , nor0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR3_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O311AI_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__O311AI_PP_BLACKBOX_V
+
+/**
+ * o311ai: 3-input OR into 3-input NAND.
+ *
+ *         Y = !((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o311ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O311AI_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__TAPVPWRVGND_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__TAPVPWRVGND_PP_SYMBOL_V
+
+/**
+ * tapvpwrvgnd: Substrate and well tap cell.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__tapvpwrvgnd (
+    //# {{power|Power}}
+    input VPB ,
+    input VPWR,
+    input VGND,
+    input VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPVPWRVGND_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A222O_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__A222O_BEHAVIORAL_PP_V
+
+/**
+ * a222o: 2-input AND into all inputs of 3-input OR.
+ *
+ *        X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a222o (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    C2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  C2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire and1_out         ;
+    wire and2_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , B1, B2                      );
+    and                                and1        (and1_out         , A1, A2                      );
+    and                                and2        (and2_out         , C1, C2                      );
+    or                                 or0         (or0_out_X        , and1_out, and0_out, and2_out);
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND       );
+    buf                                buf0        (X                , pwrgood_pp0_out_X           );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A222O_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SDFRTN_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__SDFRTN_BEHAVIORAL_V
+
+/**
+ * sdfrtn: Scan delay flop, inverted reset, inverted clock,
+ *         single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v""
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+
+`celldefine
+module sky130_fd_sc_ls__sdfrtn (
+    Q      ,
+    CLK_N  ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    input  CLK_N  ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q          ;
+    wire RESET          ;
+    wire intclk         ;
+    wire mux_out        ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire SCD_delayed    ;
+    wire SCE_delayed    ;
+    wire RESET_B_delayed;
+    wire CLK_N_delayed  ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+    wire cond2          ;
+    wire cond3          ;
+    wire cond4          ;
+
+    //                                  Name       Output   Other arguments
+    not                                 not0      (RESET  , RESET_B_delayed                             );
+    not                                 not1      (intclk , CLK_N_delayed                               );
+    sky130_fd_sc_ls__udp_mux_2to1       mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed         );
+    sky130_fd_sc_ls__udp_dff$PR_pp$PG$N dff0      (buf_Q  , mux_out, intclk, RESET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1\'b1 ) );
+    assign cond1 = ( ( SCE_delayed === 1\'b0 ) && cond0 );
+    assign cond2 = ( ( SCE_delayed === 1\'b1 ) && cond0 );
+    assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
+    assign cond4 = ( awake && ( RESET_B === 1\'b1 ) );
+    buf                                 buf0      (Q      , buf_Q                                       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFRTN_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLYMETAL6S4S_TB_V
+`define SKY130_FD_SC_LS__DLYMETAL6S4S_TB_V
+
+/**
+ * dlymetal6s4s: 6-inverter delay with output from 4th inverter on
+ *               horizontal route.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dlymetal6s4s.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   VGND = 1\'b0;
+        #60   VNB  = 1\'b0;
+        #80   VPB  = 1\'b0;
+        #100  VPWR = 1\'b0;
+        #120  A    = 1\'b1;
+        #140  VGND = 1\'b1;
+        #160  VNB  = 1\'b1;
+        #180  VPB  = 1\'b1;
+        #200  VPWR = 1\'b1;
+        #220  A    = 1\'b0;
+        #240  VGND = 1\'b0;
+        #260  VNB  = 1\'b0;
+        #280  VPB  = 1\'b0;
+        #300  VPWR = 1\'b0;
+        #320  VPWR = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VNB  = 1\'b1;
+        #380  VGND = 1\'b1;
+        #400  A    = 1\'b1;
+        #420  VPWR = 1\'bx;
+        #440  VPB  = 1\'bx;
+        #460  VNB  = 1\'bx;
+        #480  VGND = 1\'bx;
+        #500  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__dlymetal6s4s dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYMETAL6S4S_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR4_2_V
+`define SKY130_FD_SC_LS__NOR4_2_V
+
+/**
+ * nor4: 4-input NOR.
+ *
+ *       Y = !(A | B | C | D)
+ *
+ * Verilog wrapper for nor4 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nor4.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor4_2 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nor4 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor4_2 (
+    Y,
+    A,
+    B,
+    C,
+    D
+);
+
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nor4 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR4_2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A2BB2O_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__A2BB2O_BEHAVIORAL_V
+
+/**
+ * a2bb2o: 2-input AND, both inputs inverted, into first input, and
+ *         2-input AND into 2nd input of 2-input OR.
+ *
+ *         X = ((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a2bb2o (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    // Module ports
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out ;
+    wire nor0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , B1, B2            );
+    nor nor0 (nor0_out , A1_N, A2_N        );
+    or  or0  (or0_out_X, nor0_out, and0_out);
+    buf buf0 (X        , or0_out_X         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2BB2O_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A2BB2OI_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__A2BB2OI_PP_BLACKBOX_V
+
+/**
+ * a2bb2oi: 2-input AND, both inputs inverted, into first input, and
+ *          2-input AND into 2nd input of 2-input NOR.
+ *
+ *          Y = !((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a2bb2oi (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2BB2OI_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DECAPHE_6_V
+`define SKY130_FD_SC_LS__DECAPHE_6_V
+
+/**
+ * decaphe: Shielded Decoupling capacitance filler.
+ *
+ * Verilog wrapper for decaphe with size of 6 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__decaphe.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__decaphe_6 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+    sky130_fd_sc_ls__decaphe base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__decaphe_6 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__decaphe base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DECAPHE_6_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__EINVN_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__EINVN_PP_SYMBOL_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__einvn (
+    //# {{data|Data Signals}}
+    input  A   ,
+    output Z   ,
+
+    //# {{control|Control Signals}}
+    input  TE_B,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EINVN_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DECAPHE_18_V
+`define SKY130_FD_SC_LS__DECAPHE_18_V
+
+/**
+ * decaphe: Shielded Decoupling capacitance filler.
+ *
+ * Verilog wrapper for decaphe with size of 18 units (invalid?).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__decaphe.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__decaphe_18 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+    sky130_fd_sc_ls__decaphe base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__decaphe_18 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__decaphe base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DECAPHE_18_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__AND4_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__AND4_FUNCTIONAL_V
+
+/**
+ * and4: 4-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__and4 (
+    X,
+    A,
+    B,
+    C,
+    D
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Local signals
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out_X, A, B, C, D     );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND4_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O21BA_2_V
+`define SKY130_FD_SC_LS__O21BA_2_V
+
+/**
+ * o21ba: 2-input OR into first input of 2-input AND,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 | A2) & !B1_N)
+ *
+ * Verilog wrapper for o21ba with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o21ba.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o21ba_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o21ba base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o21ba_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o21ba base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21BA_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A2111OI_2_V
+`define SKY130_FD_SC_LS__A2111OI_2_V
+
+/**
+ * a2111oi: 2-input AND into first input of 4-input NOR.
+ *
+ *          Y = !((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog wrapper for a2111oi with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a2111oi.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a2111oi_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a2111oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a2111oi_2 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a2111oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2111OI_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A222OI_BLACKBOX_V
+`define SKY130_FD_SC_LS__A222OI_BLACKBOX_V
+
+/**
+ * a222oi: 2-input AND into all inputs of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a222oi (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1,
+    C2
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+    input  C2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A222OI_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O2111A_1_V
+`define SKY130_FD_SC_LS__O2111A_1_V
+
+/**
+ * o2111a: 2-input OR into first input of 4-input AND.
+ *
+ *         X = ((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog wrapper for o2111a with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o2111a.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o2111a_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o2111a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o2111a_1 (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o2111a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2111A_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND4_TB_V
+`define SKY130_FD_SC_LS__AND4_TB_V
+
+/**
+ * and4: 4-input AND.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__and4.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg B;
+    reg C;
+    reg D;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        B    = 1\'bX;
+        C    = 1\'bX;
+        D    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   B    = 1\'b0;
+        #60   C    = 1\'b0;
+        #80   D    = 1\'b0;
+        #100  VGND = 1\'b0;
+        #120  VNB  = 1\'b0;
+        #140  VPB  = 1\'b0;
+        #160  VPWR = 1\'b0;
+        #180  A    = 1\'b1;
+        #200  B    = 1\'b1;
+        #220  C    = 1\'b1;
+        #240  D    = 1\'b1;
+        #260  VGND = 1\'b1;
+        #280  VNB  = 1\'b1;
+        #300  VPB  = 1\'b1;
+        #320  VPWR = 1\'b1;
+        #340  A    = 1\'b0;
+        #360  B    = 1\'b0;
+        #380  C    = 1\'b0;
+        #400  D    = 1\'b0;
+        #420  VGND = 1\'b0;
+        #440  VNB  = 1\'b0;
+        #460  VPB  = 1\'b0;
+        #480  VPWR = 1\'b0;
+        #500  VPWR = 1\'b1;
+        #520  VPB  = 1\'b1;
+        #540  VNB  = 1\'b1;
+        #560  VGND = 1\'b1;
+        #580  D    = 1\'b1;
+        #600  C    = 1\'b1;
+        #620  B    = 1\'b1;
+        #640  A    = 1\'b1;
+        #660  VPWR = 1\'bx;
+        #680  VPB  = 1\'bx;
+        #700  VNB  = 1\'bx;
+        #720  VGND = 1\'bx;
+        #740  D    = 1\'bx;
+        #760  C    = 1\'bx;
+        #780  B    = 1\'bx;
+        #800  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__and4 dut (.A(A), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND4_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLRTP_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__DLRTP_PP_BLACKBOX_V
+
+/**
+ * dlrtp: Delay latch, inverted reset, non-inverted enable,
+ *        single output.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlrtp (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE   ,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRTP_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFBBP_V
+`define SKY130_FD_SC_LS__DFBBP_V
+
+/**
+ * dfbbp: Delay flop, inverted set, inverted reset,
+ *        complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dfbbp.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dfbbp.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dfbbp.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dfbbp.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFBBP_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFRTP_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__DFRTP_PP_BLACKBOX_V
+
+/**
+ * dfrtp: Delay flop, inverted reset, single output.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dfrtp (
+    Q      ,
+    CLK    ,
+    D      ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFRTP_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SDLCLKP_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__SDLCLKP_FUNCTIONAL_V
+
+/**
+ * sdlclkp: Scan gated clock.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_p/sky130_fd_sc_ls__udp_dlatch_p.v""
+
+`celldefine
+module sky130_fd_sc_ls__sdlclkp (
+    GCLK,
+    SCE ,
+    GATE,
+    CLK
+);
+
+    // Module ports
+    output GCLK;
+    input  SCE ;
+    input  GATE;
+    input  CLK ;
+
+    // Local signals
+    wire m0      ;
+    wire m0n     ;
+    wire clkn    ;
+    wire SCE_GATE;
+
+    //                            Name     Output    Other arguments
+    not                           not0    (m0n     , m0             );
+    not                           not1    (clkn    , CLK            );
+    nor                           nor0    (SCE_GATE, GATE, SCE      );
+    sky130_fd_sc_ls__udp_dlatch$P dlatch0 (m0      , SCE_GATE, clkn );
+    and                           and0    (GCLK    , m0n, CLK       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDLCLKP_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O2111A_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__O2111A_BEHAVIORAL_V
+
+/**
+ * o2111a: 2-input OR into first input of 4-input AND.
+ *
+ *         X = ((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__o2111a (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out   ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    or  or0  (or0_out   , A2, A1             );
+    and and0 (and0_out_X, B1, C1, or0_out, D1);
+    buf buf0 (X         , and0_out_X         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2111A_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFXTP_SYMBOL_V
+`define SKY130_FD_SC_LS__DFXTP_SYMBOL_V
+
+/**
+ * dfxtp: Delay flop, single output.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dfxtp (
+    //# {{data|Data Signals}}
+    input  D  ,
+    output Q  ,
+
+    //# {{clocks|Clocking}}
+    input  CLK
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFXTP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLRTN_BLACKBOX_V
+`define SKY130_FD_SC_LS__DLRTN_BLACKBOX_V
+
+/**
+ * dlrtn: Delay latch, inverted reset, inverted enable, single output.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlrtn (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE_N
+);
+
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE_N ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRTN_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD3_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__CLKDLYINV5SD3_PP_SYMBOL_V
+
+/**
+ * clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
+ *                stage gate.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__clkdlyinv5sd3 (
+    //# {{data|Data Signals}}
+    input  A   ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV5SD3_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FAHCIN_V
+`define SKY130_FD_SC_LS__FAHCIN_V
+
+/**
+ * fahcin: Full adder, inverted carry in.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__fahcin.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__fahcin.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__fahcin.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__fahcin.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FAHCIN_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A221OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__A221OI_FUNCTIONAL_PP_V
+
+/**
+ * a221oi: 2-input AND into first two inputs of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a221oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire and1_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , B1, B2                );
+    and                                and1        (and1_out         , A1, A2                );
+    nor                                nor0        (nor0_out_Y       , and0_out, C1, and1_out);
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A221OI_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND4B_2_V
+`define SKY130_FD_SC_LS__AND4B_2_V
+
+/**
+ * and4b: 4-input AND, first input inverted.
+ *
+ * Verilog wrapper for and4b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__and4b.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__and4b_2 (
+    X   ,
+    A_N ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__and4b base (
+        .X(X),
+        .A_N(A_N),
+        .B(B),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__and4b_2 (
+    X  ,
+    A_N,
+    B  ,
+    C  ,
+    D
+);
+
+    output X  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__and4b base (
+        .X(X),
+        .A_N(A_N),
+        .B(B),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND4B_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DECAP_4_V
+`define SKY130_FD_SC_LS__DECAP_4_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Verilog wrapper for decap with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__decap.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__decap_4 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+    sky130_fd_sc_ls__decap base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__decap_4 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__decap base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DECAP_4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__OR3B_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__OR3B_BEHAVIORAL_PP_V
+
+/**
+ * or3b: 3-input OR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__or3b (
+    X   ,
+    A   ,
+    B   ,
+    C_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , C_N                  );
+    or                                 or0         (or0_out_X        , B, A, not0_out       );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR3B_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DFF_NRS_SYMBOL_V
+`define SKY130_FD_SC_LS__UDP_DFF_NRS_SYMBOL_V
+
+/**
+ * udp_dff$NRS: Negative edge triggered D flip-flop (Q output UDP)
+ *              with both active high reset and set (reset dominate).
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__udp_dff$NRS (
+    //# {{data|Data Signals}}
+    input  D    ,
+    output Q    ,
+
+    //# {{control|Control Signals}}
+    input  RESET,
+    input  SET  ,
+
+    //# {{clocks|Clocking}}
+    input  CLK_N
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DFF_NRS_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__XOR2_V
+`define SKY130_FD_SC_LS__XOR2_V
+
+/**
+ * xor2: 2-input exclusive OR.
+ *
+ *       X = A ^ B
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__xor2.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__xor2.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__xor2.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__xor2.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XOR2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__EDFXBP_SYMBOL_V
+`define SKY130_FD_SC_LS__EDFXBP_SYMBOL_V
+
+/**
+ * edfxbp: Delay flop with loopback enable, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__edfxbp (
+    //# {{data|Data Signals}}
+    input  D  ,
+    output Q  ,
+    output Q_N,
+
+    //# {{control|Control Signals}}
+    input  DE ,
+
+    //# {{clocks|Clocking}}
+    input  CLK
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EDFXBP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR4_TB_V
+`define SKY130_FD_SC_LS__NOR4_TB_V
+
+/**
+ * nor4: 4-input NOR.
+ *
+ *       Y = !(A | B | C | D)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nor4.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg B;
+    reg C;
+    reg D;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        B    = 1\'bX;
+        C    = 1\'bX;
+        D    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   B    = 1\'b0;
+        #60   C    = 1\'b0;
+        #80   D    = 1\'b0;
+        #100  VGND = 1\'b0;
+        #120  VNB  = 1\'b0;
+        #140  VPB  = 1\'b0;
+        #160  VPWR = 1\'b0;
+        #180  A    = 1\'b1;
+        #200  B    = 1\'b1;
+        #220  C    = 1\'b1;
+        #240  D    = 1\'b1;
+        #260  VGND = 1\'b1;
+        #280  VNB  = 1\'b1;
+        #300  VPB  = 1\'b1;
+        #320  VPWR = 1\'b1;
+        #340  A    = 1\'b0;
+        #360  B    = 1\'b0;
+        #380  C    = 1\'b0;
+        #400  D    = 1\'b0;
+        #420  VGND = 1\'b0;
+        #440  VNB  = 1\'b0;
+        #460  VPB  = 1\'b0;
+        #480  VPWR = 1\'b0;
+        #500  VPWR = 1\'b1;
+        #520  VPB  = 1\'b1;
+        #540  VNB  = 1\'b1;
+        #560  VGND = 1\'b1;
+        #580  D    = 1\'b1;
+        #600  C    = 1\'b1;
+        #620  B    = 1\'b1;
+        #640  A    = 1\'b1;
+        #660  VPWR = 1\'bx;
+        #680  VPB  = 1\'bx;
+        #700  VNB  = 1\'bx;
+        #720  VGND = 1\'bx;
+        #740  D    = 1\'bx;
+        #760  C    = 1\'bx;
+        #780  B    = 1\'bx;
+        #800  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__nor4 dut (.A(A), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR4_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__EINVP_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__EINVP_PP_SYMBOL_V
+
+/**
+ * einvp: Tri-state inverter, positive enable.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__einvp (
+    //# {{data|Data Signals}}
+    input  A   ,
+    output Z   ,
+
+    //# {{control|Control Signals}}
+    input  TE  ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EINVP_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR3_1_V
+`define SKY130_FD_SC_LS__NOR3_1_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ *       Y = !(A | B | C | !D)
+ *
+ * Verilog wrapper for nor3 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nor3.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor3_1 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nor3 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor3_1 (
+    Y,
+    A,
+    B,
+    C
+);
+
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nor3 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR3_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFRTP_SYMBOL_V
+`define SKY130_FD_SC_LS__DFRTP_SYMBOL_V
+
+/**
+ * dfrtp: Delay flop, inverted reset, single output.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dfrtp (
+    //# {{data|Data Signals}}
+    input  D      ,
+    output Q      ,
+
+    //# {{control|Control Signals}}
+    input  RESET_B,
+
+    //# {{clocks|Clocking}}
+    input  CLK
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFRTP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD1_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__CLKDLYINV5SD1_FUNCTIONAL_PP_V
+
+/**
+ * clkdlyinv5sd1: Clock Delay Inverter 5-stage 0.15um length inner
+ *                stage gate.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__clkdlyinv5sd1 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out_Y       , A                     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV5SD1_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFSTP_TB_V
+`define SKY130_FD_SC_LS__DFSTP_TB_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dfstp.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg SET_B;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Q;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D     = 1\'bX;
+        SET_B = 1\'bX;
+        VGND  = 1\'bX;
+        VNB   = 1\'bX;
+        VPB   = 1\'bX;
+        VPWR  = 1\'bX;
+
+        #20   D     = 1\'b0;
+        #40   SET_B = 1\'b0;
+        #60   VGND  = 1\'b0;
+        #80   VNB   = 1\'b0;
+        #100  VPB   = 1\'b0;
+        #120  VPWR  = 1\'b0;
+        #140  D     = 1\'b1;
+        #160  SET_B = 1\'b1;
+        #180  VGND  = 1\'b1;
+        #200  VNB   = 1\'b1;
+        #220  VPB   = 1\'b1;
+        #240  VPWR  = 1\'b1;
+        #260  D     = 1\'b0;
+        #280  SET_B = 1\'b0;
+        #300  VGND  = 1\'b0;
+        #320  VNB   = 1\'b0;
+        #340  VPB   = 1\'b0;
+        #360  VPWR  = 1\'b0;
+        #380  VPWR  = 1\'b1;
+        #400  VPB   = 1\'b1;
+        #420  VNB   = 1\'b1;
+        #440  VGND  = 1\'b1;
+        #460  SET_B = 1\'b1;
+        #480  D     = 1\'b1;
+        #500  VPWR  = 1\'bx;
+        #520  VPB   = 1\'bx;
+        #540  VNB   = 1\'bx;
+        #560  VGND  = 1\'bx;
+        #580  SET_B = 1\'bx;
+        #600  D     = 1\'bx;
+    end
+
+    // Create a clock
+    reg CLK;
+    initial
+    begin
+        CLK = 1\'b0;
+    end
+
+    always
+    begin
+        #5 CLK = ~CLK;
+    end
+
+    sky130_fd_sc_ls__dfstp dut (.D(D), .SET_B(SET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFSTP_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O22A_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__O22A_PP_BLACKBOX_V
+
+/**
+ * o22a: 2-input OR into both inputs of 2-input AND.
+ *
+ *       X = ((A1 | A2) & (B1 | B2))
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o22a (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O22A_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A211OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__A211OI_BEHAVIORAL_PP_V
+
+/**
+ * a211oi: 2-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | B1 | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a211oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A1, A2                );
+    nor                                nor0        (nor0_out_Y       , and0_out, B1, C1      );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A211OI_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A21BOI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__A21BOI_FUNCTIONAL_PP_V
+
+/**
+ * a21boi: 2-input AND into first input of 2-input NOR,
+ *         2nd input inverted.
+ *
+ *         Y = !((A1 & A2) | (!B1_N))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a21boi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire b                ;
+    wire and0_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (b                , B1_N                  );
+    and                                and0        (and0_out         , A1, A2                );
+    nor                                nor0        (nor0_out_Y       , b, and0_out           );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21BOI_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DLATCH_P_PP_PG_N_SYMBOL_V
+`define SKY130_FD_SC_LS__UDP_DLATCH_P_PP_PG_N_SYMBOL_V
+
+/**
+ * udp_dlatch$P_pp$PG$N: D-latch, gated standard drive / active high
+ *                       (Q output UDP)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__udp_dlatch$P_pp$PG$N (
+    //# {{data|Data Signals}}
+    input  D       ,
+    output Q       ,
+
+    //# {{clocks|Clocking}}
+    input  GATE    ,
+
+    //# {{power|Power}}
+    input  NOTIFIER,
+    input  VPWR    ,
+    input  VGND
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DLATCH_P_PP_PG_N_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD3_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__CLKDLYINV5SD3_BEHAVIORAL_PP_V
+
+/**
+ * clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
+ *                stage gate.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__clkdlyinv5sd3 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out_Y       , A                     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV5SD3_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__TAPVPWRVGND_TB_V
+`define SKY130_FD_SC_LS__TAPVPWRVGND_TB_V
+
+/**
+ * tapvpwrvgnd: Substrate and well tap cell.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__tapvpwrvgnd.v""
+
+module top();
+
+    // Inputs are registered
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   VGND = 1\'b0;
+        #40   VNB  = 1\'b0;
+        #60   VPB  = 1\'b0;
+        #80   VPWR = 1\'b0;
+        #100  VGND = 1\'b1;
+        #120  VNB  = 1\'b1;
+        #140  VPB  = 1\'b1;
+        #160  VPWR = 1\'b1;
+        #180  VGND = 1\'b0;
+        #200  VNB  = 1\'b0;
+        #220  VPB  = 1\'b0;
+        #240  VPWR = 1\'b0;
+        #260  VPWR = 1\'b1;
+        #280  VPB  = 1\'b1;
+        #300  VNB  = 1\'b1;
+        #320  VGND = 1\'b1;
+        #340  VPWR = 1\'bx;
+        #360  VPB  = 1\'bx;
+        #380  VNB  = 1\'bx;
+        #400  VGND = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__tapvpwrvgnd dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPVPWRVGND_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR2B_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__OR2B_PP_SYMBOL_V
+
+/**
+ * or2b: 2-input OR, first input inverted.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__or2b (
+    //# {{data|Data Signals}}
+    input  A   ,
+    input  B_N ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR2B_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR4B_BLACKBOX_V
+`define SKY130_FD_SC_LS__OR4B_BLACKBOX_V
+
+/**
+ * or4b: 4-input OR, first input inverted.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__or4b (
+    X  ,
+    A  ,
+    B  ,
+    C  ,
+    D_N
+);
+
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C  ;
+    input  D_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR4B_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A22O_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__A22O_PP_SYMBOL_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ *       X = ((A1 & A2) | (B1 & B2))
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a22o (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  B1  ,
+    input  B2  ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A22O_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FAH_4_V
+`define SKY130_FD_SC_LS__FAH_4_V
+
+/**
+ * fah: Full adder.
+ *
+ * Verilog wrapper for fah with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__fah.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__fah_4 (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CI  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CI  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__fah base (
+        .COUT(COUT),
+        .SUM(SUM),
+        .A(A),
+        .B(B),
+        .CI(CI),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__fah_4 (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CI
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CI  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__fah base (
+        .COUT(COUT),
+        .SUM(SUM),
+        .A(A),
+        .B(B),
+        .CI(CI)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FAH_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A22OI_V
+`define SKY130_FD_SC_LS__A22OI_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a22oi.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a22oi.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a22oi.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a22oi.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A22OI_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O21A_TB_V
+`define SKY130_FD_SC_LS__O21A_TB_V
+
+/**
+ * o21a: 2-input OR into first input of 2-input AND.
+ *
+ *       X = ((A1 | A2) & B1)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o21a.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg B1;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        B1   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   B1   = 1\'b0;
+        #80   VGND = 1\'b0;
+        #100  VNB  = 1\'b0;
+        #120  VPB  = 1\'b0;
+        #140  VPWR = 1\'b0;
+        #160  A1   = 1\'b1;
+        #180  A2   = 1\'b1;
+        #200  B1   = 1\'b1;
+        #220  VGND = 1\'b1;
+        #240  VNB  = 1\'b1;
+        #260  VPB  = 1\'b1;
+        #280  VPWR = 1\'b1;
+        #300  A1   = 1\'b0;
+        #320  A2   = 1\'b0;
+        #340  B1   = 1\'b0;
+        #360  VGND = 1\'b0;
+        #380  VNB  = 1\'b0;
+        #400  VPB  = 1\'b0;
+        #420  VPWR = 1\'b0;
+        #440  VPWR = 1\'b1;
+        #460  VPB  = 1\'b1;
+        #480  VNB  = 1\'b1;
+        #500  VGND = 1\'b1;
+        #520  B1   = 1\'b1;
+        #540  A2   = 1\'b1;
+        #560  A1   = 1\'b1;
+        #580  VPWR = 1\'bx;
+        #600  VPB  = 1\'bx;
+        #620  VNB  = 1\'bx;
+        #640  VGND = 1\'bx;
+        #660  B1   = 1\'bx;
+        #680  A2   = 1\'bx;
+        #700  A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__o21a dut (.A1(A1), .A2(A2), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21A_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLYGATE4SD2_SYMBOL_V
+`define SKY130_FD_SC_LS__DLYGATE4SD2_SYMBOL_V
+
+/**
+ * dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlygate4sd2 (
+    //# {{data|Data Signals}}
+    input  A,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYGATE4SD2_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__XOR2_2_V
+`define SKY130_FD_SC_LS__XOR2_2_V
+
+/**
+ * xor2: 2-input exclusive OR.
+ *
+ *       X = A ^ B
+ *
+ * Verilog wrapper for xor2 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__xor2.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__xor2_2 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__xor2 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__xor2_2 (
+    X,
+    A,
+    B
+);
+
+    output X;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__xor2 base (
+        .X(X),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XOR2_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR2B_V
+`define SKY130_FD_SC_LS__NOR2B_V
+
+/**
+ * nor2b: 2-input NOR, first input inverted.
+ *
+ *        Y = !(A | B | C | !D)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__nor2b.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__nor2b.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__nor2b.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__nor2b.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR2B_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A2111OI_SYMBOL_V
+`define SKY130_FD_SC_LS__A2111OI_SYMBOL_V
+
+/**
+ * a2111oi: 2-input AND into first input of 4-input NOR.
+ *
+ *          Y = !((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a2111oi (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  B1,
+    input  C1,
+    input  D1,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2111OI_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A21BOI_BLACKBOX_V
+`define SKY130_FD_SC_LS__A21BOI_BLACKBOX_V
+
+/**
+ * a21boi: 2-input AND into first input of 2-input NOR,
+ *         2nd input inverted.
+ *
+ *         Y = !((A1 & A2) | (!B1_N))
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a21boi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21BOI_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A222OI_TB_V
+`define SKY130_FD_SC_LS__A222OI_TB_V
+
+/**
+ * a222oi: 2-input AND into all inputs of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a222oi.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg B1;
+    reg B2;
+    reg C1;
+    reg C2;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        B1   = 1\'bX;
+        B2   = 1\'bX;
+        C1   = 1\'bX;
+        C2   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   B1   = 1\'b0;
+        #80   B2   = 1\'b0;
+        #100  C1   = 1\'b0;
+        #120  C2   = 1\'b0;
+        #140  VGND = 1\'b0;
+        #160  VNB  = 1\'b0;
+        #180  VPB  = 1\'b0;
+        #200  VPWR = 1\'b0;
+        #220  A1   = 1\'b1;
+        #240  A2   = 1\'b1;
+        #260  B1   = 1\'b1;
+        #280  B2   = 1\'b1;
+        #300  C1   = 1\'b1;
+        #320  C2   = 1\'b1;
+        #340  VGND = 1\'b1;
+        #360  VNB  = 1\'b1;
+        #380  VPB  = 1\'b1;
+        #400  VPWR = 1\'b1;
+        #420  A1   = 1\'b0;
+        #440  A2   = 1\'b0;
+        #460  B1   = 1\'b0;
+        #480  B2   = 1\'b0;
+        #500  C1   = 1\'b0;
+        #520  C2   = 1\'b0;
+        #540  VGND = 1\'b0;
+        #560  VNB  = 1\'b0;
+        #580  VPB  = 1\'b0;
+        #600  VPWR = 1\'b0;
+        #620  VPWR = 1\'b1;
+        #640  VPB  = 1\'b1;
+        #660  VNB  = 1\'b1;
+        #680  VGND = 1\'b1;
+        #700  C2   = 1\'b1;
+        #720  C1   = 1\'b1;
+        #740  B2   = 1\'b1;
+        #760  B1   = 1\'b1;
+        #780  A2   = 1\'b1;
+        #800  A1   = 1\'b1;
+        #820  VPWR = 1\'bx;
+        #840  VPB  = 1\'bx;
+        #860  VNB  = 1\'bx;
+        #880  VGND = 1\'bx;
+        #900  C2   = 1\'bx;
+        #920  C1   = 1\'bx;
+        #940  B2   = 1\'bx;
+        #960  B1   = 1\'bx;
+        #980  A2   = 1\'bx;
+        #1000 A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__a222oi dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .C2(C2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A222OI_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DLATCH_P_PP_PG_N_TB_V
+`define SKY130_FD_SC_LS__UDP_DLATCH_P_PP_PG_N_TB_V
+
+/**
+ * udp_dlatch$P_pp$PG$N: D-latch, gated standard drive / active high
+ *                       (Q output UDP)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__udp_dlatch_p_pp_pg_n.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg NOTIFIER;
+    reg VPWR;
+    reg VGND;
+
+    // Outputs are wires
+    wire Q;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D        = 1\'bX;
+        NOTIFIER = 1\'bX;
+        VGND     = 1\'bX;
+        VPWR     = 1\'bX;
+
+        #20   D        = 1\'b0;
+        #40   NOTIFIER = 1\'b0;
+        #60   VGND     = 1\'b0;
+        #80   VPWR     = 1\'b0;
+        #100  D        = 1\'b1;
+        #120  NOTIFIER = 1\'b1;
+        #140  VGND     = 1\'b1;
+        #160  VPWR     = 1\'b1;
+        #180  D        = 1\'b0;
+        #200  NOTIFIER = 1\'b0;
+        #220  VGND     = 1\'b0;
+        #240  VPWR     = 1\'b0;
+        #260  VPWR     = 1\'b1;
+        #280  VGND     = 1\'b1;
+        #300  NOTIFIER = 1\'b1;
+        #320  D        = 1\'b1;
+        #340  VPWR     = 1\'bx;
+        #360  VGND     = 1\'bx;
+        #380  NOTIFIER = 1\'bx;
+        #400  D        = 1\'bx;
+    end
+
+    // Create a clock
+    reg GATE;
+    initial
+    begin
+        GATE = 1\'b0;
+    end
+
+    always
+    begin
+        #5 GATE = ~GATE;
+    end
+
+    sky130_fd_sc_ls__udp_dlatch$P_pp$PG$N dut (.D(D), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .GATE(GATE));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DLATCH_P_PP_PG_N_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__TAPVPWRVGND_V
+`define SKY130_FD_SC_LS__TAPVPWRVGND_V
+
+/**
+ * tapvpwrvgnd: Substrate and well tap cell.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__tapvpwrvgnd.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__tapvpwrvgnd.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__tapvpwrvgnd.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__tapvpwrvgnd.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPVPWRVGND_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SEDFXBP_SYMBOL_V
+`define SKY130_FD_SC_LS__SEDFXBP_SYMBOL_V
+
+/**
+ * sedfxbp: Scan delay flop, data enable, non-inverted clock,
+ *          complementary outputs.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sedfxbp (
+    //# {{data|Data Signals}}
+    input  D  ,
+    output Q  ,
+    output Q_N,
+
+    //# {{control|Control Signals}}
+    input  DE ,
+
+    //# {{scanchain|Scan Chain}}
+    input  SCD,
+    input  SCE,
+
+    //# {{clocks|Clocking}}
+    input  CLK
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SEDFXBP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR2B_4_V
+`define SKY130_FD_SC_LS__OR2B_4_V
+
+/**
+ * or2b: 2-input OR, first input inverted.
+ *
+ * Verilog wrapper for or2b with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__or2b.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__or2b_4 (
+    X   ,
+    A   ,
+    B_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__or2b base (
+        .X(X),
+        .A(A),
+        .B_N(B_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__or2b_4 (
+    X  ,
+    A  ,
+    B_N
+);
+
+    output X  ;
+    input  A  ;
+    input  B_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__or2b base (
+        .X(X),
+        .A(A),
+        .B_N(B_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR2B_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFRTN_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__SDFRTN_PP_BLACKBOX_V
+
+/**
+ * sdfrtn: Scan delay flop, inverted reset, inverted clock,
+ *         single output.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sdfrtn (
+    Q      ,
+    CLK_N  ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    input  CLK_N  ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFRTN_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O2BB2A_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__O2BB2A_BEHAVIORAL_PP_V
+
+/**
+ * o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
+ *
+ *         X = (!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__o2bb2a (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out        ;
+    wire or0_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out        , A2_N, A1_N            );
+    or                                 or0         (or0_out          , B2, B1                );
+    and                                and0        (and0_out_X       , nand0_out, or0_out    );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2BB2A_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FA_BLACKBOX_V
+`define SKY130_FD_SC_LS__FA_BLACKBOX_V
+
+/**
+ * fa: Full adder.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__fa (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CIN
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CIN ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FA_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A32OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__A32OI_FUNCTIONAL_PP_V
+
+/**
+ * a32oi: 3-input AND into first input, and 2-input AND into
+ *        2nd input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a32oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out        ;
+    wire nand1_out        ;
+    wire and0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out        , A2, A1, A3            );
+    nand                               nand1       (nand1_out        , B2, B1                );
+    and                                and0        (and0_out_Y       , nand0_out, nand1_out  );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A32OI_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__HA_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__HA_PP_SYMBOL_V
+
+/**
+ * ha: Half adder.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__ha (
+    //# {{data|Data Signals}}
+    input  A   ,
+    input  B   ,
+    output COUT,
+    output SUM ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__HA_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__EINVN_V
+`define SKY130_FD_SC_LS__EINVN_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__einvn.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__einvn.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__einvn.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__einvn.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EINVN_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A2111O_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__A2111O_BEHAVIORAL_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ *         X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a2111o (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , A1, A2              );
+    or  or0  (or0_out_X, C1, B1, and0_out, D1);
+    buf buf0 (X        , or0_out_X           );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2111O_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLYMETAL6S4S_BLACKBOX_V
+`define SKY130_FD_SC_LS__DLYMETAL6S4S_BLACKBOX_V
+
+/**
+ * dlymetal6s4s: 6-inverter delay with output from 4th inverter on
+ *               horizontal route.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlymetal6s4s (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYMETAL6S4S_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__XOR3_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__XOR3_FUNCTIONAL_PP_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ *       X = A ^ B ^ C
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__xor3 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire xor0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    xor                                xor0        (xor0_out_X       , A, B, C               );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XOR3_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD2_BLACKBOX_V
+`define SKY130_FD_SC_LS__CLKDLYINV3SD2_BLACKBOX_V
+
+/**
+ * clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
+ *                stage gate.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__clkdlyinv3sd2 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV3SD2_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFXTP_SYMBOL_V
+`define SKY130_FD_SC_LS__SDFXTP_SYMBOL_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sdfxtp (
+    //# {{data|Data Signals}}
+    input  D  ,
+    output Q  ,
+
+    //# {{scanchain|Scan Chain}}
+    input  SCD,
+    input  SCE,
+
+    //# {{clocks|Clocking}}
+    input  CLK
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFXTP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DFRBP_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__DFRBP_BEHAVIORAL_V
+
+/**
+ * dfrbp: Delay flop, inverted reset, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dfrbp (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q          ;
+    wire RESET          ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire RESET_B_delayed;
+    wire CLK_delayed    ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+
+    //                                  Name  Output  Other arguments
+    not                                 not0 (RESET , RESET_B_delayed                                    );
+    sky130_fd_sc_ls__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
+    assign cond0 = ( awake && ( RESET_B_delayed === 1\'b1 ) );
+    assign cond1 = ( awake && ( RESET_B === 1\'b1 ) );
+    buf                                 buf0 (Q     , buf_Q                                              );
+    not                                 not1 (Q_N   , buf_Q                                              );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFRBP_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND2_2_V
+`define SKY130_FD_SC_LS__AND2_2_V
+
+/**
+ * and2: 2-input AND.
+ *
+ * Verilog wrapper for and2 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__and2.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__and2_2 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__and2 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__and2_2 (
+    X,
+    A,
+    B
+);
+
+    output X;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__and2 base (
+        .X(X),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND2_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__INV_16_V
+`define SKY130_FD_SC_LS__INV_16_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog wrapper for inv with size of 16 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__inv.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__inv_16 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__inv base (
+        .Y(Y),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__inv_16 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__inv base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__INV_16_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__BUF_TB_V
+`define SKY130_FD_SC_LS__BUF_TB_V
+
+/**
+ * buf: Buffer.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__buf.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   VGND = 1\'b0;
+        #60   VNB  = 1\'b0;
+        #80   VPB  = 1\'b0;
+        #100  VPWR = 1\'b0;
+        #120  A    = 1\'b1;
+        #140  VGND = 1\'b1;
+        #160  VNB  = 1\'b1;
+        #180  VPB  = 1\'b1;
+        #200  VPWR = 1\'b1;
+        #220  A    = 1\'b0;
+        #240  VGND = 1\'b0;
+        #260  VNB  = 1\'b0;
+        #280  VPB  = 1\'b0;
+        #300  VPWR = 1\'b0;
+        #320  VPWR = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VNB  = 1\'b1;
+        #380  VGND = 1\'b1;
+        #400  A    = 1\'b1;
+        #420  VPWR = 1\'bx;
+        #440  VPB  = 1\'bx;
+        #460  VNB  = 1\'bx;
+        #480  VGND = 1\'bx;
+        #500  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__buf dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__BUF_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SDFRBP_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__SDFRBP_FUNCTIONAL_V
+
+/**
+ * sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+`include ""../../models/udp_dff_pr/sky130_fd_sc_ls__udp_dff_pr.v""
+
+`celldefine
+module sky130_fd_sc_ls__sdfrbp (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+
+    // Local signals
+    wire buf_Q  ;
+    wire RESET  ;
+    wire mux_out;
+
+    //                            Delay       Name       Output   Other arguments
+    not                                       not0      (RESET  , RESET_B            );
+    sky130_fd_sc_ls__udp_mux_2to1             mux_2to10 (mux_out, D, SCD, SCE        );
+    sky130_fd_sc_ls__udp_dff$PR   `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK, RESET);
+    buf                                       buf0      (Q      , buf_Q              );
+    not                                       not1      (Q_N    , buf_Q              );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFRBP_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFXBP_SYMBOL_V
+`define SKY130_FD_SC_LS__SDFXBP_SYMBOL_V
+
+/**
+ * sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sdfxbp (
+    //# {{data|Data Signals}}
+    input  D  ,
+    output Q  ,
+    output Q_N,
+
+    //# {{scanchain|Scan Chain}}
+    input  SCD,
+    input  SCE,
+
+    //# {{clocks|Clocking}}
+    input  CLK
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFXBP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O311A_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__O311A_PP_BLACKBOX_V
+
+/**
+ * o311a: 3-input OR into 3-input AND.
+ *
+ *        X = ((A1 | A2 | A3) & B1 & C1)
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o311a (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O311A_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__EBUFN_TB_V
+`define SKY130_FD_SC_LS__EBUFN_TB_V
+
+/**
+ * ebufn: Tri-state buffer, negative enable.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__ebufn.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg TE_B;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Z;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        TE_B = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   TE_B = 1\'b0;
+        #60   VGND = 1\'b0;
+        #80   VNB  = 1\'b0;
+        #100  VPB  = 1\'b0;
+        #120  VPWR = 1\'b0;
+        #140  A    = 1\'b1;
+        #160  TE_B = 1\'b1;
+        #180  VGND = 1\'b1;
+        #200  VNB  = 1\'b1;
+        #220  VPB  = 1\'b1;
+        #240  VPWR = 1\'b1;
+        #260  A    = 1\'b0;
+        #280  TE_B = 1\'b0;
+        #300  VGND = 1\'b0;
+        #320  VNB  = 1\'b0;
+        #340  VPB  = 1\'b0;
+        #360  VPWR = 1\'b0;
+        #380  VPWR = 1\'b1;
+        #400  VPB  = 1\'b1;
+        #420  VNB  = 1\'b1;
+        #440  VGND = 1\'b1;
+        #460  TE_B = 1\'b1;
+        #480  A    = 1\'b1;
+        #500  VPWR = 1\'bx;
+        #520  VPB  = 1\'bx;
+        #540  VNB  = 1\'bx;
+        #560  VGND = 1\'bx;
+        #580  TE_B = 1\'bx;
+        #600  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__ebufn dut (.A(A), .TE_B(TE_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Z(Z));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EBUFN_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A1 +=> X) = (0:0:0,0:0:0);
+(A2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&C1&D1)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&C1&D1)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2&C1&D1)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&B1&D1)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&B1&D1)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2&B1&D1)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&B1&C1)) (D1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&B1&C1)) (D1 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2&B1&C1)) (D1 +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFXBP_1_V
+`define SKY130_FD_SC_LS__SDFXBP_1_V
+
+/**
+ * sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
+ *
+ * Verilog wrapper for sdfxbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__sdfxbp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sdfxbp_1 (
+    Q   ,
+    Q_N ,
+    CLK ,
+    D   ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    output Q_N ;
+    input  CLK ;
+    input  D   ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__sdfxbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sdfxbp_1 (
+    Q  ,
+    Q_N,
+    CLK,
+    D  ,
+    SCD,
+    SCE
+);
+
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+    input  SCD;
+    input  SCE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__sdfxbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFXBP_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__XNOR2_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__XNOR2_FUNCTIONAL_PP_V
+
+/**
+ * xnor2: 2-input exclusive NOR.
+ *
+ *        Y = !(A ^ B)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__xnor2 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire xnor0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    xnor                               xnor0       (xnor0_out_Y      , A, B                   );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, xnor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XNOR2_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if ((A2&!B1&!B2)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((A2&!B1&B2)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((A2&B1&!B2)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!B1&!B2)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((A1&!B1&B2)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((A1&B1&!B2)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&B2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&B2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&B2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&B1)) (B2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&B1)) (B2 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&B1)) (B2 +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__OR4_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__OR4_FUNCTIONAL_V
+
+/**
+ * or4: 4-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__or4 (
+    X,
+    A,
+    B,
+    C,
+    D
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Local signals
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    or  or0  (or0_out_X, D, C, B, A     );
+    buf buf0 (X        , or0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR4_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O31A_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__O31A_FUNCTIONAL_PP_V
+
+/**
+ * o31a: 3-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__o31a (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1, A3            );
+    and                                and0        (and0_out_X       , or0_out, B1           );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O31A_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SDFSBP_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__SDFSBP_BEHAVIORAL_V
+
+/**
+ * sdfsbp: Scan delay flop, inverted set, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ls__udp_dff_ps_pp_pg_n.v""
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+
+`celldefine
+module sky130_fd_sc_ls__sdfsbp (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B
+);
+
+    // Module ports
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q        ;
+    wire SET          ;
+    wire mux_out      ;
+    reg  notifier     ;
+    wire D_delayed    ;
+    wire SCD_delayed  ;
+    wire SCE_delayed  ;
+    wire SET_B_delayed;
+    wire CLK_delayed  ;
+    wire awake        ;
+    wire cond0        ;
+    wire cond1        ;
+    wire cond2        ;
+    wire cond3        ;
+    wire cond4        ;
+
+    //                                  Name       Output   Other arguments
+    not                                 not0      (SET    , SET_B_delayed                                  );
+    sky130_fd_sc_ls__udp_mux_2to1       mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed            );
+    sky130_fd_sc_ls__udp_dff$PS_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    assign cond0 = ( ( SET_B_delayed === 1\'b1 ) && awake );
+    assign cond1 = ( ( SCE_delayed === 1\'b0 ) && cond0 );
+    assign cond2 = ( ( SCE_delayed === 1\'b1 ) && cond0 );
+    assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
+    assign cond4 = ( ( SET_B === 1\'b1 ) && awake );
+    buf                                 buf0      (Q      , buf_Q                                          );
+    not                                 not1      (Q_N    , buf_Q                                          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFSBP_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__AND4_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__AND4_FUNCTIONAL_PP_V
+
+/**
+ * and4: 4-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__and4 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out_X       , A, B, C, D            );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND4_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__OR2_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__OR2_FUNCTIONAL_PP_V
+
+/**
+ * or2: 2-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__or2 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out_X        , B, A                 );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR2_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A2BB2OI_1_V
+`define SKY130_FD_SC_LS__A2BB2OI_1_V
+
+/**
+ * a2bb2oi: 2-input AND, both inputs inverted, into first input, and
+ *          2-input AND into 2nd input of 2-input NOR.
+ *
+ *          Y = !((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a2bb2oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a2bb2oi.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a2bb2oi_1 (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a2bb2oi base (
+        .Y(Y),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a2bb2oi_1 (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a2bb2oi base (
+        .Y(Y),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2BB2OI_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLRBN_V
+`define SKY130_FD_SC_LS__DLRBN_V
+
+/**
+ * dlrbn: Delay latch, inverted reset, inverted enable,
+ *        complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlrbn.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlrbn.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlrbn.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlrbn.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRBN_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NOR4BB_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__NOR4BB_FUNCTIONAL_PP_V
+
+/**
+ * nor4bb: 4-input NOR, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__nor4bb (
+    Y   ,
+    A   ,
+    B   ,
+    C_N ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nor0_out         ;
+    wire and0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nor                                nor0        (nor0_out         , A, B                  );
+    and                                and0        (and0_out_Y       , nor0_out, C_N, D_N    );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR4BB_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A_N +=> Y) = (0:0:0,0:0:0);
+(B -=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A311OI_2_V
+`define SKY130_FD_SC_LS__A311OI_2_V
+
+/**
+ * a311oi: 3-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog wrapper for a311oi with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a311oi.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a311oi_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a311oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a311oi_2 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a311oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A311OI_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A22OI_1_V
+`define SKY130_FD_SC_LS__A22OI_1_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a22oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a22oi.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a22oi_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a22oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a22oi_1 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a22oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A22OI_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A21O_1_V
+`define SKY130_FD_SC_LS__A21O_1_V
+
+/**
+ * a21o: 2-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2) | B1)
+ *
+ * Verilog wrapper for a21o with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a21o.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a21o_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a21o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a21o_1 (
+    X ,
+    A1,
+    A2,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a21o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21O_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DECAP_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__DECAP_BEHAVIORAL_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__decap ();
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DECAP_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND4_1_V
+`define SKY130_FD_SC_LS__NAND4_1_V
+
+/**
+ * nand4: 4-input NAND.
+ *
+ * Verilog wrapper for nand4 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nand4.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nand4_1 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nand4 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nand4_1 (
+    Y,
+    A,
+    B,
+    C,
+    D
+);
+
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nand4 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND4_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O41A_SYMBOL_V
+`define SKY130_FD_SC_LS__O41A_SYMBOL_V
+
+/**
+ * o41a: 4-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o41a (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  A3,
+    input  A4,
+    input  B1,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O41A_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFBBN_1_V
+`define SKY130_FD_SC_LS__DFBBN_1_V
+
+/**
+ * dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
+ *        complementary outputs.
+ *
+ * Verilog wrapper for dfbbn with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dfbbn.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dfbbn_1 (
+    Q      ,
+    Q_N    ,
+    D      ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_ls__dfbbn base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .D(D),
+        .CLK_N(CLK_N),
+        .SET_B(SET_B),
+        .RESET_B(RESET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dfbbn_1 (
+    Q      ,
+    Q_N    ,
+    D      ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__dfbbn base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .D(D),
+        .CLK_N(CLK_N),
+        .SET_B(SET_B),
+        .RESET_B(RESET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFBBN_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A -=> Y) = (0:0:0,0:0:0);
+(B -=> Y) = (0:0:0,0:0:0);
+(C -=> Y) = (0:0:0,0:0:0);
+(D -=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DECAPHE_TB_V
+`define SKY130_FD_SC_LS__DECAPHE_TB_V
+
+/**
+ * decaphe: Shielded Decoupling capacitance filler.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__decaphe.v""
+
+module top();
+
+    // Inputs are registered
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   VGND = 1\'b0;
+        #40   VNB  = 1\'b0;
+        #60   VPB  = 1\'b0;
+        #80   VPWR = 1\'b0;
+        #100  VGND = 1\'b1;
+        #120  VNB  = 1\'b1;
+        #140  VPB  = 1\'b1;
+        #160  VPWR = 1\'b1;
+        #180  VGND = 1\'b0;
+        #200  VNB  = 1\'b0;
+        #220  VPB  = 1\'b0;
+        #240  VPWR = 1\'b0;
+        #260  VPWR = 1\'b1;
+        #280  VPB  = 1\'b1;
+        #300  VNB  = 1\'b1;
+        #320  VGND = 1\'b1;
+        #340  VPWR = 1\'bx;
+        #360  VPB  = 1\'bx;
+        #380  VNB  = 1\'bx;
+        #400  VGND = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__decaphe dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DECAPHE_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FAHCIN_SYMBOL_V
+`define SKY130_FD_SC_LS__FAHCIN_SYMBOL_V
+
+/**
+ * fahcin: Full adder, inverted carry in.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__fahcin (
+    //# {{data|Data Signals}}
+    input  A   ,
+    input  B   ,
+    input  CIN ,
+    output COUT,
+    output SUM
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FAHCIN_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A221OI_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__A221OI_PP_BLACKBOX_V
+
+/**
+ * a221oi: 2-input AND into first two inputs of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a221oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A221OI_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+( negedge RESET_B => ( Q +: RESET_B ) ) = ( 0:0:0 , 0:0:0 ) ;  // delay is tfall
+( D +=> Q ) = ( 0:0:0 , 0:0:0 ) ;  // delays are tris , tfall
+( posedge GATE => ( Q : GATE ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall
+$recrem ( posedge RESET_B , negedge GATE , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , RESETB_delayed , GATE_delayed ) ;
+$setuphold ( negedge GATE , posedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , GATE_delayed , D_delayed ) ;
+$setuphold ( negedge GATE , negedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , GATE_delayed , D_delayed ) ;
+$width ( posedge GATE &&& COND1 , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( negedge RESET_B &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( posedge RESET_B &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__EDFXTP_V
+`define SKY130_FD_SC_LS__EDFXTP_V
+
+/**
+ * edfxtp: Delay flop with loopback enable, non-inverted clock,
+ *         single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__edfxtp.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__edfxtp.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__edfxtp.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__edfxtp.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EDFXTP_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR2B_1_V
+`define SKY130_FD_SC_LS__NOR2B_1_V
+
+/**
+ * nor2b: 2-input NOR, first input inverted.
+ *
+ *        Y = !(A | B | C | !D)
+ *
+ * Verilog wrapper for nor2b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nor2b.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor2b_1 (
+    Y   ,
+    A   ,
+    B_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nor2b base (
+        .Y(Y),
+        .A(A),
+        .B_N(B_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor2b_1 (
+    Y  ,
+    A  ,
+    B_N
+);
+
+    output Y  ;
+    input  A  ;
+    input  B_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nor2b base (
+        .Y(Y),
+        .A(A),
+        .B_N(B_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR2B_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__HA_1_V
+`define SKY130_FD_SC_LS__HA_1_V
+
+/**
+ * ha: Half adder.
+ *
+ * Verilog wrapper for ha with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__ha.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__ha_1 (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__ha base (
+        .COUT(COUT),
+        .SUM(SUM),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__ha_1 (
+    COUT,
+    SUM ,
+    A   ,
+    B
+);
+
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__ha base (
+        .COUT(COUT),
+        .SUM(SUM),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__HA_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A1 -=> Y) = (0:0:0,0:0:0);
+(A2 -=> Y) = (0:0:0,0:0:0);
+(A3 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&!A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&!A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2&!A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2&A3&C1)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&!A2&A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&!A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&!A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2&!A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2&A3&B1)) (C1 -=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__TAPVGND_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__TAPVGND_PP_SYMBOL_V
+
+/**
+ * tapvgnd: Tap cell with tap to ground, isolated power connection
+ *          1 row down.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__tapvgnd (
+    //# {{power|Power}}
+    input VPB ,
+    input VPWR,
+    input VGND,
+    input VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPVGND_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O21AI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__O21AI_BEHAVIORAL_PP_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__o21ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1                 );
+    nand                               nand0       (nand0_out_Y      , B1, or0_out            );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21AI_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__FAH_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__FAH_BEHAVIORAL_PP_V
+
+/**
+ * fah: Full adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__fah (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CI  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CI  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire xor0_out_SUM        ;
+    wire pwrgood_pp0_out_SUM ;
+    wire a_b                 ;
+    wire a_ci                ;
+    wire b_ci                ;
+    wire or0_out_COUT        ;
+    wire pwrgood_pp1_out_COUT;
+
+    //                                 Name         Output                Other arguments
+    xor                                xor0        (xor0_out_SUM        , A, B, CI                );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
+    buf                                buf0        (SUM                 , pwrgood_pp0_out_SUM     );
+    and                                and0        (a_b                 , A, B                    );
+    and                                and1        (a_ci                , A, CI                   );
+    and                                and2        (b_ci                , B, CI                   );
+    or                                 or0         (or0_out_COUT        , a_b, a_ci, b_ci         );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
+    buf                                buf1        (COUT                , pwrgood_pp1_out_COUT    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FAH_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O31A_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__O31A_FUNCTIONAL_V
+
+/**
+ * o31a: 3-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__o31a (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Local signals
+    wire or0_out   ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    or  or0  (or0_out   , A2, A1, A3     );
+    and and0 (and0_out_X, or0_out, B1    );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O31A_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SDFSBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__SDFSBP_BEHAVIORAL_PP_V
+
+/**
+ * sdfsbp: Scan delay flop, inverted set, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ls__udp_dff_ps_pp_pg_n.v""
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+
+`celldefine
+module sky130_fd_sc_ls__sdfsbp (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire buf_Q        ;
+    wire SET          ;
+    wire mux_out      ;
+    reg  notifier     ;
+    wire D_delayed    ;
+    wire SCD_delayed  ;
+    wire SCE_delayed  ;
+    wire SET_B_delayed;
+    wire CLK_delayed  ;
+    wire awake        ;
+    wire cond0        ;
+    wire cond1        ;
+    wire cond2        ;
+    wire cond3        ;
+    wire cond4        ;
+
+    //                                  Name       Output   Other arguments
+    not                                 not0      (SET    , SET_B_delayed                                  );
+    sky130_fd_sc_ls__udp_mux_2to1       mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed            );
+    sky130_fd_sc_ls__udp_dff$PS_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    assign cond0 = ( ( SET_B_delayed === 1\'b1 ) && awake );
+    assign cond1 = ( ( SCE_delayed === 1\'b0 ) && cond0 );
+    assign cond2 = ( ( SCE_delayed === 1\'b1 ) && cond0 );
+    assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
+    assign cond4 = ( ( SET_B === 1\'b1 ) && awake );
+    buf                                 buf0      (Q      , buf_Q                                          );
+    not                                 not1      (Q_N    , buf_Q                                          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFSBP_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A +=> X) = (0:0:0,0:0:0);
+(B_N -=> X) = (0:0:0,0:0:0);
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__FA_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__FA_FUNCTIONAL_V
+
+/**
+ * fa: Full adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__fa (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CIN
+);
+
+    // Module ports
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CIN ;
+
+    // Local signals
+    wire or0_out     ;
+    wire and0_out    ;
+    wire and1_out    ;
+    wire and2_out    ;
+    wire nor0_out    ;
+    wire nor1_out    ;
+    wire or1_out_COUT;
+    wire or2_out_SUM ;
+
+    //  Name  Output        Other arguments
+    or  or0  (or0_out     , CIN, B            );
+    and and0 (and0_out    , or0_out, A        );
+    and and1 (and1_out    , B, CIN            );
+    or  or1  (or1_out_COUT, and1_out, and0_out);
+    buf buf0 (COUT        , or1_out_COUT      );
+    and and2 (and2_out    , CIN, A, B         );
+    nor nor0 (nor0_out    , A, or0_out        );
+    nor nor1 (nor1_out    , nor0_out, COUT    );
+    or  or2  (or2_out_SUM , nor1_out, and2_out);
+    buf buf1 (SUM         , or2_out_SUM       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FA_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A32O_BLACKBOX_V
+`define SKY130_FD_SC_LS__A32O_BLACKBOX_V
+
+/**
+ * a32o: 3-input AND into first input, and 2-input AND into
+ *       2nd input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a32o (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A32O_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DFSTP_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__DFSTP_FUNCTIONAL_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_ps/sky130_fd_sc_ls__udp_dff_ps.v""
+
+`celldefine
+module sky130_fd_sc_ls__dfstp (
+    Q    ,
+    CLK  ,
+    D    ,
+    SET_B
+);
+
+    // Module ports
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+
+    // Local signals
+    wire buf_Q;
+    wire SET  ;
+
+    //                          Delay       Name  Output  Other arguments
+    not                                     not0 (SET   , SET_B          );
+    sky130_fd_sc_ls__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , D, CLK, SET    );
+    buf                                     buf0 (Q     , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFSTP_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD2_1_V
+`define SKY130_FD_SC_LS__CLKDLYINV3SD2_1_V
+
+/**
+ * clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
+ *                stage gate.
+ *
+ * Verilog wrapper for clkdlyinv3sd2 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__clkdlyinv3sd2.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__clkdlyinv3sd2_1 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__clkdlyinv3sd2 base (
+        .Y(Y),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__clkdlyinv3sd2_1 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__clkdlyinv3sd2 base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV3SD2_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DECAP_SYMBOL_V
+`define SKY130_FD_SC_LS__DECAP_SYMBOL_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__decap ();
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DECAP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SEDFXBP_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__SEDFXBP_PP_SYMBOL_V
+
+/**
+ * sedfxbp: Scan delay flop, data enable, non-inverted clock,
+ *          complementary outputs.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sedfxbp (
+    //# {{data|Data Signals}}
+    input  D   ,
+    output Q   ,
+    output Q_N ,
+
+    //# {{control|Control Signals}}
+    input  DE  ,
+
+    //# {{scanchain|Scan Chain}}
+    input  SCD ,
+    input  SCE ,
+
+    //# {{clocks|Clocking}}
+    input  CLK ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SEDFXBP_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD2_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__CLKDLYINV3SD2_PP_SYMBOL_V
+
+/**
+ * clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
+ *                stage gate.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__clkdlyinv3sd2 (
+    //# {{data|Data Signals}}
+    input  A   ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV3SD2_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O32A_4_V
+`define SKY130_FD_SC_LS__O32A_4_V
+
+/**
+ * o32a: 3-input OR and 2-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog wrapper for o32a with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o32a.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o32a_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o32a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o32a_4 (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o32a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O32A_4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLYGATE4SD1_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__DLYGATE4SD1_FUNCTIONAL_V
+
+/**
+ * dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__dlygate4sd1 (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYGATE4SD1_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__AND4BB_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__AND4BB_BEHAVIORAL_V
+
+/**
+ * and4bb: 4-input AND, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__and4bb (
+    X  ,
+    A_N,
+    B_N,
+    C  ,
+    D
+);
+
+    // Module ports
+    output X  ;
+    input  A_N;
+    input  B_N;
+    input  C  ;
+    input  D  ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nor0_out  ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    nor nor0 (nor0_out  , A_N, B_N       );
+    and and0 (and0_out_X, nor0_out, C, D );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND4BB_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A21OI_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__A21OI_FUNCTIONAL_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a21oi (
+    Y ,
+    A1,
+    A2,
+    B1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Local signals
+    wire and0_out  ;
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out  , A1, A2         );
+    nor nor0 (nor0_out_Y, B1, and0_out   );
+    buf buf0 (Y         , nor0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21OI_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__OR4_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__OR4_BEHAVIORAL_V
+
+/**
+ * or4: 4-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__or4 (
+    X,
+    A,
+    B,
+    C,
+    D
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    or  or0  (or0_out_X, D, C, B, A     );
+    buf buf0 (X        , or0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR4_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O2111AI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__O2111AI_FUNCTIONAL_PP_V
+
+/**
+ * o2111ai: 2-input OR into first input of 4-input NAND.
+ *
+ *          Y = !((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__o2111ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1                 );
+    nand                               nand0       (nand0_out_Y      , C1, B1, D1, or0_out    );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2111AI_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A -=> Y) = (0:0:0,0:0:0);
+(B_N +=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SEDFXTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__SEDFXTP_BEHAVIORAL_PP_V
+
+/**
+ * sedfxtp: Scan delay flop, data enable, non-inverted clock,
+ *          single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+`include ""../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__sedfxtp (
+    Q   ,
+    CLK ,
+    D   ,
+    DE  ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  DE  ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q      ;
+    reg  notifier   ;
+    wire D_delayed  ;
+    wire DE_delayed ;
+    wire SCD_delayed;
+    wire SCE_delayed;
+    wire CLK_delayed;
+    wire mux_out    ;
+    wire de_d       ;
+    wire awake      ;
+    wire cond1      ;
+    wire cond2      ;
+    wire cond3      ;
+
+    //                                 Name       Output   Other arguments
+    sky130_fd_sc_ls__udp_mux_2to1      mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed            );
+    sky130_fd_sc_ls__udp_mux_2to1      mux_2to11 (de_d   , buf_Q, D_delayed, DE_delayed              );
+    sky130_fd_sc_ls__udp_dff$P_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    assign cond1 = ( awake && ( SCE_delayed === 1\'b0 ) && ( DE_delayed === 1\'b1 ) );
+    assign cond2 = ( awake && ( SCE_delayed === 1\'b1 ) );
+    assign cond3 = ( awake && ( DE_delayed === 1\'b1 ) && ( D_delayed !== SCD_delayed ) );
+    buf                                buf0      (Q      , buf_Q                                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SEDFXTP_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFRTN_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__DFRTN_PP_SYMBOL_V
+
+/**
+ * dfrtn: Delay flop, inverted reset, inverted clock,
+ *        complementary outputs.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dfrtn (
+    //# {{data|Data Signals}}
+    input  D      ,
+    output Q      ,
+
+    //# {{control|Control Signals}}
+    input  RESET_B,
+
+    //# {{clocks|Clocking}}
+    input  CLK_N  ,
+
+    //# {{power|Power}}
+    input  VPB    ,
+    input  VPWR   ,
+    input  VGND   ,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFRTN_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLYMETAL6S2S_SYMBOL_V
+`define SKY130_FD_SC_LS__DLYMETAL6S2S_SYMBOL_V
+
+/**
+ * dlymetal6s2s: 6-inverter delay with output from 2nd stage on
+ *               horizontal route.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlymetal6s2s (
+    //# {{data|Data Signals}}
+    input  A,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYMETAL6S2S_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O2111A_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__O2111A_PP_SYMBOL_V
+
+/**
+ * o2111a: 2-input OR into first input of 4-input AND.
+ *
+ *         X = ((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o2111a (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  B1  ,
+    input  C1  ,
+    input  D1  ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2111A_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__FAHCON_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__FAHCON_FUNCTIONAL_PP_V
+
+/**
+ * fahcon: Full adder, inverted carry in, inverted carry out.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__fahcon (
+    COUT_N,
+    SUM   ,
+    A     ,
+    B     ,
+    CI    ,
+    VPWR  ,
+    VGND  ,
+    VPB   ,
+    VNB
+);
+
+    // Module ports
+    output COUT_N;
+    output SUM   ;
+    input  A     ;
+    input  B     ;
+    input  CI    ;
+    input  VPWR  ;
+    input  VGND  ;
+    input  VPB   ;
+    input  VNB   ;
+
+    // Local signals
+    wire xor0_out_SUM         ;
+    wire pwrgood_pp0_out_SUM  ;
+    wire a_b                  ;
+    wire a_ci                 ;
+    wire b_ci                 ;
+    wire or0_out_coutn        ;
+    wire pwrgood_pp1_out_coutn;
+
+    //                                 Name         Output                 Other arguments
+    xor                                xor0        (xor0_out_SUM         , A, B, CI                 );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM  , xor0_out_SUM, VPWR, VGND );
+    buf                                buf0        (SUM                  , pwrgood_pp0_out_SUM      );
+    nor                                nor0        (a_b                  , A, B                     );
+    nor                                nor1        (a_ci                 , A, CI                    );
+    nor                                nor2        (b_ci                 , B, CI                    );
+    or                                 or0         (or0_out_coutn        , a_b, a_ci, b_ci          );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_coutn, or0_out_coutn, VPWR, VGND);
+    buf                                buf1        (COUT_N               , pwrgood_pp1_out_coutn    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FAHCON_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND3B_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__NAND3B_PP_BLACKBOX_V
+
+/**
+ * nand3b: 3-input NAND, first input inverted.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nand3b (
+    Y   ,
+    A_N ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND3B_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__TAP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__TAP_FUNCTIONAL_PP_V
+
+/**
+ * tap: Tap cell with no tap connections (no contacts on metal1).
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__tap (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAP_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SEDFXBP_TB_V
+`define SKY130_FD_SC_LS__SEDFXBP_TB_V
+
+/**
+ * sedfxbp: Scan delay flop, data enable, non-inverted clock,
+ *          complementary outputs.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__sedfxbp.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg DE;
+    reg SCD;
+    reg SCE;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Q;
+    wire Q_N;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D    = 1\'bX;
+        DE   = 1\'bX;
+        SCD  = 1\'bX;
+        SCE  = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   D    = 1\'b0;
+        #40   DE   = 1\'b0;
+        #60   SCD  = 1\'b0;
+        #80   SCE  = 1\'b0;
+        #100  VGND = 1\'b0;
+        #120  VNB  = 1\'b0;
+        #140  VPB  = 1\'b0;
+        #160  VPWR = 1\'b0;
+        #180  D    = 1\'b1;
+        #200  DE   = 1\'b1;
+        #220  SCD  = 1\'b1;
+        #240  SCE  = 1\'b1;
+        #260  VGND = 1\'b1;
+        #280  VNB  = 1\'b1;
+        #300  VPB  = 1\'b1;
+        #320  VPWR = 1\'b1;
+        #340  D    = 1\'b0;
+        #360  DE   = 1\'b0;
+        #380  SCD  = 1\'b0;
+        #400  SCE  = 1\'b0;
+        #420  VGND = 1\'b0;
+        #440  VNB  = 1\'b0;
+        #460  VPB  = 1\'b0;
+        #480  VPWR = 1\'b0;
+        #500  VPWR = 1\'b1;
+        #520  VPB  = 1\'b1;
+        #540  VNB  = 1\'b1;
+        #560  VGND = 1\'b1;
+        #580  SCE  = 1\'b1;
+        #600  SCD  = 1\'b1;
+        #620  DE   = 1\'b1;
+        #640  D    = 1\'b1;
+        #660  VPWR = 1\'bx;
+        #680  VPB  = 1\'bx;
+        #700  VNB  = 1\'bx;
+        #720  VGND = 1\'bx;
+        #740  SCE  = 1\'bx;
+        #760  SCD  = 1\'bx;
+        #780  DE   = 1\'bx;
+        #800  D    = 1\'bx;
+    end
+
+    // Create a clock
+    reg CLK;
+    initial
+    begin
+        CLK = 1\'b0;
+    end
+
+    always
+    begin
+        #5 CLK = ~CLK;
+    end
+
+    sky130_fd_sc_ls__sedfxbp dut (.D(D), .DE(DE), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SEDFXBP_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFRTP_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__SDFRTP_PP_BLACKBOX_V
+
+/**
+ * sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
+ *         single output.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sdfrtp (
+    Q      ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFRTP_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__HA_SYMBOL_V
+`define SKY130_FD_SC_LS__HA_SYMBOL_V
+
+/**
+ * ha: Half adder.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__ha (
+    //# {{data|Data Signals}}
+    input  A   ,
+    input  B   ,
+    output COUT,
+    output SUM
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__HA_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR2_SYMBOL_V
+`define SKY130_FD_SC_LS__NOR2_SYMBOL_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nor2 (
+    //# {{data|Data Signals}}
+    input  A,
+    input  B,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR2_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O31AI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__O31AI_FUNCTIONAL_PP_V
+
+/**
+ * o31ai: 3-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__o31ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A2, A1, A3             );
+    nand                               nand0       (nand0_out_Y      , B1, or0_out            );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O31AI_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O41A_TB_V
+`define SKY130_FD_SC_LS__O41A_TB_V
+
+/**
+ * o41a: 4-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3 | A4) & B1)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o41a.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg A3;
+    reg A4;
+    reg B1;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        A3   = 1\'bX;
+        A4   = 1\'bX;
+        B1   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   A3   = 1\'b0;
+        #80   A4   = 1\'b0;
+        #100  B1   = 1\'b0;
+        #120  VGND = 1\'b0;
+        #140  VNB  = 1\'b0;
+        #160  VPB  = 1\'b0;
+        #180  VPWR = 1\'b0;
+        #200  A1   = 1\'b1;
+        #220  A2   = 1\'b1;
+        #240  A3   = 1\'b1;
+        #260  A4   = 1\'b1;
+        #280  B1   = 1\'b1;
+        #300  VGND = 1\'b1;
+        #320  VNB  = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VPWR = 1\'b1;
+        #380  A1   = 1\'b0;
+        #400  A2   = 1\'b0;
+        #420  A3   = 1\'b0;
+        #440  A4   = 1\'b0;
+        #460  B1   = 1\'b0;
+        #480  VGND = 1\'b0;
+        #500  VNB  = 1\'b0;
+        #520  VPB  = 1\'b0;
+        #540  VPWR = 1\'b0;
+        #560  VPWR = 1\'b1;
+        #580  VPB  = 1\'b1;
+        #600  VNB  = 1\'b1;
+        #620  VGND = 1\'b1;
+        #640  B1   = 1\'b1;
+        #660  A4   = 1\'b1;
+        #680  A3   = 1\'b1;
+        #700  A2   = 1\'b1;
+        #720  A1   = 1\'b1;
+        #740  VPWR = 1\'bx;
+        #760  VPB  = 1\'bx;
+        #780  VNB  = 1\'bx;
+        #800  VGND = 1\'bx;
+        #820  B1   = 1\'bx;
+        #840  A4   = 1\'bx;
+        #860  A3   = 1\'bx;
+        #880  A2   = 1\'bx;
+        #900  A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__o41a dut (.A1(A1), .A2(A2), .A3(A3), .A4(A4), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O41A_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O21BAI_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__O21BAI_FUNCTIONAL_V
+
+/**
+ * o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
+ *         inverted.
+ *
+ *         Y = !((A1 | A2) & !B1_N)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__o21bai (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Local signals
+    wire b          ;
+    wire or0_out    ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    not  not0  (b          , B1_N           );
+    or   or0   (or0_out    , A2, A1         );
+    nand nand0 (nand0_out_Y, b, or0_out     );
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21BAI_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A222O_BLACKBOX_V
+`define SKY130_FD_SC_LS__A222O_BLACKBOX_V
+
+/**
+ * a222o: 2-input AND into all inputs of 3-input OR.
+ *
+ *        X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a222o (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1,
+    C2
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+    input  C2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A222O_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFBBP_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__DFBBP_PP_BLACKBOX_V
+
+/**
+ * dfbbp: Delay flop, inverted set, inverted reset,
+ *        complementary outputs.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dfbbp (
+    Q      ,
+    Q_N    ,
+    D      ,
+    CLK    ,
+    SET_B  ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  CLK    ;
+    input  SET_B  ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFBBP_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__TAP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__TAP_BEHAVIORAL_PP_V
+
+/**
+ * tap: Tap cell with no tap connections (no contacts on metal1).
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__tap (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAP_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__MUX2_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__MUX2_BEHAVIORAL_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+
+`celldefine
+module sky130_fd_sc_ls__mux2 (
+    X ,
+    A0,
+    A1,
+    S
+);
+
+    // Module ports
+    output X ;
+    input  A0;
+    input  A1;
+    input  S ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire mux_2to10_out_X;
+
+    //                            Name       Output           Other arguments
+    sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_2to10_out_X, A0, A1, S      );
+    buf                           buf0      (X              , mux_2to10_out_X);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MUX2_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FILL_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__FILL_PP_SYMBOL_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__fill (
+    //# {{power|Power}}
+    input VPB ,
+    input VPWR,
+    input VGND,
+    input VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FILL_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O21AI_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__O21AI_PP_BLACKBOX_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & B1)
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o21ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21AI_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O32A_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__O32A_BEHAVIORAL_V
+
+/**
+ * o32a: 3-input OR and 2-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__o32a (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out   ;
+    wire or1_out   ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    or  or0  (or0_out   , A2, A1, A3      );
+    or  or1  (or1_out   , B2, B1          );
+    and and0 (and0_out_X, or0_out, or1_out);
+    buf buf0 (X         , and0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O32A_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR4BB_4_V
+`define SKY130_FD_SC_LS__OR4BB_4_V
+
+/**
+ * or4bb: 4-input OR, first two inputs inverted.
+ *
+ * Verilog wrapper for or4bb with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__or4bb.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__or4bb_4 (
+    X   ,
+    A   ,
+    B   ,
+    C_N ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__or4bb base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C_N(C_N),
+        .D_N(D_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__or4bb_4 (
+    X  ,
+    A  ,
+    B  ,
+    C_N,
+    D_N
+);
+
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+    input  D_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__or4bb base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C_N(C_N),
+        .D_N(D_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR4BB_4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__AND4B_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__AND4B_FUNCTIONAL_PP_V
+
+/**
+ * and4b: 4-input AND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__and4b (
+    X   ,
+    A_N ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , A_N                   );
+    and                                and0        (and0_out_X       , not0_out, B, C, D     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND4B_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLYMETAL6S4S_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__DLYMETAL6S4S_BEHAVIORAL_PP_V
+
+/**
+ * dlymetal6s4s: 6-inverter delay with output from 4th inverter on
+ *               horizontal route.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlymetal6s4s (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYMETAL6S4S_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O41A_V
+`define SKY130_FD_SC_LS__O41A_V
+
+/**
+ * o41a: 4-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o41a.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o41a.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o41a.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o41a.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O41A_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFSBP_TB_V
+`define SKY130_FD_SC_LS__SDFSBP_TB_V
+
+/**
+ * sdfsbp: Scan delay flop, inverted set, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__sdfsbp.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg SCD;
+    reg SCE;
+    reg SET_B;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Q;
+    wire Q_N;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D     = 1\'bX;
+        SCD   = 1\'bX;
+        SCE   = 1\'bX;
+        SET_B = 1\'bX;
+        VGND  = 1\'bX;
+        VNB   = 1\'bX;
+        VPB   = 1\'bX;
+        VPWR  = 1\'bX;
+
+        #20   D     = 1\'b0;
+        #40   SCD   = 1\'b0;
+        #60   SCE   = 1\'b0;
+        #80   SET_B = 1\'b0;
+        #100  VGND  = 1\'b0;
+        #120  VNB   = 1\'b0;
+        #140  VPB   = 1\'b0;
+        #160  VPWR  = 1\'b0;
+        #180  D     = 1\'b1;
+        #200  SCD   = 1\'b1;
+        #220  SCE   = 1\'b1;
+        #240  SET_B = 1\'b1;
+        #260  VGND  = 1\'b1;
+        #280  VNB   = 1\'b1;
+        #300  VPB   = 1\'b1;
+        #320  VPWR  = 1\'b1;
+        #340  D     = 1\'b0;
+        #360  SCD   = 1\'b0;
+        #380  SCE   = 1\'b0;
+        #400  SET_B = 1\'b0;
+        #420  VGND  = 1\'b0;
+        #440  VNB   = 1\'b0;
+        #460  VPB   = 1\'b0;
+        #480  VPWR  = 1\'b0;
+        #500  VPWR  = 1\'b1;
+        #520  VPB   = 1\'b1;
+        #540  VNB   = 1\'b1;
+        #560  VGND  = 1\'b1;
+        #580  SET_B = 1\'b1;
+        #600  SCE   = 1\'b1;
+        #620  SCD   = 1\'b1;
+        #640  D     = 1\'b1;
+        #660  VPWR  = 1\'bx;
+        #680  VPB   = 1\'bx;
+        #700  VNB   = 1\'bx;
+        #720  VGND  = 1\'bx;
+        #740  SET_B = 1\'bx;
+        #760  SCE   = 1\'bx;
+        #780  SCD   = 1\'bx;
+        #800  D     = 1\'bx;
+    end
+
+    // Create a clock
+    reg CLK;
+    initial
+    begin
+        CLK = 1\'b0;
+    end
+
+    always
+    begin
+        #5 CLK = ~CLK;
+    end
+
+    sky130_fd_sc_ls__sdfsbp dut (.D(D), .SCD(SCD), .SCE(SCE), .SET_B(SET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFSBP_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O41AI_V
+`define SKY130_FD_SC_LS__O41AI_V
+
+/**
+ * o41ai: 4-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o41ai.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o41ai.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o41ai.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o41ai.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O41AI_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLYMETAL6S6S_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__DLYMETAL6S6S_BEHAVIORAL_V
+
+/**
+ * dlymetal6s6s: 6-inverter delay with output from 6th inverter on
+ *               horizontal route.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__dlymetal6s6s (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYMETAL6S6S_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CONB_SYMBOL_V
+`define SKY130_FD_SC_LS__CONB_SYMBOL_V
+
+/**
+ * conb: Constant value, low, high outputs.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__conb (
+    //# {{data|Data Signals}}
+    output HI,
+    output LO
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CONB_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFRTP_1_V
+`define SKY130_FD_SC_LS__DFRTP_1_V
+
+/**
+ * dfrtp: Delay flop, inverted reset, single output.
+ *
+ * Verilog wrapper for dfrtp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dfrtp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dfrtp_1 (
+    Q      ,
+    CLK    ,
+    D      ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_ls__dfrtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .RESET_B(RESET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dfrtp_1 (
+    Q      ,
+    CLK    ,
+    D      ,
+    RESET_B
+);
+
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__dfrtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .RESET_B(RESET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFRTP_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A31O_V
+`define SKY130_FD_SC_LS__A31O_V
+
+/**
+ * a31o: 3-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a31o.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a31o.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a31o.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a31o.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A31O_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__OR4BB_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__OR4BB_BEHAVIORAL_V
+
+/**
+ * or4bb: 4-input OR, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__or4bb (
+    X  ,
+    A  ,
+    B  ,
+    C_N,
+    D_N
+);
+
+    // Module ports
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+    input  D_N;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nand0_out;
+    wire or0_out_X;
+
+    //   Name   Output     Other arguments
+    nand nand0 (nand0_out, D_N, C_N       );
+    or   or0   (or0_out_X, B, A, nand0_out);
+    buf  buf0  (X        , or0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR4BB_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFBBP_SYMBOL_V
+`define SKY130_FD_SC_LS__SDFBBP_SYMBOL_V
+
+/**
+ * sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
+ *         clock, complementary outputs.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sdfbbp (
+    //# {{data|Data Signals}}
+    input  D      ,
+    output Q      ,
+    output Q_N    ,
+
+    //# {{control|Control Signals}}
+    input  RESET_B,
+    input  SET_B  ,
+
+    //# {{scanchain|Scan Chain}}
+    input  SCD    ,
+    input  SCE    ,
+
+    //# {{clocks|Clocking}}
+    input  CLK
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFBBP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O21A_SYMBOL_V
+`define SKY130_FD_SC_LS__O21A_SYMBOL_V
+
+/**
+ * o21a: 2-input OR into first input of 2-input AND.
+ *
+ *       X = ((A1 | A2) & B1)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o21a (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  B1,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21A_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFXTP_4_V
+`define SKY130_FD_SC_LS__SDFXTP_4_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Verilog wrapper for sdfxtp with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__sdfxtp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sdfxtp_4 (
+    Q   ,
+    CLK ,
+    D   ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__sdfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sdfxtp_4 (
+    Q  ,
+    CLK,
+    D  ,
+    SCD,
+    SCE
+);
+
+    output Q  ;
+    input  CLK;
+    input  D  ;
+    input  SCD;
+    input  SCE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__sdfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFXTP_4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A_N -=> X) = (0:0:0,0:0:0);
+(B +=> X) = (0:0:0,0:0:0);
+(C +=> X) = (0:0:0,0:0:0);
+(D +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKBUF_2_V
+`define SKY130_FD_SC_LS__CLKBUF_2_V
+
+/**
+ * clkbuf: Clock tree buffer.
+ *
+ * Verilog wrapper for clkbuf with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__clkbuf.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__clkbuf_2 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__clkbuf base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__clkbuf_2 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__clkbuf base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKBUF_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__EDFXBP_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__EDFXBP_PP_BLACKBOX_V
+
+/**
+ * edfxbp: Delay flop with loopback enable, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__edfxbp (
+    Q   ,
+    Q_N ,
+    CLK ,
+    D   ,
+    DE  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    output Q_N ;
+    input  CLK ;
+    input  D   ;
+    input  DE  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EDFXBP_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DFF_PR_PP_PG_N_V
+`define SKY130_FD_SC_LS__UDP_DFF_PR_PP_PG_N_V
+
+/**
+ * udp_dff$PR_pp$PG$N: Positive edge triggered D flip-flop with active
+ *                     high
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`include ""./sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.blackbox.v""
+`else
+primitive sky130_fd_sc_ls__udp_dff$PR_pp$PG$N (
+    Q       ,
+    D       ,
+    CLK     ,
+    RESET   ,
+    NOTIFIER,
+    VPWR    ,
+    VGND
+);
+
+    output Q       ;
+    input  D       ;
+    input  CLK     ;
+    input  RESET   ;
+    input  NOTIFIER;
+    input  VPWR    ;
+    input  VGND    ;
+
+    reg Q;
+
+    table
+     //          D           CLK  RESET NOTIFIER VPWR VGND :  Qt : Qt+1
+                 *            b     0      ?      1    0   :  ?  :  -    ; // data event, hold unless CP==x
+                 ?           (?0)   0      ?      1    0   :  ?  :  -    ; // CP => 0, hold
+                 ?            b    (?0)    ?      1    0   :  ?  :  -    ; // R => 0, hold unless CP==x
+                 ?            ?     1      ?      1    0   :  ?  :  0    ; // async reset
+                 0            r     ?      ?      1    0   :  ?  :  0    ; // clock data on CP
+                 1            r     0      ?      1    0   :  ?  :  1    ; // clock data on CP
+                 0           (x1)   ?      ?      1    0   :  0  :  0    ; // possible CP, hold when D==Q==0
+                 1           (x1)   0      ?      1    0   :  1  :  1    ; // possible CP, hold when D==Q==1
+                 0            x     ?      ?      1    0   :  0  :  0    ; // unkown CP, hold when D==Q==0
+                 1            x     0      ?      1    0   :  1  :  1    ; // unkown CP, hold when D==Q==1
+                 ?            b    (?x)    ?      1    0   :  0  :  0    ; // R=>x, hold when Q==0 unless CP==x
+                 ?           (?0)   x      ?      1    0   :  0  :  0    ;
+        // [\'IfDef(functional)\', \'\']                 ?            ?     ?      *      1    0   :  ?  :  -    ; // Q => - on any change on notifier
+        // [\'Else\', \'\']                 ?            ?     ?      *      1    0   :  ?  :  x    ; // Q => X on any change on notifier
+        // [\'EndIfDef(functional)\', \'\']                 ?            ?     ?      ?      *    ?   :  ?  :  x    ; // Q => X on any change on vpwr
+                 ?            ?     ?      ?      ?    *   :  ?  :  x    ; // Q => X on any change on vgnd
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DFF_PR_PP_PG_N_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O2BB2A_BLACKBOX_V
+`define SKY130_FD_SC_LS__O2BB2A_BLACKBOX_V
+
+/**
+ * o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
+ *
+ *         X = (!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o2bb2a (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2BB2A_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
+`define SKY130_FD_SC_LS__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
+
+/**
+ * udp_dlatch$P_pp$PG$N: D-latch, gated standard drive / active high
+ *                       (Q output UDP)
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__udp_dlatch$P_pp$PG$N (
+    Q       ,
+    D       ,
+    GATE    ,
+    NOTIFIER,
+    VPWR    ,
+    VGND
+);
+
+    output Q       ;
+    input  D       ;
+    input  GATE    ;
+    input  NOTIFIER;
+    input  VPWR    ;
+    input  VGND    ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A311O_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__A311O_PP_SYMBOL_V
+
+/**
+ * a311o: 3-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a311o (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  A3  ,
+    input  B1  ,
+    input  C1  ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A311O_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A1 +=> X) = (0:0:0,0:0:0);
+(A2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&!C1&!D1)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&!C1&!D1)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&!C1&!D1)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&!B1&!D1)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&!B1&!D1)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&!B1&!D1)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&!B1&!C1)) (D1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&!B1&!C1)) (D1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&!B1&!C1)) (D1 +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O31AI_V
+`define SKY130_FD_SC_LS__O31AI_V
+
+/**
+ * o31ai: 3-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3) & B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o31ai.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o31ai.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o31ai.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o31ai.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O31AI_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__TAP_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__TAP_PP_SYMBOL_V
+
+/**
+ * tap: Tap cell with no tap connections (no contacts on metal1).
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__tap (
+    //# {{power|Power}}
+    input VPB ,
+    input VPWR,
+    input VGND,
+    input VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAP_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND4B_SYMBOL_V
+`define SKY130_FD_SC_LS__NAND4B_SYMBOL_V
+
+/**
+ * nand4b: 4-input NAND, first input inverted.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nand4b (
+    //# {{data|Data Signals}}
+    input  A_N,
+    input  B  ,
+    input  C  ,
+    input  D  ,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND4B_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O21BAI_2_V
+`define SKY130_FD_SC_LS__O21BAI_2_V
+
+/**
+ * o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
+ *         inverted.
+ *
+ *         Y = !((A1 | A2) & !B1_N)
+ *
+ * Verilog wrapper for o21bai with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o21bai.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o21bai_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o21bai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o21bai_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o21bai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21BAI_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR3B_1_V
+`define SKY130_FD_SC_LS__OR3B_1_V
+
+/**
+ * or3b: 3-input OR, first input inverted.
+ *
+ * Verilog wrapper for or3b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__or3b.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__or3b_1 (
+    X   ,
+    A   ,
+    B   ,
+    C_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__or3b base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C_N(C_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__or3b_1 (
+    X  ,
+    A  ,
+    B  ,
+    C_N
+);
+
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__or3b base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C_N(C_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR3B_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A21BO_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__A21BO_FUNCTIONAL_PP_V
+
+/**
+ * a21bo: 2-input AND into first input of 2-input OR,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 & A2) | (!B1_N))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a21bo (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out        ;
+    wire nand1_out_X      ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out        , A2, A1                 );
+    nand                               nand1       (nand1_out_X      , B1_N, nand0_out        );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nand1_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21BO_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFSBP_2_V
+`define SKY130_FD_SC_LS__SDFSBP_2_V
+
+/**
+ * sdfsbp: Scan delay flop, inverted set, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog wrapper for sdfsbp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__sdfsbp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sdfsbp_2 (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_ls__sdfsbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .SET_B(SET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sdfsbp_2 (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B
+);
+
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__sdfsbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .SET_B(SET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFSBP_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__XNOR3_BLACKBOX_V
+`define SKY130_FD_SC_LS__XNOR3_BLACKBOX_V
+
+/**
+ * xnor3: 3-input exclusive NOR.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__xnor3 (
+    X,
+    A,
+    B,
+    C
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XNOR3_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DFF_P_BLACKBOX_V
+`define SKY130_FD_SC_LS__UDP_DFF_P_BLACKBOX_V
+
+/**
+ * udp_dff$P: Positive edge triggered D flip-flop (Q output UDP).
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__udp_dff$P (
+    Q  ,
+    D  ,
+    CLK
+);
+
+    output Q  ;
+    input  D  ;
+    input  CLK;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DFF_P_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DIODE_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__DIODE_BEHAVIORAL_PP_V
+
+/**
+ * diode: Antenna tie-down diode.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__diode (
+    DIODE,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    input DIODE;
+    input VPWR ;
+    input VGND ;
+    input VPB  ;
+    input VNB  ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DIODE_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFRTP_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__SDFRTP_PP_SYMBOL_V
+
+/**
+ * sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
+ *         single output.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sdfrtp (
+    //# {{data|Data Signals}}
+    input  D      ,
+    output Q      ,
+
+    //# {{control|Control Signals}}
+    input  RESET_B,
+
+    //# {{scanchain|Scan Chain}}
+    input  SCD    ,
+    input  SCE    ,
+
+    //# {{clocks|Clocking}}
+    input  CLK    ,
+
+    //# {{power|Power}}
+    input  VPB    ,
+    input  VPWR   ,
+    input  VGND   ,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFRTP_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR4BB_2_V
+`define SKY130_FD_SC_LS__NOR4BB_2_V
+
+/**
+ * nor4bb: 4-input NOR, first two inputs inverted.
+ *
+ * Verilog wrapper for nor4bb with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nor4bb.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor4bb_2 (
+    Y   ,
+    A   ,
+    B   ,
+    C_N ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nor4bb base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C_N(C_N),
+        .D_N(D_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor4bb_2 (
+    Y  ,
+    A  ,
+    B  ,
+    C_N,
+    D_N
+);
+
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+    input  D_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nor4bb base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C_N(C_N),
+        .D_N(D_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR4BB_2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__AND2B_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__AND2B_BEHAVIORAL_PP_V
+
+/**
+ * and2b: 2-input AND, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__and2b (
+    X   ,
+    A_N ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A_N ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out         ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out         , A_N                   );
+    and                                and0        (and0_out_X       , not0_out, B           );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND2B_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLYMETAL6S2S_TB_V
+`define SKY130_FD_SC_LS__DLYMETAL6S2S_TB_V
+
+/**
+ * dlymetal6s2s: 6-inverter delay with output from 2nd stage on
+ *               horizontal route.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dlymetal6s2s.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   VGND = 1\'b0;
+        #60   VNB  = 1\'b0;
+        #80   VPB  = 1\'b0;
+        #100  VPWR = 1\'b0;
+        #120  A    = 1\'b1;
+        #140  VGND = 1\'b1;
+        #160  VNB  = 1\'b1;
+        #180  VPB  = 1\'b1;
+        #200  VPWR = 1\'b1;
+        #220  A    = 1\'b0;
+        #240  VGND = 1\'b0;
+        #260  VNB  = 1\'b0;
+        #280  VPB  = 1\'b0;
+        #300  VPWR = 1\'b0;
+        #320  VPWR = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VNB  = 1\'b1;
+        #380  VGND = 1\'b1;
+        #400  A    = 1\'b1;
+        #420  VPWR = 1\'bx;
+        #440  VPB  = 1\'bx;
+        #460  VNB  = 1\'bx;
+        #480  VGND = 1\'bx;
+        #500  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__dlymetal6s2s dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYMETAL6S2S_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR3_TB_V
+`define SKY130_FD_SC_LS__OR3_TB_V
+
+/**
+ * or3: 3-input OR.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__or3.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg B;
+    reg C;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        B    = 1\'bX;
+        C    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   B    = 1\'b0;
+        #60   C    = 1\'b0;
+        #80   VGND = 1\'b0;
+        #100  VNB  = 1\'b0;
+        #120  VPB  = 1\'b0;
+        #140  VPWR = 1\'b0;
+        #160  A    = 1\'b1;
+        #180  B    = 1\'b1;
+        #200  C    = 1\'b1;
+        #220  VGND = 1\'b1;
+        #240  VNB  = 1\'b1;
+        #260  VPB  = 1\'b1;
+        #280  VPWR = 1\'b1;
+        #300  A    = 1\'b0;
+        #320  B    = 1\'b0;
+        #340  C    = 1\'b0;
+        #360  VGND = 1\'b0;
+        #380  VNB  = 1\'b0;
+        #400  VPB  = 1\'b0;
+        #420  VPWR = 1\'b0;
+        #440  VPWR = 1\'b1;
+        #460  VPB  = 1\'b1;
+        #480  VNB  = 1\'b1;
+        #500  VGND = 1\'b1;
+        #520  C    = 1\'b1;
+        #540  B    = 1\'b1;
+        #560  A    = 1\'b1;
+        #580  VPWR = 1\'bx;
+        #600  VPB  = 1\'bx;
+        #620  VNB  = 1\'bx;
+        #640  VGND = 1\'bx;
+        #660  C    = 1\'bx;
+        #680  B    = 1\'bx;
+        #700  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__or3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR3_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A311OI_4_V
+`define SKY130_FD_SC_LS__A311OI_4_V
+
+/**
+ * a311oi: 3-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog wrapper for a311oi with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a311oi.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a311oi_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a311oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a311oi_4 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a311oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A311OI_4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__INV_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__INV_FUNCTIONAL_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__inv (
+    Y,
+    A
+);
+
+    // Module ports
+    output Y;
+    input  A;
+
+    // Local signals
+    wire not0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out_Y, A              );
+    buf buf0 (Y         , not0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__INV_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__BUFBUF_SYMBOL_V
+`define SKY130_FD_SC_LS__BUFBUF_SYMBOL_V
+
+/**
+ * bufbuf: Double buffer.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__bufbuf (
+    //# {{data|Data Signals}}
+    input  A,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__BUFBUF_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR4B_1_V
+`define SKY130_FD_SC_LS__OR4B_1_V
+
+/**
+ * or4b: 4-input OR, first input inverted.
+ *
+ * Verilog wrapper for or4b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__or4b.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__or4b_1 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__or4b base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D_N(D_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__or4b_1 (
+    X  ,
+    A  ,
+    B  ,
+    C  ,
+    D_N
+);
+
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C  ;
+    input  D_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__or4b base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D_N(D_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR4B_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLRTN_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__DLRTN_BEHAVIORAL_V
+
+/**
+ * dlrtn: Delay latch, inverted reset, inverted enable, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_pr_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlrtn (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE_N
+);
+
+    // Module ports
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE_N ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire RESET          ;
+    wire intgate        ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire GATE_N_delayed ;
+    wire RESET_delayed  ;
+    wire RESET_B_delayed;
+    wire buf_Q          ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+
+    //                                     Name     Output   Other arguments
+    not                                    not0    (RESET  , RESET_B_delayed                                );
+    not                                    not1    (intgate, GATE_N_delayed                                 );
+    sky130_fd_sc_ls__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q  , D_delayed, intgate, RESET, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1\'b1 ) );
+    assign cond1 = ( awake && ( RESET_B === 1\'b1 ) );
+    buf                                    buf0    (Q      , buf_Q                                          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRTN_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A22O_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__A22O_BEHAVIORAL_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ *       X = ((A1 & A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a22o (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out ;
+    wire and1_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , B1, B2            );
+    and and1 (and1_out , A1, A2            );
+    or  or0  (or0_out_X, and1_out, and0_out);
+    buf buf0 (X        , or0_out_X         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A22O_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR3_V
+`define SKY130_FD_SC_LS__NOR3_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ *       Y = !(A | B | C | !D)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__nor3.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__nor3.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__nor3.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__nor3.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR3_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFSBP_TB_V
+`define SKY130_FD_SC_LS__DFSBP_TB_V
+
+/**
+ * dfsbp: Delay flop, inverted set, complementary outputs.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dfsbp.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg SET_B;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Q;
+    wire Q_N;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D     = 1\'bX;
+        SET_B = 1\'bX;
+        VGND  = 1\'bX;
+        VNB   = 1\'bX;
+        VPB   = 1\'bX;
+        VPWR  = 1\'bX;
+
+        #20   D     = 1\'b0;
+        #40   SET_B = 1\'b0;
+        #60   VGND  = 1\'b0;
+        #80   VNB   = 1\'b0;
+        #100  VPB   = 1\'b0;
+        #120  VPWR  = 1\'b0;
+        #140  D     = 1\'b1;
+        #160  SET_B = 1\'b1;
+        #180  VGND  = 1\'b1;
+        #200  VNB   = 1\'b1;
+        #220  VPB   = 1\'b1;
+        #240  VPWR  = 1\'b1;
+        #260  D     = 1\'b0;
+        #280  SET_B = 1\'b0;
+        #300  VGND  = 1\'b0;
+        #320  VNB   = 1\'b0;
+        #340  VPB   = 1\'b0;
+        #360  VPWR  = 1\'b0;
+        #380  VPWR  = 1\'b1;
+        #400  VPB   = 1\'b1;
+        #420  VNB   = 1\'b1;
+        #440  VGND  = 1\'b1;
+        #460  SET_B = 1\'b1;
+        #480  D     = 1\'b1;
+        #500  VPWR  = 1\'bx;
+        #520  VPB   = 1\'bx;
+        #540  VNB   = 1\'bx;
+        #560  VGND  = 1\'bx;
+        #580  SET_B = 1\'bx;
+        #600  D     = 1\'bx;
+    end
+
+    // Create a clock
+    reg CLK;
+    initial
+    begin
+        CLK = 1\'b0;
+    end
+
+    always
+    begin
+        #5 CLK = ~CLK;
+    end
+
+    sky130_fd_sc_ls__dfsbp dut (.D(D), .SET_B(SET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFSBP_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A -=> Y ) = (0:0:0,0:0:0);  // delays are tris,tfall
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A -=> Y ) = (0:0:0,0:0:0);  // delays are tris,tfall
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O221A_BLACKBOX_V
+`define SKY130_FD_SC_LS__O221A_BLACKBOX_V
+
+/**
+ * o221a: 2-input OR into first two inputs of 3-input AND.
+ *
+ *        X = ((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o221a (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O221A_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR4B_V
+`define SKY130_FD_SC_LS__OR4B_V
+
+/**
+ * or4b: 4-input OR, first input inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__or4b.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__or4b.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__or4b.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__or4b.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR4B_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A21BO_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__A21BO_BEHAVIORAL_PP_V
+
+/**
+ * a21bo: 2-input AND into first input of 2-input OR,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 & A2) | (!B1_N))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a21bo (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out        ;
+    wire nand1_out_X      ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out        , A2, A1                 );
+    nand                               nand1       (nand1_out_X      , B1_N, nand0_out        );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nand1_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21BO_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__BUFBUF_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__BUFBUF_PP_SYMBOL_V
+
+/**
+ * bufbuf: Double buffer.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__bufbuf (
+    //# {{data|Data Signals}}
+    input  A   ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__BUFBUF_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A2BB2OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__A2BB2OI_FUNCTIONAL_PP_V
+
+/**
+ * a2bb2oi: 2-input AND, both inputs inverted, into first input, and
+ *          2-input AND into 2nd input of 2-input NOR.
+ *
+ *          Y = !((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a2bb2oi (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire nor0_out         ;
+    wire nor1_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , B1, B2                );
+    nor                                nor0        (nor0_out         , A1_N, A2_N            );
+    nor                                nor1        (nor1_out_Y       , nor0_out, and0_out    );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor1_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2BB2OI_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O221A_1_V
+`define SKY130_FD_SC_LS__O221A_1_V
+
+/**
+ * o221a: 2-input OR into first two inputs of 3-input AND.
+ *
+ *        X = ((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog wrapper for o221a with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o221a.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o221a_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o221a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o221a_1 (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o221a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O221A_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O21BA_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__O21BA_PP_SYMBOL_V
+
+/**
+ * o21ba: 2-input OR into first input of 2-input AND,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 | A2) & !B1_N)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o21ba (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  B1_N,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21BA_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A1 -=> Y) = (0:0:0,0:0:0);
+(A2 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&C1)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&C1)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2&C1)) (B1 -=> Y) = (0:0:0,0:0:0);
+if ((!A1&A2&B1)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&!A2&B1)) (C1 -=> Y) = (0:0:0,0:0:0);
+if ((A1&A2&B1)) (C1 -=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_MUX_4TO2_SYMBOL_V
+`define SKY130_FD_SC_LS__UDP_MUX_4TO2_SYMBOL_V
+
+/**
+ * udp_mux_4to2: Four to one multiplexer with 2 select controls
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__udp_mux_4to2 (
+    //# {{data|Data Signals}}
+    input  A0,
+    input  A1,
+    input  A2,
+    input  A3,
+    output X ,
+
+    //# {{control|Control Signals}}
+    input  S0,
+    input  S1
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_MUX_4TO2_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__MAJ3_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__MAJ3_BEHAVIORAL_V
+
+/**
+ * maj3: 3-input majority vote.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__maj3 (
+    X,
+    A,
+    B,
+    C
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out  ;
+    wire and0_out ;
+    wire and1_out ;
+    wire or1_out_X;
+
+    //  Name  Output     Other arguments
+    or  or0  (or0_out  , B, A              );
+    and and0 (and0_out , or0_out, C        );
+    and and1 (and1_out , A, B              );
+    or  or1  (or1_out_X, and1_out, and0_out);
+    buf buf0 (X        , or1_out_X         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MAJ3_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O221A_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__O221A_FUNCTIONAL_V
+
+/**
+ * o221a: 2-input OR into first two inputs of 3-input AND.
+ *
+ *        X = ((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__o221a (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Local signals
+    wire or0_out   ;
+    wire or1_out   ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    or  or0  (or0_out   , B2, B1              );
+    or  or1  (or1_out   , A2, A1              );
+    and and0 (and0_out_X, or0_out, or1_out, C1);
+    buf buf0 (X         , and0_out_X          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O221A_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O211AI_TB_V
+`define SKY130_FD_SC_LS__O211AI_TB_V
+
+/**
+ * o211ai: 2-input OR into first input of 3-input NAND.
+ *
+ *         Y = !((A1 | A2) & B1 & C1)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o211ai.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg B1;
+    reg C1;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        B1   = 1\'bX;
+        C1   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   B1   = 1\'b0;
+        #80   C1   = 1\'b0;
+        #100  VGND = 1\'b0;
+        #120  VNB  = 1\'b0;
+        #140  VPB  = 1\'b0;
+        #160  VPWR = 1\'b0;
+        #180  A1   = 1\'b1;
+        #200  A2   = 1\'b1;
+        #220  B1   = 1\'b1;
+        #240  C1   = 1\'b1;
+        #260  VGND = 1\'b1;
+        #280  VNB  = 1\'b1;
+        #300  VPB  = 1\'b1;
+        #320  VPWR = 1\'b1;
+        #340  A1   = 1\'b0;
+        #360  A2   = 1\'b0;
+        #380  B1   = 1\'b0;
+        #400  C1   = 1\'b0;
+        #420  VGND = 1\'b0;
+        #440  VNB  = 1\'b0;
+        #460  VPB  = 1\'b0;
+        #480  VPWR = 1\'b0;
+        #500  VPWR = 1\'b1;
+        #520  VPB  = 1\'b1;
+        #540  VNB  = 1\'b1;
+        #560  VGND = 1\'b1;
+        #580  C1   = 1\'b1;
+        #600  B1   = 1\'b1;
+        #620  A2   = 1\'b1;
+        #640  A1   = 1\'b1;
+        #660  VPWR = 1\'bx;
+        #680  VPB  = 1\'bx;
+        #700  VNB  = 1\'bx;
+        #720  VGND = 1\'bx;
+        #740  C1   = 1\'bx;
+        #760  B1   = 1\'bx;
+        #780  A2   = 1\'bx;
+        #800  A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__o211ai dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O211AI_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A41O_V
+`define SKY130_FD_SC_LS__A41O_V
+
+/**
+ * a41o: 4-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a41o.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a41o.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a41o.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a41o.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A41O_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND2_2_V
+`define SKY130_FD_SC_LS__NAND2_2_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog wrapper for nand2 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nand2.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nand2_2 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nand2 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nand2_2 (
+    Y,
+    A,
+    B
+);
+
+    output Y;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nand2 base (
+        .Y(Y),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND2_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLYGATE4SD3_1_V
+`define SKY130_FD_SC_LS__DLYGATE4SD3_1_V
+
+/**
+ * dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
+ *
+ * Verilog wrapper for dlygate4sd3 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dlygate4sd3.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dlygate4sd3_1 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__dlygate4sd3 base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dlygate4sd3_1 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__dlygate4sd3 base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYGATE4SD3_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFBBP_TB_V
+`define SKY130_FD_SC_LS__SDFBBP_TB_V
+
+/**
+ * sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
+ *         clock, complementary outputs.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__sdfbbp.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg SCD;
+    reg SCE;
+    reg SET_B;
+    reg RESET_B;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Q;
+    wire Q_N;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D       = 1\'bX;
+        RESET_B = 1\'bX;
+        SCD     = 1\'bX;
+        SCE     = 1\'bX;
+        SET_B   = 1\'bX;
+        VGND    = 1\'bX;
+        VNB     = 1\'bX;
+        VPB     = 1\'bX;
+        VPWR    = 1\'bX;
+
+        #20   D       = 1\'b0;
+        #40   RESET_B = 1\'b0;
+        #60   SCD     = 1\'b0;
+        #80   SCE     = 1\'b0;
+        #100  SET_B   = 1\'b0;
+        #120  VGND    = 1\'b0;
+        #140  VNB     = 1\'b0;
+        #160  VPB     = 1\'b0;
+        #180  VPWR    = 1\'b0;
+        #200  D       = 1\'b1;
+        #220  RESET_B = 1\'b1;
+        #240  SCD     = 1\'b1;
+        #260  SCE     = 1\'b1;
+        #280  SET_B   = 1\'b1;
+        #300  VGND    = 1\'b1;
+        #320  VNB     = 1\'b1;
+        #340  VPB     = 1\'b1;
+        #360  VPWR    = 1\'b1;
+        #380  D       = 1\'b0;
+        #400  RESET_B = 1\'b0;
+        #420  SCD     = 1\'b0;
+        #440  SCE     = 1\'b0;
+        #460  SET_B   = 1\'b0;
+        #480  VGND    = 1\'b0;
+        #500  VNB     = 1\'b0;
+        #520  VPB     = 1\'b0;
+        #540  VPWR    = 1\'b0;
+        #560  VPWR    = 1\'b1;
+        #580  VPB     = 1\'b1;
+        #600  VNB     = 1\'b1;
+        #620  VGND    = 1\'b1;
+        #640  SET_B   = 1\'b1;
+        #660  SCE     = 1\'b1;
+        #680  SCD     = 1\'b1;
+        #700  RESET_B = 1\'b1;
+        #720  D       = 1\'b1;
+        #740  VPWR    = 1\'bx;
+        #760  VPB     = 1\'bx;
+        #780  VNB     = 1\'bx;
+        #800  VGND    = 1\'bx;
+        #820  SET_B   = 1\'bx;
+        #840  SCE     = 1\'bx;
+        #860  SCD     = 1\'bx;
+        #880  RESET_B = 1\'bx;
+        #900  D       = 1\'bx;
+    end
+
+    // Create a clock
+    reg CLK;
+    initial
+    begin
+        CLK = 1\'b0;
+    end
+
+    always
+    begin
+        #5 CLK = ~CLK;
+    end
+
+    sky130_fd_sc_ls__sdfbbp dut (.D(D), .SCD(SCD), .SCE(SCE), .SET_B(SET_B), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFBBP_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A -=> Y) = (0:0:0,0:0:0);
+(B -=> Y) = (0:0:0,0:0:0);
+(C -=> Y) = (0:0:0,0:0:0);
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A41OI_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__A41OI_BEHAVIORAL_V
+
+/**
+ * a41oi: 4-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a41oi (
+    Y ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out  ;
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out  , A1, A2, A3, A4 );
+    nor nor0 (nor0_out_Y, B1, and0_out   );
+    buf buf0 (Y         , nor0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A41OI_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A2111O_1_V
+`define SKY130_FD_SC_LS__A2111O_1_V
+
+/**
+ * a2111o: 2-input AND into first input of 4-input OR.
+ *
+ *         X = ((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog wrapper for a2111o with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a2111o.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a2111o_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a2111o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a2111o_1 (
+    X ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a2111o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2111O_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DFBBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__DFBBP_BEHAVIORAL_PP_V
+
+/**
+ * dfbbp: Delay flop, inverted set, inverted reset,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ls__udp_dff_nsr_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dfbbp (
+    Q      ,
+    Q_N    ,
+    D      ,
+    CLK    ,
+    SET_B  ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  CLK    ;
+    input  SET_B  ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire RESET          ;
+    wire SET            ;
+    wire buf_Q          ;
+    wire CLK_delayed    ;
+    wire RESET_B_delayed;
+    wire SET_B_delayed  ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+    wire condb          ;
+
+    //                                   Name  Output  Other arguments
+    not                                  not0 (RESET , RESET_B_delayed                                         );
+    not                                  not1 (SET   , SET_B_delayed                                           );
+    sky130_fd_sc_ls__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, D_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1\'b1 ) );
+    assign cond1 = ( awake && ( SET_B_delayed === 1\'b1 ) );
+    assign condb = ( cond0 & cond1 );
+    buf                                  buf0 (Q     , buf_Q                                                   );
+    not                                  not2 (Q_N   , buf_Q                                                   );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFBBP_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O2111AI_TB_V
+`define SKY130_FD_SC_LS__O2111AI_TB_V
+
+/**
+ * o2111ai: 2-input OR into first input of 4-input NAND.
+ *
+ *          Y = !((A1 | A2) & B1 & C1 & D1)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o2111ai.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg B1;
+    reg C1;
+    reg D1;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        B1   = 1\'bX;
+        C1   = 1\'bX;
+        D1   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   B1   = 1\'b0;
+        #80   C1   = 1\'b0;
+        #100  D1   = 1\'b0;
+        #120  VGND = 1\'b0;
+        #140  VNB  = 1\'b0;
+        #160  VPB  = 1\'b0;
+        #180  VPWR = 1\'b0;
+        #200  A1   = 1\'b1;
+        #220  A2   = 1\'b1;
+        #240  B1   = 1\'b1;
+        #260  C1   = 1\'b1;
+        #280  D1   = 1\'b1;
+        #300  VGND = 1\'b1;
+        #320  VNB  = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VPWR = 1\'b1;
+        #380  A1   = 1\'b0;
+        #400  A2   = 1\'b0;
+        #420  B1   = 1\'b0;
+        #440  C1   = 1\'b0;
+        #460  D1   = 1\'b0;
+        #480  VGND = 1\'b0;
+        #500  VNB  = 1\'b0;
+        #520  VPB  = 1\'b0;
+        #540  VPWR = 1\'b0;
+        #560  VPWR = 1\'b1;
+        #580  VPB  = 1\'b1;
+        #600  VNB  = 1\'b1;
+        #620  VGND = 1\'b1;
+        #640  D1   = 1\'b1;
+        #660  C1   = 1\'b1;
+        #680  B1   = 1\'b1;
+        #700  A2   = 1\'b1;
+        #720  A1   = 1\'b1;
+        #740  VPWR = 1\'bx;
+        #760  VPB  = 1\'bx;
+        #780  VNB  = 1\'bx;
+        #800  VGND = 1\'bx;
+        #820  D1   = 1\'bx;
+        #840  C1   = 1\'bx;
+        #860  B1   = 1\'bx;
+        #880  A2   = 1\'bx;
+        #900  A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__o2111ai dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .D1(D1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2111AI_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A211OI_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__A211OI_PP_SYMBOL_V
+
+/**
+ * a211oi: 2-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | B1 | C1)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a211oi (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  B1  ,
+    input  C1  ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A211OI_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLXBP_1_V
+`define SKY130_FD_SC_LS__DLXBP_1_V
+
+/**
+ * dlxbp: Delay latch, non-inverted enable, complementary outputs.
+ *
+ * Verilog wrapper for dlxbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dlxbp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dlxbp_1 (
+    Q   ,
+    Q_N ,
+    D   ,
+    GATE,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    output Q_N ;
+    input  D   ;
+    input  GATE;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__dlxbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .D(D),
+        .GATE(GATE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dlxbp_1 (
+    Q   ,
+    Q_N ,
+    D   ,
+    GATE
+);
+
+    output Q   ;
+    output Q_N ;
+    input  D   ;
+    input  GATE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__dlxbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .D(D),
+        .GATE(GATE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXBP_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__XNOR3_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__XNOR3_PP_BLACKBOX_V
+
+/**
+ * xnor3: 3-input exclusive NOR.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__xnor3 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XNOR3_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFXBP_TB_V
+`define SKY130_FD_SC_LS__SDFXBP_TB_V
+
+/**
+ * sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__sdfxbp.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg SCD;
+    reg SCE;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Q;
+    wire Q_N;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D    = 1\'bX;
+        SCD  = 1\'bX;
+        SCE  = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   D    = 1\'b0;
+        #40   SCD  = 1\'b0;
+        #60   SCE  = 1\'b0;
+        #80   VGND = 1\'b0;
+        #100  VNB  = 1\'b0;
+        #120  VPB  = 1\'b0;
+        #140  VPWR = 1\'b0;
+        #160  D    = 1\'b1;
+        #180  SCD  = 1\'b1;
+        #200  SCE  = 1\'b1;
+        #220  VGND = 1\'b1;
+        #240  VNB  = 1\'b1;
+        #260  VPB  = 1\'b1;
+        #280  VPWR = 1\'b1;
+        #300  D    = 1\'b0;
+        #320  SCD  = 1\'b0;
+        #340  SCE  = 1\'b0;
+        #360  VGND = 1\'b0;
+        #380  VNB  = 1\'b0;
+        #400  VPB  = 1\'b0;
+        #420  VPWR = 1\'b0;
+        #440  VPWR = 1\'b1;
+        #460  VPB  = 1\'b1;
+        #480  VNB  = 1\'b1;
+        #500  VGND = 1\'b1;
+        #520  SCE  = 1\'b1;
+        #540  SCD  = 1\'b1;
+        #560  D    = 1\'b1;
+        #580  VPWR = 1\'bx;
+        #600  VPB  = 1\'bx;
+        #620  VNB  = 1\'bx;
+        #640  VGND = 1\'bx;
+        #660  SCE  = 1\'bx;
+        #680  SCD  = 1\'bx;
+        #700  D    = 1\'bx;
+    end
+
+    // Create a clock
+    reg CLK;
+    initial
+    begin
+        CLK = 1\'b0;
+    end
+
+    always
+    begin
+        #5 CLK = ~CLK;
+    end
+
+    sky130_fd_sc_ls__sdfxbp dut (.D(D), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFXBP_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND3B_TB_V
+`define SKY130_FD_SC_LS__AND3B_TB_V
+
+/**
+ * and3b: 3-input AND, first input inverted.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__and3b.v""
+
+module top();
+
+    // Inputs are registered
+    reg A_N;
+    reg B;
+    reg C;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A_N  = 1\'bX;
+        B    = 1\'bX;
+        C    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A_N  = 1\'b0;
+        #40   B    = 1\'b0;
+        #60   C    = 1\'b0;
+        #80   VGND = 1\'b0;
+        #100  VNB  = 1\'b0;
+        #120  VPB  = 1\'b0;
+        #140  VPWR = 1\'b0;
+        #160  A_N  = 1\'b1;
+        #180  B    = 1\'b1;
+        #200  C    = 1\'b1;
+        #220  VGND = 1\'b1;
+        #240  VNB  = 1\'b1;
+        #260  VPB  = 1\'b1;
+        #280  VPWR = 1\'b1;
+        #300  A_N  = 1\'b0;
+        #320  B    = 1\'b0;
+        #340  C    = 1\'b0;
+        #360  VGND = 1\'b0;
+        #380  VNB  = 1\'b0;
+        #400  VPB  = 1\'b0;
+        #420  VPWR = 1\'b0;
+        #440  VPWR = 1\'b1;
+        #460  VPB  = 1\'b1;
+        #480  VNB  = 1\'b1;
+        #500  VGND = 1\'b1;
+        #520  C    = 1\'b1;
+        #540  B    = 1\'b1;
+        #560  A_N  = 1\'b1;
+        #580  VPWR = 1\'bx;
+        #600  VPB  = 1\'bx;
+        #620  VNB  = 1\'bx;
+        #640  VGND = 1\'bx;
+        #660  C    = 1\'bx;
+        #680  B    = 1\'bx;
+        #700  A_N  = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__and3b dut (.A_N(A_N), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND3B_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR3_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__NOR3_PP_SYMBOL_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ *       Y = !(A | B | C | !D)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nor3 (
+    //# {{data|Data Signals}}
+    input  A   ,
+    input  B   ,
+    input  C   ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR3_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR4B_TB_V
+`define SKY130_FD_SC_LS__OR4B_TB_V
+
+/**
+ * or4b: 4-input OR, first input inverted.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__or4b.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg B;
+    reg C;
+    reg D_N;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        B    = 1\'bX;
+        C    = 1\'bX;
+        D_N  = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   B    = 1\'b0;
+        #60   C    = 1\'b0;
+        #80   D_N  = 1\'b0;
+        #100  VGND = 1\'b0;
+        #120  VNB  = 1\'b0;
+        #140  VPB  = 1\'b0;
+        #160  VPWR = 1\'b0;
+        #180  A    = 1\'b1;
+        #200  B    = 1\'b1;
+        #220  C    = 1\'b1;
+        #240  D_N  = 1\'b1;
+        #260  VGND = 1\'b1;
+        #280  VNB  = 1\'b1;
+        #300  VPB  = 1\'b1;
+        #320  VPWR = 1\'b1;
+        #340  A    = 1\'b0;
+        #360  B    = 1\'b0;
+        #380  C    = 1\'b0;
+        #400  D_N  = 1\'b0;
+        #420  VGND = 1\'b0;
+        #440  VNB  = 1\'b0;
+        #460  VPB  = 1\'b0;
+        #480  VPWR = 1\'b0;
+        #500  VPWR = 1\'b1;
+        #520  VPB  = 1\'b1;
+        #540  VNB  = 1\'b1;
+        #560  VGND = 1\'b1;
+        #580  D_N  = 1\'b1;
+        #600  C    = 1\'b1;
+        #620  B    = 1\'b1;
+        #640  A    = 1\'b1;
+        #660  VPWR = 1\'bx;
+        #680  VPB  = 1\'bx;
+        #700  VNB  = 1\'bx;
+        #720  VGND = 1\'bx;
+        #740  D_N  = 1\'bx;
+        #760  C    = 1\'bx;
+        #780  B    = 1\'bx;
+        #800  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__or4b dut (.A(A), .B(B), .C(C), .D_N(D_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR4B_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND4B_BLACKBOX_V
+`define SKY130_FD_SC_LS__AND4B_BLACKBOX_V
+
+/**
+ * and4b: 4-input AND, first input inverted.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__and4b (
+    X  ,
+    A_N,
+    B  ,
+    C  ,
+    D
+);
+
+    output X  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND4B_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDLCLKP_1_V
+`define SKY130_FD_SC_LS__SDLCLKP_1_V
+
+/**
+ * sdlclkp: Scan gated clock.
+ *
+ * Verilog wrapper for sdlclkp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__sdlclkp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sdlclkp_1 (
+    GCLK,
+    SCE ,
+    GATE,
+    CLK ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output GCLK;
+    input  SCE ;
+    input  GATE;
+    input  CLK ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__sdlclkp base (
+        .GCLK(GCLK),
+        .SCE(SCE),
+        .GATE(GATE),
+        .CLK(CLK),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sdlclkp_1 (
+    GCLK,
+    SCE ,
+    GATE,
+    CLK
+);
+
+    output GCLK;
+    input  SCE ;
+    input  GATE;
+    input  CLK ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__sdlclkp base (
+        .GCLK(GCLK),
+        .SCE(SCE),
+        .GATE(GATE),
+        .CLK(CLK)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDLCLKP_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__TAPVPWRVGND_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__TAPVPWRVGND_BEHAVIORAL_V
+
+/**
+ * tapvpwrvgnd: Substrate and well tap cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__tapvpwrvgnd ();
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPVPWRVGND_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FAHCIN_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__FAHCIN_PP_SYMBOL_V
+
+/**
+ * fahcin: Full adder, inverted carry in.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__fahcin (
+    //# {{data|Data Signals}}
+    input  A   ,
+    input  B   ,
+    input  CIN ,
+    output COUT,
+    output SUM ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FAHCIN_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND4B_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__AND4B_PP_BLACKBOX_V
+
+/**
+ * and4b: 4-input AND, first input inverted.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__and4b (
+    X   ,
+    A_N ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND4B_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O21A_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__O21A_FUNCTIONAL_V
+
+/**
+ * o21a: 2-input OR into first input of 2-input AND.
+ *
+ *       X = ((A1 | A2) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__o21a (
+    X ,
+    A1,
+    A2,
+    B1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Local signals
+    wire or0_out   ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    or  or0  (or0_out   , A2, A1         );
+    and and0 (and0_out_X, or0_out, B1    );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21A_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DLATCH_P_TB_V
+`define SKY130_FD_SC_LS__UDP_DLATCH_P_TB_V
+
+/**
+ * udp_dlatch$P: D-latch, gated standard drive / active high
+ *               (Q output UDP)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__udp_dlatch_p.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+
+    // Outputs are wires
+    wire Q;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D = 1\'bX;
+
+        #20   D = 1\'b0;
+        #40   D = 1\'b1;
+        #60   D = 1\'b0;
+        #80   D = 1\'b1;
+        #100  D = 1\'bx;
+    end
+
+    // Create a clock
+    reg GATE;
+    initial
+    begin
+        GATE = 1\'b0;
+    end
+
+    always
+    begin
+        #5 GATE = ~GATE;
+    end
+
+    sky130_fd_sc_ls__udp_dlatch$P dut (.D(D), .Q(Q), .GATE(GATE));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DLATCH_P_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DFF_NSR_PP_PG_N_V
+`define SKY130_FD_SC_LS__UDP_DFF_NSR_PP_PG_N_V
+
+/**
+ * udp_dff$NSR_pp$PG$N: Negative edge triggered D flip-flop
+ *                      (Q output UDP) with both active high reset and
+ *                      set (set dominate). Includes VPWR and VGND
+ *                      power pins and notifier pin.
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`include ""./sky130_fd_sc_ls__udp_dff_nsr_pp_pg_n.blackbox.v""
+`else
+primitive sky130_fd_sc_ls__udp_dff$NSR_pp$PG$N (
+    Q       ,
+    SET     ,
+    RESET   ,
+    CLK_N   ,
+    D       ,
+    NOTIFIER,
+    VPWR    ,
+    VGND
+);
+
+    output Q       ;
+    input  SET     ;
+    input  RESET   ;
+    input  CLK_N   ;
+    input  D       ;
+    input  NOTIFIER;
+    input  VPWR    ;
+    input  VGND    ;
+
+    reg Q;
+
+    table
+     //         SET          RESET CLK_N  D  NOTIFIER VPWR VGND :  Qt : Qt+1
+                 0             1     b    ?     ?      1    0   :  ?  :  0    ; // Asserting reset
+                 0             *     ?    ?     ?      1    0   :  0  :  0    ; // Changing reset
+                 1             ?     b    ?     ?      1    0   :  ?  :  1    ; // Asserting set  (dominates reset)
+                 *             0     ?    ?     ?      1    0   :  1  :  1    ; // Changing set
+                 1             ?     n    ?     ?      1    0   :  1  :  1    ;
+                 ?             1     n    ?     ?      1    0   :  0  :  0    ;
+                 x             ?     n    ?     ?      1    0   :  1  :  1    ;
+                 ?             x     n    ?     ?      1    0   :  0  :  0    ;
+                 0             ?    (01)  0     ?      1    0   :  ?  :  0    ; // rising clock
+                 ?             0    (01)  1     ?      1    0   :  ?  :  1    ; // rising clock
+                 0             ?     p    0     ?      1    0   :  0  :  0    ; // potential rising clock
+                 ?             0     p    1     ?      1    0   :  1  :  1    ; // potential rising clock
+                 0             ?     x    0     ?      1    0   :  1  :  x    ;
+                 ?             0     x    1     ?      1    0   :  0  :  x    ;
+                 0             0     n    ?     ?      1    0   :  ?  :  -    ; // Clock falling register output does not change
+                 0             0     ?    *     ?      1    0   :  ?  :  -    ; // Changing Data
+        // [\'IfDef(functional)\', \'\']                 ?             ?     ?    ?     *      1    0   :  ?  :  -    ; // go to - on notify
+        // [\'Else\', \'\']                 ?             ?     ?    ?     *      1    0   :  ?  :  X    ; // go to X on notify
+        // [\'EndIfDef(functional)\', \'\']                 ?             ?     ?    ?     ?      *    0   :  ?  :  X    ; // any change on vpwr
+                 ?             ?     ?    ?     ?      ?    *   :  ?  :  X    ; // any change on vgnd
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DFF_NSR_PP_PG_N_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A41O_2_V
+`define SKY130_FD_SC_LS__A41O_2_V
+
+/**
+ * a41o: 4-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog wrapper for a41o with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a41o.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a41o_2 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a41o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a41o_2 (
+    X ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a41o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A41O_2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NAND4BB_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__NAND4BB_BEHAVIORAL_PP_V
+
+/**
+ * nand4bb: 4-input NAND, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__nand4bb (
+    Y   ,
+    A_N ,
+    B_N ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A_N ;
+    input  B_N ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out        ;
+    wire or0_out_Y        ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out        , D, C                 );
+    or                                 or0         (or0_out_Y        , B_N, A_N, nand0_out  );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND4BB_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLRBN_TB_V
+`define SKY130_FD_SC_LS__DLRBN_TB_V
+
+/**
+ * dlrbn: Delay latch, inverted reset, inverted enable,
+ *        complementary outputs.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dlrbn.v""
+
+module top();
+
+    // Inputs are registered
+    reg RESET_B;
+    reg D;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Q;
+    wire Q_N;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D       = 1\'bX;
+        RESET_B = 1\'bX;
+        VGND    = 1\'bX;
+        VNB     = 1\'bX;
+        VPB     = 1\'bX;
+        VPWR    = 1\'bX;
+
+        #20   D       = 1\'b0;
+        #40   RESET_B = 1\'b0;
+        #60   VGND    = 1\'b0;
+        #80   VNB     = 1\'b0;
+        #100  VPB     = 1\'b0;
+        #120  VPWR    = 1\'b0;
+        #140  D       = 1\'b1;
+        #160  RESET_B = 1\'b1;
+        #180  VGND    = 1\'b1;
+        #200  VNB     = 1\'b1;
+        #220  VPB     = 1\'b1;
+        #240  VPWR    = 1\'b1;
+        #260  D       = 1\'b0;
+        #280  RESET_B = 1\'b0;
+        #300  VGND    = 1\'b0;
+        #320  VNB     = 1\'b0;
+        #340  VPB     = 1\'b0;
+        #360  VPWR    = 1\'b0;
+        #380  VPWR    = 1\'b1;
+        #400  VPB     = 1\'b1;
+        #420  VNB     = 1\'b1;
+        #440  VGND    = 1\'b1;
+        #460  RESET_B = 1\'b1;
+        #480  D       = 1\'b1;
+        #500  VPWR    = 1\'bx;
+        #520  VPB     = 1\'bx;
+        #540  VNB     = 1\'bx;
+        #560  VGND    = 1\'bx;
+        #580  RESET_B = 1\'bx;
+        #600  D       = 1\'bx;
+    end
+
+    // Create a clock
+    reg GATE_N;
+    initial
+    begin
+        GATE_N = 1\'b0;
+    end
+
+    always
+    begin
+        #5 GATE_N = ~GATE_N;
+    end
+
+    sky130_fd_sc_ls__dlrbn dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .GATE_N(GATE_N));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRBN_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__EDFXTP_1_V
+`define SKY130_FD_SC_LS__EDFXTP_1_V
+
+/**
+ * edfxtp: Delay flop with loopback enable, non-inverted clock,
+ *         single output.
+ *
+ * Verilog wrapper for edfxtp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__edfxtp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__edfxtp_1 (
+    Q   ,
+    CLK ,
+    D   ,
+    DE  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  DE  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__edfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .DE(DE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__edfxtp_1 (
+    Q  ,
+    CLK,
+    D  ,
+    DE
+);
+
+    output Q  ;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__edfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .DE(DE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EDFXTP_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A22O_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__A22O_PP_BLACKBOX_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ *       X = ((A1 & A2) | (B1 & B2))
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a22o (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A22O_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND3_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__AND3_PP_SYMBOL_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__and3 (
+    //# {{data|Data Signals}}
+    input  A   ,
+    input  B   ,
+    input  C   ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND3_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A221OI_1_V
+`define SKY130_FD_SC_LS__A221OI_1_V
+
+/**
+ * a221oi: 2-input AND into first two inputs of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog wrapper for a221oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a221oi.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a221oi_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a221oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a221oi_1 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a221oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A221OI_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR2_4_V
+`define SKY130_FD_SC_LS__OR2_4_V
+
+/**
+ * or2: 2-input OR.
+ *
+ * Verilog wrapper for or2 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__or2.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__or2_4 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__or2 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__or2_4 (
+    X,
+    A,
+    B
+);
+
+    output X;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__or2 base (
+        .X(X),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR2_4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A41O_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__A41O_BEHAVIORAL_PP_V
+
+/**
+ * a41o: 4-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a41o (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A1, A2, A3, A4       );
+    or                                 or0         (or0_out_X        , and0_out, B1         );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A41O_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFSTP_SYMBOL_V
+`define SKY130_FD_SC_LS__SDFSTP_SYMBOL_V
+
+/**
+ * sdfstp: Scan delay flop, inverted set, non-inverted clock,
+ *         single output.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sdfstp (
+    //# {{data|Data Signals}}
+    input  D    ,
+    output Q    ,
+
+    //# {{control|Control Signals}}
+    input  SET_B,
+
+    //# {{scanchain|Scan Chain}}
+    input  SCD  ,
+    input  SCE  ,
+
+    //# {{clocks|Clocking}}
+    input  CLK
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFSTP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__EBUFN_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__EBUFN_PP_BLACKBOX_V
+
+/**
+ * ebufn: Tri-state buffer, negative enable.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__ebufn (
+    Z   ,
+    A   ,
+    TE_B,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EBUFN_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD1_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__CLKDLYINV5SD1_PP_SYMBOL_V
+
+/**
+ * clkdlyinv5sd1: Clock Delay Inverter 5-stage 0.15um length inner
+ *                stage gate.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__clkdlyinv5sd1 (
+    //# {{data|Data Signals}}
+    input  A   ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV5SD1_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A311OI_TB_V
+`define SKY130_FD_SC_LS__A311OI_TB_V
+
+/**
+ * a311oi: 3-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2 & A3) | B1 | C1)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a311oi.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg A3;
+    reg B1;
+    reg C1;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        A3   = 1\'bX;
+        B1   = 1\'bX;
+        C1   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   A3   = 1\'b0;
+        #80   B1   = 1\'b0;
+        #100  C1   = 1\'b0;
+        #120  VGND = 1\'b0;
+        #140  VNB  = 1\'b0;
+        #160  VPB  = 1\'b0;
+        #180  VPWR = 1\'b0;
+        #200  A1   = 1\'b1;
+        #220  A2   = 1\'b1;
+        #240  A3   = 1\'b1;
+        #260  B1   = 1\'b1;
+        #280  C1   = 1\'b1;
+        #300  VGND = 1\'b1;
+        #320  VNB  = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VPWR = 1\'b1;
+        #380  A1   = 1\'b0;
+        #400  A2   = 1\'b0;
+        #420  A3   = 1\'b0;
+        #440  B1   = 1\'b0;
+        #460  C1   = 1\'b0;
+        #480  VGND = 1\'b0;
+        #500  VNB  = 1\'b0;
+        #520  VPB  = 1\'b0;
+        #540  VPWR = 1\'b0;
+        #560  VPWR = 1\'b1;
+        #580  VPB  = 1\'b1;
+        #600  VNB  = 1\'b1;
+        #620  VGND = 1\'b1;
+        #640  C1   = 1\'b1;
+        #660  B1   = 1\'b1;
+        #680  A3   = 1\'b1;
+        #700  A2   = 1\'b1;
+        #720  A1   = 1\'b1;
+        #740  VPWR = 1\'bx;
+        #760  VPB  = 1\'bx;
+        #780  VNB  = 1\'bx;
+        #800  VGND = 1\'bx;
+        #820  C1   = 1\'bx;
+        #840  B1   = 1\'bx;
+        #860  A3   = 1\'bx;
+        #880  A2   = 1\'bx;
+        #900  A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__a311oi dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A311OI_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O2BB2A_1_V
+`define SKY130_FD_SC_LS__O2BB2A_1_V
+
+/**
+ * o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
+ *
+ *         X = (!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o2bb2a with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o2bb2a.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o2bb2a_1 (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o2bb2a base (
+        .X(X),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o2bb2a_1 (
+    X   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    output X   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o2bb2a base (
+        .X(X),
+        .A1_N(A1_N),
+        .A2_N(A2_N),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2BB2A_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O2111A_V
+`define SKY130_FD_SC_LS__O2111A_V
+
+/**
+ * o2111a: 2-input OR into first input of 4-input AND.
+ *
+ *         X = ((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o2111a.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o2111a.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o2111a.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o2111a.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2111A_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFBBN_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__DFBBN_PP_SYMBOL_V
+
+/**
+ * dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
+ *        complementary outputs.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dfbbn (
+    //# {{data|Data Signals}}
+    input  D      ,
+    output Q      ,
+    output Q_N    ,
+
+    //# {{control|Control Signals}}
+    input  RESET_B,
+    input  SET_B  ,
+
+    //# {{clocks|Clocking}}
+    input  CLK_N  ,
+
+    //# {{power|Power}}
+    input  VPB    ,
+    input  VPWR   ,
+    input  VGND   ,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFBBN_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__EINVN_BLACKBOX_V
+`define SKY130_FD_SC_LS__EINVN_BLACKBOX_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__einvn (
+    Z   ,
+    A   ,
+    TE_B
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EINVN_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND3B_2_V
+`define SKY130_FD_SC_LS__NAND3B_2_V
+
+/**
+ * nand3b: 3-input NAND, first input inverted.
+ *
+ * Verilog wrapper for nand3b with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nand3b.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nand3b_2 (
+    Y   ,
+    A_N ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A_N ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nand3b base (
+        .Y(Y),
+        .A_N(A_N),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nand3b_2 (
+    Y  ,
+    A_N,
+    B  ,
+    C
+);
+
+    output Y  ;
+    input  A_N;
+    input  B  ;
+    input  C  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nand3b base (
+        .Y(Y),
+        .A_N(A_N),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND3B_2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A2BB2OI_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__A2BB2OI_FUNCTIONAL_V
+
+/**
+ * a2bb2oi: 2-input AND, both inputs inverted, into first input, and
+ *          2-input AND into 2nd input of 2-input NOR.
+ *
+ *          Y = !((!A1 & !A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a2bb2oi (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    // Module ports
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Local signals
+    wire and0_out  ;
+    wire nor0_out  ;
+    wire nor1_out_Y;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out  , B1, B2            );
+    nor nor0 (nor0_out  , A1_N, A2_N        );
+    nor nor1 (nor1_out_Y, nor0_out, and0_out);
+    buf buf0 (Y         , nor1_out_Y        );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2BB2OI_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A32O_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__A32O_FUNCTIONAL_V
+
+/**
+ * a32o: 3-input AND into first input, and 2-input AND into
+ *       2nd input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a32o (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Local signals
+    wire and0_out ;
+    wire and1_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , A3, A1, A2        );
+    and and1 (and1_out , B1, B2            );
+    or  or0  (or0_out_X, and1_out, and0_out);
+    buf buf0 (X        , or0_out_X         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A32O_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O32A_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__O32A_PP_SYMBOL_V
+
+/**
+ * o32a: 3-input OR and 2-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o32a (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  A3  ,
+    input  B1  ,
+    input  B2  ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O32A_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND2B_1_V
+`define SKY130_FD_SC_LS__AND2B_1_V
+
+/**
+ * and2b: 2-input AND, first input inverted.
+ *
+ * Verilog wrapper for and2b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__and2b.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__and2b_1 (
+    X   ,
+    A_N ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A_N ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__and2b base (
+        .X(X),
+        .A_N(A_N),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__and2b_1 (
+    X  ,
+    A_N,
+    B
+);
+
+    output X  ;
+    input  A_N;
+    input  B  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__and2b base (
+        .X(X),
+        .A_N(A_N),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND2B_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O21BAI_1_V
+`define SKY130_FD_SC_LS__O21BAI_1_V
+
+/**
+ * o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
+ *         inverted.
+ *
+ *         Y = !((A1 | A2) & !B1_N)
+ *
+ * Verilog wrapper for o21bai with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o21bai.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o21bai_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o21bai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o21bai_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o21bai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1_N(B1_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21BAI_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__BUFINV_V
+`define SKY130_FD_SC_LS__BUFINV_V
+
+/**
+ * bufinv: Buffer followed by inverter.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__bufinv.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__bufinv.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__bufinv.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__bufinv.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__BUFINV_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A221OI_2_V
+`define SKY130_FD_SC_LS__A221OI_2_V
+
+/**
+ * a221oi: 2-input AND into first two inputs of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog wrapper for a221oi with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a221oi.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a221oi_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a221oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a221oi_2 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a221oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A221OI_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR4B_BLACKBOX_V
+`define SKY130_FD_SC_LS__NOR4B_BLACKBOX_V
+
+/**
+ * nor4b: 4-input NOR, first input inverted.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nor4b (
+    Y  ,
+    A  ,
+    B  ,
+    C  ,
+    D_N
+);
+
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C  ;
+    input  D_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR4B_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND4_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__NAND4_PP_BLACKBOX_V
+
+/**
+ * nand4: 4-input NAND.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nand4 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND4_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__EDFXBP_TB_V
+`define SKY130_FD_SC_LS__EDFXBP_TB_V
+
+/**
+ * edfxbp: Delay flop with loopback enable, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__edfxbp.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg DE;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Q;
+    wire Q_N;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D    = 1\'bX;
+        DE   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   D    = 1\'b0;
+        #40   DE   = 1\'b0;
+        #60   VGND = 1\'b0;
+        #80   VNB  = 1\'b0;
+        #100  VPB  = 1\'b0;
+        #120  VPWR = 1\'b0;
+        #140  D    = 1\'b1;
+        #160  DE   = 1\'b1;
+        #180  VGND = 1\'b1;
+        #200  VNB  = 1\'b1;
+        #220  VPB  = 1\'b1;
+        #240  VPWR = 1\'b1;
+        #260  D    = 1\'b0;
+        #280  DE   = 1\'b0;
+        #300  VGND = 1\'b0;
+        #320  VNB  = 1\'b0;
+        #340  VPB  = 1\'b0;
+        #360  VPWR = 1\'b0;
+        #380  VPWR = 1\'b1;
+        #400  VPB  = 1\'b1;
+        #420  VNB  = 1\'b1;
+        #440  VGND = 1\'b1;
+        #460  DE   = 1\'b1;
+        #480  D    = 1\'b1;
+        #500  VPWR = 1\'bx;
+        #520  VPB  = 1\'bx;
+        #540  VNB  = 1\'bx;
+        #560  VGND = 1\'bx;
+        #580  DE   = 1\'bx;
+        #600  D    = 1\'bx;
+    end
+
+    // Create a clock
+    reg CLK;
+    initial
+    begin
+        CLK = 1\'b0;
+    end
+
+    always
+    begin
+        #5 CLK = ~CLK;
+    end
+
+    sky130_fd_sc_ls__edfxbp dut (.D(D), .DE(DE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EDFXBP_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SEDFXTP_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__SEDFXTP_BEHAVIORAL_V
+
+/**
+ * sedfxtp: Scan delay flop, data enable, non-inverted clock,
+ *          single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+`include ""../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__sedfxtp (
+    Q  ,
+    CLK,
+    D  ,
+    DE ,
+    SCD,
+    SCE
+);
+
+    // Module ports
+    output Q  ;
+    input  CLK;
+    input  D  ;
+    input  DE ;
+    input  SCD;
+    input  SCE;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q      ;
+    reg  notifier   ;
+    wire D_delayed  ;
+    wire DE_delayed ;
+    wire SCD_delayed;
+    wire SCE_delayed;
+    wire CLK_delayed;
+    wire mux_out    ;
+    wire de_d       ;
+    wire awake      ;
+    wire cond1      ;
+    wire cond2      ;
+    wire cond3      ;
+
+    //                                 Name       Output   Other arguments
+    sky130_fd_sc_ls__udp_mux_2to1      mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed            );
+    sky130_fd_sc_ls__udp_mux_2to1      mux_2to11 (de_d   , buf_Q, D_delayed, DE_delayed              );
+    sky130_fd_sc_ls__udp_dff$P_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    assign cond1 = ( awake && ( SCE_delayed === 1\'b0 ) && ( DE_delayed === 1\'b1 ) );
+    assign cond2 = ( awake && ( SCE_delayed === 1\'b1 ) );
+    assign cond3 = ( awake && ( DE_delayed === 1\'b1 ) && ( D_delayed !== SCD_delayed ) );
+    buf                                buf0      (Q      , buf_Q                                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SEDFXTP_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A21BOI_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__A21BOI_PP_BLACKBOX_V
+
+/**
+ * a21boi: 2-input AND into first input of 2-input NOR,
+ *         2nd input inverted.
+ *
+ *         Y = !((A1 & A2) | (!B1_N))
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a21boi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21BOI_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLXBP_V
+`define SKY130_FD_SC_LS__DLXBP_V
+
+/**
+ * dlxbp: Delay latch, non-inverted enable, complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlxbp.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlxbp.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlxbp.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlxbp.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXBP_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR3B_1_V
+`define SKY130_FD_SC_LS__NOR3B_1_V
+
+/**
+ * nor3b: 3-input NOR, first input inverted.
+ *
+ *        Y = (!(A | B)) & !C)
+ *
+ * Verilog wrapper for nor3b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nor3b.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor3b_1 (
+    Y   ,
+    A   ,
+    B   ,
+    C_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nor3b base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C_N(C_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor3b_1 (
+    Y  ,
+    A  ,
+    B  ,
+    C_N
+);
+
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nor3b base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C_N(C_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR3B_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND4BB_TB_V
+`define SKY130_FD_SC_LS__AND4BB_TB_V
+
+/**
+ * and4bb: 4-input AND, first two inputs inverted.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__and4bb.v""
+
+module top();
+
+    // Inputs are registered
+    reg A_N;
+    reg B_N;
+    reg C;
+    reg D;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A_N  = 1\'bX;
+        B_N  = 1\'bX;
+        C    = 1\'bX;
+        D    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A_N  = 1\'b0;
+        #40   B_N  = 1\'b0;
+        #60   C    = 1\'b0;
+        #80   D    = 1\'b0;
+        #100  VGND = 1\'b0;
+        #120  VNB  = 1\'b0;
+        #140  VPB  = 1\'b0;
+        #160  VPWR = 1\'b0;
+        #180  A_N  = 1\'b1;
+        #200  B_N  = 1\'b1;
+        #220  C    = 1\'b1;
+        #240  D    = 1\'b1;
+        #260  VGND = 1\'b1;
+        #280  VNB  = 1\'b1;
+        #300  VPB  = 1\'b1;
+        #320  VPWR = 1\'b1;
+        #340  A_N  = 1\'b0;
+        #360  B_N  = 1\'b0;
+        #380  C    = 1\'b0;
+        #400  D    = 1\'b0;
+        #420  VGND = 1\'b0;
+        #440  VNB  = 1\'b0;
+        #460  VPB  = 1\'b0;
+        #480  VPWR = 1\'b0;
+        #500  VPWR = 1\'b1;
+        #520  VPB  = 1\'b1;
+        #540  VNB  = 1\'b1;
+        #560  VGND = 1\'b1;
+        #580  D    = 1\'b1;
+        #600  C    = 1\'b1;
+        #620  B_N  = 1\'b1;
+        #640  A_N  = 1\'b1;
+        #660  VPWR = 1\'bx;
+        #680  VPB  = 1\'bx;
+        #700  VNB  = 1\'bx;
+        #720  VGND = 1\'bx;
+        #740  D    = 1\'bx;
+        #760  C    = 1\'bx;
+        #780  B_N  = 1\'bx;
+        #800  A_N  = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__and4bb dut (.A_N(A_N), .B_N(B_N), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND4BB_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDLCLKP_SYMBOL_V
+`define SKY130_FD_SC_LS__SDLCLKP_SYMBOL_V
+
+/**
+ * sdlclkp: Scan gated clock.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sdlclkp (
+    //# {{scanchain|Scan Chain}}
+    input  SCE ,
+
+    //# {{clocks|Clocking}}
+    input  CLK ,
+    input  GATE,
+    output GCLK
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDLCLKP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFXBP_SYMBOL_V
+`define SKY130_FD_SC_LS__DFXBP_SYMBOL_V
+
+/**
+ * dfxbp: Delay flop, complementary outputs.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dfxbp (
+    //# {{data|Data Signals}}
+    input  D  ,
+    output Q  ,
+    output Q_N,
+
+    //# {{clocks|Clocking}}
+    input  CLK
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFXBP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A311O_SYMBOL_V
+`define SKY130_FD_SC_LS__A311O_SYMBOL_V
+
+/**
+ * a311o: 3-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a311o (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  A3,
+    input  B1,
+    input  C1,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A311O_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLYGATE4SD1_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__DLYGATE4SD1_PP_BLACKBOX_V
+
+/**
+ * dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlygate4sd1 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYGATE4SD1_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFRBP_TB_V
+`define SKY130_FD_SC_LS__DFRBP_TB_V
+
+/**
+ * dfrbp: Delay flop, inverted reset, complementary outputs.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dfrbp.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg RESET_B;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Q;
+    wire Q_N;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D       = 1\'bX;
+        RESET_B = 1\'bX;
+        VGND    = 1\'bX;
+        VNB     = 1\'bX;
+        VPB     = 1\'bX;
+        VPWR    = 1\'bX;
+
+        #20   D       = 1\'b0;
+        #40   RESET_B = 1\'b0;
+        #60   VGND    = 1\'b0;
+        #80   VNB     = 1\'b0;
+        #100  VPB     = 1\'b0;
+        #120  VPWR    = 1\'b0;
+        #140  D       = 1\'b1;
+        #160  RESET_B = 1\'b1;
+        #180  VGND    = 1\'b1;
+        #200  VNB     = 1\'b1;
+        #220  VPB     = 1\'b1;
+        #240  VPWR    = 1\'b1;
+        #260  D       = 1\'b0;
+        #280  RESET_B = 1\'b0;
+        #300  VGND    = 1\'b0;
+        #320  VNB     = 1\'b0;
+        #340  VPB     = 1\'b0;
+        #360  VPWR    = 1\'b0;
+        #380  VPWR    = 1\'b1;
+        #400  VPB     = 1\'b1;
+        #420  VNB     = 1\'b1;
+        #440  VGND    = 1\'b1;
+        #460  RESET_B = 1\'b1;
+        #480  D       = 1\'b1;
+        #500  VPWR    = 1\'bx;
+        #520  VPB     = 1\'bx;
+        #540  VNB     = 1\'bx;
+        #560  VGND    = 1\'bx;
+        #580  RESET_B = 1\'bx;
+        #600  D       = 1\'bx;
+    end
+
+    // Create a clock
+    reg CLK;
+    initial
+    begin
+        CLK = 1\'b0;
+    end
+
+    always
+    begin
+        #5 CLK = ~CLK;
+    end
+
+    sky130_fd_sc_ls__dfrbp dut (.D(D), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFRBP_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__MAJ3_2_V
+`define SKY130_FD_SC_LS__MAJ3_2_V
+
+/**
+ * maj3: 3-input majority vote.
+ *
+ * Verilog wrapper for maj3 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__maj3.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__maj3_2 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__maj3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__maj3_2 (
+    X,
+    A,
+    B,
+    C
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__maj3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MAJ3_2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O32A_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__O32A_FUNCTIONAL_V
+
+/**
+ * o32a: 3-input OR and 2-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__o32a (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Local signals
+    wire or0_out   ;
+    wire or1_out   ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    or  or0  (or0_out   , A2, A1, A3      );
+    or  or1  (or1_out   , B2, B1          );
+    and and0 (and0_out_X, or0_out, or1_out);
+    buf buf0 (X         , and0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O32A_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__BUF_BLACKBOX_V
+`define SKY130_FD_SC_LS__BUF_BLACKBOX_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__buf (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__BUF_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND2B_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__NAND2B_PP_SYMBOL_V
+
+/**
+ * nand2b: 2-input NAND, first input inverted.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nand2b (
+    //# {{data|Data Signals}}
+    input  A_N ,
+    input  B   ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND2B_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A311O_4_V
+`define SKY130_FD_SC_LS__A311O_4_V
+
+/**
+ * a311o: 3-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog wrapper for a311o with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a311o.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a311o_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a311o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a311o_4 (
+    X ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a311o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A311O_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DFF_NSR_SYMBOL_V
+`define SKY130_FD_SC_LS__UDP_DFF_NSR_SYMBOL_V
+
+/**
+ * udp_dff$NSR: Negative edge triggered D flip-flop (Q output UDP)
+ *              with both active high reset and set (set dominate).
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__udp_dff$NSR (
+    //# {{data|Data Signals}}
+    input  D    ,
+    output Q    ,
+
+    //# {{control|Control Signals}}
+    input  RESET,
+    input  SET  ,
+
+    //# {{clocks|Clocking}}
+    input  CLK_N
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DFF_NSR_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NOR3_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__NOR3_FUNCTIONAL_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ *       Y = !(A | B | C | !D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__nor3 (
+    Y,
+    A,
+    B,
+    C
+);
+
+    // Module ports
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+
+    // Local signals
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    nor nor0 (nor0_out_Y, C, A, B        );
+    buf buf0 (Y         , nor0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR3_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A311O_TB_V
+`define SKY130_FD_SC_LS__A311O_TB_V
+
+/**
+ * a311o: 3-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2 & A3) | B1 | C1)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a311o.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg A3;
+    reg B1;
+    reg C1;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        A3   = 1\'bX;
+        B1   = 1\'bX;
+        C1   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   A3   = 1\'b0;
+        #80   B1   = 1\'b0;
+        #100  C1   = 1\'b0;
+        #120  VGND = 1\'b0;
+        #140  VNB  = 1\'b0;
+        #160  VPB  = 1\'b0;
+        #180  VPWR = 1\'b0;
+        #200  A1   = 1\'b1;
+        #220  A2   = 1\'b1;
+        #240  A3   = 1\'b1;
+        #260  B1   = 1\'b1;
+        #280  C1   = 1\'b1;
+        #300  VGND = 1\'b1;
+        #320  VNB  = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VPWR = 1\'b1;
+        #380  A1   = 1\'b0;
+        #400  A2   = 1\'b0;
+        #420  A3   = 1\'b0;
+        #440  B1   = 1\'b0;
+        #460  C1   = 1\'b0;
+        #480  VGND = 1\'b0;
+        #500  VNB  = 1\'b0;
+        #520  VPB  = 1\'b0;
+        #540  VPWR = 1\'b0;
+        #560  VPWR = 1\'b1;
+        #580  VPB  = 1\'b1;
+        #600  VNB  = 1\'b1;
+        #620  VGND = 1\'b1;
+        #640  C1   = 1\'b1;
+        #660  B1   = 1\'b1;
+        #680  A3   = 1\'b1;
+        #700  A2   = 1\'b1;
+        #720  A1   = 1\'b1;
+        #740  VPWR = 1\'bx;
+        #760  VPB  = 1\'bx;
+        #780  VNB  = 1\'bx;
+        #800  VGND = 1\'bx;
+        #820  C1   = 1\'bx;
+        #840  B1   = 1\'bx;
+        #860  A3   = 1\'bx;
+        #880  A2   = 1\'bx;
+        #900  A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__a311o dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A311O_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DFF_PR_PP_PG_N_SYMBOL_V
+`define SKY130_FD_SC_LS__UDP_DFF_PR_PP_PG_N_SYMBOL_V
+
+/**
+ * udp_dff$PR_pp$PG$N: Positive edge triggered D flip-flop with active
+ *                     high
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__udp_dff$PR_pp$PG$N (
+    //# {{data|Data Signals}}
+    input  D       ,
+    output Q       ,
+
+    //# {{control|Control Signals}}
+    input  RESET   ,
+
+    //# {{clocks|Clocking}}
+    input  CLK     ,
+
+    //# {{power|Power}}
+    input  NOTIFIER,
+    input  VPWR    ,
+    input  VGND
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DFF_PR_PP_PG_N_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A31OI_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__A31OI_BEHAVIORAL_V
+
+/**
+ * a31oi: 3-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a31oi (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out  ;
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out  , A3, A1, A2     );
+    nor nor0 (nor0_out_Y, B1, and0_out   );
+    buf buf0 (Y         , nor0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A31OI_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND2B_SYMBOL_V
+`define SKY130_FD_SC_LS__AND2B_SYMBOL_V
+
+/**
+ * and2b: 2-input AND, first input inverted.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__and2b (
+    //# {{data|Data Signals}}
+    input  A_N,
+    input  B  ,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND2B_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A32OI_TB_V
+`define SKY130_FD_SC_LS__A32OI_TB_V
+
+/**
+ * a32oi: 3-input AND into first input, and 2-input AND into
+ *        2nd input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a32oi.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg A3;
+    reg B1;
+    reg B2;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        A3   = 1\'bX;
+        B1   = 1\'bX;
+        B2   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   A3   = 1\'b0;
+        #80   B1   = 1\'b0;
+        #100  B2   = 1\'b0;
+        #120  VGND = 1\'b0;
+        #140  VNB  = 1\'b0;
+        #160  VPB  = 1\'b0;
+        #180  VPWR = 1\'b0;
+        #200  A1   = 1\'b1;
+        #220  A2   = 1\'b1;
+        #240  A3   = 1\'b1;
+        #260  B1   = 1\'b1;
+        #280  B2   = 1\'b1;
+        #300  VGND = 1\'b1;
+        #320  VNB  = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VPWR = 1\'b1;
+        #380  A1   = 1\'b0;
+        #400  A2   = 1\'b0;
+        #420  A3   = 1\'b0;
+        #440  B1   = 1\'b0;
+        #460  B2   = 1\'b0;
+        #480  VGND = 1\'b0;
+        #500  VNB  = 1\'b0;
+        #520  VPB  = 1\'b0;
+        #540  VPWR = 1\'b0;
+        #560  VPWR = 1\'b1;
+        #580  VPB  = 1\'b1;
+        #600  VNB  = 1\'b1;
+        #620  VGND = 1\'b1;
+        #640  B2   = 1\'b1;
+        #660  B1   = 1\'b1;
+        #680  A3   = 1\'b1;
+        #700  A2   = 1\'b1;
+        #720  A1   = 1\'b1;
+        #740  VPWR = 1\'bx;
+        #760  VPB  = 1\'bx;
+        #780  VNB  = 1\'bx;
+        #800  VGND = 1\'bx;
+        #820  B2   = 1\'bx;
+        #840  B1   = 1\'bx;
+        #860  A3   = 1\'bx;
+        #880  A2   = 1\'bx;
+        #900  A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__a32oi dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A32OI_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A32O_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__A32O_BEHAVIORAL_PP_V
+
+/**
+ * a32o: 3-input AND into first input, and 2-input AND into
+ *       2nd input of 2-input OR.
+ *
+ *       X = ((A1 & A2 & A3) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a32o (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire and1_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A3, A1, A2           );
+    and                                and1        (and1_out         , B1, B2               );
+    or                                 or0         (or0_out_X        , and1_out, and0_out   );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A32O_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A311OI_1_V
+`define SKY130_FD_SC_LS__A311OI_1_V
+
+/**
+ * a311oi: 3-input AND into first input of 3-input NOR.
+ *
+ *         Y = !((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog wrapper for a311oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a311oi.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a311oi_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a311oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a311oi_1 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a311oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A311OI_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A21BOI_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__A21BOI_BEHAVIORAL_V
+
+/**
+ * a21boi: 2-input AND into first input of 2-input NOR,
+ *         2nd input inverted.
+ *
+ *         Y = !((A1 & A2) | (!B1_N))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a21boi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire b         ;
+    wire and0_out  ;
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (b         , B1_N           );
+    and and0 (and0_out  , A1, A2         );
+    nor nor0 (nor0_out_Y, b, and0_out    );
+    buf buf0 (Y         , nor0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21BOI_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND3_BLACKBOX_V
+`define SKY130_FD_SC_LS__NAND3_BLACKBOX_V
+
+/**
+ * nand3: 3-input NAND.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nand3 (
+    Y,
+    A,
+    B,
+    C
+);
+
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND3_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR4_BLACKBOX_V
+`define SKY130_FD_SC_LS__OR4_BLACKBOX_V
+
+/**
+ * or4: 4-input OR.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__or4 (
+    X,
+    A,
+    B,
+    C,
+    D
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR4_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND4_2_V
+`define SKY130_FD_SC_LS__AND4_2_V
+
+/**
+ * and4: 4-input AND.
+ *
+ * Verilog wrapper for and4 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__and4.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__and4_2 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__and4 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__and4_2 (
+    X,
+    A,
+    B,
+    C,
+    D
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__and4 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND4_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A311O_V
+`define SKY130_FD_SC_LS__A311O_V
+
+/**
+ * a311o: 3-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2 & A3) | B1 | C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a311o.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a311o.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a311o.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a311o.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A311O_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD1_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__CLKDLYINV3SD1_FUNCTIONAL_V
+
+/**
+ * clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
+ *                stage gate.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__clkdlyinv3sd1 (
+    Y,
+    A
+);
+
+    // Module ports
+    output Y;
+    input  A;
+
+    // Local signals
+    wire not0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out_Y, A              );
+    buf buf0 (Y         , not0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV3SD1_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SDFBBN_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__SDFBBN_BEHAVIORAL_V
+
+/**
+ * sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
+ *         clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+`include ""../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ls__udp_dff_nsr_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__sdfbbn (
+    Q      ,
+    Q_N    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire RESET          ;
+    wire SET            ;
+    wire CLK            ;
+    wire buf_Q          ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire SCD_delayed    ;
+    wire SCE_delayed    ;
+    wire CLK_N_delayed  ;
+    wire SET_B_delayed  ;
+    wire RESET_B_delayed;
+    wire mux_out        ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+    wire condb          ;
+    wire cond_D         ;
+    wire cond_SCD       ;
+    wire cond_SCE       ;
+
+    //                                   Name       Output   Other arguments
+    not                                  not0      (RESET  , RESET_B_delayed                               );
+    not                                  not1      (SET    , SET_B_delayed                                 );
+    not                                  not2      (CLK    , CLK_N_delayed                                 );
+    sky130_fd_sc_ls__udp_mux_2to1        mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed           );
+    sky130_fd_sc_ls__udp_dff$NSR_pp$PG$N dff0      (buf_Q  , SET, RESET, CLK, mux_out, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1\'b1 ) );
+    assign cond1 = ( awake && ( SET_B_delayed === 1\'b1 ) );
+    assign condb = ( cond0 & cond1 );
+    assign cond_D = ( ( SCE_delayed === 1\'b0 ) && condb );
+    assign cond_SCD = ( ( SCE_delayed === 1\'b1 ) && condb );
+    assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
+    buf                                  buf0      (Q      , buf_Q                                         );
+    not                                  not3      (Q_N    , buf_Q                                         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFBBN_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O32AI_2_V
+`define SKY130_FD_SC_LS__O32AI_2_V
+
+/**
+ * o32ai: 3-input OR and 2-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog wrapper for o32ai with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o32ai.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o32ai_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o32ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o32ai_2 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1,
+    B2
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o32ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O32AI_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__EDFXTP_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__EDFXTP_PP_BLACKBOX_V
+
+/**
+ * edfxtp: Delay flop with loopback enable, non-inverted clock,
+ *         single output.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__edfxtp (
+    Q   ,
+    CLK ,
+    D   ,
+    DE  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  DE  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EDFXTP_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O21BAI_SYMBOL_V
+`define SKY130_FD_SC_LS__O21BAI_SYMBOL_V
+
+/**
+ * o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
+ *         inverted.
+ *
+ *         Y = !((A1 | A2) & !B1_N)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o21bai (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  B1_N,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21BAI_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLRBN_BLACKBOX_V
+`define SKY130_FD_SC_LS__DLRBN_BLACKBOX_V
+
+/**
+ * dlrbn: Delay latch, inverted reset, inverted enable,
+ *        complementary outputs.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlrbn (
+    Q      ,
+    Q_N    ,
+    RESET_B,
+    D      ,
+    GATE_N
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE_N ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRBN_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O41A_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__O41A_BEHAVIORAL_PP_V
+
+/**
+ * o41a: 4-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__o41a (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , A4, A3, A2, A1        );
+    and                                and0        (and0_out_X       , or0_out, B1           );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O41A_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND2_8_V
+`define SKY130_FD_SC_LS__NAND2_8_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog wrapper for nand2 with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nand2.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nand2_8 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nand2 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nand2_8 (
+    Y,
+    A,
+    B
+);
+
+    output Y;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nand2 base (
+        .Y(Y),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND2_8_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__MUX2_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__MUX2_PP_SYMBOL_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__mux2 (
+    //# {{data|Data Signals}}
+    input  A0  ,
+    input  A1  ,
+    output X   ,
+
+    //# {{control|Control Signals}}
+    input  S   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MUX2_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_PWRGOOD_PP_G_V
+`define SKY130_FD_SC_LS__UDP_PWRGOOD_PP_G_V
+
+/**
+
+ *   UDP_OUT :=x when VPWR!=1
+ *   UDP_OUT :=UDP_IN when VPWR==1
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`include ""./sky130_fd_sc_ls__udp_pwrgood_pp_g.blackbox.v""
+`else
+primitive sky130_fd_sc_ls__udp_pwrgood_pp$G (
+    UDP_OUT,
+    UDP_IN ,
+    VGND
+);
+
+    output UDP_OUT;
+    input  UDP_IN ;
+    input  VGND   ;
+
+    table
+     // UDP_IN VPWR : UDP_OUT
+          0     0   :    0     ;
+          1     0   :    1     ;
+          ?     1   :    x     ;
+          ?     x   :    x     ;
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_PWRGOOD_PP_G_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A221OI_SYMBOL_V
+`define SKY130_FD_SC_LS__A221OI_SYMBOL_V
+
+/**
+ * a221oi: 2-input AND into first two inputs of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a221oi (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  B1,
+    input  B2,
+    input  C1,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A221OI_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR4BB_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__OR4BB_PP_BLACKBOX_V
+
+/**
+ * or4bb: 4-input OR, first two inputs inverted.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__or4bb (
+    X   ,
+    A   ,
+    B   ,
+    C_N ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR4BB_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLYGATE4SD1_TB_V
+`define SKY130_FD_SC_LS__DLYGATE4SD1_TB_V
+
+/**
+ * dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dlygate4sd1.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   VGND = 1\'b0;
+        #60   VNB  = 1\'b0;
+        #80   VPB  = 1\'b0;
+        #100  VPWR = 1\'b0;
+        #120  A    = 1\'b1;
+        #140  VGND = 1\'b1;
+        #160  VNB  = 1\'b1;
+        #180  VPB  = 1\'b1;
+        #200  VPWR = 1\'b1;
+        #220  A    = 1\'b0;
+        #240  VGND = 1\'b0;
+        #260  VNB  = 1\'b0;
+        #280  VPB  = 1\'b0;
+        #300  VPWR = 1\'b0;
+        #320  VPWR = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VNB  = 1\'b1;
+        #380  VGND = 1\'b1;
+        #400  A    = 1\'b1;
+        #420  VPWR = 1\'bx;
+        #440  VPB  = 1\'bx;
+        #460  VNB  = 1\'bx;
+        #480  VGND = 1\'bx;
+        #500  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__dlygate4sd1 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYGATE4SD1_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFBBP_SYMBOL_V
+`define SKY130_FD_SC_LS__DFBBP_SYMBOL_V
+
+/**
+ * dfbbp: Delay flop, inverted set, inverted reset,
+ *        complementary outputs.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dfbbp (
+    //# {{data|Data Signals}}
+    input  D      ,
+    output Q      ,
+    output Q_N    ,
+
+    //# {{control|Control Signals}}
+    input  RESET_B,
+    input  SET_B  ,
+
+    //# {{clocks|Clocking}}
+    input  CLK
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFBBP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR4BB_4_V
+`define SKY130_FD_SC_LS__NOR4BB_4_V
+
+/**
+ * nor4bb: 4-input NOR, first two inputs inverted.
+ *
+ * Verilog wrapper for nor4bb with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nor4bb.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor4bb_4 (
+    Y   ,
+    A   ,
+    B   ,
+    C_N ,
+    D_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C_N ;
+    input  D_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nor4bb base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C_N(C_N),
+        .D_N(D_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor4bb_4 (
+    Y  ,
+    A  ,
+    B  ,
+    C_N,
+    D_N
+);
+
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+    input  D_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nor4bb base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C_N(C_N),
+        .D_N(D_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR4BB_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLYGATE4SD2_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__DLYGATE4SD2_PP_SYMBOL_V
+
+/**
+ * dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlygate4sd2 (
+    //# {{data|Data Signals}}
+    input  A   ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYGATE4SD2_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A22O_4_V
+`define SKY130_FD_SC_LS__A22O_4_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ *       X = ((A1 & A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a22o with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a22o.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a22o_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a22o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a22o_4 (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a22o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A22O_4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NOR4B_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__NOR4B_FUNCTIONAL_V
+
+/**
+ * nor4b: 4-input NOR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__nor4b (
+    Y  ,
+    A  ,
+    B  ,
+    C  ,
+    D_N
+);
+
+    // Module ports
+    output Y  ;
+    input  A  ;
+    input  B  ;
+    input  C  ;
+    input  D_N;
+
+    // Local signals
+    wire not0_out  ;
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out  , D_N              );
+    nor nor0 (nor0_out_Y, A, B, C, not0_out);
+    buf buf0 (Y         , nor0_out_Y       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR4B_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR2B_TB_V
+`define SKY130_FD_SC_LS__NOR2B_TB_V
+
+/**
+ * nor2b: 2-input NOR, first input inverted.
+ *
+ *        Y = !(A | B | C | !D)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nor2b.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg B_N;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        B_N  = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   B_N  = 1\'b0;
+        #60   VGND = 1\'b0;
+        #80   VNB  = 1\'b0;
+        #100  VPB  = 1\'b0;
+        #120  VPWR = 1\'b0;
+        #140  A    = 1\'b1;
+        #160  B_N  = 1\'b1;
+        #180  VGND = 1\'b1;
+        #200  VNB  = 1\'b1;
+        #220  VPB  = 1\'b1;
+        #240  VPWR = 1\'b1;
+        #260  A    = 1\'b0;
+        #280  B_N  = 1\'b0;
+        #300  VGND = 1\'b0;
+        #320  VNB  = 1\'b0;
+        #340  VPB  = 1\'b0;
+        #360  VPWR = 1\'b0;
+        #380  VPWR = 1\'b1;
+        #400  VPB  = 1\'b1;
+        #420  VNB  = 1\'b1;
+        #440  VGND = 1\'b1;
+        #460  B_N  = 1\'b1;
+        #480  A    = 1\'b1;
+        #500  VPWR = 1\'bx;
+        #520  VPB  = 1\'bx;
+        #540  VNB  = 1\'bx;
+        #560  VGND = 1\'bx;
+        #580  B_N  = 1\'bx;
+        #600  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__nor2b dut (.A(A), .B_N(B_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR2B_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O21AI_V
+`define SKY130_FD_SC_LS__O21AI_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o21ai.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o21ai.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o21ai.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o21ai.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21AI_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+( posedge CLK => ( Q : CLK ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall
+( posedge CLK => ( Q_N : CLK ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall
+$width ( posedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( negedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+$setuphold ( posedge CLK , posedge DE , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , CLK_delayed , DE_delayed ) ;
+$setuphold ( posedge CLK , negedge DE , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , CLK_delayed , DE_delayed ) ;
+$setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND0 ,  COND0 , CLK_delayed , D_delayed ) ;
+$setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND0 ,  COND0 , CLK_delayed , D_delayed ) ;
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD3_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__CLKDLYINV3SD3_FUNCTIONAL_PP_V
+
+/**
+ * clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
+ *                stage gate.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__clkdlyinv3sd3 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out_Y       , A                     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV3SD3_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLXTP_V
+`define SKY130_FD_SC_LS__DLXTP_V
+
+/**
+ * dlxtp: Delay latch, non-inverted enable, single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlxtp.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlxtp.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlxtp.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlxtp.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXTP_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFXBP_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__DFXBP_PP_SYMBOL_V
+
+/**
+ * dfxbp: Delay flop, complementary outputs.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dfxbp (
+    //# {{data|Data Signals}}
+    input  D   ,
+    output Q   ,
+    output Q_N ,
+
+    //# {{clocks|Clocking}}
+    input  CLK ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFXBP_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O32A_V
+`define SKY130_FD_SC_LS__O32A_V
+
+/**
+ * o32a: 3-input OR and 2-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o32a.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o32a.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__o32a.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__o32a.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O32A_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O22AI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__O22AI_FUNCTIONAL_PP_V
+
+/**
+ * o22ai: 2-input OR into both inputs of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__o22ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nor0_out         ;
+    wire nor1_out         ;
+    wire or0_out_Y        ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nor                                nor0        (nor0_out         , B1, B2               );
+    nor                                nor1        (nor1_out         , A1, A2               );
+    or                                 or0         (or0_out_Y        , nor1_out, nor0_out   );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O22AI_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD3_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__CLKDLYINV5SD3_BEHAVIORAL_V
+
+/**
+ * clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
+ *                stage gate.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__clkdlyinv5sd3 (
+    Y,
+    A
+);
+
+    // Module ports
+    output Y;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out_Y, A              );
+    buf buf0 (Y         , not0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV5SD3_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFSTP_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__DFSTP_PP_BLACKBOX_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dfstp (
+    Q    ,
+    CLK  ,
+    D    ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFSTP_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O31A_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__O31A_PP_BLACKBOX_V
+
+/**
+ * o31a: 3-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3) & B1)
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o31a (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O31A_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SDFBBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__SDFBBP_FUNCTIONAL_PP_V
+
+/**
+ * sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
+ *         clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+`include ""../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ls__udp_dff_nsr_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__sdfbbp (
+    Q      ,
+    Q_N    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    CLK    ,
+    SET_B  ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  CLK    ;
+    input  SET_B  ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire RESET  ;
+    wire SET    ;
+    wire buf_Q  ;
+    wire mux_out;
+
+    //                                   Delay       Name       Output   Other arguments
+    not                                              not0      (RESET  , RESET_B                               );
+    not                                              not1      (SET    , SET_B                                 );
+    sky130_fd_sc_ls__udp_mux_2to1                    mux_2to10 (mux_out, D, SCD, SCE                           );
+    sky130_fd_sc_ls__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0      (buf_Q  , SET, RESET, CLK, mux_out, , VPWR, VGND);
+    buf                                              buf0      (Q      , buf_Q                                 );
+    not                                              not2      (Q_N    , buf_Q                                 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFBBP_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NAND2_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__NAND2_FUNCTIONAL_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__nand2 (
+    Y,
+    A,
+    B
+);
+
+    // Module ports
+    output Y;
+    input  A;
+    input  B;
+
+    // Local signals
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    nand nand0 (nand0_out_Y, B, A           );
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND2_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLXBP_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__DLXBP_FUNCTIONAL_V
+
+/**
+ * dlxbp: Delay latch, non-inverted enable, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_p/sky130_fd_sc_ls__udp_dlatch_p.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlxbp (
+    Q   ,
+    Q_N ,
+    D   ,
+    GATE
+);
+
+    // Module ports
+    output Q   ;
+    output Q_N ;
+    input  D   ;
+    input  GATE;
+
+    // Local signals
+    wire buf_Q;
+
+    //                            Delay       Name     Output  Other arguments
+    sky130_fd_sc_ls__udp_dlatch$P `UNIT_DELAY dlatch0 (buf_Q , D, GATE        );
+    buf                                       buf0    (Q     , buf_Q          );
+    not                                       not0    (Q_N   , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXBP_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__AND4_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__AND4_BEHAVIORAL_V
+
+/**
+ * and4: 4-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__and4 (
+    X,
+    A,
+    B,
+    C,
+    D
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out_X, A, B, C, D     );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND4_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__XOR2_1_V
+`define SKY130_FD_SC_LS__XOR2_1_V
+
+/**
+ * xor2: 2-input exclusive OR.
+ *
+ *       X = A ^ B
+ *
+ * Verilog wrapper for xor2 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__xor2.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__xor2_1 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__xor2 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__xor2_1 (
+    X,
+    A,
+    B
+);
+
+    output X;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__xor2 base (
+        .X(X),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XOR2_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_PWRGOOD_PP_G_SYMBOL_V
+`define SKY130_FD_SC_LS__UDP_PWRGOOD_PP_G_SYMBOL_V
+
+/**
+
+ *   UDP_OUT :=x when VPWR!=1
+ *   UDP_OUT :=UDP_IN when VPWR==1
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__udp_pwrgood_pp$G (
+    //# {{data|Data Signals}}
+    input  UDP_IN ,
+    output UDP_OUT,
+
+    //# {{power|Power}}
+    input  VGND
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_PWRGOOD_PP_G_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFRBP_2_V
+`define SKY130_FD_SC_LS__SDFRBP_2_V
+
+/**
+ * sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog wrapper for sdfrbp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__sdfrbp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sdfrbp_2 (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_ls__sdfrbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .RESET_B(RESET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sdfrbp_2 (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__sdfrbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .RESET_B(RESET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFRBP_2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A222OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__A222OI_BEHAVIORAL_PP_V
+
+/**
+ * a222oi: 2-input AND into all inputs of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a222oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    C2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  C2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out        ;
+    wire nand1_out        ;
+    wire nand2_out        ;
+    wire and0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nand                               nand0       (nand0_out        , A2, A1                         );
+    nand                               nand1       (nand1_out        , B2, B1                         );
+    nand                               nand2       (nand2_out        , C2, C1                         );
+    and                                and0        (and0_out_Y       , nand0_out, nand1_out, nand2_out);
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND         );
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y              );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A222OI_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__XOR3_TB_V
+`define SKY130_FD_SC_LS__XOR3_TB_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ *       X = A ^ B ^ C
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__xor3.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg B;
+    reg C;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        B    = 1\'bX;
+        C    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   B    = 1\'b0;
+        #60   C    = 1\'b0;
+        #80   VGND = 1\'b0;
+        #100  VNB  = 1\'b0;
+        #120  VPB  = 1\'b0;
+        #140  VPWR = 1\'b0;
+        #160  A    = 1\'b1;
+        #180  B    = 1\'b1;
+        #200  C    = 1\'b1;
+        #220  VGND = 1\'b1;
+        #240  VNB  = 1\'b1;
+        #260  VPB  = 1\'b1;
+        #280  VPWR = 1\'b1;
+        #300  A    = 1\'b0;
+        #320  B    = 1\'b0;
+        #340  C    = 1\'b0;
+        #360  VGND = 1\'b0;
+        #380  VNB  = 1\'b0;
+        #400  VPB  = 1\'b0;
+        #420  VPWR = 1\'b0;
+        #440  VPWR = 1\'b1;
+        #460  VPB  = 1\'b1;
+        #480  VNB  = 1\'b1;
+        #500  VGND = 1\'b1;
+        #520  C    = 1\'b1;
+        #540  B    = 1\'b1;
+        #560  A    = 1\'b1;
+        #580  VPWR = 1\'bx;
+        #600  VPB  = 1\'bx;
+        #620  VNB  = 1\'bx;
+        #640  VGND = 1\'bx;
+        #660  C    = 1\'bx;
+        #680  B    = 1\'bx;
+        #700  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__xor3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XOR3_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__TAPVGND_BLACKBOX_V
+`define SKY130_FD_SC_LS__TAPVGND_BLACKBOX_V
+
+/**
+ * tapvgnd: Tap cell with tap to ground, isolated power connection
+ *          1 row down.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__tapvgnd ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPVGND_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O221A_SYMBOL_V
+`define SKY130_FD_SC_LS__O221A_SYMBOL_V
+
+/**
+ * o221a: 2-input OR into first two inputs of 3-input AND.
+ *
+ *        X = ((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o221a (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  B1,
+    input  B2,
+    input  C1,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O221A_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A1 +=> X) = (0:0:0,0:0:0);
+(A2 +=> X) = (0:0:0,0:0:0);
+(A3 +=> X) = (0:0:0,0:0:0);
+(A4 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A221O_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__A221O_BEHAVIORAL_V
+
+/**
+ * a221o: 2-input AND into first two inputs of 3-input OR.
+ *
+ *        X = ((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a221o (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out ;
+    wire and1_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    and and0 (and0_out , B1, B2                );
+    and and1 (and1_out , A1, A2                );
+    or  or0  (or0_out_X, and1_out, and0_out, C1);
+    buf buf0 (X        , or0_out_X             );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A221O_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLYGATE4SD1_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__DLYGATE4SD1_PP_SYMBOL_V
+
+/**
+ * dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlygate4sd1 (
+    //# {{data|Data Signals}}
+    input  A   ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYGATE4SD1_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR2B_1_V
+`define SKY130_FD_SC_LS__OR2B_1_V
+
+/**
+ * or2b: 2-input OR, first input inverted.
+ *
+ * Verilog wrapper for or2b with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__or2b.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__or2b_1 (
+    X   ,
+    A   ,
+    B_N ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B_N ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__or2b base (
+        .X(X),
+        .A(A),
+        .B_N(B_N),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__or2b_1 (
+    X  ,
+    A  ,
+    B_N
+);
+
+    output X  ;
+    input  A  ;
+    input  B_N;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__or2b base (
+        .X(X),
+        .A(A),
+        .B_N(B_N)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR2B_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__XOR3_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__XOR3_FUNCTIONAL_V
+
+/**
+ * xor3: 3-input exclusive OR.
+ *
+ *       X = A ^ B ^ C
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__xor3 (
+    X,
+    A,
+    B,
+    C
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Local signals
+    wire xor0_out_X;
+
+    //  Name  Output      Other arguments
+    xor xor0 (xor0_out_X, A, B, C        );
+    buf buf0 (X         , xor0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XOR3_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__MUX2I_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__MUX2I_FUNCTIONAL_V
+
+/**
+ * mux2i: 2-input multiplexer, output inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1_n/sky130_fd_sc_ls__udp_mux_2to1_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__mux2i (
+    Y ,
+    A0,
+    A1,
+    S
+);
+
+    // Module ports
+    output Y ;
+    input  A0;
+    input  A1;
+    input  S ;
+
+    // Local signals
+    wire mux_2to1_n0_out_Y;
+
+    //                              Name         Output             Other arguments
+    sky130_fd_sc_ls__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S        );
+    buf                             buf0        (Y                , mux_2to1_n0_out_Y);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MUX2I_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLYMETAL6S2S_V
+`define SKY130_FD_SC_LS__DLYMETAL6S2S_V
+
+/**
+ * dlymetal6s2s: 6-inverter delay with output from 2nd stage on
+ *               horizontal route.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlymetal6s2s.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlymetal6s2s.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlymetal6s2s.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dlymetal6s2s.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYMETAL6S2S_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND2B_BLACKBOX_V
+`define SKY130_FD_SC_LS__AND2B_BLACKBOX_V
+
+/**
+ * and2b: 2-input AND, first input inverted.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__and2b (
+    X  ,
+    A_N,
+    B
+);
+
+    output X  ;
+    input  A_N;
+    input  B  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND2B_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A31OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__A31OI_BEHAVIORAL_PP_V
+
+/**
+ * a31oi: 3-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a31oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A3, A1, A2            );
+    nor                                nor0        (nor0_out_Y       , B1, and0_out          );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A31OI_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__XNOR2_4_V
+`define SKY130_FD_SC_LS__XNOR2_4_V
+
+/**
+ * xnor2: 2-input exclusive NOR.
+ *
+ *        Y = !(A ^ B)
+ *
+ * Verilog wrapper for xnor2 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__xnor2.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__xnor2_4 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__xnor2 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__xnor2_4 (
+    Y,
+    A,
+    B
+);
+
+    output Y;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__xnor2 base (
+        .Y(Y),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XNOR2_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__BUFINV_SYMBOL_V
+`define SKY130_FD_SC_LS__BUFINV_SYMBOL_V
+
+/**
+ * bufinv: Buffer followed by inverter.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__bufinv (
+    //# {{data|Data Signals}}
+    input  A,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__BUFINV_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FAH_TB_V
+`define SKY130_FD_SC_LS__FAH_TB_V
+
+/**
+ * fah: Full adder.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__fah.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg B;
+    reg CI;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire COUT;
+    wire SUM;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        B    = 1\'bX;
+        CI   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   B    = 1\'b0;
+        #60   CI   = 1\'b0;
+        #80   VGND = 1\'b0;
+        #100  VNB  = 1\'b0;
+        #120  VPB  = 1\'b0;
+        #140  VPWR = 1\'b0;
+        #160  A    = 1\'b1;
+        #180  B    = 1\'b1;
+        #200  CI   = 1\'b1;
+        #220  VGND = 1\'b1;
+        #240  VNB  = 1\'b1;
+        #260  VPB  = 1\'b1;
+        #280  VPWR = 1\'b1;
+        #300  A    = 1\'b0;
+        #320  B    = 1\'b0;
+        #340  CI   = 1\'b0;
+        #360  VGND = 1\'b0;
+        #380  VNB  = 1\'b0;
+        #400  VPB  = 1\'b0;
+        #420  VPWR = 1\'b0;
+        #440  VPWR = 1\'b1;
+        #460  VPB  = 1\'b1;
+        #480  VNB  = 1\'b1;
+        #500  VGND = 1\'b1;
+        #520  CI   = 1\'b1;
+        #540  B    = 1\'b1;
+        #560  A    = 1\'b1;
+        #580  VPWR = 1\'bx;
+        #600  VPB  = 1\'bx;
+        #620  VNB  = 1\'bx;
+        #640  VGND = 1\'bx;
+        #660  CI   = 1\'bx;
+        #680  B    = 1\'bx;
+        #700  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__fah dut (.A(A), .B(B), .CI(CI), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .COUT(COUT), .SUM(SUM));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FAH_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A222OI_1_V
+`define SKY130_FD_SC_LS__A222OI_1_V
+
+/**
+ * a222oi: 2-input AND into all inputs of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
+ *
+ * Verilog wrapper for a222oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a222oi.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a222oi_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    C2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  C2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a222oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1),
+        .C2(C2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a222oi_1 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1,
+    C2
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+    input  C2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a222oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1),
+        .C2(C2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A222OI_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NAND3_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__NAND3_FUNCTIONAL_V
+
+/**
+ * nand3: 3-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__nand3 (
+    Y,
+    A,
+    B,
+    C
+);
+
+    // Module ports
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+
+    // Local signals
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    nand nand0 (nand0_out_Y, B, A, C        );
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND3_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR2B_SYMBOL_V
+`define SKY130_FD_SC_LS__NOR2B_SYMBOL_V
+
+/**
+ * nor2b: 2-input NOR, first input inverted.
+ *
+ *        Y = !(A | B | C | !D)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nor2b (
+    //# {{data|Data Signals}}
+    input  A  ,
+    input  B_N,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR2B_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DECAP_BLACKBOX_V
+`define SKY130_FD_SC_LS__DECAP_BLACKBOX_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__decap ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DECAP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A21OI_BLACKBOX_V
+`define SKY130_FD_SC_LS__A21OI_BLACKBOX_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | B1)
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a21oi (
+    Y ,
+    A1,
+    A2,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21OI_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A21O_4_V
+`define SKY130_FD_SC_LS__A21O_4_V
+
+/**
+ * a21o: 2-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2) | B1)
+ *
+ * Verilog wrapper for a21o with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a21o.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a21o_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a21o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a21o_4 (
+    X ,
+    A1,
+    A2,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a21o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21O_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD2_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__CLKDLYINV3SD2_PP_BLACKBOX_V
+
+/**
+ * clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
+ *                stage gate.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__clkdlyinv3sd2 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV3SD2_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__FA_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__FA_BEHAVIORAL_PP_V
+
+/**
+ * fa: Full adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__fa (
+    COUT,
+    SUM ,
+    A   ,
+    B   ,
+    CIN ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+    input  CIN ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out             ;
+    wire and0_out            ;
+    wire and1_out            ;
+    wire and2_out            ;
+    wire nor0_out            ;
+    wire nor1_out            ;
+    wire or1_out_COUT        ;
+    wire pwrgood_pp0_out_COUT;
+    wire or2_out_SUM         ;
+    wire pwrgood_pp1_out_SUM ;
+
+    //                                 Name         Output                Other arguments
+    or                                 or0         (or0_out             , CIN, B                  );
+    and                                and0        (and0_out            , or0_out, A              );
+    and                                and1        (and1_out            , B, CIN                  );
+    or                                 or1         (or1_out_COUT        , and1_out, and0_out      );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, or1_out_COUT, VPWR, VGND);
+    buf                                buf0        (COUT                , pwrgood_pp0_out_COUT    );
+    and                                and2        (and2_out            , CIN, A, B               );
+    nor                                nor0        (nor0_out            , A, or0_out              );
+    nor                                nor1        (nor1_out            , nor0_out, COUT          );
+    or                                 or2         (or2_out_SUM         , nor1_out, and2_out      );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , or2_out_SUM, VPWR, VGND );
+    buf                                buf1        (SUM                 , pwrgood_pp1_out_SUM     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FA_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DECAPHETAP_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__DECAPHETAP_PP_SYMBOL_V
+
+/**
+
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__decaphetap (
+    //# {{power|Power}}
+    input VPB ,
+    input VPWR,
+    input VGND
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DECAPHETAP_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DFF_P_PP_PG_N_V
+`define SKY130_FD_SC_LS__UDP_DFF_P_PP_PG_N_V
+
+/**
+ * udp_dff$P_pp$PG$N: Positive edge triggered D flip-flop
+ *                    (Q output UDP).
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`include ""./sky130_fd_sc_ls__udp_dff_p_pp_pg_n.blackbox.v""
+`else
+primitive sky130_fd_sc_ls__udp_dff$P_pp$PG$N (
+    Q       ,
+    D       ,
+    CLK     ,
+    NOTIFIER,
+    VPWR    ,
+    VGND
+);
+
+    output Q       ;
+    input  D       ;
+    input  CLK     ;
+    input  NOTIFIER;
+    input  VPWR    ;
+    input  VGND    ;
+
+    reg Q;
+
+    table
+     //          D           CLK  NOTIFIER VPWR VGND :  Qt : Qt+1
+                 1           (01)    ?      1    0   :  ?  :  1    ; // clocked data
+                 0           (01)    ?      1    0   :  ?  :  0    ;
+                 1           (x1)    ?      1    0   :  1  :  1    ; // reducing pessimism
+                 0           (x1)    ?      1    0   :  0  :  0    ;
+                 1           (0x)    ?      1    0   :  1  :  1    ;
+                 0           (0x)    ?      1    0   :  0  :  0    ;
+                 0            x      ?      1    0   :  0  :  0    ; // Hold when CLK=X and D=Q
+                 1            x      ?      1    0   :  1  :  1    ; // Hold when CLK=X and D=Q
+                 ?           (?0)    ?      1    0   :  ?  :  -    ;
+                 *            b      ?      1    0   :  ?  :  -    ; // ignore edges on data
+        // [\'IfDef(functional)\', \'\']                 ?            ?      *      1    0   :  ?  :  -    ;
+        // [\'Else\', \'\']                 ?            ?      *      1    0   :  ?  :  x    ;
+        // [\'EndIfDef(functional)\', \'\']                 ?            ?      ?      *    ?   :  ?  :  x    ; // any change on vpwr
+                 ?            ?      ?      ?    *   :  ?  :  x    ; // any change on vgnd
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DFF_P_PP_PG_N_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O2BB2AI_BLACKBOX_V
+`define SKY130_FD_SC_LS__O2BB2AI_BLACKBOX_V
+
+/**
+ * o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
+ *
+ *          Y = !(!(A1 & A2) & (B1 | B2))
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o2bb2ai (
+    Y   ,
+    A1_N,
+    A2_N,
+    B1  ,
+    B2
+);
+
+    output Y   ;
+    input  A1_N;
+    input  A2_N;
+    input  B1  ;
+    input  B2  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2BB2AI_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A211O_V
+`define SKY130_FD_SC_LS__A211O_V
+
+/**
+ * a211o: 2-input AND into first input of 3-input OR.
+ *
+ *        X = ((A1 & A2) | B1 | C1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a211o.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a211o.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a211o.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a211o.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A211O_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O22A_4_V
+`define SKY130_FD_SC_LS__O22A_4_V
+
+/**
+ * o22a: 2-input OR into both inputs of 2-input AND.
+ *
+ *       X = ((A1 | A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o22a with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o22a.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o22a_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o22a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o22a_4 (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o22a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O22A_4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLYGATE4SD3_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__DLYGATE4SD3_BEHAVIORAL_PP_V
+
+/**
+ * dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlygate4sd3 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    buf                                buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYGATE4SD3_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CONB_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__CONB_PP_BLACKBOX_V
+
+/**
+ * conb: Constant value, low, high outputs.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__conb (
+    HI  ,
+    LO  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output HI  ;
+    output LO  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CONB_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__TAPVGND_1_V
+`define SKY130_FD_SC_LS__TAPVGND_1_V
+
+/**
+ * tapvgnd: Tap cell with tap to ground, isolated power connection
+ *          1 row down.
+ *
+ * Verilog wrapper for tapvgnd with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__tapvgnd.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__tapvgnd_1 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+    sky130_fd_sc_ls__tapvgnd base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__tapvgnd_1 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__tapvgnd base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPVGND_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DFRBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__DFRBP_FUNCTIONAL_PP_V
+
+/**
+ * dfrbp: Delay flop, inverted reset, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dfrbp (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire buf_Q;
+    wire RESET;
+
+    //                                  Delay       Name  Output  Other arguments
+    not                                             not0 (RESET , RESET_B                    );
+    sky130_fd_sc_ls__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET, , VPWR, VGND);
+    buf                                             buf0 (Q     , buf_Q                      );
+    not                                             not1 (Q_N   , buf_Q                      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFRBP_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR2_1_V
+`define SKY130_FD_SC_LS__OR2_1_V
+
+/**
+ * or2: 2-input OR.
+ *
+ * Verilog wrapper for or2 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__or2.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__or2_1 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__or2 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__or2_1 (
+    X,
+    A,
+    B
+);
+
+    output X;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__or2 base (
+        .X(X),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR2_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O2111AI_SYMBOL_V
+`define SKY130_FD_SC_LS__O2111AI_SYMBOL_V
+
+/**
+ * o2111ai: 2-input OR into first input of 4-input NAND.
+ *
+ *          Y = !((A1 | A2) & B1 & C1 & D1)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o2111ai (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  B1,
+    input  C1,
+    input  D1,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O2111AI_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if (TE ) (A -=> Z ) = (0:0:0,0:0:0);  // delays are tris,tfall
+(TE => Z ) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);  // delays are t01,t10,t0Z,tZ1,t1Z,tZ0
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLYGATE4SD1_BLACKBOX_V
+`define SKY130_FD_SC_LS__DLYGATE4SD1_BLACKBOX_V
+
+/**
+ * dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlygate4sd1 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYGATE4SD1_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__FILL_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__FILL_FUNCTIONAL_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__fill ();
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FILL_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DLATCH_PR_V
+`define SKY130_FD_SC_LS__UDP_DLATCH_PR_V
+
+/**
+ * udp_dlatch$PR: D-latch, gated clear direct / gate active high
+ *                (Q output UDP)
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`include ""./sky130_fd_sc_ls__udp_dlatch_pr.blackbox.v""
+`else
+primitive sky130_fd_sc_ls__udp_dlatch$PR (
+    Q    ,
+    D    ,
+    GATE ,
+    RESET
+);
+
+    output Q    ;
+    input  D    ;
+    input  GATE ;
+    input  RESET;
+
+    reg Q;
+
+    table
+     //  D  GATE RESET :  Qt : Qt+1
+         ?   0     0   :  ?  :  -    ; // hold
+         0   1     0   :  ?  :  0    ; // pass 0
+         1   1     0   :  ?  :  1    ; // pass 1
+         ?   ?     1   :  ?  :  0    ; // async reset
+         0   1     ?   :  ?  :  0    ; // reduce pessimism
+         0   x     0   :  0  :  0    ; // reduce pessimism
+         1   x     0   :  1  :  1    ; // reduce pessimism
+         ?   0     x   :  0  :  0    ; // reduce pessimism
+         0   x     x   :  0  :  0    ; // reduce pessimism
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DLATCH_PR_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O41A_4_V
+`define SKY130_FD_SC_LS__O41A_4_V
+
+/**
+ * o41a: 4-input OR into 2-input AND.
+ *
+ *       X = ((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog wrapper for o41a with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o41a.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o41a_4 (
+    X   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o41a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o41a_4 (
+    X ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o41a base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O41A_4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+( D +=> Q ) = ( 0:0:0 , 0:0:0 ) ;  // delays are tris , tfall
+( posedge GATE => ( Q +: D ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall
+$width ( posedge GATE &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+$setuphold ( negedge GATE , posedge D , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , GATE_delayed , D_delayed ) ;
+$setuphold ( negedge GATE , negedge D , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , GATE_delayed , D_delayed ) ;
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A1 +=> X) = (0:0:0,0:0:0);
+(A2 +=> X) = (0:0:0,0:0:0);
+(A3 +=> X) = (0:0:0,0:0:0);
+(A4 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2&!A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2&!A3&A4)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2&A3&!A4)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2&A3&A4)) (B1 +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DLATCH_PR_PP_PG_N_BLACKBOX_V
+`define SKY130_FD_SC_LS__UDP_DLATCH_PR_PP_PG_N_BLACKBOX_V
+
+/**
+ * udp_dlatch$PR_pp$PG$N: D-latch, gated clear direct / gate active
+ *                        high (Q output UDP)
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__udp_dlatch$PR_pp$PG$N (
+    Q       ,
+    D       ,
+    GATE    ,
+    RESET   ,
+    NOTIFIER,
+    VPWR    ,
+    VGND
+);
+
+    output Q       ;
+    input  D       ;
+    input  GATE    ;
+    input  RESET   ;
+    input  NOTIFIER;
+    input  VPWR    ;
+    input  VGND    ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DLATCH_PR_PP_PG_N_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FAHCON_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__FAHCON_PP_SYMBOL_V
+
+/**
+ * fahcon: Full adder, inverted carry in, inverted carry out.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__fahcon (
+    //# {{data|Data Signals}}
+    input  A     ,
+    input  B     ,
+    input  CI    ,
+    output COUT_N,
+    output SUM   ,
+
+    //# {{power|Power}}
+    input  VPB   ,
+    input  VPWR  ,
+    input  VGND  ,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FAHCON_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O41AI_2_V
+`define SKY130_FD_SC_LS__O41AI_2_V
+
+/**
+ * o41ai: 4-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog wrapper for o41ai with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o41ai.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o41ai_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o41ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o41ai_2 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o41ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O41AI_2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__HA_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__HA_BEHAVIORAL_V
+
+/**
+ * ha: Half adder.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__ha (
+    COUT,
+    SUM ,
+    A   ,
+    B
+);
+
+    // Module ports
+    output COUT;
+    output SUM ;
+    input  A   ;
+    input  B   ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out_COUT;
+    wire xor0_out_SUM ;
+
+    //  Name  Output         Other arguments
+    and and0 (and0_out_COUT, A, B           );
+    buf buf0 (COUT         , and0_out_COUT  );
+    xor xor0 (xor0_out_SUM , B, A           );
+    buf buf1 (SUM          , xor0_out_SUM   );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__HA_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O32AI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__O32AI_FUNCTIONAL_PP_V
+
+/**
+ * o32ai: 3-input OR and 2-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__o32ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nor0_out         ;
+    wire nor1_out         ;
+    wire or0_out_Y        ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    nor                                nor0        (nor0_out         , A3, A1, A2           );
+    nor                                nor1        (nor1_out         , B1, B2               );
+    or                                 or0         (or0_out_Y        , nor1_out, nor0_out   );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O32AI_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR2_1_V
+`define SKY130_FD_SC_LS__NOR2_1_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog wrapper for nor2 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__nor2.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor2_1 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__nor2 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__nor2_1 (
+    Y,
+    A,
+    B
+);
+
+    output Y;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__nor2 base (
+        .Y(Y),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR2_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FAHCON_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__FAHCON_PP_BLACKBOX_V
+
+/**
+ * fahcon: Full adder, inverted carry in, inverted carry out.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__fahcon (
+    COUT_N,
+    SUM   ,
+    A     ,
+    B     ,
+    CI    ,
+    VPWR  ,
+    VGND  ,
+    VPB   ,
+    VNB
+);
+
+    output COUT_N;
+    output SUM   ;
+    input  A     ;
+    input  B     ;
+    input  CI    ;
+    input  VPWR  ;
+    input  VGND  ;
+    input  VPB   ;
+    input  VNB   ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FAHCON_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDLCLKP_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__SDLCLKP_PP_SYMBOL_V
+
+/**
+ * sdlclkp: Scan gated clock.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sdlclkp (
+    //# {{scanchain|Scan Chain}}
+    input  SCE ,
+
+    //# {{clocks|Clocking}}
+    input  CLK ,
+    input  GATE,
+    output GCLK,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDLCLKP_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__TAP_1_V
+`define SKY130_FD_SC_LS__TAP_1_V
+
+/**
+ * tap: Tap cell with no tap connections (no contacts on metal1).
+ *
+ * Verilog wrapper for tap with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__tap.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__tap_1 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+    sky130_fd_sc_ls__tap base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__tap_1 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__tap base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAP_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__BUFINV_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__BUFINV_BEHAVIORAL_PP_V
+
+/**
+ * bufinv: Buffer followed by inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__bufinv (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    not                                not0        (not0_out_Y       , A                     );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__BUFINV_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLYGATE4SD3_BLACKBOX_V
+`define SKY130_FD_SC_LS__DLYGATE4SD3_BLACKBOX_V
+
+/**
+ * dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlygate4sd3 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLYGATE4SD3_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR4B_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__NOR4B_PP_SYMBOL_V
+
+/**
+ * nor4b: 4-input NOR, first input inverted.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nor4b (
+    //# {{data|Data Signals}}
+    input  A   ,
+    input  B   ,
+    input  C   ,
+    input  D_N ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR4B_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__INV_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__INV_BEHAVIORAL_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__inv (
+    Y,
+    A
+);
+
+    // Module ports
+    output Y;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out_Y, A              );
+    buf buf0 (Y         , not0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__INV_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__OR3B_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__OR3B_FUNCTIONAL_V
+
+/**
+ * or3b: 3-input OR, first input inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__or3b (
+    X  ,
+    A  ,
+    B  ,
+    C_N
+);
+
+    // Module ports
+    output X  ;
+    input  A  ;
+    input  B  ;
+    input  C_N;
+
+    // Local signals
+    wire not0_out ;
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    not not0 (not0_out , C_N            );
+    or  or0  (or0_out_X, B, A, not0_out );
+    buf buf0 (X        , or0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR3B_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND2_SYMBOL_V
+`define SKY130_FD_SC_LS__AND2_SYMBOL_V
+
+/**
+ * and2: 2-input AND.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__and2 (
+    //# {{data|Data Signals}}
+    input  A,
+    input  B,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND2_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFXTP_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__SDFXTP_PP_SYMBOL_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sdfxtp (
+    //# {{data|Data Signals}}
+    input  D   ,
+    output Q   ,
+
+    //# {{scanchain|Scan Chain}}
+    input  SCD ,
+    input  SCE ,
+
+    //# {{clocks|Clocking}}
+    input  CLK ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFXTP_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A +=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A31OI_1_V
+`define SKY130_FD_SC_LS__A31OI_1_V
+
+/**
+ * a31oi: 3-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | B1)
+ *
+ * Verilog wrapper for a31oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a31oi.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a31oi_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a31oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a31oi_1 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a31oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A31OI_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFRTP_2_V
+`define SKY130_FD_SC_LS__SDFRTP_2_V
+
+/**
+ * sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
+ *         single output.
+ *
+ * Verilog wrapper for sdfrtp with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__sdfrtp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sdfrtp_2 (
+    Q      ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+    sky130_fd_sc_ls__sdfrtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .RESET_B(RESET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sdfrtp_2 (
+    Q      ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B
+);
+
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__sdfrtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .RESET_B(RESET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFRTP_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O22AI_TB_V
+`define SKY130_FD_SC_LS__O22AI_TB_V
+
+/**
+ * o22ai: 2-input OR into both inputs of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & (B1 | B2))
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o22ai.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg B1;
+    reg B2;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        B1   = 1\'bX;
+        B2   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   B1   = 1\'b0;
+        #80   B2   = 1\'b0;
+        #100  VGND = 1\'b0;
+        #120  VNB  = 1\'b0;
+        #140  VPB  = 1\'b0;
+        #160  VPWR = 1\'b0;
+        #180  A1   = 1\'b1;
+        #200  A2   = 1\'b1;
+        #220  B1   = 1\'b1;
+        #240  B2   = 1\'b1;
+        #260  VGND = 1\'b1;
+        #280  VNB  = 1\'b1;
+        #300  VPB  = 1\'b1;
+        #320  VPWR = 1\'b1;
+        #340  A1   = 1\'b0;
+        #360  A2   = 1\'b0;
+        #380  B1   = 1\'b0;
+        #400  B2   = 1\'b0;
+        #420  VGND = 1\'b0;
+        #440  VNB  = 1\'b0;
+        #460  VPB  = 1\'b0;
+        #480  VPWR = 1\'b0;
+        #500  VPWR = 1\'b1;
+        #520  VPB  = 1\'b1;
+        #540  VNB  = 1\'b1;
+        #560  VGND = 1\'b1;
+        #580  B2   = 1\'b1;
+        #600  B1   = 1\'b1;
+        #620  A2   = 1\'b1;
+        #640  A1   = 1\'b1;
+        #660  VPWR = 1\'bx;
+        #680  VPB  = 1\'bx;
+        #700  VNB  = 1\'bx;
+        #720  VGND = 1\'bx;
+        #740  B2   = 1\'bx;
+        #760  B1   = 1\'bx;
+        #780  A2   = 1\'bx;
+        #800  A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__o22ai dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O22AI_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O21AI_BLACKBOX_V
+`define SKY130_FD_SC_LS__O21AI_BLACKBOX_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & B1)
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o21ai (
+    Y ,
+    A1,
+    A2,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O21AI_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A221OI_TB_V
+`define SKY130_FD_SC_LS__A221OI_TB_V
+
+/**
+ * a221oi: 2-input AND into first two inputs of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a221oi.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg B1;
+    reg B2;
+    reg C1;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        B1   = 1\'bX;
+        B2   = 1\'bX;
+        C1   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   B1   = 1\'b0;
+        #80   B2   = 1\'b0;
+        #100  C1   = 1\'b0;
+        #120  VGND = 1\'b0;
+        #140  VNB  = 1\'b0;
+        #160  VPB  = 1\'b0;
+        #180  VPWR = 1\'b0;
+        #200  A1   = 1\'b1;
+        #220  A2   = 1\'b1;
+        #240  B1   = 1\'b1;
+        #260  B2   = 1\'b1;
+        #280  C1   = 1\'b1;
+        #300  VGND = 1\'b1;
+        #320  VNB  = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VPWR = 1\'b1;
+        #380  A1   = 1\'b0;
+        #400  A2   = 1\'b0;
+        #420  B1   = 1\'b0;
+        #440  B2   = 1\'b0;
+        #460  C1   = 1\'b0;
+        #480  VGND = 1\'b0;
+        #500  VNB  = 1\'b0;
+        #520  VPB  = 1\'b0;
+        #540  VPWR = 1\'b0;
+        #560  VPWR = 1\'b1;
+        #580  VPB  = 1\'b1;
+        #600  VNB  = 1\'b1;
+        #620  VGND = 1\'b1;
+        #640  C1   = 1\'b1;
+        #660  B2   = 1\'b1;
+        #680  B1   = 1\'b1;
+        #700  A2   = 1\'b1;
+        #720  A1   = 1\'b1;
+        #740  VPWR = 1\'bx;
+        #760  VPB  = 1\'bx;
+        #780  VNB  = 1\'bx;
+        #800  VGND = 1\'bx;
+        #820  C1   = 1\'bx;
+        #840  B2   = 1\'bx;
+        #860  B1   = 1\'bx;
+        #880  A2   = 1\'bx;
+        #900  A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__a221oi dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A221OI_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__CONB_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__CONB_BEHAVIORAL_PP_V
+
+/**
+ * conb: Constant value, low, high outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_p/sky130_fd_sc_ls__udp_pwrgood_pp_p.v""
+`include ""../../models/udp_pwrgood_pp_g/sky130_fd_sc_ls__udp_pwrgood_pp_g.v""
+
+`celldefine
+module sky130_fd_sc_ls__conb (
+    HI  ,
+    LO  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output HI  ;
+    output LO  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire pullup0_out_HI  ;
+    wire pulldown0_out_LO;
+
+    //                                Name         Output            Other arguments
+    pullup                            pullup0     (pullup0_out_HI  );
+    sky130_fd_sc_ls__udp_pwrgood_pp$P pwrgood_pp0 (HI              , pullup0_out_HI, VPWR  );
+    pulldown                          pulldown0   (pulldown0_out_LO);
+    sky130_fd_sc_ls__udp_pwrgood_pp$G pwrgood_pp1 (LO              , pulldown0_out_LO, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CONB_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__AND4BB_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__AND4BB_FUNCTIONAL_PP_V
+
+/**
+ * and4bb: 4-input AND, first two inputs inverted.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__and4bb (
+    X   ,
+    A_N ,
+    B_N ,
+    C   ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A_N ;
+    input  B_N ;
+    input  C   ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nor0_out         ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    nor                                nor0        (nor0_out         , A_N, B_N              );
+    and                                and0        (and0_out_X       , nor0_out, C, D        );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND4BB_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+( negedge RESET_B => ( Q +: RESET_B ) ) = 0:0:0 ;  // delay is tris
+( negedge RESET_B => ( Q_N -: RESET_B ) ) = 0:0:0 ;  // delay is tris
+( posedge CLK => ( Q : CLK ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall
+( posedge CLK => ( Q_N : CLK ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall
+$recrem ( posedge RESET_B , posedge CLK , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , RESETB_delayed , CLK_delayed ) ;
+$setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ;
+$setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ;
+$setuphold ( posedge CLK , posedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ;
+$setuphold ( posedge CLK , negedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ;
+$setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ;
+$setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ;
+$width ( posedge CLK &&& COND4 , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( negedge CLK &&& COND4 , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( negedge RESET_B &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__CLKBUF_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__CLKBUF_FUNCTIONAL_V
+
+/**
+ * clkbuf: Clock tree buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__clkbuf (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKBUF_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A21BO_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__A21BO_BEHAVIORAL_V
+
+/**
+ * a21bo: 2-input AND into first input of 2-input OR,
+ *        2nd input inverted.
+ *
+ *        X = ((A1 & A2) | (!B1_N))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a21bo (
+    X   ,
+    A1  ,
+    A2  ,
+    B1_N
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1_N;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nand0_out  ;
+    wire nand1_out_X;
+
+    //   Name   Output       Other arguments
+    nand nand0 (nand0_out  , A2, A1         );
+    nand nand1 (nand1_out_X, B1_N, nand0_out);
+    buf  buf0  (X          , nand1_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A21BO_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A1 +=> X) = (0:0:0,0:0:0);
+(A2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2)) (B1_N -=> X) = (0:0:0,0:0:0);
+if ((A1&!A2)) (B1_N -=> X) = (0:0:0,0:0:0);
+if ((A1&A2)) (B1_N -=> X) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FAHCON_TB_V
+`define SKY130_FD_SC_LS__FAHCON_TB_V
+
+/**
+ * fahcon: Full adder, inverted carry in, inverted carry out.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__fahcon.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg B;
+    reg CI;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire COUT_N;
+    wire SUM;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        B    = 1\'bX;
+        CI   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   B    = 1\'b0;
+        #60   CI   = 1\'b0;
+        #80   VGND = 1\'b0;
+        #100  VNB  = 1\'b0;
+        #120  VPB  = 1\'b0;
+        #140  VPWR = 1\'b0;
+        #160  A    = 1\'b1;
+        #180  B    = 1\'b1;
+        #200  CI   = 1\'b1;
+        #220  VGND = 1\'b1;
+        #240  VNB  = 1\'b1;
+        #260  VPB  = 1\'b1;
+        #280  VPWR = 1\'b1;
+        #300  A    = 1\'b0;
+        #320  B    = 1\'b0;
+        #340  CI   = 1\'b0;
+        #360  VGND = 1\'b0;
+        #380  VNB  = 1\'b0;
+        #400  VPB  = 1\'b0;
+        #420  VPWR = 1\'b0;
+        #440  VPWR = 1\'b1;
+        #460  VPB  = 1\'b1;
+        #480  VNB  = 1\'b1;
+        #500  VGND = 1\'b1;
+        #520  CI   = 1\'b1;
+        #540  B    = 1\'b1;
+        #560  A    = 1\'b1;
+        #580  VPWR = 1\'bx;
+        #600  VPB  = 1\'bx;
+        #620  VNB  = 1\'bx;
+        #640  VGND = 1\'bx;
+        #660  CI   = 1\'bx;
+        #680  B    = 1\'bx;
+        #700  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_ls__fahcon dut (.A(A), .B(B), .CI(CI), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .COUT_N(COUT_N), .SUM(SUM));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FAHCON_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O221AI_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__O221AI_PP_BLACKBOX_V
+
+/**
+ * o221ai: 2-input OR into first two inputs of 3-input NAND.
+ *
+ *         Y = !((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__o221ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O221AI_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DECAPHE_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__DECAPHE_FUNCTIONAL_PP_V
+
+/**
+ * decaphe: Shielded Decoupling capacitance filler.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__decaphe (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DECAPHE_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFSBP_1_V
+`define SKY130_FD_SC_LS__DFSBP_1_V
+
+/**
+ * dfsbp: Delay flop, inverted set, complementary outputs.
+ *
+ * Verilog wrapper for dfsbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dfsbp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dfsbp_1 (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_ls__dfsbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .SET_B(SET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dfsbp_1 (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SET_B
+);
+
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__dfsbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .SET_B(SET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFSBP_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLRBN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__DLRBN_FUNCTIONAL_PP_V
+
+/**
+ * dlrbn: Delay latch, inverted reset, inverted enable,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_pr_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlrbn (
+    Q      ,
+    Q_N    ,
+    RESET_B,
+    D      ,
+    GATE_N ,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE_N ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire RESET  ;
+    wire intgate;
+    wire buf_Q  ;
+
+    //                                     Delay       Name     Output   Other arguments
+    not                                                not0    (RESET  , RESET_B                        );
+    not                                                not1    (intgate, GATE_N                         );
+    sky130_fd_sc_ls__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q  , D, intgate, RESET, , VPWR, VGND);
+    buf                                                buf0    (Q      , buf_Q                          );
+    not                                                not2    (Q_N    , buf_Q                          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRBN_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__BUF_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__BUF_FUNCTIONAL_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__buf (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__BUF_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FILL_DIODE_BLACKBOX_V
+`define SKY130_FD_SC_LS__FILL_DIODE_BLACKBOX_V
+
+/**
+ * fill_diode: Fill diode.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__fill_diode ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FILL_DIODE_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DFBBN_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__DFBBN_BEHAVIORAL_V
+
+/**
+ * dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
+ *        complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ls__udp_dff_nsr_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dfbbn (
+    Q      ,
+    Q_N    ,
+    D      ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire RESET          ;
+    wire SET            ;
+    wire CLK            ;
+    wire buf_Q          ;
+    wire CLK_N_delayed  ;
+    wire RESET_B_delayed;
+    wire SET_B_delayed  ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+    wire condb          ;
+
+    //                                   Name  Output  Other arguments
+    not                                  not0 (RESET , RESET_B_delayed                                 );
+    not                                  not1 (SET   , SET_B_delayed                                   );
+    not                                  not2 (CLK   , CLK_N_delayed                                   );
+    sky130_fd_sc_ls__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK, D_delayed, notifier, VPWR, VGND);
+    assign awake = ( VPWR === 1\'b1 );
+    assign cond0 = ( awake && ( RESET_B_delayed === 1\'b1 ) );
+    assign cond1 = ( awake && ( SET_B_delayed === 1\'b1 ) );
+    assign condb = ( cond0 & cond1 );
+    buf                                  buf0 (Q     , buf_Q                                           );
+    not                                  not3 (Q_N   , buf_Q                                           );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFBBN_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLXTP_1_V
+`define SKY130_FD_SC_LS__DLXTP_1_V
+
+/**
+ * dlxtp: Delay latch, non-inverted enable, single output.
+ *
+ * Verilog wrapper for dlxtp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dlxtp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dlxtp_1 (
+    Q   ,
+    D   ,
+    GATE,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    input  D   ;
+    input  GATE;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__dlxtp base (
+        .Q(Q),
+        .D(D),
+        .GATE(GATE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__dlxtp_1 (
+    Q   ,
+    D   ,
+    GATE
+);
+
+    output Q   ;
+    input  D   ;
+    input  GATE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__dlxtp base (
+        .Q(Q),
+        .D(D),
+        .GATE(GATE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXTP_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__MAJ3_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__MAJ3_FUNCTIONAL_PP_V
+
+/**
+ * maj3: 3-input majority vote.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__maj3 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire and0_out         ;
+    wire and1_out         ;
+    wire or1_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out          , B, A                 );
+    and                                and0        (and0_out         , or0_out, C           );
+    and                                and1        (and1_out         , A, B                 );
+    or                                 or1         (or1_out_X        , and1_out, and0_out   );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or1_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MAJ3_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__XNOR2_2_V
+`define SKY130_FD_SC_LS__XNOR2_2_V
+
+/**
+ * xnor2: 2-input exclusive NOR.
+ *
+ *        Y = !(A ^ B)
+ *
+ * Verilog wrapper for xnor2 with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__xnor2.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__xnor2_2 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__xnor2 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__xnor2_2 (
+    Y,
+    A,
+    B
+);
+
+    output Y;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__xnor2 base (
+        .Y(Y),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XNOR2_2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DFRBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__DFRBP_BEHAVIORAL_PP_V
+
+/**
+ * dfrbp: Delay flop, inverted reset, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__dfrbp (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire buf_Q          ;
+    wire RESET          ;
+    reg  notifier       ;
+    wire D_delayed      ;
+    wire RESET_B_delayed;
+    wire CLK_delayed    ;
+    wire awake          ;
+    wire cond0          ;
+    wire cond1          ;
+
+    //                                  Name  Output  Other arguments
+    not                                 not0 (RESET , RESET_B_delayed                                    );
+    sky130_fd_sc_ls__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
+    assign cond0 = ( awake && ( RESET_B_delayed === 1\'b1 ) );
+    assign cond1 = ( awake && ( RESET_B === 1\'b1 ) );
+    buf                                 buf0 (Q     , buf_Q                                              );
+    not                                 not1 (Q_N   , buf_Q                                              );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFRBP_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND2B_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__AND2B_PP_SYMBOL_V
+
+/**
+ * and2b: 2-input AND, first input inverted.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__and2b (
+    //# {{data|Data Signals}}
+    input  A_N ,
+    input  B   ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND2B_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A_N -=> X) = (0:0:0,0:0:0);
+(B_N -=> X) = (0:0:0,0:0:0);
+(C +=> X) = (0:0:0,0:0:0);
+(D +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR2B_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__NOR2B_PP_SYMBOL_V
+
+/**
+ * nor2b: 2-input NOR, first input inverted.
+ *
+ *        Y = !(A | B | C | !D)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nor2b (
+    //# {{data|Data Signals}}
+    input  A   ,
+    input  B_N ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR2B_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__AND4B_V
+`define SKY130_FD_SC_LS__AND4B_V
+
+/**
+ * and4b: 4-input AND, first input inverted.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__and4b.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__and4b.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__and4b.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__and4b.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__AND4B_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__O22A_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__O22A_BEHAVIORAL_V
+
+/**
+ * o22a: 2-input OR into both inputs of 2-input AND.
+ *
+ *       X = ((A1 | A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__o22a (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out   ;
+    wire or1_out   ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    or  or0  (or0_out   , A2, A1          );
+    or  or1  (or1_out   , B2, B1          );
+    and and0 (and0_out_X, or0_out, or1_out);
+    buf buf0 (X         , and0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O22A_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__OR3_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__OR3_FUNCTIONAL_PP_V
+
+/**
+ * or3: 3-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__or3 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    or                                 or0         (or0_out_X        , B, A, C              );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR3_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR3_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__OR3_PP_BLACKBOX_V
+
+/**
+ * or3: 3-input OR.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__or3 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR3_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD2_1_V
+`define SKY130_FD_SC_LS__CLKDLYINV5SD2_1_V
+
+/**
+ * clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
+ *                stage gate.
+ *
+ * Verilog wrapper for clkdlyinv5sd2 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__clkdlyinv5sd2.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__clkdlyinv5sd2_1 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__clkdlyinv5sd2 base (
+        .Y(Y),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__clkdlyinv5sd2_1 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__clkdlyinv5sd2 base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV5SD2_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFXTP_V
+`define SKY130_FD_SC_LS__DFXTP_V
+
+/**
+ * dfxtp: Delay flop, single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dfxtp.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dfxtp.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__dfxtp.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__dfxtp.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFXTP_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A1 +=> X) = (0:0:0,0:0:0);
+(A2 +=> X) = (0:0:0,0:0:0);
+(A3 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&!A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&!A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&!A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2&!A3&!C1)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&!A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&!A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&!A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2&!A3&!B1)) (C1 +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A221OI_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__A221OI_PP_SYMBOL_V
+
+/**
+ * a221oi: 2-input AND into first two inputs of 3-input NOR.
+ *
+ *         Y = !((A1 & A2) | (B1 & B2) | C1)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__a221oi (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  B1  ,
+    input  B2  ,
+    input  C1  ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A221OI_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NOR3_SYMBOL_V
+`define SKY130_FD_SC_LS__NOR3_SYMBOL_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ *       Y = !(A | B | C | !D)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nor3 (
+    //# {{data|Data Signals}}
+    input  A,
+    input  B,
+    input  C,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR3_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFBBP_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__SDFBBP_PP_SYMBOL_V
+
+/**
+ * sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
+ *         clock, complementary outputs.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sdfbbp (
+    //# {{data|Data Signals}}
+    input  D      ,
+    output Q      ,
+    output Q_N    ,
+
+    //# {{control|Control Signals}}
+    input  RESET_B,
+    input  SET_B  ,
+
+    //# {{scanchain|Scan Chain}}
+    input  SCD    ,
+    input  SCE    ,
+
+    //# {{clocks|Clocking}}
+    input  CLK    ,
+
+    //# {{power|Power}}
+    input  VPB    ,
+    input  VPWR   ,
+    input  VGND   ,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFBBP_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD3_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__CLKDLYINV5SD3_FUNCTIONAL_V
+
+/**
+ * clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
+ *                stage gate.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__clkdlyinv5sd3 (
+    Y,
+    A
+);
+
+    // Module ports
+    output Y;
+    input  A;
+
+    // Local signals
+    wire not0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out_Y, A              );
+    buf buf0 (Y         , not0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV5SD3_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DLXTN_SYMBOL_V
+`define SKY130_FD_SC_LS__DLXTN_SYMBOL_V
+
+/**
+ * dlxtn: Delay latch, inverted enable, single output.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__dlxtn (
+    //# {{data|Data Signals}}
+    input  D     ,
+    output Q     ,
+
+    //# {{clocks|Clocking}}
+    input  GATE_N
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLXTN_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O221AI_2_V
+`define SKY130_FD_SC_LS__O221AI_2_V
+
+/**
+ * o221ai: 2-input OR into first two inputs of 3-input NAND.
+ *
+ *         Y = !((A1 | A2) & (B1 | B2) & C1)
+ *
+ * Verilog wrapper for o221ai with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o221ai.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o221ai_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    C1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  C1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o221ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o221ai_2 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2,
+    C1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+    input  C1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o221ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .C1(C1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O221AI_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFRBP_BLACKBOX_V
+`define SKY130_FD_SC_LS__SDFRBP_BLACKBOX_V
+
+/**
+ * sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sdfrbp (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFRBP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+( negedge SET_B => ( Q -: SET_B ) ) = 0:0:0 ;  // delay is tris
+( posedge CLK => ( Q : CLK ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall
+$recrem ( posedge SET_B , posedge CLK , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , SETB_delayed , CLK_delayed ) ;
+$setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ;
+$setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ;
+$setuphold ( posedge CLK , posedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ;
+$setuphold ( posedge CLK , negedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ;
+$setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ;
+$setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ;
+$width ( posedge CLK &&& COND4 , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( negedge CLK &&& COND4 , 1.0:1.0:1.0 , 0 , notifier ) ;
+$width ( negedge SET_B &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__MUX2_4_V
+`define SKY130_FD_SC_LS__MUX2_4_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Verilog wrapper for mux2 with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__mux2.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__mux2_4 (
+    X   ,
+    A0  ,
+    A1  ,
+    S   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A0  ;
+    input  A1  ;
+    input  S   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__mux2 base (
+        .X(X),
+        .A0(A0),
+        .A1(A1),
+        .S(S),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__mux2_4 (
+    X ,
+    A0,
+    A1,
+    S
+);
+
+    output X ;
+    input  A0;
+    input  A1;
+    input  S ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__mux2 base (
+        .X(X),
+        .A0(A0),
+        .A1(A1),
+        .S(S)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MUX2_4_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__XOR2_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__XOR2_FUNCTIONAL_PP_V
+
+/**
+ * xor2: 2-input exclusive OR.
+ *
+ *       X = A ^ B
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__xor2 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire xor0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                 Name         Output             Other arguments
+    xor                                xor0        (xor0_out_X       , B, A                  );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
+    buf                                buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__XOR2_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_PWRGOOD_PP_G_BLACKBOX_V
+`define SKY130_FD_SC_LS__UDP_PWRGOOD_PP_G_BLACKBOX_V
+
+/**
+
+ *   UDP_OUT :=x when VPWR!=1
+ *   UDP_OUT :=UDP_IN when VPWR==1
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__udp_pwrgood_pp$G (
+    UDP_OUT,
+    UDP_IN ,
+    VGND
+);
+
+    output UDP_OUT;
+    input  UDP_IN ;
+    input  VGND   ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_PWRGOOD_PP_G_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A22OI_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__A22OI_FUNCTIONAL_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__a22oi (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Local signals
+    wire nand0_out ;
+    wire nand1_out ;
+    wire and0_out_Y;
+
+    //   Name   Output      Other arguments
+    nand nand0 (nand0_out , A2, A1              );
+    nand nand1 (nand1_out , B2, B1              );
+    and  and0  (and0_out_Y, nand0_out, nand1_out);
+    buf  buf0  (Y         , and0_out_Y          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A22OI_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__FAH_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__FAH_PP_SYMBOL_V
+
+/**
+ * fah: Full adder.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__fah (
+    //# {{data|Data Signals}}
+    input  A   ,
+    input  B   ,
+    input  CI  ,
+    output COUT,
+    output SUM ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FAH_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD1_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__CLKDLYINV5SD1_BEHAVIORAL_V
+
+/**
+ * clkdlyinv5sd1: Clock Delay Inverter 5-stage 0.15um length inner
+ *                stage gate.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__clkdlyinv5sd1 (
+    Y,
+    A
+);
+
+    // Module ports
+    output Y;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out_Y, A              );
+    buf buf0 (Y         , not0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKDLYINV5SD1_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFBBN_PP_SYMBOL_V
+`define SKY130_FD_SC_LS__SDFBBN_PP_SYMBOL_V
+
+/**
+ * sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
+ *         clock, complementary outputs.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sdfbbn (
+    //# {{data|Data Signals}}
+    input  D      ,
+    output Q      ,
+    output Q_N    ,
+
+    //# {{control|Control Signals}}
+    input  RESET_B,
+    input  SET_B  ,
+
+    //# {{scanchain|Scan Chain}}
+    input  SCD    ,
+    input  SCE    ,
+
+    //# {{clocks|Clocking}}
+    input  CLK_N  ,
+
+    //# {{power|Power}}
+    input  VPB    ,
+    input  VPWR   ,
+    input  VGND   ,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFBBN_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__BUF_16_V
+`define SKY130_FD_SC_LS__BUF_16_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog wrapper for buf with size of 16 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__buf.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__buf_16 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__buf base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__buf_16 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__buf base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__BUF_16_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DFRTP_TB_V
+`define SKY130_FD_SC_LS__DFRTP_TB_V
+
+/**
+ * dfrtp: Delay flop, inverted reset, single output.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__dfrtp.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg RESET_B;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Q;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D       = 1\'bX;
+        RESET_B = 1\'bX;
+        VGND    = 1\'bX;
+        VNB     = 1\'bX;
+        VPB     = 1\'bX;
+        VPWR    = 1\'bX;
+
+        #20   D       = 1\'b0;
+        #40   RESET_B = 1\'b0;
+        #60   VGND    = 1\'b0;
+        #80   VNB     = 1\'b0;
+        #100  VPB     = 1\'b0;
+        #120  VPWR    = 1\'b0;
+        #140  D       = 1\'b1;
+        #160  RESET_B = 1\'b1;
+        #180  VGND    = 1\'b1;
+        #200  VNB     = 1\'b1;
+        #220  VPB     = 1\'b1;
+        #240  VPWR    = 1\'b1;
+        #260  D       = 1\'b0;
+        #280  RESET_B = 1\'b0;
+        #300  VGND    = 1\'b0;
+        #320  VNB     = 1\'b0;
+        #340  VPB     = 1\'b0;
+        #360  VPWR    = 1\'b0;
+        #380  VPWR    = 1\'b1;
+        #400  VPB     = 1\'b1;
+        #420  VNB     = 1\'b1;
+        #440  VGND    = 1\'b1;
+        #460  RESET_B = 1\'b1;
+        #480  D       = 1\'b1;
+        #500  VPWR    = 1\'bx;
+        #520  VPB     = 1\'bx;
+        #540  VNB     = 1\'bx;
+        #560  VGND    = 1\'bx;
+        #580  RESET_B = 1\'bx;
+        #600  D       = 1\'bx;
+    end
+
+    // Create a clock
+    reg CLK;
+    initial
+    begin
+        CLK = 1\'b0;
+    end
+
+    always
+    begin
+        #5 CLK = ~CLK;
+    end
+
+    sky130_fd_sc_ls__dfrtp dut (.D(D), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFRTP_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__FAHCON_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__FAHCON_FUNCTIONAL_V
+
+/**
+ * fahcon: Full adder, inverted carry in, inverted carry out.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__fahcon (
+    COUT_N,
+    SUM   ,
+    A     ,
+    B     ,
+    CI
+);
+
+    // Module ports
+    output COUT_N;
+    output SUM   ;
+    input  A     ;
+    input  B     ;
+    input  CI    ;
+
+    // Local signals
+    wire xor0_out_SUM ;
+    wire a_b          ;
+    wire a_ci         ;
+    wire b_ci         ;
+    wire or0_out_coutn;
+
+    //  Name  Output         Other arguments
+    xor xor0 (xor0_out_SUM , A, B, CI       );
+    buf buf0 (SUM          , xor0_out_SUM   );
+    nor nor0 (a_b          , A, B           );
+    nor nor1 (a_ci         , A, CI          );
+    nor nor2 (b_ci         , B, CI          );
+    or  or0  (or0_out_coutn, a_b, a_ci, b_ci);
+    buf buf1 (COUT_N       , or0_out_coutn  );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__FAHCON_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A31OI_V
+`define SKY130_FD_SC_LS__A31OI_V
+
+/**
+ * a31oi: 3-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a31oi.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a31oi.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__a31oi.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__a31oi.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A31OI_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SDLCLKP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_LS__SDLCLKP_BEHAVIORAL_PP_V
+
+/**
+ * sdlclkp: Scan gated clock.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_ls__sdlclkp (
+    GCLK,
+    SCE ,
+    GATE,
+    CLK ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output GCLK;
+    input  SCE ;
+    input  GATE;
+    input  CLK ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire m0              ;
+    wire m0n             ;
+    wire clkn            ;
+    wire CLK_delayed     ;
+    wire SCE_delayed     ;
+    wire GATE_delayed    ;
+    wire SCE_gate_delayed;
+    reg  notifier        ;
+    wire awake           ;
+    wire SCE_awake       ;
+    wire GATE_awake      ;
+
+    //                                    Name     Output            Other arguments
+    not                                   not0    (m0n             , m0                                          );
+    not                                   not1    (clkn            , CLK_delayed                                 );
+    nor                                   nor0    (SCE_gate_delayed, GATE_delayed, SCE_delayed                   );
+    sky130_fd_sc_ls__udp_dlatch$P_pp$PG$N dlatch0 (m0              , SCE_gate_delayed, clkn, notifier, VPWR, VGND);
+    and                                   and0    (GCLK            , m0n, CLK_delayed                            );
+    assign awake = ( VPWR === 1\'b1 );
+    assign SCE_awake = ( awake & ( GATE_delayed === 1\'b0 ) );
+    assign GATE_awake = ( awake & ( SCE_delayed === 1\'b0 ) );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDLCLKP_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__A41OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__A41OI_FUNCTIONAL_PP_V
+
+/**
+ * a41oi: 4-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3 & A4) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__a41oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                 Name         Output             Other arguments
+    and                                and0        (and0_out         , A1, A2, A3, A4        );
+    nor                                nor0        (nor0_out_Y       , B1, and0_out          );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A41OI_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__MUX2I_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__MUX2I_PP_BLACKBOX_V
+
+/**
+ * mux2i: 2-input multiplexer, output inverted.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__mux2i (
+    Y   ,
+    A0  ,
+    A1  ,
+    S   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A0  ;
+    input  A1  ;
+    input  S   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__MUX2I_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__DECAP_V
+`define SKY130_FD_SC_LS__DECAP_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__decap.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__decap.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__decap.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__decap.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DECAP_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A2111OI_1_V
+`define SKY130_FD_SC_LS__A2111OI_1_V
+
+/**
+ * a2111oi: 2-input AND into first input of 4-input NOR.
+ *
+ *          Y = !((A1 & A2) | B1 | C1 | D1)
+ *
+ * Verilog wrapper for a2111oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a2111oi.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a2111oi_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    C1  ,
+    D1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  C1  ;
+    input  D1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a2111oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a2111oi_1 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    C1,
+    D1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  C1;
+    input  D1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a2111oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .C1(C1),
+        .D1(D1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A2111OI_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__SDFSTP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__SDFSTP_FUNCTIONAL_PP_V
+
+/**
+ * sdfstp: Scan delay flop, inverted set, non-inverted clock,
+ *         single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ls__udp_dff_ps_pp_pg_n.v""
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v""
+
+`celldefine
+module sky130_fd_sc_ls__sdfstp (
+    Q    ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire buf_Q  ;
+    wire SET    ;
+    wire mux_out;
+
+    //                                  Delay       Name       Output   Other arguments
+    not                                             not0      (SET    , SET_B                          );
+    sky130_fd_sc_ls__udp_mux_2to1                   mux_2to10 (mux_out, D, SCD, SCE                    );
+    sky130_fd_sc_ls__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK, SET, , VPWR, VGND);
+    buf                                             buf0      (Q      , buf_Q                          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFSTP_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__CLKINV_SYMBOL_V
+`define SKY130_FD_SC_LS__CLKINV_SYMBOL_V
+
+/**
+ * clkinv: Clock tree inverter.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__clkinv (
+    //# {{data|Data Signals}}
+    input  A,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__CLKINV_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__TAPVGNDNOVPB_SYMBOL_V
+`define SKY130_FD_SC_LS__TAPVGNDNOVPB_SYMBOL_V
+
+/**
+ * tapvgndnovpb: Substrate only tap cell.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__tapvgndnovpb ();
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__TAPVGNDNOVPB_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__UDP_DFF_PR_PP_PG_N_TB_V
+`define SKY130_FD_SC_LS__UDP_DFF_PR_PP_PG_N_TB_V
+
+/**
+ * udp_dff$PR_pp$PG$N: Positive edge triggered D flip-flop with active
+ *                     high
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg RESET;
+    reg NOTIFIER;
+    reg VPWR;
+    reg VGND;
+
+    // Outputs are wires
+    wire Q;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D        = 1\'bX;
+        NOTIFIER = 1\'bX;
+        RESET    = 1\'bX;
+        VGND     = 1\'bX;
+        VPWR     = 1\'bX;
+
+        #20   D        = 1\'b0;
+        #40   NOTIFIER = 1\'b0;
+        #60   RESET    = 1\'b0;
+        #80   VGND     = 1\'b0;
+        #100  VPWR     = 1\'b0;
+        #120  D        = 1\'b1;
+        #140  NOTIFIER = 1\'b1;
+        #160  RESET    = 1\'b1;
+        #180  VGND     = 1\'b1;
+        #200  VPWR     = 1\'b1;
+        #220  D        = 1\'b0;
+        #240  NOTIFIER = 1\'b0;
+        #260  RESET    = 1\'b0;
+        #280  VGND     = 1\'b0;
+        #300  VPWR     = 1\'b0;
+        #320  VPWR     = 1\'b1;
+        #340  VGND     = 1\'b1;
+        #360  RESET    = 1\'b1;
+        #380  NOTIFIER = 1\'b1;
+        #400  D        = 1\'b1;
+        #420  VPWR     = 1\'bx;
+        #440  VGND     = 1\'bx;
+        #460  RESET    = 1\'bx;
+        #480  NOTIFIER = 1\'bx;
+        #500  D        = 1\'bx;
+    end
+
+    // Create a clock
+    reg CLK;
+    initial
+    begin
+        CLK = 1\'b0;
+    end
+
+    always
+    begin
+        #5 CLK = ~CLK;
+    end
+
+    sky130_fd_sc_ls__udp_dff$PR_pp$PG$N dut (.D(D), .RESET(RESET), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__UDP_DFF_PR_PP_PG_N_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND3_SYMBOL_V
+`define SKY130_FD_SC_LS__NAND3_SYMBOL_V
+
+/**
+ * nand3: 3-input NAND.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__nand3 (
+    //# {{data|Data Signals}}
+    input  A,
+    input  B,
+    input  C,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND3_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFBBN_PP_BLACKBOX_V
+`define SKY130_FD_SC_LS__SDFBBN_PP_BLACKBOX_V
+
+/**
+ * sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
+ *         clock, complementary outputs.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__sdfbbn (
+    Q      ,
+    Q_N    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    CLK_N  ,
+    SET_B  ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  CLK_N  ;
+    input  SET_B  ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFBBN_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__A31OI_2_V
+`define SKY130_FD_SC_LS__A31OI_2_V
+
+/**
+ * a31oi: 3-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2 & A3) | B1)
+ *
+ * Verilog wrapper for a31oi with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__a31oi.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a31oi_2 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__a31oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__a31oi_2 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__a31oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__A31OI_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__SDFXTP_1_V
+`define SKY130_FD_SC_LS__SDFXTP_1_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Verilog wrapper for sdfxtp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__sdfxtp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sdfxtp_1 (
+    Q   ,
+    CLK ,
+    D   ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__sdfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__sdfxtp_1 (
+    Q  ,
+    CLK,
+    D  ,
+    SCD,
+    SCE
+);
+
+    output Q  ;
+    input  CLK;
+    input  D  ;
+    input  SCD;
+    input  SCE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__sdfxtp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__SDFXTP_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DLRTN_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__DLRTN_FUNCTIONAL_V
+
+/**
+ * dlrtn: Delay latch, inverted reset, inverted enable, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_pr/sky130_fd_sc_ls__udp_dlatch_pr.v""
+
+`celldefine
+module sky130_fd_sc_ls__dlrtn (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE_N
+);
+
+    // Module ports
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE_N ;
+
+    // Local signals
+    wire RESET  ;
+    wire intgate;
+    wire buf_Q  ;
+
+    //                             Delay       Name     Output   Other arguments
+    not                                        not0    (RESET  , RESET_B          );
+    not                                        not1    (intgate, GATE_N           );
+    sky130_fd_sc_ls__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q  , D, intgate, RESET);
+    buf                                        buf0    (Q      , buf_Q            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DLRTN_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__EBUFN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_LS__EBUFN_FUNCTIONAL_PP_V
+
+/**
+ * ebufn: Tri-state buffer, negative enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_ls__ebufn (
+    Z   ,
+    A   ,
+    TE_B,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire pwrgood_pp0_out_A  ;
+    wire pwrgood_pp1_out_teb;
+
+    //                                 Name         Output               Other arguments
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A  , A, VPWR, VGND                         );
+    sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND                      );
+    bufif0                             bufif00     (Z                  , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__EBUFN_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__OR4BB_SYMBOL_V
+`define SKY130_FD_SC_LS__OR4BB_SYMBOL_V
+
+/**
+ * or4bb: 4-input OR, first two inputs inverted.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_ls__or4bb (
+    //# {{data|Data Signals}}
+    input  A  ,
+    input  B  ,
+    input  C_N,
+    input  D_N,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__OR4BB_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__O41AI_4_V
+`define SKY130_FD_SC_LS__O41AI_4_V
+
+/**
+ * o41ai: 4-input OR into 2-input NAND.
+ *
+ *        Y = !((A1 | A2 | A3 | A4) & B1)
+ *
+ * Verilog wrapper for o41ai with size of 4 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_ls__o41ai.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o41ai_4 (
+    Y   ,
+    A1  ,
+    A2  ,
+    A3  ,
+    A4  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  A4  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_ls__o41ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_ls__o41ai_4 (
+    Y ,
+    A1,
+    A2,
+    A3,
+    A4,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  A4;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_ls__o41ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .A3(A3),
+        .A4(A4),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__O41AI_4_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_LS__NAND2_V
+`define SKY130_FD_SC_LS__NAND2_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__nand2.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__nand2.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_ls__nand2.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_ls__nand2.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NAND2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__DFXBP_FUNCTIONAL_V
+`define SKY130_FD_SC_LS__DFXBP_FUNCTIONAL_V
+
+/**
+ * dfxbp: Delay flop, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_p/sky130_fd_sc_ls__udp_dff_p.v""
+
+`celldefine
+module sky130_fd_sc_ls__dfxbp (
+    Q  ,
+    Q_N,
+    CLK,
+    D
+);
+
+    // Module ports
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+
+    // Local signals
+    wire buf_Q;
+
+    //                         Delay       Name  Output  Other arguments
+    sky130_fd_sc_ls__udp_dff$P `UNIT_DELAY dff0 (buf_Q , D, CLK         );
+    buf                                    buf0 (Q     , buf_Q          );
+    not                                    not0 (Q_N   , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__DFXBP_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_LS__NOR4_BEHAVIORAL_V
+`define SKY130_FD_SC_LS__NOR4_BEHAVIORAL_V
+
+/**
+ * nor4: 4-input NOR.
+ *
+ *       Y = !(A | B | C | D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_ls__nor4 (
+    Y,
+    A,
+    B,
+    C,
+    D
+);
+
+    // Module ports
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+    input  D;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    nor nor0 (nor0_out_Y, A, B, C, D     );
+    buf buf0 (Y         , nor0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_LS__NOR4_BEHAVIORAL_V"