diff --git "a/shard_new_new_cleaned_v_text_34.csv" "b/shard_new_new_cleaned_v_text_34.csv"
new file mode 100644--- /dev/null
+++ "b/shard_new_new_cleaned_v_text_34.csv"
@@ -0,0 +1,107693 @@
+text
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__A22O_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HVL__A22O_FUNCTIONAL_PP_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ *       X = ((A1 & A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__a22o (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire and1_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                  Name         Output             Other arguments
+    and                                 and0        (and0_out         , B1, B2               );
+    and                                 and1        (and1_out         , A1, A2               );
+    or                                  or0         (or0_out_X        , and1_out, and0_out   );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                 buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__A22O_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__DFRBP_FUNCTIONAL_V
+`define SKY130_FD_SC_HVL__DFRBP_FUNCTIONAL_V
+
+/**
+ * dfrbp: Delay flop, inverted reset, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_pr/sky130_fd_sc_hvl__udp_dff_pr.v""
+
+`celldefine
+module sky130_fd_sc_hvl__dfrbp (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+
+    // Local signals
+    wire buf_Q;
+    wire RESET;
+
+    //                           Delay       Name  Output  Other arguments
+    not                                      not0 (RESET , RESET_B        );
+    sky130_fd_sc_hvl__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET  );
+    buf                                      buf0 (Q     , buf_Q          );
+    not                                      not1 (Q_N   , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DFRBP_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__NOR3_PP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__NOR3_PP_BLACKBOX_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ *       Y = !(A | B | C | !D)
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__nor3 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__NOR3_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if ((!B&!C)) (A -=> Y ) = (0:0:0,0:0:0);  // delays are tris,tfall
+ifnone (A -=> Y ) = (0:0:0,0:0:0);  // delays are tris,tfall
+if ((!A&!C)) (B -=> Y ) = (0:0:0,0:0:0);  // delays are tris,tfall
+ifnone (B -=> Y ) = (0:0:0,0:0:0);  // delays are tris,tfall
+if ((!A&!B)) (C -=> Y ) = (0:0:0,0:0:0);  // delays are tris,tfall
+ifnone (C -=> Y ) = (0:0:0,0:0:0);  // delays are tris,tfall
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_DLATCH_P_SYMBOL_V
+`define SKY130_FD_SC_HVL__UDP_DLATCH_P_SYMBOL_V
+
+/**
+ * udp_dlatch$P: D-latch, gated standard drive / active high
+ *               (Q output UDP)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__udp_dlatch$P (
+    //# {{data|Data Signals}}
+    input  D   ,
+    output Q   ,
+
+    //# {{clocks|Clocking}}
+    input  GATE
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_DLATCH_P_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__NAND3_PP_SYMBOL_V
+`define SKY130_FD_SC_HVL__NAND3_PP_SYMBOL_V
+
+/**
+ * nand3: 3-input NAND.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__nand3 (
+    //# {{data|Data Signals}}
+    input  A   ,
+    input  B   ,
+    input  C   ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__NAND3_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DECAP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__DECAP_BLACKBOX_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__decap ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DECAP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__A21O_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HVL__A21O_FUNCTIONAL_PP_V
+
+/**
+ * a21o: 2-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__a21o (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                  Name         Output             Other arguments
+    and                                 and0        (and0_out         , A1, A2               );
+    or                                  or0         (or0_out_X        , and0_out, B1         );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                 buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__A21O_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__O21A_BLACKBOX_V
+`define SKY130_FD_SC_HVL__O21A_BLACKBOX_V
+
+/**
+ * o21a: 2-input OR into first input of 2-input AND.
+ *
+ *       X = ((A1 | A2) & B1)
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__o21a (
+    X ,
+    A1,
+    A2,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__O21A_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__INV_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HVL__INV_BEHAVIORAL_PP_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__inv (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                  Name         Output             Other arguments
+    not                                 not0        (not0_out_Y       , A                     );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
+    buf                                 buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__INV_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A1 +=> X) = (0:0:0,0:0:0);
+(A2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2)) (B1 +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__PROBE_P_PP_SYMBOL_V
+`define SKY130_FD_SC_HVL__PROBE_P_PP_SYMBOL_V
+
+/**
+ * probe_p: Virtual voltage probe point.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__probe_p (
+    //# {{data|Data Signals}}
+    input  A   ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__PROBE_P_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(negedge SET_B => (Q -: SET_B ) ) = 0:0:0;  // delay is tris
+(negedge SET_B => (Q_N +: SET_B ) ) = 0:0:0;  // delay is tris
+(posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall
+(posedge CLK => (Q_N : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall
+$width (posedge CLK &&& (SET_B===1\'b1) , 0:0:0, 0, notifier);
+$width (negedge CLK &&& (SET_B===1\'b1) , 0:0:0, 0, notifier);
+$width (negedge SET_B , 0:0:0 , 0 , notifier ) ;
+$recrem ( posedge SET_B , posedge CLK , 0:0:0, 0:0:0, notifier , , , SETB_delayed , CLK_delayed ) ;
+$setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND0 , CLK_delayed , D_delayed ) ;
+$setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND0 , CLK_delayed , D_delayed ) ;
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__PROBEC_P_BEHAVIORAL_V
+`define SKY130_FD_SC_HVL__PROBEC_P_BEHAVIORAL_V
+
+/**
+ * probec_p: Virtual current probe point.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__probec_p (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__PROBEC_P_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_LH_PP_SYMBOL_V
+`define SKY130_FD_SC_HVL__LSBUFHV2HV_LH_PP_SYMBOL_V
+
+/**
+ * lsbufhv2hv_lh: Level shifting buffer, High Voltage to High Voltage,
+ *                Lower Voltage to Higher Voltage.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__lsbufhv2hv_lh (
+    //# {{data|Data Signals}}
+    input  A       ,
+    output X       ,
+
+    //# {{power|Power}}
+    input  LOWHVPWR,
+    input  VPB     ,
+    input  VPWR    ,
+    input  VGND    ,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFHV2HV_LH_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__NOR3_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HVL__NOR3_FUNCTIONAL_PP_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ *       Y = !(A | B | C | !D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__nor3 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                  Name         Output             Other arguments
+    nor                                 nor0        (nor0_out_Y       , C, A, B               );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                 buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__NOR3_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_P_BLACKBOX_V
+`define SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_P_BLACKBOX_V
+
+/**
+
+ *   UDP_OUT :=x when VPWR!=1
+ *   UDP_OUT :=UDP_IN when VPWR==1
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__udp_pwrgood_pp$P (
+    UDP_OUT,
+    UDP_IN ,
+    VPWR
+);
+
+    output UDP_OUT;
+    input  UDP_IN ;
+    input  VPWR   ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_P_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__A22OI_TB_V
+`define SKY130_FD_SC_HVL__A22OI_TB_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__a22oi.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg B1;
+    reg B2;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        B1   = 1\'bX;
+        B2   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   B1   = 1\'b0;
+        #80   B2   = 1\'b0;
+        #100  VGND = 1\'b0;
+        #120  VNB  = 1\'b0;
+        #140  VPB  = 1\'b0;
+        #160  VPWR = 1\'b0;
+        #180  A1   = 1\'b1;
+        #200  A2   = 1\'b1;
+        #220  B1   = 1\'b1;
+        #240  B2   = 1\'b1;
+        #260  VGND = 1\'b1;
+        #280  VNB  = 1\'b1;
+        #300  VPB  = 1\'b1;
+        #320  VPWR = 1\'b1;
+        #340  A1   = 1\'b0;
+        #360  A2   = 1\'b0;
+        #380  B1   = 1\'b0;
+        #400  B2   = 1\'b0;
+        #420  VGND = 1\'b0;
+        #440  VNB  = 1\'b0;
+        #460  VPB  = 1\'b0;
+        #480  VPWR = 1\'b0;
+        #500  VPWR = 1\'b1;
+        #520  VPB  = 1\'b1;
+        #540  VNB  = 1\'b1;
+        #560  VGND = 1\'b1;
+        #580  B2   = 1\'b1;
+        #600  B1   = 1\'b1;
+        #620  A2   = 1\'b1;
+        #640  A1   = 1\'b1;
+        #660  VPWR = 1\'bx;
+        #680  VPB  = 1\'bx;
+        #700  VNB  = 1\'bx;
+        #720  VGND = 1\'bx;
+        #740  B2   = 1\'bx;
+        #760  B1   = 1\'bx;
+        #780  A2   = 1\'bx;
+        #800  A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_hvl__a22oi dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__A22OI_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__PROBE_P_BEHAVIORAL_V
+`define SKY130_FD_SC_HVL__PROBE_P_BEHAVIORAL_V
+
+/**
+ * probe_p: Virtual voltage probe point.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__probe_p (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__PROBE_P_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__MUX4_SYMBOL_V
+`define SKY130_FD_SC_HVL__MUX4_SYMBOL_V
+
+/**
+ * mux4: 4-input multiplexer.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__mux4 (
+    //# {{data|Data Signals}}
+    input  A0,
+    input  A1,
+    input  A2,
+    input  A3,
+    output X ,
+
+    //# {{control|Control Signals}}
+    input  S0,
+    input  S1
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__MUX4_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DFXTP_V
+`define SKY130_FD_SC_HVL__DFXTP_V
+
+/**
+ * dfxtp: Delay flop, single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__dfxtp.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__dfxtp.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__dfxtp.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__dfxtp.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DFXTP_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__DLRTP_BEHAVIORAL_V
+`define SKY130_FD_SC_HVL__DLRTP_BEHAVIORAL_V
+
+/**
+ * dlrtp: Delay latch, inverted reset, non-inverted enable,
+ *        single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_hvl__udp_dlatch_pr_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_hvl__dlrtp (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE
+);
+
+    // Module ports
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire RESET          ;
+    reg  notifier       ;
+    wire cond0          ;
+    wire D_delayed      ;
+    wire GATE_delayed   ;
+    wire RESET_delayed  ;
+    wire RESET_B_delayed;
+    wire buf_Q          ;
+
+    //                                      Name     Output  Other arguments
+    not                                     not0    (RESET , RESET_B_delayed                                     );
+    sky130_fd_sc_hvl__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
+    assign cond0 = ( RESET_B_delayed === 1\'b1 );
+    buf                                     buf0    (Q     , buf_Q                                               );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DLRTP_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__OR3_FUNCTIONAL_V
+`define SKY130_FD_SC_HVL__OR3_FUNCTIONAL_V
+
+/**
+ * or3: 3-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__or3 (
+    X,
+    A,
+    B,
+    C
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Local signals
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    or  or0  (or0_out_X, B, A, C        );
+    buf buf0 (X        , or0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__OR3_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SDLCLKP_PP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__SDLCLKP_PP_BLACKBOX_V
+
+/**
+ * sdlclkp: Scan gated clock.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__sdlclkp (
+    GCLK,
+    SCE ,
+    GATE,
+    CLK ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output GCLK;
+    input  SCE ;
+    input  GATE;
+    input  CLK ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDLCLKP_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DFSBP_1_V
+`define SKY130_FD_SC_HVL__DFSBP_1_V
+
+/**
+ * dfsbp: Delay flop, inverted set, complementary outputs.
+ *
+ * Verilog wrapper for dfsbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__dfsbp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__dfsbp_1 (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hvl__dfsbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .SET_B(SET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__dfsbp_1 (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SET_B
+);
+
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hvl__dfsbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .SET_B(SET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DFSBP_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__SDFSTP_BEHAVIORAL_V
+`define SKY130_FD_SC_HVL__SDFSTP_BEHAVIORAL_V
+
+/**
+ * sdfstp: Scan delay flop, inverted set, non-inverted clock,
+ *         single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v""
+`include ""../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hvl__udp_dff_ps_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_hvl__sdfstp (
+    Q    ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B
+);
+
+    // Module ports
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q        ;
+    wire SET          ;
+    wire mux_out      ;
+    reg  notifier     ;
+    wire cond0        ;
+    wire cond1        ;
+    wire cond2        ;
+    wire cond3        ;
+    wire D_delayed    ;
+    wire SCD_delayed  ;
+    wire SCE_delayed  ;
+    wire SET_B_delayed;
+    wire CLK_delayed  ;
+
+    //                                   Name       Output   Other arguments
+    not                                  not0      (SET    , SET_B_delayed                                  );
+    sky130_fd_sc_hvl__udp_mux_2to1       mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed            );
+    sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
+    assign cond0 = ( SET_B_delayed === 1\'b1 );
+    assign cond1 = ( ( SCE_delayed === 1\'b0 ) & cond0 );
+    assign cond2 = ( ( SCE_delayed === 1\'b1 ) & cond0 );
+    assign cond3 = ( ( D_delayed !== SCD_delayed ) & cond0 );
+    buf                                  buf0      (Q      , buf_Q                                          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFSTP_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__XNOR2_PP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__XNOR2_PP_BLACKBOX_V
+
+/**
+ * xnor2: 2-input exclusive NOR.
+ *
+ *        Y = !(A ^ B)
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__xnor2 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__XNOR2_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if ((!B)) (A -=> Y ) = (0:0:0,0:0:0);  // delays are tris,tfall
+ifnone (A -=> Y ) = (0:0:0,0:0:0);  // delays are tris,tfall
+if ((!A)) (B -=> Y ) = (0:0:0,0:0:0);  // delays are tris,tfall
+ifnone (B -=> Y ) = (0:0:0,0:0:0);  // delays are tris,tfall
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_MUX_4TO2_TB_V
+`define SKY130_FD_SC_HVL__UDP_MUX_4TO2_TB_V
+
+/**
+ * udp_mux_4to2: Four to one multiplexer with 2 select controls
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__udp_mux_4to2.v""
+
+module top();
+
+    // Inputs are registered
+    reg A0;
+    reg A1;
+    reg A2;
+    reg A3;
+    reg S0;
+    reg S1;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A0 = 1\'bX;
+        A1 = 1\'bX;
+        A2 = 1\'bX;
+        A3 = 1\'bX;
+        S0 = 1\'bX;
+        S1 = 1\'bX;
+
+        #20   A0 = 1\'b0;
+        #40   A1 = 1\'b0;
+        #60   A2 = 1\'b0;
+        #80   A3 = 1\'b0;
+        #100  S0 = 1\'b0;
+        #120  S1 = 1\'b0;
+        #140  A0 = 1\'b1;
+        #160  A1 = 1\'b1;
+        #180  A2 = 1\'b1;
+        #200  A3 = 1\'b1;
+        #220  S0 = 1\'b1;
+        #240  S1 = 1\'b1;
+        #260  A0 = 1\'b0;
+        #280  A1 = 1\'b0;
+        #300  A2 = 1\'b0;
+        #320  A3 = 1\'b0;
+        #340  S0 = 1\'b0;
+        #360  S1 = 1\'b0;
+        #380  S1 = 1\'b1;
+        #400  S0 = 1\'b1;
+        #420  A3 = 1\'b1;
+        #440  A2 = 1\'b1;
+        #460  A1 = 1\'b1;
+        #480  A0 = 1\'b1;
+        #500  S1 = 1\'bx;
+        #520  S0 = 1\'bx;
+        #540  A3 = 1\'bx;
+        #560  A2 = 1\'bx;
+        #580  A1 = 1\'bx;
+        #600  A0 = 1\'bx;
+    end
+
+    sky130_fd_sc_hvl__udp_mux_4to2 dut (.A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S0), .S1(S1), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_MUX_4TO2_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__O22A_PP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__O22A_PP_BLACKBOX_V
+
+/**
+ * o22a: 2-input OR into both inputs of 2-input AND.
+ *
+ *       X = ((A1 | A2) & (B1 | B2))
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__o22a (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__O22A_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__A22OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HVL__A22OI_BEHAVIORAL_PP_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__a22oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out        ;
+    wire nand1_out        ;
+    wire and0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                  Name         Output             Other arguments
+    nand                                nand0       (nand0_out        , A2, A1                );
+    nand                                nand1       (nand1_out        , B2, B1                );
+    and                                 and0        (and0_out_Y       , nand0_out, nand1_out  );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
+    buf                                 buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__A22OI_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_DFF_PR_PP_PG_N_V
+`define SKY130_FD_SC_HVL__UDP_DFF_PR_PP_PG_N_V
+
+/**
+ * udp_dff$PR_pp$PG$N: Positive edge triggered D flip-flop with active
+ *                     high
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`include ""./sky130_fd_sc_hvl__udp_dff_pr_pp_pg_n.blackbox.v""
+`else
+primitive sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N (
+    Q       ,
+    D       ,
+    CLK     ,
+    RESET   ,
+    NOTIFIER,
+    VPWR    ,
+    VGND
+);
+
+    output Q       ;
+    input  D       ;
+    input  CLK     ;
+    input  RESET   ;
+    input  NOTIFIER;
+    input  VPWR    ;
+    input  VGND    ;
+
+    reg Q;
+
+    table
+     //          D           CLK  RESET NOTIFIER VPWR VGND :  Qt : Qt+1
+                 *            b     0      ?      1    0   :  ?  :  -    ; // data event, hold unless CP==x
+                 ?           (?0)   0      ?      1    0   :  ?  :  -    ; // CP => 0, hold
+                 ?            b    (?0)    ?      1    0   :  ?  :  -    ; // R => 0, hold unless CP==x
+                 ?            ?     1      ?      1    0   :  ?  :  0    ; // async reset
+                 0            r     ?      ?      1    0   :  ?  :  0    ; // clock data on CP
+                 1            r     0      ?      1    0   :  ?  :  1    ; // clock data on CP
+                 0           (x1)   ?      ?      1    0   :  0  :  0    ; // possible CP, hold when D==Q==0
+                 1           (x1)   0      ?      1    0   :  1  :  1    ; // possible CP, hold when D==Q==1
+                 0            x     ?      ?      1    0   :  0  :  0    ; // unkown CP, hold when D==Q==0
+                 1            x     0      ?      1    0   :  1  :  1    ; // unkown CP, hold when D==Q==1
+                 ?            b    (?x)    ?      1    0   :  0  :  0    ; // R=>x, hold when Q==0 unless CP==x
+                 ?            f     x      ?      1    0   :  0  :  0    ; // JCWR reducing pessimism
+        // [\'IfDef(functional)\', \'\']                 ?            ?     ?      *      1    0   :  ?  :  -    ; // ignore notifier
+        // [\'Else\', \'\']                 ?            ?     ?      *      1    0   :  ?  :  x    ; // Q => X on any change on notifier
+        // [\'EndIfDef(functional)\', \'\']                 ?            ?     ?      ?      *    ?   :  ?  :  x    ; // Q => X on any change on vpwr
+                 ?            ?     ?      ?      ?    *   :  ?  :  x    ; // Q => X on any change on vgnd
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_DFF_PR_PP_PG_N_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_DFF_P_SYMBOL_V
+`define SKY130_FD_SC_HVL__UDP_DFF_P_SYMBOL_V
+
+/**
+ * udp_dff$P: Positive edge triggered D flip-flop (Q output UDP).
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__udp_dff$P (
+    //# {{data|Data Signals}}
+    input  D  ,
+    output Q  ,
+
+    //# {{clocks|Clocking}}
+    input  CLK
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_DFF_P_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_LH_V
+`define SKY130_FD_SC_HVL__LSBUFHV2HV_LH_V
+
+/**
+ * lsbufhv2hv_lh: Level shifting buffer, High Voltage to High Voltage,
+ *                Lower Voltage to Higher Voltage.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__lsbufhv2hv_lh.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__lsbufhv2hv_lh.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__lsbufhv2hv_lh.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__lsbufhv2hv_lh.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFHV2HV_LH_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__PROBE_P_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HVL__PROBE_P_FUNCTIONAL_PP_V
+
+/**
+ * probe_p: Virtual voltage probe point.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__probe_p (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                  Name         Output             Other arguments
+    buf                                 buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                 buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__PROBE_P_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__A21OI_SYMBOL_V
+`define SKY130_FD_SC_HVL__A21OI_SYMBOL_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | B1)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__a21oi (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  B1,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__A21OI_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__OR3_SYMBOL_V
+`define SKY130_FD_SC_HVL__OR3_SYMBOL_V
+
+/**
+ * or3: 3-input OR.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__or3 (
+    //# {{data|Data Signals}}
+    input  A,
+    input  B,
+    input  C,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__OR3_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__SDFRTP_FUNCTIONAL_V
+`define SKY130_FD_SC_HVL__SDFRTP_FUNCTIONAL_V
+
+/**
+ * sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
+ *         single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v""
+`include ""../../models/udp_dff_pr/sky130_fd_sc_hvl__udp_dff_pr.v""
+
+`celldefine
+module sky130_fd_sc_hvl__sdfrtp (
+    Q      ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+
+    // Local signals
+    wire buf_Q  ;
+    wire RESET  ;
+    wire mux_out;
+
+    //                             Delay       Name       Output   Other arguments
+    not                                        not0      (RESET  , RESET_B            );
+    sky130_fd_sc_hvl__udp_mux_2to1             mux_2to10 (mux_out, D, SCD, SCE        );
+    sky130_fd_sc_hvl__udp_dff$PR   `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK, RESET);
+    buf                                        buf0      (Q      , buf_Q              );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFRTP_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__O21AI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HVL__O21AI_BEHAVIORAL_PP_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__o21ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                  Name         Output             Other arguments
+    or                                  or0         (or0_out          , A2, A1                 );
+    nand                                nand0       (nand0_out_Y      , B1, or0_out            );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                 buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__O21AI_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__MUX2_V
+`define SKY130_FD_SC_HVL__MUX2_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__mux2.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__mux2.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__mux2.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__mux2.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__MUX2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__AND3_BEHAVIORAL_V
+`define SKY130_FD_SC_HVL__AND3_BEHAVIORAL_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__and3 (
+    X,
+    A,
+    B,
+    C
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out_X, C, A, B        );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__AND3_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__A21O_SYMBOL_V
+`define SKY130_FD_SC_HVL__A21O_SYMBOL_V
+
+/**
+ * a21o: 2-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2) | B1)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__a21o (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  B1,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__A21O_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DIODE_PP_SYMBOL_V
+`define SKY130_FD_SC_HVL__DIODE_PP_SYMBOL_V
+
+/**
+ * diode: Antenna tie-down diode.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__diode (
+    //# {{power|Power}}
+    input DIODE,
+    input VPB  ,
+    input VPWR ,
+    input VGND ,
+    input VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DIODE_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_BEHAVIORAL_V
+`define SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_BEHAVIORAL_V
+
+/**
+ * lsbuflv2hv_clkiso_hlkg: Level-shift clock buffer, low voltage to
+ *                         high voltage, isolated well
+ *                         on input buffer, inverting sleep
+ *                         mode input.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg (
+    X      ,
+    A      ,
+    SLEEP_B
+);
+
+    // Module ports
+    output X      ;
+    input  A      ;
+    input  SLEEP_B;
+
+    // Module supplies
+    supply1 VPWR ;
+    supply0 VGND ;
+    supply1 LVPWR;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+    // Local signals
+    wire SLEEP     ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    not not0 (SLEEP     , SLEEP_B        );
+    and and0 (and0_out_X, SLEEP_B, A     );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__DECAP_BEHAVIORAL_V
+`define SKY130_FD_SC_HVL__DECAP_BEHAVIORAL_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__decap ();
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DECAP_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_P_SYMBOL_V
+`define SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_P_SYMBOL_V
+
+/**
+
+ *   UDP_OUT :=x when VPWR!=1
+ *   UDP_OUT :=UDP_IN when VPWR==1
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__udp_pwrgood_pp$P (
+    //# {{data|Data Signals}}
+    input  UDP_IN ,
+    output UDP_OUT,
+
+    //# {{power|Power}}
+    input  VPWR
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_P_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__INV_16_V
+`define SKY130_FD_SC_HVL__INV_16_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog wrapper for inv with size of 16 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__inv.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__inv_16 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hvl__inv base (
+        .Y(Y),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__inv_16 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hvl__inv base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__INV_16_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if ((!A2&!B1&B2)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((!A2&B1&!B2)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((!A2&B1&B2)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!B1&B2)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&B1&!B2)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&B1&B2)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&!B2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&!B2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2&!B2)) (B1 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&!B1)) (B2 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&!B1)) (B2 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2&!B1)) (B2 +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__XOR2_BEHAVIORAL_V
+`define SKY130_FD_SC_HVL__XOR2_BEHAVIORAL_V
+
+/**
+ * xor2: 2-input exclusive OR.
+ *
+ *       X = A ^ B
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__xor2 (
+    X,
+    A,
+    B
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire xor0_out_X;
+
+    //  Name  Output      Other arguments
+    xor xor0 (xor0_out_X, B, A           );
+    buf buf0 (X         , xor0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__XOR2_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SDLXTP_1_V
+`define SKY130_FD_SC_HVL__SDLXTP_1_V
+
+/**
+ * sdlxtp: ????.
+ *
+ * Verilog wrapper for sdlxtp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__sdlxtp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__sdlxtp_1 (
+    Q   ,
+    D   ,
+    SCD ,
+    SCE ,
+    GATE,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    input  D   ;
+    input  SCD ;
+    input  SCE ;
+    input  GATE;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hvl__sdlxtp base (
+        .Q(Q),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .GATE(GATE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__sdlxtp_1 (
+    Q   ,
+    D   ,
+    SCD ,
+    SCE ,
+    GATE
+);
+
+    output Q   ;
+    input  D   ;
+    input  SCD ;
+    input  SCE ;
+    input  GATE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hvl__sdlxtp base (
+        .Q(Q),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .GATE(GATE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDLXTP_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__EINVN_BEHAVIORAL_V
+`define SKY130_FD_SC_HVL__EINVN_BEHAVIORAL_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__einvn (
+    Z   ,
+    A   ,
+    TE_B
+);
+
+    // Module ports
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    //     Name     Output  Other arguments
+    notif0 notif00 (Z     , A, TE_B        );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__EINVN_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__MUX2_SYMBOL_V
+`define SKY130_FD_SC_HVL__MUX2_SYMBOL_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__mux2 (
+    //# {{data|Data Signals}}
+    input  A0,
+    input  A1,
+    output X ,
+
+    //# {{control|Control Signals}}
+    input  S
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__MUX2_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DLCLKP_PP_SYMBOL_V
+`define SKY130_FD_SC_HVL__DLCLKP_PP_SYMBOL_V
+
+/**
+ * dlclkp: Clock gate.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__dlclkp (
+    //# {{clocks|Clocking}}
+    input  CLK ,
+    input  GATE,
+    output GCLK,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DLCLKP_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_ISOLATCHHV_PP_PLG_S_SYMBOL_V
+`define SKY130_FD_SC_HVL__UDP_ISOLATCHHV_PP_PLG_S_SYMBOL_V
+
+/**
+ * udp_isolatchhv_pp$PLG$S: Power isolating latch (for HV). Includes
+ *                          VPWR, LVPWR, and VGND power pins with
+ *                          active high sleep pin (SLEEP).
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__udp_isolatchhv_pp$PLG$S (
+    //# {{data|Data Signals}}
+    input  UDP_IN ,
+    output UDP_OUT,
+
+    //# {{power|Power}}
+    input  SLEEP  ,
+    input  LVPWR  ,
+    input  VPWR   ,
+    input  VGND
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_ISOLATCHHV_PP_PLG_S_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__NAND3_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HVL__NAND3_BEHAVIORAL_PP_V
+
+/**
+ * nand3: 3-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__nand3 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                  Name         Output             Other arguments
+    nand                                nand0       (nand0_out_Y      , B, A, C                );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                 buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__NAND3_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__FILL_FUNCTIONAL_V
+`define SKY130_FD_SC_HVL__FILL_FUNCTIONAL_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__fill ();
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__FILL_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__EINVP_V
+`define SKY130_FD_SC_HVL__EINVP_V
+
+/**
+ * einvp: Tri-state inverter, positive enable.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__einvp.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__einvp.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__einvp.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__einvp.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__EINVP_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__NOR3_V
+`define SKY130_FD_SC_HVL__NOR3_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ *       Y = !(A | B | C | !D)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__nor3.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__nor3.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__nor3.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__nor3.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__NOR3_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_PP_SYMBOL_V
+`define SKY130_FD_SC_HVL__LSBUFLV2HV_PP_SYMBOL_V
+
+/**
+ * lsbuflv2hv: Level-shift buffer, low voltage-to-high voltage,
+ *             isolated well on input buffer, double height cell.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__lsbuflv2hv (
+    //# {{data|Data Signals}}
+    input  A    ,
+    output X    ,
+
+    //# {{power|Power}}
+    input  LVPWR,
+    input  VPB  ,
+    input  VPWR ,
+    input  VGND ,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFLV2HV_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DFSBP_PP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__DFSBP_PP_BLACKBOX_V
+
+/**
+ * dfsbp: Delay flop, inverted set, complementary outputs.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__dfsbp (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DFSBP_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__BUF_BLACKBOX_V
+`define SKY130_FD_SC_HVL__BUF_BLACKBOX_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__buf (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__BUF_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__AND3_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HVL__AND3_BEHAVIORAL_PP_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__and3 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                  Name         Output             Other arguments
+    and                                 and0        (and0_out_X       , C, A, B               );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                 buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__AND3_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(D +=> Q ) = (0:0:0,0:0:0);                     // delays are tris,tfall
+(SCD +=> Q ) = (0:0:0,0:0:0);      // adding as per CDT 106221
+(SCE => Q ) = (0:0:0,0:0:0);       // adding as per CDT 106221
+(posedge GATE => (Q +: D ) ) = (0:0:0,0:0:0);  // delays are tris,tfall
+$width (posedge GATE , 0:0:0, 0, notifier);
+$setuphold ( negedge GATE , posedge D , 0:0:0, 0:0:0, notifier , , COND0 , GATE_delayed , D_delayed ) ;
+$setuphold ( negedge GATE , negedge D , 0:0:0, 0:0:0, notifier , , COND0 , GATE_delayed , D_delayed ) ;
+$setuphold ( negedge GATE , posedge SCD , 0:0:0, 0:0:0, notifier , , COND1 , GATE_delayed , SCD_delayed ) ;
+$setuphold ( negedge GATE , negedge SCD , 0:0:0, 0:0:0, notifier , , COND1 , GATE_delayed , SCD_delayed ) ;
+$setuphold ( negedge GATE , posedge SCE , 0:0:0, 0:0:0, notifier , , , GATE_delayed , SCE_delayed ) ;
+$setuphold ( negedge GATE , negedge SCE , 0:0:0, 0:0:0, notifier , , , GATE_delayed , SCE_delayed ) ;
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_V
+`define SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_V
+
+/**
+ * lsbufhv2lv_simple: Level shifting buffer, High Voltage to Low
+ *                    Voltage, simple (hv devices in inverters on lv
+ *                    power rail).
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__lsbufhv2lv_simple.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__lsbufhv2lv_simple.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__lsbufhv2lv_simple.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__lsbufhv2lv_simple.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall
+$width (posedge CLK , 0:0:0, 0, notifier);
+$width (negedge CLK , 0:0:0, 0, notifier);
+$setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ;
+$setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND1 , CLK_delayed , D_delayed ) ;
+$setuphold ( posedge CLK , posedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ;
+$setuphold ( posedge CLK , negedge SCD , 0:0:0, 0:0:0, notifier , , COND2 , CLK_delayed , SCD_delayed ) ;
+$setuphold ( posedge CLK , posedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ;
+$setuphold ( posedge CLK , negedge SCE , 0:0:0, 0:0:0, notifier , , COND3 , CLK_delayed , SCE_delayed ) ;
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__EINVN_PP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__EINVN_PP_BLACKBOX_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__einvn (
+    Z   ,
+    A   ,
+    TE_B,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__EINVN_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__MUX2_TB_V
+`define SKY130_FD_SC_HVL__MUX2_TB_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__mux2.v""
+
+module top();
+
+    // Inputs are registered
+    reg A0;
+    reg A1;
+    reg S;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A0   = 1\'bX;
+        A1   = 1\'bX;
+        S    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A0   = 1\'b0;
+        #40   A1   = 1\'b0;
+        #60   S    = 1\'b0;
+        #80   VGND = 1\'b0;
+        #100  VNB  = 1\'b0;
+        #120  VPB  = 1\'b0;
+        #140  VPWR = 1\'b0;
+        #160  A0   = 1\'b1;
+        #180  A1   = 1\'b1;
+        #200  S    = 1\'b1;
+        #220  VGND = 1\'b1;
+        #240  VNB  = 1\'b1;
+        #260  VPB  = 1\'b1;
+        #280  VPWR = 1\'b1;
+        #300  A0   = 1\'b0;
+        #320  A1   = 1\'b0;
+        #340  S    = 1\'b0;
+        #360  VGND = 1\'b0;
+        #380  VNB  = 1\'b0;
+        #400  VPB  = 1\'b0;
+        #420  VPWR = 1\'b0;
+        #440  VPWR = 1\'b1;
+        #460  VPB  = 1\'b1;
+        #480  VNB  = 1\'b1;
+        #500  VGND = 1\'b1;
+        #520  S    = 1\'b1;
+        #540  A1   = 1\'b1;
+        #560  A0   = 1\'b1;
+        #580  VPWR = 1\'bx;
+        #600  VPB  = 1\'bx;
+        #620  VNB  = 1\'bx;
+        #640  VGND = 1\'bx;
+        #660  S    = 1\'bx;
+        #680  A1   = 1\'bx;
+        #700  A0   = 1\'bx;
+    end
+
+    sky130_fd_sc_hvl__mux2 dut (.A0(A0), .A1(A1), .S(S), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__MUX2_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_PP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__LSBUFLV2HV_PP_BLACKBOX_V
+
+/**
+ * lsbuflv2hv: Level-shift buffer, low voltage-to-high voltage,
+ *             isolated well on input buffer, double height cell.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__lsbuflv2hv (
+    X    ,
+    A    ,
+    VPWR ,
+    VGND ,
+    LVPWR,
+    VPB  ,
+    VNB
+);
+
+    output X    ;
+    input  A    ;
+    input  VPWR ;
+    input  VGND ;
+    input  LVPWR;
+    input  VPB  ;
+    input  VNB  ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFLV2HV_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__NAND3_PP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__NAND3_PP_BLACKBOX_V
+
+/**
+ * nand3: 3-input NAND.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__nand3 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__NAND3_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DLRTP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__DLRTP_BLACKBOX_V
+
+/**
+ * dlrtp: Delay latch, inverted reset, non-inverted enable,
+ *        single output.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__dlrtp (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE
+);
+
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DLRTP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(negedge RESET_B => (Q +: RESET_B ) ) = 0:0:0;  // delay is tris
+(negedge RESET_B => (Q_N -: RESET_B ) ) = 0:0:0;  // delay is tris
+(posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall
+(posedge CLK => (Q_N : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall
+$width (posedge CLK &&& (RESET_B===1\'b1) , 0:0:0, 0, notifier);
+$width (negedge CLK &&& (RESET_B===1\'b1) , 0:0:0, 0, notifier);
+$width (negedge RESET_B , 0:0:0 , 0 , notifier ) ;
+$recrem ( posedge RESET_B , posedge CLK , 0:0:0, 0:0:0, notifier , , , RESETB_delayed , CLK_delayed ) ;
+$setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND0 , CLK_delayed , D_delayed ) ;
+$setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND0 , CLK_delayed , D_delayed ) ;
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if ((!B&!C)) (A +=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
+ifnone (A +=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
+if ((!A&!C)) (B +=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
+ifnone (B +=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
+if ((!A&!B)) (C +=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
+ifnone (C +=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DLXTP_TB_V
+`define SKY130_FD_SC_HVL__DLXTP_TB_V
+
+/**
+ * dlxtp: Delay latch, non-inverted enable, single output.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__dlxtp.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Q;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   D    = 1\'b0;
+        #40   VGND = 1\'b0;
+        #60   VNB  = 1\'b0;
+        #80   VPB  = 1\'b0;
+        #100  VPWR = 1\'b0;
+        #120  D    = 1\'b1;
+        #140  VGND = 1\'b1;
+        #160  VNB  = 1\'b1;
+        #180  VPB  = 1\'b1;
+        #200  VPWR = 1\'b1;
+        #220  D    = 1\'b0;
+        #240  VGND = 1\'b0;
+        #260  VNB  = 1\'b0;
+        #280  VPB  = 1\'b0;
+        #300  VPWR = 1\'b0;
+        #320  VPWR = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VNB  = 1\'b1;
+        #380  VGND = 1\'b1;
+        #400  D    = 1\'b1;
+        #420  VPWR = 1\'bx;
+        #440  VPB  = 1\'bx;
+        #460  VNB  = 1\'bx;
+        #480  VGND = 1\'bx;
+        #500  D    = 1\'bx;
+    end
+
+    // Create a clock
+    reg GATE;
+    initial
+    begin
+        GATE = 1\'b0;
+    end
+
+    always
+    begin
+        #5 GATE = ~GATE;
+    end
+
+    sky130_fd_sc_hvl__dlxtp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .GATE(GATE));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DLXTP_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_BEHAVIORAL_V
+`define SKY130_FD_SC_HVL__LSBUFHV2LV_BEHAVIORAL_V
+
+/**
+ * lsbufhv2lv: Level-shift buffer, low voltage-to-low voltage.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__lsbufhv2lv (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR ;
+    supply0 VGND ;
+    supply1 LVPWR;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+    //  Name  Output  Other arguments
+    buf buf0 (X     , A              );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFHV2LV_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__XOR2_FUNCTIONAL_V
+`define SKY130_FD_SC_HVL__XOR2_FUNCTIONAL_V
+
+/**
+ * xor2: 2-input exclusive OR.
+ *
+ *       X = A ^ B
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__xor2 (
+    X,
+    A,
+    B
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+
+    // Local signals
+    wire xor0_out_X;
+
+    //  Name  Output      Other arguments
+    xor xor0 (xor0_out_X, B, A           );
+    buf buf0 (X         , xor0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__XOR2_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__O21A_FUNCTIONAL_V
+`define SKY130_FD_SC_HVL__O21A_FUNCTIONAL_V
+
+/**
+ * o21a: 2-input OR into first input of 2-input AND.
+ *
+ *       X = ((A1 | A2) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__o21a (
+    X ,
+    A1,
+    A2,
+    B1
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Local signals
+    wire or0_out   ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    or  or0  (or0_out   , A2, A1         );
+    and and0 (and0_out_X, or0_out, B1    );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__O21A_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__MUX4_TB_V
+`define SKY130_FD_SC_HVL__MUX4_TB_V
+
+/**
+ * mux4: 4-input multiplexer.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__mux4.v""
+
+module top();
+
+    // Inputs are registered
+    reg A0;
+    reg A1;
+    reg A2;
+    reg A3;
+    reg S0;
+    reg S1;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A0   = 1\'bX;
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        A3   = 1\'bX;
+        S0   = 1\'bX;
+        S1   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A0   = 1\'b0;
+        #40   A1   = 1\'b0;
+        #60   A2   = 1\'b0;
+        #80   A3   = 1\'b0;
+        #100  S0   = 1\'b0;
+        #120  S1   = 1\'b0;
+        #140  VGND = 1\'b0;
+        #160  VNB  = 1\'b0;
+        #180  VPB  = 1\'b0;
+        #200  VPWR = 1\'b0;
+        #220  A0   = 1\'b1;
+        #240  A1   = 1\'b1;
+        #260  A2   = 1\'b1;
+        #280  A3   = 1\'b1;
+        #300  S0   = 1\'b1;
+        #320  S1   = 1\'b1;
+        #340  VGND = 1\'b1;
+        #360  VNB  = 1\'b1;
+        #380  VPB  = 1\'b1;
+        #400  VPWR = 1\'b1;
+        #420  A0   = 1\'b0;
+        #440  A1   = 1\'b0;
+        #460  A2   = 1\'b0;
+        #480  A3   = 1\'b0;
+        #500  S0   = 1\'b0;
+        #520  S1   = 1\'b0;
+        #540  VGND = 1\'b0;
+        #560  VNB  = 1\'b0;
+        #580  VPB  = 1\'b0;
+        #600  VPWR = 1\'b0;
+        #620  VPWR = 1\'b1;
+        #640  VPB  = 1\'b1;
+        #660  VNB  = 1\'b1;
+        #680  VGND = 1\'b1;
+        #700  S1   = 1\'b1;
+        #720  S0   = 1\'b1;
+        #740  A3   = 1\'b1;
+        #760  A2   = 1\'b1;
+        #780  A1   = 1\'b1;
+        #800  A0   = 1\'b1;
+        #820  VPWR = 1\'bx;
+        #840  VPB  = 1\'bx;
+        #860  VNB  = 1\'bx;
+        #880  VGND = 1\'bx;
+        #900  S1   = 1\'bx;
+        #920  S0   = 1\'bx;
+        #940  A3   = 1\'bx;
+        #960  A2   = 1\'bx;
+        #980  A1   = 1\'bx;
+        #1000 A0   = 1\'bx;
+    end
+
+    sky130_fd_sc_hvl__mux4 dut (.A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S0), .S1(S1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__MUX4_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_1_V
+`define SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_1_V
+
+/**
+ * lsbuflv2hv_symmetric: Level shifting buffer, Low Voltage to High
+ *                       Voltage, Symmetrical.
+ *
+ * Verilog wrapper for lsbuflv2hv_symmetric with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__lsbuflv2hv_symmetric.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1 (
+    X    ,
+    A    ,
+    VPWR ,
+    VGND ,
+    LVPWR,
+    VPB  ,
+    VNB
+);
+
+    output X    ;
+    input  A    ;
+    input  VPWR ;
+    input  VGND ;
+    input  LVPWR;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hvl__lsbuflv2hv_symmetric base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .LVPWR(LVPWR),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR ;
+    supply0 VGND ;
+    supply1 LVPWR;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+    sky130_fd_sc_hvl__lsbuflv2hv_symmetric base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__MUX2_FUNCTIONAL_V
+`define SKY130_FD_SC_HVL__MUX2_FUNCTIONAL_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v""
+
+`celldefine
+module sky130_fd_sc_hvl__mux2 (
+    X ,
+    A0,
+    A1,
+    S
+);
+
+    // Module ports
+    output X ;
+    input  A0;
+    input  A1;
+    input  S ;
+
+    // Local signals
+    wire mux_2to10_out_X;
+
+    //                             Name       Output           Other arguments
+    sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_2to10_out_X, A0, A1, S      );
+    buf                            buf0      (X              , mux_2to10_out_X);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__MUX2_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__DFRTP_BEHAVIORAL_V
+`define SKY130_FD_SC_HVL__DFRTP_BEHAVIORAL_V
+
+/**
+ * dfrtp: Delay flop, inverted reset, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hvl__udp_dff_pr_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_hvl__dfrtp (
+    Q      ,
+    CLK    ,
+    D      ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q          ;
+    wire RESET          ;
+    reg  notifier       ;
+    wire cond0          ;
+    wire D_delayed      ;
+    wire RESET_B_delayed;
+    wire CLK_delayed    ;
+
+    //                                   Name  Output  Other arguments
+    not                                  not0 (RESET , RESET_B_delayed                                    );
+    sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
+    assign cond0 = ( RESET_B_delayed === 1\'b1 );
+    buf                                  buf0 (Q     , buf_Q                                              );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DFRTP_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__CONB_BEHAVIORAL_V
+`define SKY130_FD_SC_HVL__CONB_BEHAVIORAL_V
+
+/**
+ * conb: Constant value, low, high outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__conb (
+    HI,
+    LO
+);
+
+    // Module ports
+    output HI;
+    output LO;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    //       Name       Output
+    pullup   pullup0   (HI    );
+    pulldown pulldown0 (LO    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__CONB_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SDFSBP_SYMBOL_V
+`define SKY130_FD_SC_HVL__SDFSBP_SYMBOL_V
+
+/**
+ * sdfsbp: Scan delay flop, inverted set, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__sdfsbp (
+    //# {{data|Data Signals}}
+    input  D    ,
+    output Q    ,
+    output Q_N  ,
+
+    //# {{control|Control Signals}}
+    input  SET_B,
+
+    //# {{scanchain|Scan Chain}}
+    input  SCD  ,
+    input  SCE  ,
+
+    //# {{clocks|Clocking}}
+    input  CLK
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFSBP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DFSTP_1_V
+`define SKY130_FD_SC_HVL__DFSTP_1_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Verilog wrapper for dfstp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__dfstp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__dfstp_1 (
+    Q    ,
+    CLK  ,
+    D    ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hvl__dfstp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SET_B(SET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__dfstp_1 (
+    Q    ,
+    CLK  ,
+    D    ,
+    SET_B
+);
+
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hvl__dfstp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SET_B(SET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DFSTP_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DFSTP_TB_V
+`define SKY130_FD_SC_HVL__DFSTP_TB_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__dfstp.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg SET_B;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Q;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D     = 1\'bX;
+        SET_B = 1\'bX;
+        VGND  = 1\'bX;
+        VNB   = 1\'bX;
+        VPB   = 1\'bX;
+        VPWR  = 1\'bX;
+
+        #20   D     = 1\'b0;
+        #40   SET_B = 1\'b0;
+        #60   VGND  = 1\'b0;
+        #80   VNB   = 1\'b0;
+        #100  VPB   = 1\'b0;
+        #120  VPWR  = 1\'b0;
+        #140  D     = 1\'b1;
+        #160  SET_B = 1\'b1;
+        #180  VGND  = 1\'b1;
+        #200  VNB   = 1\'b1;
+        #220  VPB   = 1\'b1;
+        #240  VPWR  = 1\'b1;
+        #260  D     = 1\'b0;
+        #280  SET_B = 1\'b0;
+        #300  VGND  = 1\'b0;
+        #320  VNB   = 1\'b0;
+        #340  VPB   = 1\'b0;
+        #360  VPWR  = 1\'b0;
+        #380  VPWR  = 1\'b1;
+        #400  VPB   = 1\'b1;
+        #420  VNB   = 1\'b1;
+        #440  VGND  = 1\'b1;
+        #460  SET_B = 1\'b1;
+        #480  D     = 1\'b1;
+        #500  VPWR  = 1\'bx;
+        #520  VPB   = 1\'bx;
+        #540  VNB   = 1\'bx;
+        #560  VGND  = 1\'bx;
+        #580  SET_B = 1\'bx;
+        #600  D     = 1\'bx;
+    end
+
+    // Create a clock
+    reg CLK;
+    initial
+    begin
+        CLK = 1\'b0;
+    end
+
+    always
+    begin
+        #5 CLK = ~CLK;
+    end
+
+    sky130_fd_sc_hvl__dfstp dut (.D(D), .SET_B(SET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DFSTP_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__A21OI_BLACKBOX_V
+`define SKY130_FD_SC_HVL__A21OI_BLACKBOX_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | B1)
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__a21oi (
+    Y ,
+    A1,
+    A2,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__A21OI_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__INV_TB_V
+`define SKY130_FD_SC_HVL__INV_TB_V
+
+/**
+ * inv: Inverter.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__inv.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   VGND = 1\'b0;
+        #60   VNB  = 1\'b0;
+        #80   VPB  = 1\'b0;
+        #100  VPWR = 1\'b0;
+        #120  A    = 1\'b1;
+        #140  VGND = 1\'b1;
+        #160  VNB  = 1\'b1;
+        #180  VPB  = 1\'b1;
+        #200  VPWR = 1\'b1;
+        #220  A    = 1\'b0;
+        #240  VGND = 1\'b0;
+        #260  VNB  = 1\'b0;
+        #280  VPB  = 1\'b0;
+        #300  VPWR = 1\'b0;
+        #320  VPWR = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VNB  = 1\'b1;
+        #380  VGND = 1\'b1;
+        #400  A    = 1\'b1;
+        #420  VPWR = 1\'bx;
+        #440  VPB  = 1\'bx;
+        #460  VNB  = 1\'bx;
+        #480  VGND = 1\'bx;
+        #500  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_hvl__inv dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__INV_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if ((!A1&!A2&!A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0);
+if ((!A1&!A2&A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&!A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0);
+if ((!A1&A2&A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&!A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0);
+if ((A1&!A2&A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2&!A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0);
+if ((A1&A2&A3&!S0&!S1)) (A0 +=> X) = (0:0:0,0:0:0);
+if ((!A0&!A2&!A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((!A0&!A2&A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((!A0&A2&!A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((!A0&A2&A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((A0&!A2&!A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((A0&!A2&A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((A0&A2&!A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((A0&A2&A3&S0&!S1)) (A1 +=> X) = (0:0:0,0:0:0);
+if ((!A0&!A1&!A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((!A0&!A1&A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((!A0&A1&!A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((!A0&A1&A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((A0&!A1&!A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((A0&!A1&A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((A0&A1&!A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((A0&A1&A3&!S0&S1)) (A2 +=> X) = (0:0:0,0:0:0);
+if ((!A0&!A1&!A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0);
+if ((!A0&!A1&A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0);
+if ((!A0&A1&!A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0);
+if ((!A0&A1&A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0);
+if ((A0&!A1&!A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0);
+if ((A0&!A1&A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0);
+if ((A0&A1&!A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0);
+if ((A0&A1&A2&S0&S1)) (A3 +=> X) = (0:0:0,0:0:0);
+if ((!A0&!A1&!A2&A3&S1)) (S0 +=> X) = (0:0:0,0:0:0);
+if ((!A0&!A1&A2&!A3&S1)) (S0 -=> X) = (0:0:0,0:0:0);
+if ((!A0&A1&!A2&!A3&!S1)) (S0 +=> X) = (0:0:0,0:0:0);
+if ((!A0&A1&!A2&A3&!S1)) (S0 +=> X) = (0:0:0,0:0:0);
+if ((!A0&A1&!A2&A3&S1)) (S0 +=> X) = (0:0:0,0:0:0);
+if ((!A0&A1&A2&!A3&!S1)) (S0 +=> X) = (0:0:0,0:0:0);
+if ((!A0&A1&A2&!A3&S1)) (S0 -=> X) = (0:0:0,0:0:0);
+if ((!A0&A1&A2&A3&!S1)) (S0 +=> X) = (0:0:0,0:0:0);
+if ((A0&!A1&!A2&!A3&!S1)) (S0 -=> X) = (0:0:0,0:0:0);
+if ((A0&!A1&!A2&A3&!S1)) (S0 -=> X) = (0:0:0,0:0:0);
+if ((A0&!A1&!A2&A3&S1)) (S0 +=> X) = (0:0:0,0:0:0);
+if ((A0&!A1&A2&!A3&!S1)) (S0 -=> X) = (0:0:0,0:0:0);
+if ((A0&!A1&A2&!A3&S1)) (S0 -=> X) = (0:0:0,0:0:0);
+if ((A0&!A1&A2&A3&!S1)) (S0 -=> X) = (0:0:0,0:0:0);
+if ((A0&A1&!A2&A3&S1)) (S0 +=> X) = (0:0:0,0:0:0);
+if ((A0&A1&A2&!A3&S1)) (S0 -=> X) = (0:0:0,0:0:0);
+if ((!A0&!A1&!A2&A3&S0)) (S1 +=> X) = (0:0:0,0:0:0);
+if ((!A0&!A1&A2&!A3&!S0)) (S1 +=> X) = (0:0:0,0:0:0);
+if ((!A0&!A1&A2&A3&!S0)) (S1 +=> X) = (0:0:0,0:0:0);
+if ((!A0&!A1&A2&A3&S0)) (S1 +=> X) = (0:0:0,0:0:0);
+if ((!A0&A1&!A2&!A3&S0)) (S1 -=> X) = (0:0:0,0:0:0);
+if ((!A0&A1&A2&!A3&!S0)) (S1 +=> X) = (0:0:0,0:0:0);
+if ((!A0&A1&A2&!A3&S0)) (S1 -=> X) = (0:0:0,0:0:0);
+if ((!A0&A1&A2&A3&!S0)) (S1 +=> X) = (0:0:0,0:0:0);
+if ((A0&!A1&!A2&!A3&!S0)) (S1 -=> X) = (0:0:0,0:0:0);
+if ((A0&!A1&!A2&A3&!S0)) (S1 -=> X) = (0:0:0,0:0:0);
+if ((A0&!A1&!A2&A3&S0)) (S1 +=> X) = (0:0:0,0:0:0);
+if ((A0&!A1&A2&A3&S0)) (S1 +=> X) = (0:0:0,0:0:0);
+if ((A0&A1&!A2&!A3&!S0)) (S1 -=> X) = (0:0:0,0:0:0);
+if ((A0&A1&!A2&!A3&S0)) (S1 -=> X) = (0:0:0,0:0:0);
+if ((A0&A1&!A2&A3&!S0)) (S1 -=> X) = (0:0:0,0:0:0);
+if ((A0&A1&A2&!A3&S0)) (S1 -=> X) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__A22O_SYMBOL_V
+`define SKY130_FD_SC_HVL__A22O_SYMBOL_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ *       X = ((A1 & A2) | (B1 & B2))
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__a22o (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  B1,
+    input  B2,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__A22O_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__MUX4_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HVL__MUX4_FUNCTIONAL_PP_V
+
+/**
+ * mux4: 4-input multiplexer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+`include ""../../models/udp_mux_4to2/sky130_fd_sc_hvl__udp_mux_4to2.v""
+
+`celldefine
+module sky130_fd_sc_hvl__mux4 (
+    X   ,
+    A0  ,
+    A1  ,
+    A2  ,
+    A3  ,
+    S0  ,
+    S1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A0  ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  S0  ;
+    input  S1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire mux_4to20_out_X  ;
+    wire pwrgood_pp0_out_X;
+
+    //                                  Name         Output             Other arguments
+    sky130_fd_sc_hvl__udp_mux_4to2      mux_4to20   (mux_4to20_out_X  , A0, A1, A2, A3, S0, S1     );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_4to20_out_X, VPWR, VGND);
+    buf                                 buf0        (X                , pwrgood_pp0_out_X          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__MUX4_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__FILL_1_V
+`define SKY130_FD_SC_HVL__FILL_1_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog wrapper for fill with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__fill.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__fill_1 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+    sky130_fd_sc_hvl__fill base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__fill_1 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hvl__fill base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__FILL_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__O22AI_BEHAVIORAL_V
+`define SKY130_FD_SC_HVL__O22AI_BEHAVIORAL_V
+
+/**
+ * o22ai: 2-input OR into both inputs of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__o22ai (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nor0_out ;
+    wire nor1_out ;
+    wire or0_out_Y;
+
+    //  Name  Output     Other arguments
+    nor nor0 (nor0_out , B1, B2            );
+    nor nor1 (nor1_out , A1, A2            );
+    or  or0  (or0_out_Y, nor1_out, nor0_out);
+    buf buf0 (Y        , or0_out_Y         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__O22AI_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_BLACKBOX_V
+`define SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_BLACKBOX_V
+
+/**
+ * lsbuflv2hv_symmetric: Level shifting buffer, Low Voltage to High
+ *                       Voltage, Symmetrical.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__lsbuflv2hv_symmetric (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR ;
+    supply0 VGND ;
+    supply1 LVPWR;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__XOR2_PP_SYMBOL_V
+`define SKY130_FD_SC_HVL__XOR2_PP_SYMBOL_V
+
+/**
+ * xor2: 2-input exclusive OR.
+ *
+ *       X = A ^ B
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__xor2 (
+    //# {{data|Data Signals}}
+    input  A   ,
+    input  B   ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__XOR2_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SDFSBP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__SDFSBP_BLACKBOX_V
+
+/**
+ * sdfsbp: Scan delay flop, inverted set, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__sdfsbp (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B
+);
+
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFSBP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__SCHMITTBUF_BEHAVIORAL_V
+`define SKY130_FD_SC_HVL__SCHMITTBUF_BEHAVIORAL_V
+
+/**
+ * schmittbuf: Schmitt Trigger Buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__schmittbuf (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SCHMITTBUF_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__A22O_PP_SYMBOL_V
+`define SKY130_FD_SC_HVL__A22O_PP_SYMBOL_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ *       X = ((A1 & A2) | (B1 & B2))
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__a22o (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  B1  ,
+    input  B2  ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__A22O_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SDFRBP_V
+`define SKY130_FD_SC_HVL__SDFRBP_V
+
+/**
+ * sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__sdfrbp.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__sdfrbp.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__sdfrbp.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__sdfrbp.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFRBP_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DFSTP_V
+`define SKY130_FD_SC_HVL__DFSTP_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__dfstp.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__dfstp.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__dfstp.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__dfstp.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DFSTP_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__CONB_V
+`define SKY130_FD_SC_HVL__CONB_V
+
+/**
+ * conb: Constant value, low, high outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__conb.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__conb.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__conb.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__conb.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__CONB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HVL__LSBUFHV2LV_BEHAVIORAL_PP_V
+
+/**
+ * lsbufhv2lv: Level-shift buffer, low voltage-to-low voltage.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__lsbufhv2lv (
+    X    ,
+    A    ,
+    VPWR ,
+    VGND ,
+    LVPWR,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output X    ;
+    input  A    ;
+    input  VPWR ;
+    input  VGND ;
+    input  LVPWR;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire pwrgood_pp0_out_A;
+    wire buf0_out_X       ;
+
+    //                                  Name         Output             Other arguments
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A, A, VPWR, VGND          );
+    buf                                 buf0        (buf0_out_X       , pwrgood_pp0_out_A      );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (X                , buf0_out_X, LVPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFHV2LV_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_DLATCH_P_V
+`define SKY130_FD_SC_HVL__UDP_DLATCH_P_V
+
+/**
+ * udp_dlatch$P: D-latch, gated standard drive / active high
+ *               (Q output UDP)
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`include ""./sky130_fd_sc_hvl__udp_dlatch_p.blackbox.v""
+`else
+primitive sky130_fd_sc_hvl__udp_dlatch$P (
+    Q   ,
+    D   ,
+    GATE
+);
+
+    output Q   ;
+    input  D   ;
+    input  GATE;
+
+    reg Q;
+
+    table
+     //  D  GATE :  Qt : Qt+1
+         ?   0   :  ?  :  -    ; // hold
+         0   1   :  ?  :  0    ; // pass 0
+         1   1   :  ?  :  1    ; // pass 1
+         0   x   :  0  :  0    ; // reduce pessimism
+         1   x   :  1  :  1    ; // reduce pessimism
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_DLATCH_P_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__SDFXBP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HVL__SDFXBP_BEHAVIORAL_PP_V
+
+/**
+ * sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hvl__udp_dff_p_pp_pg_n.v""
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v""
+
+`celldefine
+module sky130_fd_sc_hvl__sdfxbp (
+    Q   ,
+    Q_N ,
+    CLK ,
+    D   ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    output Q_N ;
+    input  CLK ;
+    input  D   ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q      ;
+    wire mux_out    ;
+    reg  notifier   ;
+    wire cond1      ;
+    wire cond2      ;
+    wire cond3      ;
+    wire D_delayed  ;
+    wire SCD_delayed;
+    wire SCE_delayed;
+    wire CLK_delayed;
+    wire buf0_out_Q ;
+    wire not0_out_qn;
+
+    //                                  Name         Output       Other arguments
+    sky130_fd_sc_hvl__udp_mux_2to1      mux_2to10   (mux_out    , D_delayed, SCD_delayed, SCE_delayed       );
+    sky130_fd_sc_hvl__udp_dff$P_pp$PG$N dff0        (buf_Q      , mux_out, CLK_delayed, notifier, VPWR, VGND);
+    assign cond1 = ( SCE_delayed === 1\'b0 );
+    assign cond2 = ( SCE_delayed === 1\'b1 );
+    assign cond3 = ( D_delayed !== SCD_delayed );
+    buf                                 buf0        (buf0_out_Q , buf_Q                                     );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q          , buf0_out_Q, VPWR, VGND                    );
+    not                                 not0        (not0_out_qn, buf_Q                                     );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (Q_N        , not0_out_qn, VPWR, VGND                   );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFXBP_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__INV_V
+`define SKY130_FD_SC_HVL__INV_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__inv.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__inv.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__inv.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__inv.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__INV_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DIODE_BLACKBOX_V
+`define SKY130_FD_SC_HVL__DIODE_BLACKBOX_V
+
+/**
+ * diode: Antenna tie-down diode.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__diode (
+    DIODE
+);
+
+    input DIODE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DIODE_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__FILL_2_V
+`define SKY130_FD_SC_HVL__FILL_2_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog wrapper for fill with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__fill.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__fill_2 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+    sky130_fd_sc_hvl__fill base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__fill_2 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hvl__fill base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__FILL_2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__XOR2_PP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__XOR2_PP_BLACKBOX_V
+
+/**
+ * xor2: 2-input exclusive OR.
+ *
+ *       X = A ^ B
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__xor2 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__XOR2_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__FILL_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HVL__FILL_FUNCTIONAL_PP_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__fill (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__FILL_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__EINVP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__EINVP_BLACKBOX_V
+
+/**
+ * einvp: Tri-state inverter, positive enable.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__einvp (
+    Z ,
+    A ,
+    TE
+);
+
+    output Z ;
+    input  A ;
+    input  TE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__EINVP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_SYMBOL_V
+`define SKY130_FD_SC_HVL__LSBUFLV2HV_SYMBOL_V
+
+/**
+ * lsbuflv2hv: Level-shift buffer, low voltage-to-high voltage,
+ *             isolated well on input buffer, double height cell.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__lsbuflv2hv (
+    //# {{data|Data Signals}}
+    input  A,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR ;
+    supply0 VGND ;
+    supply1 LVPWR;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFLV2HV_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_PG_TB_V
+`define SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_PG_TB_V
+
+/**
+
+ *   UDP_OUT :=x when VPWR!=1 or VGND!=0
+ *   UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+module top();
+
+    // Inputs are registered
+    reg UDP_IN;
+    reg VPWR;
+    reg VGND;
+
+    // Outputs are wires
+    wire UDP_OUT;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        UDP_IN = 1\'bX;
+        VGND   = 1\'bX;
+        VPWR   = 1\'bX;
+
+        #20   UDP_IN = 1\'b0;
+        #40   VGND   = 1\'b0;
+        #60   VPWR   = 1\'b0;
+        #80   UDP_IN = 1\'b1;
+        #100  VGND   = 1\'b1;
+        #120  VPWR   = 1\'b1;
+        #140  UDP_IN = 1\'b0;
+        #160  VGND   = 1\'b0;
+        #180  VPWR   = 1\'b0;
+        #200  VPWR   = 1\'b1;
+        #220  VGND   = 1\'b1;
+        #240  UDP_IN = 1\'b1;
+        #260  VPWR   = 1\'bx;
+        #280  VGND   = 1\'bx;
+        #300  UDP_IN = 1\'bx;
+    end
+
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG dut (.UDP_IN(UDP_IN), .VPWR(VPWR), .VGND(VGND), .UDP_OUT(UDP_OUT));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_PG_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_BLACKBOX_V
+`define SKY130_FD_SC_HVL__LSBUFHV2LV_BLACKBOX_V
+
+/**
+ * lsbufhv2lv: Level-shift buffer, low voltage-to-low voltage.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__lsbufhv2lv (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR ;
+    supply0 VGND ;
+    supply1 LVPWR;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFHV2LV_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__DLCLKP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HVL__DLCLKP_BEHAVIORAL_PP_V
+
+/**
+ * dlclkp: Clock gate.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+`include ""../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hvl__udp_dlatch_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_hvl__dlclkp (
+    GCLK,
+    GATE,
+    CLK ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output GCLK;
+    input  GATE;
+    input  CLK ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire m0          ;
+    wire clkn        ;
+    wire CLK_delayed ;
+    wire GATE_delayed;
+    reg  notifier    ;
+    wire GCLK_b      ;
+    wire awake       ;
+
+    //                                     Name         Output  Other arguments
+    not                                    not0        (clkn  , CLK_delayed                             );
+    sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0     (m0    , GATE_delayed, clkn, notifier, VPWR, VGND);
+    and                                    and0        (GCLK_b, m0, CLK_delayed                         );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG    pwrgood_pp0 (GCLK  , GCLK_b, VPWR, VGND                      );
+    assign awake = ( VPWR === 1\'b1 );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DLCLKP_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SDFXTP_V
+`define SKY130_FD_SC_HVL__SDFXTP_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__sdfxtp.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__sdfxtp.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__sdfxtp.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__sdfxtp.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFXTP_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__XNOR2_SYMBOL_V
+`define SKY130_FD_SC_HVL__XNOR2_SYMBOL_V
+
+/**
+ * xnor2: 2-input exclusive NOR.
+ *
+ *        Y = !(A ^ B)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__xnor2 (
+    //# {{data|Data Signals}}
+    input  A,
+    input  B,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__XNOR2_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__SDFRTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HVL__SDFRTP_BEHAVIORAL_PP_V
+
+/**
+ * sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
+ *         single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hvl__udp_dff_pr_pp_pg_n.v""
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v""
+
+`celldefine
+module sky130_fd_sc_hvl__sdfrtp (
+    Q      ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire buf_Q          ;
+    wire RESET          ;
+    wire mux_out        ;
+    reg  notifier       ;
+    wire cond0          ;
+    wire cond1          ;
+    wire cond2          ;
+    wire cond3          ;
+    wire D_delayed      ;
+    wire SCD_delayed    ;
+    wire SCE_delayed    ;
+    wire RESET_B_delayed;
+    wire CLK_delayed    ;
+    wire buf0_out_Q     ;
+
+    //                                   Name         Output      Other arguments
+    not                                  not0        (RESET     , RESET_B_delayed                                  );
+    sky130_fd_sc_hvl__udp_mux_2to1       mux_2to10   (mux_out   , D_delayed, SCD_delayed, SCE_delayed              );
+    sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0        (buf_Q     , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
+    assign cond0 = ( RESET_B_delayed === 1\'b1 );
+    assign cond1 = ( ( SCE_delayed === 1\'b0 ) & cond0 );
+    assign cond2 = ( ( SCE_delayed === 1\'b1 ) & cond0 );
+    assign cond3 = ( ( D_delayed !== SCD_delayed ) & cond0 );
+    buf                                  buf0        (buf0_out_Q, buf_Q                                            );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG  pwrgood_pp0 (Q         , buf0_out_Q, VPWR, VGND                           );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFRTP_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SCHMITTBUF_PP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__SCHMITTBUF_PP_BLACKBOX_V
+
+/**
+ * schmittbuf: Schmitt Trigger Buffer.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__schmittbuf (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SCHMITTBUF_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SCHMITTBUF_SYMBOL_V
+`define SKY130_FD_SC_HVL__SCHMITTBUF_SYMBOL_V
+
+/**
+ * schmittbuf: Schmitt Trigger Buffer.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__schmittbuf (
+    //# {{data|Data Signals}}
+    input  A,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SCHMITTBUF_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_DLATCH_PR_TB_V
+`define SKY130_FD_SC_HVL__UDP_DLATCH_PR_TB_V
+
+/**
+ * udp_dlatch$PR: D-latch, gated clear direct / gate active high
+ *                (Q output UDP)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__udp_dlatch_pr.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg RESET;
+
+    // Outputs are wires
+    wire Q;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D     = 1\'bX;
+        RESET = 1\'bX;
+
+        #20   D     = 1\'b0;
+        #40   RESET = 1\'b0;
+        #60   D     = 1\'b1;
+        #80   RESET = 1\'b1;
+        #100  D     = 1\'b0;
+        #120  RESET = 1\'b0;
+        #140  RESET = 1\'b1;
+        #160  D     = 1\'b1;
+        #180  RESET = 1\'bx;
+        #200  D     = 1\'bx;
+    end
+
+    // Create a clock
+    reg GATE;
+    initial
+    begin
+        GATE = 1\'b0;
+    end
+
+    always
+    begin
+        #5 GATE = ~GATE;
+    end
+
+    sky130_fd_sc_hvl__udp_dlatch$PR dut (.D(D), .RESET(RESET), .Q(Q), .GATE(GATE));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_DLATCH_PR_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_PP_SYMBOL_V
+`define SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_PP_SYMBOL_V
+
+/**
+ * lsbuflv2hv_isosrchvaon: Level shift buffer, low voltage to high
+ *                         voltage, isolated well on input buffer,
+ *                         inverting sleep mode input, zero power
+ *                         sleep mode.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon (
+    //# {{data|Data Signals}}
+    input  A      ,
+    output X      ,
+
+    //# {{power|Power}}
+    input  SLEEP_B,
+    input  LVPWR  ,
+    input  VPB    ,
+    input  VPWR   ,
+    input  VGND   ,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__A22OI_PP_SYMBOL_V
+`define SKY130_FD_SC_HVL__A22OI_PP_SYMBOL_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__a22oi (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  B1  ,
+    input  B2  ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__A22OI_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__EINVP_PP_SYMBOL_V
+`define SKY130_FD_SC_HVL__EINVP_PP_SYMBOL_V
+
+/**
+ * einvp: Tri-state inverter, positive enable.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__einvp (
+    //# {{data|Data Signals}}
+    input  A   ,
+    output Z   ,
+
+    //# {{control|Control Signals}}
+    input  TE  ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__EINVP_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__SDFSBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HVL__SDFSBP_FUNCTIONAL_PP_V
+
+/**
+ * sdfsbp: Scan delay flop, inverted set, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v""
+`include ""../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hvl__udp_dff_ps_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_hvl__sdfsbp (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire buf_Q      ;
+    wire SET        ;
+    wire mux_out    ;
+    wire buf0_out_Q ;
+    wire not1_out_qn;
+
+    //                                   Delay       Name         Output       Other arguments
+    not                                              not0        (SET        , SET_B                          );
+    sky130_fd_sc_hvl__udp_mux_2to1                   mux_2to10   (mux_out    , D, SCD, SCE                    );
+    sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0        (buf_Q      , mux_out, CLK, SET, , VPWR, VGND);
+    buf                                              buf0        (buf0_out_Q , buf_Q                          );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG              pwrgood_pp0 (Q          , buf0_out_Q, VPWR, VGND         );
+    not                                              not1        (not1_out_qn, buf_Q                          );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG              pwrgood_pp1 (Q_N        , not1_out_qn, VPWR, VGND        );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFSBP_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__OR2_SYMBOL_V
+`define SKY130_FD_SC_HVL__OR2_SYMBOL_V
+
+/**
+ * or2: 2-input OR.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__or2 (
+    //# {{data|Data Signals}}
+    input  A,
+    input  B,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__OR2_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SDFXBP_PP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__SDFXBP_PP_BLACKBOX_V
+
+/**
+ * sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__sdfxbp (
+    Q   ,
+    Q_N ,
+    CLK ,
+    D   ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    output Q_N ;
+    input  CLK ;
+    input  D   ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFXBP_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__MUX4_FUNCTIONAL_V
+`define SKY130_FD_SC_HVL__MUX4_FUNCTIONAL_V
+
+/**
+ * mux4: 4-input multiplexer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_4to2/sky130_fd_sc_hvl__udp_mux_4to2.v""
+
+`celldefine
+module sky130_fd_sc_hvl__mux4 (
+    X ,
+    A0,
+    A1,
+    A2,
+    A3,
+    S0,
+    S1
+);
+
+    // Module ports
+    output X ;
+    input  A0;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  S0;
+    input  S1;
+
+    // Local signals
+    wire mux_4to20_out_X;
+
+    //                             Name       Output           Other arguments
+    sky130_fd_sc_hvl__udp_mux_4to2 mux_4to20 (mux_4to20_out_X, A0, A1, A2, A3, S0, S1);
+    buf                            buf0      (X              , mux_4to20_out_X       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__MUX4_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__NAND2_PP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__NAND2_PP_BLACKBOX_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__nand2 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__NAND2_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
+`define SKY130_FD_SC_HVL__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
+
+/**
+ * udp_dff$PR_pp$PG$N: Positive edge triggered D flip-flop with active
+ *                     high
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N (
+    Q       ,
+    D       ,
+    CLK     ,
+    RESET   ,
+    NOTIFIER,
+    VPWR    ,
+    VGND
+);
+
+    output Q       ;
+    input  D       ;
+    input  CLK     ;
+    input  RESET   ;
+    input  NOTIFIER;
+    input  VPWR    ;
+    input  VGND    ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_DFF_P_PP_PG_N_SYMBOL_V
+`define SKY130_FD_SC_HVL__UDP_DFF_P_PP_PG_N_SYMBOL_V
+
+/**
+ * udp_dff$P_pp$PG$N: Positive edge triggered D flip-flop
+ *                    (Q output UDP).
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__udp_dff$P_pp$PG$N (
+    //# {{data|Data Signals}}
+    input  D       ,
+    output Q       ,
+
+    //# {{clocks|Clocking}}
+    input  CLK     ,
+
+    //# {{power|Power}}
+    input  NOTIFIER,
+    input  VPWR    ,
+    input  VGND
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_DFF_P_PP_PG_N_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__BUF_8_V
+`define SKY130_FD_SC_HVL__BUF_8_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog wrapper for buf with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__buf.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__buf_8 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hvl__buf base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__buf_8 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hvl__buf base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__BUF_8_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_DFF_P_V
+`define SKY130_FD_SC_HVL__UDP_DFF_P_V
+
+/**
+ * udp_dff$P: Positive edge triggered D flip-flop (Q output UDP).
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`include ""./sky130_fd_sc_hvl__udp_dff_p.blackbox.v""
+`else
+primitive sky130_fd_sc_hvl__udp_dff$P (
+    Q  ,
+    D  ,
+    CLK
+);
+
+    output Q  ;
+    input  D  ;
+    input  CLK;
+
+    reg Q;
+
+    table
+     //  D  CLK  :  Qt : Qt+1
+         1  (01) :  ?  :  1    ; // clocked data
+         0  (01) :  ?  :  0    ;
+         1  (x1) :  1  :  1    ; // reducing pessimism
+         0  (x1) :  0  :  0    ;
+         0   x   :  0  :  0    ; // unkown CP, hold when D==Q==0
+         1   x   :  1  :  1    ; // unkown CP, hold when D==Q==1
+         ?  (?0) :  ?  :  -    ;
+         *   b   :  ?  :  -    ; // ignore edges on data, unless CP=X
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_DFF_P_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if ((B)) (A +=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
+ifnone (A +=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
+if ((A)) (B +=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
+ifnone (B +=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_FUNCTIONAL_V
+`define SKY130_FD_SC_HVL__LSBUFLV2HV_FUNCTIONAL_V
+
+/**
+ * lsbuflv2hv: Level-shift buffer, low voltage-to-high voltage,
+ *             isolated well on input buffer, double height cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__lsbuflv2hv (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    //  Name  Output  Other arguments
+    buf buf0 (X     , A              );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFLV2HV_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__EINVP_SYMBOL_V
+`define SKY130_FD_SC_HVL__EINVP_SYMBOL_V
+
+/**
+ * einvp: Tri-state inverter, positive enable.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__einvp (
+    //# {{data|Data Signals}}
+    input  A ,
+    output Z ,
+
+    //# {{control|Control Signals}}
+    input  TE
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__EINVP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SDFXTP_PP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__SDFXTP_PP_BLACKBOX_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__sdfxtp (
+    Q   ,
+    CLK ,
+    D   ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFXTP_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_SYMBOL_V
+`define SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_SYMBOL_V
+
+/**
+ * lsbufhv2lv_simple: Level shifting buffer, High Voltage to Low
+ *                    Voltage, simple (hv devices in inverters on lv
+ *                    power rail).
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__lsbufhv2lv_simple (
+    //# {{data|Data Signals}}
+    input  A,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR ;
+    supply0 VGND ;
+    supply1 LVPWR;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_V
+`define SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_V
+
+/**
+ * lsbuflv2hv_isosrchvaon: Level shift buffer, low voltage to high
+ *                         voltage, isolated well on input buffer,
+ *                         inverting sleep mode input, zero power
+ *                         sleep mode.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__EINVP_1_V
+`define SKY130_FD_SC_HVL__EINVP_1_V
+
+/**
+ * einvp: Tri-state inverter, positive enable.
+ *
+ * Verilog wrapper for einvp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__einvp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__einvp_1 (
+    Z   ,
+    A   ,
+    TE  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hvl__einvp base (
+        .Z(Z),
+        .A(A),
+        .TE(TE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__einvp_1 (
+    Z ,
+    A ,
+    TE
+);
+
+    output Z ;
+    input  A ;
+    input  TE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hvl__einvp base (
+        .Z(Z),
+        .A(A),
+        .TE(TE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__EINVP_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__NAND3_SYMBOL_V
+`define SKY130_FD_SC_HVL__NAND3_SYMBOL_V
+
+/**
+ * nand3: 3-input NAND.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__nand3 (
+    //# {{data|Data Signals}}
+    input  A,
+    input  B,
+    input  C,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__NAND3_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__NOR2_TB_V
+`define SKY130_FD_SC_HVL__NOR2_TB_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__nor2.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg B;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Y;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        B    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   B    = 1\'b0;
+        #60   VGND = 1\'b0;
+        #80   VNB  = 1\'b0;
+        #100  VPB  = 1\'b0;
+        #120  VPWR = 1\'b0;
+        #140  A    = 1\'b1;
+        #160  B    = 1\'b1;
+        #180  VGND = 1\'b1;
+        #200  VNB  = 1\'b1;
+        #220  VPB  = 1\'b1;
+        #240  VPWR = 1\'b1;
+        #260  A    = 1\'b0;
+        #280  B    = 1\'b0;
+        #300  VGND = 1\'b0;
+        #320  VNB  = 1\'b0;
+        #340  VPB  = 1\'b0;
+        #360  VPWR = 1\'b0;
+        #380  VPWR = 1\'b1;
+        #400  VPB  = 1\'b1;
+        #420  VNB  = 1\'b1;
+        #440  VGND = 1\'b1;
+        #460  B    = 1\'b1;
+        #480  A    = 1\'b1;
+        #500  VPWR = 1\'bx;
+        #520  VPB  = 1\'bx;
+        #540  VNB  = 1\'bx;
+        #560  VGND = 1\'bx;
+        #580  B    = 1\'bx;
+        #600  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_hvl__nor2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__NOR2_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_DFF_PS_PP_PG_N_SYMBOL_V
+`define SKY130_FD_SC_HVL__UDP_DFF_PS_PP_PG_N_SYMBOL_V
+
+/**
+ * udp_dff$PS_pp$PG$N: Positive edge triggered D flip-flop with active
+ *                     high
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N (
+    //# {{data|Data Signals}}
+    input  D       ,
+    output Q       ,
+
+    //# {{control|Control Signals}}
+    input  SET     ,
+
+    //# {{clocks|Clocking}}
+    input  CLK     ,
+
+    //# {{power|Power}}
+    input  NOTIFIER,
+    input  VPWR    ,
+    input  VGND
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_DFF_PS_PP_PG_N_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__A22O_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HVL__A22O_BEHAVIORAL_PP_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ *       X = ((A1 & A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__a22o (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire and1_out         ;
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                  Name         Output             Other arguments
+    and                                 and0        (and0_out         , B1, B2               );
+    and                                 and1        (and1_out         , A1, A2               );
+    or                                  or0         (or0_out_X        , and1_out, and0_out   );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                 buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__A22O_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__O22A_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HVL__O22A_FUNCTIONAL_PP_V
+
+/**
+ * o22a: 2-input OR into both inputs of 2-input AND.
+ *
+ *       X = ((A1 | A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__o22a (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire or1_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                  Name         Output             Other arguments
+    or                                  or0         (or0_out          , A2, A1                );
+    or                                  or1         (or1_out          , B2, B1                );
+    and                                 and0        (and0_out_X       , or0_out, or1_out      );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                 buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__O22A_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_HL_PP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__LSBUFHV2HV_HL_PP_BLACKBOX_V
+
+/**
+ * lsbufhv2hv_hl: Level shifting buffer, High Voltage to High Voltage,
+ *                Higher Voltage to Lower Voltage.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__lsbufhv2hv_hl (
+    X       ,
+    A       ,
+    VPWR    ,
+    VGND    ,
+    LOWHVPWR,
+    VPB     ,
+    VNB
+);
+
+    output X       ;
+    input  A       ;
+    input  VPWR    ;
+    input  VGND    ;
+    input  LOWHVPWR;
+    input  VPB     ;
+    input  VNB     ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFHV2HV_HL_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DLCLKP_SYMBOL_V
+`define SKY130_FD_SC_HVL__DLCLKP_SYMBOL_V
+
+/**
+ * dlclkp: Clock gate.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__dlclkp (
+    //# {{clocks|Clocking}}
+    input  CLK ,
+    input  GATE,
+    output GCLK
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DLCLKP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__A21OI_PP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__A21OI_PP_BLACKBOX_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | B1)
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__a21oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__A21OI_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__O21A_TB_V
+`define SKY130_FD_SC_HVL__O21A_TB_V
+
+/**
+ * o21a: 2-input OR into first input of 2-input AND.
+ *
+ *       X = ((A1 | A2) & B1)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__o21a.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg B1;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        B1   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   B1   = 1\'b0;
+        #80   VGND = 1\'b0;
+        #100  VNB  = 1\'b0;
+        #120  VPB  = 1\'b0;
+        #140  VPWR = 1\'b0;
+        #160  A1   = 1\'b1;
+        #180  A2   = 1\'b1;
+        #200  B1   = 1\'b1;
+        #220  VGND = 1\'b1;
+        #240  VNB  = 1\'b1;
+        #260  VPB  = 1\'b1;
+        #280  VPWR = 1\'b1;
+        #300  A1   = 1\'b0;
+        #320  A2   = 1\'b0;
+        #340  B1   = 1\'b0;
+        #360  VGND = 1\'b0;
+        #380  VNB  = 1\'b0;
+        #400  VPB  = 1\'b0;
+        #420  VPWR = 1\'b0;
+        #440  VPWR = 1\'b1;
+        #460  VPB  = 1\'b1;
+        #480  VNB  = 1\'b1;
+        #500  VGND = 1\'b1;
+        #520  B1   = 1\'b1;
+        #540  A2   = 1\'b1;
+        #560  A1   = 1\'b1;
+        #580  VPWR = 1\'bx;
+        #600  VPB  = 1\'bx;
+        #620  VNB  = 1\'bx;
+        #640  VGND = 1\'bx;
+        #660  B1   = 1\'bx;
+        #680  A2   = 1\'bx;
+        #700  A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_hvl__o21a dut (.A1(A1), .A2(A2), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__O21A_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__O22A_V
+`define SKY130_FD_SC_HVL__O22A_V
+
+/**
+ * o22a: 2-input OR into both inputs of 2-input AND.
+ *
+ *       X = ((A1 | A2) & (B1 | B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__o22a.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__o22a.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__o22a.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__o22a.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__O22A_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_DFF_PS_PP_PG_N_TB_V
+`define SKY130_FD_SC_HVL__UDP_DFF_PS_PP_PG_N_TB_V
+
+/**
+ * udp_dff$PS_pp$PG$N: Positive edge triggered D flip-flop with active
+ *                     high
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__udp_dff_ps_pp_pg_n.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg SET;
+    reg NOTIFIER;
+    reg VPWR;
+    reg VGND;
+
+    // Outputs are wires
+    wire Q;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D        = 1\'bX;
+        NOTIFIER = 1\'bX;
+        SET      = 1\'bX;
+        VGND     = 1\'bX;
+        VPWR     = 1\'bX;
+
+        #20   D        = 1\'b0;
+        #40   NOTIFIER = 1\'b0;
+        #60   SET      = 1\'b0;
+        #80   VGND     = 1\'b0;
+        #100  VPWR     = 1\'b0;
+        #120  D        = 1\'b1;
+        #140  NOTIFIER = 1\'b1;
+        #160  SET      = 1\'b1;
+        #180  VGND     = 1\'b1;
+        #200  VPWR     = 1\'b1;
+        #220  D        = 1\'b0;
+        #240  NOTIFIER = 1\'b0;
+        #260  SET      = 1\'b0;
+        #280  VGND     = 1\'b0;
+        #300  VPWR     = 1\'b0;
+        #320  VPWR     = 1\'b1;
+        #340  VGND     = 1\'b1;
+        #360  SET      = 1\'b1;
+        #380  NOTIFIER = 1\'b1;
+        #400  D        = 1\'b1;
+        #420  VPWR     = 1\'bx;
+        #440  VGND     = 1\'bx;
+        #460  SET      = 1\'bx;
+        #480  NOTIFIER = 1\'bx;
+        #500  D        = 1\'bx;
+    end
+
+    // Create a clock
+    reg CLK;
+    initial
+    begin
+        CLK = 1\'b0;
+    end
+
+    always
+    begin
+        #5 CLK = ~CLK;
+    end
+
+    sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dut (.D(D), .SET(SET), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_DFF_PS_PP_PG_N_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__SDFXTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HVL__SDFXTP_BEHAVIORAL_PP_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hvl__udp_dff_p_pp_pg_n.v""
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v""
+
+`celldefine
+module sky130_fd_sc_hvl__sdfxtp (
+    Q   ,
+    CLK ,
+    D   ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q      ;
+    wire mux_out    ;
+    reg  notifier   ;
+    wire cond1      ;
+    wire cond2      ;
+    wire cond3      ;
+    wire D_delayed  ;
+    wire SCD_delayed;
+    wire SCE_delayed;
+    wire CLK_delayed;
+    wire buf0_out_Q ;
+
+    //                                  Name         Output      Other arguments
+    sky130_fd_sc_hvl__udp_mux_2to1      mux_2to10   (mux_out   , D_delayed, SCD_delayed, SCE_delayed       );
+    sky130_fd_sc_hvl__udp_dff$P_pp$PG$N dff0        (buf_Q     , mux_out, CLK_delayed, notifier, VPWR, VGND);
+    assign cond1 = ( SCE_delayed === 1\'b0 );
+    assign cond2 = ( SCE_delayed === 1\'b1 );
+    assign cond3 = ( D_delayed !== SCD_delayed );
+    buf                                 buf0        (buf0_out_Q, buf_Q                                     );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q         , buf0_out_Q, VPWR, VGND                    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFXTP_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__MUX4_BLACKBOX_V
+`define SKY130_FD_SC_HVL__MUX4_BLACKBOX_V
+
+/**
+ * mux4: 4-input multiplexer.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__mux4 (
+    X ,
+    A0,
+    A1,
+    A2,
+    A3,
+    S0,
+    S1
+);
+
+    output X ;
+    input  A0;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  S0;
+    input  S1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__MUX4_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DFRBP_TB_V
+`define SKY130_FD_SC_HVL__DFRBP_TB_V
+
+/**
+ * dfrbp: Delay flop, inverted reset, complementary outputs.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__dfrbp.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg RESET_B;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Q;
+    wire Q_N;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D       = 1\'bX;
+        RESET_B = 1\'bX;
+        VGND    = 1\'bX;
+        VNB     = 1\'bX;
+        VPB     = 1\'bX;
+        VPWR    = 1\'bX;
+
+        #20   D       = 1\'b0;
+        #40   RESET_B = 1\'b0;
+        #60   VGND    = 1\'b0;
+        #80   VNB     = 1\'b0;
+        #100  VPB     = 1\'b0;
+        #120  VPWR    = 1\'b0;
+        #140  D       = 1\'b1;
+        #160  RESET_B = 1\'b1;
+        #180  VGND    = 1\'b1;
+        #200  VNB     = 1\'b1;
+        #220  VPB     = 1\'b1;
+        #240  VPWR    = 1\'b1;
+        #260  D       = 1\'b0;
+        #280  RESET_B = 1\'b0;
+        #300  VGND    = 1\'b0;
+        #320  VNB     = 1\'b0;
+        #340  VPB     = 1\'b0;
+        #360  VPWR    = 1\'b0;
+        #380  VPWR    = 1\'b1;
+        #400  VPB     = 1\'b1;
+        #420  VNB     = 1\'b1;
+        #440  VGND    = 1\'b1;
+        #460  RESET_B = 1\'b1;
+        #480  D       = 1\'b1;
+        #500  VPWR    = 1\'bx;
+        #520  VPB     = 1\'bx;
+        #540  VNB     = 1\'bx;
+        #560  VGND    = 1\'bx;
+        #580  RESET_B = 1\'bx;
+        #600  D       = 1\'bx;
+    end
+
+    // Create a clock
+    reg CLK;
+    initial
+    begin
+        CLK = 1\'b0;
+    end
+
+    always
+    begin
+        #5 CLK = ~CLK;
+    end
+
+    sky130_fd_sc_hvl__dfrbp dut (.D(D), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DFRBP_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DFSBP_PP_SYMBOL_V
+`define SKY130_FD_SC_HVL__DFSBP_PP_SYMBOL_V
+
+/**
+ * dfsbp: Delay flop, inverted set, complementary outputs.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__dfsbp (
+    //# {{data|Data Signals}}
+    input  D    ,
+    output Q    ,
+    output Q_N  ,
+
+    //# {{control|Control Signals}}
+    input  SET_B,
+
+    //# {{clocks|Clocking}}
+    input  CLK  ,
+
+    //# {{power|Power}}
+    input  VPB  ,
+    input  VPWR ,
+    input  VGND ,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DFSBP_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_FUNCTIONAL_V
+`define SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_FUNCTIONAL_V
+
+/**
+ * lsbuflv2hv_isosrchvaon: Level shift buffer, low voltage to high
+ *                         voltage, isolated well on input buffer,
+ *                         inverting sleep mode input, zero power
+ *                         sleep mode.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon (
+    X      ,
+    A      ,
+    SLEEP_B
+);
+
+    // Module ports
+    output X      ;
+    input  A      ;
+    input  SLEEP_B;
+
+    // Local signals
+    wire SLEEP     ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    not not0 (SLEEP     , SLEEP_B        );
+    and and0 (and0_out_X, SLEEP_B, A     );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__OR2_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HVL__OR2_FUNCTIONAL_PP_V
+
+/**
+ * or2: 2-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__or2 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out_X        ;
+    wire pwrgood_pp0_out_X;
+
+    //                                  Name         Output             Other arguments
+    or                                  or0         (or0_out_X        , B, A                 );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
+    buf                                 buf0        (X                , pwrgood_pp0_out_X    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__OR2_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__A22OI_1_V
+`define SKY130_FD_SC_HVL__A22OI_1_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a22oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__a22oi.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__a22oi_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hvl__a22oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__a22oi_1 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hvl__a22oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__A22OI_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DIODE_TB_V
+`define SKY130_FD_SC_HVL__DIODE_TB_V
+
+/**
+ * diode: Antenna tie-down diode.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__diode.v""
+
+module top();
+
+    // Inputs are registered
+    reg DIODE;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        DIODE = 1\'bX;
+        VGND  = 1\'bX;
+        VNB   = 1\'bX;
+        VPB   = 1\'bX;
+        VPWR  = 1\'bX;
+
+        #20   DIODE = 1\'b0;
+        #40   VGND  = 1\'b0;
+        #60   VNB   = 1\'b0;
+        #80   VPB   = 1\'b0;
+        #100  VPWR  = 1\'b0;
+        #120  DIODE = 1\'b1;
+        #140  VGND  = 1\'b1;
+        #160  VNB   = 1\'b1;
+        #180  VPB   = 1\'b1;
+        #200  VPWR  = 1\'b1;
+        #220  DIODE = 1\'b0;
+        #240  VGND  = 1\'b0;
+        #260  VNB   = 1\'b0;
+        #280  VPB   = 1\'b0;
+        #300  VPWR  = 1\'b0;
+        #320  VPWR  = 1\'b1;
+        #340  VPB   = 1\'b1;
+        #360  VNB   = 1\'b1;
+        #380  VGND  = 1\'b1;
+        #400  DIODE = 1\'b1;
+        #420  VPWR  = 1\'bx;
+        #440  VPB   = 1\'bx;
+        #460  VNB   = 1\'bx;
+        #480  VGND  = 1\'bx;
+        #500  DIODE = 1\'bx;
+    end
+
+    sky130_fd_sc_hvl__diode dut (.DIODE(DIODE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DIODE_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_MUX_4TO2_BLACKBOX_V
+`define SKY130_FD_SC_HVL__UDP_MUX_4TO2_BLACKBOX_V
+
+/**
+ * udp_mux_4to2: Four to one multiplexer with 2 select controls
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__udp_mux_4to2 (
+    X ,
+    A0,
+    A1,
+    A2,
+    A3,
+    S0,
+    S1
+);
+
+    output X ;
+    input  A0;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  S0;
+    input  S1;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_MUX_4TO2_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_LH_1_V
+`define SKY130_FD_SC_HVL__LSBUFHV2HV_LH_1_V
+
+/**
+ * lsbufhv2hv_lh: Level shifting buffer, High Voltage to High Voltage,
+ *                Lower Voltage to Higher Voltage.
+ *
+ * Verilog wrapper for lsbufhv2hv_lh with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__lsbufhv2hv_lh.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__lsbufhv2hv_lh_1 (
+    X       ,
+    A       ,
+    VPWR    ,
+    VGND    ,
+    LOWHVPWR,
+    VPB     ,
+    VNB
+);
+
+    output X       ;
+    input  A       ;
+    input  VPWR    ;
+    input  VGND    ;
+    input  LOWHVPWR;
+    input  VPB     ;
+    input  VNB     ;
+    sky130_fd_sc_hvl__lsbufhv2hv_lh base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .LOWHVPWR(LOWHVPWR),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__lsbufhv2hv_lh_1 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR    ;
+    supply0 VGND    ;
+    supply1 LOWHVPWR;
+    supply1 VPB     ;
+    supply0 VNB     ;
+
+    sky130_fd_sc_hvl__lsbufhv2hv_lh base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFHV2HV_LH_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SDFSTP_SYMBOL_V
+`define SKY130_FD_SC_HVL__SDFSTP_SYMBOL_V
+
+/**
+ * sdfstp: Scan delay flop, inverted set, non-inverted clock,
+ *         single output.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__sdfstp (
+    //# {{data|Data Signals}}
+    input  D    ,
+    output Q    ,
+
+    //# {{control|Control Signals}}
+    input  SET_B,
+
+    //# {{scanchain|Scan Chain}}
+    input  SCD  ,
+    input  SCE  ,
+
+    //# {{clocks|Clocking}}
+    input  CLK
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFSTP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__DLXTP_FUNCTIONAL_V
+`define SKY130_FD_SC_HVL__DLXTP_FUNCTIONAL_V
+
+/**
+ * dlxtp: Delay latch, non-inverted enable, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_p/sky130_fd_sc_hvl__udp_dlatch_p.v""
+
+`celldefine
+module sky130_fd_sc_hvl__dlxtp (
+    Q   ,
+    D   ,
+    GATE
+);
+
+    // Module ports
+    output Q   ;
+    input  D   ;
+    input  GATE;
+
+    // Local signals
+    wire buf_Q;
+
+    //                             Delay       Name     Output  Other arguments
+    sky130_fd_sc_hvl__udp_dlatch$P `UNIT_DELAY dlatch0 (buf_Q , D, GATE        );
+    buf                                        buf0    (Q     , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DLXTP_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__O21A_SYMBOL_V
+`define SKY130_FD_SC_HVL__O21A_SYMBOL_V
+
+/**
+ * o21a: 2-input OR into first input of 2-input AND.
+ *
+ *       X = ((A1 | A2) & B1)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__o21a (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  B1,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__O21A_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DFRBP_PP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__DFRBP_PP_BLACKBOX_V
+
+/**
+ * dfrbp: Delay flop, inverted reset, complementary outputs.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__dfrbp (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DFRBP_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_FUNCTIONAL_PP_V
+
+/**
+ * lsbuflv2hv_clkiso_hlkg: Level-shift clock buffer, low voltage to
+ *                         high voltage, isolated well
+ *                         on input buffer, inverting sleep
+ *                         mode input.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_isolatchhv_pp_plg_s/sky130_fd_sc_hvl__udp_isolatchhv_pp_plg_s.v""
+
+`celldefine
+module sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg (
+    X      ,
+    A      ,
+    SLEEP_B,
+    VPWR   ,
+    VGND   ,
+    LVPWR  ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output X      ;
+    input  A      ;
+    input  SLEEP_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  LVPWR  ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire SLEEP               ;
+    wire and0_out_X          ;
+    wire isolatchhv_pp0_out_X;
+
+    //                                        Name            Output                Other arguments
+    not                                       not0           (SLEEP               , SLEEP_B                             );
+    and                                       and0           (and0_out_X          , SLEEP_B, A                          );
+    sky130_fd_sc_hvl__udp_isolatchhv_pp$PLG$S isolatchhv_pp0 (isolatchhv_pp0_out_X, and0_out_X, VPWR, LVPWR, VGND, SLEEP);
+    buf                                       buf0           (X                   , isolatchhv_pp0_out_X                );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__DLRTP_FUNCTIONAL_V
+`define SKY130_FD_SC_HVL__DLRTP_FUNCTIONAL_V
+
+/**
+ * dlrtp: Delay latch, inverted reset, non-inverted enable,
+ *        single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_pr/sky130_fd_sc_hvl__udp_dlatch_pr.v""
+
+`celldefine
+module sky130_fd_sc_hvl__dlrtp (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE
+);
+
+    // Module ports
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+
+    // Local signals
+    wire RESET;
+    wire buf_Q;
+
+    //                              Delay       Name     Output  Other arguments
+    not                                         not0    (RESET , RESET_B        );
+    sky130_fd_sc_hvl__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET );
+    buf                                         buf0    (Q     , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DLRTP_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__NOR3_PP_SYMBOL_V
+`define SKY130_FD_SC_HVL__NOR3_PP_SYMBOL_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ *       Y = !(A | B | C | !D)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__nor3 (
+    //# {{data|Data Signals}}
+    input  A   ,
+    input  B   ,
+    input  C   ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__NOR3_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SCHMITTBUF_1_V
+`define SKY130_FD_SC_HVL__SCHMITTBUF_1_V
+
+/**
+ * schmittbuf: Schmitt Trigger Buffer.
+ *
+ * Verilog wrapper for schmittbuf with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__schmittbuf.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__schmittbuf_1 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hvl__schmittbuf base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__schmittbuf_1 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hvl__schmittbuf base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SCHMITTBUF_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_BLACKBOX_V
+`define SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_BLACKBOX_V
+
+/**
+ * lsbuflv2hv_clkiso_hlkg: Level-shift clock buffer, low voltage to
+ *                         high voltage, isolated well
+ *                         on input buffer, inverting sleep
+ *                         mode input.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg (
+    X      ,
+    A      ,
+    SLEEP_B
+);
+
+    output X      ;
+    input  A      ;
+    input  SLEEP_B;
+
+    // Voltage supply signals
+    supply1 VPWR ;
+    supply0 VGND ;
+    supply1 LVPWR;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__O21A_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HVL__O21A_BEHAVIORAL_PP_V
+
+/**
+ * o21a: 2-input OR into first input of 2-input AND.
+ *
+ *       X = ((A1 | A2) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__o21a (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                  Name         Output             Other arguments
+    or                                  or0         (or0_out          , A2, A1                );
+    and                                 and0        (and0_out_X       , or0_out, B1           );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                 buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__O21A_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SDFSBP_1_V
+`define SKY130_FD_SC_HVL__SDFSBP_1_V
+
+/**
+ * sdfsbp: Scan delay flop, inverted set, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog wrapper for sdfsbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__sdfsbp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__sdfsbp_1 (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hvl__sdfsbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .SET_B(SET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__sdfsbp_1 (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B
+);
+
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hvl__sdfsbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .SET_B(SET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFSBP_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DFSTP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__DFSTP_BLACKBOX_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__dfstp (
+    Q    ,
+    CLK  ,
+    D    ,
+    SET_B
+);
+
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DFSTP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__AND3_V
+`define SKY130_FD_SC_HVL__AND3_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__and3.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__and3.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__and3.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__and3.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__AND3_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__FILL_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HVL__FILL_BEHAVIORAL_PP_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__fill (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__FILL_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__CONB_PP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__CONB_PP_BLACKBOX_V
+
+/**
+ * conb: Constant value, low, high outputs.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__conb (
+    HI  ,
+    LO  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output HI  ;
+    output LO  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__CONB_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_BEHAVIORAL_PP_V
+
+/**
+ * lsbuflv2hv_symmetric: Level shifting buffer, Low Voltage to High
+ *                       Voltage, Symmetrical.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__lsbuflv2hv_symmetric (
+    X    ,
+    A    ,
+    VPWR ,
+    VGND ,
+    LVPWR,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output X    ;
+    input  A    ;
+    input  VPWR ;
+    input  VGND ;
+    input  LVPWR;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire pwrgood_pp0_out_A;
+    wire buf0_out_X       ;
+
+    //                                  Name         Output             Other arguments
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A, A, LVPWR, VGND        );
+    buf                                 buf0        (buf0_out_X       , pwrgood_pp0_out_A     );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (X                , buf0_out_X, VPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DFXBP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__DFXBP_BLACKBOX_V
+
+/**
+ * dfxbp: Delay flop, complementary outputs.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__dfxbp (
+    Q  ,
+    Q_N,
+    CLK,
+    D
+);
+
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DFXBP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SDLXTP_PP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__SDLXTP_PP_BLACKBOX_V
+
+/**
+ * sdlxtp: ????.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__sdlxtp (
+    Q   ,
+    D   ,
+    SCD ,
+    SCE ,
+    GATE,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    input  D   ;
+    input  SCD ;
+    input  SCE ;
+    input  GATE;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDLXTP_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__BUF_16_V
+`define SKY130_FD_SC_HVL__BUF_16_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog wrapper for buf with size of 16 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__buf.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__buf_16 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hvl__buf base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__buf_16 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hvl__buf base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__BUF_16_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DECAP_PP_SYMBOL_V
+`define SKY130_FD_SC_HVL__DECAP_PP_SYMBOL_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__decap (
+    //# {{power|Power}}
+    input VPB ,
+    input VPWR,
+    input VGND,
+    input VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DECAP_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__NOR3_1_V
+`define SKY130_FD_SC_HVL__NOR3_1_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ *       Y = !(A | B | C | !D)
+ *
+ * Verilog wrapper for nor3 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__nor3.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__nor3_1 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hvl__nor3 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__nor3_1 (
+    Y,
+    A,
+    B,
+    C
+);
+
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hvl__nor3 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__NOR3_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__NOR2_1_V
+`define SKY130_FD_SC_HVL__NOR2_1_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog wrapper for nor2 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__nor2.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__nor2_1 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hvl__nor2 base (
+        .Y(Y),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__nor2_1 (
+    Y,
+    A,
+    B
+);
+
+    output Y;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hvl__nor2 base (
+        .Y(Y),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__NOR2_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_DLATCH_PR_SYMBOL_V
+`define SKY130_FD_SC_HVL__UDP_DLATCH_PR_SYMBOL_V
+
+/**
+ * udp_dlatch$PR: D-latch, gated clear direct / gate active high
+ *                (Q output UDP)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__udp_dlatch$PR (
+    //# {{data|Data Signals}}
+    input  D    ,
+    output Q    ,
+
+    //# {{control|Control Signals}}
+    input  RESET,
+
+    //# {{clocks|Clocking}}
+    input  GATE
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_DLATCH_PR_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__O22AI_1_V
+`define SKY130_FD_SC_HVL__O22AI_1_V
+
+/**
+ * o22ai: 2-input OR into both inputs of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & (B1 | B2))
+ *
+ * Verilog wrapper for o22ai with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__o22ai.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__o22ai_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hvl__o22ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__o22ai_1 (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hvl__o22ai base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__O22AI_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DLXTP_V
+`define SKY130_FD_SC_HVL__DLXTP_V
+
+/**
+ * dlxtp: Delay latch, non-inverted enable, single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__dlxtp.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__dlxtp.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__dlxtp.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__dlxtp.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DLXTP_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__O21AI_PP_SYMBOL_V
+`define SKY130_FD_SC_HVL__O21AI_PP_SYMBOL_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & B1)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__o21ai (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  B1  ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__O21AI_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__EINVP_TB_V
+`define SKY130_FD_SC_HVL__EINVP_TB_V
+
+/**
+ * einvp: Tri-state inverter, positive enable.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__einvp.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg TE;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Z;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        TE   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   TE   = 1\'b0;
+        #60   VGND = 1\'b0;
+        #80   VNB  = 1\'b0;
+        #100  VPB  = 1\'b0;
+        #120  VPWR = 1\'b0;
+        #140  A    = 1\'b1;
+        #160  TE   = 1\'b1;
+        #180  VGND = 1\'b1;
+        #200  VNB  = 1\'b1;
+        #220  VPB  = 1\'b1;
+        #240  VPWR = 1\'b1;
+        #260  A    = 1\'b0;
+        #280  TE   = 1\'b0;
+        #300  VGND = 1\'b0;
+        #320  VNB  = 1\'b0;
+        #340  VPB  = 1\'b0;
+        #360  VPWR = 1\'b0;
+        #380  VPWR = 1\'b1;
+        #400  VPB  = 1\'b1;
+        #420  VNB  = 1\'b1;
+        #440  VGND = 1\'b1;
+        #460  TE   = 1\'b1;
+        #480  A    = 1\'b1;
+        #500  VPWR = 1\'bx;
+        #520  VPB  = 1\'bx;
+        #540  VNB  = 1\'bx;
+        #560  VGND = 1\'bx;
+        #580  TE   = 1\'bx;
+        #600  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_hvl__einvp dut (.A(A), .TE(TE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Z(Z));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__EINVP_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__O21AI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HVL__O21AI_FUNCTIONAL_PP_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__o21ai (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                  Name         Output             Other arguments
+    or                                  or0         (or0_out          , A2, A1                 );
+    nand                                nand0       (nand0_out_Y      , B1, or0_out            );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                 buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__O21AI_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_HL_V
+`define SKY130_FD_SC_HVL__LSBUFHV2HV_HL_V
+
+/**
+ * lsbufhv2hv_hl: Level shifting buffer, High Voltage to High Voltage,
+ *                Higher Voltage to Lower Voltage.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__lsbufhv2hv_hl.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__lsbufhv2hv_hl.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__lsbufhv2hv_hl.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__lsbufhv2hv_hl.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFHV2HV_HL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__A22OI_V
+`define SKY130_FD_SC_HVL__A22OI_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__a22oi.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__a22oi.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__a22oi.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__a22oi.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__A22OI_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_PP_SYMBOL_V
+`define SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_PP_SYMBOL_V
+
+/**
+ * lsbufhv2lv_simple: Level shifting buffer, High Voltage to Low
+ *                    Voltage, simple (hv devices in inverters on lv
+ *                    power rail).
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__lsbufhv2lv_simple (
+    //# {{data|Data Signals}}
+    input  A    ,
+    output X    ,
+
+    //# {{power|Power}}
+    input  LVPWR,
+    input  VPB  ,
+    input  VPWR ,
+    input  VGND ,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__A21O_BLACKBOX_V
+`define SKY130_FD_SC_HVL__A21O_BLACKBOX_V
+
+/**
+ * a21o: 2-input AND into first input of 2-input OR.
+ *
+ *       X = ((A1 & A2) | B1)
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__a21o (
+    X ,
+    A1,
+    A2,
+    B1
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__A21O_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__CONB_TB_V
+`define SKY130_FD_SC_HVL__CONB_TB_V
+
+/**
+ * conb: Constant value, low, high outputs.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__conb.v""
+
+module top();
+
+    // Inputs are registered
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire HI;
+    wire LO;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   VGND = 1\'b0;
+        #40   VNB  = 1\'b0;
+        #60   VPB  = 1\'b0;
+        #80   VPWR = 1\'b0;
+        #100  VGND = 1\'b1;
+        #120  VNB  = 1\'b1;
+        #140  VPB  = 1\'b1;
+        #160  VPWR = 1\'b1;
+        #180  VGND = 1\'b0;
+        #200  VNB  = 1\'b0;
+        #220  VPB  = 1\'b0;
+        #240  VPWR = 1\'b0;
+        #260  VPWR = 1\'b1;
+        #280  VPB  = 1\'b1;
+        #300  VNB  = 1\'b1;
+        #320  VGND = 1\'b1;
+        #340  VPWR = 1\'bx;
+        #360  VPB  = 1\'bx;
+        #380  VNB  = 1\'bx;
+        #400  VGND = 1\'bx;
+    end
+
+    sky130_fd_sc_hvl__conb dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .HI(HI), .LO(LO));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__CONB_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_ISOLATCHHV_PP_PLG_S_BLACKBOX_V
+`define SKY130_FD_SC_HVL__UDP_ISOLATCHHV_PP_PLG_S_BLACKBOX_V
+
+/**
+ * udp_isolatchhv_pp$PLG$S: Power isolating latch (for HV). Includes
+ *                          VPWR, LVPWR, and VGND power pins with
+ *                          active high sleep pin (SLEEP).
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__udp_isolatchhv_pp$PLG$S (
+    UDP_OUT,
+    UDP_IN ,
+    VPWR   ,
+    LVPWR  ,
+    VGND   ,
+    SLEEP
+);
+
+    output UDP_OUT;
+    input  UDP_IN ;
+    input  VPWR   ;
+    input  LVPWR  ;
+    input  VGND   ;
+    input  SLEEP  ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_ISOLATCHHV_PP_PLG_S_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__A22O_1_V
+`define SKY130_FD_SC_HVL__A22O_1_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ *       X = ((A1 & A2) | (B1 & B2))
+ *
+ * Verilog wrapper for a22o with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__a22o.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__a22o_1 (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hvl__a22o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__a22o_1 (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hvl__a22o base (
+        .X(X),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .B2(B2)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__A22O_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__NAND2_BLACKBOX_V
+`define SKY130_FD_SC_HVL__NAND2_BLACKBOX_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__nand2 (
+    Y,
+    A,
+    B
+);
+
+    output Y;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__NAND2_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DFXBP_1_V
+`define SKY130_FD_SC_HVL__DFXBP_1_V
+
+/**
+ * dfxbp: Delay flop, complementary outputs.
+ *
+ * Verilog wrapper for dfxbp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__dfxbp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__dfxbp_1 (
+    Q   ,
+    Q_N ,
+    CLK ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    output Q_N ;
+    input  CLK ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hvl__dfxbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__dfxbp_1 (
+    Q  ,
+    Q_N,
+    CLK,
+    D
+);
+
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hvl__dfxbp base (
+        .Q(Q),
+        .Q_N(Q_N),
+        .CLK(CLK),
+        .D(D)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DFXBP_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SDFRTP_SYMBOL_V
+`define SKY130_FD_SC_HVL__SDFRTP_SYMBOL_V
+
+/**
+ * sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
+ *         single output.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__sdfrtp (
+    //# {{data|Data Signals}}
+    input  D      ,
+    output Q      ,
+
+    //# {{control|Control Signals}}
+    input  RESET_B,
+
+    //# {{scanchain|Scan Chain}}
+    input  SCD    ,
+    input  SCE    ,
+
+    //# {{clocks|Clocking}}
+    input  CLK
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFRTP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__NAND2_FUNCTIONAL_V
+`define SKY130_FD_SC_HVL__NAND2_FUNCTIONAL_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__nand2 (
+    Y,
+    A,
+    B
+);
+
+    // Module ports
+    output Y;
+    input  A;
+    input  B;
+
+    // Local signals
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    nand nand0 (nand0_out_Y, B, A           );
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__NAND2_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DFXTP_SYMBOL_V
+`define SKY130_FD_SC_HVL__DFXTP_SYMBOL_V
+
+/**
+ * dfxtp: Delay flop, single output.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__dfxtp (
+    //# {{data|Data Signals}}
+    input  D  ,
+    output Q  ,
+
+    //# {{clocks|Clocking}}
+    input  CLK
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DFXTP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_MUX_2TO1_SYMBOL_V
+`define SKY130_FD_SC_HVL__UDP_MUX_2TO1_SYMBOL_V
+
+/**
+ * udp_mux_2to1: Two to one multiplexer
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__udp_mux_2to1 (
+    //# {{data|Data Signals}}
+    input  A0,
+    input  A1,
+    output X ,
+
+    //# {{control|Control Signals}}
+    input  S
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_MUX_2TO1_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_DFF_PR_PP_PG_N_SYMBOL_V
+`define SKY130_FD_SC_HVL__UDP_DFF_PR_PP_PG_N_SYMBOL_V
+
+/**
+ * udp_dff$PR_pp$PG$N: Positive edge triggered D flip-flop with active
+ *                     high
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N (
+    //# {{data|Data Signals}}
+    input  D       ,
+    output Q       ,
+
+    //# {{control|Control Signals}}
+    input  RESET   ,
+
+    //# {{clocks|Clocking}}
+    input  CLK     ,
+
+    //# {{power|Power}}
+    input  NOTIFIER,
+    input  VPWR    ,
+    input  VGND
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_DFF_PR_PP_PG_N_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__O21AI_BEHAVIORAL_V
+`define SKY130_FD_SC_HVL__O21AI_BEHAVIORAL_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__o21ai (
+    Y ,
+    A1,
+    A2,
+    B1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out    ;
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    or   or0   (or0_out    , A2, A1         );
+    nand nand0 (nand0_out_Y, B1, or0_out    );
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__O21AI_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DFSTP_PP_SYMBOL_V
+`define SKY130_FD_SC_HVL__DFSTP_PP_SYMBOL_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__dfstp (
+    //# {{data|Data Signals}}
+    input  D    ,
+    output Q    ,
+
+    //# {{control|Control Signals}}
+    input  SET_B,
+
+    //# {{clocks|Clocking}}
+    input  CLK  ,
+
+    //# {{power|Power}}
+    input  VPB  ,
+    input  VPWR ,
+    input  VGND ,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DFSTP_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DLXTP_SYMBOL_V
+`define SKY130_FD_SC_HVL__DLXTP_SYMBOL_V
+
+/**
+ * dlxtp: Delay latch, non-inverted enable, single output.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__dlxtp (
+    //# {{data|Data Signals}}
+    input  D   ,
+    output Q   ,
+
+    //# {{clocks|Clocking}}
+    input  GATE
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DLXTP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__NAND2_BEHAVIORAL_V
+`define SKY130_FD_SC_HVL__NAND2_BEHAVIORAL_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__nand2 (
+    Y,
+    A,
+    B
+);
+
+    // Module ports
+    output Y;
+    input  A;
+    input  B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nand0_out_Y;
+
+    //   Name   Output       Other arguments
+    nand nand0 (nand0_out_Y, B, A           );
+    buf  buf0  (Y          , nand0_out_Y    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__NAND2_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_HL_SYMBOL_V
+`define SKY130_FD_SC_HVL__LSBUFHV2HV_HL_SYMBOL_V
+
+/**
+ * lsbufhv2hv_hl: Level shifting buffer, High Voltage to High Voltage,
+ *                Higher Voltage to Lower Voltage.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__lsbufhv2hv_hl (
+    //# {{data|Data Signals}}
+    input  A,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR    ;
+    supply0 VGND    ;
+    supply1 LOWHVPWR;
+    supply1 VPB     ;
+    supply0 VNB     ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFHV2HV_HL_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DLCLKP_1_V
+`define SKY130_FD_SC_HVL__DLCLKP_1_V
+
+/**
+ * dlclkp: Clock gate.
+ *
+ * Verilog wrapper for dlclkp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__dlclkp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__dlclkp_1 (
+    GCLK,
+    GATE,
+    CLK ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output GCLK;
+    input  GATE;
+    input  CLK ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hvl__dlclkp base (
+        .GCLK(GCLK),
+        .GATE(GATE),
+        .CLK(CLK),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__dlclkp_1 (
+    GCLK,
+    GATE,
+    CLK
+);
+
+    output GCLK;
+    input  GATE;
+    input  CLK ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hvl__dlclkp base (
+        .GCLK(GCLK),
+        .GATE(GATE),
+        .CLK(CLK)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DLCLKP_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SDFSTP_1_V
+`define SKY130_FD_SC_HVL__SDFSTP_1_V
+
+/**
+ * sdfstp: Scan delay flop, inverted set, non-inverted clock,
+ *         single output.
+ *
+ * Verilog wrapper for sdfstp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__sdfstp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__sdfstp_1 (
+    Q    ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hvl__sdfstp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .SET_B(SET_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__sdfstp_1 (
+    Q    ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B
+);
+
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hvl__sdfstp base (
+        .Q(Q),
+        .CLK(CLK),
+        .D(D),
+        .SCD(SCD),
+        .SCE(SCE),
+        .SET_B(SET_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFSTP_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__AND3_BLACKBOX_V
+`define SKY130_FD_SC_HVL__AND3_BLACKBOX_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__and3 (
+    X,
+    A,
+    B,
+    C
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__AND3_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__AND2_TB_V
+`define SKY130_FD_SC_HVL__AND2_TB_V
+
+/**
+ * and2: 2-input AND.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__and2.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg B;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        B    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   B    = 1\'b0;
+        #60   VGND = 1\'b0;
+        #80   VNB  = 1\'b0;
+        #100  VPB  = 1\'b0;
+        #120  VPWR = 1\'b0;
+        #140  A    = 1\'b1;
+        #160  B    = 1\'b1;
+        #180  VGND = 1\'b1;
+        #200  VNB  = 1\'b1;
+        #220  VPB  = 1\'b1;
+        #240  VPWR = 1\'b1;
+        #260  A    = 1\'b0;
+        #280  B    = 1\'b0;
+        #300  VGND = 1\'b0;
+        #320  VNB  = 1\'b0;
+        #340  VPB  = 1\'b0;
+        #360  VPWR = 1\'b0;
+        #380  VPWR = 1\'b1;
+        #400  VPB  = 1\'b1;
+        #420  VNB  = 1\'b1;
+        #440  VGND = 1\'b1;
+        #460  B    = 1\'b1;
+        #480  A    = 1\'b1;
+        #500  VPWR = 1\'bx;
+        #520  VPB  = 1\'bx;
+        #540  VNB  = 1\'bx;
+        #560  VGND = 1\'bx;
+        #580  B    = 1\'bx;
+        #600  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_hvl__and2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__AND2_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__NAND2_V
+`define SKY130_FD_SC_HVL__NAND2_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__nand2.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__nand2.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__nand2.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__nand2.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__NAND2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__BUF_BEHAVIORAL_V
+`define SKY130_FD_SC_HVL__BUF_BEHAVIORAL_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__buf (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__BUF_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__O22AI_V
+`define SKY130_FD_SC_HVL__O22AI_V
+
+/**
+ * o22ai: 2-input OR into both inputs of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & (B1 | B2))
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__o22ai.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__o22ai.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__o22ai.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__o22ai.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__O22AI_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__SDFSBP_BEHAVIORAL_V
+`define SKY130_FD_SC_HVL__SDFSBP_BEHAVIORAL_V
+
+/**
+ * sdfsbp: Scan delay flop, inverted set, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v""
+`include ""../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hvl__udp_dff_ps_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_hvl__sdfsbp (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B
+);
+
+    // Module ports
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q        ;
+    wire SET          ;
+    wire mux_out      ;
+    reg  notifier     ;
+    wire cond0        ;
+    wire cond1        ;
+    wire cond2        ;
+    wire cond3        ;
+    wire D_delayed    ;
+    wire SCD_delayed  ;
+    wire SCE_delayed  ;
+    wire SET_B_delayed;
+    wire CLK_delayed  ;
+
+    //                                   Name       Output   Other arguments
+    not                                  not0      (SET    , SET_B_delayed                                  );
+    sky130_fd_sc_hvl__udp_mux_2to1       mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed            );
+    sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
+    assign cond0 = ( SET_B_delayed === 1\'b1 );
+    assign cond1 = ( ( SCE_delayed === 1\'b0 ) & cond0 );
+    assign cond2 = ( ( SCE_delayed === 1\'b1 ) & cond0 );
+    assign cond3 = ( ( D_delayed !== SCD_delayed ) & cond0 );
+    buf                                  buf0      (Q      , buf_Q                                          );
+    not                                  not1      (Q_N    , buf_Q                                          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFSBP_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_FUNCTIONAL_V
+`define SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_FUNCTIONAL_V
+
+/**
+ * lsbuflv2hv_clkiso_hlkg: Level-shift clock buffer, low voltage to
+ *                         high voltage, isolated well
+ *                         on input buffer, inverting sleep
+ *                         mode input.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg (
+    X      ,
+    A      ,
+    SLEEP_B
+);
+
+    // Module ports
+    output X      ;
+    input  A      ;
+    input  SLEEP_B;
+
+    // Local signals
+    wire SLEEP     ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    not not0 (SLEEP     , SLEEP_B        );
+    and and0 (and0_out_X, SLEEP_B, A     );
+    buf buf0 (X         , and0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_DFF_PR_PP_PG_N_TB_V
+`define SKY130_FD_SC_HVL__UDP_DFF_PR_PP_PG_N_TB_V
+
+/**
+ * udp_dff$PR_pp$PG$N: Positive edge triggered D flip-flop with active
+ *                     high
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__udp_dff_pr_pp_pg_n.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg RESET;
+    reg NOTIFIER;
+    reg VPWR;
+    reg VGND;
+
+    // Outputs are wires
+    wire Q;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D        = 1\'bX;
+        NOTIFIER = 1\'bX;
+        RESET    = 1\'bX;
+        VGND     = 1\'bX;
+        VPWR     = 1\'bX;
+
+        #20   D        = 1\'b0;
+        #40   NOTIFIER = 1\'b0;
+        #60   RESET    = 1\'b0;
+        #80   VGND     = 1\'b0;
+        #100  VPWR     = 1\'b0;
+        #120  D        = 1\'b1;
+        #140  NOTIFIER = 1\'b1;
+        #160  RESET    = 1\'b1;
+        #180  VGND     = 1\'b1;
+        #200  VPWR     = 1\'b1;
+        #220  D        = 1\'b0;
+        #240  NOTIFIER = 1\'b0;
+        #260  RESET    = 1\'b0;
+        #280  VGND     = 1\'b0;
+        #300  VPWR     = 1\'b0;
+        #320  VPWR     = 1\'b1;
+        #340  VGND     = 1\'b1;
+        #360  RESET    = 1\'b1;
+        #380  NOTIFIER = 1\'b1;
+        #400  D        = 1\'b1;
+        #420  VPWR     = 1\'bx;
+        #440  VGND     = 1\'bx;
+        #460  RESET    = 1\'bx;
+        #480  NOTIFIER = 1\'bx;
+        #500  D        = 1\'bx;
+    end
+
+    // Create a clock
+    reg CLK;
+    initial
+    begin
+        CLK = 1\'b0;
+    end
+
+    always
+    begin
+        #5 CLK = ~CLK;
+    end
+
+    sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dut (.D(D), .RESET(RESET), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_DFF_PR_PP_PG_N_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__BUF_FUNCTIONAL_V
+`define SKY130_FD_SC_HVL__BUF_FUNCTIONAL_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__buf (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Local signals
+    wire buf0_out_X;
+
+    //  Name  Output      Other arguments
+    buf buf0 (buf0_out_X, A              );
+    buf buf1 (X         , buf0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__BUF_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__EINVN_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HVL__EINVN_FUNCTIONAL_PP_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__einvn (
+    Z   ,
+    A   ,
+    TE_B,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire pwrgood_pp0_out_A  ;
+    wire pwrgood_pp1_out_teb;
+
+    //                                  Name         Output               Other arguments
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A  , A, VPWR, VGND                         );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND                      );
+    notif0                              notif00     (Z                  , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__EINVN_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HVL__LSBUFLV2HV_BEHAVIORAL_PP_V
+
+/**
+ * lsbuflv2hv: Level-shift buffer, low voltage-to-high voltage,
+ *             isolated well on input buffer, double height cell.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__lsbuflv2hv (
+    X    ,
+    A    ,
+    VPWR ,
+    VGND ,
+    LVPWR,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output X    ;
+    input  A    ;
+    input  VPWR ;
+    input  VGND ;
+    input  LVPWR;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire pwrgood_pp0_out_A;
+    wire buf0_out_X       ;
+
+    //                                  Name         Output             Other arguments
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A, A, LVPWR, VGND        );
+    buf                                 buf0        (buf0_out_X       , pwrgood_pp0_out_A     );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (X                , buf0_out_X, VPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFLV2HV_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__BUF_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HVL__BUF_BEHAVIORAL_PP_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__buf (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                  Name         Output             Other arguments
+    buf                                 buf0        (buf0_out_X       , A                     );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
+    buf                                 buf1        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__BUF_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__EINVP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HVL__EINVP_BEHAVIORAL_PP_V
+
+/**
+ * einvp: Tri-state inverter, positive enable.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__einvp (
+    Z   ,
+    A   ,
+    TE  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Z   ;
+    input  A   ;
+    input  TE  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire pwrgood_pp0_out_A ;
+    wire pwrgood_pp1_out_TE;
+
+    //                                  Name         Output              Other arguments
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND                        );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_TE, TE, VPWR, VGND                       );
+    notif1                              notif10     (Z                 , pwrgood_pp0_out_A, pwrgood_pp1_out_TE);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__EINVP_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__BUF_2_V
+`define SKY130_FD_SC_HVL__BUF_2_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog wrapper for buf with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__buf.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__buf_2 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hvl__buf base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__buf_2 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hvl__buf base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__BUF_2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__DFSTP_BEHAVIORAL_V
+`define SKY130_FD_SC_HVL__DFSTP_BEHAVIORAL_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hvl__udp_dff_ps_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_hvl__dfstp (
+    Q    ,
+    CLK  ,
+    D    ,
+    SET_B
+);
+
+    // Module ports
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q        ;
+    wire SET          ;
+    reg  notifier     ;
+    wire cond0        ;
+    wire D_delayed    ;
+    wire SET_B_delayed;
+    wire CLK_delayed  ;
+
+    //                                   Name  Output  Other arguments
+    not                                  not0 (SET   , SET_B_delayed                                    );
+    sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
+    assign cond0 = ( SET_B_delayed === 1\'b1 );
+    buf                                  buf0 (Q     , buf_Q                                            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DFSTP_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__O21AI_V
+`define SKY130_FD_SC_HVL__O21AI_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & B1)
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__o21ai.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__o21ai.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__o21ai.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__o21ai.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__O21AI_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DIODE_V
+`define SKY130_FD_SC_HVL__DIODE_V
+
+/**
+ * diode: Antenna tie-down diode.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__diode.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__diode.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__diode.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__diode.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DIODE_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SDLXTP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__SDLXTP_BLACKBOX_V
+
+/**
+ * sdlxtp: ????.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__sdlxtp (
+    Q   ,
+    D   ,
+    SCD ,
+    SCE ,
+    GATE
+);
+
+    output Q   ;
+    input  D   ;
+    input  SCD ;
+    input  SCE ;
+    input  GATE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDLXTP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__BUF_SYMBOL_V
+`define SKY130_FD_SC_HVL__BUF_SYMBOL_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__buf (
+    //# {{data|Data Signals}}
+    input  A,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__BUF_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__SDFXTP_BEHAVIORAL_V
+`define SKY130_FD_SC_HVL__SDFXTP_BEHAVIORAL_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hvl__udp_dff_p_pp_pg_n.v""
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v""
+
+`celldefine
+module sky130_fd_sc_hvl__sdfxtp (
+    Q  ,
+    CLK,
+    D  ,
+    SCD,
+    SCE
+);
+
+    // Module ports
+    output Q  ;
+    input  CLK;
+    input  D  ;
+    input  SCD;
+    input  SCE;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q      ;
+    wire mux_out    ;
+    reg  notifier   ;
+    wire cond1      ;
+    wire cond2      ;
+    wire cond3      ;
+    wire D_delayed  ;
+    wire SCD_delayed;
+    wire SCE_delayed;
+    wire CLK_delayed;
+
+    //                                  Name       Output   Other arguments
+    sky130_fd_sc_hvl__udp_mux_2to1      mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed       );
+    sky130_fd_sc_hvl__udp_dff$P_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, notifier, VPWR, VGND);
+    assign cond1 = ( SCE_delayed === 1\'b0 );
+    assign cond2 = ( SCE_delayed === 1\'b1 );
+    assign cond3 = ( D_delayed !== SCD_delayed );
+    buf                                 buf0      (Q      , buf_Q                                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFXTP_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_DFF_PS_PP_PG_N_V
+`define SKY130_FD_SC_HVL__UDP_DFF_PS_PP_PG_N_V
+
+/**
+ * udp_dff$PS_pp$PG$N: Positive edge triggered D flip-flop with active
+ *                     high
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`include ""./sky130_fd_sc_hvl__udp_dff_ps_pp_pg_n.blackbox.v""
+`else
+primitive sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N (
+    Q       ,
+    D       ,
+    CLK     ,
+    SET     ,
+    NOTIFIER,
+    VPWR    ,
+    VGND
+);
+
+    output Q       ;
+    input  D       ;
+    input  CLK     ;
+    input  SET     ;
+    input  NOTIFIER;
+    input  VPWR    ;
+    input  VGND    ;
+
+    reg Q;
+
+    table
+     //          D           CLK  SET  NOTIFIER VPWR VGND :  Qt : Qt+1
+                 *            b    0      ?      1    0   :  ?  :  -    ; // data event, hold unless CP==x
+                 ?           (?0)  0      ?      1    0   :  ?  :  -    ; // CP => 0, hold
+                 ?            b   (?0)    ?      1    0   :  ?  :  -    ; // S => 0, hold unless CP==x
+                 ?            ?    1      ?      1    0   :  ?  :  1    ; // async set
+                 0            r    0      ?      1    0   :  ?  :  0    ; // clock data on CP
+                 1            r    ?      ?      1    0   :  ?  :  1    ; // clock data on CP
+                 0           (x1)  0      ?      1    0   :  0  :  0    ; // possible CP, hold when D==Q==0
+                 1           (x1)  ?      ?      1    0   :  1  :  1    ; // possible CP, hold when D==Q==1
+                 0            x    0      ?      1    0   :  0  :  0    ; // unkown CP, hold when D==Q==0
+                 1            x    ?      ?      1    0   :  1  :  1    ; // unkown CP, hold when D==Q==1
+                 ?            b   (?x)    ?      1    0   :  1  :  1    ; // S=>x, hold when Q==1 unless CP==x
+                 ?            f    x      ?      1    0   :  1  :  1    ; // JCWR reducing pessimism
+        // [\'IfDef(functional)\', \'\']                 ?            ?    ?      *      1    0   :  ?  :  -    ; // ignore notifier
+        // [\'Else\', \'\']                 ?            ?    ?      *      1    0   :  ?  :  x    ; // Q => X on any change on notifier
+        // [\'EndIfDef(functional)\', \'\']                 ?            ?    ?      ?      *    ?   :  ?  :  x    ; // Q => X on any change on vpwr
+                 ?            ?    ?      ?      ?    *   :  ?  :  x    ; // Q => X on any change on vgnd
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_DFF_PS_PP_PG_N_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__SDFSBP_FUNCTIONAL_V
+`define SKY130_FD_SC_HVL__SDFSBP_FUNCTIONAL_V
+
+/**
+ * sdfsbp: Scan delay flop, inverted set, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v""
+`include ""../../models/udp_dff_ps/sky130_fd_sc_hvl__udp_dff_ps.v""
+
+`celldefine
+module sky130_fd_sc_hvl__sdfsbp (
+    Q    ,
+    Q_N  ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B
+);
+
+    // Module ports
+    output Q    ;
+    output Q_N  ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+
+    // Local signals
+    wire buf_Q  ;
+    wire SET    ;
+    wire mux_out;
+
+    //                             Delay       Name       Output   Other arguments
+    not                                        not0      (SET    , SET_B            );
+    sky130_fd_sc_hvl__udp_mux_2to1             mux_2to10 (mux_out, D, SCD, SCE      );
+    sky130_fd_sc_hvl__udp_dff$PS   `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK, SET);
+    buf                                        buf0      (Q      , buf_Q            );
+    not                                        not1      (Q_N    , buf_Q            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFSBP_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__OR3_BEHAVIORAL_V
+`define SKY130_FD_SC_HVL__OR3_BEHAVIORAL_V
+
+/**
+ * or3: 3-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__or3 (
+    X,
+    A,
+    B,
+    C
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    or  or0  (or0_out_X, B, A, C        );
+    buf buf0 (X        , or0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__OR3_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_DLATCH_PR_PP_PG_N_SYMBOL_V
+`define SKY130_FD_SC_HVL__UDP_DLATCH_PR_PP_PG_N_SYMBOL_V
+
+/**
+ * udp_dlatch$PR_pp$PG$N: D-latch, gated clear direct / gate active
+ *                        high (Q output UDP)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__udp_dlatch$PR_pp$PG$N (
+    //# {{data|Data Signals}}
+    input  D       ,
+    output Q       ,
+
+    //# {{control|Control Signals}}
+    input  RESET   ,
+
+    //# {{clocks|Clocking}}
+    input  GATE    ,
+
+    //# {{power|Power}}
+    input  NOTIFIER,
+    input  VPWR    ,
+    input  VGND
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_DLATCH_PR_PP_PG_N_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SDFXBP_TB_V
+`define SKY130_FD_SC_HVL__SDFXBP_TB_V
+
+/**
+ * sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__sdfxbp.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg SCD;
+    reg SCE;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Q;
+    wire Q_N;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D    = 1\'bX;
+        SCD  = 1\'bX;
+        SCE  = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   D    = 1\'b0;
+        #40   SCD  = 1\'b0;
+        #60   SCE  = 1\'b0;
+        #80   VGND = 1\'b0;
+        #100  VNB  = 1\'b0;
+        #120  VPB  = 1\'b0;
+        #140  VPWR = 1\'b0;
+        #160  D    = 1\'b1;
+        #180  SCD  = 1\'b1;
+        #200  SCE  = 1\'b1;
+        #220  VGND = 1\'b1;
+        #240  VNB  = 1\'b1;
+        #260  VPB  = 1\'b1;
+        #280  VPWR = 1\'b1;
+        #300  D    = 1\'b0;
+        #320  SCD  = 1\'b0;
+        #340  SCE  = 1\'b0;
+        #360  VGND = 1\'b0;
+        #380  VNB  = 1\'b0;
+        #400  VPB  = 1\'b0;
+        #420  VPWR = 1\'b0;
+        #440  VPWR = 1\'b1;
+        #460  VPB  = 1\'b1;
+        #480  VNB  = 1\'b1;
+        #500  VGND = 1\'b1;
+        #520  SCE  = 1\'b1;
+        #540  SCD  = 1\'b1;
+        #560  D    = 1\'b1;
+        #580  VPWR = 1\'bx;
+        #600  VPB  = 1\'bx;
+        #620  VNB  = 1\'bx;
+        #640  VGND = 1\'bx;
+        #660  SCE  = 1\'bx;
+        #680  SCD  = 1\'bx;
+        #700  D    = 1\'bx;
+    end
+
+    // Create a clock
+    reg CLK;
+    initial
+    begin
+        CLK = 1\'b0;
+    end
+
+    always
+    begin
+        #5 CLK = ~CLK;
+    end
+
+    sky130_fd_sc_hvl__sdfxbp dut (.D(D), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFXBP_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__CONB_SYMBOL_V
+`define SKY130_FD_SC_HVL__CONB_SYMBOL_V
+
+/**
+ * conb: Constant value, low, high outputs.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__conb (
+    //# {{data|Data Signals}}
+    output HI,
+    output LO
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__CONB_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__NOR2_BEHAVIORAL_V
+`define SKY130_FD_SC_HVL__NOR2_BEHAVIORAL_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__nor2 (
+    Y,
+    A,
+    B
+);
+
+    // Module ports
+    output Y;
+    input  A;
+    input  B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    nor nor0 (nor0_out_Y, A, B           );
+    buf buf0 (Y         , nor0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__NOR2_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SDFRBP_SYMBOL_V
+`define SKY130_FD_SC_HVL__SDFRBP_SYMBOL_V
+
+/**
+ * sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__sdfrbp (
+    //# {{data|Data Signals}}
+    input  D      ,
+    output Q      ,
+    output Q_N    ,
+
+    //# {{control|Control Signals}}
+    input  RESET_B,
+
+    //# {{scanchain|Scan Chain}}
+    input  SCD    ,
+    input  SCE    ,
+
+    //# {{clocks|Clocking}}
+    input  CLK
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFRBP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__O22A_FUNCTIONAL_V
+`define SKY130_FD_SC_HVL__O22A_FUNCTIONAL_V
+
+/**
+ * o22a: 2-input OR into both inputs of 2-input AND.
+ *
+ *       X = ((A1 | A2) & (B1 | B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__o22a (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    // Module ports
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Local signals
+    wire or0_out   ;
+    wire or1_out   ;
+    wire and0_out_X;
+
+    //  Name  Output      Other arguments
+    or  or0  (or0_out   , A2, A1          );
+    or  or1  (or1_out   , B2, B1          );
+    and and0 (and0_out_X, or0_out, or1_out);
+    buf buf0 (X         , and0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__O22A_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_DFF_P_PP_PG_N_BLACKBOX_V
+`define SKY130_FD_SC_HVL__UDP_DFF_P_PP_PG_N_BLACKBOX_V
+
+/**
+ * udp_dff$P_pp$PG$N: Positive edge triggered D flip-flop
+ *                    (Q output UDP).
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__udp_dff$P_pp$PG$N (
+    Q       ,
+    D       ,
+    CLK     ,
+    NOTIFIER,
+    VPWR    ,
+    VGND
+);
+
+    output Q       ;
+    input  D       ;
+    input  CLK     ;
+    input  NOTIFIER;
+    input  VPWR    ;
+    input  VGND    ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_DFF_P_PP_PG_N_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__PROBE_P_8_V
+`define SKY130_FD_SC_HVL__PROBE_P_8_V
+
+/**
+ * probe_p: Virtual voltage probe point.
+ *
+ * Verilog wrapper for probe_p with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__probe_p.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__probe_p_8 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hvl__probe_p base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__probe_p_8 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hvl__probe_p base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__PROBE_P_8_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_HL_FUNCTIONAL_V
+`define SKY130_FD_SC_HVL__LSBUFHV2HV_HL_FUNCTIONAL_V
+
+/**
+ * lsbufhv2hv_hl: Level shifting buffer, High Voltage to High Voltage,
+ *                Higher Voltage to Lower Voltage.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__lsbufhv2hv_hl (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    //  Name  Output  Other arguments
+    buf buf0 (X     , A              );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFHV2HV_HL_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DFRTP_PP_SYMBOL_V
+`define SKY130_FD_SC_HVL__DFRTP_PP_SYMBOL_V
+
+/**
+ * dfrtp: Delay flop, inverted reset, single output.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__dfrtp (
+    //# {{data|Data Signals}}
+    input  D      ,
+    output Q      ,
+
+    //# {{control|Control Signals}}
+    input  RESET_B,
+
+    //# {{clocks|Clocking}}
+    input  CLK    ,
+
+    //# {{power|Power}}
+    input  VPB    ,
+    input  VPWR   ,
+    input  VGND   ,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DFRTP_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__SDLCLKP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HVL__SDLCLKP_FUNCTIONAL_PP_V
+
+/**
+ * sdlclkp: Scan gated clock.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+`include ""../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hvl__udp_dlatch_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_hvl__sdlclkp (
+    GCLK,
+    SCE ,
+    GATE,
+    CLK ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output GCLK;
+    input  SCE ;
+    input  GATE;
+    input  CLK ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire m0      ;
+    wire m0n     ;
+    wire clkn    ;
+    wire SCE_GATE;
+    wire GCLK_b  ;
+
+    //                                     Name         Output    Other arguments
+    not                                    not0        (m0n     , m0                          );
+    not                                    not1        (clkn    , CLK                         );
+    nor                                    nor0        (SCE_GATE, GATE, SCE                   );
+    sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0     (m0      , SCE_GATE, clkn, , VPWR, VGND);
+    and                                    and0        (GCLK_b  , m0n, CLK                    );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG    pwrgood_pp0 (GCLK    , GCLK_b, VPWR, VGND          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDLCLKP_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__O21AI_BLACKBOX_V
+`define SKY130_FD_SC_HVL__O21AI_BLACKBOX_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & B1)
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__o21ai (
+    Y ,
+    A1,
+    A2,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__O21AI_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__DLRTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HVL__DLRTP_BEHAVIORAL_PP_V
+
+/**
+ * dlrtp: Delay latch, inverted reset, non-inverted enable,
+ *        single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_hvl__udp_dlatch_pr_pp_pg_n.v""
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__dlrtp (
+    Q      ,
+    RESET_B,
+    D      ,
+    GATE   ,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    input  RESET_B;
+    input  D      ;
+    input  GATE   ;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire RESET          ;
+    reg  notifier       ;
+    wire cond0          ;
+    wire D_delayed      ;
+    wire GATE_delayed   ;
+    wire RESET_delayed  ;
+    wire RESET_B_delayed;
+    wire buf_Q          ;
+    wire buf0_out_Q     ;
+
+    //                                      Name         Output      Other arguments
+    not                                     not0        (RESET     , RESET_B_delayed                                     );
+    sky130_fd_sc_hvl__udp_dlatch$PR_pp$PG$N dlatch0     (buf_Q     , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
+    assign cond0 = ( RESET_B_delayed === 1\'b1 );
+    buf                                     buf0        (buf0_out_Q, buf_Q                                               );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG     pwrgood_pp0 (Q         , buf0_out_Q, VPWR, VGND                              );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DLRTP_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DFRTP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__DFRTP_BLACKBOX_V
+
+/**
+ * dfrtp: Delay flop, inverted reset, single output.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__dfrtp (
+    Q      ,
+    CLK    ,
+    D      ,
+    RESET_B
+);
+
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DFRTP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__INV_8_V
+`define SKY130_FD_SC_HVL__INV_8_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog wrapper for inv with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__inv.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__inv_8 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hvl__inv base (
+        .Y(Y),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__inv_8 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hvl__inv base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__INV_8_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_DFF_P_TB_V
+`define SKY130_FD_SC_HVL__UDP_DFF_P_TB_V
+
+/**
+ * udp_dff$P: Positive edge triggered D flip-flop (Q output UDP).
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__udp_dff_p.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+
+    // Outputs are wires
+    wire Q;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D = 1\'bX;
+
+        #20   D = 1\'b0;
+        #40   D = 1\'b1;
+        #60   D = 1\'b0;
+        #80   D = 1\'b1;
+        #100  D = 1\'bx;
+    end
+
+    // Create a clock
+    reg CLK;
+    initial
+    begin
+        CLK = 1\'b0;
+    end
+
+    always
+    begin
+        #5 CLK = ~CLK;
+    end
+
+    sky130_fd_sc_hvl__udp_dff$P dut (.D(D), .Q(Q), .CLK(CLK));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_DFF_P_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_1_V
+`define SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_1_V
+
+/**
+ * lsbufhv2lv_simple: Level shifting buffer, High Voltage to Low
+ *                    Voltage, simple (hv devices in inverters on lv
+ *                    power rail).
+ *
+ * Verilog wrapper for lsbufhv2lv_simple with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__lsbufhv2lv_simple.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__lsbufhv2lv_simple_1 (
+    X    ,
+    A    ,
+    VPWR ,
+    VGND ,
+    LVPWR,
+    VPB  ,
+    VNB
+);
+
+    output X    ;
+    input  A    ;
+    input  VPWR ;
+    input  VGND ;
+    input  LVPWR;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hvl__lsbufhv2lv_simple base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .LVPWR(LVPWR),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__lsbufhv2lv_simple_1 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR ;
+    supply0 VGND ;
+    supply1 LVPWR;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+    sky130_fd_sc_hvl__lsbufhv2lv_simple base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__OR3_TB_V
+`define SKY130_FD_SC_HVL__OR3_TB_V
+
+/**
+ * or3: 3-input OR.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__or3.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg B;
+    reg C;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        B    = 1\'bX;
+        C    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   B    = 1\'b0;
+        #60   C    = 1\'b0;
+        #80   VGND = 1\'b0;
+        #100  VNB  = 1\'b0;
+        #120  VPB  = 1\'b0;
+        #140  VPWR = 1\'b0;
+        #160  A    = 1\'b1;
+        #180  B    = 1\'b1;
+        #200  C    = 1\'b1;
+        #220  VGND = 1\'b1;
+        #240  VNB  = 1\'b1;
+        #260  VPB  = 1\'b1;
+        #280  VPWR = 1\'b1;
+        #300  A    = 1\'b0;
+        #320  B    = 1\'b0;
+        #340  C    = 1\'b0;
+        #360  VGND = 1\'b0;
+        #380  VNB  = 1\'b0;
+        #400  VPB  = 1\'b0;
+        #420  VPWR = 1\'b0;
+        #440  VPWR = 1\'b1;
+        #460  VPB  = 1\'b1;
+        #480  VNB  = 1\'b1;
+        #500  VGND = 1\'b1;
+        #520  C    = 1\'b1;
+        #540  B    = 1\'b1;
+        #560  A    = 1\'b1;
+        #580  VPWR = 1\'bx;
+        #600  VPB  = 1\'bx;
+        #620  VNB  = 1\'bx;
+        #640  VGND = 1\'bx;
+        #660  C    = 1\'bx;
+        #680  B    = 1\'bx;
+        #700  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_hvl__or3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__OR3_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DECAP_V
+`define SKY130_FD_SC_HVL__DECAP_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__decap.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__decap.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__decap.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__decap.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DECAP_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__DFXBP_FUNCTIONAL_V
+`define SKY130_FD_SC_HVL__DFXBP_FUNCTIONAL_V
+
+/**
+ * dfxbp: Delay flop, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_p/sky130_fd_sc_hvl__udp_dff_p.v""
+
+`celldefine
+module sky130_fd_sc_hvl__dfxbp (
+    Q  ,
+    Q_N,
+    CLK,
+    D
+);
+
+    // Module ports
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+
+    // Local signals
+    wire buf_Q;
+
+    //                          Delay       Name  Output  Other arguments
+    sky130_fd_sc_hvl__udp_dff$P `UNIT_DELAY dff0 (buf_Q , D, CLK         );
+    buf                                     buf0 (Q     , buf_Q          );
+    not                                     not0 (Q_N   , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DFXBP_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__SDLXTP_FUNCTIONAL_V
+`define SKY130_FD_SC_HVL__SDLXTP_FUNCTIONAL_V
+
+/**
+ * sdlxtp: ????.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v""
+`include ""../../models/udp_dlatch_p/sky130_fd_sc_hvl__udp_dlatch_p.v""
+
+`celldefine
+module sky130_fd_sc_hvl__sdlxtp (
+    Q   ,
+    D   ,
+    SCD ,
+    SCE ,
+    GATE
+);
+
+    // Module ports
+    output Q   ;
+    input  D   ;
+    input  SCD ;
+    input  SCE ;
+    input  GATE;
+
+    // Local signals
+    wire mux_out;
+    wire buf_Q  ;
+
+    //                             Delay       Name       Output   Other arguments
+    sky130_fd_sc_hvl__udp_mux_2to1             mux_2to10 (mux_out, D, SCD, SCE    );
+    sky130_fd_sc_hvl__udp_dlatch$P `UNIT_DELAY dlatch0   (buf_Q  , mux_out, GATE  );
+    buf                                        buf0      (Q      , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDLXTP_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DECAP_8_V
+`define SKY130_FD_SC_HVL__DECAP_8_V
+
+/**
+ * decap: Decoupling capacitance filler.
+ *
+ * Verilog wrapper for decap with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__decap.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__decap_8 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+    sky130_fd_sc_hvl__decap base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__decap_8 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hvl__decap base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DECAP_8_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__A22OI_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HVL__A22OI_FUNCTIONAL_PP_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__a22oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out        ;
+    wire nand1_out        ;
+    wire and0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                  Name         Output             Other arguments
+    nand                                nand0       (nand0_out        , A2, A1                );
+    nand                                nand1       (nand1_out        , B2, B1                );
+    and                                 and0        (and0_out_Y       , nand0_out, nand1_out  );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
+    buf                                 buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__A22OI_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DFRBP_V
+`define SKY130_FD_SC_HVL__DFRBP_V
+
+/**
+ * dfrbp: Delay flop, inverted reset, complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__dfrbp.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__dfrbp.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__dfrbp.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__dfrbp.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DFRBP_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_1_V
+`define SKY130_FD_SC_HVL__LSBUFHV2LV_1_V
+
+/**
+ * lsbufhv2lv: Level-shift buffer, low voltage-to-low voltage.
+ *
+ * Verilog wrapper for lsbufhv2lv with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__lsbufhv2lv.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__lsbufhv2lv_1 (
+    X    ,
+    A    ,
+    VPWR ,
+    VGND ,
+    LVPWR,
+    VPB  ,
+    VNB
+);
+
+    output X    ;
+    input  A    ;
+    input  VPWR ;
+    input  VGND ;
+    input  LVPWR;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hvl__lsbufhv2lv base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .LVPWR(LVPWR),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__lsbufhv2lv_1 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR ;
+    supply0 VGND ;
+    supply1 LVPWR;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+    sky130_fd_sc_hvl__lsbufhv2lv base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFHV2LV_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SDFRTP_PP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__SDFRTP_PP_BLACKBOX_V
+
+/**
+ * sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
+ *         single output.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__sdfrtp (
+    Q      ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFRTP_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_HL_1_V
+`define SKY130_FD_SC_HVL__LSBUFHV2HV_HL_1_V
+
+/**
+ * lsbufhv2hv_hl: Level shifting buffer, High Voltage to High Voltage,
+ *                Higher Voltage to Lower Voltage.
+ *
+ * Verilog wrapper for lsbufhv2hv_hl with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__lsbufhv2hv_hl.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__lsbufhv2hv_hl_1 (
+    X       ,
+    A       ,
+    VPWR    ,
+    VGND    ,
+    LOWHVPWR,
+    VPB     ,
+    VNB
+);
+
+    output X       ;
+    input  A       ;
+    input  VPWR    ;
+    input  VGND    ;
+    input  LOWHVPWR;
+    input  VPB     ;
+    input  VNB     ;
+    sky130_fd_sc_hvl__lsbufhv2hv_hl base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .LOWHVPWR(LOWHVPWR),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__lsbufhv2hv_hl_1 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR    ;
+    supply0 VGND    ;
+    supply1 LOWHVPWR;
+    supply1 VPB     ;
+    supply0 VNB     ;
+
+    sky130_fd_sc_hvl__lsbufhv2hv_hl base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFHV2HV_HL_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__SDLXTP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HVL__SDLXTP_FUNCTIONAL_PP_V
+
+/**
+ * sdlxtp: ????.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v""
+`include ""../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hvl__udp_dlatch_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_hvl__sdlxtp (
+    Q   ,
+    D   ,
+    SCD ,
+    SCE ,
+    GATE,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    input  D   ;
+    input  SCD ;
+    input  SCE ;
+    input  GATE;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire mux_out   ;
+    wire buf_Q     ;
+    wire buf0_out_Q;
+
+    //                                     Delay       Name         Output      Other arguments
+    sky130_fd_sc_hvl__udp_mux_2to1                     mux_2to10   (mux_out   , D, SCD, SCE                );
+    sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N `UNIT_DELAY dlatch0     (buf_Q     , mux_out, GATE, , VPWR, VGND);
+    buf                                                buf0        (buf0_out_Q, buf_Q                      );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG                pwrgood_pp0 (Q         , buf0_out_Q, VPWR, VGND     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDLXTP_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__O21A_PP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__O21A_PP_BLACKBOX_V
+
+/**
+ * o21a: 2-input OR into first input of 2-input AND.
+ *
+ *       X = ((A1 | A2) & B1)
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__o21a (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__O21A_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__INV_2_V
+`define SKY130_FD_SC_HVL__INV_2_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog wrapper for inv with size of 2 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__inv.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__inv_2 (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hvl__inv base (
+        .Y(Y),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__inv_2 (
+    Y,
+    A
+);
+
+    output Y;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hvl__inv base (
+        .Y(Y),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__INV_2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__DFXTP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HVL__DFXTP_FUNCTIONAL_PP_V
+
+/**
+ * dfxtp: Delay flop, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hvl__udp_dff_p_pp_pg_n.v""
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__dfxtp (
+    Q   ,
+    CLK ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q     ;
+    wire buf0_out_Q;
+
+    //                                  Delay       Name         Output      Other arguments
+    sky130_fd_sc_hvl__udp_dff$P_pp$PG$N `UNIT_DELAY dff0        (buf_Q     , D, CLK, , VPWR, VGND  );
+    buf                                             buf0        (buf0_out_Q, buf_Q                 );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG             pwrgood_pp0 (Q         , buf0_out_Q, VPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DFXTP_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_PP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__LSBUFHV2LV_PP_BLACKBOX_V
+
+/**
+ * lsbufhv2lv: Level-shift buffer, low voltage-to-low voltage.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__lsbufhv2lv (
+    X    ,
+    A    ,
+    VPWR ,
+    VGND ,
+    LVPWR,
+    VPB  ,
+    VNB
+);
+
+    output X    ;
+    input  A    ;
+    input  VPWR ;
+    input  VGND ;
+    input  LVPWR;
+    input  VPB  ;
+    input  VNB  ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFHV2LV_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_PP_SYMBOL_V
+`define SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_PP_SYMBOL_V
+
+/**
+ * lsbuflv2hv_symmetric: Level shifting buffer, Low Voltage to High
+ *                       Voltage, Symmetrical.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__lsbuflv2hv_symmetric (
+    //# {{data|Data Signals}}
+    input  A    ,
+    output X    ,
+
+    //# {{power|Power}}
+    input  LVPWR,
+    input  VPB  ,
+    input  VPWR ,
+    input  VGND ,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__MUX4_PP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__MUX4_PP_BLACKBOX_V
+
+/**
+ * mux4: 4-input multiplexer.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__mux4 (
+    X   ,
+    A0  ,
+    A1  ,
+    A2  ,
+    A3  ,
+    S0  ,
+    S1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A0  ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  S0  ;
+    input  S1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__MUX4_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_G_SYMBOL_V
+`define SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_G_SYMBOL_V
+
+/**
+
+ *   UDP_OUT :=x when VPWR!=1
+ *   UDP_OUT :=UDP_IN when VPWR==1
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__udp_pwrgood_pp$G (
+    //# {{data|Data Signals}}
+    input  UDP_IN ,
+    output UDP_OUT,
+
+    //# {{power|Power}}
+    input  VGND
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_G_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SDLXTP_PP_SYMBOL_V
+`define SKY130_FD_SC_HVL__SDLXTP_PP_SYMBOL_V
+
+/**
+ * sdlxtp: ????.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__sdlxtp (
+    //# {{data|Data Signals}}
+    input  D   ,
+    output Q   ,
+
+    //# {{scanchain|Scan Chain}}
+    input  SCD ,
+    input  SCE ,
+
+    //# {{clocks|Clocking}}
+    input  GATE,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDLXTP_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SDFSBP_TB_V
+`define SKY130_FD_SC_HVL__SDFSBP_TB_V
+
+/**
+ * sdfsbp: Scan delay flop, inverted set, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__sdfsbp.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg SCD;
+    reg SCE;
+    reg SET_B;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Q;
+    wire Q_N;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D     = 1\'bX;
+        SCD   = 1\'bX;
+        SCE   = 1\'bX;
+        SET_B = 1\'bX;
+        VGND  = 1\'bX;
+        VNB   = 1\'bX;
+        VPB   = 1\'bX;
+        VPWR  = 1\'bX;
+
+        #20   D     = 1\'b0;
+        #40   SCD   = 1\'b0;
+        #60   SCE   = 1\'b0;
+        #80   SET_B = 1\'b0;
+        #100  VGND  = 1\'b0;
+        #120  VNB   = 1\'b0;
+        #140  VPB   = 1\'b0;
+        #160  VPWR  = 1\'b0;
+        #180  D     = 1\'b1;
+        #200  SCD   = 1\'b1;
+        #220  SCE   = 1\'b1;
+        #240  SET_B = 1\'b1;
+        #260  VGND  = 1\'b1;
+        #280  VNB   = 1\'b1;
+        #300  VPB   = 1\'b1;
+        #320  VPWR  = 1\'b1;
+        #340  D     = 1\'b0;
+        #360  SCD   = 1\'b0;
+        #380  SCE   = 1\'b0;
+        #400  SET_B = 1\'b0;
+        #420  VGND  = 1\'b0;
+        #440  VNB   = 1\'b0;
+        #460  VPB   = 1\'b0;
+        #480  VPWR  = 1\'b0;
+        #500  VPWR  = 1\'b1;
+        #520  VPB   = 1\'b1;
+        #540  VNB   = 1\'b1;
+        #560  VGND  = 1\'b1;
+        #580  SET_B = 1\'b1;
+        #600  SCE   = 1\'b1;
+        #620  SCD   = 1\'b1;
+        #640  D     = 1\'b1;
+        #660  VPWR  = 1\'bx;
+        #680  VPB   = 1\'bx;
+        #700  VNB   = 1\'bx;
+        #720  VGND  = 1\'bx;
+        #740  SET_B = 1\'bx;
+        #760  SCE   = 1\'bx;
+        #780  SCD   = 1\'bx;
+        #800  D     = 1\'bx;
+    end
+
+    // Create a clock
+    reg CLK;
+    initial
+    begin
+        CLK = 1\'b0;
+    end
+
+    always
+    begin
+        #5 CLK = ~CLK;
+    end
+
+    sky130_fd_sc_hvl__sdfsbp dut (.D(D), .SCD(SCD), .SCE(SCE), .SET_B(SET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFSBP_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__DFRBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HVL__DFRBP_FUNCTIONAL_PP_V
+
+/**
+ * dfrbp: Delay flop, inverted reset, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hvl__udp_dff_pr_pp_pg_n.v""
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__dfrbp (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire buf_Q      ;
+    wire RESET      ;
+    wire buf0_out_Q ;
+    wire not1_out_qn;
+
+    //                                   Delay       Name         Output       Other arguments
+    not                                              not0        (RESET      , RESET_B                    );
+    sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0        (buf_Q      , D, CLK, RESET, , VPWR, VGND);
+    buf                                              buf0        (buf0_out_Q , buf_Q                      );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG              pwrgood_pp0 (Q          , buf0_out_Q, VPWR, VGND     );
+    not                                              not1        (not1_out_qn, buf_Q                      );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG              pwrgood_pp1 (Q_N        , not1_out_qn, VPWR, VGND    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DFRBP_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SDFSBP_PP_SYMBOL_V
+`define SKY130_FD_SC_HVL__SDFSBP_PP_SYMBOL_V
+
+/**
+ * sdfsbp: Scan delay flop, inverted set, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__sdfsbp (
+    //# {{data|Data Signals}}
+    input  D    ,
+    output Q    ,
+    output Q_N  ,
+
+    //# {{control|Control Signals}}
+    input  SET_B,
+
+    //# {{scanchain|Scan Chain}}
+    input  SCD  ,
+    input  SCE  ,
+
+    //# {{clocks|Clocking}}
+    input  CLK  ,
+
+    //# {{power|Power}}
+    input  VPB  ,
+    input  VPWR ,
+    input  VGND ,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFSBP_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_HL_BEHAVIORAL_V
+`define SKY130_FD_SC_HVL__LSBUFHV2HV_HL_BEHAVIORAL_V
+
+/**
+ * lsbufhv2hv_hl: Level shifting buffer, High Voltage to High Voltage,
+ *                Higher Voltage to Lower Voltage.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__lsbufhv2hv_hl (
+    X,
+    A
+);
+
+    // Module ports
+    output X;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR    ;
+    supply0 VGND    ;
+    supply1 LOWHVPWR;
+    supply1 VPB     ;
+    supply0 VNB     ;
+
+    //  Name  Output  Other arguments
+    buf buf0 (X     , A              );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFHV2HV_HL_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__NOR2_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HVL__NOR2_FUNCTIONAL_PP_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__nor2 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                  Name         Output             Other arguments
+    nor                                 nor0        (nor0_out_Y       , A, B                  );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                 buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__NOR2_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SDFXBP_V
+`define SKY130_FD_SC_HVL__SDFXBP_V
+
+/**
+ * sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__sdfxbp.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__sdfxbp.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__sdfxbp.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__sdfxbp.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFXBP_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if ((!B)) (A +=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
+if ((B)) (A -=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
+if ((!A)) (B +=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
+if ((A)) (B -=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__INV_SYMBOL_V
+`define SKY130_FD_SC_HVL__INV_SYMBOL_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__inv (
+    //# {{data|Data Signals}}
+    input  A,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__INV_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_ISOLATCHHV_PP_PLG_S_TB_V
+`define SKY130_FD_SC_HVL__UDP_ISOLATCHHV_PP_PLG_S_TB_V
+
+/**
+ * udp_isolatchhv_pp$PLG$S: Power isolating latch (for HV). Includes
+ *                          VPWR, LVPWR, and VGND power pins with
+ *                          active high sleep pin (SLEEP).
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__udp_isolatchhv_pp_plg_s.v""
+
+module top();
+
+    // Inputs are registered
+    reg UDP_IN;
+    reg VPWR;
+    reg LVPWR;
+    reg VGND;
+    reg SLEEP;
+
+    // Outputs are wires
+    wire UDP_OUT;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        LVPWR  = 1\'bX;
+        SLEEP  = 1\'bX;
+        UDP_IN = 1\'bX;
+        VGND   = 1\'bX;
+        VPWR   = 1\'bX;
+
+        #20   LVPWR  = 1\'b0;
+        #40   SLEEP  = 1\'b0;
+        #60   UDP_IN = 1\'b0;
+        #80   VGND   = 1\'b0;
+        #100  VPWR   = 1\'b0;
+        #120  LVPWR  = 1\'b1;
+        #140  SLEEP  = 1\'b1;
+        #160  UDP_IN = 1\'b1;
+        #180  VGND   = 1\'b1;
+        #200  VPWR   = 1\'b1;
+        #220  LVPWR  = 1\'b0;
+        #240  SLEEP  = 1\'b0;
+        #260  UDP_IN = 1\'b0;
+        #280  VGND   = 1\'b0;
+        #300  VPWR   = 1\'b0;
+        #320  VPWR   = 1\'b1;
+        #340  VGND   = 1\'b1;
+        #360  UDP_IN = 1\'b1;
+        #380  SLEEP  = 1\'b1;
+        #400  LVPWR  = 1\'b1;
+        #420  VPWR   = 1\'bx;
+        #440  VGND   = 1\'bx;
+        #460  UDP_IN = 1\'bx;
+        #480  SLEEP  = 1\'bx;
+        #500  LVPWR  = 1\'bx;
+    end
+
+    sky130_fd_sc_hvl__udp_isolatchhv_pp$PLG$S dut (.UDP_IN(UDP_IN), .VPWR(VPWR), .LVPWR(LVPWR), .VGND(VGND), .SLEEP(SLEEP), .UDP_OUT(UDP_OUT));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_ISOLATCHHV_PP_PLG_S_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__A22OI_BLACKBOX_V
+`define SKY130_FD_SC_HVL__A22OI_BLACKBOX_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__a22oi (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__A22OI_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__A22O_TB_V
+`define SKY130_FD_SC_HVL__A22O_TB_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ *       X = ((A1 & A2) | (B1 & B2))
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__a22o.v""
+
+module top();
+
+    // Inputs are registered
+    reg A1;
+    reg A2;
+    reg B1;
+    reg B2;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A1   = 1\'bX;
+        A2   = 1\'bX;
+        B1   = 1\'bX;
+        B2   = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A1   = 1\'b0;
+        #40   A2   = 1\'b0;
+        #60   B1   = 1\'b0;
+        #80   B2   = 1\'b0;
+        #100  VGND = 1\'b0;
+        #120  VNB  = 1\'b0;
+        #140  VPB  = 1\'b0;
+        #160  VPWR = 1\'b0;
+        #180  A1   = 1\'b1;
+        #200  A2   = 1\'b1;
+        #220  B1   = 1\'b1;
+        #240  B2   = 1\'b1;
+        #260  VGND = 1\'b1;
+        #280  VNB  = 1\'b1;
+        #300  VPB  = 1\'b1;
+        #320  VPWR = 1\'b1;
+        #340  A1   = 1\'b0;
+        #360  A2   = 1\'b0;
+        #380  B1   = 1\'b0;
+        #400  B2   = 1\'b0;
+        #420  VGND = 1\'b0;
+        #440  VNB  = 1\'b0;
+        #460  VPB  = 1\'b0;
+        #480  VPWR = 1\'b0;
+        #500  VPWR = 1\'b1;
+        #520  VPB  = 1\'b1;
+        #540  VNB  = 1\'b1;
+        #560  VGND = 1\'b1;
+        #580  B2   = 1\'b1;
+        #600  B1   = 1\'b1;
+        #620  A2   = 1\'b1;
+        #640  A1   = 1\'b1;
+        #660  VPWR = 1\'bx;
+        #680  VPB  = 1\'bx;
+        #700  VNB  = 1\'bx;
+        #720  VGND = 1\'bx;
+        #740  B2   = 1\'bx;
+        #760  B1   = 1\'bx;
+        #780  A2   = 1\'bx;
+        #800  A1   = 1\'bx;
+    end
+
+    sky130_fd_sc_hvl__a22o dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__A22O_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_DFF_PR_BLACKBOX_V
+`define SKY130_FD_SC_HVL__UDP_DFF_PR_BLACKBOX_V
+
+/**
+ * udp_dff$PR: Positive edge triggered D flip-flop with active high
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__udp_dff$PR (
+    Q    ,
+    D    ,
+    CLK  ,
+    RESET
+);
+
+    output Q    ;
+    input  D    ;
+    input  CLK  ;
+    input  RESET;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_DFF_PR_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__A22OI_PP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__A22OI_PP_BLACKBOX_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__a22oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    B2  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  B2  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__A22OI_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__FILL_8_V
+`define SKY130_FD_SC_HVL__FILL_8_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog wrapper for fill with size of 8 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__fill.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__fill_8 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+    sky130_fd_sc_hvl__fill base (
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__fill_8 ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hvl__fill base ();
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__FILL_8_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DLXTP_1_V
+`define SKY130_FD_SC_HVL__DLXTP_1_V
+
+/**
+ * dlxtp: Delay latch, non-inverted enable, single output.
+ *
+ * Verilog wrapper for dlxtp with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__dlxtp.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__dlxtp_1 (
+    Q   ,
+    D   ,
+    GATE,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    input  D   ;
+    input  GATE;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hvl__dlxtp base (
+        .Q(Q),
+        .D(D),
+        .GATE(GATE),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__dlxtp_1 (
+    Q   ,
+    D   ,
+    GATE
+);
+
+    output Q   ;
+    input  D   ;
+    input  GATE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hvl__dlxtp base (
+        .Q(Q),
+        .D(D),
+        .GATE(GATE)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DLXTP_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__MUX2_1_V
+`define SKY130_FD_SC_HVL__MUX2_1_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Verilog wrapper for mux2 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__mux2.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__mux2_1 (
+    X   ,
+    A0  ,
+    A1  ,
+    S   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A0  ;
+    input  A1  ;
+    input  S   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hvl__mux2 base (
+        .X(X),
+        .A0(A0),
+        .A1(A1),
+        .S(S),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__mux2_1 (
+    X ,
+    A0,
+    A1,
+    S
+);
+
+    output X ;
+    input  A0;
+    input  A1;
+    input  S ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hvl__mux2 base (
+        .X(X),
+        .A0(A0),
+        .A1(A1),
+        .S(S)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__MUX2_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SDFSTP_TB_V
+`define SKY130_FD_SC_HVL__SDFSTP_TB_V
+
+/**
+ * sdfstp: Scan delay flop, inverted set, non-inverted clock,
+ *         single output.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__sdfstp.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg SCD;
+    reg SCE;
+    reg SET_B;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Q;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D     = 1\'bX;
+        SCD   = 1\'bX;
+        SCE   = 1\'bX;
+        SET_B = 1\'bX;
+        VGND  = 1\'bX;
+        VNB   = 1\'bX;
+        VPB   = 1\'bX;
+        VPWR  = 1\'bX;
+
+        #20   D     = 1\'b0;
+        #40   SCD   = 1\'b0;
+        #60   SCE   = 1\'b0;
+        #80   SET_B = 1\'b0;
+        #100  VGND  = 1\'b0;
+        #120  VNB   = 1\'b0;
+        #140  VPB   = 1\'b0;
+        #160  VPWR  = 1\'b0;
+        #180  D     = 1\'b1;
+        #200  SCD   = 1\'b1;
+        #220  SCE   = 1\'b1;
+        #240  SET_B = 1\'b1;
+        #260  VGND  = 1\'b1;
+        #280  VNB   = 1\'b1;
+        #300  VPB   = 1\'b1;
+        #320  VPWR  = 1\'b1;
+        #340  D     = 1\'b0;
+        #360  SCD   = 1\'b0;
+        #380  SCE   = 1\'b0;
+        #400  SET_B = 1\'b0;
+        #420  VGND  = 1\'b0;
+        #440  VNB   = 1\'b0;
+        #460  VPB   = 1\'b0;
+        #480  VPWR  = 1\'b0;
+        #500  VPWR  = 1\'b1;
+        #520  VPB   = 1\'b1;
+        #540  VNB   = 1\'b1;
+        #560  VGND  = 1\'b1;
+        #580  SET_B = 1\'b1;
+        #600  SCE   = 1\'b1;
+        #620  SCD   = 1\'b1;
+        #640  D     = 1\'b1;
+        #660  VPWR  = 1\'bx;
+        #680  VPB   = 1\'bx;
+        #700  VNB   = 1\'bx;
+        #720  VGND  = 1\'bx;
+        #740  SET_B = 1\'bx;
+        #760  SCE   = 1\'bx;
+        #780  SCD   = 1\'bx;
+        #800  D     = 1\'bx;
+    end
+
+    // Create a clock
+    reg CLK;
+    initial
+    begin
+        CLK = 1\'b0;
+    end
+
+    always
+    begin
+        #5 CLK = ~CLK;
+    end
+
+    sky130_fd_sc_hvl__sdfstp dut (.D(D), .SCD(SCD), .SCE(SCE), .SET_B(SET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFSTP_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DFXBP_PP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__DFXBP_PP_BLACKBOX_V
+
+/**
+ * dfxbp: Delay flop, complementary outputs.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__dfxbp (
+    Q   ,
+    Q_N ,
+    CLK ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    output Q_N ;
+    input  CLK ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DFXBP_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if (~TE_B ) (A -=> Z ) = (0:0:0,0:0:0);  // delays are tris,tfall
+(TE_B => Z ) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);  // delays are t01,t10,t0Z,tZ1,t1Z,tZ0
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(SLEEP_B +=> X) = (0:0:0,0:0:0);
+(A +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__NAND3_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HVL__NAND3_FUNCTIONAL_PP_V
+
+/**
+ * nand3: 3-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__nand3 (
+    Y   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                  Name         Output             Other arguments
+    nand                                nand0       (nand0_out_Y      , B, A, C                );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                 buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__NAND3_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__SDFSTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HVL__SDFSTP_BEHAVIORAL_PP_V
+
+/**
+ * sdfstp: Scan delay flop, inverted set, non-inverted clock,
+ *         single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v""
+`include ""../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hvl__udp_dff_ps_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_hvl__sdfstp (
+    Q    ,
+    CLK  ,
+    D    ,
+    SCD  ,
+    SCE  ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SCD  ;
+    input  SCE  ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire buf_Q        ;
+    wire SET          ;
+    wire mux_out      ;
+    reg  notifier     ;
+    wire cond0        ;
+    wire cond1        ;
+    wire cond2        ;
+    wire cond3        ;
+    wire D_delayed    ;
+    wire SCD_delayed  ;
+    wire SCE_delayed  ;
+    wire SET_B_delayed;
+    wire CLK_delayed  ;
+    wire buf0_out_Q   ;
+
+    //                                   Name         Output      Other arguments
+    not                                  not0        (SET       , SET_B_delayed                                  );
+    sky130_fd_sc_hvl__udp_mux_2to1       mux_2to10   (mux_out   , D_delayed, SCD_delayed, SCE_delayed            );
+    sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dff0        (buf_Q     , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
+    assign cond0 = ( SET_B_delayed === 1\'b1 );
+    assign cond1 = ( ( SCE_delayed === 1\'b0 ) & cond0 );
+    assign cond2 = ( ( SCE_delayed === 1\'b1 ) & cond0 );
+    assign cond3 = ( ( D_delayed !== SCD_delayed ) & cond0 );
+    buf                                  buf0        (buf0_out_Q, buf_Q                                          );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG  pwrgood_pp0 (Q         , buf0_out_Q, VPWR, VGND                         );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFSTP_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SDLCLKP_PP_SYMBOL_V
+`define SKY130_FD_SC_HVL__SDLCLKP_PP_SYMBOL_V
+
+/**
+ * sdlclkp: Scan gated clock.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__sdlclkp (
+    //# {{scanchain|Scan Chain}}
+    input  SCE ,
+
+    //# {{clocks|Clocking}}
+    input  CLK ,
+    input  GATE,
+    output GCLK,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDLCLKP_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__AND3_SYMBOL_V
+`define SKY130_FD_SC_HVL__AND3_SYMBOL_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__and3 (
+    //# {{data|Data Signals}}
+    input  A,
+    input  B,
+    input  C,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__AND3_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__AND3_1_V
+`define SKY130_FD_SC_HVL__AND3_1_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog wrapper for and3 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__and3.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__and3_1 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hvl__and3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__and3_1 (
+    X,
+    A,
+    B,
+    C
+);
+
+    output X;
+    input  A;
+    input  B;
+    input  C;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hvl__and3 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .C(C)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__AND3_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DFXTP_PP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__DFXTP_PP_BLACKBOX_V
+
+/**
+ * dfxtp: Delay flop, single output.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__dfxtp (
+    Q   ,
+    CLK ,
+    D   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DFXTP_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if ((B&C)) (A -=> Y ) = (0:0:0,0:0:0);  // delays are tris,tfall
+ifnone (A -=> Y ) = (0:0:0,0:0:0);  // delays are tris,tfall
+if ((A&C)) (B -=> Y ) = (0:0:0,0:0:0);  // delays are tris,tfall
+ifnone (B -=> Y ) = (0:0:0,0:0:0);  // delays are tris,tfall
+if ((A&B)) (C -=> Y ) = (0:0:0,0:0:0);  // delays are tris,tfall
+ifnone (C -=> Y ) = (0:0:0,0:0:0);  // delays are tris,tfall
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__MUX4_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HVL__MUX4_BEHAVIORAL_PP_V
+
+/**
+ * mux4: 4-input multiplexer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+`include ""../../models/udp_mux_4to2/sky130_fd_sc_hvl__udp_mux_4to2.v""
+
+`celldefine
+module sky130_fd_sc_hvl__mux4 (
+    X   ,
+    A0  ,
+    A1  ,
+    A2  ,
+    A3  ,
+    S0  ,
+    S1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A0  ;
+    input  A1  ;
+    input  A2  ;
+    input  A3  ;
+    input  S0  ;
+    input  S1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire mux_4to20_out_X  ;
+    wire pwrgood_pp0_out_X;
+
+    //                                  Name         Output             Other arguments
+    sky130_fd_sc_hvl__udp_mux_4to2      mux_4to20   (mux_4to20_out_X  , A0, A1, A2, A3, S0, S1     );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_4to20_out_X, VPWR, VGND);
+    buf                                 buf0        (X                , pwrgood_pp0_out_X          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__MUX4_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__EINVN_TB_V
+`define SKY130_FD_SC_HVL__EINVN_TB_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__einvn.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg TE_B;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Z;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        TE_B = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   TE_B = 1\'b0;
+        #60   VGND = 1\'b0;
+        #80   VNB  = 1\'b0;
+        #100  VPB  = 1\'b0;
+        #120  VPWR = 1\'b0;
+        #140  A    = 1\'b1;
+        #160  TE_B = 1\'b1;
+        #180  VGND = 1\'b1;
+        #200  VNB  = 1\'b1;
+        #220  VPB  = 1\'b1;
+        #240  VPWR = 1\'b1;
+        #260  A    = 1\'b0;
+        #280  TE_B = 1\'b0;
+        #300  VGND = 1\'b0;
+        #320  VNB  = 1\'b0;
+        #340  VPB  = 1\'b0;
+        #360  VPWR = 1\'b0;
+        #380  VPWR = 1\'b1;
+        #400  VPB  = 1\'b1;
+        #420  VNB  = 1\'b1;
+        #440  VGND = 1\'b1;
+        #460  TE_B = 1\'b1;
+        #480  A    = 1\'b1;
+        #500  VPWR = 1\'bx;
+        #520  VPB  = 1\'bx;
+        #540  VNB  = 1\'bx;
+        #560  VGND = 1\'bx;
+        #580  TE_B = 1\'bx;
+        #600  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_hvl__einvn dut (.A(A), .TE_B(TE_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Z(Z));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__EINVN_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_DLATCH_P_PP_PG_N_SYMBOL_V
+`define SKY130_FD_SC_HVL__UDP_DLATCH_P_PP_PG_N_SYMBOL_V
+
+/**
+ * udp_dlatch$P_pp$PG$N: D-latch, gated standard drive / active high
+ *                       (Q output UDP)
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N (
+    //# {{data|Data Signals}}
+    input  D       ,
+    output Q       ,
+
+    //# {{clocks|Clocking}}
+    input  GATE    ,
+
+    //# {{power|Power}}
+    input  NOTIFIER,
+    input  VPWR    ,
+    input  VGND
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_DLATCH_P_PP_PG_N_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DIODE_PP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__DIODE_PP_BLACKBOX_V
+
+/**
+ * diode: Antenna tie-down diode.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__diode (
+    DIODE,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    input DIODE;
+    input VPWR ;
+    input VGND ;
+    input VPB  ;
+    input VNB  ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DIODE_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__NOR2_BLACKBOX_V
+`define SKY130_FD_SC_HVL__NOR2_BLACKBOX_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__nor2 (
+    Y,
+    A,
+    B
+);
+
+    output Y;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__NOR2_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__SDFXTP_FUNCTIONAL_V
+`define SKY130_FD_SC_HVL__SDFXTP_FUNCTIONAL_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_p/sky130_fd_sc_hvl__udp_dff_p.v""
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v""
+
+`celldefine
+module sky130_fd_sc_hvl__sdfxtp (
+    Q  ,
+    CLK,
+    D  ,
+    SCD,
+    SCE
+);
+
+    // Module ports
+    output Q  ;
+    input  CLK;
+    input  D  ;
+    input  SCD;
+    input  SCE;
+
+    // Local signals
+    wire buf_Q  ;
+    wire mux_out;
+
+    //                             Delay       Name       Output   Other arguments
+    sky130_fd_sc_hvl__udp_mux_2to1             mux_2to10 (mux_out, D, SCD, SCE    );
+    sky130_fd_sc_hvl__udp_dff$P    `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK   );
+    buf                                        buf0      (Q      , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFXTP_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__A21OI_1_V
+`define SKY130_FD_SC_HVL__A21OI_1_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | B1)
+ *
+ * Verilog wrapper for a21oi with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__a21oi.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__a21oi_1 (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hvl__a21oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__a21oi_1 (
+    Y ,
+    A1,
+    A2,
+    B1
+);
+
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hvl__a21oi base (
+        .Y(Y),
+        .A1(A1),
+        .A2(A2),
+        .B1(B1)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__A21OI_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__AND3_PP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__AND3_PP_BLACKBOX_V
+
+/**
+ * and3: 3-input AND.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__and3 (
+    X   ,
+    A   ,
+    B   ,
+    C   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  C   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__AND3_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_TB_V
+`define SKY130_FD_SC_HVL__LSBUFLV2HV_TB_V
+
+/**
+ * lsbuflv2hv: Level-shift buffer, low voltage-to-high voltage,
+ *             isolated well on input buffer, double height cell.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__lsbuflv2hv.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg VPWR;
+    reg VGND;
+    reg LVPWR;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A     = 1\'bX;
+        LVPWR = 1\'bX;
+        VGND  = 1\'bX;
+        VNB   = 1\'bX;
+        VPB   = 1\'bX;
+        VPWR  = 1\'bX;
+
+        #20   A     = 1\'b0;
+        #40   LVPWR = 1\'b0;
+        #60   VGND  = 1\'b0;
+        #80   VNB   = 1\'b0;
+        #100  VPB   = 1\'b0;
+        #120  VPWR  = 1\'b0;
+        #140  A     = 1\'b1;
+        #160  LVPWR = 1\'b1;
+        #180  VGND  = 1\'b1;
+        #200  VNB   = 1\'b1;
+        #220  VPB   = 1\'b1;
+        #240  VPWR  = 1\'b1;
+        #260  A     = 1\'b0;
+        #280  LVPWR = 1\'b0;
+        #300  VGND  = 1\'b0;
+        #320  VNB   = 1\'b0;
+        #340  VPB   = 1\'b0;
+        #360  VPWR  = 1\'b0;
+        #380  VPWR  = 1\'b1;
+        #400  VPB   = 1\'b1;
+        #420  VNB   = 1\'b1;
+        #440  VGND  = 1\'b1;
+        #460  LVPWR = 1\'b1;
+        #480  A     = 1\'b1;
+        #500  VPWR  = 1\'bx;
+        #520  VPB   = 1\'bx;
+        #540  VNB   = 1\'bx;
+        #560  VGND  = 1\'bx;
+        #580  LVPWR = 1\'bx;
+        #600  A     = 1\'bx;
+    end
+
+    sky130_fd_sc_hvl__lsbuflv2hv dut (.A(A), .VPWR(VPWR), .VGND(VGND), .LVPWR(LVPWR), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFLV2HV_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__FILL_BLACKBOX_V
+`define SKY130_FD_SC_HVL__FILL_BLACKBOX_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__fill ();
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__FILL_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__O22AI_PP_SYMBOL_V
+`define SKY130_FD_SC_HVL__O22AI_PP_SYMBOL_V
+
+/**
+ * o22ai: 2-input OR into both inputs of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & (B1 | B2))
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__o22ai (
+    //# {{data|Data Signals}}
+    input  A1  ,
+    input  A2  ,
+    input  B1  ,
+    input  B2  ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__O22AI_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_BLACKBOX_V
+`define SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_BLACKBOX_V
+
+/**
+ * lsbufhv2lv_simple: Level shifting buffer, High Voltage to Low
+ *                    Voltage, simple (hv devices in inverters on lv
+ *                    power rail).
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__lsbufhv2lv_simple (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR ;
+    supply0 VGND ;
+    supply1 LVPWR;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__DIODE_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HVL__DIODE_FUNCTIONAL_PP_V
+
+/**
+ * diode: Antenna tie-down diode.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__diode (
+    DIODE,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    input DIODE;
+    input VPWR ;
+    input VGND ;
+    input VPB  ;
+    input VNB  ;
+     // No contents.
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DIODE_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__SDLXTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HVL__SDLXTP_BEHAVIORAL_PP_V
+
+/**
+ * sdlxtp: ????.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v""
+`include ""../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hvl__udp_dlatch_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_hvl__sdlxtp (
+    Q   ,
+    D   ,
+    SCD ,
+    SCE ,
+    GATE,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    input  D   ;
+    input  SCD ;
+    input  SCE ;
+    input  GATE;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q       ;
+    wire GATE_delayed;
+    wire D_delayed   ;
+    wire SCD_delayed ;
+    wire SCE_delayed ;
+    wire cond0       ;
+    wire cond1       ;
+    wire cond2       ;
+    reg  notifier    ;
+    wire mux_out     ;
+    wire buf0_out_Q  ;
+
+    //                                     Name         Output      Other arguments
+    assign cond0 = ( SCE_delayed === 1\'b0 );
+    assign cond1 = ( SCE_delayed === 1\'b1 );
+    sky130_fd_sc_hvl__udp_mux_2to1         mux_2to10   (mux_out   , D_delayed, SCD_delayed, SCE_delayed        );
+    sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0     (buf_Q     , mux_out, GATE_delayed, notifier, VPWR, VGND);
+    buf                                    buf0        (buf0_out_Q, buf_Q                                      );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG    pwrgood_pp0 (Q         , buf0_out_Q, VPWR, VGND                     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDLXTP_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SDFRTP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__SDFRTP_BLACKBOX_V
+
+/**
+ * sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
+ *         single output.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__sdfrtp (
+    Q      ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B
+);
+
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFRTP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__NAND2_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HVL__NAND2_BEHAVIORAL_PP_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__nand2 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                  Name         Output             Other arguments
+    nand                                nand0       (nand0_out_Y      , B, A                   );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                 buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__NAND2_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A +=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__XOR2_V
+`define SKY130_FD_SC_HVL__XOR2_V
+
+/**
+ * xor2: 2-input exclusive OR.
+ *
+ *       X = A ^ B
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__xor2.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__xor2.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__xor2.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__xor2.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__XOR2_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_TB_V
+`define SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_TB_V
+
+/**
+ * lsbufhv2lv_simple: Level shifting buffer, High Voltage to Low
+ *                    Voltage, simple (hv devices in inverters on lv
+ *                    power rail).
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__lsbufhv2lv_simple.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg VPWR;
+    reg VGND;
+    reg LVPWR;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A     = 1\'bX;
+        LVPWR = 1\'bX;
+        VGND  = 1\'bX;
+        VNB   = 1\'bX;
+        VPB   = 1\'bX;
+        VPWR  = 1\'bX;
+
+        #20   A     = 1\'b0;
+        #40   LVPWR = 1\'b0;
+        #60   VGND  = 1\'b0;
+        #80   VNB   = 1\'b0;
+        #100  VPB   = 1\'b0;
+        #120  VPWR  = 1\'b0;
+        #140  A     = 1\'b1;
+        #160  LVPWR = 1\'b1;
+        #180  VGND  = 1\'b1;
+        #200  VNB   = 1\'b1;
+        #220  VPB   = 1\'b1;
+        #240  VPWR  = 1\'b1;
+        #260  A     = 1\'b0;
+        #280  LVPWR = 1\'b0;
+        #300  VGND  = 1\'b0;
+        #320  VNB   = 1\'b0;
+        #340  VPB   = 1\'b0;
+        #360  VPWR  = 1\'b0;
+        #380  VPWR  = 1\'b1;
+        #400  VPB   = 1\'b1;
+        #420  VNB   = 1\'b1;
+        #440  VGND  = 1\'b1;
+        #460  LVPWR = 1\'b1;
+        #480  A     = 1\'b1;
+        #500  VPWR  = 1\'bx;
+        #520  VPB   = 1\'bx;
+        #540  VNB   = 1\'bx;
+        #560  VGND  = 1\'bx;
+        #580  LVPWR = 1\'bx;
+        #600  A     = 1\'bx;
+    end
+
+    sky130_fd_sc_hvl__lsbufhv2lv_simple dut (.A(A), .VPWR(VPWR), .VGND(VGND), .LVPWR(LVPWR), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__NAND2_PP_SYMBOL_V
+`define SKY130_FD_SC_HVL__NAND2_PP_SYMBOL_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__nand2 (
+    //# {{data|Data Signals}}
+    input  A   ,
+    input  B   ,
+    output Y   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__NAND2_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_DFF_P_PP_PG_N_TB_V
+`define SKY130_FD_SC_HVL__UDP_DFF_P_PP_PG_N_TB_V
+
+/**
+ * udp_dff$P_pp$PG$N: Positive edge triggered D flip-flop
+ *                    (Q output UDP).
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__udp_dff_p_pp_pg_n.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg NOTIFIER;
+    reg VPWR;
+    reg VGND;
+
+    // Outputs are wires
+    wire Q;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D        = 1\'bX;
+        NOTIFIER = 1\'bX;
+        VGND     = 1\'bX;
+        VPWR     = 1\'bX;
+
+        #20   D        = 1\'b0;
+        #40   NOTIFIER = 1\'b0;
+        #60   VGND     = 1\'b0;
+        #80   VPWR     = 1\'b0;
+        #100  D        = 1\'b1;
+        #120  NOTIFIER = 1\'b1;
+        #140  VGND     = 1\'b1;
+        #160  VPWR     = 1\'b1;
+        #180  D        = 1\'b0;
+        #200  NOTIFIER = 1\'b0;
+        #220  VGND     = 1\'b0;
+        #240  VPWR     = 1\'b0;
+        #260  VPWR     = 1\'b1;
+        #280  VGND     = 1\'b1;
+        #300  NOTIFIER = 1\'b1;
+        #320  D        = 1\'b1;
+        #340  VPWR     = 1\'bx;
+        #360  VGND     = 1\'bx;
+        #380  NOTIFIER = 1\'bx;
+        #400  D        = 1\'bx;
+    end
+
+    // Create a clock
+    reg CLK;
+    initial
+    begin
+        CLK = 1\'b0;
+    end
+
+    always
+    begin
+        #5 CLK = ~CLK;
+    end
+
+    sky130_fd_sc_hvl__udp_dff$P_pp$PG$N dut (.D(D), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_DFF_P_PP_PG_N_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if (TE ) (A -=> Z ) = (0:0:0,0:0:0);  // delays are tris,tfall
+(TE => Z ) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);  // delays are t01,t10,t0Z,tZ1,t1Z,tZ0
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__NOR3_BEHAVIORAL_V
+`define SKY130_FD_SC_HVL__NOR3_BEHAVIORAL_V
+
+/**
+ * nor3: 3-input NOR.
+ *
+ *       Y = !(A | B | C | !D)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__nor3 (
+    Y,
+    A,
+    B,
+    C
+);
+
+    // Module ports
+    output Y;
+    input  A;
+    input  B;
+    input  C;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    nor nor0 (nor0_out_Y, C, A, B        );
+    buf buf0 (Y         , nor0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__NOR3_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__SDFXBP_FUNCTIONAL_V
+`define SKY130_FD_SC_HVL__SDFXBP_FUNCTIONAL_V
+
+/**
+ * sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_p/sky130_fd_sc_hvl__udp_dff_p.v""
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v""
+
+`celldefine
+module sky130_fd_sc_hvl__sdfxbp (
+    Q  ,
+    Q_N,
+    CLK,
+    D  ,
+    SCD,
+    SCE
+);
+
+    // Module ports
+    output Q  ;
+    output Q_N;
+    input  CLK;
+    input  D  ;
+    input  SCD;
+    input  SCE;
+
+    // Local signals
+    wire buf_Q  ;
+    wire mux_out;
+
+    //                             Delay       Name       Output   Other arguments
+    sky130_fd_sc_hvl__udp_mux_2to1             mux_2to10 (mux_out, D, SCD, SCE    );
+    sky130_fd_sc_hvl__udp_dff$P    `UNIT_DELAY dff0      (buf_Q  , mux_out, CLK   );
+    buf                                        buf0      (Q      , buf_Q          );
+    not                                        not0      (Q_N    , buf_Q          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFXBP_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__XNOR2_BLACKBOX_V
+`define SKY130_FD_SC_HVL__XNOR2_BLACKBOX_V
+
+/**
+ * xnor2: 2-input exclusive NOR.
+ *
+ *        Y = !(A ^ B)
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__xnor2 (
+    Y,
+    A,
+    B
+);
+
+    output Y;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__XNOR2_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__INV_PP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__INV_PP_BLACKBOX_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__inv (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__INV_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__PROBEC_P_BLACKBOX_V
+`define SKY130_FD_SC_HVL__PROBEC_P_BLACKBOX_V
+
+/**
+ * probec_p: Virtual current probe point.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__probec_p (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__PROBEC_P_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_MUX_4TO2_SYMBOL_V
+`define SKY130_FD_SC_HVL__UDP_MUX_4TO2_SYMBOL_V
+
+/**
+ * udp_mux_4to2: Four to one multiplexer with 2 select controls
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__udp_mux_4to2 (
+    //# {{data|Data Signals}}
+    input  A0,
+    input  A1,
+    input  A2,
+    input  A3,
+    output X ,
+
+    //# {{control|Control Signals}}
+    input  S0,
+    input  S1
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_MUX_4TO2_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_1_V
+`define SKY130_FD_SC_HVL__LSBUFLV2HV_1_V
+
+/**
+ * lsbuflv2hv: Level-shift buffer, low voltage-to-high voltage,
+ *             isolated well on input buffer, double height cell.
+ *
+ * Verilog wrapper for lsbuflv2hv with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__lsbuflv2hv.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__lsbuflv2hv_1 (
+    X    ,
+    A    ,
+    VPWR ,
+    VGND ,
+    LVPWR,
+    VPB  ,
+    VNB
+);
+
+    output X    ;
+    input  A    ;
+    input  VPWR ;
+    input  VGND ;
+    input  LVPWR;
+    input  VPB  ;
+    input  VNB  ;
+    sky130_fd_sc_hvl__lsbuflv2hv base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .LVPWR(LVPWR),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__lsbuflv2hv_1 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR ;
+    supply0 VGND ;
+    supply1 LVPWR;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+    sky130_fd_sc_hvl__lsbuflv2hv base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFLV2HV_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SDFRBP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__SDFRBP_BLACKBOX_V
+
+/**
+ * sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__sdfrbp (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFRBP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DFXBP_PP_SYMBOL_V
+`define SKY130_FD_SC_HVL__DFXBP_PP_SYMBOL_V
+
+/**
+ * dfxbp: Delay flop, complementary outputs.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__dfxbp (
+    //# {{data|Data Signals}}
+    input  D   ,
+    output Q   ,
+    output Q_N ,
+
+    //# {{clocks|Clocking}}
+    input  CLK ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DFXBP_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__SDLCLKP_FUNCTIONAL_V
+`define SKY130_FD_SC_HVL__SDLCLKP_FUNCTIONAL_V
+
+/**
+ * sdlclkp: Scan gated clock.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dlatch_p/sky130_fd_sc_hvl__udp_dlatch_p.v""
+
+`celldefine
+module sky130_fd_sc_hvl__sdlclkp (
+    GCLK,
+    SCE ,
+    GATE,
+    CLK
+);
+
+    // Module ports
+    output GCLK;
+    input  SCE ;
+    input  GATE;
+    input  CLK ;
+
+    // Local signals
+    wire m0      ;
+    wire m0n     ;
+    wire clkn    ;
+    wire SCE_GATE;
+
+    //                             Name     Output    Other arguments
+    not                            not0    (m0n     , m0             );
+    not                            not1    (clkn    , CLK            );
+    nor                            nor0    (SCE_GATE, GATE, SCE      );
+    sky130_fd_sc_hvl__udp_dlatch$P dlatch0 (m0      , SCE_GATE, clkn );
+    and                            and0    (GCLK    , m0n, CLK       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDLCLKP_FUNCTIONAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__SDLCLKP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HVL__SDLCLKP_BEHAVIORAL_PP_V
+
+/**
+ * sdlclkp: Scan gated clock.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+`include ""../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hvl__udp_dlatch_p_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_hvl__sdlclkp (
+    GCLK,
+    SCE ,
+    GATE,
+    CLK ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output GCLK;
+    input  SCE ;
+    input  GATE;
+    input  CLK ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire m0              ;
+    wire m0n             ;
+    wire clkn            ;
+    wire CLK_delayed     ;
+    wire SCE_delayed     ;
+    wire GATE_delayed    ;
+    wire SCE_gate_delayed;
+    wire GCLK_b          ;
+    reg  notifier        ;
+    wire awake           ;
+    wire SCE_awake       ;
+    wire GATE_awake      ;
+
+    //                                     Name         Output            Other arguments
+    not                                    not0        (m0n             , m0                                          );
+    not                                    not1        (clkn            , CLK_delayed                                 );
+    nor                                    nor0        (SCE_gate_delayed, GATE_delayed, SCE_delayed                   );
+    sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dlatch0     (m0              , SCE_gate_delayed, clkn, notifier, VPWR, VGND);
+    and                                    and0        (GCLK_b          , m0n, CLK_delayed                            );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG    pwrgood_pp0 (GCLK            , GCLK_b, VPWR, VGND                          );
+    assign awake = ( VPWR === 1\'b1 );
+    assign SCE_awake = ( ( GATE_delayed === 1\'b0 ) & awake );
+    assign GATE_awake = ( ( SCE_delayed === 1\'b0 ) & awake );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDLCLKP_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_DLATCH_PR_PP_PG_N_TB_V
+`define SKY130_FD_SC_HVL__UDP_DLATCH_PR_PP_PG_N_TB_V
+
+/**
+ * udp_dlatch$PR_pp$PG$N: D-latch, gated clear direct / gate active
+ *                        high (Q output UDP)
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__udp_dlatch_pr_pp_pg_n.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg RESET;
+    reg NOTIFIER;
+    reg VPWR;
+    reg VGND;
+
+    // Outputs are wires
+    wire Q;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D        = 1\'bX;
+        NOTIFIER = 1\'bX;
+        RESET    = 1\'bX;
+        VGND     = 1\'bX;
+        VPWR     = 1\'bX;
+
+        #20   D        = 1\'b0;
+        #40   NOTIFIER = 1\'b0;
+        #60   RESET    = 1\'b0;
+        #80   VGND     = 1\'b0;
+        #100  VPWR     = 1\'b0;
+        #120  D        = 1\'b1;
+        #140  NOTIFIER = 1\'b1;
+        #160  RESET    = 1\'b1;
+        #180  VGND     = 1\'b1;
+        #200  VPWR     = 1\'b1;
+        #220  D        = 1\'b0;
+        #240  NOTIFIER = 1\'b0;
+        #260  RESET    = 1\'b0;
+        #280  VGND     = 1\'b0;
+        #300  VPWR     = 1\'b0;
+        #320  VPWR     = 1\'b1;
+        #340  VGND     = 1\'b1;
+        #360  RESET    = 1\'b1;
+        #380  NOTIFIER = 1\'b1;
+        #400  D        = 1\'b1;
+        #420  VPWR     = 1\'bx;
+        #440  VGND     = 1\'bx;
+        #460  RESET    = 1\'bx;
+        #480  NOTIFIER = 1\'bx;
+        #500  D        = 1\'bx;
+    end
+
+    // Create a clock
+    reg GATE;
+    initial
+    begin
+        GATE = 1\'b0;
+    end
+
+    always
+    begin
+        #5 GATE = ~GATE;
+    end
+
+    sky130_fd_sc_hvl__udp_dlatch$PR_pp$PG$N dut (.D(D), .RESET(RESET), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .GATE(GATE));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_DLATCH_PR_PP_PG_N_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A +=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_DFF_PS_BLACKBOX_V
+`define SKY130_FD_SC_HVL__UDP_DFF_PS_BLACKBOX_V
+
+/**
+ * udp_dff$PS: Positive edge triggered D flip-flop with active high
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__udp_dff$PS (
+    Q  ,
+    D  ,
+    CLK,
+    SET
+);
+
+    output Q  ;
+    input  D  ;
+    input  CLK;
+    input  SET;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_DFF_PS_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_FUNCTIONAL_PP_V
+
+/**
+ * lsbufhv2lv_simple: Level shifting buffer, High Voltage to Low
+ *                    Voltage, simple (hv devices in inverters on lv
+ *                    power rail).
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__lsbufhv2lv_simple (
+    X    ,
+    A    ,
+    VPWR ,
+    VGND ,
+    LVPWR,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output X    ;
+    input  A    ;
+    input  VPWR ;
+    input  VGND ;
+    input  LVPWR;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire pwrgood_pp0_out_A;
+    wire buf0_out_X       ;
+
+    //                                  Name         Output             Other arguments
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A, A, VPWR, VGND          );
+    buf                                 buf0        (buf0_out_X       , pwrgood_pp0_out_A      );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (X                , buf0_out_X, LVPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_V
+`define SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_V
+
+/**
+ * lsbuflv2hv_clkiso_hlkg: Level-shift clock buffer, low voltage to
+ *                         high voltage, isolated well
+ *                         on input buffer, inverting sleep
+ *                         mode input.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__OR2_PP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__OR2_PP_BLACKBOX_V
+
+/**
+ * or2: 2-input OR.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__or2 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__OR2_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__AND2_SYMBOL_V
+`define SKY130_FD_SC_HVL__AND2_SYMBOL_V
+
+/**
+ * and2: 2-input AND.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__and2 (
+    //# {{data|Data Signals}}
+    input  A,
+    input  B,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__AND2_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SDLCLKP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__SDLCLKP_BLACKBOX_V
+
+/**
+ * sdlclkp: Scan gated clock.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__sdlclkp (
+    GCLK,
+    SCE ,
+    GATE,
+    CLK
+);
+
+    output GCLK;
+    input  SCE ;
+    input  GATE;
+    input  CLK ;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDLCLKP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_DFF_PR_SYMBOL_V
+`define SKY130_FD_SC_HVL__UDP_DFF_PR_SYMBOL_V
+
+/**
+ * udp_dff$PR: Positive edge triggered D flip-flop with active high
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__udp_dff$PR (
+    //# {{data|Data Signals}}
+    input  D    ,
+    output Q    ,
+
+    //# {{control|Control Signals}}
+    input  RESET,
+
+    //# {{clocks|Clocking}}
+    input  CLK
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_DFF_PR_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+if ((B&C)) (A +=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
+ifnone (A +=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
+if ((A&C)) (B +=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
+ifnone (B +=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
+if ((A&B)) (C +=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
+ifnone (C +=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DFXBP_TB_V
+`define SKY130_FD_SC_HVL__DFXBP_TB_V
+
+/**
+ * dfxbp: Delay flop, complementary outputs.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__dfxbp.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Q;
+    wire Q_N;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   D    = 1\'b0;
+        #40   VGND = 1\'b0;
+        #60   VNB  = 1\'b0;
+        #80   VPB  = 1\'b0;
+        #100  VPWR = 1\'b0;
+        #120  D    = 1\'b1;
+        #140  VGND = 1\'b1;
+        #160  VNB  = 1\'b1;
+        #180  VPB  = 1\'b1;
+        #200  VPWR = 1\'b1;
+        #220  D    = 1\'b0;
+        #240  VGND = 1\'b0;
+        #260  VNB  = 1\'b0;
+        #280  VPB  = 1\'b0;
+        #300  VPWR = 1\'b0;
+        #320  VPWR = 1\'b1;
+        #340  VPB  = 1\'b1;
+        #360  VNB  = 1\'b1;
+        #380  VGND = 1\'b1;
+        #400  D    = 1\'b1;
+        #420  VPWR = 1\'bx;
+        #440  VPB  = 1\'bx;
+        #460  VNB  = 1\'bx;
+        #480  VGND = 1\'bx;
+        #500  D    = 1\'bx;
+    end
+
+    // Create a clock
+    reg CLK;
+    initial
+    begin
+        CLK = 1\'b0;
+    end
+
+    always
+    begin
+        #5 CLK = ~CLK;
+    end
+
+    sky130_fd_sc_hvl__dfxbp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DFXBP_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__O22A_BLACKBOX_V
+`define SKY130_FD_SC_HVL__O22A_BLACKBOX_V
+
+/**
+ * o22a: 2-input OR into both inputs of 2-input AND.
+ *
+ *       X = ((A1 | A2) & (B1 | B2))
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__o22a (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__O22A_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__SDFRBP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HVL__SDFRBP_FUNCTIONAL_PP_V
+
+/**
+ * sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hvl__udp_dff_pr_pp_pg_n.v""
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v""
+
+`celldefine
+module sky130_fd_sc_hvl__sdfrbp (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    // Module ports
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+
+    // Local signals
+    wire buf_Q      ;
+    wire RESET      ;
+    wire mux_out    ;
+    wire buf0_out_Q ;
+    wire not1_out_qn;
+
+    //                                   Delay       Name         Output       Other arguments
+    not                                              not0        (RESET      , RESET_B                          );
+    sky130_fd_sc_hvl__udp_mux_2to1                   mux_2to10   (mux_out    , D, SCD, SCE                      );
+    sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0        (buf_Q      , mux_out, CLK, RESET, , VPWR, VGND);
+    buf                                              buf0        (buf0_out_Q , buf_Q                            );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG              pwrgood_pp0 (Q          , buf0_out_Q, VPWR, VGND           );
+    not                                              not1        (not1_out_qn, buf_Q                            );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG              pwrgood_pp1 (Q_N        , not1_out_qn, VPWR, VGND          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFRBP_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SDFRBP_PP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__SDFRBP_PP_BLACKBOX_V
+
+/**
+ * sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
+ *         complementary outputs.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__sdfrbp (
+    Q      ,
+    Q_N    ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B,
+    VPWR   ,
+    VGND   ,
+    VPB    ,
+    VNB
+);
+
+    output Q      ;
+    output Q_N    ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  VPB    ;
+    input  VNB    ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFRBP_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__PROBE_P_PP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__PROBE_P_PP_BLACKBOX_V
+
+/**
+ * probe_p: Virtual voltage probe point.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__probe_p (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__PROBE_P_PP_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_DFF_PR_TB_V
+`define SKY130_FD_SC_HVL__UDP_DFF_PR_TB_V
+
+/**
+ * udp_dff$PR: Positive edge triggered D flip-flop with active high
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__udp_dff_pr.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg RESET;
+
+    // Outputs are wires
+    wire Q;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D     = 1\'bX;
+        RESET = 1\'bX;
+
+        #20   D     = 1\'b0;
+        #40   RESET = 1\'b0;
+        #60   D     = 1\'b1;
+        #80   RESET = 1\'b1;
+        #100  D     = 1\'b0;
+        #120  RESET = 1\'b0;
+        #140  RESET = 1\'b1;
+        #160  D     = 1\'b1;
+        #180  RESET = 1\'bx;
+        #200  D     = 1\'bx;
+    end
+
+    // Create a clock
+    reg CLK;
+    initial
+    begin
+        CLK = 1\'b0;
+    end
+
+    always
+    begin
+        #5 CLK = ~CLK;
+    end
+
+    sky130_fd_sc_hvl__udp_dff$PR dut (.D(D), .RESET(RESET), .Q(Q), .CLK(CLK));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_DFF_PR_TB_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__INV_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HVL__INV_FUNCTIONAL_PP_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__inv (
+    Y   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire not0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                  Name         Output             Other arguments
+    not                                 not0        (not0_out_Y       , A                     );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
+    buf                                 buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__INV_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+( CLK +=> GCLK ) = ( 0:0:0 , 0:0:0 ) ;                         // delays are tris , tfall
+$width ( negedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ;
+$setuphold ( posedge CLK , posedge GATE , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , CLK_delayed , GATE_delayed ) ;
+$setuphold ( posedge CLK , negedge GATE , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , CLK_delayed , GATE_delayed ) ;
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__A21OI_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HVL__A21OI_BEHAVIORAL_PP_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__a21oi (
+    Y   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire and0_out         ;
+    wire nor0_out_Y       ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                  Name         Output             Other arguments
+    and                                 and0        (and0_out         , A1, A2                );
+    nor                                 nor0        (nor0_out_Y       , B1, and0_out          );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
+    buf                                 buf0        (Y                , pwrgood_pp0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__A21OI_BEHAVIORAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_PP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_PP_BLACKBOX_V
+
+/**
+ * lsbuflv2hv_isosrchvaon: Level shift buffer, low voltage to high
+ *                         voltage, isolated well on input buffer,
+ *                         inverting sleep mode input, zero power
+ *                         sleep mode.
+ *
+ * Verilog stub definition (black box with power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon (
+    X      ,
+    A      ,
+    SLEEP_B,
+    VPWR   ,
+    VGND   ,
+    LVPWR  ,
+    VPB    ,
+    VNB
+);
+
+    output X      ;
+    input  A      ;
+    input  SLEEP_B;
+    input  VPWR   ;
+    input  VGND   ;
+    input  LVPWR  ;
+    input  VPB    ;
+    input  VNB    ;
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_PP_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(negedge SET_B => (Q -: SET_B ) ) = 0:0:0;  // delay is tris
+(posedge CLK => (Q : CLK ) ) = (0:0:0,0:0:0); // delays are tris,tfall
+$width (posedge CLK &&& (SET_B===1\'b1) , 0:0:0, 0, notifier);
+$width (negedge CLK &&& (SET_B===1\'b1) , 0:0:0, 0, notifier);
+$width (negedge SET_B , 0:0:0 , 0 , notifier ) ;
+$recrem ( posedge SET_B , posedge CLK , 0:0:0, 0:0:0, notifier , , , SETB_delayed , CLK_delayed ) ;
+$setuphold ( posedge CLK , posedge D , 0:0:0, 0:0:0, notifier , , COND0 , CLK_delayed , D_delayed ) ;
+$setuphold ( posedge CLK , negedge D , 0:0:0, 0:0:0, notifier , , COND0 , CLK_delayed , D_delayed ) ;
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DFRBP_SYMBOL_V
+`define SKY130_FD_SC_HVL__DFRBP_SYMBOL_V
+
+/**
+ * dfrbp: Delay flop, inverted reset, complementary outputs.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__dfrbp (
+    //# {{data|Data Signals}}
+    input  D      ,
+    output Q      ,
+    output Q_N    ,
+
+    //# {{control|Control Signals}}
+    input  RESET_B,
+
+    //# {{clocks|Clocking}}
+    input  CLK
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DFRBP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__OR2_FUNCTIONAL_V
+`define SKY130_FD_SC_HVL__OR2_FUNCTIONAL_V
+
+/**
+ * or2: 2-input OR.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__or2 (
+    X,
+    A,
+    B
+);
+
+    // Module ports
+    output X;
+    input  A;
+    input  B;
+
+    // Local signals
+    wire or0_out_X;
+
+    //  Name  Output     Other arguments
+    or  or0  (or0_out_X, B, A           );
+    buf buf0 (X        , or0_out_X      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__OR2_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_SYMBOL_V
+`define SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_SYMBOL_V
+
+/**
+ * lsbuflv2hv_isosrchvaon: Level shift buffer, low voltage to high
+ *                         voltage, isolated well on input buffer,
+ *                         inverting sleep mode input, zero power
+ *                         sleep mode.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon (
+    //# {{data|Data Signals}}
+    input  A      ,
+    output X      ,
+
+    //# {{power|Power}}
+    input  SLEEP_B
+);
+
+    // Voltage supply signals
+    supply1 VPWR ;
+    supply0 VGND ;
+    supply1 LVPWR;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__DFSTP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HVL__DFSTP_FUNCTIONAL_PP_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+`include ""../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hvl__udp_dff_ps_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_hvl__dfstp (
+    Q    ,
+    CLK  ,
+    D    ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire buf_Q     ;
+    wire SET       ;
+    wire buf0_out_Q;
+
+    //                                   Delay       Name         Output      Other arguments
+    not                                              not0        (SET       , SET_B                    );
+    sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0        (buf_Q     , D, CLK, SET, , VPWR, VGND);
+    buf                                              buf0        (buf0_out_Q, buf_Q                    );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG              pwrgood_pp0 (Q         , buf0_out_Q, VPWR, VGND   );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DFSTP_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__O21AI_SYMBOL_V
+`define SKY130_FD_SC_HVL__O21AI_SYMBOL_V
+
+/**
+ * o21ai: 2-input OR into first input of 2-input NAND.
+ *
+ *        Y = !((A1 | A2) & B1)
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__o21ai (
+    //# {{data|Data Signals}}
+    input  A1,
+    input  A2,
+    input  B1,
+    output Y
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__O21AI_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SDFRTP_V
+`define SKY130_FD_SC_HVL__SDFRTP_V
+
+/**
+ * sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
+ *         single output.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__sdfrtp.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__sdfrtp.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__sdfrtp.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__sdfrtp.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFRTP_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_SYMBOL_V
+`define SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_SYMBOL_V
+
+/**
+ * lsbuflv2hv_clkiso_hlkg: Level-shift clock buffer, low voltage to
+ *                         high voltage, isolated well
+ *                         on input buffer, inverting sleep
+ *                         mode input.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg (
+    //# {{data|Data Signals}}
+    input  A      ,
+    output X      ,
+
+    //# {{power|Power}}
+    input  SLEEP_B
+);
+
+    // Voltage supply signals
+    supply1 VPWR ;
+    supply0 VGND ;
+    supply1 LVPWR;
+    supply1 VPB  ;
+    supply0 VNB  ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SDFXBP_SYMBOL_V
+`define SKY130_FD_SC_HVL__SDFXBP_SYMBOL_V
+
+/**
+ * sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__sdfxbp (
+    //# {{data|Data Signals}}
+    input  D  ,
+    output Q  ,
+    output Q_N,
+
+    //# {{scanchain|Scan Chain}}
+    input  SCD,
+    input  SCE,
+
+    //# {{clocks|Clocking}}
+    input  CLK
+);
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFXBP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__CONB_PP_SYMBOL_V
+`define SKY130_FD_SC_HVL__CONB_PP_SYMBOL_V
+
+/**
+ * conb: Constant value, low, high outputs.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__conb (
+    //# {{data|Data Signals}}
+    output HI  ,
+    output LO  ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__CONB_PP_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__A22OI_BEHAVIORAL_V
+`define SKY130_FD_SC_HVL__A22OI_BEHAVIORAL_V
+
+/**
+ * a22oi: 2-input AND into both inputs of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | (B1 & B2))
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__a22oi (
+    Y ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire nand0_out ;
+    wire nand1_out ;
+    wire and0_out_Y;
+
+    //   Name   Output      Other arguments
+    nand nand0 (nand0_out , A2, A1              );
+    nand nand1 (nand1_out , B2, B1              );
+    and  and0  (and0_out_Y, nand0_out, nand1_out);
+    buf  buf0  (Y         , and0_out_Y          );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__A22OI_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__DFSTP_BEHAVIORAL_PP_V
+`define SKY130_FD_SC_HVL__DFSTP_BEHAVIORAL_PP_V
+
+/**
+ * dfstp: Delay flop, inverted set, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+`include ""../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hvl__udp_dff_ps_pp_pg_n.v""
+
+`celldefine
+module sky130_fd_sc_hvl__dfstp (
+    Q    ,
+    CLK  ,
+    D    ,
+    SET_B,
+    VPWR ,
+    VGND ,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output Q    ;
+    input  CLK  ;
+    input  D    ;
+    input  SET_B;
+    input  VPWR ;
+    input  VGND ;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire buf_Q        ;
+    wire SET          ;
+    reg  notifier     ;
+    wire cond0        ;
+    wire D_delayed    ;
+    wire SET_B_delayed;
+    wire CLK_delayed  ;
+    wire buf0_out_Q   ;
+
+    //                                   Name         Output      Other arguments
+    not                                  not0        (SET       , SET_B_delayed                                    );
+    sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dff0        (buf_Q     , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
+    assign cond0 = ( SET_B_delayed === 1\'b1 );
+    buf                                  buf0        (buf0_out_Q, buf_Q                                            );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG  pwrgood_pp0 (Q         , buf0_out_Q, VPWR, VGND                           );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DFSTP_BEHAVIORAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__O21A_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HVL__O21A_FUNCTIONAL_PP_V
+
+/**
+ * o21a: 2-input OR into first input of 2-input AND.
+ *
+ *       X = ((A1 | A2) & B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__o21a (
+    X   ,
+    A1  ,
+    A2  ,
+    B1  ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output X   ;
+    input  A1  ;
+    input  A2  ;
+    input  B1  ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire or0_out          ;
+    wire and0_out_X       ;
+    wire pwrgood_pp0_out_X;
+
+    //                                  Name         Output             Other arguments
+    or                                  or0         (or0_out          , A2, A1                );
+    and                                 and0        (and0_out_X       , or0_out, B1           );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
+    buf                                 buf0        (X                , pwrgood_pp0_out_X     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__O21A_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__OR3_PP_SYMBOL_V
+`define SKY130_FD_SC_HVL__OR3_PP_SYMBOL_V
+
+/**
+ * or3: 3-input OR.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__or3 (
+    //# {{data|Data Signals}}
+    input  A   ,
+    input  B   ,
+    input  C   ,
+    output X   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__OR3_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_LH_SYMBOL_V
+`define SKY130_FD_SC_HVL__LSBUFHV2HV_LH_SYMBOL_V
+
+/**
+ * lsbufhv2hv_lh: Level shifting buffer, High Voltage to High Voltage,
+ *                Lower Voltage to Higher Voltage.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__lsbufhv2hv_lh (
+    //# {{data|Data Signals}}
+    input  A,
+    output X
+);
+
+    // Voltage supply signals
+    supply1 VPWR    ;
+    supply0 VGND    ;
+    supply1 LOWHVPWR;
+    supply1 VPB     ;
+    supply0 VNB     ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFHV2HV_LH_SYMBOL_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__NAND2_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HVL__NAND2_FUNCTIONAL_PP_V
+
+/**
+ * nand2: 2-input NAND.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__nand2 (
+    Y   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Y   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire nand0_out_Y      ;
+    wire pwrgood_pp0_out_Y;
+
+    //                                  Name         Output             Other arguments
+    nand                                nand0       (nand0_out_Y      , B, A                   );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
+    buf                                 buf0        (Y                , pwrgood_pp0_out_Y      );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__NAND2_FUNCTIONAL_PP_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__SDFRTP_TB_V
+`define SKY130_FD_SC_HVL__SDFRTP_TB_V
+
+/**
+ * sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
+ *         single output.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__sdfrtp.v""
+
+module top();
+
+    // Inputs are registered
+    reg D;
+    reg SCD;
+    reg SCE;
+    reg RESET_B;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire Q;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        D       = 1\'bX;
+        RESET_B = 1\'bX;
+        SCD     = 1\'bX;
+        SCE     = 1\'bX;
+        VGND    = 1\'bX;
+        VNB     = 1\'bX;
+        VPB     = 1\'bX;
+        VPWR    = 1\'bX;
+
+        #20   D       = 1\'b0;
+        #40   RESET_B = 1\'b0;
+        #60   SCD     = 1\'b0;
+        #80   SCE     = 1\'b0;
+        #100  VGND    = 1\'b0;
+        #120  VNB     = 1\'b0;
+        #140  VPB     = 1\'b0;
+        #160  VPWR    = 1\'b0;
+        #180  D       = 1\'b1;
+        #200  RESET_B = 1\'b1;
+        #220  SCD     = 1\'b1;
+        #240  SCE     = 1\'b1;
+        #260  VGND    = 1\'b1;
+        #280  VNB     = 1\'b1;
+        #300  VPB     = 1\'b1;
+        #320  VPWR    = 1\'b1;
+        #340  D       = 1\'b0;
+        #360  RESET_B = 1\'b0;
+        #380  SCD     = 1\'b0;
+        #400  SCE     = 1\'b0;
+        #420  VGND    = 1\'b0;
+        #440  VNB     = 1\'b0;
+        #460  VPB     = 1\'b0;
+        #480  VPWR    = 1\'b0;
+        #500  VPWR    = 1\'b1;
+        #520  VPB     = 1\'b1;
+        #540  VNB     = 1\'b1;
+        #560  VGND    = 1\'b1;
+        #580  SCE     = 1\'b1;
+        #600  SCD     = 1\'b1;
+        #620  RESET_B = 1\'b1;
+        #640  D       = 1\'b1;
+        #660  VPWR    = 1\'bx;
+        #680  VPB     = 1\'bx;
+        #700  VNB     = 1\'bx;
+        #720  VGND    = 1\'bx;
+        #740  SCE     = 1\'bx;
+        #760  SCD     = 1\'bx;
+        #780  RESET_B = 1\'bx;
+        #800  D       = 1\'bx;
+    end
+
+    // Create a clock
+    reg CLK;
+    initial
+    begin
+        CLK = 1\'b0;
+    end
+
+    always
+    begin
+        #5 CLK = ~CLK;
+    end
+
+    sky130_fd_sc_hvl__sdfrtp dut (.D(D), .SCD(SCD), .SCE(SCE), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFRTP_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__AND2_BLACKBOX_V
+`define SKY130_FD_SC_HVL__AND2_BLACKBOX_V
+
+/**
+ * and2: 2-input AND.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__and2 (
+    X,
+    A,
+    B
+);
+
+    output X;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__AND2_BLACKBOX_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__UDP_ISOLATCHHV_PP_PLG_S_V
+`define SKY130_FD_SC_HVL__UDP_ISOLATCHHV_PP_PLG_S_V
+
+/**
+ * udp_isolatchhv_pp$PLG$S: Power isolating latch (for HV). Includes
+ *                          VPWR, LVPWR, and VGND power pins with
+ *                          active high sleep pin (SLEEP).
+ *
+ * Verilog primitive definition.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef NO_PRIMITIVES
+`include ""./sky130_fd_sc_hvl__udp_isolatchhv_pp_plg_s.blackbox.v""
+`else
+primitive sky130_fd_sc_hvl__udp_isolatchhv_pp$PLG$S (
+    UDP_OUT,
+    UDP_IN ,
+    VPWR   ,
+    LVPWR  ,
+    VGND   ,
+    SLEEP
+);
+
+    output UDP_OUT;
+    input  UDP_IN ;
+    input  VPWR   ;
+    input  LVPWR  ;
+    input  VGND   ;
+    input  SLEEP  ;
+
+    table
+     // UDP_IN VPWR LVPWR VGND SLEEP : out
+          0     1     1    0     b   :  0   ;
+          1     1     1    0     0   :  1   ;
+          b     1     ?    0     1   :  0   ;
+          ?     1     0    0     1   :  0   ;
+          x     1     1    0     1   :  x   ;
+    endtable
+endprimitive
+`endif // NO_PRIMITIVES
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__UDP_ISOLATCHHV_PP_PLG_S_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__NOR2_V
+`define SKY130_FD_SC_HVL__NOR2_V
+
+/**
+ * nor2: 2-input NOR.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__nor2.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__nor2.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__nor2.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__nor2.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__NOR2_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(SLEEP_B +=> X) = (0:0:0,0:0:0);
+(A +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__FILL_SYMBOL_V
+`define SKY130_FD_SC_HVL__FILL_SYMBOL_V
+
+/**
+ * fill: Fill cell.
+ *
+ * Verilog stub (without power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__fill ();
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__FILL_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__A22O_BLACKBOX_V
+`define SKY130_FD_SC_HVL__A22O_BLACKBOX_V
+
+/**
+ * a22o: 2-input AND into both inputs of 2-input OR.
+ *
+ *       X = ((A1 & A2) | (B1 & B2))
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__a22o (
+    X ,
+    A1,
+    A2,
+    B1,
+    B2
+);
+
+    output X ;
+    input  A1;
+    input  A2;
+    input  B1;
+    input  B2;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__A22O_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__SDFXTP_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HVL__SDFXTP_FUNCTIONAL_PP_V
+
+/**
+ * sdfxtp: Scan delay flop, non-inverted clock, single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hvl__udp_dff_p_pp_pg_n.v""
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v""
+
+`celldefine
+module sky130_fd_sc_hvl__sdfxtp (
+    Q   ,
+    CLK ,
+    D   ,
+    SCD ,
+    SCE ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    // Module ports
+    output Q   ;
+    input  CLK ;
+    input  D   ;
+    input  SCD ;
+    input  SCE ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+
+    // Local signals
+    wire buf_Q     ;
+    wire mux_out   ;
+    wire buf0_out_Q;
+
+    //                                  Delay       Name         Output      Other arguments
+    sky130_fd_sc_hvl__udp_mux_2to1                  mux_2to10   (mux_out   , D, SCD, SCE               );
+    sky130_fd_sc_hvl__udp_dff$P_pp$PG$N `UNIT_DELAY dff0        (buf_Q     , mux_out, CLK, , VPWR, VGND);
+    buf                                             buf0        (buf0_out_Q, buf_Q                     );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG             pwrgood_pp0 (Q         , buf0_out_Q, VPWR, VGND    );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFXTP_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__SDFRTP_BEHAVIORAL_V
+`define SKY130_FD_SC_HVL__SDFRTP_BEHAVIORAL_V
+
+/**
+ * sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
+ *         single output.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hvl__udp_dff_pr_pp_pg_n.v""
+`include ""../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v""
+
+`celldefine
+module sky130_fd_sc_hvl__sdfrtp (
+    Q      ,
+    CLK    ,
+    D      ,
+    SCD    ,
+    SCE    ,
+    RESET_B
+);
+
+    // Module ports
+    output Q      ;
+    input  CLK    ;
+    input  D      ;
+    input  SCD    ;
+    input  SCE    ;
+    input  RESET_B;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire buf_Q          ;
+    wire RESET          ;
+    wire mux_out        ;
+    reg  notifier       ;
+    wire cond0          ;
+    wire cond1          ;
+    wire cond2          ;
+    wire cond3          ;
+    wire D_delayed      ;
+    wire SCD_delayed    ;
+    wire SCE_delayed    ;
+    wire RESET_B_delayed;
+    wire CLK_delayed    ;
+
+    //                                   Name       Output   Other arguments
+    not                                  not0      (RESET  , RESET_B_delayed                                  );
+    sky130_fd_sc_hvl__udp_mux_2to1       mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed              );
+    sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0      (buf_Q  , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
+    assign cond0 = ( RESET_B_delayed === 1\'b1 );
+    assign cond1 = ( ( SCE_delayed === 1\'b0 ) & cond0 );
+    assign cond2 = ( ( SCE_delayed === 1\'b1 ) & cond0 );
+    assign cond3 = ( ( D_delayed !== SCD_delayed ) & cond0 );
+    buf                                  buf0      (Q      , buf_Q                                            );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__SDFRTP_BEHAVIORAL_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_FUNCTIONAL_PP_V
+`define SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_FUNCTIONAL_PP_V
+
+/**
+ * lsbuflv2hv_symmetric: Level shifting buffer, Low Voltage to High
+ *                       Voltage, Symmetrical.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v""
+
+`celldefine
+module sky130_fd_sc_hvl__lsbuflv2hv_symmetric (
+    X    ,
+    A    ,
+    VPWR ,
+    VGND ,
+    LVPWR,
+    VPB  ,
+    VNB
+);
+
+    // Module ports
+    output X    ;
+    input  A    ;
+    input  VPWR ;
+    input  VGND ;
+    input  LVPWR;
+    input  VPB  ;
+    input  VNB  ;
+
+    // Local signals
+    wire pwrgood_pp0_out_A;
+    wire buf0_out_X       ;
+
+    //                                  Name         Output             Other arguments
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A, A, LVPWR, VGND        );
+    buf                                 buf0        (buf0_out_X       , pwrgood_pp0_out_A     );
+    sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (X                , buf0_out_X, VPWR, VGND);
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_FUNCTIONAL_PP_V"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__MUX4_BEHAVIORAL_V
+`define SKY130_FD_SC_HVL__MUX4_BEHAVIORAL_V
+
+/**
+ * mux4: 4-input multiplexer.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+// Import user defined primitives.
+`include ""../../models/udp_mux_4to2/sky130_fd_sc_hvl__udp_mux_4to2.v""
+
+`celldefine
+module sky130_fd_sc_hvl__mux4 (
+    X ,
+    A0,
+    A1,
+    A2,
+    A3,
+    S0,
+    S1
+);
+
+    // Module ports
+    output X ;
+    input  A0;
+    input  A1;
+    input  A2;
+    input  A3;
+    input  S0;
+    input  S1;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire mux_4to20_out_X;
+
+    //                             Name       Output           Other arguments
+    sky130_fd_sc_hvl__udp_mux_4to2 mux_4to20 (mux_4to20_out_X, A0, A1, A2, A3, S0, S1);
+    buf                            buf0      (X              , mux_4to20_out_X       );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__MUX4_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__OR2_TB_V
+`define SKY130_FD_SC_HVL__OR2_TB_V
+
+/**
+ * or2: 2-input OR.
+ *
+ * Autogenerated test bench.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__or2.v""
+
+module top();
+
+    // Inputs are registered
+    reg A;
+    reg B;
+    reg VPWR;
+    reg VGND;
+    reg VPB;
+    reg VNB;
+
+    // Outputs are wires
+    wire X;
+
+    initial
+    begin
+        // Initial state is x for all inputs.
+        A    = 1\'bX;
+        B    = 1\'bX;
+        VGND = 1\'bX;
+        VNB  = 1\'bX;
+        VPB  = 1\'bX;
+        VPWR = 1\'bX;
+
+        #20   A    = 1\'b0;
+        #40   B    = 1\'b0;
+        #60   VGND = 1\'b0;
+        #80   VNB  = 1\'b0;
+        #100  VPB  = 1\'b0;
+        #120  VPWR = 1\'b0;
+        #140  A    = 1\'b1;
+        #160  B    = 1\'b1;
+        #180  VGND = 1\'b1;
+        #200  VNB  = 1\'b1;
+        #220  VPB  = 1\'b1;
+        #240  VPWR = 1\'b1;
+        #260  A    = 1\'b0;
+        #280  B    = 1\'b0;
+        #300  VGND = 1\'b0;
+        #320  VNB  = 1\'b0;
+        #340  VPB  = 1\'b0;
+        #360  VPWR = 1\'b0;
+        #380  VPWR = 1\'b1;
+        #400  VPB  = 1\'b1;
+        #420  VNB  = 1\'b1;
+        #440  VGND = 1\'b1;
+        #460  B    = 1\'b1;
+        #480  A    = 1\'b1;
+        #500  VPWR = 1\'bx;
+        #520  VPB  = 1\'bx;
+        #540  VNB  = 1\'bx;
+        #560  VGND = 1\'bx;
+        #580  B    = 1\'bx;
+        #600  A    = 1\'bx;
+    end
+
+    sky130_fd_sc_hvl__or2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__OR2_TB_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__XOR2_1_V
+`define SKY130_FD_SC_HVL__XOR2_1_V
+
+/**
+ * xor2: 2-input exclusive OR.
+ *
+ *       X = A ^ B
+ *
+ * Verilog wrapper for xor2 with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__xor2.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__xor2_1 (
+    X   ,
+    A   ,
+    B   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  B   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hvl__xor2 base (
+        .X(X),
+        .A(A),
+        .B(B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__xor2_1 (
+    X,
+    A,
+    B
+);
+
+    output X;
+    input  A;
+    input  B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hvl__xor2 base (
+        .X(X),
+        .A(A),
+        .B(B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__XOR2_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__BUF_V
+`define SKY130_FD_SC_HVL__BUF_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__buf.functional.pp.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__buf.behavioral.pp.v""
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+`include ""sky130_fd_sc_hvl__buf.functional.v""
+`else  // FUNCTIONAL
+`include ""sky130_fd_sc_hvl__buf.behavioral.v""
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__BUF_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_HL_BLACKBOX_V
+`define SKY130_FD_SC_HVL__LSBUFHV2HV_HL_BLACKBOX_V
+
+/**
+ * lsbufhv2hv_hl: Level shifting buffer, High Voltage to High Voltage,
+ *                Higher Voltage to Lower Voltage.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__lsbufhv2hv_hl (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR    ;
+    supply0 VGND    ;
+    supply1 LOWHVPWR;
+    supply1 VPB     ;
+    supply0 VNB     ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__LSBUFHV2HV_HL_BLACKBOX_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__INV_BEHAVIORAL_V
+`define SKY130_FD_SC_HVL__INV_BEHAVIORAL_V
+
+/**
+ * inv: Inverter.
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__inv (
+    Y,
+    A
+);
+
+    // Module ports
+    output Y;
+    input  A;
+
+    // Module supplies
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    // Local signals
+    wire not0_out_Y;
+
+    //  Name  Output      Other arguments
+    not not0 (not0_out_Y, A              );
+    buf buf0 (Y         , not0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__INV_BEHAVIORAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__MUX2_PP_SYMBOL_V
+`define SKY130_FD_SC_HVL__MUX2_PP_SYMBOL_V
+
+/**
+ * mux2: 2-input multiplexer.
+ *
+ * Verilog stub (with power pins) for graphical symbol definition
+ * generation.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__mux2 (
+    //# {{data|Data Signals}}
+    input  A0  ,
+    input  A1  ,
+    output X   ,
+
+    //# {{control|Control Signals}}
+    input  S   ,
+
+    //# {{power|Power}}
+    input  VPB ,
+    input  VPWR,
+    input  VGND,
+    input  VNB
+);
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__MUX2_PP_SYMBOL_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__EINVN_1_V
+`define SKY130_FD_SC_HVL__EINVN_1_V
+
+/**
+ * einvn: Tri-state inverter, negative enable.
+ *
+ * Verilog wrapper for einvn with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__einvn.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__einvn_1 (
+    Z   ,
+    A   ,
+    TE_B,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hvl__einvn base (
+        .Z(Z),
+        .A(A),
+        .TE_B(TE_B),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__einvn_1 (
+    Z   ,
+    A   ,
+    TE_B
+);
+
+    output Z   ;
+    input  A   ;
+    input  TE_B;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hvl__einvn base (
+        .Z(Z),
+        .A(A),
+        .TE_B(TE_B)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__EINVN_1_V
+"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__BUF_1_V
+`define SKY130_FD_SC_HVL__BUF_1_V
+
+/**
+ * buf: Buffer.
+ *
+ * Verilog wrapper for buf with size of 1 units.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`include ""sky130_fd_sc_hvl__buf.v""
+
+`ifdef USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__buf_1 (
+    X   ,
+    A   ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output X   ;
+    input  A   ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    sky130_fd_sc_hvl__buf base (
+        .X(X),
+        .A(A),
+        .VPWR(VPWR),
+        .VGND(VGND),
+        .VPB(VPB),
+        .VNB(VNB)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`else // If not USE_POWER_PINS
+/*********************************************************/
+
+`celldefine
+module sky130_fd_sc_hvl__buf_1 (
+    X,
+    A
+);
+
+    output X;
+    input  A;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+    sky130_fd_sc_hvl__buf base (
+        .X(X),
+        .A(A)
+    );
+
+endmodule
+`endcelldefine
+
+/*********************************************************/
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__BUF_1_V
+"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+specify
+(A +=> X) = (0:0:0,0:0:0);
+endspecify"
+"/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+
+`ifndef SKY130_FD_SC_HVL__A21OI_FUNCTIONAL_V
+`define SKY130_FD_SC_HVL__A21OI_FUNCTIONAL_V
+
+/**
+ * a21oi: 2-input AND into first input of 2-input NOR.
+ *
+ *        Y = !((A1 & A2) | B1)
+ *
+ * Verilog simulation functional model.
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`celldefine
+module sky130_fd_sc_hvl__a21oi (
+    Y ,
+    A1,
+    A2,
+    B1
+);
+
+    // Module ports
+    output Y ;
+    input  A1;
+    input  A2;
+    input  B1;
+
+    // Local signals
+    wire and0_out  ;
+    wire nor0_out_Y;
+
+    //  Name  Output      Other arguments
+    and and0 (and0_out  , A1, A2         );
+    nor nor0 (nor0_out_Y, B1, and0_out   );
+    buf buf0 (Y         , nor0_out_Y     );
+
+endmodule
+`endcelldefine
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__A21OI_FUNCTIONAL_V"
+"/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_FD_SC_HVL__DLXTP_BLACKBOX_V
+`define SKY130_FD_SC_HVL__DLXTP_BLACKBOX_V
+
+/**
+ * dlxtp: Delay latch, non-inverted enable, single output.
+ *
+ * Verilog stub definition (black box without power pins).
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+(* blackbox *)
+module sky130_fd_sc_hvl__dlxtp (
+    Q   ,
+    D   ,
+    GATE
+);
+
+    output Q   ;
+    input  D   ;
+    input  GATE;
+
+    // Voltage supply signals
+    supply1 VPWR;
+    supply0 VGND;
+    supply1 VPB ;
+    supply0 VNB ;
+
+endmodule
+
+`default_nettype wire
+`endif  // SKY130_FD_SC_HVL__DLXTP_BLACKBOX_V
+"
+"/*
+ *  16-bit full adder
+ *  Copyright (C) 2008-2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+module zet_fulladd16 (
+    input  [15:0] x,
+    input  [15:0] y,
+    input         ci,
+    output        co,
+    output [15:0] z,
+    input         s
+  );
+
+  // Continuous assignments
+  assign {co,z} = {1'b0, x} + {s, y} + ci;
+endmodule
+"
+"module ICAP_core
+  (
+   input        fastclk,
+   input [4:0]  design_num,
+   input        reconfigure,
+   input        powerup,
+   input [3:0]  sw_in,
+   output [3:0] sw_out,
+   output [3:0] pwr_out,
+   output       initialized,
+   output [7:0] test
+   );
+
+   reg [1:0]    clk;
+   reg          reconfigure_sync;
+
+   reg [15:0]   icap_din;
+   reg          icap_ce;
+   reg          icap_wr;
+
+   wire [15:0]  icap_dout_reversed;
+   reg [15:0]   icap_dout;
+
+   reg [15:0]   ff_icap_din_reversed;
+   reg          ff_icap_ce;
+   reg          ff_icap_wr;
+
+   reg [3:0]    MBT_REBOOT = 4\'b0000;
+
+   reg [7:0]    soft_dip = 8\'b00000000;
+
+   reg test_trig;
+
+   assign test = { 8\'b0 };
+
+   assign sw_out = powerup ? sw_in : soft_dip[3:0];
+
+   assign pwr_out = powerup ? sw_in : soft_dip[7:4];
+
+   assign initialized = state == IDLE;
+
+   wire busy;
+
+   ICAP_SPARTAN6 ICAP_SPARTAN6_inst
+     (
+      .BUSY      (busy),   // Busy output
+      .O         (icap_dout_reversed),   // 16-bit data output
+      .CE        (ff_icap_ce),   // Clock enable input
+      .CLK       (clk[0]),         // Clock input
+      .I         (ff_icap_din_reversed),  // 16-bit data input
+      .WRITE     (ff_icap_wr)    // Write input
+      );
+
+
+   //  -------------------------------------------------
+   //  --  State Machine for ICAP_SPARTAN6 MultiBoot  --
+   //  --   sequence.                                 --
+   //  -------------------------------------------------
+
+
+   parameter
+
+     INIT             = 0,
+
+     RD_DUMMY         = 1,
+     RD_SYNC_H        = 2,
+     RD_SYNC_L        = 3,
+     RD_NOOP_1        = 4,
+     RD_NOOP_2        = 5,
+     RD_GEN5          = 6,
+     RD_NOOP_3        = 7,
+     RD_NOOP_4        = 8,
+     RD_NOOP_5        = 9,
+     RD_NOOP_6        = 10,
+     RD_AVOID_ABORT_1 = 11,
+     RD_AVOID_ABORT_2 = 12,
+     RD_LATCH_DATA    = 13,
+     RD_AVOID_ABORT_3 = 14,
+     RD_AVOID_ABORT_4 = 15,
+     RD_DESYNC_H      = 16,
+     RD_DESYNC_L      = 17,
+     RD_NOOP_7        = 18,
+
+     IDLE             = 19,
+     DUMMY_1          = 20,
+     DUMMY_2          = 21,
+     SYNC_H           = 22,
+     SYNC_L           = 23,
+
+     GEN1_H           = 24,
+     GEN1_L           = 25,
+
+     GEN2_H           = 26,
+     GEN2_L           = 27,
+
+     GEN5_H           = 28,
+     GEN5_L           = 29,
+
+     RBT_H            = 30,
+     RBT_L            = 31,
+
+     RBT_NOOP_0       = 32,
+     RBT_NOOP_1       = 33,
+     RBT_NOOP_2       = 34,
+     RBT_NOOP_3       = 35;
+
+   reg [5:0]    state = INIT;
+   reg [5:0]    next_state;
+
+   always @(MBT_REBOOT or state or design_num or reconfigure_sync or powerup or sw_in or busy or soft_dip)
+     begin: COMB
+
+        case (state)
+
+
+          //--------------------
+
+          INIT:
+            begin
+               next_state  = RD_DUMMY;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16\'hFFFF;  // Null data
+            end
+
+          RD_DUMMY:
+            begin
+               next_state  = RD_SYNC_H;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16\'hAA99;   // Sync word part 1
+            end
+
+          RD_SYNC_H:
+            begin
+               next_state  = RD_SYNC_L;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16\'h5566;    // Sync word part 2
+            end
+
+          RD_SYNC_L:
+            begin
+               next_state  = RD_NOOP_1;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16\'h2000;    // NOOP
+            end
+
+          RD_NOOP_1:
+            begin
+               next_state  = RD_NOOP_2;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16\'h2000;    // NOOP
+            end
+
+          RD_NOOP_2:
+            begin
+               next_state  = RD_GEN5;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16\'h2ae1;    //  Read General_5 register
+            end
+
+          RD_GEN5:
+            begin
+               next_state  = RD_NOOP_3;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16\'h2000;    //  NOOP
+            end
+
+          RD_NOOP_3:
+            begin
+               next_state  = RD_NOOP_4;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16\'h2000;    //  NOOP
+            end
+
+          RD_NOOP_4:
+            begin
+               next_state  = RD_NOOP_5;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16\'h2000;    //  NOOP
+            end
+
+          RD_NOOP_5:
+            begin
+               next_state  = RD_NOOP_6;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16\'h2000;    //  NOOP
+            end
+
+         RD_NOOP_6:
+            begin
+               next_state  = RD_AVOID_ABORT_1;
+               icap_ce     = 1;
+               icap_wr     = 0;
+               icap_din    = 16\'hffff;    // Dummy Data
+            end
+
+         RD_AVOID_ABORT_1:
+            begin
+               next_state  = RD_AVOID_ABORT_2;
+               icap_ce     = 1;
+               icap_wr     = 1;
+               icap_din    = 16\'hffff;    // Dummy Data
+            end
+
+         RD_AVOID_ABORT_2:
+            begin
+               next_state  = RD_LATCH_DATA;
+               icap_ce     = 0;
+               icap_wr     = 1;
+               icap_din    = 16\'hffff;    // Dummy Data
+            end
+
+         RD_LATCH_DATA:
+            begin
+               if (busy) begin
+                   next_state  = RD_LATCH_DATA;
+                   icap_ce     = 0;
+                   icap_wr     = 1;
+                   icap_din    = 16\'hffff;    // Dummy Data
+               end else begin
+                   next_state  = RD_AVOID_ABORT_3;
+                   icap_ce     = 1;
+                   icap_wr     = 1;
+                   icap_din    = 16\'hffff;    // Dummy Data
+               end
+            end
+
+         RD_AVOID_ABORT_3:
+            begin
+               next_state  = RD_AVOID_ABORT_4;
+               icap_ce     = 1;
+               icap_wr     = 0;
+               icap_din    = 16\'hffff;    // Dummy Data
+            end
+
+         RD_AVOID_ABORT_4:
+            begin
+               next_state  = RD_DESYNC_H;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16\'h30a1;  // Write to CMD Register
+            end
+
+          RD_DESYNC_H:
+            begin
+               next_state  = RD_DESYNC_L;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16\'h000d;  // DESYNC command
+            end
+
+          RD_DESYNC_L:
+            begin
+               next_state  = RD_NOOP_7;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16\'h2000;  // NOOP
+            end
+
+          RD_NOOP_7:
+            begin
+               next_state  = IDLE;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16\'h2000;  // NOOP
+            end
+
+          IDLE:
+            begin
+               if (reconfigure_sync) begin
+                  next_state  = DUMMY_1;
+               end else begin
+                  next_state  = IDLE;
+               end
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16\'hFFFF;  // Null data
+            end
+
+          DUMMY_1:
+            begin
+               next_state  = DUMMY_2;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16\'hFFFF;  // Null data
+            end
+
+          DUMMY_2:
+            begin
+               next_state  = SYNC_H;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16\'hAA99;   // Sync word part 1
+            end
+
+          SYNC_H:
+            begin
+               next_state  = SYNC_L;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16\'h5566;    // Sync word part 2
+            end
+
+         SYNC_L:
+            begin
+              next_state  = GEN1_H;
+              icap_ce     = 0;
+              icap_wr     = 0;
+              icap_din    = 16\'h3261;    //  Write to GENERAL_1 Register....
+            end
+
+          GEN1_H:
+            begin
+               next_state  = GEN1_L;
+               icap_ce     = 0;
+               icap_wr     = 0;
+
+               case (design_num)
+                 5\'b10000: icap_din    = 16\'h0000;
+                 5\'b00000: icap_din    = 16\'h4000;
+                 5\'b00001: icap_din    = 16\'h4000;
+                 5\'b00010: icap_din    = 16\'h4000;
+                 5\'b00011: icap_din    = 16\'h4000;
+                 5\'b00100: icap_din    = 16\'h8000;
+                 5\'b00101: icap_din    = 16\'hC000;
+                 5\'b00110: icap_din    = 16\'hC000;
+                 5\'b00111: icap_din    = 16\'hC000;
+                 5\'b01000: icap_din    = 16\'h0000;
+                 5\'b01001: icap_din    = 16\'h4000;
+                 5\'b01010: icap_din    = 16\'h8000;
+                 5\'b01011: icap_din    = 16\'hC000;
+                 5\'b01100: icap_din    = 16\'h0000;
+                 5\'b01101: icap_din    = 16\'h4000;
+                 5\'b01110: icap_din    = 16\'h8000; // The Null Co Processor
+                 5\'b01111: icap_din    = 16\'hC000;
+                 default:  icap_din    = 16\'h8000; // The Null Co Processor
+               endcase
+
+            end
+
+          GEN1_L:
+            begin
+               next_state  = GEN2_H;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16\'h3281;    //  Write to GENERAL_2 Register....
+            end
+
+          GEN2_H:
+            begin
+               next_state  = GEN2_L;
+               icap_ce     = 0;
+               icap_wr     = 0;
+
+               case (design_num)
+                 5\'b10000: icap_din    = 16\'h0300;
+                 5\'b00000: icap_din    = 16\'h0305;
+                 5\'b00001: icap_din    = 16\'h0305;
+                 5\'b00010: icap_din    = 16\'h0305;
+                 5\'b00011: icap_din    = 16\'h0305;
+                 5\'b00100: icap_din    = 16\'h030a;
+                 5\'b00101: icap_din    = 16\'h030f;
+                 5\'b00110: icap_din    = 16\'h030f;
+                 5\'b00111: icap_din    = 16\'h030f;
+                 5\'b01000: icap_din    = 16\'h0315;
+                 5\'b01001: icap_din    = 16\'h031a;
+                 5\'b01010: icap_din    = 16\'h031f;
+                 5\'b01011: icap_din    = 16\'h0324;
+                 5\'b01100: icap_din    = 16\'h032a;
+                 5\'b01101: icap_din    = 16\'h032f;
+                 5\'b01110: icap_din    = 16\'h0334; // The Null/SPI Co Processor
+                 5\'b01111: icap_din    = 16\'h0339;
+                 default:  icap_din    = 16\'h0334; // The Null/SPI Co Processor
+               endcase
+
+            end
+
+          //--------------------
+
+
+          GEN2_L:
+            begin
+               next_state  = GEN5_H;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16\'h32e1;    //  Write to GENERAL_5 Register....
+            end
+
+          GEN5_H:
+            begin
+               next_state  = GEN5_L;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din[15:8] = 8\'b0;
+               icap_din[7:4] = powerup ? sw_in : soft_dip[7:4];
+               icap_din[3:0] = powerup ? sw_in : design_num[3:0];
+            end
+
+
+          //--------------------
+
+          GEN5_L:
+            begin
+               next_state  = RBT_H;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16\'h30A1;      //  Write to Command Register....
+            end
+
+          RBT_H:
+            begin
+               next_state  = RBT_L;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16\'h000E;      // REBOOT Command issued....  value = 0x000E
+            end
+
+          //--------------------
+
+          RBT_L:
+            begin
+               next_state  = RBT_NOOP_0;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16\'h2000;    //  RBT_NOOP
+            end
+
+          RBT_NOOP_0:
+            begin
+               next_state  = RBT_NOOP_1;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16\'h2000;    // RBT_NOOP
+            end
+
+          RBT_NOOP_1:
+            begin
+               next_state  = RBT_NOOP_2;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16\'h2000;    // RBT_NOOP
+            end
+
+          RBT_NOOP_2:
+            begin
+               next_state  = RBT_NOOP_3;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16\'h2000;    // RBT_NOOP
+            end
+
+          //--------------------
+
+          RBT_NOOP_3:
+            begin
+               next_state  = IDLE;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16\'hffff;    // NULL value
+            end
+
+          default:
+            begin
+               next_state  = IDLE;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16\'hffff;    //  16\'h1111""
+            end
+
+        endcase
+     end
+
+
+   // Clock ICAP_SPARTAN6 and the state machine with clocks that are 90deg phase apart.
+   //
+   // This is an attempt to cure some reconfiguration unreliability.
+   //
+   // The problem is that ICAP_SPARTAN2 isn\'t treated by the Xilinx tools as a synchronous
+   // component, so when clocked off the same clock there can be timing issues.
+   //
+   // The below clocking patten runs the clock at 8MHz (half what it was before).
+   //
+   // It ensures there is plenty of setup and hold time margin for signals passing
+   // between ICAP_SPARTAN6 and the state machine, regardless of which clk edge is used
+   // ICAP_SPARTAN6.
+   //
+   // See this link for some related discussion:
+   // https://forums.xilinx.com/t5/Spartan-Family-FPGAs/20Mhz-limitation-for-ICAP-SPARTAN6/td-p/238060
+   //
+   // NOTE: I\'m hedging here, as this bug is quite difficult to reproduce, and changing almost anything
+   // (e.g. connecting state to the test pins) causes the problem to go away.
+   //
+   // At worst this change should be harmless!
+   //
+   // Dave Banks - 18/07/2017
+   
+   always@(posedge fastclk) begin
+      if (clk == 2\'b00)
+        clk <= 2\'b10;
+      else if (clk == 2\'b10)
+        clk <= 2\'b11;
+      else if (clk == 2\'b11)
+        clk <= 2\'b01;
+      else
+        clk <= 2\'b00;
+   end
+
+   // Give a bit of delay before starting the state machine
+   always @(posedge clk[1]) begin
+      reconfigure_sync <= reconfigure;
+      if (MBT_REBOOT == 4\'b1111) begin
+         state <= next_state;
+      end else begin
+         MBT_REBOOT <= MBT_REBOOT + 4\'b0001;
+         state <= INIT;
+      end
+      if (state == RD_LATCH_DATA) begin
+         test_trig <= 1\'b1;
+      end else begin
+         test_trig <= 1\'b0;
+      end
+      if (state == RD_LATCH_DATA && !busy) begin
+         soft_dip <= icap_dout[7:0];
+      end
+   end
+
+
+   always @(posedge clk[1]) begin:   ICAP_FF
+        // need to reverse bits to ICAP module since D0 bit is read first
+        ff_icap_din_reversed[0]  <= icap_din[7];
+        ff_icap_din_reversed[1]  <= icap_din[6];
+        ff_icap_din_reversed[2]  <= icap_din[5];
+        ff_icap_din_reversed[3]  <= icap_din[4];
+        ff_icap_din_reversed[4]  <= icap_din[3];
+        ff_icap_din_reversed[5]  <= icap_din[2];
+        ff_icap_din_reversed[6]  <= icap_din[1];
+        ff_icap_din_reversed[7]  <= icap_din[0];
+        ff_icap_din_reversed[8]  <= icap_din[15];
+        ff_icap_din_reversed[9]  <= icap_din[14];
+        ff_icap_din_reversed[10] <= icap_din[13];
+        ff_icap_din_reversed[11] <= icap_din[12];
+        ff_icap_din_reversed[12] <= icap_din[11];
+        ff_icap_din_reversed[13] <= icap_din[10];
+        ff_icap_din_reversed[14] <= icap_din[9];
+        ff_icap_din_reversed[15] <= icap_din[8];
+        ff_icap_ce  <= icap_ce;
+        ff_icap_wr  <= icap_wr;
+     end
+
+   always @(icap_dout_reversed) begin
+      // need to reverse bits to ICAP module since D0 bit is read first
+      icap_dout[0]  <= icap_dout_reversed[7];
+      icap_dout[1]  <= icap_dout_reversed[6];
+      icap_dout[2]  <= icap_dout_reversed[5];
+      icap_dout[3]  <= icap_dout_reversed[4];
+      icap_dout[4]  <= icap_dout_reversed[3];
+      icap_dout[5]  <= icap_dout_reversed[2];
+      icap_dout[6]  <= icap_dout_reversed[1];
+      icap_dout[7]  <= icap_dout_reversed[0];
+      icap_dout[8]  <= icap_dout_reversed[15];
+      icap_dout[9]  <= icap_dout_reversed[14];
+      icap_dout[10] <= icap_dout_reversed[13];
+      icap_dout[11] <= icap_dout_reversed[12];
+      icap_dout[12] <= icap_dout_reversed[11];
+      icap_dout[13] <= icap_dout_reversed[10];
+      icap_dout[14] <= icap_dout_reversed[9];
+      icap_dout[15] <= icap_dout_reversed[8];
+   end
+
+endmodule
+"
+"/*
+ *  Microcode execution stage for Zet
+ *  Copyright (C) 2008-2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+`timescale 1ns/10ps
+
+`include ""defines.v""
+
+module zet_exec (
+    input         clk,
+    input         rst,
+
+    input [`IR_SIZE-1:0] ir,
+    input [15:0]  off,
+    input [15:0]  imm,
+    output [15:0] cs,
+    output [15:0] ip,
+    output        of,
+    output        zf,
+    output        cx_zero,
+    input [15:0]  memout,
+
+    output [15:0] wr_data,
+    output [19:0] addr,
+    output        we,
+    output        m_io,
+    output        byteop,
+    input         block,
+    output        div_exc,
+    input         wrip0,
+
+    output        ifl,
+    output        tfl,
+    output        wr_ss
+  );
+
+  // Net declarations
+  wire [15:0] c;
+  wire [15:0] omemalu;
+  wire [ 3:0] addr_a;
+  wire [ 3:0] addr_c;
+  wire [ 3:0] addr_d;
+  wire [ 8:0] flags;
+  wire [15:0] a, b, s, alu_iflags, bus_b;
+  wire [31:0] aluout;
+  wire [3:0]  addr_b;
+  wire [2:0]  t, func;
+  wire [1:0]  addr_s;
+  wire        wrfl, high, memalu, r_byte, c_byte;
+  wire        wr, wr_reg;
+  wire        wr_cnd;
+  wire        jmp;
+  wire        b_imm;
+  wire  [8:0] iflags, oflags;
+  wire  [4:0] logic_flags;
+  wire        alu_word;
+  wire        a_byte;
+  wire        b_byte;
+  wire        wr_high;
+  wire        dive;
+
+  // Module instances
+  zet_alu alu( {c, a }, bus_b, aluout, t, func, alu_iflags, oflags,
+               alu_word, s, off, clk, dive);
+  zet_regfile regfile (
+        a, b, c, cs, ip, {aluout[31:16], omemalu}, s, flags, wr_reg, wrfl,
+                wr_high, clk, rst, addr_a, addr_b, addr_c, addr_d, addr_s, iflags,
+                ~byteop, a_byte, b_byte, c_byte, cx_zero, wrip0);
+  zet_jmp_cond jmp_cond (logic_flags, addr_b, addr_c[0], c, jmp);
+
+  // Assignments
+  assign addr_s = ir[1:0];
+  assign addr_a = ir[5:2];
+  assign addr_b = ir[9:6];
+  assign addr_c = ir[13:10];
+  assign addr_d = ir[17:14];
+  assign wrfl   = ir[18];
+  assign we     = ir[19];
+  assign wr     = ir[20];
+  assign wr_cnd = ir[21];
+  assign high   = ir[22];
+  assign t      = ir[25:23];
+  assign func   = ir[28:26];
+  assign byteop = ir[29];
+  assign memalu = ir[30];
+  assign m_io   = ir[32];
+  assign b_imm  = ir[33];
+  assign r_byte = ir[34];
+  assign c_byte = ir[35];
+
+  assign omemalu = memalu ? aluout[15:0] : memout;
+  assign bus_b   = b_imm ? imm : b;
+
+  assign addr = aluout[19:0];
+  assign wr_data = c;
+  assign wr_reg  = (wr | (jmp & wr_cnd)) && !block && !div_exc;
+  assign wr_high = high && !block && !div_exc;
+  assign of  = flags[8];
+  assign ifl = flags[6];
+  assign tfl = flags[5];
+  assign zf  = flags[3];
+
+  assign iflags = oflags;
+  assign alu_iflags = { 4\'b1111, flags[8:3], 1\'b0, flags[2], 1\'b0, flags[1],
+                        1\'b1, flags[0] };
+  assign logic_flags = { flags[8], flags[4], flags[3], flags[1], flags[0] };
+
+  assign alu_word = (t==3\'b011) ? ~r_byte : ~byteop;
+  assign a_byte = (t==3\'b011 && func[1]) ? 1\'b0 : r_byte;
+  assign b_byte = r_byte;
+  assign div_exc = dive && wr;
+
+  assign wr_ss = (addr_d == 4\'b1010) && wr;
+
+endmodule
+"
+"// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+// This file is part of the M32632 project\r
+// http://opencores.org/project,m32632\r
+//\r
+// Filename: ICACHE_SM.v\r
+// Version:  1.0\r
+// Date:     30 May 2015\r
+//\r
+// Copyright (C) 2015 Udo Moeller\r
+// \r
+// This source file may be used and distributed without \r
+// restriction provided that this copyright statement is not \r
+// removed from the file and that any derivative work contains \r
+// the original copyright notice and the associated disclaimer.\r
+// \r
+// This source file is free software; you can redistribute it \r
+// and/or modify it under the terms of the GNU Lesser General \r
+// Public License as published by the Free Software Foundation;\r
+// either version 2.1 of the License, or (at your option) any \r
+// later version. \r
+// \r
+// This source is distributed in the hope that it will be \r
+// useful, but WITHOUT ANY WARRANTY; without even the implied \r
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR \r
+// PURPOSE. See the GNU Lesser General Public License for more \r
+// details. \r
+// \r
+// You should have received a copy of the GNU Lesser General \r
+// Public License along with this source; if not, download it \r
+// from http://www.opencores.org/lgpl.shtml \r
+// \r
+// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\tModules contained in this file:\r
+//\t1. KOLDETECT \tCollision Detection Unit\r
+//\t2. ICACHE_SM \tInstruction Cache State Machine\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t1. KOLDETECT \tCollision Detection Unit\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module KOLDETECT ( BCLK, BRESET, DRAM_WR, CVALID, ADDR, TAG0, TAG1 , CFG , C_VALID, READ_I, ACC_OK, HOLD, KDET, INVAL_A, ENA_HK,\r
+\t\t\t\t   NEWCVAL, KOLLISION, STOP_ICRD, RUN_ICRD, KILL, KILLADR, ICTODC, STOP_CINV );\r
+\r
+\tinput\t\t\tBCLK;\r
+\tinput\t\t\tBRESET;\r
+\tinput\t\t\tDRAM_WR;\r
+\tinput\t[23:0]\tCVALID;\t\t// Data from master Valid RAM\r
+\tinput\t[27:4]\tADDR;\r
+\tinput  [27:12]\tTAG0,TAG1;\r
+\tinput\t [1:0]\tCFG;\r
+\tinput\t[23:0]\tC_VALID;\t// Data from secondary Valid RAM\r
+\tinput\t\t\tREAD_I;\r
+\tinput\t\t\tACC_OK;\r
+\tinput\t\t\tHOLD;\t\t// active low\r
+\tinput\t\t\tKDET;\r
+\tinput\t\t\tINVAL_A;\t// Cache Invalidate All\r
+\tinput\t\t\tENA_HK;\t\t// Enable HOLD and Kohaerenz\r
+\t\r
+\toutput\t[23:0]\tNEWCVAL;\r
+\toutput\t\t\tKOLLISION;\r
+\toutput\t\t\tSTOP_ICRD;\r
+\toutput\t\t\tRUN_ICRD;\r
+\toutput\t\t\tKILL;\r
+\toutput\t[11:7]\tKILLADR;\r
+\toutput\t [2:0]\tICTODC;\r
+\toutput\t\t\tSTOP_CINV;\r
+\t\r
+\treg\t\t[27:4]\taddr_r;\r
+\treg\t\t [7:0]\tmaske,clear;\r
+\treg\t\t\t\tdo_koll;\r
+\treg\t\t [2:0]\tcounter;\r
+\treg\t\t [1:0]\twpointer,rpointer;\r
+\treg\t\t[35:0]\tadrfifo;\r
+\treg\t\t [8:0]\tfifo_q,fifo_c;\r
+\treg\t\t [1:0]\tstate;\r
+\treg\t\t\t\tpipe;\r
+\treg\t\t\t\tdo_kill;\r
+\treg\t\t\t\tdma;\r
+\r
+\twire\t[7:0]\tset_0,set_1;\r
+\twire\t\t\tmatch_0,match_1;\r
+\twire\t\t\tvalid_0,valid_1;\r
+\twire\t\t\tfound_0,found_1;\r
+\twire\t\t\tkolli,dma_kolli;\r
+\twire\t\t\tlast_match;\r
+\twire\t\t\twr_entry;\r
+\twire\t[23:0]\tcdaten;\r
+\twire\t [8:0]\tkaddr;\r
+\twire\t [7:0]\tnew_0,new_1;\r
+\twire\t\t\tdma_mode,ic_dma;\r
+\twire\t\t\tfree,ende;\r
+\twire\t\t\tinit_b;\r
+\r
+\talways @(posedge BCLK) do_koll <= DRAM_WR & CFG[0];\t// one cycle pulse, without Cache Enable no collision\r
+\talways @(posedge BCLK) addr_r <= ADDR;\r
+\t\r
+\t// similar logic like in CA_MATCH\r
+\t\r
+\tassign set_0 = C_VALID[7:0];\r
+\tassign set_1 = C_VALID[15:8];\r
+\t\t\r
+\tassign valid_0 = set_0[addr_r[6:4]];\r
+\tassign valid_1 = set_1[addr_r[6:4]];\r
+\t\r
+\tassign match_0 = ( TAG0 == addr_r[27:12] );\t// 4KB\r
+\tassign match_1 = ( TAG1 == addr_r[27:12] );\t// 4KB\r
+\t\r
+\tassign found_0 = valid_0 & match_0;\r
+\tassign found_1 = valid_1 & match_1;\r
+\t\r
+\tassign kolli = (found_0 | found_1) & ~CFG[1] & do_koll;\t// Action only if ICACHE is not locked\r
+\r
+\tassign KOLLISION = (found_0 | found_1) & do_koll;\t// to Statistik Modul, Register there\r
+\r
+\tassign dma_kolli = (found_0 | found_1) & ~CFG[1] & CFG[0];\r
+\t\r
+\t// the FIFO with 4 entries :\r
+\tassign init_b = CFG[0] & ~INVAL_A;\t// initialise if CINV A too\r
+\t\r
+\talways @(posedge BCLK)\r
+\t\tif (!init_b) wpointer <= 2\'b00;\r
+\t\t\telse\r
+\t\t\t\twpointer <= wpointer + {1\'b0,wr_entry};\r
+\t\t\t\t\r
+\talways @(posedge BCLK)\r
+\t\tif (!init_b) rpointer <= 2\'b00;\r
+\t\t\telse\r
+\t\t\t\trpointer <= rpointer + {1\'b0,do_kill};\r
+\t\r
+\talways @(posedge BCLK)\r
+\t  begin\r
+\t\tif (wr_entry && (wpointer == 2\'b00)) adrfifo[8:0]   <= {addr_r[11:4],found_1};\r
+\t\tif (wr_entry && (wpointer == 2\'b01)) adrfifo[17:9]  <= {addr_r[11:4],found_1};\r
+\t\tif (wr_entry && (wpointer == 2\'b10)) adrfifo[26:18] <= {addr_r[11:4],found_1};\r
+\t\tif (wr_entry && (wpointer == 2\'b11)) adrfifo[35:27] <= {addr_r[11:4],found_1};\r
+\t  end\r
+\t\t\r
+\talways @(adrfifo or rpointer)\r
+\t\tcase (rpointer)\r
+\t\t  2\'b00 : fifo_q = adrfifo[8:0];\r
+\t\t  2\'b01 : fifo_q = adrfifo[17:9];\r
+\t\t  2\'b10 : fifo_q = adrfifo[26:18];\r
+\t\t  2\'b11 : fifo_q = adrfifo[35:27];\r
+\t\tendcase\r
+\t\t\r
+\talways @(adrfifo or wpointer)\t// for Match of last entry use wpointer\r
+\t\tcase (wpointer)\r
+\t\t  2\'b01 : fifo_c = adrfifo[8:0];\r
+\t\t  2\'b10 : fifo_c = adrfifo[17:9];\r
+\t\t  2\'b11 : fifo_c = adrfifo[26:18];\r
+\t\t  2\'b00 : fifo_c = adrfifo[35:27];\r
+\t\tendcase\r
+\t\t\r
+\t// Control\r
+\t\r
+\tassign last_match = counter[2] & (fifo_c == {addr_r[11:4],found_1});\t// if Match with last Entry no new Entry\r
+\r
+\tassign wr_entry = kolli & ~last_match;\r
+\t\r
+\talways @(posedge BCLK)\r
+\t\tcasex ({init_b,wr_entry,do_kill,counter})\r
+\t\t  6\'b0_xx_xxx : counter <= 3\'b000;\r
+\t\t  6\'b1_00_xxx : counter <= counter;\r
+\t\t  6\'b1_11_xxx : counter <= counter;\r
+\t\t  6\'b1_10_000 : counter <= 3\'b100;\r
+\t\t  6\'b1_10_1xx : counter <= (counter[1:0] == 2\'b11) ? 3\'b111 : {counter[2],(counter[1:0] + 2\'b01)};\t// Overflow avoid\r
+\t\t  6\'b1_01_1xx : counter <= (counter[1:0] == 2\'b00) ? 3\'b000 : {counter[2],(counter[1:0] + 2\'b11)};\r
+\t\t  default\t  : counter <= counter;\r
+\t\tendcase\r
+\r
+\t// DMA Access\r
+\talways @(posedge BCLK) dma <= ~HOLD;\t// there is only one FF for this , from here to DCACHE\r
+\t\r
+\t// Controlling of ICACHE\r
+\t\r
+\tassign free = (~READ_I | ACC_OK) & ENA_HK;\t// switch off if CINV\r
+\t\r
+\talways @(posedge BCLK)\t\t\t\t\t//  state[1]  state[0]\r
+\t\tcasex ({BRESET,dma,counter[2],free,ende,STOP_ICRD,dma_mode})\r
+\t\t  7\'b0_xx_xx_xx : state <= 2\'b00;\r
+\t\t  7\'b1_00_xx_00 : state <= 2\'b00;\r
+\t\t  7\'b1_01_1x_00 : state <= 2\'b10;\t// Start of DCACHE Kohaerenz\r
+\t\t  7\'b1_1x_1x_00 : state <= 2\'b11;\t// Start of DMA\r
+\t//\r
+\t\t  7\'b1_xx_x0_10 : state <= 2\'b10;\t// without ""ende"" it stays as is\r
+\t\t  7\'b1_0x_x1_10 : state <= 2\'b00;\t// DMA is not active\r
+\t\t  7\'b1_1x_x1_10 : state <= 2\'b11;\t// to DMA !\r
+\t//\r
+\t\t  7\'b1_00_xx_11 : state <= 2\'b00;\r
+\t\t  7\'b1_01_xx_11 : state <= 2\'b10;\r
+\t\t  7\'b1_1x_xx_11 : state <= 2\'b11;\r
+\t\t  default\t\t: state <= 2\'b00;\r
+\t\tendcase\r
+\t\r
+\tassign STOP_ICRD = state[1];\t// used for Multiplexer\r
+\tassign dma_mode  = state[0];\t// internal Multiplexer\r
+\r
+\tassign STOP_CINV = state[1] & ~ENA_HK;\t// stops CINV if DMA access or Kohaerenz access\r
+\t\r
+\tassign ende = (counter[1:0] == 2\'b00) & do_kill;\r
+\t\r
+\tassign ic_dma = STOP_ICRD & dma_mode;\t// Signal to DCACHE that ICACHE has stoped\r
+\t\r
+\talways @(posedge BCLK) pipe <= STOP_ICRD;\r
+\t\t\r
+\tassign RUN_ICRD = ~(STOP_ICRD | pipe);\t// Release for IC_READ\r
+\t\r
+\talways @(posedge BCLK) do_kill <= STOP_ICRD & ~dma_mode & ~do_kill;\t// Write pulse in Cache Valid RAM, 1 cycle on, 1 cycle off\r
+\t\r
+\tassign KILL = do_kill | (KDET & dma_kolli);\r
+\t\r
+\t// Valid Daten prepare : different sources for DMA and DCACHE Kohaerenz\r
+\t\r
+\tassign cdaten = dma_mode ? C_VALID : CVALID;\r
+\tassign kaddr  = dma_mode ? {addr_r[11:4],found_1} : fifo_q;\r
+\t\r
+\tassign KILLADR = kaddr[8:4];\r
+\t\r
+\talways @(kaddr)\r
+\t\tcase (kaddr[3:1])\r
+\t\t  3\'h0 : clear = 8\'hFE;\r
+\t\t  3\'h1 : clear = 8\'hFD;\r
+\t\t  3\'h2 : clear = 8\'hFB;\r
+\t\t  3\'h3 : clear = 8\'hF7;\r
+\t\t  3\'h4 : clear = 8\'hEF;\r
+\t\t  3\'h5 : clear = 8\'hDF;\r
+\t\t  3\'h6 : clear = 8\'hBF;\r
+\t\t  3\'h7 : clear = 8\'h7F;\r
+\t\tendcase\r
+\t\r
+\tassign new_0 = kaddr[0] ? cdaten[7:0] : (cdaten[7:0] & clear);\r
+\tassign new_1 = kaddr[0] ? (cdaten[15:8] & clear) : cdaten[15:8];\r
+\r
+\tassign NEWCVAL = {cdaten[23:16],new_1,new_0};\r
+\t\r
+\t// multiple signals are needed in DCACHE :\r
+\tassign ICTODC = {dma,ic_dma,~(counter[2:1] == 2\'b11)};\r
+\t\r
+endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t2. ICACHE_SM \tInstruction Cache State Machine\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module ICACHE_SM ( BCLK, BRESET, IO_SPACE, MDONE, IO_READY, MMU_HIT, CA_HIT, READ, PTE_ACC,\r
+\t\t\t\t   USE_CA, PTB_WR, PTB_SEL, USER, PROT_ERROR,\r
+\t\t\t\t   DRAM_ACC, IO_RD, IO_ACC, IC_PREQ, ACC_OK, HIT_ALL, CUPDATE, AUX_DAT, NEW_PTB, PTB_ONE );\r
+\r
+\tinput\t\t\tBCLK;\r
+\tinput\t\t\tBRESET;\r
+\tinput\t\t\tIO_SPACE;\r
+\tinput\t\t\tMDONE;\t\t// Memory Done : Feedback from DRAM Controller, BCLK aligned\r
+\tinput\t\t\tIO_READY;\r
+\tinput\t\t\tMMU_HIT,CA_HIT;\r
+\tinput\t\t\tREAD;\r
+\tinput\t\t\tPTE_ACC;\r
+\tinput\t\t\tUSE_CA;\r
+\tinput\t\t\tPTB_WR,PTB_SEL;\r
+\tinput\t\t\tUSER;\r
+\tinput\t\t\tPROT_ERROR;\r
+\t\r
+\toutput\treg\t\tDRAM_ACC,IO_RD;\r
+\toutput\t\t\tIO_ACC;\r
+\toutput\t\t\tIC_PREQ;\r
+\toutput\t\t\tACC_OK;\r
+\toutput\t\t\tHIT_ALL;\r
+\toutput\t\t\tCUPDATE;\r
+\toutput\t\t\tAUX_DAT;\r
+\toutput\treg\t\tNEW_PTB,PTB_ONE;\r
+\t\r
+\treg\t\t [3:0]\tnew_state;\r
+\treg\t\t\t\trd_done;\r
+\treg\t\t\t\tcard_flag;\r
+\treg\t\t\t\trd_rdy;\r
+\r
+\twire\t\t\tio_busy;\r
+\twire\t\t\tdram_go;\r
+\twire\t\t\trd_ende;\r
+\twire\t\t\tdo_ca_rd;\r
+\t\r
+// Cycle :\t\t\t/-\\_/-\\_/-\\_/-\\_/-\\_/-\\_/-\\_/-\\_/-\\_/-\\_\r
+// Access :\t\t\t_/-----------------------------------\\__\r
+// State Machine :  ____/----------------------------\\______\r
+//\t\t\t\t\t\t\tBusy status ...\r
+\r
+\tassign rd_ende = CA_HIT | rd_rdy;\t// CA_HIT only if Cache activ !\r
+\r
+\talways @(\t READ\t \t// only READ , global control\r
+\t\t\t  or PROT_ERROR\t// is not allowed !\r
+\t\t\t//\r
+\t\t\t  or IO_SPACE\t// indicates access in the IO_WELT\r
+\t\t\t  or io_busy\t// is already active ?\r
+\t\t\t//\r
+\t\t\t  or MMU_HIT\t// Hit in the MMU , now only a READ can be active\r
+\t\t\t  or rd_ende\t// Cache Hit\r
+\t\t\t  or DRAM_ACC\t// DRAM Access running\r
+\t\t\t//\r
+\t\t\t  or PTE_ACC )\t// PTE Access running\r
+\t\t\t//\t\t\t\t  #_#\t\t\t   #_#\t\t\t\t\t\t#_#\r
+\t\tcasex ({READ,PROT_ERROR,IO_SPACE,io_busy,MMU_HIT,rd_ende,DRAM_ACC,PTE_ACC})\r
+\t\t// MMU Miss : PTE load from memory \r
+\t\t  8\'b10_xx_0xx_0 : new_state = 4\'b0100;\t// start PTE access\r
+\t  \t// IO-Address selected : external access starts if not already BUSY\r
+\t\t  8\'b10_10_1xx_x : new_state = 4\'b0001;\r
+\t\t// DRAM Access : Cache Miss at READ\r
+\t\t  8\'b10_0x_100_x : new_state = 4\'b1010;\t// can start directly\r
+\t\t  default \t\t : new_state = 4\'b0;\r
+\t\tendcase\r
+\t\t\r
+\tassign IO_ACC   = new_state[0];\t// to load the Register for Data and Addr\r
+\tassign dram_go  = new_state[1];\r
+\tassign IC_PREQ  = new_state[2];\t// MMU to DCACHE !\r
+\tassign do_ca_rd = new_state[3];\r
+\t\r
+\tassign HIT_ALL = MMU_HIT & CA_HIT;\t// for Update ""Last-Set"" , MMU_HIT contains ZUGRIFF\r
+\t\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) card_flag <= 1\'b0;\r
+\t\t\telse card_flag <= (do_ca_rd & ~rd_rdy) | (card_flag & ~MDONE);\r
+\t\r
+\tassign CUPDATE = card_flag & USE_CA & MDONE;\t// USE_CA = ~CI & ~LDC;\r
+\t\r
+\talways @(posedge BCLK) rd_rdy <= card_flag & MDONE;\t\r
+\t\r
+\t// The cache RAM can not provide fast enough the data after an Update. In this case a secondary data path is activated\r
+\tassign AUX_DAT = rd_rdy;\r
+\t\r
+\t// DRAM Interface :\r
+\r
+\talways @(posedge BCLK) if (dram_go) DRAM_ACC <= 1\'b1;\r
+\t\t\t\t\t\t\t else\r
+\t\t\t\t\t\t\t\tDRAM_ACC <= DRAM_ACC & ~MDONE & BRESET;\r
+\t// IO Interface :\r
+\t\r
+\talways @(posedge BCLK)\r
+\t  begin\r
+\t\tif (IO_ACC) IO_RD <= READ;  else IO_RD <= IO_RD & ~IO_READY & BRESET;\r
+\t  end\r
+\t  \r
+\tassign io_busy = IO_RD | rd_done;\t// access is gone in next clock cycle, therefore blocked with ""rd_done""\r
+\t\r
+\talways @(posedge BCLK) rd_done <= READ & IO_READY;\t// For READ one clock later for data to come through\r
+\t\r
+\t// global feedback to opcode fetch unit : you can continue\r
+\t\r
+\tassign ACC_OK = IO_SPACE ? rd_done : (READ & MMU_HIT & rd_ende);\r
+\t\r
+\t// PTB1 und PTB0\r
+\t\r
+\talways @(posedge BCLK) NEW_PTB <= PTB_WR;\t\t\t// to MMU Update Block\r
+\talways @(posedge BCLK) if (PTB_WR) PTB_ONE <= PTB_SEL;\r
+\t\r
+endmodule\r
+"
+"/*
+ *  Altera Quartus II multiplier inference module
+ *  Copyright (C) 2008-2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+module zet_signmul17 (
+    input clk,
+
+    input      signed [16:0] a,
+    input      signed [16:0] b,
+    output reg signed [33:0] p
+  );
+
+  // Behaviour
+  always @(posedge clk) p <= a * b;
+endmodule
+"
+"//////////////////////////////////////////////////////////////////
+//                                                              //
+//  Wrapper for Xilinx Spartan-6 RAM Block                      //
+//                                                              //
+//  This file is part of the Amber project                      //
+//  http://www.opencores.org/project,amber                      //
+//                                                              //
+//  Description                                                 //
+//  256 words x 128 bits with a write enable per byte           //
+//                                                              //
+//  Author(s):                                                  //
+//      - Conor Santifort, csantifort.amber@gmail.com           //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+//                                                              //
+// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
+//                                                              //
+// This source file may be used and distributed without         //
+// restriction provided that this copyright statement is not    //
+// removed from the file and that any derivative work contains  //
+// the original copyright notice and the associated disclaimer. //
+//                                                              //
+// This source file is free software; you can redistribute it   //
+// and/or modify it under the terms of the GNU Lesser General   //
+// Public License as published by the Free Software Foundation; //
+// either version 2.1 of the License, or (at your option) any   //
+// later version.                                               //
+//                                                              //
+// This source is distributed in the hope that it will be       //
+// useful, but WITHOUT ANY WARRANTY; without even the implied   //
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
+// PURPOSE.  See the GNU Lesser General Public License for more //
+// details.                                                     //
+//                                                              //
+// You should have received a copy of the GNU Lesser General    //
+// Public License along with this source; if not, download it   //
+// from http://www.opencores.org/lgpl.shtml                     //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+
+
+module xs6_sram_256x128_byte_en 
+
+#(
+parameter DATA_WIDTH    = 128,
+parameter ADDRESS_WIDTH = 8
+)
+
+(
+input                           i_clk,
+input      [DATA_WIDTH-1:0]     i_write_data,
+input                           i_write_enable,
+input      [ADDRESS_WIDTH-1:0]  i_address,
+input      [DATA_WIDTH/8-1:0]   i_byte_enable,
+output     [DATA_WIDTH-1:0]     o_read_data
+
+);
+
+genvar      i;
+wire [DATA_WIDTH/8-1:0] byte_write_enable;
+
+assign byte_write_enable = {DATA_WIDTH/8{i_write_enable}} & i_byte_enable;
+
+
+generate
+    for (i=0;i<4;i=i+1) begin : u_gen
+        RAMB8BWER #(
+            .DATA_WIDTH_A        ( 36                        ),
+            .DATA_WIDTH_B        ( 36                        ),
+            .RAM_MODE            ( ""SDP""                     ),
+            .SIM_COLLISION_CHECK ( ""GENERATE_X_ONLY""         ),
+            .WRITE_MODE_A        ( ""READ_FIRST""              ),
+            .WRITE_MODE_B        ( ""READ_FIRST""              )
+         ) 
+        u_ramb8bwer (
+            .CLKAWRCLK      ( i_clk                          ),     
+            .CLKBRDCLK      ( i_clk                          ),
+            .ADDRAWRADDR    ( {i_address, 5\'d0}              ),
+            .ADDRBRDADDR    ( {i_address, 5\'d0}              ),
+            .ENAWREN        ( i_write_enable                 ),       
+            .ENBRDEN        ( ~i_write_enable                ),
+            
+            // Port A is lower 2 bytes
+            .WEAWEL         ( byte_write_enable[4*i+1:4*i+0] ),  
+            .DIADI          ( i_write_data[32*i+15:32*i+ 0]  ), 
+            .DOADO          ( o_read_data [32*i+15:32*i+ 0]  ),
+            
+            // Port B is upper 2 bytes
+            .WEBWEU         ( byte_write_enable[4*i+3:4*i+2] ),
+            .DIBDI          ( i_write_data[32*i+31:32*i+16]  ),
+            .DOBDO          ( o_read_data [32*i+31:32*i+16]  ),
+
+            // These guys are not used, so they are just tied off
+            // ----------------------------------------------------
+            .DIPBDIP        ( 2\'d0                           ),
+            .DIPADIP        ( 2\'d0                           ),      
+            .DOPADOP        (                                ),
+            .DOPBDOP        (                                ),
+          
+            .REGCEA         ( 1\'d0                           ),
+            .REGCEBREGCE    ( 1\'d0                           ),
+            .RSTA           ( 1\'d0                           ),
+            .RSTBRST        ( 1\'d0                           )
+        );
+
+    end
+endgenerate
+
+//synopsys translate_off
+initial
+    begin
+    if ( DATA_WIDTH    != 128 ) $display(""%M Warning: Incorrect parameter DATA_WIDTH"");
+    if ( ADDRESS_WIDTH != 8   ) $display(""%M Warning: Incorrect parameter ADDRESS_WIDTH"");
+    end
+//synopsys translate_on
+
+endmodule
+
+"
+"//////////////////////////////////////////////////////////////////
+//                                                              //
+//  Register Bank for Amber Core                                //
+//                                                              //
+//  This file is part of the Amber project                      //
+//  http://www.opencores.org/project,amber                      //
+//                                                              //
+//  Description                                                 //
+//  Contains 37 32-bit registers, 16 of which are visible       //
+//  ina any one operating mode. Registers use real flipflops,   //
+//  rather than SRAM. This makes sense for an FPGA              //
+//  implementation, where flipflops are plentiful.              //
+//                                                              //
+//  Author(s):                                                  //
+//      - Conor Santifort, csantifort.amber@gmail.com           //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+//                                                              //
+// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
+//                                                              //
+// This source file may be used and distributed without         //
+// restriction provided that this copyright statement is not    //
+// removed from the file and that any derivative work contains  //
+// the original copyright notice and the associated disclaimer. //
+//                                                              //
+// This source file is free software; you can redistribute it   //
+// and/or modify it under the terms of the GNU Lesser General   //
+// Public License as published by the Free Software Foundation; //
+// either version 2.1 of the License, or (at your option) any   //
+// later version.                                               //
+//                                                              //
+// This source is distributed in the hope that it will be       //
+// useful, but WITHOUT ANY WARRANTY; without even the implied   //
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
+// PURPOSE.  See the GNU Lesser General Public License for more //
+// details.                                                     //
+//                                                              //
+// You should have received a copy of the GNU Lesser General    //
+// Public License along with this source; if not, download it   //
+// from http://www.opencores.org/lgpl.shtml                     //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+
+module a23_register_bank (
+
+input                       i_clk,
+input                       i_fetch_stall,
+
+input       [1:0]           i_mode_idec,            // user, supervisor, irq_idec, firq_idec etc.
+                                                    // Used for register writes
+input       [1:0]           i_mode_exec,            // 1 periods delayed from i_mode_idec
+                                                    // Used for register reads
+input       [3:0]           i_mode_rds_exec,        // Use one-hot version specifically for rds, 
+                                                    // includes i_user_mode_regs_store
+input                       i_user_mode_regs_load,
+input                       i_firq_not_user_mode,
+input       [3:0]           i_rm_sel,
+input       [3:0]           i_rds_sel,
+input       [3:0]           i_rn_sel,
+
+input                       i_pc_wen,
+input       [14:0]          i_reg_bank_wen,
+
+input       [23:0]          i_pc,                   // program counter [25:2]
+input       [31:0]          i_reg,
+
+input       [3:0]           i_status_bits_flags,
+input                       i_status_bits_irq_mask,
+input                       i_status_bits_firq_mask,
+
+output      [31:0]          o_rm,
+output reg  [31:0]          o_rs,
+output reg  [31:0]          o_rd,
+output      [31:0]          o_rn,
+output      [31:0]          o_pc
+
+);
+
+`include ""a23_localparams.vh""
+`include ""a23_functions.vh""
+
+
+// User Mode Registers
+reg  [31:0] r0  = 32\'hdead_beef;
+reg  [31:0] r1  = 32\'hdead_beef;
+reg  [31:0] r2  = 32\'hdead_beef;
+reg  [31:0] r3  = 32\'hdead_beef;
+reg  [31:0] r4  = 32\'hdead_beef;
+reg  [31:0] r5  = 32\'hdead_beef;
+reg  [31:0] r6  = 32\'hdead_beef;
+reg  [31:0] r7  = 32\'hdead_beef;
+reg  [31:0] r8  = 32\'hdead_beef;
+reg  [31:0] r9  = 32\'hdead_beef;
+reg  [31:0] r10 = 32\'hdead_beef;
+reg  [31:0] r11 = 32\'hdead_beef;
+reg  [31:0] r12 = 32\'hdead_beef;
+reg  [31:0] r13 = 32\'hdead_beef;
+reg  [31:0] r14 = 32\'hdead_beef;
+reg  [23:0] r15 = 24\'hc0_ffee;
+
+wire  [31:0] r0_out;
+wire  [31:0] r1_out;
+wire  [31:0] r2_out;
+wire  [31:0] r3_out;
+wire  [31:0] r4_out;
+wire  [31:0] r5_out;
+wire  [31:0] r6_out;
+wire  [31:0] r7_out;
+wire  [31:0] r8_out;
+wire  [31:0] r9_out;
+wire  [31:0] r10_out;
+wire  [31:0] r11_out;
+wire  [31:0] r12_out;
+wire  [31:0] r13_out;
+wire  [31:0] r14_out;
+wire  [31:0] r15_out_rm;
+wire  [31:0] r15_out_rm_nxt;
+wire  [31:0] r15_out_rn;
+
+wire  [31:0] r8_rds;
+wire  [31:0] r9_rds;
+wire  [31:0] r10_rds;
+wire  [31:0] r11_rds;
+wire  [31:0] r12_rds;
+wire  [31:0] r13_rds;
+wire  [31:0] r14_rds;
+
+// Supervisor Mode Registers
+reg  [31:0] r13_svc = 32\'hdead_beef;
+reg  [31:0] r14_svc = 32\'hdead_beef;
+
+// Interrupt Mode Registers
+reg  [31:0] r13_irq = 32\'hdead_beef;
+reg  [31:0] r14_irq = 32\'hdead_beef;
+
+// Fast Interrupt Mode Registers
+reg  [31:0] r8_firq  = 32\'hdead_beef;
+reg  [31:0] r9_firq  = 32\'hdead_beef;
+reg  [31:0] r10_firq = 32\'hdead_beef;
+reg  [31:0] r11_firq = 32\'hdead_beef;
+reg  [31:0] r12_firq = 32\'hdead_beef;
+reg  [31:0] r13_firq = 32\'hdead_beef;
+reg  [31:0] r14_firq = 32\'hdead_beef;
+
+wire        usr_exec;
+wire        svc_exec;
+wire        irq_exec;
+wire        firq_exec;
+
+wire        usr_idec;
+wire        svc_idec;
+wire        irq_idec;
+wire        firq_idec;
+
+    // Write Enables from execute stage
+assign usr_idec  =  i_user_mode_regs_load || i_mode_idec == USR;
+assign svc_idec  = !i_user_mode_regs_load && i_mode_idec == SVC;
+assign irq_idec  = !i_user_mode_regs_load && i_mode_idec == IRQ;
+
+// pre-encoded in decode stage to speed up long path
+assign firq_idec = i_firq_not_user_mode;
+
+    // Read Enables from stage 1 (fetch)
+assign usr_exec  = i_mode_exec == USR;
+assign svc_exec  = i_mode_exec == SVC;
+assign irq_exec  = i_mode_exec == IRQ;
+assign firq_exec = i_mode_exec == FIRQ;
+
+
+// ========================================================
+// Register Update
+// ========================================================
+always @ ( posedge i_clk )
+    if (!i_fetch_stall)
+        begin
+        r0       <=  i_reg_bank_wen[0 ]              ? i_reg : r0;  
+        r1       <=  i_reg_bank_wen[1 ]              ? i_reg : r1;  
+        r2       <=  i_reg_bank_wen[2 ]              ? i_reg : r2;  
+        r3       <=  i_reg_bank_wen[3 ]              ? i_reg : r3;  
+        r4       <=  i_reg_bank_wen[4 ]              ? i_reg : r4;  
+        r5       <=  i_reg_bank_wen[5 ]              ? i_reg : r5;  
+        r6       <=  i_reg_bank_wen[6 ]              ? i_reg : r6;  
+        r7       <=  i_reg_bank_wen[7 ]              ? i_reg : r7;  
+        
+        r8       <= (i_reg_bank_wen[8 ] && !firq_idec) ? i_reg : r8;  
+        r9       <= (i_reg_bank_wen[9 ] && !firq_idec) ? i_reg : r9;  
+        r10      <= (i_reg_bank_wen[10] && !firq_idec) ? i_reg : r10; 
+        r11      <= (i_reg_bank_wen[11] && !firq_idec) ? i_reg : r11; 
+        r12      <= (i_reg_bank_wen[12] && !firq_idec) ? i_reg : r12; 
+        
+        r8_firq  <= (i_reg_bank_wen[8 ] &&  firq_idec) ? i_reg : r8_firq;
+        r9_firq  <= (i_reg_bank_wen[9 ] &&  firq_idec) ? i_reg : r9_firq;
+        r10_firq <= (i_reg_bank_wen[10] &&  firq_idec) ? i_reg : r10_firq;
+        r11_firq <= (i_reg_bank_wen[11] &&  firq_idec) ? i_reg : r11_firq;
+        r12_firq <= (i_reg_bank_wen[12] &&  firq_idec) ? i_reg : r12_firq;
+
+        r13      <= (i_reg_bank_wen[13] &&  usr_idec)  ? i_reg : r13;
+        r14      <= (i_reg_bank_wen[14] &&  usr_idec)  ? i_reg : r14;
+     
+        r13_svc  <= (i_reg_bank_wen[13] &&  svc_idec)  ? i_reg : r13_svc;
+        r14_svc  <= (i_reg_bank_wen[14] &&  svc_idec)  ? i_reg : r14_svc;   
+       
+        r13_irq  <= (i_reg_bank_wen[13] &&  irq_idec)  ? i_reg : r13_irq;
+        r14_irq  <= (i_reg_bank_wen[14] &&  irq_idec)  ? i_reg : r14_irq;       
+      
+        r13_firq <= (i_reg_bank_wen[13] &&  firq_idec) ? i_reg : r13_firq;
+        r14_firq <= (i_reg_bank_wen[14] &&  firq_idec) ? i_reg : r14_firq;  
+        
+        r15      <=  i_pc_wen                          ?  i_pc : r15;
+        end
+    
+    
+// ========================================================
+// Register Read based on Mode
+// ========================================================
+assign r0_out = r0;
+assign r1_out = r1;
+assign r2_out = r2;
+assign r3_out = r3;
+assign r4_out = r4;
+assign r5_out = r5;
+assign r6_out = r6;
+assign r7_out = r7;
+
+assign r8_out  = firq_exec ? r8_firq  : r8;
+assign r9_out  = firq_exec ? r9_firq  : r9;
+assign r10_out = firq_exec ? r10_firq : r10;
+assign r11_out = firq_exec ? r11_firq : r11;
+assign r12_out = firq_exec ? r12_firq : r12;
+
+assign r13_out = usr_exec ? r13      :
+                 svc_exec ? r13_svc  :
+                 irq_exec ? r13_irq  :
+                          r13_firq ;
+                       
+assign r14_out = usr_exec ? r14      :
+                 svc_exec ? r14_svc  :
+                 irq_exec ? r14_irq  :
+                          r14_firq ;
+ 
+
+assign r15_out_rm     = { i_status_bits_flags, 
+                          i_status_bits_irq_mask, 
+                          i_status_bits_firq_mask, 
+                          r15, 
+                          i_mode_exec};
+
+assign r15_out_rm_nxt = { i_status_bits_flags, 
+                          i_status_bits_irq_mask, 
+                          i_status_bits_firq_mask, 
+                          i_pc, 
+                          i_mode_exec};
+                      
+assign r15_out_rn     = {6\'d0, r15, 2\'d0};
+
+
+// rds outputs
+assign r8_rds  = i_mode_rds_exec[OH_FIRQ] ? r8_firq  : r8;
+assign r9_rds  = i_mode_rds_exec[OH_FIRQ] ? r9_firq  : r9;
+assign r10_rds = i_mode_rds_exec[OH_FIRQ] ? r10_firq : r10;
+assign r11_rds = i_mode_rds_exec[OH_FIRQ] ? r11_firq : r11;
+assign r12_rds = i_mode_rds_exec[OH_FIRQ] ? r12_firq : r12;
+
+assign r13_rds = i_mode_rds_exec[OH_USR]  ? r13      :
+                 i_mode_rds_exec[OH_SVC]  ? r13_svc  :
+                 i_mode_rds_exec[OH_IRQ]  ? r13_irq  :
+                                            r13_firq ;
+                       
+assign r14_rds = i_mode_rds_exec[OH_USR]  ? r14      :
+                 i_mode_rds_exec[OH_SVC]  ? r14_svc  :
+                 i_mode_rds_exec[OH_IRQ]  ? r14_irq  :
+                                            r14_firq ;
+
+// ========================================================
+// Program Counter out
+// ========================================================
+assign o_pc = r15_out_rn;
+
+// ========================================================
+// Rm Selector
+// ========================================================
+assign o_rm = i_rm_sel == 4\'d0  ? r0_out  :
+              i_rm_sel == 4\'d1  ? r1_out  : 
+              i_rm_sel == 4\'d2  ? r2_out  : 
+              i_rm_sel == 4\'d3  ? r3_out  : 
+              i_rm_sel == 4\'d4  ? r4_out  : 
+              i_rm_sel == 4\'d5  ? r5_out  : 
+              i_rm_sel == 4\'d6  ? r6_out  : 
+              i_rm_sel == 4\'d7  ? r7_out  : 
+              i_rm_sel == 4\'d8  ? r8_out  : 
+              i_rm_sel == 4\'d9  ? r9_out  : 
+              i_rm_sel == 4\'d10 ? r10_out : 
+              i_rm_sel == 4\'d11 ? r11_out : 
+              i_rm_sel == 4\'d12 ? r12_out : 
+              i_rm_sel == 4\'d13 ? r13_out : 
+              i_rm_sel == 4\'d14 ? r14_out : 
+                                  r15_out_rm ; 
+
+
+
+
+// ========================================================
+// Rds Selector
+// ========================================================
+always @*
+    case (i_rds_sel)
+       4\'d0  :  o_rs = r0_out  ;
+       4\'d1  :  o_rs = r1_out  ; 
+       4\'d2  :  o_rs = r2_out  ; 
+       4\'d3  :  o_rs = r3_out  ; 
+       4\'d4  :  o_rs = r4_out  ; 
+       4\'d5  :  o_rs = r5_out  ; 
+       4\'d6  :  o_rs = r6_out  ; 
+       4\'d7  :  o_rs = r7_out  ; 
+       4\'d8  :  o_rs = r8_rds  ; 
+       4\'d9  :  o_rs = r9_rds  ; 
+       4\'d10 :  o_rs = r10_rds ; 
+       4\'d11 :  o_rs = r11_rds ; 
+       4\'d12 :  o_rs = r12_rds ; 
+       4\'d13 :  o_rs = r13_rds ; 
+       4\'d14 :  o_rs = r14_rds ; 
+       default: o_rs = r15_out_rn ; 
+    endcase
+
+                                    
+
+// ========================================================
+// Rd Selector
+// ========================================================
+always @*
+    case (i_rds_sel)
+       4\'d0  :  o_rd = r0_out  ;
+       4\'d1  :  o_rd = r1_out  ; 
+       4\'d2  :  o_rd = r2_out  ; 
+       4\'d3  :  o_rd = r3_out  ; 
+       4\'d4  :  o_rd = r4_out  ; 
+       4\'d5  :  o_rd = r5_out  ; 
+       4\'d6  :  o_rd = r6_out  ; 
+       4\'d7  :  o_rd = r7_out  ; 
+       4\'d8  :  o_rd = r8_rds  ; 
+       4\'d9  :  o_rd = r9_rds  ; 
+       4\'d10 :  o_rd = r10_rds ; 
+       4\'d11 :  o_rd = r11_rds ; 
+       4\'d12 :  o_rd = r12_rds ; 
+       4\'d13 :  o_rd = r13_rds ; 
+       4\'d14 :  o_rd = r14_rds ; 
+       default: o_rd = r15_out_rm_nxt ; 
+    endcase
+
+                                    
+// ========================================================
+// Rn Selector
+// ========================================================
+assign o_rn = i_rn_sel == 4\'d0  ? r0_out  :
+              i_rn_sel == 4\'d1  ? r1_out  : 
+              i_rn_sel == 4\'d2  ? r2_out  : 
+              i_rn_sel == 4\'d3  ? r3_out  : 
+              i_rn_sel == 4\'d4  ? r4_out  : 
+              i_rn_sel == 4\'d5  ? r5_out  : 
+              i_rn_sel == 4\'d6  ? r6_out  : 
+              i_rn_sel == 4\'d7  ? r7_out  : 
+              i_rn_sel == 4\'d8  ? r8_out  : 
+              i_rn_sel == 4\'d9  ? r9_out  : 
+              i_rn_sel == 4\'d10 ? r10_out : 
+              i_rn_sel == 4\'d11 ? r11_out : 
+              i_rn_sel == 4\'d12 ? r12_out : 
+              i_rn_sel == 4\'d13 ? r13_out : 
+              i_rn_sel == 4\'d14 ? r14_out : 
+                                  r15_out_rn ; 
+
+
+endmodule
+
+
+"
+"//----------------------------------------------------------------------------
+// Wishbone SRAM controller
+//----------------------------------------------------------------------------
+module wb_sram16 #(
+        parameter                  adr_width = 19,   
+        parameter                  latency   = 0    // 0 .. 7
+) (
+        input                      clk,
+        input                      reset,
+        // Wishbone interface
+        input                      wb_stb_i,
+        input                      wb_cyc_i,
+        input                      wb_tga_i,
+        output reg                 wb_ack_o,
+        input                      wb_we_i,
+        input               [18:0] wb_adr_i,
+        input                [1:0] wb_sel_i,
+        input               [15:0] wb_dat_i,
+        output reg          [15:0] wb_dat_o,
+        // SRAM connection
+        output reg [adr_width-1:0] sram_adr,
+        inout               [15:0] sram_dat,
+        output reg           [1:0] sram_be_n,    // Byte   Enable
+        output reg                 sram_ce_n,    // Chip   Enable
+        output reg                 sram_oe_n,    // Output Enable
+        output reg                 sram_we_n     // Write  Enable
+);
+
+//----------------------------------------------------------------------------
+//
+//----------------------------------------------------------------------------
+
+// Wishbone handling
+wire wb_rd = wb_stb_i & wb_cyc_i & ~wb_we_i & ~wb_ack_o;
+wire wb_wr = wb_stb_i & wb_cyc_i &  wb_we_i & ~wb_ack_o;
+
+// Translate wishbone address to sram address
+wire [adr_width-1:0] adr = wb_adr_i[adr_width-1:0];
+
+// Tri-State-Driver
+reg [15:0] wdat;
+reg        wdat_oe;
+
+assign sram_dat = wdat_oe ? wdat : 16'bz;
+
+
+// Latency countdown
+reg  [2:0] lcount;
+
+//----------------------------------------------------------------------------
+// State Machine
+//----------------------------------------------------------------------------
+parameter s_idle   = 0;
+parameter s_read   = 1;
+parameter s_write  = 2;
+
+reg [2:0] state;
+
+always @(posedge clk)
+begin
+        if (reset) begin
+                state    <= s_idle;
+                lcount   <= 0;
+                wb_ack_o <= 0;
+        end else begin
+                case (state)
+                s_idle: begin
+                        wb_ack_o <= 0;
+
+                        if (wb_rd) begin
+                                sram_ce_n  <=  0;
+                                sram_oe_n  <=  0;
+                                sram_we_n  <=  1;
+                                sram_adr   <=  adr;
+                                sram_be_n  <=  2'b00;
+                                wdat_oe    <=  0;
+                                lcount     <=  latency;
+                                state      <=  s_read;
+                        end else if (wb_wr) begin
+                                sram_ce_n  <=  0;
+                                sram_oe_n  <=  1;
+                                sram_we_n  <=  0;
+                                sram_adr   <=  adr;
+                                sram_be_n  <= ~wb_sel_i;
+                                wdat       <=  wb_dat_i;
+                                wdat_oe    <=  1;
+                                lcount     <=  latency;
+                                state      <=  s_write;
+                        end else begin
+                                sram_ce_n  <=  1;
+                                sram_oe_n  <=  1;
+                                sram_we_n  <=  1;
+                                wdat_oe    <=  0;
+                        end
+                end
+                s_read: begin
+                        if (lcount != 0) begin
+                                lcount     <= lcount - 1;
+                        end else begin
+                                sram_ce_n  <=  1;
+                                sram_oe_n  <=  1;
+                                sram_we_n  <=  1;
+                                wb_dat_o   <=  sram_dat;
+                                wb_ack_o   <=  1;
+                                state      <=  s_idle;
+                        end
+                end
+                s_write: begin
+                        if (lcount != 0) begin
+                                lcount     <= lcount - 1;
+                        end else begin
+                                sram_ce_n  <=  1;
+                                sram_oe_n  <=  1;
+                                sram_we_n  <=  1;
+                                wb_ack_o   <=  1;       // XXX   We could acknoledge write  XXX
+                                state      <=  s_idle;  // XXX   requests 1 cycle ahead     XXX
+                        end
+                end
+                endcase
+        end
+end
+
+endmodule
+"
+"// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+// This file is part of the M32632 project\r
+// http://opencores.org/project,m32632\r
+//\r
+// Filename: M32632.v\r
+// Version:  1.1 bug fix\r
+// History:  1.0 first release of 30 Mai 2015\r
+// Date:     7 October 2015\r
+//\r
+// Copyright (C) 2015 Udo Moeller\r
+// \r
+// This source file may be used and distributed without \r
+// restriction provided that this copyright statement is not \r
+// removed from the file and that any derivative work contains \r
+// the original copyright notice and the associated disclaimer.\r
+// \r
+// This source file is free software; you can redistribute it \r
+// and/or modify it under the terms of the GNU Lesser General \r
+// Public License as published by the Free Software Foundation;\r
+// either version 2.1 of the License, or (at your option) any \r
+// later version. \r
+// \r
+// This source is distributed in the hope that it will be \r
+// useful, but WITHOUT ANY WARRANTY; without even the implied \r
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR \r
+// PURPOSE. See the GNU Lesser General Public License for more \r
+// details. \r
+// \r
+// You should have received a copy of the GNU Lesser General \r
+// Public License along with this source; if not, download it \r
+// from http://www.opencores.org/lgpl.shtml \r
+// \r
+// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\tModules contained in this file:\r
+//\tM32632\t\tThe top level of M32632\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+module M32632( BCLK, MCLK, WRCFG, BRESET, NMI_N, INT_N, STATUS, ILO, STATSIGS,\r
+\t\t\t   IO_WR, IO_RD, IO_A, IO_BE, IO_DI, IO_Q, IO_READY,\r
+\t\t\t   ENDRAM, IC_MDONE, DC_MDONE, ENWR, WAMUX, WADDR, DRAM_Q, DWCTRL, IWCTRL,\r
+\t\t\t   IC_ACC, IDRAM_ADR, DC_ACC, DC_WR, DRAM_ADR, DRAM_DI,\r
+\t\t\t   HOLD, HLDA, FILLRAM, DMA_AA,\r
+\t\t\t   COP_GO, COP_OP, COP_OUT, COP_DONE, COP_IN );\r
+\r
+// ++++++++++ Basic Signals\r
+input\t\t\tBCLK;\t// Basic Clock for everything\r
+input\t\t\tMCLK;\t// Memory Clock, used in Caches\r
+input\t\t\tWRCFG;\r
+input\t\t\tBRESET;\r
+input\t\t\tNMI_N;\r
+input\t\t\tINT_N;\r
+output\t [3:0]\tSTATUS;\r
+output\t\t\tILO;\r
+output\t [7:0]\tSTATSIGS;\r
+// +++++++++ General Purpose Interface\r
+output\t\t\tIO_WR;\r
+output\t\t\tIO_RD;\r
+output\t[31:0]\tIO_A;\r
+output\t [3:0]\tIO_BE;\r
+output\t[31:0]\tIO_DI;\r
+input\t[31:0]\tIO_Q;\r
+input\t\t\tIO_READY;\r
+// +++++++++ DRAM Interface In\r
+input\t\t\tENDRAM;\r
+input\t\t\tIC_MDONE;\r
+input\t\t\tDC_MDONE;\r
+input\t\t\tENWR;\r
+input\t\t\tWAMUX;\r
+input\t[11:2]\tWADDR;\r
+input\t[31:0]\tDRAM_Q;\r
+input\t [2:0]\tDWCTRL;\r
+input\t [2:0]\tIWCTRL;\r
+// +++++++++ DRAM Interface Out\r
+output\t\t\tIC_ACC;\r
+output\t[27:0]\tIDRAM_ADR;\r
+output\t\t\tDC_ACC;\r
+output\t\t\tDC_WR;\r
+output\t[27:0]\tDRAM_ADR;\r
+output\t[35:0]\tDRAM_DI;\r
+// ++++++++++ DMA Interface\r
+input\t\t\tHOLD;\r
+output\t\t\tHLDA;\r
+input\t\t\tFILLRAM;\r
+input\t[27:4]\tDMA_AA;\r
+// ++++++++++ Coprocessor Interface\r
+output\t\t\tCOP_GO;\r
+output\t[23:0]\tCOP_OP;\r
+output [127:0]\tCOP_OUT;\r
+input\t\t\tCOP_DONE;\r
+input\t[63:0]\tCOP_IN;\r
+\r
+wire\t\t\tACC_DONE;\r
+wire\t [5:0]\tACC_STAT;\r
+wire\t[12:0]\tCFG;\r
+wire\t [3:0]\tCINV;\r
+wire\t\t\tDATA_HOLD;\r
+wire\t\t\tDC_INIT;\r
+wire\t\t\tY_INIT;\r
+wire\t\t\tDONE;\r
+wire\t[63:0]\tDP_Q;\r
+wire\t [3:0]\tIACC_STAT;\r
+wire\t\t\tPROT_ERROR;\r
+wire\t [2:0]\tGENSTAT;\r
+wire\t\t\tIC_INIT;\r
+wire\t\t\tIC_PREQ;\r
+wire\t\t\tIC_READ;\r
+wire\t [1:0]\tIC_SIGS;\r
+wire\t\t\tIC_USER;\r
+wire   [31:12]\tIC_VA;\r
+wire\t [3:0]\tICTODC;\r
+wire\t [6:0]\tINFO_AU;\r
+wire\t [1:0]\tIVAR;\r
+wire\t\t\tKDET;\r
+wire\t[27:4]\tKOLLI_A;\r
+wire\t [3:0]\tMCR;\r
+wire\t[23:0]\tMMU_DIN;\r
+wire\t[11:0]\tPSR;\r
+wire\t\t\tPTB_SEL;\r
+wire\t\t\tPTB_WR;\r
+wire\t\t\tREAD;\r
+wire\t\t\tWRITE;\r
+wire\t\t\tZTEST;\r
+wire\t\t\tRMW;\r
+wire\t\t\tQWATWO;\r
+wire\t [2:0]\tRWVAL;\r
+wire\t\t\tRWVFLAG;\r
+wire\t [3:0]\tD_IOBE;\r
+wire\t\t\tD_IORDY;\r
+wire\t\t\tREG_OUT;\r
+wire\t [3:0]\tPACKET;\r
+wire\t [1:0]\tSIZE;\r
+wire\t[31:0]\tVADR;\r
+wire\t\t\tWREN_REG;\r
+wire\t\t\tLD_DIN;\r
+wire\t\t\tLD_IMME;\r
+wire\t\t\tWR_REG;\r
+wire\t[14:0]\tACC_FELD;\r
+wire\t[31:0]\tDIN;\r
+wire\t[31:0]\tDISP;\r
+wire\t [2:0]\tIC_TEX;\r
+wire\t[31:0]\tIMME_Q;\r
+wire\t [1:0]\tLD_OUT;\r
+wire\t[12:0]\tDETOIP;\r
+wire\t [1:0]\tMMU_UPDATE;\r
+wire\t[10:0]\tOPER;\r
+wire\t[31:0]\tPC_ARCHI;\r
+wire\t[31:0]\tPC_ICACHE;\r
+wire\t [7:0]\tRDAA;\r
+wire\t [7:0]\tRDAB;\r
+wire\t [1:0]\tSTART;\r
+wire\t [1:0]\tWMASKE;\r
+wire\t [5:0]\tWRADR;\r
+wire\t\t\tI_IORDY;\r
+wire\t\t\tACB_ZERO;\r
+wire\t\t\tDC_ABORT;\r
+wire\t\t\tSAVE_PC;\r
+wire\t[31:0]\tIC_DIN;\r
+wire\t[31:0]\tPC_NEW;\r
+wire\t [4:0]\tSTRING;\r
+wire\t [5:0]\tTRAPS;\r
+wire\t\t\tI_IORD;\r
+wire\t\t\tD_IOWR;\r
+wire\t\t\tD_IORD;\r
+wire\t[31:0]\tD_IOA;\r
+wire\t[31:0]\tI_IOA;\r
+wire\t\t\tENA_HK;\r
+wire\t\t\tSTOP_CINV;\r
+wire\t\t\tKOLLISION;\r
+wire\t\t\tILO_SIG;\r
+wire\t [1:0]\tPTE_STAT;\r
+wire\t\t\tDBG_HIT;\r
+wire\t[40:2]\tDBG_IN;\r
+
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//            The Data Cache\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+DCACHE\tARMS(\r
+\t.MCLK(MCLK),\r
+\t.BCLK(BCLK),\r
+\t.WRCFG(WRCFG),\r
+\t.BRESET(BRESET),\r
+\t.PTB_WR(PTB_WR),\r
+\t.PTB_SEL(PTB_SEL),\r
+\t.MDONE(DC_MDONE),\r
+\t.IO_READY(D_IORDY),\r
+\t.REG_OUT(REG_OUT),\r
+\t.PSR_USER(INFO_AU[1]),\r
+\t.WRITE(WRITE),\r
+\t.READ(READ),\r
+\t.ZTEST(ZTEST),\r
+\t.RMW(RMW),\r
+\t.QWATWO(QWATWO),\r
+\t.WAMUX(WAMUX),\r
+\t.ENWR(ENWR),\r
+\t.IC_PREQ(IC_PREQ),\r
+\t.FILLRAM(FILLRAM),\r
+//\t.CFG(CFG[10:9]),\r
+\t.CFG(2'b00),\r
+\t.ENDRAM(ENDRAM),\r
+\t.CINVAL(CINV[1:0]),\r
+\t.DMA_AA(DMA_AA),\r
+\t.DP_Q(DP_Q),\r
+\t.DRAM_Q(DRAM_Q),\r
+\t.IC_VA(IC_VA),\r
+\t.ICTODC(ICTODC),\r
+\t.IO_Q(IO_Q),\r
+\t.IVAR(IVAR),\r
+//\t.MCR_FLAGS(MCR),\r
+\t.MCR_FLAGS(4'b0),\r
+\t.PACKET(PACKET),\r
+\t.SIZE(SIZE),\r
+\t.VADR(VADR),\r
+\t.WADDR(WADDR),\r
+\t.WCTRL(DWCTRL),\r
+\t.DRAM_ACC(DC_ACC),\r
+\t.DRAM_WR(DC_WR),\r
+\t.IO_RD(D_IORD),\r
+\t.IO_WR(D_IOWR),\r
+\t.INIT_RUN(DC_INIT),\r
+\t.KDET(KDET),\r
+\t.HLDA(HLDA),\r
+\t.ACC_STAT(ACC_STAT),\r
+\t.DP_DI(DIN),\r
+\t.DRAM_A(DRAM_ADR),\r
+\t.DRAM_DI(DRAM_DI),\r
+\t.IACC_STAT(IACC_STAT[3:1]),\r
+\t.IC_SIGS(IC_SIGS),\r
+\t.IO_A(D_IOA),\r
+\t.IO_BE(D_IOBE),\r
+\t.IO_DI(IO_DI),\r
+\t.PTE_STAT(PTE_STAT),\r
+\t.DBG_HIT(DBG_HIT),\r
+\t.DBG_IN(DBG_IN),\r
+\t.KOLLI_A(KOLLI_A),\r
+\t.MMU_DIN(MMU_DIN),\r
+\t.RWVAL(RWVAL),\r
+\t.RWVFLAG(RWVFLAG));\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//            The Datapath\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+DATENPFAD\tSTOMACH(\r
+\t.WREN(WREN_REG),\r
+\t.BRESET(BRESET),\r
+\t.BCLK(BCLK),\r
+\t.IO_READY(D_IORDY),\r
+\t.LD_DIN(LD_DIN),\r
+\t.LD_IMME(LD_IMME),\r
+\t.WR_REG(WR_REG),\r
+\t.IC_USER(IC_USER),\r
+\t.ACC_FELD(ACC_FELD),\r
+\t.ACC_STAT(ACC_STAT),\r
+\t.DIN(DIN),\r
+\t.DISP(DISP),\r
+\t.IC_TEX(IC_TEX),\r
+\t.IMME_Q(IMME_Q),\r
+\t.INFO_AU(INFO_AU),\r
+\t.LD_OUT(LD_OUT),\r
+\t.DETOIP(DETOIP),\r
+\t.MMU_UPDATE(MMU_UPDATE),\r
+\t.OPER(OPER),\r
+\t.PC_ARCHI(PC_ARCHI),\r
+\t.PC_ICACHE(PC_ICACHE),\r
+\t.RDAA(RDAA),\r
+\t.RDAB(RDAB),\r
+\t.START(START),\r
+\t.WMASKE(WMASKE),\r
+\t.WRADR(WRADR),\r
+\t.READ_OUT(READ),\r
+\t.WRITE_OUT(WRITE),\r
+\t.ZTEST(ZTEST),\r
+\t.RMW(RMW),\r
+\t.QWATWO(QWATWO),\r
+\t.ACC_DONE(ACC_DONE),\r
+\t.REG_OUT(REG_OUT),\r
+\t.Y_INIT(Y_INIT),\r
+\t.DONE(DONE),\r
+\t.PTB_WR(PTB_WR),\r
+\t.PTB_SEL(PTB_SEL),\r
+\t.ACB_ZERO(ACB_ZERO),\r
+\t.ABORT(DC_ABORT),\r
+\t.SAVE_PC(SAVE_PC),\r
+\t.CFG(CFG),\r
+\t.CINV(CINV),\r
+\t.DP_Q(DP_Q),\r
+\t.IVAR(IVAR),\r
+\t.MCR(MCR),\r
+\t.PACKET(PACKET),\r
+\t.PC_NEW(PC_NEW),\r
+\t.PSR(PSR),\r
+\t.SIZE(SIZE),\r
+\t.STRING(STRING),\r
+\t.TRAPS(TRAPS),\r
+\t.VADR(VADR),\r
+\t.RWVFLAG(RWVFLAG),\r
+\t.DBG_HIT(DBG_HIT),\r
+\t.DBG_IN(DBG_IN),\r
+\t.COP_DONE(COP_DONE),\r
+\t.COP_OP(COP_OP),\r
+\t.COP_IN(COP_IN),\r
+\t.COP_GO(COP_GO),\r
+\t.COP_OUT(COP_OUT));\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//            The Instruction Cache\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+ICACHE\tLEGS(\r
+\t.MCLK(MCLK),\r
+\t.BCLK(BCLK),\r
+\t.BRESET(BRESET),\r
+\t.PTB_WR(PTB_WR),\r
+\t.PTB_SEL(PTB_SEL),\r
+\t.MDONE(IC_MDONE),\r
+\t.IO_READY(I_IORDY),\r
+\t.READ_I(IC_READ),\r
+\t.PSR_USER(IC_USER),\r
+\t.DATA_HOLD(DATA_HOLD),\r
+\t.DRAM_WR(DC_WR),\r
+\t.KDET(KDET),\r
+\t.HOLD(HOLD),\r
+//\t.CFG(CFG[12:11]),\r
+\t.CFG(2'b00),\r
+\t.ENDRAM(ENDRAM),\r
+\t.DRAM_Q(DRAM_Q),\r
+\t.CINVAL(CINV[3:2]),\r
+\t.IC_SIGS(IC_SIGS),\r
+\t.IO_Q(IO_Q),\r
+\t.IVAR(IVAR),\r
+\t.KOLLI_A(KOLLI_A),\r
+//\t.MCR_FLAGS(MCR),\r
+\t.MCR_FLAGS(4'b0),\r
+\t.MMU_DIN(MMU_DIN),\r
+\t.VADR(PC_ICACHE),\r
+\t.WADDR(WADDR),\r
+\t.WCTRL(IWCTRL),\r
+\t.DRAM_ACC(IC_ACC),\r
+\t.IO_RD(I_IORD),\r
+\t.INIT_RUN(IC_INIT),\r
+\t.PROT_ERROR(PROT_ERROR),\r
+\t.ACC_OK(IACC_STAT[0]),\r
+\t.IC_PREQ(IC_PREQ),\r
+\t.KOLLISION(KOLLISION),\r
+\t.DRAM_A(IDRAM_ADR),\r
+\t.IC_DQ(IC_DIN),\r
+\t.IC_VA(IC_VA),\r
+\t.ICTODC(ICTODC),\r
+\t.ENA_HK(ENA_HK),\r
+\t.STOP_CINV(STOP_CINV),\r
+\t.IO_A(I_IOA));\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//            The Control Unit\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+STEUERUNG\tBRAIN(\r
+\t.BCLK(BCLK),\r
+\t.BRESET(BRESET),\r
+\t.DC_ACC_DONE(ACC_DONE),\r
+\t.ACB_ZERO(ACB_ZERO),\r
+\t.DONE(DONE),\r
+\t.NMI_N(NMI_N),\r
+\t.INT_N(INT_N),\r
+\t.DC_ABORT(DC_ABORT),\r
+\t.IC_INIT(IC_INIT),\r
+\t.DC_INIT(DC_INIT),\r
+\t.Y_INIT(Y_INIT),\r
+\t.SAVE_PC(SAVE_PC),\r
+\t.CFG(CFG[8:0]),\r
+\t.IACC_STAT(IACC_STAT),\r
+\t.PROT_ERROR(PROT_ERROR),\r
+\t.IC_DIN(IC_DIN),\r
+\t.PC_NEW(PC_NEW),\r
+\t.PSR(PSR),\r
+\t.STRING(STRING),\r
+\t.TRAPS(TRAPS),\r
+\t.IC_READ(IC_READ),\r
+\t.DATA_HOLD(DATA_HOLD),\r
+\t.LD_DIN(LD_DIN),\r
+\t.LD_IMME(LD_IMME),\r
+\t.WREN(WREN_REG),\r
+\t.WR_REG(WR_REG),\r
+\t.GENSTAT(GENSTAT),\r
+\t.IC_USER(IC_USER),\r
+\t.ACC_FELD(ACC_FELD),\r
+\t.DISP(DISP),\r
+\t.IC_TEX(IC_TEX),\r
+\t.IMME_Q(IMME_Q),\r
+\t.INFO_AU(INFO_AU),\r
+\t.LD_OUT(LD_OUT),\r
+\t.DETOIP(DETOIP),\r
+\t.MMU_UPDATE(MMU_UPDATE),\r
+\t.OPER(OPER),\r
+\t.PC_ARCHI(PC_ARCHI),\r
+\t.PC_ICACHE(PC_ICACHE),\r
+\t.RDAA(RDAA),\r
+\t.RDAB(RDAB),\r
+\t.START(START),\r
+\t.WMASKE(WMASKE),\r
+\t.WRADR(WRADR),\r
+\t.ENA_HK(ENA_HK),\r
+\t.STOP_CINV(STOP_CINV),\r
+\t.COP_OP(COP_OP),\r
+\t.ILO(ILO_SIG),\r
+\t.RWVAL(RWVAL));\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//            The Input/Output Interface\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+IO_SWITCH\tISWITCH(\r
+\t.I_IORD(I_IORD),\r
+\t.D_IOWR(D_IOWR),\r
+\t.IO_READY(IO_READY),\r
+\t.D_IORD(D_IORD),\r
+\t.D_IOBE(D_IOBE),\r
+\t.BRESET(BRESET),\r
+\t.BCLK(BCLK),\r
+\t.GENSTAT(GENSTAT),\r
+\t.D_IOA(D_IOA),\r
+\t.I_IOA(I_IOA),\r
+\t.D_IORDY(D_IORDY),\r
+\t.I_IORDY(I_IORDY),\r
+\t.IO_RD(IO_RD),\r
+\t.IO_WR(IO_WR),\r
+\t.IO_BE(IO_BE),\r
+\t.ILO_SIG(ILO_SIG),\r
+\t.ILO(ILO),\r
+\t.IO_A(IO_A),\r
+\t.DCWACC({DC_WR,DC_ACC}),\r
+\t.STATUS(STATUS));\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//            The Statistic Signal Generator\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+MAKE_STAT\tMKSTAT(\r
+\t.BCLK(BCLK),\r
+\t.READ(READ),\r
+\t.DACC_OK(ACC_STAT[0]),\r
+\t.KOLLISION(KOLLISION),\r
+\t.DC_ACC(DC_ACC),\r
+\t.DPTE_ACC(PTE_STAT[0]),\r
+\t.DC_MDONE(DC_MDONE),\r
+\t.DRAM_WR(DC_WR),\r
+\t.IC_READ(IC_READ),\r
+\t.IACC_OK(IACC_STAT[0]),\r
+\t.IC_ACC(IC_ACC),\r
+\t.IPTE_ACC(PTE_STAT[1]),\r
+\t.IC_MDONE(IC_MDONE),\r
+\t.DATA_HOLD(DATA_HOLD),\r
+\t.STATSIGS(STATSIGS));\r
+\r
+endmodule\r
+"
+"(
+    input rst_b,
+    input p1_clk,
+    input p1_select,
+    input p1_rdnw,
+    input p2_clk,
+    input p2_select,
+    input p2_rdnw,
+    output p2_data_available,
+    output p1_full
+);
+
+   // Initial state: 0 = empty; 1 = full
+   
+   // TODO - Implement this!
+   parameter init = 0;
+
+   wire req;
+   reg req_s1;
+   reg req_s2;
+   reg req_edge;
+
+   reg [1:0] p1_state;
+
+   wire ack;
+   reg ack_s1;
+   reg ack_s2;
+   reg ack_edge;
+   reg [1:0] p2_state;
+
+
+   always @ (`p1edge p1_clk or negedge rst_b )
+     begin
+        if (!rst_b) begin
+          ack_s1 <= 1'b0;
+          ack_s2 <= 1'b0;
+          ack_edge <= 1'b0;
+          p1_state <= { 1'b0, init};
+        end else begin
+          ack_s1 <= ack;
+          ack_s2 <= ack_s1;
+          ack_edge <= ack_s2 ^ ack_s1;
+          case (p1_state)
+            2'b00:
+              if (p1_select & !p1_rdnw)
+                p1_state <= 2'b01;
+            2'b01:
+              if (ack_edge)
+                p1_state <= 2'b11;
+            2'b11:
+              if (p1_select & !p1_rdnw)
+                p1_state <= 2'b10;
+            2'b10:
+              if (ack_edge)
+                p1_state <= 2'b00;
+          endcase
+        end
+      end
+
+   assign req = p1_state[0];
+   assign p1_full = p1_state[0] ^ p1_state[1];
+
+   always @ (`p2edge p2_clk or negedge rst_b )
+     begin
+        if (!rst_b) begin
+          req_s1 <= 1'b0;
+          req_s2 <= 1'b0;
+          req_edge <= 1'b0;
+          p2_state <= { init, 1'b0 };
+        end else begin
+          req_s1 <= req;
+          req_s2 <= req_s1;
+          req_edge <= req_s2 ^ req_s1;
+          case (p2_state)
+            2'b00:
+              if (req_edge)
+                p2_state <= 2'b10;
+            2'b10:
+              if (p2_select & p2_rdnw)
+                p2_state <= 2'b11;
+            2'b11:
+              if (req_edge)
+                p2_state <= 2'b01;
+            2'b01:
+              if (p2_select & p2_rdnw)
+                p2_state <= 2'b00;
+          endcase
+        end
+      end
+
+    assign ack = p2_state[0];
+    assign p2_data_available = p2_state[0] ^ p2_state[1];
+
+endmodule
+"
+"//////////////////////////////////////////////////////////////////
+//                                                              //
+//  Decode stage of Amber 2 Core                                //
+//                                                              //
+//  This file is part of the Amber project                      //
+//  http://www.opencores.org/project,amber                      //
+//                                                              //
+//  Description                                                 //
+//  This module is the most complex part of the Amber core      //
+//  It decodes and sequences all instructions and handles all   //
+//  interrupts                                                  //
+//                                                              //
+//  Author(s):                                                  //
+//      - Conor Santifort, csantifort.amber@gmail.com           //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+//                                                              //
+// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
+//                                                              //
+// This source file may be used and distributed without         //
+// restriction provided that this copyright statement is not    //
+// removed from the file and that any derivative work contains  //
+// the original copyright notice and the associated disclaimer. //
+//                                                              //
+// This source file is free software; you can redistribute it   //
+// and/or modify it under the terms of the GNU Lesser General   //
+// Public License as published by the Free Software Foundation; //
+// either version 2.1 of the License, or (at your option) any   //
+// later version.                                               //
+//                                                              //
+// This source is distributed in the hope that it will be       //
+// useful, but WITHOUT ANY WARRANTY; without even the implied   //
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
+// PURPOSE.  See the GNU Lesser General Public License for more //
+// details.                                                     //
+//                                                              //
+// You should have received a copy of the GNU Lesser General    //
+// Public License along with this source; if not, download it   //
+// from http://www.opencores.org/lgpl.shtml                     //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+`include ""global_defines.vh""
+
+module a23_decode
+(
+input                       i_clk,
+input       [31:0]          i_read_data,
+input                       i_fetch_stall,                  // stall all stages of the cpu at the same time
+input                       i_irq,                          // interrupt request
+input                       i_firq,                         // Fast interrupt request
+input                       i_dabt,                         // data abort interrupt request
+input                       i_iabt,                         // instruction pre-fetch abort flag
+input                       i_adex,                         // Address Exception
+input       [31:0]          i_execute_address,              // Registered address output by execute stage
+                                                            // 2 LSBs of read address used for calculating
+                                                            // shift in LDRB ops
+input       [7:0]           i_abt_status,                   // Abort status
+input       [31:0]          i_execute_status_bits,          // current status bits values in execute stage
+input                       i_multiply_done,                // multiply unit is nearly done
+
+
+// --------------------------------------------------
+// Control signals to execute stage
+// --------------------------------------------------
+output reg  [31:0]          o_read_data = 1\'d0,
+output reg  [4:0]           o_read_data_alignment = 1\'d0,  // 2 LSBs of read address used for calculating shift in LDRB ops
+
+output reg  [31:0]          o_imm32 = \'d0,
+output reg  [4:0]           o_imm_shift_amount = \'d0,
+output reg                  o_shift_imm_zero = \'d0,
+output wire [3:0]           o_condition,
+output reg                  o_exclusive_exec = \'d0,         // exclusive access request ( swap instruction )
+output reg                  o_data_access_exec = \'d0,       // high means the memory access is a read
+                                                            // read or write, low for instruction
+output wire [1:0]           o_status_bits_mode,
+output wire                 o_status_bits_irq_mask,
+output wire                 o_status_bits_firq_mask,
+
+output reg  [3:0]           o_rm_sel = \'d0,
+output reg  [3:0]           o_rds_sel = \'d0,
+output reg  [3:0]           o_rn_sel = \'d0,
+output      [3:0]           o_rm_sel_nxt,
+output      [3:0]           o_rds_sel_nxt,
+output      [3:0]           o_rn_sel_nxt,
+output reg  [1:0]           o_barrel_shift_amount_sel = \'d0,
+output reg  [1:0]           o_barrel_shift_data_sel = \'d0,
+output reg  [1:0]           o_barrel_shift_function = \'d0,
+output reg  [8:0]           o_alu_function = \'d0,
+output reg                  o_use_carry_in = \'d0,
+output reg  [1:0]           o_multiply_function = \'d0,
+output reg  [2:0]           o_interrupt_vector_sel = \'d0,
+output wire [3:0]           o_address_sel,
+output wire [1:0]           o_pc_sel,
+output reg  [1:0]           o_byte_enable_sel = \'d0,        // byte, halfword or word write
+output reg  [2:0]           o_status_bits_sel = \'d0,
+output reg  [2:0]           o_reg_write_sel,
+output reg                  o_user_mode_regs_load,
+output reg                  o_user_mode_regs_store_nxt,
+output reg                  o_firq_not_user_mode,
+
+output reg                  o_write_data_wen = \'d0,
+output reg                  o_base_address_wen = \'d0,       // save LDM base address register
+                                                            // in case of data abort
+output wire                 o_pc_wen,
+output reg  [14:0]          o_reg_bank_wen = \'d0,
+output reg  [3:0]           o_reg_bank_wsel = \'d0,
+output reg                  o_status_bits_flags_wen = \'d0,
+output reg                  o_status_bits_mode_wen = \'d0,
+output reg                  o_status_bits_irq_mask_wen = \'d0,
+output reg                  o_status_bits_firq_mask_wen = \'d0,
+
+// --------------------------------------------------
+// Co-Processor interface
+// --------------------------------------------------
+output reg  [2:0]           o_copro_opcode1 = \'d0,
+output reg  [2:0]           o_copro_opcode2 = \'d0,
+output reg  [3:0]           o_copro_crn = \'d0,
+output reg  [3:0]           o_copro_crm = \'d0,
+output reg  [3:0]           o_copro_num = \'d0,
+output reg  [1:0]           o_copro_operation = \'d0, // 0 = no operation,
+                                                     // 1 = Move to Amber Core Register from Coprocessor
+                                                     // 2 = Move to Coprocessor from Amber Core Register
+output reg                  o_copro_write_data_wen = \'d0,
+output                      o_iabt_trigger,
+output      [31:0]          o_iabt_address,
+output      [7:0]           o_iabt_status,
+output                      o_dabt_trigger,
+output      [31:0]          o_dabt_address,
+output      [7:0]           o_dabt_status
+
+
+);
+
+`include ""a23_localparams.vh""
+`include ""a23_functions.vh""
+
+localparam [4:0] RST_WAIT1      = 5\'d0,
+                 RST_WAIT2      = 5\'d1,
+                 INT_WAIT1      = 5\'d2,
+                 INT_WAIT2      = 5\'d3,
+                 EXECUTE        = 5\'d4,
+                 PRE_FETCH_EXEC = 5\'d5,  // Execute the Pre-Fetched Instruction
+                 MEM_WAIT1      = 5\'d6,  // conditionally decode current instruction, in case
+                                         // previous instruction does not execute in S2
+                 MEM_WAIT2      = 5\'d7,
+                 PC_STALL1      = 5\'d8,  // Program Counter altered
+                                         // conditionally decude current instruction, in case
+                                         // previous instruction does not execute in S2
+                 PC_STALL2      = 5\'d9,
+                 MTRANS_EXEC1   = 5\'d10,
+                 MTRANS_EXEC2   = 5\'d11,
+                 MTRANS_EXEC3   = 5\'d12,
+                 MTRANS_EXEC3B  = 5\'d13,
+                 MTRANS_EXEC4   = 5\'d14,
+                 MTRANS5_ABORT  = 5\'d15,
+                 MULT_PROC1     = 5\'d16,  // first cycle, save pre fetch instruction
+                 MULT_PROC2     = 5\'d17,  // do multiplication
+                 MULT_STORE     = 5\'d19,  // save RdLo
+                 MULT_ACCUMU    = 5\'d20,  // Accumulate add lower 32 bits
+                 SWAP_WRITE     = 5\'d22,
+                 SWAP_WAIT1     = 5\'d23,
+                 SWAP_WAIT2     = 5\'d24,
+                 COPRO_WAIT     = 5\'d25;
+
+
+// ========================================================
+// Internal signals
+// ========================================================
+wire    [31:0]         instruction;
+wire                   instruction_iabt;        // abort flag, follows the instruction
+wire                   instruction_adex;        // address exception flag, follows the instruction
+wire    [31:0]         instruction_address;     // instruction virtual address, follows
+                                                // the instruction
+wire    [7:0]          instruction_iabt_status; // abort status, follows the instruction
+wire    [1:0]          instruction_sel;
+reg     [3:0]          itype;
+wire    [3:0]          opcode;
+wire    [7:0]          imm8;
+wire    [31:0]         offset12;
+wire    [31:0]         offset24;
+wire    [4:0]          shift_imm;
+
+wire                   opcode_compare;
+wire                   mem_op;
+wire                   load_op;
+wire                   store_op;
+wire                   write_pc;
+wire                   immediate_shifter_operand;
+wire                   rds_use_rs;
+wire                   branch;
+wire                   mem_op_pre_indexed;
+wire                   mem_op_post_indexed;
+
+// Flop inputs
+wire    [31:0]         imm32_nxt;
+wire    [4:0]          imm_shift_amount_nxt;
+wire                   shift_imm_zero_nxt;
+wire    [3:0]          condition_nxt;
+reg                    exclusive_exec_nxt;
+reg                    data_access_exec_nxt;
+wire                   shift_extend;
+
+reg     [1:0]          barrel_shift_function_nxt;
+wire    [8:0]          alu_function_nxt;
+reg                    use_carry_in_nxt;
+reg     [1:0]          multiply_function_nxt;
+reg     [1:0]          status_bits_mode_nxt;
+reg                    status_bits_irq_mask_nxt;
+reg                    status_bits_firq_mask_nxt;
+
+reg     [1:0]          barrel_shift_amount_sel_nxt;
+reg     [1:0]          barrel_shift_data_sel_nxt;
+reg     [3:0]          address_sel_nxt;
+reg     [1:0]          pc_sel_nxt;
+reg     [1:0]          byte_enable_sel_nxt;
+reg     [2:0]          status_bits_sel_nxt;
+reg     [2:0]          reg_write_sel_nxt;
+reg                    user_mode_regs_load_nxt;
+wire                   firq_not_user_mode_nxt;
+
+// ALU Function signals
+reg                    alu_swap_sel_nxt;
+reg                    alu_not_sel_nxt;
+reg     [1:0]          alu_cin_sel_nxt;
+reg                    alu_cout_sel_nxt;
+reg     [3:0]          alu_out_sel_nxt;
+
+reg                    write_data_wen_nxt;
+reg                    copro_write_data_wen_nxt;
+reg                    base_address_wen_nxt;
+reg                    pc_wen_nxt;
+reg     [3:0]          reg_bank_wsel_nxt;
+reg                    status_bits_flags_wen_nxt;
+reg                    status_bits_mode_wen_nxt;
+reg                    status_bits_irq_mask_wen_nxt;
+reg                    status_bits_firq_mask_wen_nxt;
+
+reg                    saved_current_instruction_wen;   // saved load instruction
+reg                    pre_fetch_instruction_wen;       // pre-fetch instruction
+
+reg     [4:0]          control_state = RST_WAIT1;
+reg     [4:0]          control_state_nxt;
+
+
+wire                   dabt;
+reg                    dabt_reg = \'d0;
+reg                    dabt_reg_d1;
+reg                    iabt_reg = \'d0;
+reg                    adex_reg = \'d0;
+reg     [31:0]         abt_address_reg = \'d0;
+reg     [7:0]          abt_status_reg = \'d0;
+reg     [31:0]         saved_current_instruction = \'d0;
+reg                    saved_current_instruction_iabt = \'d0;          // access abort flag
+reg                    saved_current_instruction_adex = \'d0;          // address exception
+reg     [31:0]         saved_current_instruction_address = \'d0;       // virtual address of abort instruction
+reg     [7:0]          saved_current_instruction_iabt_status = \'d0;   // status of abort instruction
+reg     [31:0]         pre_fetch_instruction = \'d0;
+reg                    pre_fetch_instruction_iabt = \'d0;              // access abort flag
+reg                    pre_fetch_instruction_adex = \'d0;              // address exception
+reg     [31:0]         pre_fetch_instruction_address = \'d0;           // virtual address of abort instruction
+reg     [7:0]          pre_fetch_instruction_iabt_status = \'d0;       // status of abort instruction
+
+wire                   instruction_valid;
+wire                   instruction_execute;
+
+reg     [3:0]          mtrans_reg;              // the current register being accessed as part of STM/LDM
+reg     [3:0]          mtrans_reg_d1 = \'d0;     // delayed by 1 period
+reg     [3:0]          mtrans_reg_d2 = \'d0;     // delayed by 2 periods
+reg     [31:0]         mtrans_instruction_nxt;
+
+wire   [31:0]          mtrans_base_reg_change;
+wire   [4:0]           mtrans_num_registers;
+wire                   use_saved_current_instruction;
+wire                   use_pre_fetch_instruction;
+wire                   interrupt;
+wire   [1:0]           interrupt_mode;
+wire   [2:0]           next_interrupt;
+reg                    irq = \'d0;
+reg                    firq = \'d0;
+wire                   firq_request;
+wire                   irq_request;
+wire                   swi_request;
+wire                   und_request;
+wire                   dabt_request;
+reg    [1:0]           copro_operation_nxt;
+reg                    mtrans_r15 = \'d0;
+reg                    mtrans_r15_nxt;
+reg                    restore_base_address = \'d0;
+reg                    restore_base_address_nxt;
+
+wire                   regop_set_flags;
+
+
+// ========================================================
+// registers for output ports with non-zero initial values
+// ========================================================
+reg  [3:0]           condition_r = 4\'he;             // 4\'he = al
+reg  [1:0]           status_bits_mode_r = 2\'b11;     // SVC
+reg                  status_bits_irq_mask_r = 1\'d1;
+reg                  status_bits_firq_mask_r = 1\'d1;
+reg  [3:0]           address_sel_r = 4\'d2;
+reg  [1:0]           pc_sel_r = 2\'d2;
+reg                  pc_wen_r = 1\'d1;
+
+assign o_condition              = condition_r;
+assign o_status_bits_mode       = status_bits_mode_r;
+assign o_status_bits_irq_mask   = status_bits_irq_mask_r;
+assign o_status_bits_firq_mask  = status_bits_firq_mask_r;
+assign o_address_sel            = address_sel_r;
+assign o_pc_sel                 = pc_sel_r;
+assign o_pc_wen                 = pc_wen_r;
+
+
+
+// ========================================================
+// Instruction Abort and Data Abort outputs
+// ========================================================
+
+assign o_iabt_trigger     = instruction_iabt && status_bits_mode_r == SVC && control_state == INT_WAIT1;
+assign o_iabt_address     = instruction_address;
+assign o_iabt_status      = instruction_iabt_status;
+
+assign o_dabt_trigger     = dabt_reg && !dabt_reg_d1;
+assign o_dabt_address     = abt_address_reg;
+assign o_dabt_status      = abt_status_reg;
+
+
+// ========================================================
+// Instruction Decode
+// ========================================================
+
+// for instructions that take more than one cycle
+// the instruction is saved in the \'saved_mem_instruction\'
+// register and then that register is used for the rest of
+// the execution of the instruction.
+// But if the instruction does not execute because of the
+// condition, then need to select the next instruction to
+// decode
+assign use_saved_current_instruction =  instruction_execute &&
+                          ( control_state == MEM_WAIT1     ||
+                            control_state == MEM_WAIT2     ||
+                            control_state == MTRANS_EXEC1  ||
+                            control_state == MTRANS_EXEC2  ||
+                            control_state == MTRANS_EXEC3  ||
+                            control_state == MTRANS_EXEC3B ||
+                            control_state == MTRANS_EXEC4  ||
+                            control_state == MTRANS5_ABORT ||
+                            control_state == MULT_PROC1    ||
+                            control_state == MULT_PROC2    ||
+                            control_state == MULT_ACCUMU   ||
+                            control_state == MULT_STORE    ||
+                            control_state == INT_WAIT1     ||
+                            control_state == INT_WAIT2     ||
+                            control_state == SWAP_WRITE    ||
+                            control_state == SWAP_WAIT1    ||
+                            control_state == SWAP_WAIT2    ||
+                            control_state == COPRO_WAIT     );
+
+assign use_pre_fetch_instruction = control_state == PRE_FETCH_EXEC;
+
+
+assign instruction_sel  =         use_saved_current_instruction  ? 2\'d1 :  // saved_current_instruction
+                                  use_pre_fetch_instruction      ? 2\'d2 :  // pre_fetch_instruction
+                                                                   2\'d0 ;  // o_read_data
+
+assign instruction      =         instruction_sel == 2\'d0 ? o_read_data               :
+                                  instruction_sel == 2\'d1 ? saved_current_instruction :
+                                                            pre_fetch_instruction     ;
+
+// abort flag
+assign instruction_iabt =         instruction_sel == 2\'d0 ? iabt_reg                       :
+                                  instruction_sel == 2\'d1 ? saved_current_instruction_iabt :
+                                                            pre_fetch_instruction_iabt     ;
+
+assign instruction_address =      instruction_sel == 2\'d0 ? abt_address_reg                   :
+                                  instruction_sel == 2\'d1 ? saved_current_instruction_address :
+                                                            pre_fetch_instruction_address     ;
+
+assign instruction_iabt_status =  instruction_sel == 2\'d0 ? abt_status_reg                        :
+                                  instruction_sel == 2\'d1 ? saved_current_instruction_iabt_status :
+                                                            pre_fetch_instruction_iabt_status     ;
+
+// instruction address exception
+assign instruction_adex =         instruction_sel == 2\'d0 ? adex_reg                       :
+                                  instruction_sel == 2\'d1 ? saved_current_instruction_adex :
+                                                            pre_fetch_instruction_adex     ;
+
+// Instruction Decode - Order is important!
+always @*
+    casez ({instruction[27:20], instruction[7:4]})
+        12\'b00010?001001 : itype = SWAP;
+        12\'b000000??1001 : itype = MULT;
+        12\'b00?????????? : itype = REGOP;
+        12\'b01?????????? : itype = TRANS;
+        12\'b100????????? : itype = MTRANS;
+        12\'b101????????? : itype = BRANCH;
+        12\'b110????????? : itype = CODTRANS;
+        12\'b1110???????0 : itype = COREGOP;
+        12\'b1110???????1 : itype = CORTRANS;
+        default:           itype = SWI;
+    endcase
+
+
+// ========================================================
+// Fixed fields within the instruction
+// ========================================================
+
+assign opcode        = instruction[24:21];
+assign condition_nxt = instruction[31:28];
+
+assign o_rm_sel_nxt    = instruction[3:0];
+
+assign o_rn_sel_nxt    = branch  ? 4\'d15              : // Use PC to calculate branch destination
+                                   instruction[19:16] ;
+
+assign o_rds_sel_nxt   = control_state == SWAP_WRITE  ? instruction[3:0]   : // Rm gets written out to memory
+                         itype == MTRANS              ? mtrans_reg         :
+                         branch                       ? 4\'d15              : // Update the PC
+                         rds_use_rs                   ? instruction[11:8]  :
+                                                        instruction[15:12] ;
+
+
+assign shift_imm     = instruction[11:7];
+
+// this is used for RRX
+assign shift_extend  = !instruction[25] && !instruction[4] && !(|instruction[11:7]) && instruction[6:5] == 2\'b11;
+
+assign offset12      = { 20\'h0, instruction[11:0]};
+assign offset24      = {{6{instruction[23]}}, instruction[23:0], 2\'d0 }; // sign extend
+assign imm8          = instruction[7:0];
+
+assign immediate_shifter_operand = instruction[25];
+assign rds_use_rs                = (itype == REGOP && !instruction[25] && instruction[4]) ||
+                                   (itype == MULT &&
+                                    (control_state == MULT_PROC1  ||
+                                     control_state == MULT_PROC2  ||
+                                     instruction_valid && !interrupt )) ;
+assign branch                    = itype == BRANCH;
+assign opcode_compare =
+            opcode == CMP ||
+            opcode == CMN ||
+            opcode == TEQ ||
+            opcode == TST ;
+
+
+assign mem_op               = itype == TRANS;
+assign load_op              = mem_op && instruction[20];
+assign store_op             = mem_op && !instruction[20];
+assign write_pc             = pc_wen_nxt && pc_sel_nxt != 2\'d0;
+assign regop_set_flags      = itype == REGOP && instruction[20];
+
+assign mem_op_pre_indexed   =  instruction[24] && instruction[21];
+assign mem_op_post_indexed  = !instruction[24];
+
+assign imm32_nxt            =  // add 0 to Rm
+                               itype == MULT               ? {  32\'d0                      } :
+
+                               // 4 x number of registers
+                               itype == MTRANS             ? {  mtrans_base_reg_change     } :
+                               itype == BRANCH             ? {  offset24                   } :
+                               itype == TRANS              ? {  offset12                   } :
+                               instruction[11:8] == 4\'h0  ? {            24\'h0, imm8[7:0] } :
+                               instruction[11:8] == 4\'h1  ? { imm8[1:0], 24\'h0, imm8[7:2] } :
+                               instruction[11:8] == 4\'h2  ? { imm8[3:0], 24\'h0, imm8[7:4] } :
+                               instruction[11:8] == 4\'h3  ? { imm8[5:0], 24\'h0, imm8[7:6] } :
+                               instruction[11:8] == 4\'h4  ? { imm8[7:0], 24\'h0            } :
+                               instruction[11:8] == 4\'h5  ? { 2\'h0,  imm8[7:0], 22\'h0     } :
+                               instruction[11:8] == 4\'h6  ? { 4\'h0,  imm8[7:0], 20\'h0     } :
+                               instruction[11:8] == 4\'h7  ? { 6\'h0,  imm8[7:0], 18\'h0     } :
+                               instruction[11:8] == 4\'h8  ? { 8\'h0,  imm8[7:0], 16\'h0     } :
+                               instruction[11:8] == 4\'h9  ? { 10\'h0, imm8[7:0], 14\'h0     } :
+                               instruction[11:8] == 4\'ha  ? { 12\'h0, imm8[7:0], 12\'h0     } :
+                               instruction[11:8] == 4\'hb  ? { 14\'h0, imm8[7:0], 10\'h0     } :
+                               instruction[11:8] == 4\'hc  ? { 16\'h0, imm8[7:0], 8\'h0      } :
+                               instruction[11:8] == 4\'hd  ? { 18\'h0, imm8[7:0], 6\'h0      } :
+                               instruction[11:8] == 4\'he  ? { 20\'h0, imm8[7:0], 4\'h0      } :
+                                                            { 22\'h0, imm8[7:0], 2\'h0      } ;
+
+
+assign imm_shift_amount_nxt = shift_imm ;
+
+       // This signal is encoded in the decode stage because
+       // it is on the critical path in the execute stage
+assign shift_imm_zero_nxt   = imm_shift_amount_nxt == 5\'d0 &&       // immediate amount = 0
+                              barrel_shift_amount_sel_nxt == 2\'d2;  // shift immediate amount
+
+assign alu_function_nxt     = { alu_swap_sel_nxt,
+                                alu_not_sel_nxt,
+                                alu_cin_sel_nxt,
+                                alu_cout_sel_nxt,
+                                alu_out_sel_nxt  };
+
+
+// ========================================================
+// MTRANS Operations
+// ========================================================
+
+   // Bit 15 = r15
+   // Bit 0  = R0
+   // In LDM and STM instructions R0 is loaded or stored first
+always @*
+    casez (instruction[15:0])
+    16\'b???????????????1 : mtrans_reg = 4\'h0 ;
+    16\'b??????????????10 : mtrans_reg = 4\'h1 ;
+    16\'b?????????????100 : mtrans_reg = 4\'h2 ;
+    16\'b????????????1000 : mtrans_reg = 4\'h3 ;
+    16\'b???????????10000 : mtrans_reg = 4\'h4 ;
+    16\'b??????????100000 : mtrans_reg = 4\'h5 ;
+    16\'b?????????1000000 : mtrans_reg = 4\'h6 ;
+    16\'b????????10000000 : mtrans_reg = 4\'h7 ;
+    16\'b???????100000000 : mtrans_reg = 4\'h8 ;
+    16\'b??????1000000000 : mtrans_reg = 4\'h9 ;
+    16\'b?????10000000000 : mtrans_reg = 4\'ha ;
+    16\'b????100000000000 : mtrans_reg = 4\'hb ;
+    16\'b???1000000000000 : mtrans_reg = 4\'hc ;
+    16\'b??10000000000000 : mtrans_reg = 4\'hd ;
+    16\'b?100000000000000 : mtrans_reg = 4\'he ;
+    default              : mtrans_reg = 4\'hf ;
+    endcase
+
+
+always @*
+    casez (instruction[15:0])
+    16\'b???????????????1 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 1],  1\'d0};
+    16\'b??????????????10 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 2],  2\'d0};
+    16\'b?????????????100 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 3],  3\'d0};
+    16\'b????????????1000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 4],  4\'d0};
+    16\'b???????????10000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 5],  5\'d0};
+    16\'b??????????100000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 6],  6\'d0};
+    16\'b?????????1000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 7],  7\'d0};
+    16\'b????????10000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 8],  8\'d0};
+    16\'b???????100000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 9],  9\'d0};
+    16\'b??????1000000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15:10], 10\'d0};
+    16\'b?????10000000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15:11], 11\'d0};
+    16\'b????100000000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15:12], 12\'d0};
+    16\'b???1000000000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15:13], 13\'d0};
+    16\'b??10000000000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15:14], 14\'d0};
+    16\'b?100000000000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15   ], 15\'d0};
+    default              : mtrans_instruction_nxt = {instruction[31:16],                     16\'d0};
+    endcase
+
+
+// number of registers to be stored
+assign mtrans_num_registers =   {4\'d0, instruction[15]} +
+                                {4\'d0, instruction[14]} +
+                                {4\'d0, instruction[13]} +
+                                {4\'d0, instruction[12]} +
+                                {4\'d0, instruction[11]} +
+                                {4\'d0, instruction[10]} +
+                                {4\'d0, instruction[ 9]} +
+                                {4\'d0, instruction[ 8]} +
+                                {4\'d0, instruction[ 7]} +
+                                {4\'d0, instruction[ 6]} +
+                                {4\'d0, instruction[ 5]} +
+                                {4\'d0, instruction[ 4]} +
+                                {4\'d0, instruction[ 3]} +
+                                {4\'d0, instruction[ 2]} +
+                                {4\'d0, instruction[ 1]} +
+                                {4\'d0, instruction[ 0]} ;
+
+// 4 x number of registers to be stored
+assign mtrans_base_reg_change = {25\'d0, mtrans_num_registers, 2\'d0};
+
+// ========================================================
+// Interrupts
+// ========================================================
+
+assign firq_request = firq && !i_execute_status_bits[26];
+assign irq_request  = irq  && !i_execute_status_bits[27];
+assign swi_request  = itype == SWI;
+assign dabt_request = dabt_reg;
+
+// copro15 and copro13 only supports reg trans opcodes
+// all other opcodes involving co-processors cause an
+// undefined instrution interrupt
+assign und_request  =   itype == CODTRANS ||
+                        itype == COREGOP  ||
+                      ( itype == CORTRANS && instruction[11:8] != 4\'d15 );
+
+
+  // in order of priority !!
+  // Highest
+  // 1 Reset
+  // 2 Data Abort (including data TLB miss)
+  // 3 FIRQ
+  // 4 IRQ
+  // 5 Prefetch Abort (including prefetch TLB miss)
+  // 6 Undefined instruction, SWI
+  // Lowest
+assign next_interrupt = dabt_request     ? 3\'d1 :  // Data Abort
+                        firq_request     ? 3\'d2 :  // FIRQ
+                        irq_request      ? 3\'d3 :  // IRQ
+                        instruction_adex ? 3\'d4 :  // Address Exception
+                        instruction_iabt ? 3\'d5 :  // PreFetch Abort, only triggered
+                                                   // if the instruction is used
+                        und_request      ? 3\'d6 :  // Undefined Instruction
+                        swi_request      ? 3\'d7 :  // SWI
+                                           3\'d0 ;  // none
+
+        // SWI and undefined instructions do not cause an interrupt in the decode
+        // stage. They only trigger interrupts if they arfe executed, so the
+        // interrupt is triggered if the execute condition is met in the execute stage
+assign interrupt      = next_interrupt != 3\'d0 &&
+                        next_interrupt != 3\'d7 &&  // SWI
+                        next_interrupt != 3\'d6 ;   // undefined interrupt
+
+
+assign interrupt_mode = next_interrupt == 3\'d2 ? FIRQ :
+                        next_interrupt == 3\'d3 ? IRQ  :
+                        next_interrupt == 3\'d4 ? SVC  :
+                        next_interrupt == 3\'d5 ? SVC  :
+                        next_interrupt == 3\'d6 ? SVC  :
+                        next_interrupt == 3\'d7 ? SVC  :
+                        next_interrupt == 3\'d1 ? SVC  :
+                                                 USR  ;
+
+
+
+
+// ========================================================
+// Generate control signals
+// ========================================================
+always @*
+    begin
+    // default mode
+    status_bits_mode_nxt            = i_execute_status_bits[1:0];   // change to mode in execute stage get reflected
+                                                                    // back to this stage automatically
+    status_bits_irq_mask_nxt        = status_bits_irq_mask_r;
+    status_bits_firq_mask_nxt       = status_bits_firq_mask_r;
+    exclusive_exec_nxt              = 1\'d0;
+    data_access_exec_nxt            = 1\'d0;
+    copro_operation_nxt             = \'d0;
+
+    // Save an instruction to use later
+    saved_current_instruction_wen   = 1\'d0;
+    pre_fetch_instruction_wen       = 1\'d0;
+    mtrans_r15_nxt                  = mtrans_r15;
+    restore_base_address_nxt        = restore_base_address;
+
+    // default Mux Select values
+    barrel_shift_amount_sel_nxt     = \'d0;  // don\'t shift the input
+    barrel_shift_data_sel_nxt       = \'d0;  // immediate value
+    barrel_shift_function_nxt       = \'d0;
+    use_carry_in_nxt                = \'d0;
+    multiply_function_nxt           = \'d0;
+    address_sel_nxt                 = \'d0;
+    pc_sel_nxt                      = \'d0;
+    byte_enable_sel_nxt             = \'d0;
+    status_bits_sel_nxt             = \'d0;
+    reg_write_sel_nxt               = \'d0;
+    user_mode_regs_load_nxt         = \'d0;
+    o_user_mode_regs_store_nxt      = \'d0;
+
+    // ALU Muxes
+    alu_swap_sel_nxt                = \'d0;
+    alu_not_sel_nxt                 = \'d0;
+    alu_cin_sel_nxt                 = \'d0;
+    alu_cout_sel_nxt                = \'d0;
+    alu_out_sel_nxt                 = \'d0;
+
+    // default Flop Write Enable values
+    write_data_wen_nxt              = \'d0;
+    copro_write_data_wen_nxt        = \'d0;
+    base_address_wen_nxt            = \'d0;
+    pc_wen_nxt                      = \'d1;
+    reg_bank_wsel_nxt               = \'hF;  // Don\'t select any
+    status_bits_flags_wen_nxt       = \'d0;
+    status_bits_mode_wen_nxt        = \'d0;
+    status_bits_irq_mask_wen_nxt    = \'d0;
+    status_bits_firq_mask_wen_nxt   = \'d0;
+
+    if ( instruction_valid && !interrupt )
+        begin
+        if ( itype == REGOP )
+            begin
+            if ( !opcode_compare )
+                begin
+                // Check is the load destination is the PC
+                if (instruction[15:12]  == 4\'d15)
+                    begin
+                    pc_sel_nxt      = 2\'d1; // alu_out
+                    address_sel_nxt = 4\'d1; // alu_out
+                    end
+                else
+                    reg_bank_wsel_nxt = instruction[15:12];
+                end
+
+            if ( !immediate_shifter_operand )
+                barrel_shift_function_nxt  = instruction[6:5];
+
+            if ( !immediate_shifter_operand )
+                barrel_shift_data_sel_nxt = 2\'d2; // Shift value from Rm register
+
+            if ( !immediate_shifter_operand && instruction[4] )
+                barrel_shift_amount_sel_nxt = 2\'d1; // Shift amount from Rs registter
+
+            if ( !immediate_shifter_operand && !instruction[4] )
+                barrel_shift_amount_sel_nxt = 2\'d2; // Shift immediate amount
+
+            // regops that do not change the overflow flag
+            if ( opcode == AND || opcode == EOR || opcode == TST || opcode == TEQ ||
+                 opcode == ORR || opcode == MOV || opcode == BIC || opcode == MVN )
+                status_bits_sel_nxt = 3\'d5;
+
+            if ( opcode == ADD || opcode == CMN )   // CMN is just like an ADD
+                begin
+                alu_out_sel_nxt  = 4\'d1; // Add
+                use_carry_in_nxt = shift_extend;
+                end
+
+            if ( opcode == ADC ) // Add with Carry
+                begin
+                alu_out_sel_nxt  = 4\'d1; // Add
+                alu_cin_sel_nxt  = 2\'d2; // carry in from status_bits
+                use_carry_in_nxt = shift_extend;
+                end
+
+            if ( opcode == SUB || opcode == CMP ) // Subtract
+                begin
+                alu_out_sel_nxt  = 4\'d1; // Add
+                alu_cin_sel_nxt  = 2\'d1; // cin = 1
+                alu_not_sel_nxt  = 1\'d1; // invert B
+                end
+
+            // SBC (Subtract with Carry) subtracts the value of its
+            // second operand and the value of NOT(Carry flag) from
+            // the value of its first operand.
+            //  Rd = Rn - shifter_operand - NOT(C Flag)
+            if ( opcode == SBC ) // Subtract with Carry
+                begin
+                alu_out_sel_nxt  = 4\'d1; // Add
+                alu_cin_sel_nxt  = 2\'d2; // carry in from status_bits
+                alu_not_sel_nxt  = 1\'d1; // invert B
+                use_carry_in_nxt = 1\'d1;
+                end
+
+            if ( opcode == RSB ) // Reverse Subtract
+                begin
+                alu_out_sel_nxt  = 4\'d1; // Add
+                alu_cin_sel_nxt  = 2\'d1; // cin = 1
+                alu_not_sel_nxt  = 1\'d1; // invert B
+                alu_swap_sel_nxt = 1\'d1; // swap A and B
+                end
+
+            if ( opcode == RSC ) // Reverse Subtract with carry
+                begin
+                alu_out_sel_nxt  = 4\'d1; // Add
+                alu_cin_sel_nxt  = 2\'d2; // carry in from status_bits
+                alu_not_sel_nxt  = 1\'d1; // invert B
+                alu_swap_sel_nxt = 1\'d1; // swap A and B
+                use_carry_in_nxt = 1\'d1;
+                end
+
+            if ( opcode == AND || opcode == TST ) // Logical AND, Test  (using AND operator)
+                begin
+                alu_out_sel_nxt  = 4\'d8;  // AND
+                alu_cout_sel_nxt = 1\'d1;  // i_barrel_shift_carry
+                end
+
+            if ( opcode == EOR || opcode == TEQ ) // Logical Exclusive OR, Test Equivalence (using EOR operator)
+                begin
+                alu_out_sel_nxt  = 4\'d6; // XOR
+                alu_cout_sel_nxt = 1\'d1; // i_barrel_shift_carry
+                use_carry_in_nxt = 1\'d1;
+                end
+
+            if ( opcode == ORR )
+                begin
+                alu_out_sel_nxt  = 4\'d7; // OR
+                alu_cout_sel_nxt = 1\'d1; // i_barrel_shift_carry
+                use_carry_in_nxt = 1\'d1;
+                end
+
+            if ( opcode == BIC ) // Bit Clear (using AND & NOT operators)
+                begin
+                alu_out_sel_nxt  = 4\'d8;  // AND
+                alu_not_sel_nxt  = 1\'d1;  // invert B
+                alu_cout_sel_nxt = 1\'d1;  // i_barrel_shift_carry
+                use_carry_in_nxt = 1\'d1;
+                end
+
+            if ( opcode == MOV ) // Move
+                begin
+                alu_cout_sel_nxt = 1\'d1;  // i_barrel_shift_carry
+                use_carry_in_nxt = 1\'d1;
+                end
+
+            if ( opcode == MVN ) // Move NOT
+                begin
+                alu_not_sel_nxt  = 1\'d1; // invert B
+                alu_cout_sel_nxt = 1\'d1; // i_barrel_shift_carry
+                use_carry_in_nxt = 1\'d1;
+                end
+            end
+
+        // Load & Store instructions
+        if ( mem_op )
+            begin
+            saved_current_instruction_wen   = 1\'d1; // Save the memory access instruction to refer back to later
+            pc_wen_nxt                      = 1\'d0; // hold current PC value
+            data_access_exec_nxt            = 1\'d1; // indicate that its a data read or write,
+                                                    // rather than an instruction fetch
+            alu_out_sel_nxt                 = 4\'d1; // Add
+
+            if ( !instruction[23] )  // U: Subtract offset
+                begin
+                alu_cin_sel_nxt  = 2\'d1; // cin = 1
+                alu_not_sel_nxt  = 1\'d1; // invert B
+                end
+
+            if ( store_op )
+                begin
+                write_data_wen_nxt = 1\'d1;
+                if ( itype == TRANS && instruction[22] )
+                    byte_enable_sel_nxt = 2\'d1;         // Save byte
+                end
+
+                // need to update the register holding the address ?
+                // This is Rn bits [19:16]
+            if ( mem_op_pre_indexed || mem_op_post_indexed )
+                begin
+                // Check is the load destination is the PC
+                if ( o_rn_sel_nxt  == 4\'d15 )
+                    pc_sel_nxt = 2\'d1;
+                else
+                    reg_bank_wsel_nxt = o_rn_sel_nxt;
+                end
+
+                // if post-indexed, then use Rn rather than ALU output, as address
+            if ( mem_op_post_indexed )
+               address_sel_nxt = 4\'d4; // Rn
+            else
+               address_sel_nxt = 4\'d1; // alu out
+
+            if ( instruction[25] && itype ==  TRANS )
+                barrel_shift_data_sel_nxt = 2\'d2; // Shift value from Rm register
+
+            if ( itype == TRANS && instruction[25] && shift_imm != 5\'d0 )
+                begin
+                barrel_shift_function_nxt   = instruction[6:5];
+                barrel_shift_amount_sel_nxt = 2\'d2; // imm_shift_amount
+                end
+            end
+
+        if ( itype == BRANCH )
+            begin
+            pc_sel_nxt      = 2\'d1; // alu_out
+            address_sel_nxt = 4\'d1; // alu_out
+            alu_out_sel_nxt = 4\'d1; // Add
+
+            if ( instruction[24] ) // Link
+                begin
+                reg_bank_wsel_nxt  = 4\'d14;  // Save PC to LR
+                reg_write_sel_nxt = 3\'d1;            // pc - 32\'d4
+                end
+            end
+
+        if ( itype == MTRANS )
+            begin
+            saved_current_instruction_wen   = 1\'d1; // Save the memory access instruction to refer back to later
+            pc_wen_nxt                      = 1\'d0; // hold current PC value
+            data_access_exec_nxt            = 1\'d1; // indicate that its a data read or write,
+                                                    // rather than an instruction fetch
+            alu_out_sel_nxt                 = 4\'d1; // Add
+            mtrans_r15_nxt                  = instruction[15];  // load or save r15 ?
+            base_address_wen_nxt            = 1\'d1; // Save the value of the register used for the base address,
+                                                    // in case of a data abort, and need to restore the value
+
+            // The spec says -
+            // If the instruction would have overwritten the base with data
+            // (that is, it has the base in the transfer list), the overwriting is prevented.
+            // This is true even when the abort occurs after the base word gets loaded
+            restore_base_address_nxt        = instruction[20] &&
+                                                (instruction[15:0] & (1\'d1 << instruction[19:16]));
+
+            // Increment or Decrement
+            if ( instruction[23] ) // increment
+                begin
+                if ( instruction[24] )    // increment before
+                    address_sel_nxt = 4\'d7; // Rn + 4
+                else
+                    address_sel_nxt = 4\'d4; // Rn
+                end
+            else // decrement
+                begin
+                alu_cin_sel_nxt  = 2\'d1; // cin = 1
+                alu_not_sel_nxt  = 1\'d1; // invert B
+                if ( !instruction[24] )    // decrement after
+                    address_sel_nxt  = 4\'d6; // alu out + 4
+                else
+                    address_sel_nxt  = 4\'d1; // alu out
+                end
+
+            // Load or store ?
+            if ( !instruction[20] )  // Store
+                write_data_wen_nxt = 1\'d1;
+
+            // LDM: load into user mode registers, when in priviledged mode
+            // Don\'t use mtrans_r15 here because its not loaded yet
+            //if ( {instruction[22],instruction[20],instruction[15]} == 3\'b110 )
+            if ( {instruction[22:20],instruction[15]} == 4\'b1010 )
+                user_mode_regs_load_nxt = 1\'d1;
+
+            // SDM: store the user mode registers, when in priviledged mode
+            //if ( {instruction[22],instruction[20]} == 3\'b10 )
+            if ( {instruction[22:20]} == 3\'b100 )
+                o_user_mode_regs_store_nxt = 1\'d1;
+
+            // update the base register ?
+            if ( instruction[21] )  // the W bit
+                reg_bank_wsel_nxt  = o_rn_sel_nxt;
+            end
+
+
+        if ( itype == MULT )
+            begin
+            multiply_function_nxt[0]        = 1\'d1; // set enable
+                                                    // some bits can be changed just below
+            saved_current_instruction_wen   = 1\'d1; // Save the Multiply instruction to
+                                                    // refer back to later
+            pc_wen_nxt                      = 1\'d0; // hold current PC value
+
+            if ( instruction[21] )
+                multiply_function_nxt[1]    = 1\'d1; // accumulate
+            end
+
+
+        // swp - do read part first
+        if ( itype == SWAP )
+            begin
+            saved_current_instruction_wen   = 1\'d1; // Save the memory access instruction to refer back to later
+            pc_wen_nxt                      = 1\'d0; // hold current PC value
+            data_access_exec_nxt            = 1\'d1; // indicate that its a data read or write,
+                                                    // rather than an instruction fetch
+            barrel_shift_data_sel_nxt       = 2\'d2; // Shift value from Rm register
+            address_sel_nxt                 = 4\'d4; // Rn
+            exclusive_exec_nxt              = 1\'d1; // signal an exclusive access
+            end
+
+
+        // mcr & mrc - takes two cycles
+        if ( itype == CORTRANS && !und_request )
+            begin
+            saved_current_instruction_wen   = 1\'d1; // Save the memory access instruction to refer back to later
+            pc_wen_nxt                      = 1\'d0; // hold current PC value
+            address_sel_nxt                 = 4\'d3; // pc  (not pc + 4)
+
+            if ( instruction[20] ) // MRC
+                copro_operation_nxt         = 2\'d1;  // Register transfer from Co-Processor
+            else // MCR
+                begin
+                 // Don\'t enable operation to Co-Processor until next period
+                 // So'b' it gets the Rd value from the execution stage at the same time
+                copro_operation_nxt      = 2\'d0;
+                copro_write_data_wen_nxt = 1\'d1;  // Rd register value to co-processor
+                end
+            end
+
+
+        if ( itype == SWI || und_request )
+            begin
+            // save address of next instruction to Supervisor Mode LR
+            reg_write_sel_nxt               = 3\'d1;            // pc -4
+            reg_bank_wsel_nxt               = 4\'d14;  // LR
+
+            address_sel_nxt                 = 4\'d2;            // interrupt_vector
+            pc_sel_nxt                      = 2\'d2;            // interrupt_vector
+
+            status_bits_mode_nxt            = interrupt_mode;  // e.g. Supervisor mode
+            status_bits_mode_wen_nxt        = 1\'d1;
+
+            // disable normal interrupts
+            status_bits_irq_mask_nxt        = 1\'d1;
+            status_bits_irq_mask_wen_nxt    = 1\'d1;
+            end
+
+
+        if ( regop_set_flags )
+            begin
+            status_bits_flags_wen_nxt = 1\'d1;
+
+            // If <Rd> is r15, the ALU output is copied to the Status Bits.
+            // Not allowed to use r15 for mul or lma instructions
+            if ( instruction[15:12] == 4\'d15 )
+                begin
+                status_bits_sel_nxt       = 3\'d1; // alu out
+
+                // Priviledged mode? Then also update the other status bits
+                if ( i_execute_status_bits[1:0] != USR )
+                    begin
+                    status_bits_mode_wen_nxt      = 1\'d1;
+                    status_bits_irq_mask_wen_nxt  = 1\'d1;
+                    status_bits_firq_mask_wen_nxt = 1\'d1;
+                    end
+                end
+            end
+
+        end
+
+    // Handle asynchronous interrupts.
+    // interrupts are processed only during execution states
+    // multicycle instructions must complete before the interrupt starts
+    // SWI, Address Exception and Undefined Instruction interrupts are only executed if the
+    // instruction that causes the interrupt is conditionally executed so
+    // its not handled here
+    if ( instruction_valid && interrupt &&  next_interrupt != 3\'d6 )
+        begin
+        // Save the interrupt causing instruction to refer back to later
+        // This also saves the instruction abort vma and status, in the case of an
+        // instruction abort interrupt
+        saved_current_instruction_wen   = 1\'d1;
+
+        // save address of next instruction to Supervisor Mode LR
+        // Address Exception ?
+        if ( next_interrupt == 3\'d4 )
+            reg_write_sel_nxt               = 3\'d7;            // pc
+        else
+            reg_write_sel_nxt               = 3\'d1;            // pc -4
+
+        reg_bank_wsel_nxt               = 4\'d14;           // LR
+
+        address_sel_nxt                 = 4\'d2;            // interrupt_vector
+        pc_sel_nxt                      = 2\'d2;            // interrupt_vector
+
+        status_bits_mode_nxt            = interrupt_mode;  // e.g. Supervisor mode
+        status_bits_mode_wen_nxt        = 1\'d1;
+
+        // disable normal interrupts
+        status_bits_irq_mask_nxt        = 1\'d1;
+        status_bits_irq_mask_wen_nxt    = 1\'d1;
+
+        // disable fast interrupts
+        if ( next_interrupt == 3\'d2 ) // FIRQ
+            begin
+            status_bits_firq_mask_nxt        = 1\'d1;
+            status_bits_firq_mask_wen_nxt    = 1\'d1;
+            end
+        end
+
+
+    // previous instruction was either ldr or sdr
+    // if it is currently executing in the execute stage do the following
+    if ( control_state == MEM_WAIT1 )
+        begin
+        // Save the next instruction to execute later
+        // Do this even if this instruction does not execute because of Condition
+        pre_fetch_instruction_wen   = 1\'d1;
+
+        if ( instruction_execute ) // conditional execution state
+            begin
+            address_sel_nxt             = 4\'d3; // pc  (not pc + 4)
+            pc_wen_nxt                  = 1\'d0; // hold current PC value
+            end
+        end
+
+
+    // completion of load operation
+    if ( control_state == MEM_WAIT2 && load_op )
+        begin
+        barrel_shift_data_sel_nxt   = 2\'d1;  // load word from memory
+        barrel_shift_amount_sel_nxt = 2\'d3;  // shift by address[1:0] x 8
+
+        // shift needed
+        if ( i_execute_address[1:0] != 2\'d0 )
+            barrel_shift_function_nxt = ROR;
+
+        // load a byte
+        if ( itype == TRANS && instruction[22] )
+            alu_out_sel_nxt             = 4\'d3;  // zero_extend8
+
+        if ( !dabt )  // dont load data there is an abort on the data read
+            begin
+            // Check if the load destination is the PC
+            if (instruction[15:12]  == 4\'d15)
+                begin
+                pc_sel_nxt      = 2\'d1; // alu_out
+                address_sel_nxt = 4\'d1; // alu_out
+                end
+            else
+                reg_bank_wsel_nxt = instruction[15:12];
+            end
+        end
+
+
+    // second cycle of multiple load or store
+    if ( control_state == MTRANS_EXEC1 )
+        begin
+        // Save the next instruction to execute later
+        // Do this even if this instruction does not execute because of Condition
+        pre_fetch_instruction_wen   = 1\'d1;
+
+        if ( instruction_execute ) // conditional execution state
+            begin
+            address_sel_nxt             = 4\'d5;  // o_address
+            pc_wen_nxt                  = 1\'d0;  // hold current PC value
+            data_access_exec_nxt        = 1\'d1;  // indicate that its a data read or write,
+                                                 // rather than an instruction fetch
+
+            if ( !instruction[20] ) // Store
+                write_data_wen_nxt = 1\'d1;
+
+            // LDM: load into user mode registers, when in priviledged mode
+            //if ( {instruction[22],instruction[20],mtrans_r15} == 3\'b110 )
+            if ( {instruction[22:20],mtrans_r15} == 4\'b1010 )
+                user_mode_regs_load_nxt = 1\'d1;
+
+            // SDM: store the user mode registers, when in priviledged mode
+            //if ( {instruction[22],instruction[20]} == 2\'b10 )
+            if ( {instruction[22:20]} == 3\'b100 )
+                o_user_mode_regs_store_nxt = 1\'d1;
+            end
+        end
+
+
+        // third cycle of multiple load or store
+    if ( control_state == MTRANS_EXEC2 )
+        begin
+        address_sel_nxt             = 4\'d5;  // o_address
+        pc_wen_nxt                  = 1\'d0;  // hold current PC value
+        data_access_exec_nxt        = 1\'d1;  // indicate that its a data read or write,
+                                             // rather than an instruction fetch
+        barrel_shift_data_sel_nxt   = 2\'d1;  // load word from memory
+
+        // Load or Store
+        if ( instruction[20] ) // Load
+            begin
+            // Can never be loading the PC in this state, as the PC is always
+            // the last register in the set to be loaded
+            if ( !dabt )
+                reg_bank_wsel_nxt = mtrans_reg_d2;
+            end
+        else // Store
+            write_data_wen_nxt = 1\'d1;
+
+        // LDM: load into user mode registers, when in priviledged mode
+        if ( {instruction[22],instruction[20],mtrans_r15} == 3\'b110 )
+            user_mode_regs_load_nxt = 1\'d1;
+
+        // SDM: store the user mode registers, when in priviledged mode
+        if ( {instruction[22],instruction[20]} == 2\'b10 )
+            o_user_mode_regs_store_nxt = 1\'d1;
+        end
+
+
+        // second or fourth cycle of multiple load or store
+    if ( control_state == MTRANS_EXEC3 && instruction_execute )
+        begin
+        address_sel_nxt             = 4\'d3; // pc  (not pc + 4)
+        pc_wen_nxt                  = 1\'d0;  // hold current PC value
+        barrel_shift_data_sel_nxt   = 2\'d1;  // load word from memory
+
+        // Can never be loading the PC in this state, as the PC is always
+        // the last register in the set to be loaded
+        if ( instruction[20] && !dabt ) // Load
+            reg_bank_wsel_nxt = mtrans_reg_d2;
+
+        // LDM: load into user mode registers, when in priviledged mode
+        if ( {instruction[22],instruction[20],mtrans_r15} == 3\'b110 )
+            user_mode_regs_load_nxt = 1\'d1;
+
+        // SDM: store the user mode registers, when in priviledged mode
+        //if ( {instruction[22:20]} == 3\'b100 )
+        if ( {instruction[22],instruction[20]} == 2\'b10 )
+            o_user_mode_regs_store_nxt = 1\'d1;
+       end
+
+    // state is used for LMD/STM of a single register
+    if ( control_state == MTRANS_EXEC3B && instruction_execute )
+        begin
+        // Save the next instruction to execute later
+        // Do this even if this instruction does not execute because of Condition
+        pre_fetch_instruction_wen   = 1\'d1;
+
+        address_sel_nxt             = 4\'d3;  // pc  (not pc + 4)
+        pc_wen_nxt                  = 1\'d0;  // hold current PC value
+
+        // LDM: load into user mode registers, when in priviledged mode
+        if ( {instruction[22],instruction[20],mtrans_r15} == 3\'b110 )
+            user_mode_regs_load_nxt = 1\'d1;
+
+        // SDM: store the user mode registers, when in priviledged mode
+        if ( {instruction[22],instruction[20]} == 2\'b10 )
+            o_user_mode_regs_store_nxt = 1\'d1;
+        end
+
+    if ( control_state == MTRANS_EXEC4 )
+        begin
+        barrel_shift_data_sel_nxt   = 2\'d1;  // load word from memory
+
+        if ( instruction[20] ) // Load
+            begin
+            if (!dabt) // dont overwrite registers or status if theres a data abort
+                begin
+                if ( mtrans_reg_d2 == 4\'d15 ) // load new value into PC
+                    begin
+                    address_sel_nxt = 4\'d1; // alu_out - read instructions using new PC value
+                    pc_sel_nxt      = 2\'d1; // alu_out
+                    pc_wen_nxt      = 1\'d1; // write PC
+
+                    // ldm with S bit and pc: the Status bits are updated
+                    // Node this must be done only at the end
+                    // so the register set is the set in the mode before it
+                    // gets changed.
+                    if ( instruction[22] )
+                         begin
+                         status_bits_sel_nxt           = 3\'d1; // alu out
+                         status_bits_flags_wen_nxt     = 1\'d1;
+
+                         // Can\'t change the mode or mask bits in User mode
+                         if ( i_execute_status_bits[1:0] != USR )
+                            begin
+                            status_bits_mode_wen_nxt      = 1\'d1;
+                            status_bits_irq_mask_wen_nxt  = 1\'d1;
+                            status_bits_firq_mask_wen_nxt = 1\'d1;
+                            end
+                         end
+                    end
+                else
+                    begin
+                    reg_bank_wsel_nxt = mtrans_reg_d2;
+                    end
+                end
+            end
+
+           // we have a data abort interrupt
+        if ( dabt )
+            begin
+            pc_wen_nxt = 1\'d0;  // hold current PC value
+            end
+
+        // LDM: load into user mode registers, when in priviledged mode
+        if ( {instruction[22],instruction[20],mtrans_r15} == 3\'b110 )
+            user_mode_regs_load_nxt = 1\'d1;
+
+        // SDM: store the user mode registers, when in priviledged mode
+        if ( {instruction[22],instruction[20]} == 2\'b10 )
+            o_user_mode_regs_store_nxt = 1\'d1;
+        end
+
+
+    // state is for when a data abort interrupt is triggered during an LDM
+    if ( control_state == MTRANS5_ABORT )
+        begin
+        // Restore the Base Address, if the base register is included in the
+        // list of registers being loaded
+        if (restore_base_address) // LDM with base address in register list
+            begin
+            reg_write_sel_nxt = 3\'d6;                        // write base_register
+            reg_bank_wsel_nxt  = instruction[19:16];         // to Rn
+            end
+        end
+
+
+        // Multiply or Multiply-Accumulate
+    if ( control_state == MULT_PROC1 && instruction_execute )
+        begin
+        // Save the next instruction to execute later
+        // Do this even if this instruction does not execute because of Condition
+        pre_fetch_instruction_wen   = 1\'d1;
+        pc_wen_nxt                  = 1\'d0;  // hold current PC value
+        multiply_function_nxt       = o_multiply_function;
+        end
+
+
+        // Multiply or Multiply-Accumulate
+        // Do multiplication
+        // Wait for done or accumulate signal
+    if ( control_state == MULT_PROC2 )
+        begin
+        // Save the next instruction to execute later
+        // Do this even if this instruction does not execute because of Condition
+        pc_wen_nxt              = 1\'d0;  // hold current PC value
+        address_sel_nxt         = 4\'d3;  // pc  (not pc + 4)
+        multiply_function_nxt   = o_multiply_function;
+        end
+
+
+    // Save RdLo
+    // always last cycle of all multiply or multiply accumulate operations
+    if ( control_state == MULT_STORE )
+        begin
+        reg_write_sel_nxt     = 3\'d2; // multiply_out
+        multiply_function_nxt = o_multiply_function;
+
+        if ( itype == MULT ) // 32-bit
+            reg_bank_wsel_nxt      = instruction[19:16]; // Rd
+        else  // 64-bit / Long
+            reg_bank_wsel_nxt      = instruction[15:12]; // RdLo
+
+        if ( instruction[20] )  // the \'S\' bit
+            begin
+            status_bits_sel_nxt       = 3\'d4; // { multiply_flags, status_bits_flags[1:0] }
+            status_bits_flags_wen_nxt = 1\'d1;
+            end
+        end
+
+        // Add lower 32 bits to multiplication product
+    if ( control_state == MULT_ACCUMU )
+        begin
+        multiply_function_nxt = o_multiply_function;
+        pc_wen_nxt            = 1\'d0;  // hold current PC value
+        address_sel_nxt       = 4\'d3;  // pc  (not pc + 4)
+        end
+
+    // swp - do write request in 2nd cycle
+    if ( control_state == SWAP_WRITE && instruction_execute )
+        begin
+        barrel_shift_data_sel_nxt       = 2\'d2; // Shift value from Rm register
+        address_sel_nxt                 = 4\'d4; // Rn
+        write_data_wen_nxt              = 1\'d1;
+        data_access_exec_nxt            = 1\'d1; // indicate that its a data read or write,
+                                                // rather than an instruction fetch
+
+        if ( instruction[22] )
+            byte_enable_sel_nxt = 2\'d1;         // Save byte
+
+        if ( instruction_execute )                         // conditional execution state
+            pc_wen_nxt                  = 1\'d0; // hold current PC value
+
+        // Save the next instruction to execute later
+        // Do this even if this instruction does not execute because of Condition
+        pre_fetch_instruction_wen   = 1\'d1;
+
+        end
+
+
+    // swp - receive read response in 3rd cycle
+    if ( control_state == SWAP_WAIT1 )
+        begin
+        barrel_shift_data_sel_nxt   = 2\'d1;  // load word from memory
+        barrel_shift_amount_sel_nxt = 2\'d3;  // shift by address[1:0] x 8
+
+        // shift needed
+        if ( i_execute_address[1:0] != 2\'d0 )
+            barrel_shift_function_nxt = ROR;
+
+        if ( instruction_execute ) // conditional execution state
+            begin
+            address_sel_nxt             = 4\'d3; // pc  (not pc + 4)
+            pc_wen_nxt                  = 1\'d0; // hold current PC value
+            end
+
+        // load a byte
+        if ( instruction[22] )
+            alu_out_sel_nxt = 4\'d3;  // zero_extend8
+
+        if ( !dabt )
+            begin
+            // Check is the load destination is the PC
+            if ( instruction[15:12]  == 4\'d15 )
+                begin
+                pc_sel_nxt      = 2\'d1; // alu_out
+                address_sel_nxt = 4\'d1; // alu_out
+                end
+            else
+                reg_bank_wsel_nxt = instruction[15:12];
+            end
+        end
+
+    // 1 cycle delay for Co-Processor Register access
+    if ( control_state == COPRO_WAIT && instruction_execute )
+        begin
+        pre_fetch_instruction_wen = 1\'d1;
+
+        if ( instruction[20] ) // mrc instruction
+            begin
+            // Check is the load destination is the PC
+            if ( instruction[15:12]  == 4\'d15 )
+                begin
+                // If r15 is specified for <Rd>, the condition code flags are
+                // updated instead of a general-purpose register.
+                status_bits_sel_nxt           = 3\'d3;  // i_copro_data
+                status_bits_flags_wen_nxt     = 1\'d1;
+
+                // Can\'t change these in USR mode
+                if ( i_execute_status_bits[1:0] != USR )
+                   begin
+                   status_bits_mode_wen_nxt      = 1\'d1;
+                   status_bits_irq_mask_wen_nxt  = 1\'d1;
+                   status_bits_firq_mask_wen_nxt = 1\'d1;
+                   end
+                end
+            else
+                reg_bank_wsel_nxt = instruction[15:12];
+
+            reg_write_sel_nxt = 3\'d5;     // i_copro_data
+            end
+        else // mcr instruction
+            begin
+            copro_operation_nxt      = 2\'d2;  // Register transfer to Co-Processor
+            end
+        end
+
+
+    // Have just changed the status_bits mode but this
+    // creates a 1 cycle gap with the old mode
+    // coming back from execute into instruction_decode
+    // So squash that old mode value during this
+    // cycle of the interrupt transition
+    if ( control_state == INT_WAIT1 )
+        status_bits_mode_nxt            = status_bits_mode_r;   // Supervisor mode
+
+    end
+
+
+// Speed up the long path from u_decode/o_read_data to u_register_bank/r8_firq
+// This pre-encodes the firq_s3 signal thats used in u_register_bank
+assign firq_not_user_mode_nxt = !user_mode_regs_load_nxt && status_bits_mode_nxt == FIRQ;
+
+
+// ========================================================
+// Next State Logic
+// ========================================================
+
+// this replicates the current value of the execute signal in the execute stage
+assign instruction_execute = conditional_execute ( condition_r, i_execute_status_bits[31:28] );
+
+assign instruction_valid = (control_state == EXECUTE || control_state == PRE_FETCH_EXEC) ||
+                     // when last instruction was multi-cycle instruction but did not execute
+                     // because condition was false then act like you\'re in the execute state
+                    (!instruction_execute && (control_state == PC_STALL1    ||
+                                              control_state == MEM_WAIT1    ||
+                                              control_state == COPRO_WAIT   ||
+                                              control_state == SWAP_WRITE   ||
+                                              control_state == MULT_PROC1   ||
+                                              control_state == MTRANS_EXEC1 ||
+                                              control_state == MTRANS_EXEC3 ||
+                                              control_state == MTRANS_EXEC3B  ) );
+
+
+ always @*
+    begin
+    // default is to hold the current state
+    control_state_nxt = control_state;
+
+    // Note: The order is important here
+    if ( control_state == RST_WAIT1 )     control_state_nxt = RST_WAIT2;
+    if ( control_state == RST_WAIT2 )     control_state_nxt = EXECUTE;
+    if ( control_state == INT_WAIT1 )     control_state_nxt = INT_WAIT2;
+    if ( control_state == INT_WAIT2 )     control_state_nxt = EXECUTE;
+    if ( control_state == COPRO_WAIT )    control_state_nxt = PRE_FETCH_EXEC;
+    if ( control_state == PC_STALL1 )     control_state_nxt = PC_STALL2;
+    if ( control_state == PC_STALL2 )     control_state_nxt = EXECUTE;
+    if ( control_state == SWAP_WRITE )    control_state_nxt = SWAP_WAIT1;
+    if ( control_state == SWAP_WAIT1 )    control_state_nxt = SWAP_WAIT2;
+    if ( control_state == MULT_STORE )    control_state_nxt = PRE_FETCH_EXEC;
+    if ( control_state == MTRANS5_ABORT ) control_state_nxt = PRE_FETCH_EXEC;
+
+    if ( control_state == MEM_WAIT1 )
+        control_state_nxt = MEM_WAIT2;
+
+    if ( control_state == MEM_WAIT2   ||
+        control_state == SWAP_WAIT2    )
+        begin
+        if ( write_pc ) // writing to the PC!!
+            control_state_nxt = PC_STALL1;
+        else
+            control_state_nxt = PRE_FETCH_EXEC;
+        end
+
+    if ( control_state == MTRANS_EXEC1 )
+        begin
+        if (mtrans_instruction_nxt[15:0] != 16\'d0)
+            control_state_nxt = MTRANS_EXEC2;
+        else   // if the register list holds a single register
+            control_state_nxt = MTRANS_EXEC3;
+        end
+
+        // Stay in State MTRANS_EXEC2 until the full list of registers to
+        // load or store has been processed
+    if ( control_state == MTRANS_EXEC2 && mtrans_num_registers == 5\'d1 )
+        control_state_nxt = MTRANS_EXEC3;
+
+    if ( control_state == MTRANS_EXEC3 )     control_state_nxt = MTRANS_EXEC4;
+
+    if ( control_state == MTRANS_EXEC3B )    control_state_nxt = MTRANS_EXEC4;
+
+    if ( control_state == MTRANS_EXEC4  )
+        begin
+        if ( dabt ) // data abort
+            control_state_nxt = MTRANS5_ABORT;
+        else if (write_pc) // writing to the PC!!
+            control_state_nxt = PC_STALL1;
+        else
+            control_state_nxt = PRE_FETCH_EXEC;
+        end
+
+    if ( control_state == MULT_PROC1 )
+        begin
+        if (!instruction_execute)
+            control_state_nxt = PRE_FETCH_EXEC;
+        else
+            control_state_nxt = MULT_PROC2;
+        end
+
+    if ( control_state == MULT_PROC2 )
+        begin
+        if ( i_multiply_done )
+            if      ( o_multiply_function[1] )  // Accumulate ?
+                control_state_nxt = MULT_ACCUMU;
+            else
+                control_state_nxt = MULT_STORE;
+        end
+
+
+    if ( control_state == MULT_ACCUMU )
+        begin
+        control_state_nxt = MULT_STORE;
+        end
+
+
+    // This should come at the end, so that conditional execution works
+    // correctly
+    if ( instruction_valid )
+        begin
+        // default is to stay in execute state, or to move into this
+        // state from a conditional execute state
+        control_state_nxt = EXECUTE;
+
+        if ( mem_op )  // load or store word or byte
+             control_state_nxt = MEM_WAIT1;
+        if ( write_pc )
+             control_state_nxt = PC_STALL1;
+        if ( itype == MTRANS )
+            begin
+            if ( mtrans_num_registers != 5\'d0 )
+                begin
+                // check for LDM/STM of a single register
+                if ( mtrans_num_registers == 5\'d1 )
+                    control_state_nxt = MTRANS_EXEC3B;
+                else
+                    control_state_nxt = MTRANS_EXEC1;
+                end
+            else
+                control_state_nxt = MTRANS_EXEC3;
+            end
+
+        if ( itype == MULT )
+                control_state_nxt = MULT_PROC1;
+
+        if ( itype == SWAP )
+                control_state_nxt = SWAP_WRITE;
+
+        if ( itype == CORTRANS && !und_request )
+                control_state_nxt = COPRO_WAIT;
+
+         // interrupt overrides everything else so its last
+        if ( interrupt )
+                control_state_nxt = INT_WAIT1;
+        end
+    end
+
+
+// ========================================================
+// Register Update
+// ========================================================
+always @ ( posedge i_clk )
+    if (!i_fetch_stall)
+        begin
+        o_read_data                 <= i_read_data;
+        o_read_data_alignment       <= {i_execute_address[1:0], 3\'d0};
+        abt_address_reg             <= i_execute_address;
+        iabt_reg                    <= i_iabt;
+        adex_reg                    <= i_adex;
+        abt_status_reg              <= i_abt_status;
+        status_bits_mode_r          <= status_bits_mode_nxt;
+        status_bits_irq_mask_r      <= status_bits_irq_mask_nxt;
+        status_bits_firq_mask_r     <= status_bits_firq_mask_nxt;
+        o_imm32                     <= imm32_nxt;
+        o_imm_shift_amount          <= imm_shift_amount_nxt;
+        o_shift_imm_zero            <= shift_imm_zero_nxt;
+
+                                        // when have an interrupt, execute the interrupt operation
+                                        // unconditionally in the execute stage
+                                        // ensures that status_bits register gets updated correctly
+                                        // Likewise when in middle of multi-cycle instructions
+                                        // execute them unconditionally
+        condition_r                 <= instruction_valid && !interrupt ? condition_nxt : AL;
+        o_exclusive_exec            <= exclusive_exec_nxt;
+        o_data_access_exec          <= data_access_exec_nxt;
+
+        o_rm_sel                    <= o_rm_sel_nxt;
+        o_rds_sel                   <= o_rds_sel_nxt;
+        o_rn_sel                    <= o_rn_sel_nxt;
+        o_barrel_shift_amount_sel   <= barrel_shift_amount_sel_nxt;
+        o_barrel_shift_data_sel     <= barrel_shift_data_sel_nxt;
+        o_barrel_shift_function     <= barrel_shift_function_nxt;
+        o_alu_function              <= alu_function_nxt;
+        o_use_carry_in              <= use_carry_in_nxt;
+        o_multiply_function         <= multiply_function_nxt;
+        o_interrupt_vector_sel      <= next_interrupt;
+        address_sel_r               <= address_sel_nxt;
+        pc_sel_r                    <= pc_sel_nxt;
+        o_byte_enable_sel           <= byte_enable_sel_nxt;
+        o_status_bits_sel           <= status_bits_sel_nxt;
+        o_reg_write_sel             <= reg_write_sel_nxt;
+        o_user_mode_regs_load       <= user_mode_regs_load_nxt;
+        o_firq_not_user_mode        <= firq_not_user_mode_nxt;
+        o_write_data_wen            <= write_data_wen_nxt;
+        o_base_address_wen          <= base_address_wen_nxt;
+        pc_wen_r                    <= pc_wen_nxt;
+        o_reg_bank_wsel             <= reg_bank_wsel_nxt;
+        o_reg_bank_wen              <= decode ( reg_bank_wsel_nxt );
+        o_status_bits_flags_wen     <= status_bits_flags_wen_nxt;
+        o_status_bits_mode_wen      <= status_bits_mode_wen_nxt;
+        o_status_bits_irq_mask_wen  <= status_bits_irq_mask_wen_nxt;
+        o_status_bits_firq_mask_wen <= status_bits_firq_mask_wen_nxt;
+
+        o_copro_opcode1             <= instruction[23:21];
+        o_copro_opcode2             <= instruction[7:5];
+        o_copro_crn                 <= instruction[19:16];
+        o_copro_crm                 <= instruction[3:0];
+        o_copro_num                 <= instruction[11:8];
+        o_copro_operation           <= copro_operation_nxt;
+        o_copro_write_data_wen      <= copro_write_data_wen_nxt;
+        mtrans_r15                  <= mtrans_r15_nxt;
+        restore_base_address        <= restore_base_address_nxt;
+        control_state               <= control_state_nxt;
+        mtrans_reg_d1               <= mtrans_reg;
+        mtrans_reg_d2               <= mtrans_reg_d1;
+        end
+
+
+
+always @ ( posedge i_clk )
+    if ( !i_fetch_stall )
+        begin
+        // sometimes this is a pre-fetch instruction
+        // e.g. two ldr instructions in a row. The second ldr will be saved
+        // to the pre-fetch instruction register
+        // then when its decoded, a copy is saved to the saved_current_instruction
+        // register
+        if      (itype == MTRANS)
+            begin
+            saved_current_instruction              <= mtrans_instruction_nxt;
+            saved_current_instruction_iabt         <= instruction_iabt;
+            saved_current_instruction_adex         <= instruction_adex;
+            saved_current_instruction_address      <= instruction_address;
+            saved_current_instruction_iabt_status  <= instruction_iabt_status;
+            end
+        else if (saved_current_instruction_wen)
+            begin
+            saved_current_instruction              <= instruction;
+            saved_current_instruction_iabt         <= instruction_iabt;
+            saved_current_instruction_adex         <= instruction_adex;
+            saved_current_instruction_address      <= instruction_address;
+            saved_current_instruction_iabt_status  <= instruction_iabt_status;
+            end
+
+        if      (pre_fetch_instruction_wen)
+            begin
+            pre_fetch_instruction                  <= o_read_data;
+            pre_fetch_instruction_iabt             <= iabt_reg;
+            pre_fetch_instruction_adex             <= adex_reg;
+            pre_fetch_instruction_address          <= abt_address_reg;
+            pre_fetch_instruction_iabt_status      <= abt_status_reg;
+            end
+        end
+
+
+
+always @ ( posedge i_clk )
+    if ( !i_fetch_stall )
+        begin
+        irq   <= i_irq;
+        firq  <= i_firq;
+
+        if ( control_state == INT_WAIT1 && status_bits_mode_r == SVC )
+            begin
+            dabt_reg  <= 1\'d0;
+            end
+        else
+            begin
+            dabt_reg  <= dabt_reg || i_dabt;
+            end
+
+        dabt_reg_d1  <= dabt_reg;
+        end
+
+assign dabt = dabt_reg || i_dabt;
+
+
+// ========================================================
+// Decompiler for debugging core - not synthesizable
+// ========================================================
+//synopsys translate_off
+
+`include ""debug_functions.vh""
+
+a23_decompile  u_decompile (
+    .i_clk                      ( i_clk                            ),
+    .i_fetch_stall              ( i_fetch_stall                    ),
+    .i_instruction              ( instruction                      ),
+    .i_instruction_valid        ( instruction_valid                ),
+    .i_instruction_execute      ( instruction_execute              ),
+    .i_instruction_address      ( instruction_address              ),
+    .i_interrupt                ( {3{interrupt}} & next_interrupt  ),
+    .i_interrupt_state          ( control_state == INT_WAIT2       ),
+    .i_instruction_undefined    ( und_request                      ),
+    .i_pc_sel                   ( pc_sel_r                         ),
+    .i_pc_wen                   ( pc_wen_r                         ));
+
+
+
+wire    [(15*8)-1:0]    xCONTROL_STATE;
+wire    [(15*8)-1:0]    xMODE;
+
+assign xCONTROL_STATE        =
+                               control_state == RST_WAIT1      ? ""RST_WAIT1""      :
+                               control_state == RST_WAIT2      ? ""RST_WAIT2""      :
+
+
+                               control_state == INT_WAIT1      ? ""INT_WAIT1""      :
+                               control_state == INT_WAIT2      ? ""INT_WAIT2""      :
+                               control_state == EXECUTE        ? ""EXECUTE""        :
+                               control_state == PRE_FETCH_EXEC ? ""PRE_FETCH_EXEC"" :
+                               control_state == MEM_WAIT1      ? ""MEM_WAIT1""      :
+                               control_state == MEM_WAIT2      ? ""MEM_WAIT2""      :
+                               control_state == PC_STALL1      ? ""PC_STALL1""      :
+                               control_state == PC_STALL2      ? ""PC_STALL2""      :
+                               control_state == MTRANS_EXEC1   ? ""MTRANS_EXEC1""   :
+                               control_state == MTRANS_EXEC2   ? ""MTRANS_EXEC2""   :
+                               control_state == MTRANS_EXEC3   ? ""MTRANS_EXEC3""   :
+                               control_state == MTRANS_EXEC3B  ? ""MTRANS_EXEC3B""  :
+                               control_state == MTRANS_EXEC4   ? ""MTRANS_EXEC4""   :
+                               control_state == MTRANS5_ABORT  ? ""MTRANS5_ABORT""  :
+                               control_state == MULT_PROC1     ? ""MULT_PROC1""     :
+                               control_state == MULT_PROC2     ? ""MULT_PROC2""     :
+                               control_state == MULT_STORE     ? ""MULT_STORE""     :
+                               control_state == MULT_ACCUMU    ? ""MULT_ACCUMU""    :
+                               control_state == SWAP_WRITE     ? ""SWAP_WRITE""     :
+                               control_state == SWAP_WAIT1     ? ""SWAP_WAIT1""     :
+                               control_state == SWAP_WAIT2     ? ""SWAP_WAIT2""     :
+                               control_state == COPRO_WAIT     ? ""COPRO_WAIT""     :
+                                                                 ""UNKNOWN ""       ;
+
+assign xMODE  = mode_name ( status_bits_mode_r );
+
+always @( posedge i_clk )
+    if (control_state == EXECUTE && ((instruction[0] === 1\'bx) || (instruction[31] === 1\'bx)))
+        begin
+        `TB_ERROR_MESSAGE
+        $display(""Instruction with x\'s =%08h"", instruction);
+        end
+//synopsys translate_on
+
+endmodule
+
+
+"
+"//////////////////////////////////////////////////////////////////
+//                                                              //
+//  Fetch - Instantiates the fetch stage sub-modules of         //
+//  the Amber 2 Core                                            //
+//                                                              //
+//  This file is part of the Amber project                      //
+//  http://www.opencores.org/project,amber                      //
+//                                                              //
+//  Description                                                 //
+//  Instantiates the Cache and Wishbone I/F                     //
+//  Also contains a little bit of logic to decode memory        //
+//  accesses to decide if they are cached or not                //
+//                                                              //
+//  Author(s):                                                  //
+//      - Conor Santifort, csantifort.amber@gmail.com           //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+//                                                              //
+// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
+//                                                              //
+// This source file may be used and distributed without         //
+// restriction provided that this copyright statement is not    //
+// removed from the file and that any derivative work contains  //
+// the original copyright notice and the associated disclaimer. //
+//                                                              //
+// This source file is free software; you can redistribute it   //
+// and/or modify it under the terms of the GNU Lesser General   //
+// Public License as published by the Free Software Foundation; //
+// either version 2.1 of the License, or (at your option) any   //
+// later version.                                               //
+//                                                              //
+// This source is distributed in the hope that it will be       //
+// useful, but WITHOUT ANY WARRANTY; without even the implied   //
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
+// PURPOSE.  See the GNU Lesser General Public License for more //
+// details.                                                     //
+//                                                              //
+// You should have received a copy of the GNU Lesser General    //
+// Public License along with this source; if not, download it   //
+// from http://www.opencores.org/lgpl.shtml                     //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+
+
+module a23_fetch
+(
+input                       i_clk,
+
+input       [31:0]          i_address,
+input                       i_address_valid,
+input       [31:0]          i_address_nxt,      // un-registered version of address to the cache rams
+input       [31:0]          i_write_data,
+input                       i_write_enable,
+output       [31:0]         o_read_data,
+input                       i_priviledged,
+input                       i_exclusive,        // high for read part of swap access
+input       [3:0]           i_byte_enable,
+input                       i_data_access,      // high for data petch, low for instruction fetch
+input                       i_cache_enable,     // cache enable
+input                       i_cache_flush,      // cache flush
+input       [31:0]          i_cacheable_area,   // each bit corresponds to 2MB address space
+input                       i_system_rdy,
+output                      o_fetch_stall,      // when this is asserted all registers 
+                                                // in all 3 pipeline stages are held
+                                                // at their current values
+
+// Wishbone Master I/F
+output      [31:0]          o_wb_adr,
+output      [3:0]           o_wb_sel,
+output                      o_wb_we,
+input       [31:0]          i_wb_dat,
+output      [31:0]          o_wb_dat,
+output                      o_wb_cyc,
+output                      o_wb_stb,
+input                       i_wb_ack,
+input                       i_wb_err
+
+);
+
+//`include ""memory_configuration.vh""
+
+function in_cachable_mem;
+    input [31:0] address;
+begin
+    in_cachable_mem = 1\'b0 ; 
+end
+endfunction
+
+wire                        cache_stall;
+wire                        wb_stall;
+wire    [31:0]              cache_read_data;
+wire                        sel_cache;
+wire                        sel_wb;
+wire                        cache_wb_req;
+wire                        address_cachable;
+
+// ======================================
+// Memory Decode
+// ======================================
+assign address_cachable  = in_cachable_mem( i_address ) && i_cacheable_area[i_address[25:21]];
+
+assign sel_cache         = address_cachable && i_address_valid && i_cache_enable &&  !i_exclusive;
+
+// Don\'t start wishbone transfers when the cache is stalling the core
+// The cache stalls the core during its initialization sequence
+assign sel_wb            = !sel_cache && i_address_valid && !(cache_stall);
+
+// Return read data either from the wishbone bus or the cache
+assign o_read_data       = sel_cache  ? cache_read_data : 
+                           sel_wb     ? i_wb_dat        :
+                                        32\'hffeeddcc    ;
+
+// Stall the instruction decode and execute stages of the core
+// when the fetch stage needs more than 1 cycle to return the requested
+// read data
+assign o_fetch_stall     = !i_system_rdy || wb_stall || cache_stall;
+
+
+// ======================================
+// L1 Cache (Unified Instruction and Data)
+// ======================================
+a23_cache u_cache (
+    .i_clk                      ( i_clk                 ),
+     
+    .i_select                   ( sel_cache             ),
+    .i_exclusive                ( i_exclusive           ),
+    .i_write_data               ( i_write_data          ),
+    .i_write_enable             ( i_write_enable        ),
+    .i_address                  ( i_address             ),
+    .i_address_nxt              ( i_address_nxt         ),
+    .i_byte_enable              ( i_byte_enable         ),
+    .i_cache_enable             ( i_cache_enable        ),
+    .i_cache_flush              ( i_cache_flush         ),
+    .o_read_data                ( cache_read_data       ),
+    
+    .o_stall                    ( cache_stall           ),
+    .i_core_stall               ( o_fetch_stall         ),
+    .o_wb_req                   ( cache_wb_req          ),
+    .i_wb_address               ( o_wb_adr              ),
+    .i_wb_read_data             ( i_wb_dat              ),
+    .i_wb_stall                 ( o_wb_stb & ~i_wb_ack  )
+);
+
+
+
+// ======================================
+//  Wishbone Master I/F
+// ======================================
+a23_wishbone u_wishbone (
+    // CPU Side
+    .i_clk                      ( i_clk                 ),
+    
+    // Core Accesses to Wishbone bus
+    .i_select                   ( sel_wb                ),
+    .i_write_data               ( i_write_data          ),
+    .i_write_enable             ( i_write_enable        ),
+    .i_byte_enable              ( i_byte_enable         ),
+    .i_data_access              ( i_data_access         ),
+    .i_exclusive                ( i_exclusive           ),
+    .i_address                  ( i_address             ),
+    .o_stall                    ( wb_stall              ),
+
+    // Cache Accesses to Wishbone bus 
+    // L1 Cache enable - used for hprot
+    .i_cache_req                ( cache_wb_req          ),
+
+    .o_wb_adr                   ( o_wb_adr              ),
+    .o_wb_sel                   ( o_wb_sel              ),
+    .o_wb_we                    ( o_wb_we               ),
+    .i_wb_dat                   ( i_wb_dat              ),
+    .o_wb_dat                   ( o_wb_dat              ),
+    .o_wb_cyc                   ( o_wb_cyc              ),
+    .o_wb_stb                   ( o_wb_stb              ),
+    .i_wb_ack                   ( i_wb_ack              ),
+    .i_wb_err                   ( i_wb_err              )
+);
+
+
+endmodule
+
+"
+"/*
+ *  Opcode decoder lookup table for Zet
+ *  Copyright (C) 2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+`include ""defines.v""
+
+module zet_opcode_deco (
+    input [7:0] op,
+    input [7:0] modrm,
+    input       rep,
+    input [2:0] sovr_pr,
+
+    output reg [`MICRO_ADDR_WIDTH-1:0] seq_addr,
+    output reg need_modrm,
+    output reg need_off,
+    output reg need_imm,
+    output     off_size,
+    output reg imm_size,
+
+    output reg [3:0] src,
+    output reg [3:0] dst,
+    output [3:0] base,
+    output [3:0] index,
+    output [1:0] seg
+  );
+
+  // Net declarations
+  wire [1:0] mod;
+  wire [2:0] regm;
+  wire [2:0] rm;
+  wire       d, b, sm, dm;
+  wire       off_size_mod, need_off_mod;
+  wire [2:0] srcm, dstm;
+  wire       off_size_from_mod;
+
+  // Module instantiations
+  zet_memory_regs memory_regs (rm, mod, sovr_pr, base, index, seg);
+
+  // Assignments
+  assign mod  = modrm[7:6];
+  assign regm = modrm[5:3];
+  assign rm   = modrm[2:0];
+  assign d    = op[1];
+  assign dstm = d ? regm : rm;
+  assign sm   = d & (mod != 2\'b11);
+  assign dm   = ~d & (mod != 2\'b11);
+  assign srcm = d ? rm : regm;
+  assign b    = ~op[0];
+  assign off_size_mod = (base == 4\'b1100 && index == 4\'b1100) ? 1\'b1 : mod[1];
+  assign need_off_mod = (base == 4\'b1100 && index == 4\'b1100) || ^mod;
+  assign off_size_from_mod = !op[7] | (!op[5] & !op[4]) | (op[6] & op[4]);
+  assign off_size = !off_size_from_mod | off_size_mod;
+
+  // Behaviour
+  always @(op or dm or b or need_off_mod or srcm or sm or dstm
+           or mod or rm or regm or rep or modrm)
+    casex (op)
+      8\'b00xx_x00x: // add/or/adc/sbb/and/sub/xor/cmp r->r, r->m
+        begin
+          seq_addr   <= (mod==2\'b11) ? (b ? `LOGRRB : `LOGRRW)
+                                     : (b ? `LOGRMB : `LOGRMW);
+          need_modrm <= 1\'b1;
+          need_off   <= need_off_mod;
+          need_imm   <= 1\'b0;
+          imm_size   <= 1\'b0;
+          dst        <= { 1\'b0, dstm };
+          src        <= { 1\'b0, srcm };
+        end
+
+      8\'b00xx_x01x: // add/or/adc/sbb/and/sub/xor/cmp r->r, m->r
+        begin
+          seq_addr   <= (mod==2\'b11) ? (b ? `LOGRRB : `LOGRRW)
+                                     : (b ? `LOGMRB : `LOGMRW);
+          need_modrm <= 1\'b1;
+          need_off   <= need_off_mod;
+          need_imm   <= 1\'b0;
+          imm_size   <= 1\'b0;
+          dst        <= { 1\'b0, dstm };
+          src        <= { 1\'b0, srcm };
+        end
+
+      8\'b00xx_x10x: // add/or/adc/sbb/and/sub/xor/cmp i->r
+        begin
+          seq_addr   <= b ? `LOGIRB : `LOGIRW;
+          need_modrm <= 1\'b0;
+          need_off   <= 1\'b0;
+          need_imm   <= 1\'b1;
+          imm_size   <= ~b;
+          dst        <= 4\'b0;
+          src        <= 4\'b0;
+        end
+
+      8\'b000x_x110: // push seg
+        begin
+          seq_addr <= `PUSHR;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= { 2\'b10, op[4:3] };
+          dst <= 4\'b0;
+        end
+
+      8\'b000x_x111: // pop seg
+        begin
+          seq_addr <= `POPR;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src      <= 4\'b0;
+          dst      <= { 2\'b10, op[4:3] };
+        end
+
+      8\'b0010_0111: // daa
+        begin
+          seq_addr   <= `DAA;
+          need_modrm <= 1\'b0;
+          need_off   <= 1\'b0;
+          need_imm   <= 1\'b0;
+          imm_size   <= 1\'b0;
+          dst        <= 4\'b0;
+          src        <= 4\'b0;
+        end
+
+      8\'b0010_1111: // das
+        begin
+          seq_addr   <= `DAS;
+          need_modrm <= 1\'b0;
+          need_off   <= 1\'b0;
+          need_imm   <= 1\'b0;
+          imm_size   <= 1\'b0;
+          dst        <= 4\'b0;
+          src        <= 4\'b0;
+        end
+
+      8\'b0011_0111: // aaa
+        begin
+          seq_addr   <= `AAA;
+          need_modrm <= 1\'b0;
+          need_off   <= 1\'b0;
+          need_imm   <= 1\'b0;
+          imm_size   <= 1\'b0;
+          dst        <= 4\'b0;
+          src        <= 4\'b0;
+        end
+
+      8\'b0011_1111: // aas
+        begin
+          seq_addr   <= `AAS;
+          need_modrm <= 1\'b0;
+          need_off   <= 1\'b0;
+          need_imm   <= 1\'b0;
+          imm_size   <= 1\'b0;
+          dst        <= 4\'b0;
+          src        <= 4\'b0;
+        end
+
+      8\'b0100_0xxx: // inc
+        begin
+          seq_addr   <= `INCRW;
+          need_modrm <= 1\'b0;
+          need_off   <= 1\'b0;
+          need_imm   <= 1\'b0;
+          imm_size   <= 1\'b0;
+          dst        <= 4\'b0;
+          src        <= { 1\'b0, op[2:0] };
+        end
+
+      8\'b0100_1xxx: // dec
+        begin
+          seq_addr   <= `DECRW;
+          need_modrm <= 1\'b0;
+          need_off   <= 1\'b0;
+          need_imm   <= 1\'b0;
+          imm_size   <= 1\'b0;
+          dst        <= 4\'b0;
+          src        <= { 1\'b0, op[2:0] };
+        end
+
+      8\'b0101_0xxx: // push reg
+        begin
+          seq_addr <= `PUSHR;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= { 1\'b0, op[2:0] };
+          dst <= 4\'b0;
+        end
+
+      8\'b0101_1xxx: // pop reg
+        begin
+          seq_addr <= `POPR;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= { 1\'b0, op[2:0] };
+        end
+
+      8\'b0110_0000: // pusha
+        begin
+          seq_addr <= `PUSHA;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b0110_0001: // popa
+        begin
+          seq_addr <= `POPA;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+      
+      8\'b0110_10x0: // push imm
+        begin
+          seq_addr <= `PUSHI;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b1;
+          imm_size <= !op[1];
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b0110_10x1: // imul imm
+        begin
+          seq_addr <= (mod==2\'b11) ? `IMULIR : `IMULIM;
+          need_modrm <= 1\'b1;
+          need_off <= need_off_mod;
+          need_imm <= 1\'b1;
+          imm_size <= !op[1];
+          src <= { 1\'b0, rm };
+          dst <= { 1\'b0, regm };
+        end
+
+      8\'b0110_110x: // ins
+        begin
+          seq_addr <= rep ? (b ? `INSBR : `INSWR) : (b ? `INSB : `INSW);
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b0110_111x: // outs
+        begin
+          seq_addr <= rep ? (b ? `OUTSBR : `OUTSWR) : (b ? `OUTSB : `OUTSW);
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+      
+      8\'b0111_xxxx: // jcc
+        begin
+          seq_addr <= `JCC;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b1;
+          imm_size <= 1\'b0;
+          src <= { op[3:0] };
+          dst <= 4\'b0;
+        end
+
+      8\'b1000_00xx: // add/or/adc/sbb/and/sub/xor/cmp imm
+        begin
+          seq_addr <= (mod==2\'b11) ? (b ? `LOGIRB : `LOGIRW)
+                                   : (b ? `LOGIMB : `LOGIMW);
+          need_modrm <= 1\'b1;
+          need_off   <= need_off_mod;
+          need_imm   <= 1\'b1;
+          imm_size   <= !op[1] & op[0];
+          dst        <= { 1\'b0, modrm[2:0] };
+          src        <= 4\'b0;
+        end
+
+      8\'b1000_010x: // test r->r, r->m
+        begin
+          seq_addr   <= (mod==2\'b11) ? (b ? `TSTRRB : `TSTRRW)
+                                     : (b ? `TSTMRB : `TSTMRW);
+          need_modrm <= 1\'b1;
+          need_off   <= need_off_mod;
+          need_imm   <= 1\'b0;
+          imm_size   <= 1\'b0;
+          dst        <= { 1\'b0, srcm };
+          src        <= { 1\'b0, dstm };
+        end
+
+      8\'b1000_011x: // xchg
+        begin
+          seq_addr <= (mod==2\'b11) ? (b ? `XCHRRB : `XCHRRW)
+                                   : (b ? `XCHRMB : `XCHRMW);
+          need_modrm <= 1\'b1;
+          need_off <= need_off_mod;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          dst <= { 1\'b0, dstm };
+          src <= { 1\'b0, srcm };
+        end
+      8\'b1000_10xx: // mov: r->r, r->m, m->r
+        begin
+          if (dm)   // r->m
+            begin
+              seq_addr <= b ? `MOVRMB : `MOVRMW;
+              need_off <= need_off_mod;
+              src <= { 1\'b0, srcm };
+              dst <= 4\'b0;
+            end
+          else if(sm) // m->r
+            begin
+              seq_addr <= b ? `MOVMRB : `MOVMRW;
+              need_off <= need_off_mod;
+              src <= 4\'b0;
+              dst <= { 1\'b0, dstm };
+            end
+          else     // r->r
+            begin
+              seq_addr <= b ? `MOVRRB : `MOVRRW;
+              need_off <= 1\'b0;
+              dst <= { 1\'b0, dstm };
+              src <= { 1\'b0, srcm };
+            end
+          need_imm <= 1\'b0;
+          need_modrm <= 1\'b1;
+          imm_size <= 1\'b0;
+        end
+
+      8\'b1000_1100: // mov: s->m, s->r
+        begin
+          if (dm)   // s->m
+            begin
+              seq_addr <= `MOVRMW;
+              need_off <= need_off_mod;
+              src <= { 1\'b1, srcm };
+              dst <= 4\'b0;
+            end
+          else     // s->r
+            begin
+              seq_addr <= `MOVRRW;
+              need_off <= 1\'b0;
+              src <= { 1\'b1, srcm };
+              dst <= { 1\'b0, dstm };
+            end
+          need_imm <= 1\'b0;
+          need_modrm <= 1\'b1;
+          imm_size <= 1\'b0;
+        end
+
+      8\'b1000_1101: // lea
+        begin
+          seq_addr <= `LEA;
+          need_modrm <= 1\'b1;
+          need_off <= need_off_mod;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= { 1\'b0, srcm };
+          dst <= 4\'b0;
+        end
+
+      8\'b1000_1110: // mov: m->s, r->s
+        begin
+          if (sm)   // m->s
+            begin
+              seq_addr <= `MOVMRW;
+              need_off <= need_off_mod;
+              src <= 4\'b0;
+              dst <= { 1\'b1, dstm };
+            end
+          else     // r->s
+            begin
+              seq_addr <= `MOVRRW;
+              need_off <= 1\'b0;
+              src <= { 1\'b0, srcm };
+              dst <= { 1\'b1, dstm };
+            end
+          need_modrm <= 1\'b1;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+        end
+
+      8\'b1000_1111: // pop mem or (pop reg non-standard)
+        begin
+          seq_addr <= (mod==2\'b11) ? `POPR : `POPM;
+          need_modrm <= 1\'b1;
+          need_off <= need_off_mod;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= { 1\'b0, rm };
+        end
+
+      8\'b1001_0xxx: // nop, xchg acum
+        begin
+          seq_addr <= `XCHRRW;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0000;
+          dst <= { 1\'b0, op[2:0] };
+        end
+
+      8\'b1001_1000: // cbw
+        begin
+          seq_addr   <= `CBW;
+          need_modrm <= 1\'b0;
+          need_off   <= 1\'b0;
+          need_imm   <= 1\'b0;
+          imm_size   <= 1\'b0;
+          dst        <= 4\'b0;
+          src        <= 4\'b0;
+        end
+
+      8\'b1001_1001: // cwd
+        begin
+          seq_addr   <= `CWD;
+          need_modrm <= 1\'b0;
+          need_off   <= 1\'b0;
+          need_imm   <= 1\'b0;
+          imm_size   <= 1\'b0;
+          dst        <= 4\'b0;
+          src        <= 4\'b0;
+        end
+
+      8\'b1001_1010: // call different seg
+        begin
+          seq_addr <= `CALLF;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b1;
+          need_imm <= 1\'b1;
+          imm_size <= 1\'b1;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1001_1011: // wait
+        begin
+          seq_addr <= `NOP;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1001_1100: // pushf
+        begin
+          seq_addr <= `PUSHF;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1001_1101: // popf
+        begin
+          seq_addr <= `POPF;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1001_1110: // sahf
+        begin
+          seq_addr <= `SAHF;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1001_1111: // lahf
+        begin
+          seq_addr <= `LAHF;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1010_000x: // mov: m->a
+        begin
+          seq_addr <= b ? `MOVMAB : `MOVMAW;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b1;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1010_001x: // mov: a->m
+        begin
+          seq_addr <= b ? `MOVAMB : `MOVAMW;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b1;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1010_010x: // movs
+        begin
+          seq_addr <= rep ? (b ? `MOVSBR : `MOVSWR) : (b ? `MOVSB : `MOVSW);
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1010_011x: // cmps
+        begin
+          seq_addr <= rep ? (b ? `CMPSBR : `CMPSWR) : (b ? `CMPSB : `CMPSW);
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1010_100x: // test i->r
+        begin
+          seq_addr   <= b ? `TSTIRB : `TSTIRW;
+          need_modrm <= 1\'b0;
+          need_off   <= 1\'b0;
+          need_imm   <= 1\'b1;
+          imm_size   <= ~b;
+          dst        <= 4\'b0;
+          src        <= 4\'b0;
+        end
+
+      8\'b1010_101x: // stos
+        begin
+          seq_addr <= rep ? (b ? `STOSBR : `STOSWR) : (b ? `STOSB : `STOSW);
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1010_110x: // lods
+        begin
+          seq_addr <= rep ? (b ? `LODSBR : `LODSWR) : (b ? `LODSB : `LODSW);
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1010_111x: // scas
+        begin
+          seq_addr <= rep ? (b ? `SCASBR : `SCASWR) : (b ? `SCASB : `SCASW);
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1011_xxxx: // mov: i->r
+        begin
+          seq_addr <= op[3] ? `MOVIRW : `MOVIRB;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b1;
+          imm_size <= op[3];
+
+          src <= 4\'b0;
+          dst <= { 1\'b0, op[2:0] };
+        end
+
+      8\'b1100_000x: // ror/rol/rcr/rcl/sal/shl/sar/shr imm8/imm16
+        begin
+          seq_addr <= (mod==2\'b11) ? (b ? `RSHIRB : `RSHIRW)
+                                   : (b ? `RSHIMB : `RSHIMW);
+          need_modrm <= 1\'b1;
+          need_off <= need_off_mod;
+          need_imm <= 1\'b1;
+          imm_size <= 1\'b0;
+          src <= rm;
+          dst <= rm;
+        end
+
+      8\'b1100_0010: // ret near with value
+        begin
+          seq_addr <= `RETNV;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b1;
+          imm_size <= 1\'b1;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1100_0011: // ret near
+        begin
+          seq_addr <= `RETN0;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1100_0100: // les
+        begin
+          seq_addr <= `LES;
+          need_modrm <= 1\'b1;
+          need_off <= need_off_mod;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= { 1\'b0, srcm };
+          dst <= 4\'b0;
+        end
+
+      8\'b1100_0101: // lds
+        begin
+          seq_addr <= `LDS;
+          need_modrm <= 1\'b1;
+          need_off <= need_off_mod;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= { 1\'b0, srcm };
+          dst <= 4\'b0;
+        end
+
+      8\'b1100_011x: // mov: i->m (or i->r non-standard)
+        begin
+          seq_addr <= (mod==2\'b11) ? (b ? `MOVIRB : `MOVIRW)
+                                   : (b ? `MOVIMB : `MOVIMW);
+          need_modrm <= 1\'b1;
+          need_off <= need_off_mod;
+          need_imm <= 1\'b1;
+          imm_size <= ~b;
+
+          src <= 4\'b0;
+          dst <= { 1\'b0, rm };
+        end
+
+      8\'b1100_1000: // enter
+        begin
+          seq_addr <= `ENTER;
+          need_modrm <= 1\'b0;
+          need_off <= need_off_mod;
+          need_imm <= 1\'b1;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1100_1001: // leave
+        begin
+          seq_addr <= `LEAVE;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1100_1010: // ret far with value
+        begin
+          seq_addr <= `RETFV;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b1;
+          imm_size <= 1\'b1;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1100_1011: // ret far
+        begin
+          seq_addr <= `RETF0;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1100_1100: // int 3
+        begin
+          seq_addr <= `INT3;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1100_1101: // int
+        begin
+          seq_addr <= `INT;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b1;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1100_1110: // into
+        begin
+          seq_addr <= `INTO;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1100_1111: // iret
+        begin
+          seq_addr <= `IRET;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1101_00xx: // sal/shl
+        begin
+          seq_addr <= (mod==2\'b11) ? (op[1] ? (b ? `RSHCRB : `RSHCRW)
+                                            : (b ? `RSH1RB : `RSH1RW))
+                                   : (op[1] ? (b ? `RSHCMB : `RSHCMW)
+                                            : (b ? `RSH1MB : `RSH1MW));
+          need_modrm <= 1\'b1;
+          need_off <= need_off_mod;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= rm;
+          dst <= rm;
+        end
+
+      8\'b1101_0100: // aam
+        begin
+          seq_addr <= `AAM;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b1;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1101_0101: // aad
+        begin
+          seq_addr <= `AAD;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b1;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1101_0111: // xlat
+        begin
+          seq_addr <= `XLAT;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1101_1xxx: // esc
+        begin
+          seq_addr <= (mod==2\'b11) ? `ESCRW : `ESCMW;
+          need_modrm <= 1\'b1;
+          need_off   <= need_off_mod;
+          need_imm   <= 1\'b0;
+          imm_size   <= 1\'b0;
+          src        <= { 1\'b0, modrm[2:0] };
+          dst        <= 4\'b0;
+        end
+
+      8\'b1110_0000: // loopne
+        begin
+          seq_addr <= `LOOPNE;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b1;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1110_0001: // loope
+        begin
+          seq_addr <= `LOOPE;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b1;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1110_0010: // loop
+        begin
+          seq_addr <= `LOOP;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b1;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1110_0011: // jcxz
+        begin
+          seq_addr <= `JCXZ;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b1;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1110_010x: // in imm
+        begin
+          seq_addr <= b ? `INIB : `INIW;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b1;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1110_011x: // out imm
+        begin
+          seq_addr <= b ? `OUTIB : `OUTIW;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b1;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1110_1000: // call same segment
+        begin
+          seq_addr <= `CALLN;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b1;
+          imm_size <= 1\'b1;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1110_10x1: // jmp direct
+        begin
+          seq_addr <= `JMPI;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b1;
+          imm_size <= ~op[1];
+
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1110_1010: // jmp indirect different segment
+        begin
+          seq_addr <= `LJMPI;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b1;
+          need_imm <= 1\'b1;
+          imm_size <= 1\'b1;
+
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1110_110x: // in dx
+        begin
+          seq_addr <= b ? `INRB : `INRW;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1110_111x: // out dx
+        begin
+          seq_addr <= b ? `OUTRB : `OUTRW;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1111_0100: // hlt
+        begin
+          seq_addr <= `NOP; // hlt processing is in zet_core.v
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1111_0101: // cmc
+        begin
+          seq_addr <= `CMC;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1111_011x: // test, not, neg, mul, imul
+        begin
+          case (regm)
+            3\'b000: seq_addr <= (mod==2\'b11) ?
+             (b ? `TSTIRB : `TSTIRW) : (b ? `TSTIMB : `TSTIMW);
+            3\'b010: seq_addr <= (mod==2\'b11) ?
+             (b ? `NOTRB : `NOTRW) : (b ? `NOTMB : `NOTMW);
+            3\'b011: seq_addr <= (mod==2\'b11) ?
+             (b ? `NEGRB : `NEGRW) : (b ? `NEGMB : `NEGMW);
+            3\'b100: seq_addr <= (mod==2\'b11) ?
+             (b ? `MULRB : `MULRW) : (b ? `MULMB : `MULMW);
+            3\'b101: seq_addr <= (mod==2\'b11) ?
+             (b ? `IMULRB : `IMULRW) : (b ? `IMULMB : `IMULMW);
+            3\'b110: seq_addr <= (mod==2\'b11) ?
+             (b ? `DIVRB : `DIVRW) : (b ? `DIVMB : `DIVMW);
+            3\'b111: seq_addr <= (mod==2\'b11) ?
+             (b ? `IDIVRB : `IDIVRW) : (b ? `IDIVMB : `IDIVMW);
+            default: seq_addr <= `INVOP;
+          endcase
+
+          need_modrm <= 1\'b1;
+          need_off   <= need_off_mod;
+          need_imm   <= (regm == 3\'b000); // imm on test
+          imm_size   <= ~b;
+          dst        <= { 1\'b0, modrm[2:0] };
+          src        <= { 1\'b0, modrm[2:0] };
+        end
+
+      8\'b1111_1000: // clc
+        begin
+          seq_addr <= `CLC;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1111_1001: // stc
+        begin
+          seq_addr <= `STC;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1111_1010: // cli
+        begin
+          seq_addr <= `CLI;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1111_1011: // sti
+        begin
+          seq_addr <= `STI;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1111_1100: // cld
+        begin
+          seq_addr <= `CLD;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1111_1101: // std
+        begin
+          seq_addr <= `STD;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+      8\'b1111_1110: // inc
+        begin
+          case (regm)
+            3\'b000: seq_addr <= (mod==2\'b11) ? `INCRB : `INCMB;
+            3\'b001: seq_addr <= (mod==2\'b11) ? `DECRB : `DECMB;
+            default: seq_addr <= `INVOP;
+          endcase
+          need_modrm <= 1\'b1;
+          need_off <= need_off_mod;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+
+          src <= { 1\'b0, rm };
+          dst <= 4\'b0;
+        end
+
+      8\'b1111_1111:
+        begin
+          case (regm)
+            3\'b000: seq_addr <= (mod==2\'b11) ? `INCRW : `INCMW;
+            3\'b001: seq_addr <= (mod==2\'b11) ? `DECRW : `DECMW;
+            3\'b010: seq_addr <= (mod==2\'b11) ? `CALLNR : `CALLNM;
+            3\'b011: seq_addr <= `CALLFM;
+            3\'b100: seq_addr <= (mod==2\'b11) ? `JMPR : `JMPM;
+            3\'b101: seq_addr <= `LJMPM;
+            3\'b110: seq_addr <= (mod==2\'b11) ? `PUSHR : `PUSHM;
+            default: seq_addr <= `INVOP;
+          endcase
+          need_modrm <= 1\'b1;
+          need_off <= need_off_mod;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+
+          src <= { 1\'b0, rm };
+          dst <= 4\'b0;
+        end
+
+      default: // invalid opcode
+        begin
+          seq_addr <= `INVOP;
+          need_modrm <= 1\'b0;
+          need_off <= 1\'b0;
+          need_imm <= 1\'b0;
+          imm_size <= 1\'b0;
+          src <= 4\'b0;
+          dst <= 4\'b0;
+        end
+
+  endcase
+
+endmodule
+"
+"/*
+ * verilog model of 65C02 CPU.
+ *
+ * Based on original 6502 ""Arlet 6502 Core"" by Arlet Ottens 
+ * 
+ * (C) Arlet Ottens, <arlet@c-scape.nl>
+ *
+ * Feel free to use this code in any project (commercial or not), as long as you
+ * keep this message, and the copyright notice. This code is provided ""as is"", 
+ * without any warranties of any kind.
+ * 
+ * Support for 65C02 instructions and addressing modes by David Banks and Ed Spittles
+ *
+ * (C) 2016 David Banks and Ed Spittles
+ * 
+ * Feel free to use this code in any project (commercial or not), as long as you
+ * keep this message, and the copyright notice. This code is provided ""as is"", 
+ * without any warranties of any kind.
+ * 
+ */
+
+/*
+ * Note that not all 6502 interface signals are supported (yet).  The goal
+ * is to create an Acorn Atom model, and the Atom didn\'t use all signals on
+ * the main board.
+ *
+ * The data bus is implemented as separate read/write buses. Combine them
+ * on the output pads if external memory is required.
+ */
+
+/*
+ * Two things were needed to correctly implement 65C02 NOPs
+ * 1. Ensure the microcode state machine uses an appropriate addressing mode for the opcode length
+ * 2. Ensure there are no side-effects (e.g. register updates, memory stores, etc)
+ * 
+ * If IMPLEMENT_NOPS is defined, the state machine is modified accordingly.
+ */
+
+`define IMPLEMENT_NOPS
+
+/*
+ * Two things were needed to correctly implement 65C02 BCD arithmentic
+ * 1. The Z flag needs calculating over the BCD adjusted ALU output
+ * 2. The N flag needs calculating over the BCD adjusted ALU output
+ *
+ * If IMPLEMENT_CORRECT_BCD_FLAGS is defined, this additional logic is added
+ */
+
+// `define IMPLEMENT_CORRECT_BCD_FLAGS
+
+module cpu_65c02( clk, reset, AB, DI, DO, WE, IRQ, NMI, RDY );
+
+input clk;              // CPU clock 
+input reset;            // reset signal
+output reg [15:0] AB;   // address bus
+input [7:0] DI;         // data in, read bus
+output [7:0] DO;        // data out, write bus
+output WE;              // write enable
+input IRQ;              // interrupt request
+input NMI;              // non-maskable interrupt request
+input RDY;              // Ready signal. Pauses CPU when RDY=0 
+
+/*
+ * internal signals
+ */
+
+reg  [15:0] PC;         // Program Counter 
+reg  [7:0] ABL;         // Address Bus Register LSB
+reg  [7:0] ABH;         // Address Bus Register MSB
+wire [7:0] ADD;         // Adder Hold Register (registered in ALU)
+
+reg  [7:0] DIHOLD;      // Hold for Data In
+reg  DIHOLD_valid;      //
+wire [7:0] DIMUX;       //
+
+reg  [7:0] IRHOLD;      // Hold for Instruction register 
+reg  IRHOLD_valid;      // Valid instruction in IRHOLD
+
+reg  [7:0] AXYS[3:0];   // A, X, Y and S register file
+
+reg  C = 0;             // carry flag (init at zero to avoid X\'s in ALU sim)
+reg  Z = 0;             // zero flag
+reg  I = 0;             // interrupt flag
+reg  D = 0;             // decimal flag
+reg  V = 0;             // overflow flag
+reg  N = 0;             // negative flag
+wire AZ;                // ALU Zero flag
+wire AZ1;               // ALU Zero flag (BCD adjusted)
+reg  AZ2;               // ALU Second Zero flag, set using TSB/TRB semantics
+wire AV;                // ALU overflow flag
+wire AN;                // ALU negative flag
+wire AN1;               // ALU negative flag (BCD adjusted)
+wire HC;                // ALU half carry
+
+reg  [7:0] AI;          // ALU Input A
+reg  [7:0] BI;          // ALU Input B
+wire [7:0] DI;          // Data In
+wire [7:0] IR;          // Instruction register
+reg  [7:0] DO;          // Data Out 
+wire [7:0] AO;          // ALU output after BCD adjustment
+reg  WE;                // Write Enable
+reg  CI;                // Carry In
+wire CO;                // Carry Out 
+wire [7:0] PCH = PC[15:8];
+wire [7:0] PCL = PC[7:0];
+
+reg NMI_edge = 0;       // captured NMI edge
+
+reg [1:0] regsel;                       // Select A, X, Y or S register
+wire [7:0] regfile = AXYS[regsel];      // Selected register output
+
+parameter 
+        SEL_A    = 2\'d0,
+        SEL_S    = 2\'d1,
+        SEL_X    = 2\'d2, 
+        SEL_Y    = 2\'d3;
+
+/*
+ * define some signals for watching in simulator output
+ */
+
+
+`ifdef SIM
+wire [7:0]   A = AXYS[SEL_A];           // Accumulator
+wire [7:0]   X = AXYS[SEL_X];           // X register
+wire [7:0]   Y = AXYS[SEL_Y];           // Y register 
+wire [7:0]   S = AXYS[SEL_S];           // Stack pointer 
+`endif
+
+wire [7:0] P = { N, V, 2\'b11, D, I, Z, C };
+
+/*
+ * instruction decoder/sequencer
+ */
+
+reg [5:0] state;
+
+/*
+ * control signals
+ */
+
+reg PC_inc;             // Increment PC
+reg [15:0] PC_temp;     // intermediate value of PC 
+
+reg [1:0] src_reg;      // source register index
+reg [1:0] dst_reg;      // destination register index
+
+reg index_y;            // if set, then Y is index reg rather than X 
+reg load_reg;           // loading a register (A, X, Y, S) in this instruction
+reg inc;                // increment
+reg write_back;         // set if memory is read/modified/written 
+reg load_only;          // LDA/LDX/LDY instruction
+reg store;              // doing store (STA/STX/STY)
+reg adc_sbc;            // doing ADC/SBC
+reg compare;            // doing CMP/CPY/CPX
+reg shift;              // doing shift/rotate instruction
+reg rotate;             // doing rotate (no shift)
+reg backwards;          // backwards branch
+reg cond_true;          // branch condition is true
+reg [3:0] cond_code;    // condition code bits from instruction
+reg shift_right;        // Instruction ALU shift/rotate right 
+reg alu_shift_right;    // Current cycle shift right enable
+reg [3:0] op;           // Main ALU operation for instruction
+reg [3:0] alu_op;       // Current cycle ALU operation 
+reg adc_bcd;            // ALU should do BCD style carry 
+reg adj_bcd;            // results should be BCD adjusted
+
+/* 
+ * some flip flops to remember we\'re doing special instructions. These
+ * get loaded at the DECODE state, and used later
+ */
+reg store_zero;         // doing STZ instruction
+reg trb_ins;            // doing TRB instruction
+reg txb_ins;            // doing TSB/TRB instruction
+reg bit_ins;            // doing BIT instruction
+reg bit_ins_nv;         // doing BIT instruction that will update the n and v flags (i.e. not BIT imm)
+reg plp;                // doing PLP instruction
+reg php;                // doing PHP instruction 
+reg clc;                // clear carry
+reg sec;                // set carry
+reg cld;                // clear decimal
+reg sed;                // set decimal
+reg cli;                // clear interrupt
+reg sei;                // set interrupt
+reg clv;                // clear overflow 
+reg brk;                // doing BRK
+
+reg res;                // in reset
+
+/*
+ * ALU operations
+ */
+
+parameter
+        OP_OR  = 4\'b1100,
+        OP_AND = 4\'b1101,
+        OP_EOR = 4\'b1110,
+        OP_ADD = 4\'b0011,
+        OP_SUB = 4\'b0111,
+        OP_ROL = 4\'b1011,
+        OP_A   = 4\'b1111;
+
+/*
+ * Microcode state machine. Basically, every addressing mode has its own
+ * path through the state machine. Additional information, such as the
+ * operation, source and destination registers are decoded in parallel, and
+ * kept in separate flops. 
+ */
+
+parameter 
+    ABS0   = 6\'d0,  // ABS     - fetch LSB      
+    ABS1   = 6\'d1,  // ABS     - fetch MSB
+    ABSX0  = 6\'d2,  // ABS, X  - fetch LSB and send to ALU (+X)
+    ABSX1  = 6\'d3,  // ABS, X  - fetch MSB and send to ALU (+Carry)
+    ABSX2  = 6\'d4,  // ABS, X  - Wait for ALU (only if needed)
+    BRA0   = 6\'d5,  // Branch  - fetch offset and send to ALU (+PC[7:0])
+    BRA1   = 6\'d6,  // Branch  - fetch opcode, and send PC[15:8] to ALU 
+    BRA2   = 6\'d7,  // Branch  - fetch opcode (if page boundary crossed)
+    BRK0   = 6\'d8,  // BRK/IRQ - push PCH, send S to ALU (-1)
+    BRK1   = 6\'d9,  // BRK/IRQ - push PCL, send S to ALU (-1)
+    BRK2   = 6\'d10, // BRK/IRQ - push P, send S to ALU (-1)
+    BRK3   = 6\'d11, // BRK/IRQ - write S, and fetch @ fffe
+    DECODE = 6\'d12, // IR is valid, decode instruction, and write prev reg
+    FETCH  = 6\'d13, // fetch next opcode, and perform prev ALU op
+    INDX0  = 6\'d14, // (ZP,X)  - fetch ZP address, and send to ALU (+X)
+    INDX1  = 6\'d15, // (ZP,X)  - fetch LSB at ZP+X, calculate ZP+X+1
+    INDX2  = 6\'d16, // (ZP,X)  - fetch MSB at ZP+X+1
+    INDX3  = 6\'d17, // (ZP,X)  - fetch data 
+    INDY0  = 6\'d18, // (ZP),Y  - fetch ZP address, and send ZP to ALU (+1)
+    INDY1  = 6\'d19, // (ZP),Y  - fetch at ZP+1, and send LSB to ALU (+Y) 
+    INDY2  = 6\'d20, // (ZP),Y  - fetch data, and send MSB to ALU (+Carry)
+    INDY3  = 6\'d21, // (ZP),Y) - fetch data (if page boundary crossed)
+    JMP0   = 6\'d22, // JMP     - fetch PCL and hold
+    JMP1   = 6\'d23, // JMP     - fetch PCH
+    JMPI0  = 6\'d24, // JMP IND - fetch LSB and send to ALU for delay (+0)
+    JMPI1  = 6\'d25, // JMP IND - fetch MSB, proceed with JMP0 state
+    JSR0   = 6\'d26, // JSR     - push PCH, save LSB, send S to ALU (-1)
+    JSR1   = 6\'d27, // JSR     - push PCL, send S to ALU (-1)
+    JSR2   = 6\'d28, // JSR     - write S
+    JSR3   = 6\'d29, // JSR     - fetch MSB
+    PULL0  = 6\'d30, // PLP/PLA/PLX/PLY - save next op in IRHOLD, send S to ALU (+1)
+    PULL1  = 6\'d31, // PLP/PLA/PLX/PLY - fetch data from stack, write S
+    PULL2  = 6\'d32, // PLP/PLA/PLX/PLY - prefetch op, but don\'t increment PC
+    PUSH0  = 6\'d33, // PHP/PHA/PHX/PHY - send A to ALU (+0)
+    PUSH1  = 6\'d34, // PHP/PHA/PHX/PHY - write A/P, send S to ALU (-1)
+    READ   = 6\'d35, // Read memory for read/modify/write (INC, DEC, shift)
+    REG    = 6\'d36, // Read register for reg-reg transfers
+    RTI0   = 6\'d37, // RTI     - send S to ALU (+1)
+    RTI1   = 6\'d38, // RTI     - read P from stack 
+    RTI2   = 6\'d39, // RTI     - read PCL from stack
+    RTI3   = 6\'d40, // RTI     - read PCH from stack
+    RTI4   = 6\'d41, // RTI     - read PCH from stack
+    RTS0   = 6\'d42, // RTS     - send S to ALU (+1)
+    RTS1   = 6\'d43, // RTS     - read PCL from stack 
+    RTS2   = 6\'d44, // RTS     - write PCL to ALU, read PCH 
+    RTS3   = 6\'d45, // RTS     - load PC and increment
+    WRITE  = 6\'d46, // Write memory for read/modify/write 
+    ZP0    = 6\'d47, // Z-page  - fetch ZP address
+    ZPX0   = 6\'d48, // ZP, X   - fetch ZP, and send to ALU (+X)
+    ZPX1   = 6\'d49, // ZP, X   - load from memory
+    IND0   = 6\'d50, // (ZP)    - fetch ZP address, and send to ALU (+0)
+    JMPIX0 = 6\'d51, // JMP (,X)- fetch LSB and send to ALU (+X)
+    JMPIX1 = 6\'d52, // JMP (,X)- fetch MSB and send to ALU (+Carry)
+    JMPIX2 = 6\'d53; // JMP (,X)- Wait for ALU (only if needed)
+
+`ifdef SIM
+
+/*
+ * easy to read names in simulator output
+ */
+reg [8*6-1:0] statename;
+
+always @*
+    case( state )
+            DECODE: statename = ""DECODE"";
+            REG:    statename = ""REG"";
+            ZP0:    statename = ""ZP0"";
+            ZPX0:   statename = ""ZPX0"";
+            ZPX1:   statename = ""ZPX1"";
+            ABS0:   statename = ""ABS0"";
+            ABS1:   statename = ""ABS1"";
+            ABSX0:  statename = ""ABSX0"";
+            ABSX1:  statename = ""ABSX1"";
+            ABSX2:  statename = ""ABSX2"";
+            IND0:   statename = ""IND0"";
+            INDX0:  statename = ""INDX0"";
+            INDX1:  statename = ""INDX1"";
+            INDX2:  statename = ""INDX2"";
+            INDX3:  statename = ""INDX3"";
+            INDY0:  statename = ""INDY0"";
+            INDY1:  statename = ""INDY1"";
+            INDY2:  statename = ""INDY2"";
+            INDY3:  statename = ""INDY3"";
+             READ:  statename = ""READ"";
+            WRITE:  statename = ""WRITE"";
+            FETCH:  statename = ""FETCH"";
+            PUSH0:  statename = ""PUSH0"";
+            PUSH1:  statename = ""PUSH1"";
+            PULL0:  statename = ""PULL0"";
+            PULL1:  statename = ""PULL1"";
+            PULL2:  statename = ""PULL2"";
+            JSR0:   statename = ""JSR0"";
+            JSR1:   statename = ""JSR1"";
+            JSR2:   statename = ""JSR2"";
+            JSR3:   statename = ""JSR3"";
+            RTI0:   statename = ""RTI0"";
+            RTI1:   statename = ""RTI1"";
+            RTI2:   statename = ""RTI2"";
+            RTI3:   statename = ""RTI3"";
+            RTI4:   statename = ""RTI4"";
+            RTS0:   statename = ""RTS0"";
+            RTS1:   statename = ""RTS1"";
+            RTS2:   statename = ""RTS2"";
+            RTS3:   statename = ""RTS3"";
+            BRK0:   statename = ""BRK0"";
+            BRK1:   statename = ""BRK1"";
+            BRK2:   statename = ""BRK2"";
+            BRK3:   statename = ""BRK3"";
+            BRA0:   statename = ""BRA0"";
+            BRA1:   statename = ""BRA1"";
+            BRA2:   statename = ""BRA2"";
+            JMP0:   statename = ""JMP0"";
+            JMP1:   statename = ""JMP1"";
+            JMPI0:  statename = ""JMPI0"";
+            JMPI1:  statename = ""JMPI1"";
+            JMPIX0: statename = ""JMPIX0"";
+            JMPIX1: statename = ""JMPIX1"";
+            JMPIX2: statename = ""JMPIX2"";
+          
+    endcase
+
+//always @( PC )
+//      $display( ""%t, PC:%04x IR:%02x A:%02x X:%02x Y:%02x S:%02x C:%d Z:%d V:%d N:%d P:%02x"", $time, PC, IR, A, X, Y, S, C, Z, V, N, P );
+
+`endif
+
+
+
+/*
+ * Program Counter Increment/Load. First calculate the base value in
+ * PC_temp.
+ */
+always @*
+    case( state )
+        DECODE:         if( (~I & IRQ) | NMI_edge )
+                            PC_temp = { ABH, ABL };
+                        else
+                            PC_temp = PC;
+
+
+        JMP1,
+        JMPI1,
+        JMPIX1,
+        JSR3,
+        RTS3,           
+        RTI4:           PC_temp = { DIMUX, ADD };
+                        
+        BRA1:           PC_temp = { ABH, ADD };
+
+        JMPIX2,
+        BRA2:           PC_temp = { ADD, PCL };
+
+        BRK2:           PC_temp =      res ? 16\'hfffc : 
+                                  NMI_edge ? 16\'hfffa : 16\'hfffe;
+
+        default:        PC_temp = PC;
+    endcase
+
+/*
+ * Determine wether we need PC_temp, or PC_temp + 1
+ */
+always @*
+    case( state )
+        DECODE:         if( (~I & IRQ) | NMI_edge )
+                            PC_inc = 0;
+                        else
+                            PC_inc = 1;
+
+        ABS0,
+        JMPIX0,
+        JMPIX2,
+        ABSX0,
+        FETCH,
+        BRA0,
+        BRA2,
+        BRK3,
+        JMPI1,
+        JMP1,
+        RTI4,
+        RTS3:           PC_inc = 1;
+
+        JMPIX1:         PC_inc = ~CO;       // Don\'t increment PC if we are going to go through JMPIX2
+
+        BRA1:           PC_inc = CO ^~ backwards;
+
+        default:        PC_inc = 0;
+    endcase
+
+/* 
+ * Set new PC
+ */
+always @(posedge clk) 
+    if( RDY )
+        PC <= PC_temp + PC_inc;
+
+/*
+ * Address Generator 
+ */
+
+parameter
+        ZEROPAGE  = 8\'h00,
+        STACKPAGE = 8\'h01;
+
+always @*
+    case( state )
+        JMPIX1,
+        ABSX1,
+        INDX3,
+        INDY2,
+        JMP1,
+        JMPI1,
+        RTI4,
+        ABS1:           AB = { DIMUX, ADD };
+
+        BRA2,
+        INDY3,
+        JMPIX2,
+        ABSX2:          AB = { ADD, ABL };
+
+        BRA1:           AB = { ABH, ADD };
+
+        JSR0,
+        PUSH1,
+        RTS0,
+        RTI0,
+        BRK0:           AB = { STACKPAGE, regfile };
+
+        BRK1,
+        JSR1,
+        PULL1,
+        RTS1,
+        RTS2,
+        RTI1,
+        RTI2,
+        RTI3,
+        BRK2:           AB = { STACKPAGE, ADD };
+        
+        INDY1,
+        INDX1,
+        ZPX1,
+        INDX2:          AB = { ZEROPAGE, ADD };
+
+        ZP0,
+        INDY0:          AB = { ZEROPAGE, DIMUX };
+
+        REG,
+        READ,
+        WRITE:          AB = { ABH, ABL };
+
+        default:        AB = PC;
+    endcase
+
+/*
+ * ABH/ABL pair is used for registering previous address bus state.
+ * This can be used to keep the current address, freeing up the original
+ * source of the address, such as the ALU or DI.
+ */
+always @(posedge clk)
+    if( state != PUSH0 && state != PUSH1 && RDY && 
+        state != PULL0 && state != PULL1 && state != PULL2 )
+    begin
+        ABL <= AB[7:0];
+        ABH <= AB[15:8];
+    end
+
+/*
+ * Data Out MUX 
+ */
+always @*
+    case( state )
+        WRITE:   DO = ADD;
+
+        JSR0,
+        BRK0:    DO = PCH;
+
+        JSR1,
+        BRK1:    DO = PCL;
+
+        PUSH1:   DO = php ? P : ADD;
+
+        BRK2:    DO = (IRQ | NMI_edge) ? (P & 8\'b1110_1111) : P;
+
+        default: DO = store_zero ? 0 : regfile;
+    endcase
+
+/*
+ * Write Enable Generator
+ */
+
+always @*
+    case( state )
+        BRK0,   // writing to stack or memory
+        BRK1,
+        BRK2,
+        JSR0,
+        JSR1,
+        PUSH1,
+        WRITE:   WE = 1;
+
+        INDX3,  // only if doing a STA, STX or STY
+        INDY3,
+        ABSX2,
+        ABS1,
+        ZPX1,
+        ZP0:     WE = store;
+
+        default: WE = 0;
+    endcase
+
+/*
+ * register file, contains A, X, Y and S (stack pointer) registers. At each
+ * cycle only 1 of those registers needs to be accessed, so they combined
+ * in a small memory, saving resources.
+ */
+
+reg write_register;             // set when register file is written
+
+always @*
+    case( state )
+        DECODE: write_register = load_reg & ~plp;
+
+        PULL1, 
+         RTS2, 
+         RTI3,
+         BRK3,
+         JSR0,
+         JSR2 : write_register = 1;
+
+       default: write_register = 0;
+    endcase
+
+/*
+ * BCD adjust logic
+ */
+
+always @(posedge clk)
+    adj_bcd <= adc_sbc & D;     // \'1\' when doing a BCD instruction
+
+reg [3:0] ADJL;
+reg [3:0] ADJH;
+
+// adjustment term to be added to ADD[3:0] based on the following
+// adj_bcd: \'1\' if doing ADC/SBC with D=1
+// adc_bcd: \'1\' if doing ADC with D=1
+// HC     : half carry bit from ALU
+always @* begin
+    casex( {adj_bcd, adc_bcd, HC} )
+         3\'b0xx: ADJL = 4\'d0;   // no BCD instruction
+         3\'b100: ADJL = 4\'d10;  // SBC, and digital borrow
+         3\'b101: ADJL = 4\'d0;   // SBC, but no borrow
+         3\'b110: ADJL = 4\'d0;   // ADC, but no carry
+         3\'b111: ADJL = 4\'d6;   // ADC, and decimal/digital carry
+    endcase
+end
+
+// adjustment term to be added to ADD[7:4] based on the following
+// adj_bcd: \'1\' if doing ADC/SBC with D=1
+// adc_bcd: \'1\' if doing ADC with D=1
+// CO     : carry out bit from ALU
+always @* begin
+    casex( {adj_bcd, adc_bcd, CO} )
+         3\'b0xx: ADJH = 4\'d0;   // no BCD instruction
+         3\'b100: ADJH = 4\'d10;  // SBC, and digital borrow
+         3\'b101: ADJH = 4\'d0;   // SBC, but no borrow
+         3\'b110: ADJH = 4\'d0;   // ADC, but no carry
+         3\'b111: ADJH = 4\'d6;   // ADC, and decimal/digital carry
+    endcase
+end
+
+assign AO = { ADD[7:4] + ADJH, ADD[3:0] + ADJL };
+
+`ifdef IMPLEMENT_CORRECT_BCD_FLAGS
+
+assign AN1 = AO[7];
+assign AZ1 = ~|AO;
+
+`else
+
+assign AN1 = AN;
+assign AZ1 = AZ;
+
+`endif
+   
+/*
+ * write to a register. Usually this is the (BCD corrected) output of the
+ * ALU, but in case of the JSR0 we use the S register to temporarily store
+ * the PCL. This is possible, because the S register itself is stored in
+ * the ALU during those cycles.
+ */
+always @(posedge clk)
+    if( write_register & RDY )
+        AXYS[regsel] <= (state == JSR0) ? DIMUX : AO;
+
+/*
+ * register select logic. This determines which of the A, X, Y or
+ * S registers will be accessed. 
+ */
+
+always @*  
+    case( state )
+        INDY1,
+        INDX0,
+        ZPX0,
+        JMPIX0,
+        ABSX0  : regsel = index_y ? SEL_Y : SEL_X;
+
+
+        DECODE : regsel = dst_reg; 
+
+        BRK0,
+        BRK3,
+        JSR0,
+        JSR2,
+        PULL0,
+        PULL1,
+        PUSH1,
+        RTI0,
+        RTI3,
+        RTS0,
+        RTS2   : regsel = SEL_S;
+        
+        default: regsel = src_reg; 
+    endcase
+
+/*
+ * ALU
+ */
+
+ALU ALU( .clk(clk),
+         .op(alu_op),
+         .right(alu_shift_right),
+         .AI(AI),
+         .BI(BI),
+         .CI(CI),
+         .BCD(adc_bcd & (state == FETCH)),
+         .CO(CO),
+         .OUT(ADD),
+         .V(AV),
+         .Z(AZ),
+         .N(AN),
+         .HC(HC),
+         .RDY(RDY) );
+
+/*
+ * Select current ALU operation
+ */
+
+always @*
+    case( state )
+        READ:   alu_op = op;
+
+        BRA1:   alu_op = backwards ? OP_SUB : OP_ADD; 
+
+        FETCH,
+        REG :   alu_op = op; 
+
+        DECODE,
+        ABS1:   alu_op = 1\'bx;
+
+        PUSH1,
+        BRK0,
+        BRK1,
+        BRK2,
+        JSR0,
+        JSR1:   alu_op = OP_SUB;
+
+     default:   alu_op = OP_ADD;
+    endcase
+
+/*
+ * Determine shift right signal to ALU
+ */
+
+always @*
+    if( state == FETCH || state == REG || state == READ )
+        alu_shift_right = shift_right;
+    else
+        alu_shift_right = 0;
+
+/*
+ * Sign extend branch offset.  
+ */
+
+always @(posedge clk)
+    if( RDY )
+        backwards <= DIMUX[7];
+
+/* 
+ * ALU A Input MUX 
+ */
+
+always @*
+    case( state )
+        JSR1,
+        RTS1,
+        RTI1,
+        RTI2,
+        BRK1,
+        BRK2,
+        INDX1:  AI = ADD;
+
+        REG,
+        ZPX0,
+        INDX0,
+        JMPIX0,
+        ABSX0,
+        RTI0,
+        RTS0,
+        JSR0,
+        JSR2,
+        BRK0,
+        PULL0,
+        INDY1,
+        PUSH0,
+        PUSH1:  AI = regfile;
+
+        BRA0,
+        READ:   AI = DIMUX;
+
+        BRA1:   AI = ABH;       // don\'t use PCH in case we\'re 
+
+        FETCH:  AI = load_only ? 0 : regfile;
+
+        DECODE,
+        ABS1:   AI = 8\'hxx;     // don\'t care
+
+        default:  AI = 0;
+    endcase
+
+
+/*
+ * ALU B Input mux
+ */
+
+always @*
+    case( state )
+         BRA1,
+         RTS1,
+         RTI0,
+         RTI1,
+         RTI2,
+         INDX1,
+         REG,
+         JSR0,
+         JSR1,
+         JSR2,
+         BRK0,
+         BRK1,
+         BRK2,
+         PUSH0, 
+         PUSH1,
+         PULL0,
+         RTS0:  BI = 8\'h00;
+
+         READ:  BI = txb_ins ? (trb_ins ? ~regfile : regfile) : 8\'h00;
+
+         BRA0:  BI = PCL;
+
+         DECODE,
+         ABS1:  BI = 8\'hxx;
+
+         default:       BI = DIMUX;
+    endcase
+
+/*
+ * ALU CI (carry in) mux
+ */
+
+always @*
+    case( state )
+        INDY2,
+        BRA1,
+        JMPIX1,
+        ABSX1:  CI = CO;
+
+        DECODE,
+        ABS1:   CI = 1\'bx;
+
+        READ,
+        REG:    CI = rotate ? C :
+                     shift ? 0 : inc;
+
+        FETCH:  CI = rotate  ? C : 
+                     compare ? 1 : 
+                     (shift | load_only) ? 0 : C;
+
+        PULL0,
+        RTI0,
+        RTI1,
+        RTI2,
+        RTS0,
+        RTS1,
+        INDY0,
+        INDX1:  CI = 1; 
+
+        default:        CI = 0;
+    endcase
+
+/*
+ * Processor Status Register update
+ *
+ */
+
+/*
+ * Update C flag when doing ADC/SBC, shift/rotate, compare
+ */
+always @(posedge clk )
+    if( shift && state == WRITE ) 
+        C <= CO;
+    else if( state == RTI2 )
+        C <= DIMUX[0];
+    else if( ~write_back && state == DECODE ) begin
+        if( adc_sbc | shift | compare )
+            C <= CO;
+        else if( plp )
+            C <= ADD[0];
+        else begin
+            if( sec ) C <= 1;
+            if( clc ) C <= 0;
+        end
+    end
+
+/*
+ * Special Z flag got TRB/TSB
+ */ 
+always @(posedge clk) 
+    AZ2 <= ~|(AI & regfile);
+
+/*
+ * Update Z, N flags when writing A, X, Y, Memory, or when doing compare
+ */
+
+always @(posedge clk) 
+    if( state == WRITE)
+        Z <= txb_ins ? AZ2 : AZ1;
+    else if( state == RTI2 )
+        Z <= DIMUX[1];
+    else if( state == DECODE ) begin
+        if( plp )
+            Z <= ADD[1];
+        else if( (load_reg & (regsel != SEL_S)) | compare | bit_ins )
+            Z <= AZ1;
+    end
+
+always @(posedge clk)
+    if( state == WRITE && ~txb_ins)
+        N <= AN1;
+    else if( state == RTI2 )
+        N <= DIMUX[7];
+    else if( state == DECODE ) begin
+        if( plp )
+            N <= ADD[7];
+        else if( (load_reg & (regsel != SEL_S)) | compare )
+            N <= AN1;
+    end else if( state == FETCH && bit_ins_nv )
+        N <= DIMUX[7];
+
+/*
+ * Update I flag
+ */
+
+always @(posedge clk)
+    if( state == BRK3 )
+        I <= 1;
+    else if( state == RTI2 )
+        I <= DIMUX[2];
+    else if( state == REG ) begin
+        if( sei ) I <= 1;
+        if( cli ) I <= 0;
+    end else if( state == DECODE )
+        if( plp ) I <= ADD[2];
+
+/*
+ * Update D flag
+ */
+always @(posedge clk ) 
+    if( state == RTI2 )
+        D <= DIMUX[3];
+    else if( state == DECODE ) begin
+        if( sed ) D <= 1;
+        if( cld ) D <= 0;
+        if( plp ) D <= ADD[3];
+    end
+
+/*
+ * Update V flag
+ */
+always @(posedge clk )
+    if( state == RTI2 ) 
+        V <= DIMUX[6];
+    else if( state == DECODE ) begin
+        if( adc_sbc ) V <= AV;
+        if( clv )     V <= 0;
+        if( plp )     V <= ADD[6];
+    end else if( state == FETCH && bit_ins_nv )
+        V <= DIMUX[6];
+
+/*
+ * Instruction decoder
+ */
+
+/*
+ * IR register/mux. Hold previous DI value in IRHOLD in PULL0 and PUSH0
+ * states. In these states, the IR has been prefetched, and there is no
+ * time to read the IR again before the next decode.
+ */
+
+//reg RDY1 = 1;
+
+//always @(posedge clk )
+//    RDY1 <= RDY;
+
+//always @(posedge clk )
+//    if( ~RDY && RDY1 )
+//        DIHOLD <= DI;
+
+always @(posedge clk )
+    if( reset )
+        IRHOLD_valid <= 0;
+    else if( RDY ) begin
+        if( state == PULL0 || state == PUSH0 ) begin
+            IRHOLD <= DIMUX;
+            IRHOLD_valid <= 1;
+        end else if( state == DECODE )
+            IRHOLD_valid <= 0;
+    end
+
+assign IR = (IRQ & ~I) | NMI_edge ? 8\'h00 :
+                     IRHOLD_valid ? IRHOLD : DIMUX;
+
+//assign DIMUX = ~RDY1 ? DIHOLD : DI;
+   
+assign DIMUX = DI;   
+
+/*
+ * Microcode state machine
+ */
+always @(posedge clk or posedge reset)
+    if( reset )
+        state <= BRK0;
+    else if( RDY ) case( state )
+        DECODE  : 
+            casex ( IR )
+                // TODO Review for simplifications as in verilog the first matching case has priority
+                8\'b0000_0000:   state <= BRK0;
+                8\'b0010_0000:   state <= JSR0;
+                8\'b0010_1100:   state <= ABS0;  // BIT abs
+                8\'b1001_1100:   state <= ABS0;  // STZ abs
+                8\'b000x_1100:   state <= ABS0;  // TSB/TRB
+                8\'b0100_0000:   state <= RTI0;  // 
+                8\'b0100_1100:   state <= JMP0;
+                8\'b0110_0000:   state <= RTS0;
+                8\'b0110_1100:   state <= JMPI0;
+                8\'b0111_1100:   state <= JMPIX0;
+`ifdef IMPLEMENT_NOPS             
+                8\'bxxxx_xx11:   state <= REG;   // (NOP1: 3/7/B/F column)
+                8\'bxxx0_0010:   state <= FETCH; // (NOP2: 2 column, 4 column handled correctly below)
+                8\'bx1x1_1100:   state <= ABS0;  // (NOP3: C column)
+`endif
+                8\'b0x00_1000:   state <= PUSH0;
+                8\'b0x10_1000:   state <= PULL0;
+                8\'b0xx1_1000:   state <= REG;   // CLC, SEC, CLI, SEI 
+                8\'b11x0_00x0:   state <= FETCH; // IMM
+                8\'b1x10_00x0:   state <= FETCH; // IMM
+                8\'b1xx0_1100:   state <= ABS0;  // X/Y abs
+                8\'b1xxx_1000:   state <= REG;   // DEY, TYA, ... 
+                8\'bxxx0_0001:   state <= INDX0;
+                8\'bxxx1_0010:   state <= IND0;  // (ZP) odd 2 column
+                8\'b000x_0100:   state <= ZP0;   // TSB/TRB
+                8\'bxxx0_01xx:   state <= ZP0;
+                8\'bxxx0_1001:   state <= FETCH; // IMM
+                8\'bxxx0_1101:   state <= ABS0;  // even D column
+                8\'bxxx0_1110:   state <= ABS0;  // even E column
+                8\'bxxx1_0000:   state <= BRA0;  // odd 0 column (Branches)
+                8\'b1000_0000:   state <= BRA0;  // BRA
+                8\'bxxx1_0001:   state <= INDY0; // odd 1 column
+                8\'bxxx1_01xx:   state <= ZPX0;  // odd 4,5,6,7 columns
+                8\'bxxx1_1001:   state <= ABSX0; // odd 9 column
+                8\'bx011_1100:   state <= ABSX0; // C column BIT (3C), LDY (BC)
+                8\'bxxx1_11x1:   state <= ABSX0; // odd D, F columns
+                8\'bxxx1_111x:   state <= ABSX0; // odd E, F columns
+                8\'bx101_1010:   state <= PUSH0; // PHX/PHY
+                8\'bx111_1010:   state <= PULL0; // PLX/PLY
+                8\'bx0xx_1010:   state <= REG;   // <shift> A, TXA, ...  NOP
+                8\'bxxx0_1010:   state <= REG;   // <shift> A, TXA, ...  NOP
+            endcase
+
+        ZP0     : state <= write_back ? READ : FETCH;
+
+        ZPX0    : state <= ZPX1;
+        ZPX1    : state <= write_back ? READ : FETCH;
+
+        ABS0    : state <= ABS1;
+        ABS1    : state <= write_back ? READ : FETCH;
+
+        ABSX0   : state <= ABSX1;
+        ABSX1   : state <= (CO | store | write_back) ? ABSX2 : FETCH;
+        ABSX2   : state <= write_back ? READ : FETCH;
+
+        JMPIX0  : state <= JMPIX1;
+        JMPIX1  : state <= CO ? JMPIX2 : JMP0;
+        JMPIX2  : state <= JMP0;
+
+        IND0    : state <= INDX1;
+
+        INDX0   : state <= INDX1;
+        INDX1   : state <= INDX2;
+        INDX2   : state <= INDX3;
+        INDX3   : state <= FETCH;
+
+        INDY0   : state <= INDY1;
+        INDY1   : state <= INDY2;
+        INDY2   : state <= (CO | store) ? INDY3 : FETCH;
+        INDY3   : state <= FETCH;
+
+        READ    : state <= WRITE;
+        WRITE   : state <= FETCH;
+        FETCH   : state <= DECODE;
+
+        REG     : state <= DECODE;
+        
+        PUSH0   : state <= PUSH1;
+        PUSH1   : state <= DECODE;
+
+        PULL0   : state <= PULL1;
+        PULL1   : state <= PULL2; 
+        PULL2   : state <= DECODE;
+
+        JSR0    : state <= JSR1;
+        JSR1    : state <= JSR2;
+        JSR2    : state <= JSR3;
+        JSR3    : state <= FETCH; 
+
+        RTI0    : state <= RTI1;
+        RTI1    : state <= RTI2;
+        RTI2    : state <= RTI3;
+        RTI3    : state <= RTI4;
+        RTI4    : state <= DECODE;
+
+        RTS0    : state <= RTS1;
+        RTS1    : state <= RTS2;
+        RTS2    : state <= RTS3;
+        RTS3    : state <= FETCH;
+
+        BRA0    : state <= cond_true ? BRA1 : DECODE;
+        BRA1    : state <= (CO ^ backwards) ? BRA2 : DECODE;
+        BRA2    : state <= DECODE;
+
+        JMP0    : state <= JMP1;
+        JMP1    : state <= DECODE; 
+
+        JMPI0   : state <= JMPI1;
+        JMPI1   : state <= JMP0;
+
+        BRK0    : state <= BRK1;
+        BRK1    : state <= BRK2;
+        BRK2    : state <= BRK3;
+        BRK3    : state <= JMP0;
+
+    endcase
+
+/*
+ * Additional control signals
+ */
+
+always @(posedge clk)
+     if( reset )
+         res <= 1;
+     else if( state == DECODE )
+         res <= 0;
+
+always @(posedge clk)
+     if( state == DECODE && RDY )
+        casex( IR )             // DMB: Checked for 65C02 NOP collisions
+                8\'b0xx1_0010,   // ORA, AND, EOR, ADC (zp)
+                8\'b1x11_0010,   // LDA, SBC (zp)
+                8\'b0xxx_1010,   // ASLA, INCA, ROLA, DECA, LSRA, PHY, RORA, PLY
+                8\'b'b""0xxx_xx01,   // ORA, AND, EOR, ADC
+                8'b100x_10x0,   // DEY, TYA, TXA, TXS
+                8'b1010_xxx0,   // LDA/LDX/LDY 
+                8'b1011_1010,   // TSX
+                8'b1011_x1x0,   // LDX/LDY
+                8'b1100_1010,   // DEX
+                8'b11x1_1010,   // PHX, PLX
+                8'b1x1x_xx01,   // LDA, SBC
+                8'bxxx0_1000:   // PHP, PLP, PHA, PLA, DEY, TAY, INY, INX
+                                load_reg <= 1;
+
+                default:        load_reg <= 0;
+        endcase
+
+always @(posedge clk)
+     if( state == DECODE && RDY )
+        casex( IR )
+                8'b1110_1000,   // INX
+                8'b1100_1010,   // DEX
+                8'b1111_1010,   // PLX
+                8'b1010_0010,   // LDX imm
+                8'b101x_x110,   // LDX
+                8'b101x_1x10:   // LDX, TAX, TSX
+                                dst_reg <= SEL_X;
+
+                8'b0x00_1000,   // PHP, PHA
+                8'bx101_1010,   // PHX, PHY
+                8'b1001_1010:   // TXS
+                                dst_reg <= SEL_S;
+
+                8'b1x00_1000,   // DEY, DEX
+                8'b0111_1010,   // PLY
+                8'b101x_x100,   // LDY
+                8'b1010_x000:   // LDY #imm, TAY
+                                dst_reg <= SEL_Y;
+
+                default:        dst_reg <= SEL_A;
+        endcase
+
+always @(posedge clk)
+     if( state == DECODE && RDY )
+        casex( IR )
+                8'b1011_1010:   // TSX 
+                                src_reg <= SEL_S; 
+
+                8'b100x_x110,   // STX
+                8'b100x_1x10,   // TXA, TXS
+                8'b1110_xx00,   // INX, CPX
+                8'b1101_1010,   // PHX
+                8'b1100_1010:   // DEX
+                                src_reg <= SEL_X; 
+
+                8'b100x_x100,   // STY
+                8'b1001_1000,   // TYA
+                8'b1100_xx00,   // CPY
+                8'b0101_1010,   // PHY
+                8'b1x00_1000:   // DEY, INY
+                                src_reg <= SEL_Y;
+
+                default:        src_reg <= SEL_A;
+        endcase
+
+always @(posedge clk) 
+     if( state == DECODE && RDY )
+        casex( IR )
+                8'bxxx1_0001,   // INDY
+                8'b10x1_0110,   // LDX zp,Y / STX zp,Y
+                8'b1011_1110,   // LDX abs,Y
+                8'bxxxx_1001:   // abs, Y
+                                index_y <= 1;
+
+                default:        index_y <= 0;
+        endcase
+
+
+always @(posedge clk)
+     if( state == DECODE && RDY )
+        casex( IR )             // DMB: Checked for 65C02 NOP collisions
+                8'b1001_0010,   // STA (zp)
+                8'b100x_x1x0,   // STX, STY, STZ abs, STZ abs,x
+                8'b011x_0100,   // STZ zp, STZ zp,x
+                8'b100x_xx01:   // STA
+                                store <= 1;
+
+                default:        store <= 0;
+
+        endcase
+
+always @(posedge clk )
+     if( state == DECODE && RDY )
+        casex( IR )             // DMB: Checked for 65C02 NOP collisions
+                8'b0xxx_x110,   // ASL, ROL, LSR, ROR
+                8'b000x_x100,   // TSB/TRB
+                8'b11xx_x110:   // DEC/INC 
+                                write_back <= 1;
+
+                default:        write_back <= 0;
+        endcase
+
+
+always @(posedge clk )
+     if( state == DECODE && RDY )
+        casex( IR )
+                8'b101x_xxxx:   // LDA, LDX, LDY
+                                load_only <= 1;
+                default:        load_only <= 0;
+        endcase
+
+always @(posedge clk )
+     if( state == DECODE && RDY )
+        casex( IR )
+                8'b0001_1010,   // INCA
+                8'b111x_x110,   // INC 
+                8'b11x0_1000:   // INX, INY
+                                inc <= 1;
+
+                default:        inc <= 0;
+        endcase
+
+always @(posedge clk )
+     if( (state == DECODE || state == BRK0) && RDY )
+        casex( IR )
+                8'bx111_0010,   // SBC (zp), ADC (zp)
+                8'bx11x_xx01:   // SBC, ADC
+                                adc_sbc <= 1;
+
+                default:        adc_sbc <= 0;
+        endcase
+
+always @(posedge clk )
+     if( (state == DECODE || state == BRK0) && RDY )
+        casex( IR )
+                8'b0111_0010,   // ADC (zp)
+                8'b011x_xx01:   // ADC
+                                adc_bcd <= D;
+
+                default:        adc_bcd <= 0;
+        endcase
+
+always @(posedge clk )
+     if( state == DECODE && RDY )
+        casex( IR )
+                8'b0xxx_x110,   // ASL, ROL, LSR, ROR (abs, absx, zpg, zpgx)
+                8'b0xx0_1010:   // ASL, ROL, LSR, ROR (acc)
+                                shift <= 1;
+
+                default:        shift <= 0;
+        endcase
+
+always @(posedge clk )
+     if( state == DECODE && RDY )
+        casex( IR )
+                8'b1101_0010,   // CMP (zp)
+                8'b11x0_0x00,   // CPX, CPY (imm/zp)
+                8'b11x0_1100,   // CPX, CPY (abs)
+                8'b110x_xx01:   // CMP 
+                                compare <= 1;
+
+                default:        compare <= 0;
+        endcase
+
+always @(posedge clk )
+     if( state == DECODE && RDY )
+        casex( IR )
+                8'b01xx_x110,   // ROR, LSR
+                8'b01xx_1x10:   // ROR, LSR
+                                shift_right <= 1;
+
+                default:        shift_right <= 0; 
+        endcase
+
+always @(posedge clk )
+     if( state == DECODE && RDY )
+        casex( IR )
+                8'b0x10_1010,   // ROL A, ROR A
+                8'b0x1x_x110:   // ROR, ROL 
+                                rotate <= 1;
+
+                default:        rotate <= 0; 
+        endcase
+
+always @(posedge clk )
+     if( state == DECODE && RDY )
+        casex( IR )
+                8'b0000_x100:   // TSB
+                                op <= OP_OR;
+
+                8'b0001_x100:   // TRB
+                                op <= OP_AND;
+
+                8'b00xx_x110,   // ROL, ASL
+                8'b00x0_1010:   // ROL, ASL
+                                op <= OP_ROL;
+
+                8'b1000_1001,   // BIT imm
+                8'b001x_x100:   // BIT zp/abs/zpx/absx
+                                op <= OP_AND;
+
+                8'b01xx_x110,   // ROR, LSR
+                8'b01xx_1x10:   // ROR, LSR
+                                op <= OP_A;
+
+                8'b11x1_0010,   // CMP, SBC (zp)
+                8'b0011_1010,   // DEC A
+                8'b1000_1000,   // DEY
+                8'b1100_1010,   // DEX 
+                8'b110x_x110,   // DEC 
+                8'b11xx_xx01,   // CMP, SBC
+                8'b11x0_0x00,   // CPX, CPY (imm, zpg)
+                8'b11x0_1100:   op <= OP_SUB;
+
+                8'b00x1_0010,   // ORA, AND (zp)
+                8'b0x01_0010,   // ORA, EOR (zp)
+                8'b010x_xx01,   // EOR
+                8'b00xx_xx01:   // ORA, AND
+                                op <= { 2'b11, IR[6:5] };
+                
+                default:        op <= OP_ADD; 
+        endcase
+
+always @(posedge clk )
+     if( state == DECODE && RDY )
+        casex( IR )
+                8'b001x_x100:   // BIT zp/abs/zpx/absx (update N,V,Z)
+                                {bit_ins, bit_ins_nv}  <= 2'b11;
+
+                8'b1000_1001:   // BIT imm (update Z)
+                                {bit_ins, bit_ins_nv}  <= 2'b10;
+
+                default:        // not a BIT instruction
+                                {bit_ins, bit_ins_nv}  <= 2'b00;
+        endcase
+
+always @(posedge clk )
+     if( state == DECODE && RDY )
+        casex( IR )
+                8'b000x_x100:   // TRB/TSB
+                                txb_ins <= 1;
+
+                default:        txb_ins <= 0;
+        endcase
+
+always @(posedge clk )
+     if( state == DECODE && RDY )
+        casex( IR )
+                8'b0001_x100:   // TRB
+                                trb_ins <= 1;
+
+                default:        trb_ins <= 0;
+        endcase
+
+always @(posedge clk )
+     if( state == DECODE && RDY )
+        casex( IR )
+                8'b1001_11x0,   // STZ abs, STZ abs,x
+                8'b011x_0100:   // STZ zp, STZ zp,x
+                                store_zero <= 1;
+
+                default:        store_zero <= 0;
+        endcase
+
+/*
+ * special instructions
+ */
+always @(posedge clk )
+     if( state == DECODE && RDY ) begin
+        php <= (IR == 8'h08);
+        clc <= (IR == 8'h18);
+        plp <= (IR == 8'h28);
+        sec <= (IR == 8'h38);
+        cli <= (IR == 8'h58);
+        sei <= (IR == 8'h78);
+        clv <= (IR == 8'hb8);
+        cld <= (IR == 8'hd8);
+        sed <= (IR == 8'hf8);
+        brk <= (IR == 8'h00);
+     end
+
+always @(posedge clk)
+    if( RDY )
+        cond_code <= IR[7:4];
+
+always @*
+    case( cond_code )
+            4'b0001: cond_true = ~N;
+            4'b0011: cond_true = N;
+            4'b0101: cond_true = ~V;
+            4'b0111: cond_true = V;
+            4'b1001: cond_true = ~C;
+            4'b1011: cond_true = C;
+            4'b1101: cond_true = ~Z;
+            4'b1111: cond_true = Z;
+            default: cond_true = 1; // BRA is 80
+    endcase
+
+
+reg NMI_1 = 0;          // delayed NMI signal
+
+always @(posedge clk)
+    NMI_1 <= NMI;
+
+always @(posedge clk )
+    if( NMI_edge && state == BRK3 )
+        NMI_edge <= 0;
+    else if( NMI & ~NMI_1 )
+        NMI_edge <= 1;
+
+endmodule
+"
+"/*
+ *  Microcode instruction generator for Zet
+ *  Copyright (C) 2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+`include ""defines.v""
+
+module zet_micro_data (
+    input  [`MICRO_ADDR_WIDTH-1:0] n_micro,
+    input  [15:0] off_i,
+    input  [15:0] imm_i,
+    input  [ 3:0] src,
+    input  [ 3:0] dst,
+    input  [ 3:0] base,
+    input  [ 3:0] index,
+    input  [ 1:0] seg,
+    input  [ 2:0] fdec,
+    output        div,
+    output        end_seq,
+
+    output [`IR_SIZE-1:0] ir,
+    output [15:0]         off_o,
+    output [15:0]         imm_o
+  );
+
+  // Net declarations
+  wire [`MICRO_DATA_WIDTH-1:0] micro_o;
+  wire [ 6:0] ir1;
+  wire [ 1:0] ir0;
+  wire var_s, var_off;
+  wire [1:0] var_a, var_b, var_c, var_d;
+  wire [2:0] var_imm;
+
+  wire [3:0] addr_a, addr_b, addr_c, addr_d;
+  wire [3:0] micro_a, micro_b, micro_c, micro_d;
+  wire [1:0] addr_s, micro_s;
+  wire [2:0] t;
+  wire [2:0] f;
+  wire [2:0] f_rom;
+  wire       wr_flag;
+  wire       wr_mem;
+  wire       wr_rom;
+  wire       wr_d;
+
+  // Module instantiations
+  zet_micro_rom micro_rom (n_micro, micro_o);
+
+  // Assignments
+  assign micro_s = micro_o[1:0];
+  assign micro_a = micro_o[5:2];
+  assign micro_b = micro_o[9:6];
+  assign micro_c = micro_o[13:10];
+  assign micro_d = micro_o[17:14];
+  assign wr_flag = micro_o[18];
+  assign wr_mem  = micro_o[19];
+  assign wr_rom  = micro_o[20];
+  assign ir0     = micro_o[22:21];
+  assign t       = micro_o[25:23];
+  assign f_rom   = micro_o[28:26];
+  assign ir1     = micro_o[35:29];
+  assign var_s   = micro_o[36];
+  assign var_a   = micro_o[38:37];
+  assign var_b   = micro_o[40:39];
+  assign var_c   = micro_o[42:41];
+  assign var_d   = micro_o[44:43];
+  assign var_off = micro_o[45];
+  assign var_imm = micro_o[48:46];
+  assign end_seq = micro_o[49];
+
+  assign imm_o = var_imm == 3\'d0 ? (16\'h0000)
+               : (var_imm == 3\'d1 ? (16\'h0002)
+               : (var_imm == 3\'d2 ? (16\'h0004)
+               : (var_imm == 3\'d3 ? off_i
+               : (var_imm == 3\'d4 ? imm_i
+               : (var_imm == 3\'d5 ? 16\'hffff
+               : (var_imm == 3\'d6 ? 16\'b11 : 16\'d1))))));
+
+  assign off_o = var_off ? off_i : 16\'h0000;
+
+  assign addr_a = var_a == 2\'d0 ? micro_a
+                : (var_a == 2\'d1 ? base
+                : (var_a == 2\'d2 ? dst : src ));
+  assign addr_b = var_b == 2\'d0 ? micro_b
+                : (var_b == 2\'d1 ? index : src);
+  assign addr_c = var_c == 2\'d0 ? micro_c
+                : (var_c == 2\'d1 ? dst : src);
+  assign addr_d = var_d == 2\'d0 ? micro_d
+                : (var_d == 2\'d1 ? dst : src);
+  assign addr_s = var_s ? seg : micro_s;
+
+  assign div  = (t==3\'d3 && (f_rom[2]|f_rom[1]) && !wr_rom);
+  assign f    = (t==3\'d6 && wr_flag || t==3\'d5 && wr_rom) ? fdec : f_rom;
+  assign wr_d = (t==3\'d5 && f==3\'d7) ? 1\'b0 : wr_rom; /* CMP doesn\'t write */
+
+  assign ir = { ir1, f, t, ir0, wr_d, wr_mem, wr_flag, addr_d,
+                addr_c, addr_b, addr_a, addr_s };
+endmodule
+"
+"/*
+ *  Wishbone switch and address decoder
+ *  Copyright (C) 2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *  Copyright (C) 2008, 2009 Sebastien Bourdeauducq - http://lekernel.net
+ *  Copyright (C) 2000 Johny Chi - chisuhua@yahoo.com.cn
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+module wb_switch #(
+    parameter s0_addr_1 = 32'h00000000,
+    parameter s0_mask_1 = 32'h00000000,
+    parameter s0_addr_2 = 32'h00000000,
+    parameter s0_mask_2 = 32'h00000000,
+    parameter s1_addr_1 = 32'h00000000,
+    parameter s1_mask_1 = 32'h00000000,
+    parameter s2_addr_1 = 32'h00000000,
+    parameter s2_mask_1 = 32'h00000000
+
+  )(
+    // Master interface
+    input  [31:0] m_dat_i,
+    output [31:0] m_dat_o,
+    input  [31:0] m_adr_i,
+    input  [ 3:0] m_sel_i,
+    input         m_we_i,
+    input         m_cyc_i,
+    input         m_stb_i,
+    output        m_ack_o,
+
+    // Slave 0 interface
+    input  [31:0] s0_dat_i,
+    output [31:0] s0_dat_o,
+    output [31:0] s0_adr_o,
+    output [ 3:0] s0_sel_o,
+    output        s0_we_o,
+    output        s0_cyc_o,
+    output        s0_stb_o,
+    input         s0_ack_i,
+
+    // Slave 1 interface
+    input  [31:0] s1_dat_i,
+    output [31:0] s1_dat_o,
+    output [31:0] s1_adr_o,
+    output [ 3:0] s1_sel_o,
+    output        s1_we_o,
+    output        s1_cyc_o,
+    output        s1_stb_o,
+    input         s1_ack_i,
+
+    // Slave 2 interface
+    input  [31:0] s2_dat_i,
+    output [31:0] s2_dat_o,
+    output [31:0] s2_adr_o,
+    output [ 3:0] s2_sel_o,
+    output        s2_we_o,
+    output        s2_cyc_o,
+    output        s2_stb_o,
+    input         s2_ack_i,
+
+    // Slave 3 interface - the default
+    input  [31:0] s3_dat_i,
+    output [31:0] s3_dat_o,
+    output [31:0] s3_adr_o,
+    output [ 3:0] s3_sel_o,
+    output        s3_we_o,
+    output        s3_cyc_o,
+    output        s3_stb_o,
+    input         s3_ack_i
+    
+  );
+
+`define mbusw_ls  32 + 4 + 32 + 1 + 1 + 1  // address + byte select + data + cyc + we + stb
+
+wire [3:0] slave_sel;
+wire [31:0] i_dat_s;   // internal shared bus, slave data to master
+wire        i_bus_ack; // internal shared bus, ack signal
+
+wire [`mbusw_ls -1:0] i_bus_m;    // internal shared bus, master data and control to slave
+
+assign m_dat_o = i_dat_s;
+assign m_ack_o = i_bus_ack;
+
+// Bus Acknowlegement
+assign i_bus_ack =   s0_ack_i | s1_ack_i | s2_ack_i | s3_ack_i;
+
+assign i_dat_s =   ({32{slave_sel[ 0]}} & s0_dat_i)
+          |({32{slave_sel[ 1]}} & s1_dat_i)
+          |({32{slave_sel[ 2]}} & s2_dat_i)
+          |({32{slave_sel[ 3]}} & s3_dat_i)
+        ;
+
+// Bus Selection logic
+assign slave_sel[0] =  ((m_adr_i & s0_mask_1) == s0_addr_1) | ((m_adr_i & s0_mask_2) == s0_addr_2);
+assign slave_sel[1] = ~(|slave_sel[0]) & ((m_adr_i & s1_mask_1) == s1_addr_1);
+assign slave_sel[2] = ~(|slave_sel[1:0]) & ((m_adr_i & s2_mask_1) == s2_addr_1);
+assign slave_sel[3] = ~(|slave_sel[2:0]);
+
+assign i_bus_m = {m_adr_i, m_sel_i, m_dat_i, m_we_i, m_cyc_i, m_stb_i};
+
+assign {s0_adr_o, s0_sel_o, s0_dat_o, s0_we_o, s0_cyc_o}  = i_bus_m[`mbusw_ls -1:1];  // slave 0
+assign  s0_stb_o = i_bus_m[1] & i_bus_m[0] & slave_sel[0];
+
+assign {s1_adr_o, s1_sel_o, s1_dat_o, s1_we_o, s1_cyc_o} = i_bus_m[`mbusw_ls -1:1];    // slave 1
+assign  s1_stb_o = i_bus_m[1] & i_bus_m[0] & slave_sel[1];
+
+assign {s2_adr_o, s2_sel_o, s2_dat_o, s2_we_o, s2_cyc_o} = i_bus_m[`mbusw_ls -1:1];    // slave 2
+assign  s2_stb_o = i_bus_m[1] & i_bus_m[0] & slave_sel[2];
+
+assign {s3_adr_o, s3_sel_o, s3_dat_o, s3_we_o, s3_cyc_o} = i_bus_m[`mbusw_ls -1:1];    // slave 3
+assign  s3_stb_o = i_bus_m[1] & i_bus_m[0] & slave_sel[3];
+
+endmodule
+"
+"// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+// This file is part of the M32632 project\r
+// http://opencores.org/project,m32632\r
+//\r
+// Filename: ICACHE.v\r
+// Version:  1.0\r
+// Date:     30 May 2015\r
+//\r
+// Copyright (C) 2015 Udo Moeller\r
+// \r
+// This source file may be used and distributed without \r
+// restriction provided that this copyright statement is not \r
+// removed from the file and that any derivative work contains \r
+// the original copyright notice and the associated disclaimer.\r
+// \r
+// This source file is free software; you can redistribute it \r
+// and/or modify it under the terms of the GNU Lesser General \r
+// Public License as published by the Free Software Foundation;\r
+// either version 2.1 of the License, or (at your option) any \r
+// later version. \r
+// \r
+// This source is distributed in the hope that it will be \r
+// useful, but WITHOUT ANY WARRANTY; without even the implied \r
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR \r
+// PURPOSE. See the GNU Lesser General Public License for more \r
+// details. \r
+// \r
+// You should have received a copy of the GNU Lesser General \r
+// Public License along with this source; if not, download it \r
+// from http://www.opencores.org/lgpl.shtml \r
+// \r
+// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\tModules contained in this file:\r
+//\tICACHE\t\tthe instruction cache of M32632\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+module ICACHE( BCLK, MCLK, MDONE, BRESET, READ_I, IO_READY, PSR_USER, DATA_HOLD, PTB_WR, PTB_SEL, DRAM_WR,\r
+\t\t\t   KDET, HOLD, CFG, DRAM_Q, CINVAL, IC_SIGS, IO_Q, IVAR, KOLLI_A, MCR_FLAGS, MMU_DIN, VADR, WADDR,\r
+\t\t\t   WCTRL, IO_RD, DRAM_ACC, INIT_RUN, PROT_ERROR, ACC_OK, IC_PREQ, KOLLISION, ENA_HK, STOP_CINV,\r
+\t\t\t   DRAM_A, IC_DQ, IC_VA, ICTODC, IO_A, ENDRAM );\r
+\r
+input\t\t\tBCLK;\r
+input\t\t\tMCLK;\r
+input\t\t\tMDONE;\r
+input\t\t\tBRESET;\r
+input\t\t\tREAD_I;\r
+input\t\t\tIO_READY;\r
+input\t\t\tPSR_USER;\r
+input\t\t\tDATA_HOLD;\r
+input\t\t\tPTB_WR;\r
+input\t\t\tPTB_SEL;\r
+input\t\t\tDRAM_WR;\r
+input\t\t\tKDET;\r
+input\t\t\tHOLD;\r
+input\t [1:0]\tCFG;\r
+input\t[31:0]\tDRAM_Q;\r
+input\t [1:0]\tCINVAL;\r
+input\t [1:0]\tIC_SIGS;\r
+input\t[31:0]\tIO_Q;\r
+input\t [1:0]\tIVAR;\r
+input\t[27:4]\tKOLLI_A;\r
+input\t [3:0]\tMCR_FLAGS;\r
+input\t[23:0]\tMMU_DIN;\r
+input\t[31:0]\tVADR;\r
+input\t[11:2]\tWADDR;\r
+input\t [2:0]\tWCTRL;\r
+input\t\t\tENA_HK;\r
+input\t\t\tENDRAM;\r
+\r
+output\t\t\tIO_RD;\r
+output\t\t\tDRAM_ACC;\r
+output\t\t\tINIT_RUN;\r
+output\t\t\tPROT_ERROR;\r
+output\t\t\tACC_OK;\r
+output\t\t\tIC_PREQ;\r
+output\t\t\tKOLLISION;\r
+output\t\t\tSTOP_CINV;\r
+output\t[31:0]\tIC_DQ;\r
+output [31:12]\tIC_VA;\r
+output\t [3:0]\tICTODC;\r
+output reg\t[27:0]\tDRAM_A;\r
+output reg\t[31:0]\tIO_A;\r
+\r
+reg\t\t[31:0]\tVADR_R;\r
+reg\t\t[31:0]\tCAPDAT;\r
+reg\t\t[31:0]\tDFFE_IOR;\r
+reg\t\t\t\tHOLD_ON;\r
+reg\t\t\t\tDFF_HDFF1;\r
+reg\t\t\t\tDFF_IRD_REG;\r
+\r
+wire\t[4:0]\tA_CV;\r
+wire\t\t\tACOK;\r
+wire\t[4:0]\tACV;\r
+wire\t\t\tAUX_DAT;\r
+wire\t\t\tCA_HIT;\r
+wire\t\t\tCA_SET;\r
+wire\t\t\tCUPDATE;\r
+wire\t[23:0]\tD_CV;\r
+wire\t\t\tHIT_ALL;\r
+wire\t\t\tINIT_CA_RUN;\r
+wire\t\t\tIO_ACC;\r
+wire\t\t\tKILL;\r
+wire\t\t\tNEW_PTB;\r
+wire\t\t\tPTB_ONE;\r
+wire   [31:12]\tRADR;\r
+wire\t\t\tREAD;\r
+wire\t\t\tRUN_ICRD;\r
+wire\t\t\tSTOP_ICRD;\r
+wire\t[23:0]\tUPCD;\r
+wire\t[23:0]\tUPDATE_C;\r
+wire\t[31:0]\tUPDATE_M;\r
+wire\t\t\tUSE_CA;\r
+wire\t\t\tUSER;\r
+wire\t[11:7]\tV_ADR;\r
+wire\t\t\tWE_CV;\r
+wire\t\t\tWEMV;\r
+wire\t\t\tWRCRAM0;\r
+wire\t\t\tWRCRAM1;\r
+wire\t\t\tWRSET0;\r
+wire\t\t\tWRSET1;\r
+wire\t\t\tWRITE;\r
+wire\t[11:7]\tKILLADR;\r
+wire\t\t\tAUX_ALT;\r
+wire\t\t\tVIRT_A;\r
+wire\t\t\tCI;\r
+wire\t\t\tMMU_HIT;\r
+wire\t\t\tLD_DRAM_A;\r
+wire\t\t\tIO_SPACE;\r
+wire\t\t\tLAST_MUX;\r
+wire\t\t\tVIRTUELL;\r
+wire\t\t\tNEW_PTB_RUN;\r
+wire\t[31:0]\tSET_DAT;\r
+wire\t[31:0]\tALT_DAT;\r
+wire\t[31:0]\tDAT_MV;\r
+wire\t [3:0]\tRADR_MV;\r
+wire\t [3:0]\tWADR_MV;\r
+wire\t[23:0]\tNEWCVAL;\r
+wire\t\t\tKILL_C,KILL_K;\r
+wire\t\t\tRMW;\r
+\r
+// +++++++++++++++++++ Memories ++++++++++++++++++++\r
+\r
+reg\t \t[31:0]\tDATA0 [0:1023];\t\t// Data Set 0 : 4 kBytes\r
+reg\t\t[31:0]\tSET_DAT0;\r
+\r
+reg\t \t[31:0]\tDATA1 [0:1023];\t\t// Data Set 1 : 4 kBytes\r
+reg\t\t[31:0]\tSET_DAT1;\r
+\r
+reg\t\t[15:0]\tTAGSET_0 [0:255];\t// Tag Set for Data Set 0 : 256 entries of 16 bits\r
+reg\t\t[15:0]\tTAG0;\r
+\r
+reg\t\t[15:0]\tTAGSET_1 [0:255];\t// Tag Set for Data Set 1 : 256 entries of 16 bits\r
+reg\t\t[15:0]\tTAG1;\r
+\r
+reg\t\t[23:0]\tCA_VALID [0:31];\t// Valid bits for Data Set 0 and 1 : 32 entries of 24 bits\r
+reg\t\t[23:0]\tCVALID;\r
+\r
+reg\t\t[35:0]\tMMU_TAGS [0:255];\t// Tag Set for MMU : 256 entries of 36 bits\r
+reg\t\t[35:0]\tMMU_Q;\r
+\r
+reg\t\t[31:0]\tMMU_VALID [0:15];\t// Valid bits for MMU Tag Set : 16 entries of 32 bits\r
+reg\t\t[31:0]\tMVALID;\r
+\r
+reg\t\t[15:0]\tKTAGSET_0 [0:255];\t// Kollision Tag Set for Data Set 0 : 256 entries of 16 bits\r
+reg\t\t[15:0]\tKTAG0;\r
+\r
+reg\t\t[15:0]\tKTAGSET_1 [0:255];\t// Kollision Tag Set for Data Set 1 : 256 entries of 16 bits\r
+reg\t\t[15:0]\tKTAG1;\r
+\r
+reg\t\t[23:0]\tKCA_VALID [0:31];\t// Kollision Valid bits for Data Set 0 and 1 : 32 entries of 24 bits\r
+reg\t\t[23:0]\tKCVALID;\r
+\r
+assign\tREAD\t= READ_I & ~HOLD_ON & RUN_ICRD;\r
+assign\tWRITE\t= 1'b0;\r
+assign\tRMW\t\t= 1'b0;\r
+\r
+assign\tALT_DAT\t= AUX_ALT ? DFFE_IOR : CAPDAT ;\r
+\r
+assign\tRADR\t= VIRT_A ? MMU_Q[19:0] : VADR_R[31:12] ;\r
+\r
+assign\tV_ADR\t= STOP_ICRD ? KILLADR : VADR[11:7] ;\r
+assign\tACV\t\t= STOP_ICRD ? KILLADR : A_CV ;\r
+assign\tUPCD\t= STOP_ICRD ? NEWCVAL : UPDATE_C ;\r
+\r
+assign\tIC_DQ\t= LAST_MUX ? ALT_DAT : SET_DAT ;\r
+\r
+assign\tSET_DAT = CA_SET ? SET_DAT1 : SET_DAT0 ;\r
+\r
+assign\tKILL\t= KILL_C | KILL_K;\r
+\r
+assign\tIC_VA\t= VADR_R[31:12];\r
+\r
+assign\tVIRT_A\t= ~CINVAL[0] & VIRTUELL;\r
+\r
+assign\tACC_OK\t= HOLD_ON | ACOK;\r
+\r
+assign\tUSER\t= ~MCR_FLAGS[3] & PSR_USER;\r
+\r
+assign\tAUX_ALT = HOLD_ON | DFF_IRD_REG;\r
+\r
+assign\tLAST_MUX = AUX_ALT | AUX_DAT;\r
+\r
+assign\tINIT_RUN = NEW_PTB_RUN | INIT_CA_RUN;\r
+\r
+assign\tLD_DRAM_A = ~DRAM_ACC | MDONE;\r
+\r
+assign\tICTODC[3] = USER;\r
+\r
+always @(posedge BCLK) VADR_R <= VADR;\r
+\r
+always @(posedge BCLK) DFF_IRD_REG <= IO_RD;\r
+\r
+always @(posedge BCLK) DFF_HDFF1 <= IO_READY;\r
+\r
+always @(posedge BCLK) if (LD_DRAM_A) DRAM_A[27:0] <= {RADR[27:12],VADR_R[11:2],USE_CA,CA_SET};\r
+\r
+always @(posedge BCLK) if (IO_ACC) IO_A <= {RADR[31:12],VADR_R[11:0]};\r
+\r
+always @(posedge BCLK) if (IO_RD) DFFE_IOR <= IO_Q;\r
+\r
+always @(posedge BCLK or negedge BRESET)\r
+\tif (!BRESET) HOLD_ON <= 1'b0;\r
+\t\telse HOLD_ON <= (DATA_HOLD & DFF_HDFF1) | (HOLD_ON & DATA_HOLD);\r
+\r
+always @(posedge MCLK) if (WCTRL[2]) CAPDAT <= DRAM_Q;\r
+\r
+// +++++++++++++++++++++++++  Cache Valid  +++++++++++++++++++\r
+\r
+always @(posedge BCLK) CVALID <= CA_VALID[V_ADR[11:7]];\r
+\r
+always @(negedge BCLK) if (WE_CV) CA_VALID[ACV] <= D_CV;\r
+\r
+// +++++++++++++++++++++++++  Tag Set 0  +++++++++++++++++++++\r
+\r
+always @(posedge BCLK) TAG0 <= TAGSET_0[VADR[11:4]];\r
+\r
+always @(negedge BCLK) if (WRCRAM0) TAGSET_0[VADR_R[11:4]] <= RADR[27:12];\r
+\r
+// +++++++++++++++++++++++++  Tag Set 1  +++++++++++++++++++++\r
+\r
+always @(posedge BCLK) TAG1 <= TAGSET_1[VADR[11:4]];\r
+\r
+always @(negedge BCLK) if (WRCRAM1) TAGSET_1[VADR_R[11:4]] <= RADR[27:12];\r
+\r
+// +++++++++++++++++++++++++  Data Set 0  ++++++++++++++++++++\r
+\r
+always @(posedge BCLK) SET_DAT0 <= DATA0[VADR[11:2]];\r
+\t\r
+always @(posedge MCLK) if (WRSET0) DATA0[WADDR] <= DRAM_Q;\r
+\t\t\r
+// +++++++++++++++++++++++++  Data Set 1  ++++++++++++++++++++\r
+\r
+always @(posedge BCLK) SET_DAT1 <= DATA1[VADR[11:2]];\r
+\t\r
+always @(posedge MCLK) if (WRSET1) DATA1[WADDR] <= DRAM_Q;\r
+\r
+CA_MATCH\tDCA_COMPARE(\r
+\t.INVAL_L(CINVAL[0]),\r
+\t.CI(CI),\r
+\t.MMU_HIT(MMU_HIT),\r
+\t.WRITE(WRITE),\r
+\t.KDET(1'b0),\r
+\t.ADDR({RADR[27:12],VADR_R[11:4]}),\r
+\t.CFG(CFG),\r
+\t.ENDRAM(ENDRAM),\r
+\t.CVALID(CVALID),\r
+\t.TAG0(TAG0),\r
+\t.TAG1(TAG1),\r
+\t.CA_HIT(CA_HIT),\r
+\t.CA_SET(CA_SET),\r
+\t.WB_ACC(),\r
+\t.USE_CA(USE_CA),\r
+\t.IOSEL(RADR[31:28]),\r
+\t.IO_SPACE(IO_SPACE),\r
+\t.DC_ILO(1'b0),\r
+\t.KILL(KILL_C),\r
+\t.UPDATE(UPDATE_C));\r
+\t\r
+DCA_CONTROL\tDCA_CTRL(\r
+\t.BCLK(BCLK),\r
+\t.MCLK(1'b0),\r
+\t.WRCFG(1'b1),\r
+\t.BRESET(BRESET),\r
+\t.CA_SET(CA_SET),\r
+\t.HIT_ALL(HIT_ALL),\r
+\t.UPDATE(UPCD),\r
+\t.VADR_R(VADR_R[11:7]),\r
+\t.DRAM_ACC(DRAM_ACC),\r
+\t.CUPDATE(CUPDATE),\r
+\t.KILL(KILL),\r
+\t.WRITE(WRITE),\r
+\t.WCTRL(WCTRL[1:0]),\r
+\t.INVAL_A(CINVAL[1]),\r
+\t.DAT_CV(D_CV),\r
+\t.WADR_CV(A_CV),\r
+\t.WE_CV(WE_CV),\r
+\t.INIT_CA_RUN(INIT_CA_RUN),\r
+\t.WRCRAM0(WRCRAM0),\r
+\t.WRCRAM1(WRCRAM1),\r
+\t.WRSET0(WRSET0),\r
+\t.WRSET1(WRSET1));\r
+\r
+ICACHE_SM\tIC_SM(\r
+\t.BCLK(BCLK),\r
+\t.BRESET(BRESET),\r
+\t.IO_SPACE(IO_SPACE),\r
+\t.READ(READ),\r
+\t.MDONE(MDONE),\r
+\t.IO_READY(IO_READY),\r
+\t.MMU_HIT(MMU_HIT),\r
+\t.CA_HIT(CA_HIT),\r
+\t.USE_CA(USE_CA),\r
+\t.PTB_WR(PTB_WR),\r
+\t.PTB_SEL(PTB_SEL),\r
+\t.USER(USER),\r
+\t.PROT_ERROR(PROT_ERROR),\r
+\t.PTE_ACC(IC_SIGS[1]),\r
+\t.ACC_OK(ACOK),\r
+\t.PTB_ONE(PTB_ONE),\r
+\t.NEW_PTB(NEW_PTB),\r
+\t.AUX_DAT(AUX_DAT),\r
+\t.CUPDATE(CUPDATE),\r
+\t.IO_RD(IO_RD),\r
+\t.IO_ACC(IO_ACC),\r
+\t.DRAM_ACC(DRAM_ACC),\r
+\t.IC_PREQ(IC_PREQ),\r
+\t.HIT_ALL(HIT_ALL));\r
+\r
+// +++++++++++++++++++++++++  Kollision Valid  +++++++++++++++\r
+\r
+always @(posedge BCLK) KCVALID <= KCA_VALID[KOLLI_A[11:7]];\r
+\r
+always @(negedge BCLK) if (WE_CV) KCA_VALID[ACV] <= D_CV;\r
+\r
+// +++++++++++++++++++++++++  Kollision Tag Set 0  +++++++++++\r
+\r
+always @(posedge BCLK) KTAG0 <= KTAGSET_0[KOLLI_A[11:4]];\r
+\r
+always @(negedge BCLK) if (WRCRAM0) KTAGSET_0[VADR_R[11:4]] <= RADR[27:12];\r
+\r
+// +++++++++++++++++++++++++  Kollision Tag Set 1  +++++++++++\r
+\r
+always @(posedge BCLK) KTAG1 <= KTAGSET_1[KOLLI_A[11:4]];\r
+\r
+always @(negedge BCLK) if (WRCRAM1) KTAGSET_1[VADR_R[11:4]] <= RADR[27:12];\r
+\r
+KOLDETECT\tKOLLOGIK(\r
+\t.DRAM_WR(DRAM_WR),\r
+\t.BCLK(BCLK),\r
+\t.READ_I(READ_I),\r
+\t.ACC_OK(ACC_OK),\r
+\t.BRESET(BRESET),\r
+\t.INVAL_A(CINVAL[1]),\r
+\t.KDET(KDET),\r
+\t.HOLD(HOLD),\r
+\t.ENA_HK(ENA_HK),\r
+\t.STOP_CINV(STOP_CINV),\r
+\t.ADDR(KOLLI_A),\r
+\t.C_VALID(KCVALID),\r
+\t.CFG(CFG),\r
+\t.CVALID(CVALID),\r
+\t.TAG0(KTAG0),\r
+\t.TAG1(KTAG1),\r
+\t.KOLLISION(KOLLISION),\r
+\t.STOP_ICRD(STOP_ICRD),\r
+\t.RUN_ICRD(RUN_ICRD),\r
+\t.KILL(KILL_K),\r
+\t.ICTODC(ICTODC[2:0]),\r
+\t.KILLADR(KILLADR),\r
+\t.NEWCVAL(NEWCVAL));\r
+\r
+MMU_MATCH\tMMU_COMPARE(\r
+\t.USER(USER),\r
+\t.READ(READ),\r
+\t.WRITE(WRITE),\r
+\t.RMW(RMW),\r
+\t.IVAR(IVAR),\r
+\t.MCR_FLAGS(MCR_FLAGS[2:0]),\r
+\t.MMU_VA(MMU_Q[35:20]),\r
+\t.MVALID(MVALID),\r
+\t.VADR_R(VADR_R[31:12]),\r
+\t.MMU_HIT(MMU_HIT),\r
+\t.PROT_ERROR(PROT_ERROR),\r
+\t.VIRTUELL(VIRTUELL),\r
+\t.CI(CI),\r
+\t.SEL_PTB1(),\r
+\t.UPDATE(UPDATE_M));\r
+\r
+MMU_UP\tMMU_CTRL(\r
+\t.NEW_PTB(NEW_PTB),\r
+\t.IVAR(IVAR[1]),\r
+\t.BRESET(BRESET),\r
+\t.PTB1(PTB_ONE),\r
+\t.BCLK(BCLK),\r
+\t.WR_MRAM(IC_SIGS[0]),\r
+\t.MVALID(MVALID),\r
+\t.UPDATE(UPDATE_M),\r
+\t.VADR(VADR[19:16]),\r
+\t.VADR_R(VADR_R[19:16]),\r
+\t.WE_MV(WEMV),\r
+\t.NEW_PTB_RUN(NEW_PTB_RUN),\r
+\t.DAT_MV(DAT_MV),\r
+\t.RADR_MV(RADR_MV),\r
+\t.WADR_MV(WADR_MV));\r
+\r
+// +++++++++++++++++++++++++  MMU Valid  +++++++++++++++++++++\r
+\r
+always @(posedge BCLK) MVALID <= MMU_VALID[RADR_MV];\r
+\r
+always @(negedge BCLK) if (WEMV) MMU_VALID[WADR_MV] <= DAT_MV;\r
+\r
+// +++++++++++++++++++++++++  MMU Tags  ++++++++++++++++++++++\r
+\r
+always @(posedge BCLK) MMU_Q <= MMU_TAGS[VADR[19:12]];\r
+\r
+always @(negedge BCLK) if (IC_SIGS[0]) MMU_TAGS[VADR_R[19:12]] <= {VADR_R[31:20],MMU_DIN[23:0]};\r
+\r
+endmodule\r
+"
+"//////////////////////////////////////////////////////////////////
+//                                                              //
+//  Arithmetic Logic Unit (ALU) for Amber 2 Core                //
+//                                                              //
+//  This file is part of the Amber project                      //
+//  http://www.opencores.org/project,amber                      //
+//                                                              //
+//  Description                                                 //
+//  Supported functions: 32-bit add and subtract, AND, OR,      //
+//  XOR, NOT, Zero extent 8-bit numbers                         //
+//                                                              //
+//  Author(s):                                                  //
+//      - Conor Santifort, csantifort.amber@gmail.com           //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+//                                                              //
+// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
+//                                                              //
+// This source file may be used and distributed without         //
+// restriction provided that this copyright statement is not    //
+// removed from the file and that any derivative work contains  //
+// the original copyright notice and the associated disclaimer. //
+//                                                              //
+// This source file is free software; you can redistribute it   //
+// and/or modify it under the terms of the GNU Lesser General   //
+// Public License as published by the Free Software Foundation; //
+// either version 2.1 of the License, or (at your option) any   //
+// later version.                                               //
+//                                                              //
+// This source is distributed in the hope that it will be       //
+// useful, but WITHOUT ANY WARRANTY; without even the implied   //
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
+// PURPOSE.  See the GNU Lesser General Public License for more //
+// details.                                                     //
+//                                                              //
+// You should have received a copy of the GNU Lesser General    //
+// Public License along with this source; if not, download it   //
+// from http://www.opencores.org/lgpl.shtml                     //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+
+
+module a23_alu (
+
+input       [31:0]          i_a_in,
+input       [31:0]          i_b_in,
+input                       i_barrel_shift_carry,
+input                       i_status_bits_carry,
+input       [8:0]           i_function,
+
+output      [31:0]          o_out,
+output      [3:0]           o_flags       // negative, zero, carry, overflow
+);
+
+wire     [31:0]         a, b, b_not;
+wire     [31:0]         and_out, or_out, xor_out;
+wire     [31:0]         sign_ex8_out, sign_ex_16_out;
+wire     [31:0]         zero_ex8_out, zero_ex_16_out;
+wire     [32:0]         fadder_out;
+wire                    swap_sel;
+wire                    not_sel;
+wire     [1:0]          cin_sel;
+wire                    cout_sel;
+wire     [3:0]          out_sel;
+wire                    carry_in;
+wire                    carry_out;
+wire                    overflow_out;
+wire                    fadder_carry_out;
+
+assign  { swap_sel, not_sel, cin_sel, cout_sel, out_sel } = i_function;
+
+
+// ========================================================
+// A Select
+// ========================================================
+assign a     = (swap_sel ) ? i_b_in : i_a_in ;
+
+// ========================================================
+// B Select
+// ========================================================
+assign b     = (swap_sel ) ? i_a_in : i_b_in ;
+                             
+// ========================================================
+// Not Select
+// ========================================================
+assign b_not     = (not_sel ) ? ~b : b ;
+                             
+// ========================================================
+// Cin Select
+// ========================================================
+assign carry_in  = (cin_sel==2'd0 ) ? 1'd0                   :
+                   (cin_sel==2'd1 ) ? 1'd1                   :
+                                      i_status_bits_carry    ;  // add with carry
+
+// ========================================================
+// Cout Select
+// ========================================================
+assign carry_out = (cout_sel==1'd0 ) ? fadder_carry_out     :
+                                       i_barrel_shift_carry ;
+
+// For non-addition/subtractions that incorporate a shift 
+// operation, C is set to the last bit
+// shifted out of the value by the shifter.
+
+
+// ========================================================
+// Overflow out
+// ========================================================
+// Only assert the overflow flag when using the adder
+assign  overflow_out    = out_sel == 4'd1 &&
+                            // overflow if adding two positive numbers and get a negative number
+                          ( (!a[31] && !b_not[31] && fadder_out[31]) ||
+                            // or adding two negative numbers and get a positive number
+                            (a[31] && b_not[31] && !fadder_out[31])     );
+
+
+// ========================================================
+// ALU Operations
+// ========================================================
+
+`ifdef XILINX_FPGA
+
+    // XIlinx Spartan 6 DSP module
+    `ifdef XILINX_SPARTAN6_FPGA
+        xs6_addsub_n #(.WIDTH(33)) 
+    `endif
+    `ifdef XILINX_VIRTEX6_FPGA
+        xv6_addsub_n #(.WIDTH(33)) 
+    `endif
+        u_xx_addsub_33(
+        .i_a    ( {1'd0,a}      ),
+        .i_b    ( {1'd0,b_not}  ),
+        .i_cin  ( carry_in      ),
+        .i_sub  ( 1'd0          ),
+        .o_sum  ( fadder_out    ),
+        .o_co   (               )
+    );
+
+`else
+assign fadder_out       = { 1'd0,a} + {1'd0,b_not} + {32'd0,carry_in};
+`endif                                                
+
+assign fadder_carry_out = fadder_out[32];
+assign and_out          = a & b_not;
+assign or_out           = a | b_not;
+assign xor_out          = a ^ b_not;
+assign zero_ex8_out     = {24'd0,  b_not[7:0]};
+assign zero_ex_16_out   = {16'd0,  b_not[15:0]};
+assign sign_ex8_out     = {{24{b_not[7]}},  b_not[7:0]};
+assign sign_ex_16_out   = {{16{b_not[15]}}, b_not[15:0]};
+                          
+// ========================================================
+// Out Select
+// ========================================================
+assign o_out = out_sel == 4'd0 ? b_not            : 
+               out_sel == 4'd1 ? fadder_out[31:0] : 
+               out_sel == 4'd2 ? zero_ex_16_out   :
+               out_sel == 4'd3 ? zero_ex8_out     :
+               out_sel == 4'd4 ? sign_ex_16_out   :
+               out_sel == 4'd5 ? sign_ex8_out     :
+               out_sel == 4'd6 ? xor_out          :
+               out_sel == 4'd7 ? or_out           :
+                                 and_out          ;
+
+assign o_flags       = {  o_out[31],      // negative
+                         |o_out == 1'd0,  // zero
+                         carry_out,       // carry
+                         overflow_out     // overflow
+                         };
+                         
+                                     
+endmodule
+
+
+"
+"//////////////////////////////////////////////////////////////////
+//                                                              //
+//  Wishbone master interface for the Amber core                //
+//                                                              //
+//  This file is part of the Amber project                      //
+//  http://www.opencores.org/project,amber                      //
+//                                                              //
+//  Description                                                 //
+//  Turns memory access requests from the execute stage and     //
+//  cache into wishbone bus cycles. For 4-word read requests    //
+//  from the cache and swap accesses ( read followed by write   //
+//  to the same address) from the execute stage,                //
+//  a block transfer is done. All other requests result in      //
+//  single word transfers.                                      //
+//                                                              //
+//  Write accesses can be done in a single clock cycle on       //
+//  the wishbone bus, is the destination allows it. The         //
+//  next transfer will begin immediately on the                 //
+//  next cycle on the bus. This looks like a block transfer     //
+//  and does hold ownership of the wishbone bus, preventing     //
+//  the other master ( the ethernet MAC) from gaining           //
+//  ownership between those two cycles. But otherwise it would  //
+//  be necessary to insert a wait cycle after every write,      //
+//  slowing down the performance of the core by around 5 to     //
+//  10%.                                                        //
+//                                                              //
+//  Author(s):                                                  //
+//      - Conor Santifort, csantifort.amber@gmail.com           //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+//                                                              //
+// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
+//                                                              //
+// This source file may be used and distributed without         //
+// restriction provided that this copyright statement is not    //
+// removed from the file and that any derivative work contains  //
+// the original copyright notice and the associated disclaimer. //
+//                                                              //
+// This source file is free software; you can redistribute it   //
+// and/or modify it under the terms of the GNU Lesser General   //
+// Public License as published by the Free Software Foundation; //
+// either version 2.1 of the License, or (at your option) any   //
+// later version.                                               //
+//                                                              //
+// This source is distributed in the hope that it will be       //
+// useful, but WITHOUT ANY WARRANTY; without even the implied   //
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
+// PURPOSE.  See the GNU Lesser General Public License for more //
+// details.                                                     //
+//                                                              //
+// You should have received a copy of the GNU Lesser General    //
+// Public License along with this source; if not, download it   //
+// from http://www.opencores.org/lgpl.shtml                     //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+
+
+module a23_wishbone
+(
+input                       i_clk,
+
+// Core Accesses to Wishbone bus
+input                       i_select,
+input       [31:0]          i_write_data,
+input                       i_write_enable,
+input       [3:0]           i_byte_enable,    // valid for writes only
+input                       i_data_access,
+input                       i_exclusive,      // high for read part of swap access
+input       [31:0]          i_address,
+output                      o_stall,
+
+// Cache Accesses to Wishbone bus
+input                       i_cache_req,
+
+// Wishbone Bus
+output reg  [31:0]          o_wb_adr = \'d0,
+output reg  [3:0]           o_wb_sel = \'d0,
+output reg                  o_wb_we  = \'d0,
+input       [31:0]          i_wb_dat,
+output reg  [31:0]          o_wb_dat = \'d0,
+output reg                  o_wb_cyc = \'d0,
+output reg                  o_wb_stb = \'d0,
+input                       i_wb_ack,
+input                       i_wb_err
+
+);
+
+
+localparam [3:0] WB_IDLE            = 3\'d0,
+                 WB_BURST1          = 3\'d1,
+                 WB_BURST2          = 3\'d2,
+                 WB_BURST3          = 3\'d3,
+                 WB_WAIT_ACK        = 3\'d4;
+
+reg     [2:0]               wishbone_st = WB_IDLE;
+
+wire                        core_read_request;
+wire                        core_write_request;
+wire                        cache_read_request;
+wire                        cache_write_request;
+wire                        start_access;
+reg                         servicing_cache = \'d0;
+wire    [3:0]               byte_enable;
+reg                         exclusive_access = \'d0;
+wire                        read_ack;
+wire                        wait_write_ack;
+wire                        wb_wait;
+
+// Write buffer
+reg     [31:0]              wbuf_addr_r = \'d0;
+reg     [3:0]               wbuf_sel_r  = \'d0;
+reg                         wbuf_busy_r = \'d0;
+
+
+assign read_ack             = !o_wb_we && i_wb_ack;
+assign o_stall              = ( core_read_request  && !read_ack )       || 
+                              ( core_read_request  && servicing_cache ) ||
+                              ( core_write_request && servicing_cache ) ||
+                              ( core_write_request && wishbone_st == WB_WAIT_ACK) ||
+                              ( cache_write_request && wishbone_st == WB_WAIT_ACK) ||
+                              wbuf_busy_r;
+
+                              // Don\'t stall on writes
+                              // Wishbone is doing burst read so make core wait to execute the write
+                              // ( core_write_request && !i_wb_ack )  ;
+                              
+assign core_read_request    = i_select && !i_write_enable;
+assign core_write_request   = i_select &&  i_write_enable;
+
+assign cache_read_request   = i_cache_req && !i_write_enable;
+assign cache_write_request  = i_cache_req &&  i_write_enable;
+
+assign wb_wait              = o_wb_stb && !i_wb_ack;
+assign start_access         = (core_read_request || core_write_request || i_cache_req) && !wb_wait ;
+
+// For writes the byte enable is always 4\'hf
+assign byte_enable          = wbuf_busy_r                                   ? wbuf_sel_r    :
+                              ( core_write_request || cache_write_request ) ? i_byte_enable : 
+                                                                              4\'hf          ;
+                                    
+
+
+// ======================================
+// Write buffer
+// ======================================
+
+
+always @( posedge i_clk )
+    if ( wb_wait && !wbuf_busy_r && (core_write_request || cache_write_request) )
+        begin
+        wbuf_addr_r <= i_address;
+        wbuf_sel_r  <= i_byte_enable;
+        wbuf_busy_r <= 1\'d1;
+        end
+    else if (!o_wb_stb)
+        wbuf_busy_r <= 1\'d0;
+    
+// ======================================
+// Register Accesses
+// ======================================
+always @( posedge i_clk )
+    if ( start_access )
+        o_wb_dat <= i_write_data;
+
+
+assign wait_write_ack = o_wb_stb && o_wb_we && !i_wb_ack;
+
+
+always @( posedge i_clk )
+    case ( wishbone_st )
+        WB_IDLE :
+            begin 
+                
+            if ( start_access )
+                begin
+                o_wb_stb            <= 1\'d1; 
+                o_wb_cyc            <= 1\'d1; 
+                o_wb_sel            <= byte_enable;
+                end
+            else if ( !wait_write_ack )
+                begin
+                o_wb_stb            <= 1\'d0;
+                
+                // Hold cyc high after an exclusive access
+                // to hold ownership of the wishbone bus
+                o_wb_cyc            <= exclusive_access;
+                end
+
+            // cache has priority over the core                     
+            servicing_cache <= cache_read_request && !wait_write_ack;
+
+            if ( wait_write_ack )
+                begin
+                // still waiting for last (write) access to complete
+                wishbone_st      <= WB_WAIT_ACK;
+                end  
+            // do a burst of 4 read to fill a cache line                   
+            else if ( cache_read_request )
+                begin
+                wishbone_st         <= WB_BURST1;
+                exclusive_access    <= 1\'d0;
+                end                    
+            else if ( core_read_request )
+                begin
+                wishbone_st         <= WB_WAIT_ACK;
+                exclusive_access    <= i_exclusive;
+                end                    
+           // The core does not currently issue exclusive write requests
+           // but there\'s no reason why this might not be added some
+           // time in the future so allow for it here
+            else if ( core_write_request )
+                exclusive_access <= i_exclusive;
+
+                            
+            if ( start_access )
+                begin
+                if (wbuf_busy_r)
+                    begin
+                    o_wb_we              <= 1\'d1;
+                    o_wb_adr[31:2]       <= wbuf_addr_r[31:2];
+                    end
+                else
+                    begin
+                    o_wb_we              <= core_write_request || cache_write_request;
+                    // only update these on new wb access to make debug easier
+                    o_wb_adr[31:2]       <= i_address[31:2];
+                    end
+                    
+                o_wb_adr[1:0]        <= byte_enable == 4\'b0001 ? 2\'d0 :
+                                        byte_enable == 4\'b0010 ? 2\'d1 :
+                                        byte_enable == 4\'b0100 ? 2\'d2 :
+                                        byte_enable == 4\'b1000 ? 2\'d3 :
+                                       
+                                        byte_enable == 4\'b0011 ? 2\'d0 :
+                                        byte_enable == 4\'b1100 ? 2\'d2 :
+                                       
+                                                                 2\'d0 ;
+                end
+            end
+                    
+
+        // Read burst, wait for first ack
+        WB_BURST1:  
+            if ( i_wb_ack )
+                begin
+                // burst of 4 that wraps
+                o_wb_adr[3:2]   <= o_wb_adr[3:2] + 1\'d1;
+                wishbone_st     <= WB_BURST2;
+                end
+            
+            
+        // Read burst, wait for second ack
+        WB_BURST2:  
+            if ( i_wb_ack )
+                begin
+                // burst of 4 that wraps
+                o_wb_adr[3:2]   <= o_wb_adr[3:2] + 1\'d1;
+                wishbone_st     <= WB_BURST3;
+                end
+            
+            
+        // Read burst, wait for third ack
+        WB_BURST3:  
+            if ( i_wb_ack )
+                begin
+                // burst of 4 that wraps
+                o_wb_adr[3:2]   <= o_wb_adr[3:2] + 1\'d1;
+                wishbone_st     <= WB_WAIT_ACK;
+                end
+
+
+        // Wait for the wishbone ack to be asserted
+        WB_WAIT_ACK:   
+            if ( i_wb_ack )
+                begin
+                wishbone_st         <= WB_IDLE;
+                o_wb_stb            <= 1\'d0; 
+                o_wb_cyc            <= exclusive_access; 
+                o_wb_we             <= 1\'d0;
+                servicing_cache     <= 1\'d0;
+                end
+                         
+    endcase
+        
+        
+
+// ========================================================
+// Debug Wishbone bus - not synthesizable
+// ========================================================
+//synopsys translate_off
+wire    [(14*8)-1:0]   xAS_STATE;
+
+
+assign xAS_STATE  = wishbone_st == WB_IDLE       ? ""WB_IDLE""       :
+                    wishbone_st == WB_BURST1     ? ""WB_BURST1""     :
+                    wishbone_st == WB_BURST2     ? ""WB_BURST2""     :
+                    wishbone_st == WB_BURST3     ? ""WB_BURST3""     :
+                    wishbone_st == WB_WAIT_ACK   ? ""WB_WAIT_ACK""   :
+                                                      ""UNKNOWN""       ;
+
+//synopsys translate_on
+    
+endmodule
+
+"
+"module bootrom (
+    input clk,
+    input rst,
+
+    // Wishbone slave interface
+    input      [31:0] wb_dat_i,
+    output reg [31:0] wb_dat_o,
+    input      [31:0] wb_adr_i,
+    input             wb_we_i,
+    input             wb_stb_i,
+    input             wb_cyc_i,
+    input      [ 3:0] wb_sel_i,
+    output reg        wb_ack_o
+  );
+
+  // Net declarations
+  reg  [31:0] rom[0:4095];  // Instantiate the ROM
+
+  wire [ 11:0] rom_addr;
+  wire        stb;
+  reg        stb1;
+   
+  // Combinatorial logic
+  assign rom_addr = wb_adr_i[13:2];
+  assign stb      = wb_stb_i & wb_cyc_i;
+
+  always @(posedge clk)
+    begin
+       stb1 <= stb;
+       wb_ack_o <= stb & ~stb1;
+       wb_dat_o <= rom[rom_addr];  
+    end
+  
+  initial $readmemh(""bootrom.dat"", rom);
+
+endmodule
+"
+"/*
+ *  Instruction decoder for Zet
+ *  Copyright (C) 2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+`include ""defines.v""
+
+module zet_decode (
+    input clk,
+    input rst,
+    input [7:0] opcode,
+    input [7:0] modrm,
+    input       rep,
+    input block,
+    input exec_st,
+    input div_exc,
+    input ld_base,
+    input div,
+    input        tfl,
+    output       tflm,
+
+    output need_modrm,
+    output need_off,
+    output need_imm,
+    output off_size,
+    output imm_size,
+
+    input  [2:0] sop_l,
+
+    input        intr,
+    input        ifl,
+    output       iflm,
+    output reg   inta,
+    output       ext_int,
+    input        nmir,
+    output reg   nmia,
+    input        wr_ss,
+    output       iflss,
+
+    // to microcode
+    output [`MICRO_ADDR_WIDTH-1:0] seq_addr,
+    output [3:0] src,
+    output [3:0] dst,
+    output [3:0] base,
+    output [3:0] index,
+    output [1:0] seg,
+    output [2:0] f,
+
+    // from microcode
+    input  end_seq,
+
+    input use_eintp
+  );
+
+  // Net declarations
+  wire [`MICRO_ADDR_WIDTH-1:0] base_addr;
+  reg  [`MICRO_ADDR_WIDTH-1:0] seq;
+  reg  dive;
+  reg  tfle;
+  reg  tfld;
+  reg  ifld;
+  reg  iflssd;
+  reg  ext_irq;
+  reg  ext_nmi;
+  reg  old_ext_irq;
+  reg  old_ext_nmi;
+
+  reg [4:0] div_cnt;
+
+  // Module instantiations
+  zet_opcode_deco opcode_deco (opcode, modrm, rep, sop_l, base_addr, need_modrm,
+                             need_off, need_imm, off_size, imm_size, src, dst,
+                             base, index, seg);
+
+  // Assignments
+  assign seq_addr = (tfle ? `INTT : (dive ? `INTD
+    : (ext_int ? (use_eintp ? `EINTP : `EINT) : base_addr))) + seq;
+
+  assign f = opcode[7] ? modrm[5:3] : opcode[5:3];
+
+  assign iflm = ifl & ifld;
+  assign tflm = tfl & tfld;
+
+  assign iflss = !wr_ss & iflssd;
+
+  // Behaviour
+  always @(posedge clk)
+    ifld <= rst ? 1\'b0 : (exec_st ? ifld : ifl);
+
+  always @(posedge clk)
+    tfld <= rst ? 1\'b0 : (exec_st ? tfld : tfl);
+
+  always @(posedge clk)
+    if (rst)
+      iflssd <= 1\'b0;
+    else
+    begin
+      if (!exec_st)
+        iflssd <= 1\'b1;
+      else if (wr_ss)
+        iflssd <= 1\'b0;
+    end
+
+  // seq
+  always @(posedge clk)
+    seq <= rst ? `MICRO_ADDR_WIDTH\'d0
+         : block ? seq
+         : end_seq ? `MICRO_ADDR_WIDTH\'d0
+         : |div_cnt ? seq
+         : exec_st ? (seq + `MICRO_ADDR_WIDTH\'d1) : `MICRO_ADDR_WIDTH\'d0;
+
+  // div_cnt - divisor counter
+  always @(posedge clk)
+    div_cnt <= rst ? 5\'d0
+       : ((div & exec_st) ? (div_cnt==5\'d0 ? 5\'d18 : div_cnt - 5\'d1) : 5\'d0);
+
+  // dive
+  always @(posedge clk)
+    if (rst) dive <= 1\'b0;
+    else dive <= block ? dive
+     : (div_exc ? 1\'b1 : (dive ? !end_seq : 1\'b0));
+
+  // tfle
+  always @(posedge clk)
+    if (rst) tfle <= 1\'b0;
+    else tfle <= block ? tfle
+     : ((((tflm & !tfle) & iflss) & exec_st & end_seq) ? 1\'b1 : (tfle ? !end_seq : 1\'b0));
+
+  // ext_irq
+  always @(posedge clk)
+    if (rst) ext_irq <= 1\'b0;
+    else ext_irq <= block ? ext_irq
+      : ((!nmir & intr & iflm & iflss & exec_st & end_seq) ? 1\'b1
+        : (ext_irq ? !end_seq : 1\'b0));
+
+  // ext_nmi
+  always @(posedge clk)
+    if (rst) ext_nmi <= 1\'b0;
+    else ext_nmi <= block ? ext_nmi
+      : ((nmir  & iflss & exec_st & end_seq) ? 1\'b1
+        : (ext_nmi ? !end_seq : 1\'b0));
+
+  assign ext_int = ext_irq | ext_nmi;
+
+  // old_ext_int
+  always @(posedge clk) old_ext_irq <= rst ? 1\'b0 : ext_irq;
+
+  // old_ext_int
+  always @(posedge clk) old_ext_nmi <= rst ? 1\'b0 : ext_nmi;
+
+  // inta
+  always @(posedge clk)
+    inta <= rst ? 1\'b0 : (!old_ext_irq & ext_irq);
+
+  // nmia
+  always @(posedge clk)
+    nmia <= rst ? 1\'b0 : (!old_ext_nmi & ext_nmi);
+
+endmodule
+"
+"// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+// This file is part of the M32632 project\r
+// http://opencores.org/project,m32632\r
+//\r
+// Filename: DCACHE.v\r
+// Version:  1.1 bug fix\r
+// History:  1.0 first release of 30 Mai 2015\r
+// Date:     7 October 2015\r
+//\r
+// Copyright (C) 2015 Udo Moeller\r
+// \r
+// This source file may be used and distributed without \r
+// restriction provided that this copyright statement is not \r
+// removed from the file and that any derivative work contains \r
+// the original copyright notice and the associated disclaimer.\r
+// \r
+// This source file is free software; you can redistribute it \r
+// and/or modify it under the terms of the GNU Lesser General \r
+// Public License as published by the Free Software Foundation;\r
+// either version 2.1 of the License, or (at your option) any \r
+// later version. \r
+// \r
+// This source is distributed in the hope that it will be \r
+// useful, but WITHOUT ANY WARRANTY; without even the implied \r
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR \r
+// PURPOSE. See the GNU Lesser General Public License for more \r
+// details. \r
+// \r
+// You should have received a copy of the GNU Lesser General \r
+// Public License along with this source; if not, download it \r
+// from http://www.opencores.org/lgpl.shtml \r
+// \r
+// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\tModules contained in this file:\r
+//\tDCACHE\t\tthe data cache of M32632\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+module DCACHE( \tBCLK, MCLK,\tWRCFG, MDONE, BRESET, PTB_WR, PTB_SEL, IO_READY, REG_OUT, PSR_USER, WRITE, READ, RMW, QWATWO,\r
+\t\t\t\tWAMUX, ENWR, IC_PREQ, FILLRAM, CFG, CINVAL, DMA_AA, DP_Q, DRAM_Q, IC_VA, ICTODC, IO_Q, IVAR, MCR_FLAGS, \r
+\t\t\t\tPACKET, SIZE, VADR,\tWADDR, WCTRL, IO_RD, IO_WR, DRAM_ACC, DRAM_WR, INIT_RUN, PTE_STAT, KDET, HLDA, \r
+\t\t\t\tACC_STAT, DP_DI, DRAM_A, DRAM_DI, IACC_STAT, IC_SIGS, IO_A, IO_BE, IO_DI, KOLLI_A, MMU_DIN, ZTEST, \r
+\t\t\t\tRWVAL, RWVFLAG, DBG_IN, DBG_HIT, ENDRAM );\r
+\r
+input\t\t\tBCLK;\r
+input\t\t\tMCLK;\r
+input\t\t\tWRCFG;\r
+input\t\t\tMDONE;\r
+input\t\t\tBRESET;\r
+input\t\t\tPTB_WR;\r
+input\t\t\tPTB_SEL;\r
+input\t\t\tIO_READY;\r
+input\t\t\tREG_OUT;\r
+input\t\t\tPSR_USER;\r
+input\t\t\tWRITE;\r
+input\t\t\tREAD;\r
+input\t\t\tZTEST;\r
+input\t\t\tRMW;\r
+input\t\t\tQWATWO;\r
+input\t\t\tWAMUX;\r
+input\t\t\tENWR;\r
+input\t\t\tIC_PREQ;\r
+input\t\t\tFILLRAM;\r
+input\t [1:0]\tCFG;\r
+input\t [1:0]\tCINVAL;\r
+input\t[27:4]\tDMA_AA;\r
+input\t[63:0]\tDP_Q;\r
+input\t[31:0]\tDRAM_Q;\r
+input  [31:12]\tIC_VA;\r
+input\t [3:0]\tICTODC;\r
+input\t[31:0]\tIO_Q;\r
+input\t [1:0]\tIVAR;\r
+input\t [3:0]\tMCR_FLAGS;\r
+input\t [3:0]\tPACKET;\r
+input\t [1:0]\tSIZE;\r
+input\t[31:0]\tVADR;\r
+input\t[11:2]\tWADDR;\r
+input\t [2:0]\tWCTRL;\r
+input\t [2:0]\tRWVAL;\r
+input\t[40:2]\tDBG_IN;\r
+input\t\t\tENDRAM;\r
+\r
+output\t\t\tIO_RD;\r
+output\t\t\tIO_WR;\r
+output\t\t\tDRAM_ACC;\r
+output\t\t\tDRAM_WR;\r
+output\t\t\tINIT_RUN;\r
+output\t [1:0]\tPTE_STAT;\r
+output\t\t\tKDET;\r
+output\t\t\tHLDA;\r
+output\t\t\tRWVFLAG;\r
+output\t [5:0]\tACC_STAT;\r
+output\t[31:0]\tDP_DI;\r
+output\t [3:1]\tIACC_STAT;\r
+output\t [1:0]\tIC_SIGS;\r
+output\t[27:4]\tKOLLI_A;\r
+output\t[23:0]\tMMU_DIN;\r
+output reg\t[27:0]\tDRAM_A;\r
+output reg\t[35:0]\tDRAM_DI;\r
+output reg\t[31:0]\tIO_A;\r
+output reg\t [3:0]\tIO_BE;\r
+output reg\t[31:0]\tIO_DI;\r
+output\t\t\tDBG_HIT;\r
+\r
+reg\t\t[31:0]\tDFFE_IOR;\r
+reg\t\t[31:0]\tCAPDAT;\r
+reg\t\t[31:0]\tVADR_R;\r
+reg\t\t\t\tAUX_ALT;\r
+reg\t\t\t\tDFF_QWEXT;\r
+\r
+wire\t[27:4]\tADDR;\r
+wire\t\t\tADR_EQU;\r
+wire\t\t\tAUX_DAT;\r
+wire\t\t\tCA_HIT;\r
+wire\t\t\tCA_SET;\r
+wire\t\t\tCUPDATE;\r
+wire\t\t\tDMA_MUX;\r
+wire\t [3:0]\tENBYTE;\r
+wire\t\t\tHIT_ALL;\r
+wire\t\t\tINIT_CA_RUN;\r
+wire\t\t\tIO_ACC;\r
+wire\t\t\tIO_SPACE;\r
+wire\t\t\tKOMUX;\r
+wire\t\t\tMMU_HIT;\r
+wire\t\t\tNEW_PTB;\r
+wire\t\t\tPTB_ONE;\r
+wire\t[27:0]\tPTE_ADR;\r
+wire   [31:12]\tRADR;\r
+wire\t[11:4]\tTAGA;\r
+wire\t[23:0]\tUPDATE_C;\r
+wire\t[31:0]\tUPDATE_M;\r
+wire\t\t\tUSE_CA;\r
+wire\t\t\tUSER;\r
+wire\t\t\tWB_ACC;\r
+wire\t\t\tWEMV;\r
+wire\t\t\tWR_MRAM;\r
+wire\t[31:0]\tWRDATA;\r
+wire\t\t\tVIRT_A;\r
+wire\t\t\tPTE_MUX;\r
+wire\t\t\tWE_CV;\r
+wire\t[23:0]\tDAT_CV;\r
+wire\t [4:0]\tWADR_CV;\r
+wire\t\t\tWRSET0;\r
+wire\t [3:0]\tBE_SET;\r
+wire\t[31:0]\tDAT_SET;\r
+wire\t [9:0]\tA_SET;\r
+wire\t\t\tWRSET1;\r
+wire\t\t\tSEL_PTB1;\r
+wire\t\t\tCI;\r
+wire\t[27:0]\tADR_MX;\r
+wire\t\t\tLD_DRAM_A;\r
+wire\t\t\tVIRTUELL;\r
+wire\t\t\tNEW_PTB_RUN;\r
+wire\t\t\tKILL;\r
+wire\t\t\tLAST_MUX;\r
+wire\t[31:0]\tSET_DAT;\r
+wire\t[31:0]\tALT_DAT;\r
+wire\t[31:0]\tDAT_MV;\r
+wire\t [3:0]\tRADR_MV;\r
+wire\t [3:0]\tWADR_MV;\r
+wire\t[31:0]\tLAST_DAT;\r
+wire\t\t\tWRCRAM0;\r
+wire\t\t\tWRCRAM1;\r
+wire\t\t\tPROT_ERROR;\r
+wire\t\t\tAUX_QW;\r
+wire\t\t\tPD_MUX;\r
+wire\t[19:0]\tPTE_DAT;\r
+wire\t\t\tPKEEP;\r
+\r
+// +++++++++++++++++++ Memories ++++++++++++++++++++\r
+\r
+reg\t \t [7:0]\tDATA0_D [0:1023];\t// Data Set 0 : 4 kBytes\r
+reg\t \t [7:0]\tDATA0_C [0:1023];\r
+reg\t \t [7:0]\tDATA0_B [0:1023];\r
+reg\t \t [7:0]\tDATA0_A [0:1023];\r
+reg\t\t[31:0]\tSET_DAT0;\r
+\r
+reg\t \t [7:0]\tDATA1_D [0:1023];\t// Data Set 1 : 4 kBytes\r
+reg\t \t [7:0]\tDATA1_C [0:1023];\r
+reg\t \t [7:0]\tDATA1_B [0:1023];\r
+reg\t \t [7:0]\tDATA1_A [0:1023];\r
+reg\t\t[31:0]\tSET_DAT1;\r
+\r
+reg\t\t[15:0]\tTAGSET_0 [0:255];\t// Tag Set for Data Set 0 : 256 entries of 16 bits\r
+reg\t\t[15:0]\tTAG0;\r
+\r
+reg\t\t[15:0]\tTAGSET_1 [0:255];\t// Tag Set for Data Set 1 : 256 entries of 16 bits\r
+reg\t\t[15:0]\tTAG1;\r
+\r
+reg\t\t[23:0]\tCA_VALID [0:31];\t// Valid bits for Data Set 0 and 1 : 32 entries of 24 bits\r
+reg\t\t[23:0]\tCVALID;\r
+\r
+reg\t\t[35:0]\tMMU_TAGS [0:255];\t// Tag Set for MMU : 256 entries of 36 bits\r
+reg\t\t[35:0]\tMMU_Q;\r
+\r
+reg\t\t[31:0]\tMMU_VALID [0:15];\t// Valid bits for MMU Tag Set : 16 entries of 32 bits\r
+reg\t\t[31:0]\tMVALID;\r
+\r
+assign\tADR_EQU\t= ({RADR[27:12],VADR_R[11:4]} == DRAM_A[27:4]);\t// Limited to 256 MB\r
+\r
+assign\tALT_DAT\t= AUX_ALT ? DFFE_IOR : CAPDAT ;\r
+\r
+assign\tRADR\t= VIRT_A ? MMU_Q[19:0] : VADR_R[31:12] ;\r
+\r
+assign\tADR_MX\t= PTE_MUX ? PTE_ADR : {RADR[27:12],VADR_R[11:2],USE_CA,CA_SET} ;\r
+\r
+assign\tKOLLI_A\t= DMA_MUX ? DMA_AA : DRAM_A[27:4] ;\r
+\r
+assign\tSET_DAT\t= CA_SET ? SET_DAT1 : SET_DAT0 ;\r
+\r
+assign\tVIRT_A\t= ~CINVAL[0] & VIRTUELL;\r
+\r
+assign\tUSER\t= ~MCR_FLAGS[3] & PSR_USER;\r
+\r
+assign\tDAT_SET\t= WRITE ? WRDATA : DRAM_Q ;\r
+\r
+assign\tBE_SET \t= ENBYTE | {~WRITE,~WRITE,~WRITE,~WRITE};\r
+\r
+assign\tADDR\t= KDET ? KOLLI_A : {RADR[27:12],VADR_R[11:4]} ;\r
+\r
+assign\tA_SET\t= WAMUX ? WADDR : VADR_R[11:2] ;\r
+\r
+assign\tTAGA\t= KOMUX ? KOLLI_A[11:4] : VADR[11:4] ;\r
+\r
+assign\tINIT_RUN = NEW_PTB_RUN | INIT_CA_RUN;\r
+\r
+assign\tLAST_MUX = AUX_ALT | AUX_DAT | AUX_QW;\r
+\r
+assign\tLAST_DAT = LAST_MUX ? ALT_DAT : SET_DAT ;\r
+\r
+assign\tLD_DRAM_A = ~(DRAM_ACC | PKEEP);\r
+\r
+assign\tACC_STAT[4] = IO_ACC;\r
+assign\tACC_STAT[5] = CA_HIT;\r
+\r
+always @(posedge BCLK)\r
+\tif (IO_ACC)\r
+\t\tbegin\r
+\t\t\tIO_BE <= ENBYTE;\r
+\t\t\tIO_DI <= WRDATA;\r
+\t\t\tIO_A  <= {RADR[31:12],VADR_R[11:0]};\r
+\t\tend\r
+\r
+always @(posedge BCLK) if (LD_DRAM_A) DRAM_A[27:0] <= ADR_MX[27:0];\r
+\r
+always @(posedge BCLK) if (IO_RD) DFFE_IOR <= IO_Q;\r
+\r
+always @(posedge BCLK)\r
+\tbegin\r
+\t\tDRAM_DI\t  <= {(PD_MUX ? PTE_DAT[19:16] : ENBYTE),WRDATA[31:16],\r
+\t\t\t\t\t  (PD_MUX ? PTE_DAT[15:0]  : WRDATA[15:0])};\r
+\t\tAUX_ALT\t  <= DFF_QWEXT | IO_RD;\r
+\t\tDFF_QWEXT <= IO_RD & SIZE[0] & SIZE[1];\r
+\t\tVADR_R\t  <= VADR;\r
+\tend\r
+\r
+always @(posedge MCLK) if (WCTRL[2]) CAPDAT <= DRAM_Q;\r
+\r
+// +++++++++++++++++++++++++  Cache Valid  +++++++++++++++++++\r
+\r
+always @(posedge BCLK) CVALID <= CA_VALID[TAGA[11:7]];\r
+\r
+always @(negedge BCLK) if (WE_CV) CA_VALID[WADR_CV] <= DAT_CV;\r
+\r
+// +++++++++++++++++++++++++  Tag Set 0  +++++++++++++++++++++\r
+\r
+always @(posedge BCLK) TAG0 <= TAGSET_0[TAGA];\r
+\r
+always @(negedge BCLK) if (WRCRAM0) TAGSET_0[VADR_R[11:4]] <= RADR[27:12];\r
+\r
+// +++++++++++++++++++++++++  Tag Set 1  +++++++++++++++++++++\r
+\r
+always @(posedge BCLK) TAG1 <= TAGSET_1[TAGA];\r
+\r
+always @(negedge BCLK) if (WRCRAM1) TAGSET_1[VADR_R[11:4]] <= RADR[27:12];\r
+\r
+// +++++++++++++++++++++++++  Data Set 0  ++++++++++++++++++++\r
+\r
+always @(posedge BCLK)\r
+\tbegin\r
+\t\tSET_DAT0[31:24]\t<= DATA0_D[VADR[11:2]];\r
+\t\tSET_DAT0[23:16]\t<= DATA0_C[VADR[11:2]];\r
+\t\tSET_DAT0[15:8]\t<= DATA0_B[VADR[11:2]];\r
+\t\tSET_DAT0[7:0]\t<= DATA0_A[VADR[11:2]];\r
+\tend\r
+\t\r
+always @(posedge MCLK)\r
+\tif (WRSET0)\r
+\t\tbegin\r
+\t\t\tif (BE_SET[3]) DATA0_D[A_SET] <= DAT_SET[31:24];\r
+\t\t\tif (BE_SET[2]) DATA0_C[A_SET] <= DAT_SET[23:16];\r
+\t\t\tif (BE_SET[1]) DATA0_B[A_SET] <= DAT_SET[15:8];\r
+\t\t\tif (BE_SET[0]) DATA0_A[A_SET] <= DAT_SET[7:0];\r
+\t\tend\r
+\t\t\r
+// +++++++++++++++++++++++++  Data Set 1  ++++++++++++++++++++\r
+\r
+always @(posedge BCLK)\r
+\tbegin\r
+\t\tSET_DAT1[31:24]\t<= DATA1_D[VADR[11:2]];\r
+\t\tSET_DAT1[23:16]\t<= DATA1_C[VADR[11:2]];\r
+\t\tSET_DAT1[15:8]\t<= DATA1_B[VADR[11:2]];\r
+\t\tSET_DAT1[7:0]\t<= DATA1_A[VADR[11:2]];\r
+\tend\r
+\t\r
+always @(posedge MCLK)\r
+\tif (WRSET1)\r
+\t\tbegin\r
+\t\t\tif (BE_SET[3]) DATA1_D[A_SET] <= DAT_SET[31:24];\r
+\t\t\tif (BE_SET[2]) DATA1_C[A_SET] <= DAT_SET[23:16];\r
+\t\t\tif (BE_SET[1]) DATA1_B[A_SET] <= DAT_SET[15:8];\r
+\t\t\tif (BE_SET[0]) DATA1_A[A_SET] <= DAT_SET[7:0];\r
+\t\tend\r
+\r
+DCACHE_SM\tDC_SM(\r
+\t.BCLK(BCLK),\r
+\t.BRESET(BRESET),\r
+\t.VIRTUELL(VIRTUELL),\r
+\t.IO_SPACE(IO_SPACE),\r
+\t.MDONE(MDONE),\r
+\t.MMU_HIT(MMU_HIT),\r
+\t.CA_HIT(CA_HIT),\r
+\t.READ(READ),\r
+\t.WRITE(WRITE),\r
+\t.ZTEST(ZTEST),\r
+\t.RMW(RMW),\r
+\t.QWATWO(QWATWO),\r
+\t.USE_CA(USE_CA),\r
+\t.PTB_WR(PTB_WR),\r
+\t.PTB_SEL(PTB_SEL),\r
+\t.SEL_PTB1(SEL_PTB1),\r
+\t.IO_READY(IO_READY),\r
+\t.USER(USER),\r
+\t.PROTECT(ACC_STAT[3]),\r
+\t.PROT_ERROR(PROT_ERROR),\r
+\t.ENWR(ENWR),\r
+\t.WB_ACC(WB_ACC),\r
+\t.ADR_EQU(ADR_EQU),\r
+\t.IC_PREQ(IC_PREQ),\r
+\t.CAPDAT(CAPDAT[31:0]),\r
+\t.CPU_OUT(DP_Q[59:44]),\r
+\t.FILLRAM(FILLRAM),\r
+\t.IC_VA(IC_VA),\r
+\t.ICTODC(ICTODC),\r
+\t.VADR_R(VADR_R[31:12]),\r
+\t.NEW_PTB(NEW_PTB),\r
+\t.PTB_ONE(PTB_ONE),\r
+\t.DRAM_ACC(DRAM_ACC),\r
+\t.DRAM_WR(DRAM_WR),\r
+\t.IO_ACC(IO_ACC),\r
+\t.IO_RD(IO_RD),\r
+\t.IO_WR(IO_WR),\r
+\t.PTE_STAT(PTE_STAT),\r
+\t.ABORT(ACC_STAT[1]),\r
+\t.WR_MRAM(WR_MRAM),\r
+\t.CUPDATE(CUPDATE),\r
+\t.AUX_DAT(AUX_DAT),\r
+\t.PTE_MUX(PTE_MUX),\r
+\t.ACC_OK(ACC_STAT[0]),\r
+\t.ABO_LEVEL1(ACC_STAT[2]),\r
+\t.IACC_STAT(IACC_STAT),\r
+\t.KOMUX(KOMUX),\r
+\t.KDET(KDET),\r
+\t.HIT_ALL(HIT_ALL),\r
+\t.DMA_MUX(DMA_MUX),\r
+\t.HLDA(HLDA),\r
+\t.RWVAL(RWVAL[1:0]),\r
+\t.RWVFLAG(RWVFLAG),\r
+\t.IC_SIGS(IC_SIGS),\r
+\t.MMU_DIN(MMU_DIN),\r
+\t.PD_MUX(PD_MUX),\r
+\t.PKEEP(PKEEP),\r
+\t.PTE_ADR(PTE_ADR),\r
+\t.PTE_DAT(PTE_DAT));\r
+\r
+CA_MATCH\tDCA_COMPARE(\r
+\t.INVAL_L(CINVAL[0]),\r
+\t.CI(CI),\r
+\t.MMU_HIT(MMU_HIT),\r
+\t.WRITE(WRITE),\r
+\t.KDET(KDET),\r
+\t.ADDR(ADDR),\r
+\t.CFG(CFG),\r
+\t.ENDRAM(ENDRAM),\r
+\t.CVALID(CVALID),\r
+\t.TAG0(TAG0),\r
+\t.TAG1(TAG1),\r
+\t.CA_HIT(CA_HIT),\r
+\t.CA_SET(CA_SET),\r
+\t.WB_ACC(WB_ACC),\r
+\t.USE_CA(USE_CA),\r
+\t.IOSEL(RADR[31:28]),\r
+\t.IO_SPACE(IO_SPACE),\r
+\t.KILL(KILL),\r
+\t.DC_ILO(RWVAL[2]),\r
+\t.UPDATE(UPDATE_C));\r
+\r
+DCA_CONTROL\tDCA_CTRL(\r
+\t.BCLK(BCLK),\r
+\t.MCLK(MCLK),\r
+\t.BRESET(BRESET),\r
+\t.CA_SET(CA_SET),\r
+\t.HIT_ALL(HIT_ALL),\r
+\t.UPDATE(UPDATE_C),\r
+\t.VADR_R(ADDR[11:7]),\r
+\t.DRAM_ACC(DRAM_ACC),\r
+\t.CUPDATE(CUPDATE),\r
+\t.KILL(KILL),\r
+\t.WRITE(WRITE),\r
+\t.WRCFG(WRCFG),\r
+\t.WCTRL(WCTRL[1:0]),\r
+\t.INVAL_A(CINVAL[1]),\r
+\t.DAT_CV(DAT_CV),\r
+\t.WADR_CV(WADR_CV),\r
+\t.WE_CV(WE_CV),\r
+\t.INIT_CA_RUN(INIT_CA_RUN),\r
+\t.WRCRAM0(WRCRAM0),\r
+\t.WRCRAM1(WRCRAM1),\r
+\t.WRSET0(WRSET0),\r
+\t.WRSET1(WRSET1));\r
+\r
+MMU_MATCH\tMMU_COMPARE(\r
+\t.USER(USER),\r
+\t.WRITE(WRITE),\r
+\t.READ(READ),\r
+\t.RMW(RMW),\r
+\t.IVAR(IVAR),\r
+\t.MCR_FLAGS(MCR_FLAGS[2:0]),\r
+\t.MMU_VA(MMU_Q[35:20]),\r
+\t.MVALID(MVALID),\r
+\t.VADR_R(VADR_R[31:12]),\r
+\t.MMU_HIT(MMU_HIT),\r
+\t.PROT_ERROR(PROT_ERROR),\r
+\t.VIRTUELL(VIRTUELL),\r
+\t.CI(CI),\r
+\t.SEL_PTB1(SEL_PTB1),\r
+\t.UPDATE(UPDATE_M));\r
+\r
+MMU_UP\tMMU_CTRL(\r
+\t.BCLK(BCLK),\r
+\t.BRESET(BRESET),\r
+\t.NEW_PTB(NEW_PTB),\r
+\t.IVAR(IVAR[1]),\r
+\t.PTB1(PTB_ONE),\r
+\t.WR_MRAM(WR_MRAM),\r
+\t.MVALID(MVALID),\r
+\t.UPDATE(UPDATE_M),\r
+\t.VADR(VADR[19:16]),\r
+\t.VADR_R(VADR_R[19:16]),\r
+\t.WE_MV(WEMV),\r
+\t.NEW_PTB_RUN(NEW_PTB_RUN),\r
+\t.DAT_MV(DAT_MV),\r
+\t.RADR_MV(RADR_MV),\r
+\t.WADR_MV(WADR_MV));\r
+\r
+// +++++++++++++++++++++++++  MMU Valid  +++++++++++++++++++++\r
+\r
+always @(posedge BCLK) MVALID <= MMU_VALID[RADR_MV];\r
+\r
+always @(negedge BCLK) if (WEMV) MMU_VALID[WADR_MV] <= DAT_MV;\r
+\r
+// +++++++++++++++++++++++++  MMU Tags  ++++++++++++++++++++++\r
+\r
+always @(posedge BCLK) MMU_Q <= MMU_TAGS[VADR[19:12]];\r
+\r
+always @(negedge BCLK) if (WR_MRAM) MMU_TAGS[VADR_R[19:12]] <= {VADR_R[31:20],MMU_DIN[23:0]};\r
+\r
+RD_ALIGNER\tRD_ALI(\r
+\t.BCLK(BCLK),\r
+\t.ACC_OK(ACC_STAT[0]),\r
+\t.REG_OUT(REG_OUT),\r
+\t.PACKET(PACKET),\r
+\t.RDDATA(LAST_DAT),\r
+\t.SIZE(SIZE),\r
+\t.CA_HIT(CA_HIT),\r
+\t.DP_DI(DP_DI),\r
+\t.AUX_QW(AUX_QW));\r
+\r
+WR_ALIGNER\tWR_ALI(\r
+\t.DP_Q(DP_Q),\r
+\t.PACKET(PACKET),\r
+\t.SIZE(SIZE),\r
+\t.ENBYTE(ENBYTE),\r
+\t.WRDATA(WRDATA));\r
+\t\r
+DEBUG_AE DBGAE(\r
+\t.DBG_IN(DBG_IN),\r
+\t.READ(READ),\r
+\t.WRITE(WRITE),\r
+\t.USER(USER),\r
+\t.VIRTUELL(VIRTUELL),\r
+\t.ACC_OK(ACC_STAT[0]),\r
+\t.VADR_R(VADR_R[31:2]),\r
+\t.MMU_Q(MMU_Q[19:0]),\r
+\t.ENBYTE(ENBYTE),\r
+\t.DBG_HIT(DBG_HIT));\r
+\r
+endmodule\r
+"
+"// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+// This file is part of the M32632 project\r
+// http://opencores.org/project,m32632\r
+//\r
+// Filename: DECODER.v\r
+// Version:  1.1 bug fix\r
+// History:  1.0 first release of 30 Mai 2015\r
+// Date:     21 January 2016\r
+//\r
+// Copyright (C) 2016 Udo Moeller\r
+// \r
+// This source file may be used and distributed without \r
+// restriction provided that this copyright statement is not \r
+// removed from the file and that any derivative work contains \r
+// the original copyright notice and the associated disclaimer.\r
+// \r
+// This source file is free software; you can redistribute it \r
+// and/or modify it under the terms of the GNU Lesser General \r
+// Public License as published by the Free Software Foundation;\r
+// either version 2.1 of the License, or (at your option) any \r
+// later version. \r
+// \r
+// This source is distributed in the hope that it will be \r
+// useful, but WITHOUT ANY WARRANTY; without even the implied \r
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR \r
+// PURPOSE. See the GNU Lesser General Public License for more \r
+// details. \r
+// \r
+// You should have received a copy of the GNU Lesser General \r
+// Public License along with this source; if not, download it \r
+// from http://www.opencores.org/lgpl.shtml \r
+// \r
+// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\tModules contained in this file:\r
+//\tDECODER\t\tInstruction Decoding and Flow Control\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+module DECODER ( BCLK, BRESET, INT_N, NMI_N, ANZ_VAL, OPREG, CFG, PSR, ACC_DONE, DC_ABORT, IC_ABORT, ACB_ZERO, DONE,\r
+\t\t\t\t PC_SAVE, STRING, INIT_DONE, ILL, UNDEF, TRAPS, IC_READ, STOP_CINV,\r
+\t\t\t\t GENSTAT, DISP, IMME_Q, DISP_BR, USED, NEW, LOAD_PC, NEXT_PCA, RDAA, RDAB, OPER, START, LD_OUT, LD_DIN, LD_IMME,\r
+\t\t\t\t INFO_AU, ACC_FELD, WREN, WRADR, WMASKE, WR_REG, DETOIP, MMU_UPDATE, RESTART, STOP_IC, RWVAL, ENA_HK, ILO, COP_OP );\r
+\r
+\tinput\t\t\tBCLK,BRESET;\r
+\tinput\t\t\tINT_N,NMI_N;\t// external inputs\r
+\tinput\t [2:0]\tANZ_VAL;\r
+\tinput\t[55:0]\tOPREG;\t\t\t// the OPREG contains the bytes to decode, OPREG[55:32] are don\'t care\r
+\tinput\t [8:0]\tCFG;\t\t\t// CONFIG : many bits are don\'t-care\r
+\tinput\t[11:0]\tPSR;\r
+\tinput\t\t\tACC_DONE;\r
+\tinput\t\t\tDC_ABORT,IC_ABORT;\r
+\tinput\t\t\tACB_ZERO;\r
+\tinput\t\t\tDONE;\r
+\tinput\t[31:0]\tPC_SAVE;\r
+\tinput\t [4:0]\tSTRING;\r
+\tinput\t\t\tINIT_DONE;\r
+\tinput\t\t\tILL,UNDEF;\r
+\tinput\t [5:0]\tTRAPS;\r
+\tinput\t\t\tIC_READ;\r
+\tinput\t\t\tSTOP_CINV;\t\t// not to mix it up with STOP_IC\r
+\t\r
+\toutput\t [2:0]\tGENSTAT;\r
+\toutput\t[31:0]\tDISP,IMME_Q,DISP_BR;\t// three main data busses : Displacement, Immediate and Displacement for Branch\r
+\toutput\t [2:0]\tUSED;\r
+\toutput\t\t\tNEW;\r
+\toutput\t\t\tLOAD_PC;\r
+\toutput\t\t\tNEXT_PCA;\r
+\toutput\t [7:0]\tRDAA,RDAB;\r
+\toutput\t[10:0]\tOPER;\r
+\toutput\t [1:0]\tSTART,LD_OUT;\r
+\toutput\t\t\tLD_DIN,LD_IMME;\r
+\toutput\t [6:0]\tINFO_AU;\r
+\toutput\t[14:0]\tACC_FELD;\r
+\toutput\t\t\tWREN;\r
+\toutput\t [5:0]\tWRADR;\r
+\toutput\t [1:0]\tWMASKE;\r
+\toutput\treg\t\tWR_REG;\r
+\toutput\t[12:0]\tDETOIP;\r
+\toutput\t [1:0]\tMMU_UPDATE;\r
+\toutput\t\t\tRESTART;\r
+\toutput\t\t\tSTOP_IC;\r
+\toutput\t [2:0]\tRWVAL;\r
+\toutput\t\t\tENA_HK;\r
+\toutput\treg\t\tILO;\r
+\toutput\t[23:0]\tCOP_OP;\r
+\t\r
+\treg\t\t[31:0]\tDISP,disp_val;\r
+\treg\t\t[10:0]\toper_i;\r
+\treg\t\t [2:0]\tUSED;\r
+\treg\t\t[14:0]\tACC_FELD;\r
+\treg\t\t [1:0]\tldoreg;\r
+\treg\t\t\t\twren_i;\r
+\treg\t\t [5:0]\twradr_i;\r
+\treg\t\t [1:0]\twmaske_i;\r
+\treg\t\t [1:0]\tSTART;\r
+\treg\t\t[23:0]\tCOP_OP;\r
+\treg\t\t\t\tspupd_i;\r
+\treg\t\t [3:0]\tdisp_sel;\r
+\treg\t\t[52:0]\top1_feld;\r
+\treg\t\t[47:0]\top2_feld;\r
+\treg\t\t[47:0]\top3_feld;\r
+\treg\t\t[47:0]\top_feld_reg;\r
+\treg\t\t[31:0]\timme_i;\r
+\treg\t\t [2:0]\tvalid;\r
+\treg\t\t [7:0]\tphase_reg;\r
+\treg\t\t [3:0]\tdi_stat;\t// Displacement Status\r
+\treg\t\t [3:0]\tcc_feld;\r
+\treg\t\t [1:0]\tex_br_op;\r
+\treg\t\t\t\tacb_reg;\r
+\treg\t\t\t\tjsr_flag;\r
+\treg\t\t [8:0]\twaitop,wait_reg;\r
+\treg\t\t\t\tbranch;\r
+\treg\t\t [3:0]\tdim_feld;\r
+\treg\t\t[66:0]\tnew_op;\r
+\treg\t\t\t\tshort_op_reg;\r
+\treg\t\t[15:0]\tidx_reg;\r
+\treg\t\t[35:0]\tgen_src1;\r
+\treg\t\t[33:0]\tgen_src2;\r
+\treg\t\t\t\tqw_flag;\r
+\treg\t\t\t\tlong_reg;\r
+\treg\t\t\t\tnew_spsel;\r
+\treg\t\t\t\ts_user,old_su;\r
+\treg\t\t [1:0]\tstack_sel;\t// Stack select for USER and SUPERVISOR\r
+\treg\t\t [1:0]\ts_mod;\t\t// Modifier for Stack select\r
+\treg\t\t\t\tupd_info,dw_info;\r
+\treg\t\t [2:0]\trpointer;\r
+\treg\t\t [5:0]\tresto;\t\t// for RESTORE\r
+\treg\t\t\t\tinit_rlist;\r
+\treg\t\t\t\tnew_fp;\r
+\treg\t\t\t\tformat1;\r
+\treg\t\t\t\tldpc_phase;\r
+\treg\t\t\t\treti_flag;\r
+\treg\t\t\t\tno_t2p;\r
+\treg\t\t\t\tiabort,ia_save;\r
+\treg\t\t\t\tmmu_sel;\r
+\treg\t\t [1:0]\tnmi_reg;\r
+\treg\t\t\t\tnmi_flag,int_flag;\r
+\treg\t\t\t\ttype_nmi;\r
+\treg\t\t [3:0]\texc_vector;\r
+\treg\t\t\t\tphase_exc;\r
+\treg\t\t [3:0]\tovf_pipe;\r
+\treg\t\t\t\tdbg_s,dbg_trap,dbg_en,addr_cmp;\r
+\treg\t\t\t\tssrc_flag,sdest_flag;\r
+\treg\t\t\t\top_setcfg,setcfg_lsb;\r
+\treg\t\t\t\tinss_op;\r
+\treg\t\t\t\texin_cmd,extract;\t// EXT/INS\r
+\treg\t\t\t\tbit_reg;\t// Flag for Bit opcodes : Source2 = Reg\r
+\treg\t\t\t\tkurz_st;\t// Flag for MOVM/CMPM\r
+\treg\t\t\t\tkill_opt;\t// Flag for optimized MOVS\r
+\treg\t\t\t\tcmps_flag;\t// Flag for CMPS\r
+\treg\t\t\t\tskps_flag;\t// Flag for SKPS\r
+\treg\t\t\t\tmt_flag;\t// Flag for Match and Translate\r
+\treg\t\t\t\tspu_block;\t// block of SP update at Long operation\r
+\treg\t\t\t\tdia_op,dia_flag;\t// Flag for DIA\r
+\treg\t\t\t\tm_ussu,m_usel,dc_user;\t// MOVUS/SU\r
+\treg\t\t\t\trwval_flag,wrval_flag;\t// RDVAL/WRVAL\r
+\treg\t\t\t\tcinv_flag;\t// Flag for CINV\r
+\treg\t\t [5:0]\tlmrreg;\r
+\treg\t\t\t\tno_init,a_ivar;\r
+\treg\t\t\t\tindex_cmd;\r
+\treg\t\t\t\tstop_d;\r
+\treg\t\t\t\tdc_ilo;\r
+\t\r
+\twire\t\t\tPHASE_0;\r
+\twire\t [7:0]\tphase_ein;\t// Phase after ABORT has changed the content to 0\r
+\twire\t\t\tde_flag,ivec_flag;\r
+\twire\t\t\tnext;\r
+\twire\t[18:0]\tnew_addr,pop_fp,save_pc;\r
+\twire\t[13:0]\tnew_regs;\r
+\twire\t [7:0]\tnew_ph,ppfp;\r
+\twire\t [7:0]\tnew_nx;\r
+\twire\t\t\top_1byte,op_12byte,op_2byte,op_3byte;\r
+\twire\t\t\tjump;\r
+\twire\t\t\tshort_op,short_def;\r
+\twire\t\t\tacb_op,acb_flag;\r
+\twire\t\t\tzero,carry_psr,negativ,larger,flag;\r
+\twire\t\t\tvalid_size;\r
+\twire\t\t\top_ok;\r
+\twire\t\t\tstop;\r
+\twire\t[47:0]\topc_bits;\r
+\twire\t[47:0]\top_feld;\r
+\twire\t [2:0]\tatys,atyd;\r
+\twire\t [3:0]\tauop_s,auop_d;\r
+\twire\t\t\tlong,src2_flag,dest_flag;\r
+\twire\t [6:0]\tsrc_1,src_2,src_1l,src_2l;\r
+\twire\t [1:0]\tsrc1_le,src2_le;\r
+\twire\t\t\tacc1,acc2;\r
+\twire\t\t\tspupd;\r
+\twire\t [6:0]\tsaver;\t// for SAVE\r
+\twire\t [2:0]\treg_nr;\r
+\twire\t\t\tsave_reg;\r
+\twire\t\t\tld_disp,disp_ok;\r
+\twire\t\t\tstore_pc;\r
+\twire\t\t\tdo_xor;\r
+\twire\t\t\tdo_long;\r
+\twire\t [1:0]\tidx_n,n_idx;\r
+\twire\t\t\tidx;\r
+\twire\t [1:0]\totype;\r
+\twire\t[10:0]\topera,op_str,op_sho;\r
+\twire\t [5:0]\tdest_r,dest_rl;\r
+\twire\t\t\tphase_idx;\r
+\twire\t[15:0]\tidx_bytes,idx_feld;\r
+\twire\t [3:0]\tidx_1,idx_2;\r
+\twire\t [4:0]\tsrc1_addr,src2_addr;\r
+\twire\t [6:0]\tusp_1,usp_2;\r
+\twire\t[33:0]\ttos_oper;\r
+\twire\t[18:0]\tadrd1,exr11,exr12,adrd2,adwr2,exr22,exw22,re_wr,st_src,st_src2,st_dest,st_len,st_trde,st_trs2;\r
+\twire\t [7:0]\tphrd1,phrd2,phwr2;\r
+\twire\t [6:0]\trega1,irrw1,rega2,irrw2;\r
+\twire\t [3:0]\tnxrd1,nxrw2;\r
+\twire\t\t\trmw;\r
+\twire\t [6:0]\tquei1,quet1;\t\t// Registeradr\r
+\twire\t [7:0]\tendea,goacb,dowait;\t// Phase\r
+\twire\t [3:0]\tdiacb;\t\t\t\t// DIMM access\r
+\twire\t\t\tqword;\r
+\twire\t [6:0]\tstack,no_modul,ttstak;\r
+\twire\t[12:0]\tpop_1;\r
+\twire\t\t\tmpoi_1,mpoi_2;\r
+\twire\t [1:0]\tsrc1_tos;\t\t// the code for REUSE is 2\'b11\r
+\twire\t\t\tsvc_flag,bpt_flag,flag_flag,trac_flag;\r
+\twire\t [3:0]\tmisc_vectors;\r
+\twire\t [2:0]\tpsr_code;\r
+\twire\t\t\texception;\r
+\twire\t\t\tinterrupt;\r
+\twire\t\t\tabort;\t\t// DC_ABORT | iabort;\r
+\twire\t\t\tabo_int;\r
+\twire\t\t\tiabo_fall;\r
+\twire\t\t\tabbruch,fpu_trap,dvz_trap;\r
+\twire\t\t\tabbruch2;\r
+\twire\t\t\tdbg_flag;\r
+\twire\t\t\tovf_op,ovf2_op,ovf_flag;\r
+\twire\t\t\tpc_match;\r
+\twire\t\t\tno_trap;\r
+\twire\t[10:0]\top_psr,op_scp;\r
+\twire\t[30:0]\tai_next;\r
+\twire\t\t\tset_src,set_dest,clr_sflag;\r
+\twire\t [7:0]\trrepa;\t// Repair Phase of Abort for String opcodes\r
+\twire\t [7:0]\tph_str;\t// working phase String\r
+\twire\t\t\tph_match;\r
+\twire\t\t\tt2p;\r
+\twire\t\t\trw_bit,op_ilo;\r
+\twire\t\t\tsetcfg;\r
+\twire\t\t\tstring_ende;\r
+\twire\t\t\twlor;\t// Flag to generate WR_REG signal\r
+\twire\t [5:0]\twstr0,wstr1,wstr2;\r
+\twire\t [6:0]\trstr0,rstr1,rstr2;\r
+\twire\t\t\trett_exc;\r
+\twire\t\t\tchk_rmw;\r
+\r
+\t// Variables for 2- and 3-Byte Dekoder :\r
+\treg\t\t [5:0]\thzr_c;\t// CASE Statement\r
+\twire\t [1:0]\thzl_a;\r
+\twire\t [2:0]\thzl_b;\r
+\twire\t [5:0]\thzr_a,hzr_b,hzr_s;\r
+\twire\t\t\thdx_a;\r
+\twire\t\t\thdo_b;\r
+\twire\t [3:0]\thdo_a,hdo_c,hdo_e;\r
+\twire\t [7:0]\thdo_d;\r
+\twire\t [1:0]\thdl_b,hdl_d,hdl_f,hdl_g,hdl_h;\r
+\twire\t [2:0]\thdl_a,hdl_c,hdl_e;\r
+\twire\t [5:0]\thdr_a,hdr_b,hdr_c,hdr_d,hdr_e,hdr_f,hdr_g,hdr_m;\r
+\t\r
+\twire\t[66:0]\tstate_0,state_group_50,state_group_60;\t// for the Gruppe 2 opcodes\r
+\t\r
+\t// Address field : Size:2 RD WR LDEA FULLACC INDEX:4 SPUPD disp_val:4 POST CLRMSW SRC2SEL:2\r
+\t\r
+\tparameter addr_nop\t= 19\'b10_0000_0000_0_0000_0000;\t// all parameter to 0\r
+\tparameter push_op\t= 19\'b10_0111_0000_1_1010_0000;\t// i.e. for BSR, ENTER ...\r
+\tparameter push_ea\t= 19\'b10_0111_0000_1_1010_0011;\t// SAVE middle\r
+\tparameter pop_op\t= 19\'b10_1011_0010_1_0000_1000;\t// RET/RESTORE\r
+\tparameter adddisp\t= 19\'b10_0010_0000_0_0000_0011;\t// for RET : reuse of EA\r
+\tparameter adddispn\t= 19\'b10_0010_0000_0_0000_0000;\t// for RETT : add Disp to Stack\r
+\tparameter save_sp\t= 19\'b10_0000_0000_1_0000_0000;\t// u.a. RET : update of Stack\r
+\tparameter next_po\t= 19\'b10_1011_0010_1_0000_1011;\t// RESTORE middle\r
+\tparameter dispmin\t= 19\'b10_0010_0000_0_0100_0011;\t// Reuse for ENTER\r
+\tparameter rmod_rxp\t= 19\'b10_1001_0000_1_0000_0100;\t// MODUL+0 read : SB , SP Update , therefore no LDEA\r
+\tparameter rmod_rtt\t= 19\'b10_1001_0000_0_0000_0100;\t// MODUL+0 read : SB , no LDEA\r
+\tparameter rmod_4\t= 19\'b10_1011_0000_0_0001_0100;\t// MODUL+4 read : Link Table Base\r
+\tparameter rmod_8\t= 19\'b10_1011_0000_0_0010_0100;\t// MODUL+8 read : Program Base\r
+\tparameter rdltab\t= 19\'b10_1010_0000_0_1000_0000;\t// Link table read - EA Phase\r
+\tparameter ea_push\t= 19\'b10_0110_0000_0_1010_0011;\t// CXP : 2. Push EA Phase\r
+\tparameter ea_min8\t= 19\'b10_1010_0000_0_1011_0011;\t// CXP : reuse of MOD+8\r
+\tparameter pop_ru\t= 19\'b10_1010_0010_0_0000_1011;\t// RXP : EA Phase MOD POP\r
+\tparameter rd_icu\t= 19\'b00_1001_0000_0_1100_0010;\t// Read ICU : Byte of fix address\r
+\tparameter get_vec\t= 19\'b10_1001_0000_0_01xx_0000;\t// Read Exception-Vector : Index Exception No.\r
+\tparameter get_veci\t= 19\'b10_1001_0110_0_0000_0000;\t// Read Exception-Vector : Index external Interrupt\r
+\tparameter load_ea\t= 19\'b10_0010_0000_0_0000_0000;\t// used for store of TEAR and MSR\r
+\tparameter save_msr\t= 19\'b10_0010_0001_0_0000_0000;\t// used for store of TEAR and MSR\r
+\tparameter ivar_adr\t= 19\'b10_0000_0100_0_0000_0010;\t// only pass SRC1\r
+\tparameter st_trans\t= 19\'b00_1001_0100_0_0000_0000;\t// Translate at String : SRC1 + SRC2 , Byte\r
+\tparameter src_x\t\t= 7\'hxx;\r
+\tparameter dest_x\t= 6\'hxx;\r
+\tparameter imme\t\t= {1\'b1,6\'hxx};\r
+\tparameter frame\t\t= 7\'h18;\r
+\tparameter ibase\t\t= 7\'h1E;\r
+\tparameter modul\t\t= 7\'h1F;\r
+\tparameter w_msr\t\t= 6\'h0A;\r
+\tparameter w_tear\t= 6\'h0B;\r
+\tparameter fsr_r\t\t= 6\'h17;\t// not defined register for FSR for opcodes LFSR and SFSR\r
+\tparameter temp_l\t= 6\'h3C;\r
+\tparameter temp_h\t= 6\'h3D;\t// second last space for 8B TEMP register\r
+\tparameter temp_1\t= 6\'h3E;\t// Backup for register at String operations\r
+\tparameter temp_2\t= 6\'h3F;\r
+\tparameter rtmpl\t\t= 7\'h3C;\r
+\tparameter rtmph\t\t= 7\'h3D;\r
+\tparameter rtmp1\t\t= 7\'h3E;\r
+\tparameter rtmp2\t\t= 7\'h3F;\r
+\tparameter op_mov\t= 11\'h345;\r
+\tparameter op_adr\t= 11\'h349;\r
+\tparameter op_add\t= 11\'h340;\t// for CXP\r
+\tparameter op_flip\t= 11\'h364;\t// for CXP : LSHD -16,Ri\r
+\tparameter op_lmr\t= 11\'h36A;\t// for LPR CFG, LMR and CINV\r
+\tparameter op_wrp\t= 11\'h387;\t// for CXP : write PSR , used also for Exception processing\r
+\tparameter op_ldp\t= 11\'h388;\t// for RETT and RETI : load of PSR from Stack\r
+\tparameter op_zex\t= 11\'h076;\t// Zero Extension for ICU Vector - is also used at String Option ""T""\r
+\tparameter op_cop\t= 8\'hDD;\t// Coprozessor Opcode\r
+\t\r
+\t// ++++++++++++++++++++++++++  The switch logic for the state machine  +++++++++++++++++++++++++++++\r
+\t\r
+\talways @(ANZ_VAL)\r
+\t\tcase (ANZ_VAL)\r
+\t\t  3\'d0  : valid = 3\'b000;\r
+\t\t  3\'d1  : valid = 3\'b001;\r
+\t\t  3\'d2  : valid = 3\'b011;\r
+\t\tdefault : valid = 3\'b111;\r
+\t\tendcase\r
+\r
+\tassign next = ( PHASE_0 ? op_ok :\t\t// Opcode decoded or Exception processed\r
+\t\t\t\t\t\t// Displacement or Immediate operand and external memory access can happen in parallel\r
+\t\t\t\t\t\t// i.e. addressing mode Memory Relative\r
+\t\t\t\t    (  ((~dim_feld[0] | ACC_DONE) & (~dim_feld[3] | di_stat[0]))\t// ACC_DONE resets dim_feld\r
+\t\t\t\t\t\t// long operation\r
+\t\t\t\t     & ~(long_reg & ~DONE) ) )\r
+\t\t\t\t\t\t// hard break : abort or fpu_trap or dvz_trap or ovf_flag\r
+\t\t\t\t  | abbruch ;\r
+\t\t\t\t  \r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) long_reg <= 1\'b0;\r
+\t\t  else\r
+\t\t\tlong_reg <= next ? do_long : long_reg;\t// START[1]\r
+\t\r
+\talways @(posedge BCLK or negedge BRESET)\t// the central phase register\r
+\t\tif (!BRESET) phase_reg <= 8\'h0;\r
+\t\t  else\r
+\t\t\tif (next) phase_reg <= new_op[47:40];\r
+\t\t\t\r
+\talways @(*)\t// next switch of micro program counter\r
+\t\tcasex ({PHASE_0,op_ok,dim_feld[3],di_stat[0]})\r
+\t\t  4\'b11_xx : USED = {1\'b0,~op_1byte,(op_1byte | op_3byte)};\r
+\t\t  4\'b0x_11 : USED = di_stat[3:1];\r
+\t\t  default  : USED = 3\'d0;\r
+\t\tendcase\r
+\t\r
+\t// Special phases\r
+\t\r
+\tassign PHASE_0 = (phase_reg == 8\'h00);\t// During Phase 0 the opcode is decoded\r
+\t\r
+\tassign NEXT_PCA = PHASE_0 & ~ovf_flag & ~dbg_flag;\r
+\t\r
+\t// Pulse to transfer from Trace Bit to Pending Trace Bit, only once in the beginning of phase 0\r
+\t// The priority is such that a TRACE exception is served before an UNDEFINED/ILLEGAL exception\r
+\talways @(posedge BCLK) no_t2p <= PHASE_0 & ~op_ok;\r
+\tassign t2p = PHASE_0 & ~no_t2p;\t// signal to I_PFAD\r
+\t\r
+\t// ++++++++++++++++++++++++++  global control signals  ++++++++++++++++\r
+\t\r
+\tassign de_flag   = CFG[8];\r
+\tassign ivec_flag = CFG[0];\r
+\tassign dvz_trap  = TRAPS[1];\r
+\tassign fpu_trap  = TRAPS[0];\r
+\t\r
+\talways @(posedge BCLK) nmi_reg\t<= {nmi_reg[0],NMI_N};\t// one clock sync and than falling edge detection\r
+\t\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) nmi_flag <= 1\'b0;\r
+\t\t  else nmi_flag <= (nmi_reg == 2\'b10) | (nmi_flag & ~(phase_reg == 8\'h82));\r
+\t\t  \r
+\talways @(posedge BCLK) int_flag <= PSR[11] & ~INT_N;\t// one clock to synchronise\r
+\t\r
+\tassign stop\t\t = (int_flag | nmi_flag) &   PHASE_0 & ~stop_d;\t\t// neccesary if FPU_TRAP and INT at the same time\r
+\tassign interrupt = (int_flag | nmi_flag) & (~PHASE_0 |  stop_d);\r
+\t\r
+\talways @(posedge BCLK or negedge BRESET) \r
+\t\tif (!BRESET) stop_d <= 1\'d0;\r
+\t\t  else stop_d <= stop;\r
+\t\r
+\t// ++++++++++++++++++++++++++  Exception processing  +++++++++++++++\r
+\t\r
+\t// IC_ABORT is valid if Opcode Decoder cannot continue\r
+\tassign iabo_fall = IC_ABORT & (PHASE_0 ? ~op_ok : (~di_stat[0] & dim_feld[3]));\r
+\t\r
+\talways @(posedge BCLK) iabort  <= iabo_fall & ~ia_save;\t// DC_ABORT ist a pulse\r
+\talways @(posedge BCLK) ia_save <= iabo_fall;\r
+\t\r
+\t// mmu_sel is used in ADDR_UNIT\r
+\talways @(posedge BCLK) mmu_sel <= DC_ABORT | (mmu_sel & ~iabort);\t// 1 = DCACHE , 0 = ICACHE\r
+\tassign MMU_UPDATE[0] = mmu_sel;\r
+\t\r
+\tassign abort = DC_ABORT | iabort;\r
+\t\r
+\t// that is the end of String loops where interrupts are checked : 8\'hC7 & 8\'hCF\r
+\tassign string_ende = (phase_reg[7:4] == 4\'hC) & (phase_reg[2:0] == 3\'b111);\t// attention : 8\'hCF does not exist\r
+\r
+\talways @(posedge BCLK) if (PHASE_0 || string_ende) type_nmi <= nmi_flag;\t// during processing kept stable\r
+\t\r
+\tassign svc_flag  = (OPREG[7:0] == 8\'hE2) & valid[0];\t// Vector  5 : 0101 , Illegal Vector  4 : 0100\r
+\tassign bpt_flag  = (OPREG[7:0] == 8\'hF2) & valid[0];\t// Vector  8 : 1000 , Undefined Vec. 10 : 1010\r
+\tassign flag_flag = (phase_reg  == 8\'h89) & flag;\t\t// Vector  7 - has an own state\r
+\tassign trac_flag = t2p & PSR[10];\t\t\t\t\t\t// Vector  9 : 1001 , PSR[10] = P Bit , Pending Trace\r
+\tassign ovf_flag  = (ovf_pipe[3] & flag) | (ovf_pipe[1] & TRAPS[2]);\t\t// Vector 13 : 1101\r
+\tassign dbg_flag  = dbg_trap | (dbg_s & PHASE_0);\t\t// Vector 14 : 1110\r
+\t\r
+\t// abort + dvz_trap during a opcode, fpu_trap + ovf_flag + dbg_flag later\r
+\tassign abbruch  = abort | fpu_trap | dvz_trap | ovf_flag | dbg_flag;\t// this 5 stop everything\r
+\tassign abbruch2 = abort | fpu_trap | dvz_trap | ovf_flag;\t// for exc_vector generation\r
+\t\r
+\t// forces the next step of state machine (op_ok), generates otype=""11"" for Trap Service\r
+\tassign exception = interrupt | svc_flag | bpt_flag | ILL | UNDEF | trac_flag | abbruch;\t\r
+\t\r
+\t// a TRACE Exception is done before the opcode execution\r
+\tassign misc_vectors = trac_flag ? 4\'h9 : {(bpt_flag | UNDEF),(svc_flag | ILL),UNDEF,svc_flag};\t// the vectors are exclusiv\r
+\t\r
+\talways @(posedge BCLK)\r
+\t\tif (PHASE_0 || abbruch)\t// ABORTs, fpu_trap, dvz_trap + ovf_flag can happen every time\r
+\t\t  begin\r
+\t\t\texc_vector <= abbruch ? (abbruch2  ? {ovf_flag,(dvz_trap | ovf_flag),~ovf_flag,(fpu_trap | ovf_flag)} : 4\'hE)\r
+\t\t\t\t\t\t\t\t  : (interrupt ? {3\'b0,nmi_flag} : misc_vectors);\t// misc_vectors is default\r
+\t\t  end\r
+\t\t  else\r
+\t\t    if (flag_flag) exc_vector <= 4\'h7;\t// FLAG-Trap\r
+\t\t      else\r
+\t\t\t\tif (interrupt && string_ende) exc_vector <= {3\'b0,nmi_flag};\r
+\t\t  \r
+\tassign psr_code[2] = ~psr_code[1];\t\t\t\t\t\t// Absicht : codiert das Sichern des PSR bei Exception-Entry \r
+\tassign psr_code[1] = abort | ILL | UNDEF | trac_flag;\t// enable for reseting the P-Bit during write of PSR to stack\r
+\tassign psr_code[0] = (interrupt & ~fpu_trap) | abort;\t// enable for reseting the I-Bit of new PSR\r
+\r
+\t// valid codes are x\'89 to x\'8F\r
+\tassign op_psr = {8\'b0_00_1000_1,psr_code};\t// is used during first clock cylce after exception, is transfered as OPCODE to I_PFAD\r
+\t\r
+\t// Specialitiies : ABORT stores address & flags , the Interrrupts read vectors : all is used in big CASE\r
+\tassign abo_int = (exc_vector == 4\'h2) | (exc_vector[3:1] == 3\'b000);\r
+\tassign ai_next = (exc_vector == 4\'h2) ? {load_ea,8\'h84,4\'h0} : {rd_icu,8\'h82,4\'h1};\r
+\t\r
+\tassign save_pc = {7\'b10_0010_0,dia_flag,7\'b00_0_0000,dia_flag,3\'b001};\t// Exception : PC_ARCHI => EA, special case DIA\r
+\tassign no_trap = ~fpu_trap & ~ovf_flag & ~dbg_flag;\t// suppresion of WREN and LD_OUT[1] and ADDR_UNIT operation\r
+\r
+\t// ++++++++++++++++++++++++++  Overflow Trap  ++++++++++++++\r
+\t\r
+\talways @(posedge BCLK)\r
+\t\tif (ovf_flag || !PSR[4]) ovf_pipe <= 4\'d0;\r
+\t\t  else\r
+\t\t\tif (PHASE_0) ovf_pipe <= {ovf_pipe[2],(ovf_op & op_ok),ovf_pipe[0],(ovf2_op & op_ok)};\t// V-Bit switches on\r
+\t\t  \r
+\tassign ovf_op =  ( ((OPREG[6:2] == 5\'b000_11)\t// ADDQi\r
+\t\t\t\t\t  | (OPREG[3:2] == 2\'b00)) & (OPREG[1:0] != 2\'b10))\t\t// ADDi,ADDCi,SUBi,SUBCi\r
+\t\t\t\t\t| ((OPREG[7:0] == 8\'h4E) & OPREG[13] & (OPREG[11:10] == 2\'b00))\t// NEGi,ABSi\r
+\t\t\t\t\t| ((OPREG[7:0] == 8\'hEE) & ~OPREG[10]);\t// CHECKi\r
+\r
+\tassign ovf2_op =  ((OPREG[6:2] == 5\'b100_11) & (OPREG[1:0] != 2\'b10))\t// ACBi, these overflows have no FLAG\r
+\t\t\t\t\t| ((OPREG[13:10] == 4\'h1) & (OPREG[7:0] == 8\'h4E))\t// ASHi\r
+\t\t\t\t\t| ( OPREG[13] & (OPREG[11] == OPREG[10]) & (OPREG[7:0] == 8\'hCE)); // MULi,DEIi,QUOi,DIVi\r
+\t\t\t\t\t\r
+\t// ++++++++++++++++++++++++++  Debug Trap  ++++++++++++++\r
+\t\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) dbg_s <= 1\'b0;\r
+\t\t  else dbg_s <= dbg_trap | (dbg_s & ~((exc_vector == 4\'hE) & (phase_reg == 8\'h81)));\r
+\t\t  \r
+\talways @(posedge BCLK) dbg_en <= op_ok | ~PHASE_0;\r
+\t\r
+\tassign pc_match = dbg_en & TRAPS[3] & PHASE_0 & ~exception;\t// TRAPS[3] is only combinatorical\r
+\t\r
+\talways @(posedge BCLK) dbg_trap <= (pc_match | (addr_cmp & PHASE_0)) & TRAPS[5];\t// TRAPS[5] = Enable Trap\r
+\t\r
+\talways @(posedge BCLK) addr_cmp <= TRAPS[4] | (addr_cmp & ~PHASE_0);\t// TRAPS[4] = CAR HIT\r
+\t\t\t  \r
+\t// ++++++++++++++++++++++++++  Special case String Abort  ++++++++++++++\r
+\t\r
+\t// Flags cleared if entry and exit of string operation and during  Abort sequence, not valid for MOVM/CMPM\r
+\t// special case UNTIL/WHILE : reset if exit (op_feld_reg[17] = 1 = UNTIL)\r
+\tassign clr_sflag = \t   (phase_reg == 8\'hC0) | (phase_reg == 8\'hC7) | (phase_reg == 8\'hC8) | (phase_reg == 8\'h81)\r
+\t\t\t\t\t   | (((phase_reg == 8\'hD7) | (phase_reg == 8\'hDF)) & ~(STRING[3] ^ op_feld_reg[17])) ;\r
+\tassign set_src\t =     (phase_reg == 8\'hC1) | (phase_reg == 8\'hC9);\r
+\tassign set_dest\t =     (phase_reg == 8\'hC4) | (phase_reg == 8\'hCC);\r
+\t\r
+\talways @(posedge BCLK or negedge BRESET)\t// R1 is modified\r
+\t\tif (!BRESET) ssrc_flag <= 1\'b0;\r
+\t\t  else ssrc_flag <= (set_src & ~kurz_st) | (ssrc_flag & ~clr_sflag);\r
+\t\t  \r
+\talways @(posedge BCLK or negedge BRESET)\t// R2 is modified\r
+\t\tif (!BRESET) sdest_flag <= 1\'b0;\r
+\t\t  else sdest_flag <= (set_dest & ~kurz_st) | (sdest_flag & ~clr_sflag);\r
+\t\t  \r
+\tassign rrepa = {7\'b1000_011,~sdest_flag};\t// R1 and if necessary R2 restore\r
+\t\r
+\t// ++++++++++++++++++++++++++  The one byte opcodes  +++++++++++++++++++\r
+\t\r
+\t// The one byte opcodes have a special case : one byte opcode but the second byte should be valid too\r
+\t// Used with SAVE, RESTORE, ENTER and EXIT with their reg list. \r
+\t// The advantage is that the reg list is store in op_feld_reg.\r
+\t\r
+\t//\t[52:34]\taddressing\r
+\t//\t[33:20] register\r
+\t//\t[19:18]\t1 or 2 Byte opcode\r
+\t//\t[17:16]\tBSR/BR\r
+\t// \t [15:8]\tnext phase\r
+\t//\t  [7:4]\tSTART + LD_OUT\r
+\t//\t  [3:0]\toperand access : Displacement or Speicher\r
+\t\r
+\talways @(*)\t\t// SVC (E2) and BPT (F2) decode as exception\r
+\t\tcasex (OPREG[7:0])\r
+\t\t\t8\'hxA : op1_feld = {addr_nop, src_x, src_x, 2\'b01,2\'b01,8\'h01,4\'h0,4\'hE};\t// Bcc , DISP read\r
+\t\t\t8\'h02 : op1_feld = {addr_nop, src_x, src_x, 2\'b01,2\'b10,8\'h01,4\'h0,4\'hE};\t// BSR , DISP read\r
+\t\t\t8\'h12 : op1_feld = {pop_op  , src_x, stack, 2\'b01,2\'b00,8\'h2A,4\'h0,4\'h1};\t// RET , DISP later\r
+\t\t\t8\'h22 : op1_feld = {rmod_4\t, src_x, modul, 2\'b01,2\'b00,8\'h35,4\'h0,4\'h1};\t// CXP\r
+\t\t\t8\'h32 : op1_feld = {pop_op,   src_x, stack, 2\'b01,2\'b00,8\'h40,4\'h0,4\'h1};\t// RXP\r
+\t\t\t8\'h42 : op1_feld = {pop_op,\t  src_x, stack, 2\'b01,2\'b00,8\'h46,4\'h0,4\'h1};\t// RETT\r
+\t\t\t8\'h52 : op1_feld = {rd_icu,\t  src_x, src_x, 2\'b01,2\'b00,8\'h45,4\'h0,4\'h1};\t// RETI\r
+\t\t\t8\'h62 : op1_feld = {addr_nop, src_x, src_x, 2\'b10,2\'b00,8\'h30,4\'h0,4\'h0};\t// SAVE\r
+\t\t\t8\'h72 : op1_feld = {addr_nop, src_x, src_x, 2\'b10,2\'b00,8\'h32,4\'h0,4\'h0};\t// RESTORE\r
+\t\t\t8\'h82 : op1_feld = {push_op , frame, stack, 2\'b10,2\'b00,8\'h2D,4\'h2,4\'h1};\t// ENTER : PUSH FP\r
+\t\t\t8\'h92 : op1_feld = {addr_nop, src_x, src_x, 2\'b10,2\'b00,8\'h32,4\'h0,4\'h0};\t// EXIT : POP FP\r
+\t\t\t8\'hA2 : op1_feld = {addr_nop, src_x, src_x, 2\'b01,2\'b00,8\'h00,4\'h0,4\'h0};\t// NOP\r
+\t\t\t8\'hB2 : op1_feld = {addr_nop, src_x, src_x, 2\'b01,2\'b00,8\'h88,4\'h0,4\'h0};\t// WAIT\r
+\t\t\t8\'hC2 : op1_feld = {addr_nop, src_x, src_x, 2\'b01,2\'b00,8\'h88,4\'h0,4\'h0};\t// DIA\r
+\t\t\t8\'hD2 : op1_feld = {addr_nop, src_x, src_x, 2\'b01,2\'b00,8\'h89,4\'h0,4\'h0};\t// FLAG\r
+\t\t  default : op1_feld = {19\'hxxxxx,14\'hxxxx,     2\'b00,2\'b00,16\'hxxxx};\r
+\t\tendcase\r
+\t\t\r
+\tassign op_1byte  = op1_feld[18] &  valid[0];\r
+\tassign op_12byte = op1_feld[19] & (valid[1:0] == 2\'b11);\r
+\t\r
+\tassign new_addr = op1_feld[52:34];\r
+\tassign new_regs = op1_feld[33:20];\r
+\tassign new_ph   = op1_feld[15:8];\r
+\tassign new_nx   = op1_feld[7:0];\t// at Bcond DISP read\r
+\t\r
+\tassign pop_fp\t= new_fp ? pop_op : addr_nop;\r
+\tassign ppfp\t\t= new_fp ? 8\'h34 : 8\'h00;\r
+\t\r
+\talways @(posedge BCLK)\r
+\t\tif (PHASE_0)\r
+\t\t  begin\r
+\t\t\tex_br_op\t<= op1_feld[17:16];\t// BSR/BR\r
+\t\t\tcc_feld\t\t<= OPREG[7:4];\r
+\t\t\tnew_fp\t\t<= (OPREG[7:6] == 2\'b10);\t// not decoded complete but is sufficient\r
+\t\t\treti_flag\t<= OPREG[4];\t\t// only difference between RETI and RETT is important\r
+\t\t\tdia_op\t\t<= OPREG[6];\t\t// only difference between DIA and WAIT is important\r
+\t\t  end\r
+\t\t  \r
+\talways @(posedge BCLK) dia_flag <= dia_op & (phase_reg == 8\'h88);\t// special case DIA compared to WAIT : Addr DIA to Stack\r
+\t\r
+\talways @(posedge BCLK)\t// Format 1 opcodes write always DWord to reg, the same is true for Exceptions\r
+\t\tif (PHASE_0 || abbruch) format1 <= (valid[0] & (OPREG[3:0] == 4\'h2)) | exception;\r
+\t\t  else\r
+\t\t\tif (flag_flag || (interrupt && string_ende)) format1 <= 1\'b1;\r
+\t\r
+\t//\t\t\t\t\tBranch etc.\t\t\t\tCXP\t\t\t\t\t\tCXPD\r
+\tassign store_pc = (phase_reg == 8\'d1) | (phase_reg == 8\'h37) | (phase_reg == 8\'h6B);\t// only save in DIN Reg of DATENPFAD\r
+\tassign jump = (ex_br_op[0] & branch) | (acb_reg & ~ACB_ZERO) | ex_br_op[1];\r
+\t\r
+\talways @(posedge BCLK) ldpc_phase <=  (phase_reg == 8\'h3E)\t// PC load 'b'at CXP/Traps , all one clock cycle guaranted\r
+\t\t\t\t\t\t\t\t\t\t| (phase_reg == 8\'h43)\t// PC load at RXP\r
+\t\t\t\t\t\t\t\t\t\t| ((phase_reg == 8\'h49)\t& reti_flag)\t// PC load at RETI\r
+\t\t\t\t\t\t\t\t\t\t| (phase_reg == 8\'h4E)\t// PC load at RETT\r
+\t\t\t\t\t\t\t\t\t\t| (phase_reg == 8\'h66)\t// PC load at JUMP/JSR/CASE\r
+\t\t\t\t\t\t\t\t\t\t| (phase_reg == 8\'h7B);\t// PC load at DE = Direct Exception\r
+\t\r
+\tassign NEW = ((phase_reg == 8\'d1) &  jump & di_stat[0]) | LOAD_PC;\r
+\tassign LOAD_PC = ((phase_reg == 8\'h2B) & di_stat[0])\t// only one pulse, but DISP must be ok => di_stat[0] (RET)\r
+\t\t\t\t\t| ldpc_phase;\r
+\t\r
+\tassign no_modul = de_flag ? {1\'b0,dest_x} : {1\'b1,modul[5:0]};\r
+\t\r
+\tassign negativ\t = PSR[7];\r
+\tassign zero      = PSR[6];\r
+\tassign flag\t\t = PSR[5];\r
+\tassign larger\t = PSR[2];\r
+\tassign carry_psr = PSR[0];\r
+\t\r
+\tassign rett_exc = ~reti_flag & (phase_reg == 8\'h4B);\t// special case RETT : Stack can change during opcode\r
+\talways @(posedge BCLK) phase_exc <= (phase_reg == 8\'h80);\t// 1. Exception phase\r
+\talways @(negedge BCLK) if (PHASE_0 || phase_exc || rett_exc) s_user <= PSR[9];\t// Select Bit for Stack, delayed update\r
+\talways @(negedge BCLK)\r
+\t\tif (PHASE_0 || phase_exc) s_mod <= {PSR[9],~PSR[9]};\r
+\t\t  else\r
+\t\t\tif (rett_exc) s_mod <= s_mod | {PSR[9],~PSR[9]};\t// Both can be updated\r
+\t\r
+\talways @(cc_feld or zero or carry_psr or larger or negativ or flag)\r
+\t\tcase (cc_feld)\r
+\t\t  4\'h0 : branch =  zero;\t\t// EQual\r
+\t\t  4\'h1 : branch = ~zero;\t\t// Not Equal\r
+\t\t  4\'h2 : branch =  carry_psr;\t// Carry Set\r
+\t\t  4\'h3 : branch = ~carry_psr;\t// Carry Clear\r
+\t\t  4\'h4 : branch =  larger;\t\t// Higher\r
+\t\t  4\'h5 : branch = ~larger;\t\t// Lower or Same\r
+\t\t  4\'h6 : branch =  negativ;\t\t// Greater Than\r
+\t\t  4\'h7 : branch = ~negativ;\t\t// Less or Equal\r
+\t\t  4\'h8 : branch =  flag;\t\t// Flag Set\r
+\t\t  4\'h9 : branch = ~flag;\t\t// Flag Clear\r
+\t\t  4\'hA : branch = ~larger  & ~zero;\t// LOwer\r
+\t\t  4\'hB : branch =  larger  |  zero;\t// Higher or Same\r
+\t\t  4\'hC : branch = ~negativ & ~zero;\t// Less Than\r
+\t\t  4\'hD : branch =  negativ |  zero;\t// Greater or Equal\r
+\t\t  4\'hE : branch = 1\'b1;\t\t\t// True\r
+\t\t  4\'hF : branch = 1\'b0;\t\t\t// False\r
+\t\tendcase\r
+\t\t\r
+\t// +++++++++++++++++++++++  Register List Processing  ++++++++++++++++++++++++++++\r
+\t\r
+\talways @(posedge BCLK) init_rlist <= PHASE_0 | (phase_reg == 8\'h2E);\r
+\t\r
+\talways @(posedge BCLK)\r
+\t\tif (PHASE_0) rpointer <= 3\'b000;\r
+\t\t  else\r
+\t\t\tif (ACC_DONE || init_rlist) rpointer <= reg_nr;\r
+\t\t\t\r
+\tREG_LIST scanner ( .DIN(op_feld_reg[22:15]), .INIT(init_rlist), .IPOS(rpointer), .VALID(save_reg), .OPOS(reg_nr) );\r
+\t\r
+\tassign saver = {4\'h0,reg_nr};\r
+\t\r
+\talways @(posedge BCLK) if (ACC_DONE || init_rlist) resto <= {3\'h0,~reg_nr};\t// EXIT and RESTORE have the list mirrored : R0...R7\r
+\t\t\r
+\t// ++++++++++++++++++++++++++  Processing of Displacement and Immediate Operand  +++++++++++++++++++\r
+\t\r
+\talways @(posedge BCLK or negedge BRESET)\t// Flag for DISP and IMME access\r
+\t\tif (!BRESET) dim_feld[3] <= 1\'b0;\r
+\t\t  else dim_feld[3] <= next ? new_op[3] : ~di_stat[0] & dim_feld[3];\r
+\t\t\t\t\r
+\talways @(posedge BCLK) if (next) dim_feld[2:1] <= new_op[2:1];\r
+\t\r
+\talways @(posedge BCLK or negedge BRESET) \t// Flag for external access\r
+\t\tif (!BRESET) dim_feld[0] <= 1\'b0;\r
+\t\t  else dim_feld[0] <= next ? new_op[0] : ~ACC_DONE & dim_feld[0];\r
+\t\t  \r
+\t// special case QWORD, last term for security\r
+\talways @(posedge BCLK) qw_flag <= dim_feld[0] & ACC_DONE & (ACC_FELD[13:12] == 2\'b11) & ~qw_flag;\r
+\t\t\t\t\r
+\tassign LD_IMME = (dim_feld[3] & (dim_feld[2:1] != 2\'b11)) | short_op | store_pc;\t// Data multiplexer\r
+\tassign LD_DIN  =  (di_stat[0] & dim_feld[3] & (dim_feld[2:1] != 2\'b11))\t\t\t\t// Enable for DIN Register\r
+\t\t\t\t\t| (ACC_DONE   & dim_feld[0]) | qw_flag | short_op | store_pc;\t\t// next not possible : i.e. immediate and disp parallel\r
+\tassign ld_disp = (dim_feld[3:1] == 3\'b111);\t\t\t\t\t\t\t\t\t\t\t// Enable for DISP Register\r
+\r
+\t// Signal to ADDR_UNIT , only Displacement critical\r
+\tassign disp_ok = ld_disp ? di_stat[0] : 1\'b1;\r
+\t\r
+\talways @(dim_feld or OPREG or valid or ANZ_VAL)\t// Bit 0 is ""Data ok"", the upper 3 bits are for USED\r
+\t\tcasex ({dim_feld[2:1],OPREG[7:6]})\r
+\t\t  4\'b00_xx : di_stat = {3\'b001,valid[0]};\r
+\t\t  4\'b01_xx : di_stat = {3\'b010,(valid[1] & valid[0])};\r
+\t\t  4\'b10_xx : di_stat = {3\'b100,ANZ_VAL[2]};\r
+\t\t  4\'b11_0x : di_stat = {3\'b001,valid[0]};\r
+\t\t  4\'b11_10 : di_stat = {3\'b010,(valid[1] & valid[0])};\r
+\t\t  4\'b11_11 : di_stat = {3\'b100,ANZ_VAL[2]};\r
+\t\tendcase\r
+\r
+\talways @(OPREG)\r
+\t\tcasex (OPREG[7:6])\r
+\t\t  2\'b0x : disp_val = {{26{OPREG[6]}},OPREG[5:0]};\r
+\t\t  2\'b10 : disp_val = {{19{OPREG[5]}},OPREG[4:0],OPREG[15:8]};\r
+\t\t  2\'b11 : disp_val = {{3{OPREG[5]}},OPREG[4:0],OPREG[15:8],OPREG[23:16],OPREG[31:24]};\r
+\t\tendcase\r
+\t\t\r
+\tassign DISP_BR = disp_val;\t// DISP is also used for Bcc opcode\r
+\t\r
+\t// The generator for DISP : data is used in ADDR_UNIT\r
+\talways @(*)\r
+\t\tcasex ({ld_disp,disp_sel})\t//\tdisp_sel from new_op\r
+\t\t  5\'b1_00xx : DISP = disp_val;\r
+\t\t  5\'b1_01xx : DISP = 32\'h0 - disp_val;\t// special case for ENTER\r
+\t\t  5\'b1_1xxx : DISP = {disp_val[29:0],2\'b00};\t// DISP*4 for External Address Mode\r
+\t\t  5\'b0_11xx : DISP = {20\'hFFFFF,3\'h7,type_nmi,8\'h00};\t// Interrupt Service Address\r
+\t\t  5\'b0_1000 : DISP = 32\'hFFFF_FFFF;\t\t// PUSH Byte\r
+\t\t  5\'b0_1001 : DISP = 32\'hFFFF_FFFE;\t\t// PUSH Word\r
+\t\t  5\'b0_1010 : DISP = 32\'hFFFF_FFFC;\t\t// PUSH DWord\r
+\t\t  5\'b0_1011 : DISP = 32\'hFFFF_FFF8;\t\t// PUSH QWord\r
+\t\t  5\'b0_01xx : DISP = {26\'h0,exc_vector,2\'b00};\t\t// the exception vector as Offset for INTBASE\r
+\t\t  5\'b0_00xx : DISP = {28\'h0,disp_sel[1:0],2\'b00};\t// 0,+4,+8,+12 used with MOD, default is 0\r
+\t\tendcase\r
+\t\t\r
+\talways @(short_op or dim_feld or OPREG or op_setcfg or setcfg_lsb)\r
+\t\tcasex ({short_op,dim_feld[2:1]})\r
+\t\t  3\'b000 : imme_i = op_setcfg ? {28\'h0000_00F,OPREG[2:0],setcfg_lsb} : {24\'hxx_xxxx,OPREG[7:0]};\r
+\t\t  3\'b001 : imme_i =    {16\'hxxxx,OPREG[7:0],OPREG[15:8]};\r
+\t\t  3\'b01x : imme_i = {OPREG[7:0],OPREG[15:8],OPREG[23:16],OPREG[31:24]};\r
+\t\t  3\'b1xx : imme_i = {{29{OPREG[10]}},OPREG[9:7]};\t// for MOVQ etc. only OPREG can be used\r
+\t\tendcase\r
+\t\t\r
+\tassign IMME_Q = store_pc ? PC_SAVE : imme_i;\r
+\t\r
+\t// ++++++++++++++  Stack Control  +++++++++++++++++\r
+\t\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) new_spsel <= 1\'b0;\r
+\t\t  else new_spsel <= spupd | (new_spsel & ~PHASE_0 & ~fpu_trap & ~dvz_trap);\r
+\t\t\t\r
+\talways @(posedge BCLK) upd_info <= PHASE_0 & new_spsel;\t// one clock cycle earlier a change occurs, i.e. ADDF TOS,F0 => fpu_trap\r
+\t\r
+\tassign do_xor = fpu_trap ? upd_info : (PHASE_0 & new_spsel);\r
+\t\r
+\talways @(negedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) stack_sel <= 2\'b00;\r
+\t\t  else\r
+\t\t\tif (do_xor) stack_sel <= stack_sel ^ s_mod;\r
+\t\t\t\r
+\t// Special case RETT\r
+\talways @(posedge BCLK) if (!phase_reg[1]) old_su <= s_user;\t// is tested in state x\'49 and used in x\'4B\r
+\tassign ttstak = {1\'b0,((old_su == PSR[9]) ^ stack_sel[PSR[9]]),3\'b110,PSR[9],1\'b1};\r
+\t\r
+\t// ++++++++++++++  2 byte opcodes  +++++++++++++++++\r
+\t\r
+\t// Hint : short_op is decoded separatly\r
+\t\r
+\t// [47:45]\tSource : [2] TOS=>(SP), [1] Ri => (Ri), [0] 1=access of memory\r
+\t// [44:42]\tDestination : like [47:45]\r
+\t// \t  [41]\tlong opcode\t[41:39] only for standard sequenz - not Gruppe 2\r
+\t//    [40]\tsrc2_flag - Source 2 is read\r
+\t// \t  [39]\tdest_flag - a target operand exists\r
+\t// [38:33]\tsrc1_r Register field, no message about Immediate\r
+\t// [32:27]\tsrc2_r Register field\r
+\t// [26:25]\tsrc1_le Length of Source1 - this is used for qword\r
+\t// [24:23]\tsrc2_le Length of Source2 : 00=1/01=2/10=4/11=8 Bytes => WMASKE \r
+\t// [22:18]\tsrc1 field\r
+\t// [17:13]\tsrc2 field\r
+\t// [12:11]\top_type 2 Bit for sort of opcode\r
+\t//    [10]\tFL : F=1/L=0\r
+\t//   [9:8]\toriginal BWD : B=00/W=01/D=11\r
+\t//   [7:0]\topcode: operation code\r
+\t\r
+\tassign valid_size = (OPREG[1:0] != 2\'b10) & (valid[1:0] == 2\'b11);\t// valid size + valid OPREG-Bytes\r
+\t\r
+\tassign hzl_a = (OPREG[1:0] == 2\'b11) ? 2\'b10 : OPREG[1:0];\t// length field recoded\r
+\tassign hzl_b = {1\'b0,OPREG[1:0]};\t\t// standard Length field\r
+\tassign hzr_a = {3\'b000,OPREG[13:11]};\t// SRC2 or SRC1 regfield\r
+\tassign hzr_b = {3\'b000,OPREG[8:6]};\t\t// SRC2 regfield\r
+\tassign hzr_s = {((OPREG[15:11] == 5\'h17) ^ stack_sel[s_user]),3\'b110,s_user,1\'b1};\t// USER or SUPERVISOR Stack, TOS special case\r
+\t// Special case LPR & SPR regfield:\r
+\talways @(OPREG or stack_sel or s_user)\r
+\t\tcasex ({OPREG[10:7]})\r
+\t\t  4\'b1001 : hzr_c = {stack_sel[s_user],3\'b110,s_user,1\'b1};\t// USER or SUPERVISOR Stack\r
+\t\t  4\'b1011 : hzr_c = {stack_sel[1]\t  ,3\'b110,1\'b1,  1\'b1};\t// USER Stack\r
+\t\t  4\'b1100 : hzr_c = OPREG[6] ? temp_h : 6\'h1C;\t// CFG special case : LPR : SPR\r
+\t\t  default : hzr_c = {2\'b01,OPREG[10:7]};\r
+\t\tendcase\r
+\t\r
+\t// Unfortunately SETCFG must be implemented : it is transformed to a two byte opcode with one byte IMM operand\r
+\tassign setcfg = (OPREG[13:0] == 14\'h0B0E) & (valid[1:0] == 2\'b11);\r
+\r
+\talways @(*)\r
+\t  casex ({setcfg,OPREG[10:2]})\r
+\t\t// Short-Op Codes , ACB is an ADD with following jump\r
+\t\t10\'b0xxxx_x0011 : op2_feld = {6\'o11,3\'o3,6\'hxx,hzr_a,hzl_a,hzl_a,5\'h14,OPREG[15:11],2\'b00,hzl_b,8\'h40};\t// ADDQ ACB\r
+\t\t10\'b0xxxx_00111 : op2_feld = {6\'o11,3\'o2,6\'hxx,hzr_a,hzl_a,hzl_a,5\'h14,OPREG[15:11],2\'b00,hzl_b,8\'h41};\t// CMPQ\r
+\t\t10\'b0xxxx_01011 : op2_feld = {6\'o11,3\'o1,hzr_c,hzr_a,hzl_a,hzl_a,5\'h00,OPREG[15:11],2\'b00,hzl_b,8\'h45};\t// SPR\r
+\t\t// Scond is moving the SHORT operand in the Integer area as condition field\r
+\t\t10\'b0xxxx_01111 : op2_feld = {6\'o11,3\'o1,6\'hxx,hzr_a,hzl_a,hzl_a,5\'h14,OPREG[15:11],2\'b00,hzl_b,8\'h7A};\t// Format 7, A=(UNDEF)\r
+\t\t10\'b0xxxx_10111 : op2_feld = {6\'o11,3\'o1,6\'hxx,hzr_a,hzl_a,hzl_a,5\'h14,OPREG[15:11],2\'b00,hzl_b,8\'h45};\t// MOVQ\r
+\t\t10\'b0xxxx_11011 : op2_feld = {6\'o11,3\'o1,hzr_a,hzr_c,hzl_a,2\'b10,OPREG[15:11],5\'h00,2\'b00,hzl_b,8\'h76};\t// LPR => MOVZiD\r
+\t\t// Format 3 opcodes :\r
+\t\t10\'b00x10_11111 : op2_feld = {6\'o11,3\'o1,hzr_a,6\'h1D,hzl_a,hzl_a,OPREG[15:11],5\'h00,2\'b00,hzl_b,4\'h3,OPREG[10:7]}; // BIC/SPSR\r
+\t\t10\'b0x100_11111 : op2_feld = {6\'o61,3\'o1,hzr_a,hzr_b,hzl_a,hzl_a,OPREG[15:11],5\'h00,2\'b10,hzl_b,4\'h3,OPREG[10:7]}; // JUMP/JSR\r
+\t\t10\'b01110_11111 : op2_feld = {6\'o11,3\'o1,hzr_a,hzr_b,hzl_a,hzl_a,OPREG[15:11],5\'h00,2\'b10,hzl_b,4\'h3,OPREG[10:7]}; // CASE\r
+\t\t// Format 4 opcodes : main group\r
+\t\t10\'b0xxxx_xxxx0 : op2_feld = {6\'o11,3\'o3,hzr_a,hzr_b,hzl_a,hzl_a,OPREG[15:6],\t\t2\'b00,hzl_b,4\'h4,OPREG[5:2]};\r
+\t\t10\'b0xxxx_x0001 : op2_feld = {6\'o11,3\'o2,hzr_a,hzr_b,hzl_a,hzl_a,OPREG[15:6],\t\t2\'b00,hzl_b,4\'h4,OPREG[5:2]}; //CMP no WR\r
+\t\t10\'b0xxxx_x0101 : op2_feld = {6\'o11,3\'o1,hzr_a,hzr_b,hzl_a,hzl_a,OPREG[15:6],\t\t2\'b00,hzl_b,4\'h4,OPREG[5:2]}; //MOV no 2.Op\r
+\t\t10\'b0xxxx_x1101 : op2_feld = (OPREG[10:9] == 2\'b00) ?\t// target is Register => standard flow\r
+\t\t\t\t\t\t\t\t\t {6\'o11,3\'o2,hzr_a,hzr_b,hzl_a,2\'bxx,OPREG[15:6],\t\t2\'b00,hzl_b,4\'h4,OPREG[5:2]}\t// TBIT\r
+\t\t\t\t\t\t\t\t   : {6\'o14,3\'o2,hzr_a,hzr_b,hzl_a,2\'b00,OPREG[15:6],\t\t2\'b10,hzl_b,4\'h4,OPREG[5:2]};\r
+\t\t// ADJSPi\r
+\t\t10\'b01010_11111 : op2_feld = {6\'o11,3\'o3,hzr_a,hzr_s,hzl_a,2\'b10,OPREG[15:11],5\'h00,2\'b00,hzl_b,8\'h48};\t// is a SUBD\r
+\t\t// ADDR, length field not valid\r
+\t\t10\'b0xxxx_x1001 : op2_feld = {6\'o61,3\'o1,hzr_a,hzr_b,hzl_a,hzl_a,OPREG[15:6],\t\t2\'b00,hzl_b,8\'h49};\r
+\t\t10\'b00000_11111 : op2_feld = {6\'o71,3\'o1,hzr_a,hzr_b,hzl_a,hzl_a,OPREG[15:11],5\'h00,2\'b10,hzl_b,4\'h3,OPREG[10:7]}; // CXPD no Opcode\r
+\t\t// SETCFG => MOV Befehl , SRC1 is genrated for 32 bit , target is Register temp_h\r
+\t\t10\'b1xxxx_xxxxx\t: op2_feld = {40\'b001001_001_000000_111101_00_10_10100_00000_00_011,\t\t\t8\'h76};\r
+\t\tdefault\t \t\t: op2_feld = {40\'hxx_xxxx_xxxx,4\'hA,4\'hx};\r
+\t  endcase\r
+\t\t\r
+\tassign op_2byte = (valid_size | setcfg) & ~op2_feld[7];\t// it must be for sure shown ""Invalid Opcode""\r
+\r
+\t// Special case : the quick opcodes with the exception SPR and LPR\r
+\tassign short_op = ((~OPREG[5]) | (OPREG[6:4] == 3\'b011)) & (OPREG[3:2] == 2\'b11) & valid_size & PHASE_0;\r
+\talways @(posedge BCLK) if (PHASE_0) short_op_reg <= short_op;\r
+\tassign short_def =  PHASE_0 ? short_op : short_op_reg;\t\t\t\t\t\t\t// for the big state machine\r
+\tassign op_sho = (OPREG[6:4] == 3\'b011) ? 11\'h07A : op_mov;\t// Special case Scond at Index as Dest. , used only in Phase 0\r
+\t\r
+\t// 2. special case ACB\r
+\tassign acb_op = (OPREG[6:2] == 5\'h13) & valid_size;\r
+\talways @(posedge BCLK) if (PHASE_0) acb_reg <= acb_op;\r
+\tassign acb_flag = PHASE_0 ? acb_op : acb_reg;\r
+\tassign goacb = acb_flag ? 8\'h28 : 8\'h00;\t// x\'28 = 40 , wait jump at REG operation - short-op special case\r
+\r
+\t// 3. special case load of PSR and Init-Done opcodes : because of U bit in PSR a restart must follow,\r
+\t// CINV and LMR PTB must wait until Init-Done and than Restart.\r
+\t// All variants of LPR and BIC/S have an extra cycle due to TRACE operation\r
+\talways @(OPREG)\r
+\t\tcasex (OPREG[18:0])\r
+\t\t  19\'bxxx_xxxxx_1101_110_11_xx : waitop = 9\'h14C;\t// LPRi PSR,...\r
+\t\t  19\'bxxx_xxxxx_1100_110_11_xx : waitop = 9\'h174;\t// LPRi CFG,...\r
+\t\t  19\'bxxx_xxxxx_0x10_111_11_xx : waitop = 9\'h14C;\t// BICPSRi/BISPSRi ...\r
+\t\t  19\'bxxxx_x_0010_xx_0000_1110 : waitop = 9\'h174;\t// SETCFG []\r
+\t\t  19\'bxxxx_0_0010_xx_0001_1110 : waitop = 9\'h174;\t// LMR  - at the end Restart\r
+\t\t  19\'bxxxx_0_1001_xx_0001_1110 : waitop = 9\'h174;\t// CINV - at the end Restart\r
+\t\t  default\t\t\t\t\t   : waitop = 9\'h000;\r
+\t\tendcase\r
+\t\t\r
+\tassign dowait = waitop[7:0];\t// is used in Phase 0 if PSR is loaded from Register\r
+\talways @(posedge BCLK) if (PHASE_0) wait_reg <= waitop;\r
+\r
+\t// Here 2. and 3. special case are coming together:\r
+\t// Phase definition, end over jump for ACB , not used in Phase 0\r
+\tassign endea = acb_reg ? 8\'h01 : (wait_reg[8] ? wait_reg[7:0] : 8\'h00);\t\r
+\tassign diacb = acb_reg ? 4\'hE : 4\'h0;\t// load Disp ?\r
+\t\r
+\t// special case ADJSPi : SP=SRC2 always 32 Bit\r
+\talways @(posedge BCLK)\r
+\t\tif (PHASE_0) dw_info <= (OPREG[10:2] == 9\'b1010_11111);\r
+\t\t  else dw_info <= dw_info & ~phase_reg[7];\t// for security at ABORT\r
+\t\r
+\t// SETCFG : Flag to transform the Byte Immeadiate operand\r
+\talways @(posedge BCLK) if (PHASE_0) op_setcfg  <= setcfg;\r
+\talways @(posedge BCLK) if (PHASE_0) setcfg_lsb <= OPREG[15];\r
+\t\r
+\talways @(posedge BCLK) if (PHASE_0) jsr_flag <= (OPREG[10:2] == 9\'b1100_11111);\t\t// JSR : for PUSH\r
+\talways @(posedge BCLK)\t// Bit opcodes to Register and EXT:SRC1 / INS:SRC2\r
+\t\tif (PHASE_0) bit_reg  <= ((OPREG[3] ? ((OPREG[7:6] == 2\'d0) ? OPREG[23:22] : OPREG[18:17]) : OPREG[10:9]) == 2\'b00);\r
+\talways @(posedge BCLK) if (PHASE_0) exin_cmd <= (~OPREG[10] & (OPREG[6:0] == 7\'h2E)) & (valid[2:0] == 3\'b111);\r
+\talways @(posedge BCLK) if (PHASE_0) extract <= ~OPREG[7];\r
+\talways @(posedge BCLK) if (PHASE_0) inss_op <= (OPREG[13:10] == 4\'h2) & (OPREG[7:0] == 8\'hCE) & (valid[2:0] == 3\'b111);\t// INSS\r
+\t\t\r
+\t// ++++++++++++++  3 byte opcodes  +++++++++++++++++\r
+\r
+\t// [47:45]\tSource : [2] TOS=>(SP), [1] Ri => (Ri), [0] 1=access of memory\r
+\t// [44:42]\tDestination : like [47:45]\r
+\t// \t  [41]\tlong opcode\t[41:39] only for standard sequenz - not Gruppe 2\r
+\t//    [40]\tsrc2_flag - Source 2 is read\r
+\t// \t  [39]\tdest_flag - a target operand exists\r
+\t// [38:33]\tsrc1_r Register field, no message about Immediate\r
+\t// [32:27]\tsrc2_r Register field\r
+\t// [26:25]\tsrc1_le Length of Source1 - this is used for qword\r
+\t// [24:23]\tsrc2_le Length of Source2 : 00=1/01=2/10=4/11=8 Bytes => WMASKE \r
+\t// [22:18]\tsrc1 field\r
+\t// [17:13]\tsrc2 field\r
+\t// [12:11]\top_type 2 Bit for sort of opcode\r
+\t//    [10]\tFL : F=1/L=0\r
+\t//   [9:8]\toriginal BWD : B=00/W=01/D=11\r
+\t//   [7:0]\topcode: operation code\r
+\t\r
+\tassign hdx_a = OPREG[7] ? OPREG[8] : OPREG[10];\r
+\tassign hdo_a = OPREG[13:10];\r
+\tassign hdo_b = ~hdx_a;\t\t\t\t// long operation if L\r
+\tassign hdo_c = {1\'b0,OPREG[10],OPREG[7:6]};\t// Format 8 opcodes\r
+\tassign hdo_d = {6\'b0101_00,OPREG[10],1\'b0};\t// CMPM/S or MOVM/S : 8\'h52 or 8\'h50\r
+\tassign hdo_e = {3\'b011,OPREG[10]};\t// Special codes for LOGB and SCALB due to DP_OUT datapath\r
+\t// Definitions of length\r
+\tassign hdl_a = {1\'b0,OPREG[9:8]};\t// i size, is used in OPER\r
+\tassign hdl_b = (OPREG[9:8] == 2\'b11) ? 2\'b10 : OPREG[9:8];\t// recode length field, is used in ACC field\r
+\tassign hdl_c = OPREG[10:8];\t\t\t// FL + BWD\r
+\tassign hdl_d = {1\'b1,~hdx_a};\t\t// length FP\r
+\tassign hdl_e = {OPREG[8],2\'bxx};\t// BWD don\'t care\r
+\tassign hdl_f = (OPREG[18:17] == 2\'b00) ? OPREG[9:8] : {OPREG[8],~(OPREG[9] ^ OPREG[8])};\t// exclusiv for DEI\r
+\tassign hdl_g = {(OPREG[9:8] != 2\'b00),(OPREG[9:8] == 2\'b00)};\t// exclusiv for EXT/EXTS base operand\r
+\tassign hdl_h = {(OPREG[9:8] != 2\'b00),(OPREG[9:8] != 2\'b01)};\t// exclusiv for CHECK bound operand\r
+\t// Register definitions\r
+\tassign hdr_a = {3\'b000,OPREG[21:19]};\t// SRC1 Integer Register\r
+\tassign hdr_b = {3\'b000,OPREG[16:14]};\t// SRC2 Integer Register\r
+\tassign hdr_c = hdx_a ? {2\'b10,OPREG[21:20],1\'b0,OPREG[19]} : {2\'b10,OPREG[21:19],1\'b1};\r
+\tassign hdr_d = hdx_a ? {2\'b10,OPREG[16:15],1\'b0,OPREG[14]} : {2\'b10,OPREG[16:14],1\'b1};\r
+\tassign hdr_e = OPREG[11] ? {2\'b10,OPREG[21:20],1\'b0,OPREG[19]} : {2\'b10,OPREG[21:19],1\'b1};\r
+\tassign hdr_f = OPREG[11] ? {2\'b10,OPREG[16:14],1\'b1}\t\t   : {2\'b10,OPREG[16:15],1\'b0,OPREG[14]};\r
+\tassign hdr_g = {3\'b000,OPREG[16:15],~OPREG[14]};\t// exclusiv for DEI/MEI\r
+\tassign hdr_m = {3\'b001,OPREG[17:15]};\t// MMU Register Index 8-15\r
+\t\r
+\talways @(*)\r
+\t\tcasex (OPREG[13:3])\r
+\t\t  11\'b1000_xx_1100x : op3_feld = {6\'o11,3\'o3,hdr_a,hdr_b, hdl_b,hdl_b,OPREG[23:14],2\'b00,hdl_a,4\'h7,hdo_a};\t// MULi\r
+\t\t  11\'b000x_xx_0100x : op3_feld = {6\'o11,3\'o3,hdr_a,hdr_b, 2\'b00,hdl_b,OPREG[23:14],2\'b00,hdl_a,4\'h6,hdo_a};\t// ROTi,ASHi\r
+\t\t  11\'b0101_xx_0100x : op3_feld = {6\'o11,3\'o3,hdr_a,hdr_b, 2\'b00,hdl_b,OPREG[23:14],2\'b00,hdl_a,4\'h6,hdo_a};\t// LSHi\r
+\t\t  11\'b1x0x_xx_0100x : op3_feld = {6\'o11,3\'o1,hdr_a,hdr_b, hdl_b,hdl_b,OPREG[23:14],2\'b00,hdl_a,4\'h6,hdo_a};\t// NEGi,NOTi,ABSi,COMi\r
+\t\t  11\'b010x_xx_1100x : op3_feld = {6\'o11,3\'o1,hdr_a,hdr_b, hdl_b,2\'b01,OPREG[23:14],2\'b00,hdl_a,4\'h7,hdo_a};\t// MOVX/ZiW\r
+\t\t  11\'b011x_xx_1100x : op3_feld = {6\'o11,3\'o1,hdr_a,hdr_b, hdl_b,2\'b10,OPREG[23:14],2\'b00,hdl_a,4\'h7,hdo_a};\t// MOVX/ZiD\r
+\t\t  11\'b0001_xx_0110x : op3_feld = {6\'o11,3\'o3,hdr_a,hdr_b, hdl_b,2\'b00,OPREG[23:14],2\'b00,hdl_a,4\'h8,hdo_c};\t// FFSi\r
+\t// Floating Point opcodes\r
+\t\t  11\'b000x_xx_0011x : op3_feld = {6\'o11,hdo_b,2\'b01,hdr_a,hdr_d, hdl_b,hdl_d,OPREG[23:14],2\'b00,hdl_c,4\'h9,hdo_a};\t// MOVif\r
+\t\t  11\'b010x_xx_0011x : op3_feld = {6\'o11,       3\'o5,hdr_e,hdr_f, 2\'b11,2\'b10,OPREG[23:14],2\'b00,hdl_c,4\'h9,hdo_a};\t// MOVLF\r
+\t\t  11\'b011x_xx_0011x : op3_feld = {6\'o11,       3\'o5,hdr_e,hdr_f, 2\'b10,2\'b11,OPREG[23:14],2\'b00,hdl_c,4\'h9,hdo_a};\t// MOVFL\r
+\t\t  11\'b10xx_xx_0011x : op3_feld = {6\'o11,hdo_b,2\'b01,hdr_c,hdr_b, hdl_d,hdl_b,OPREG[23:14],2\'b00,hdl_c,4\'h9,hdo_a};\t// ROUNDi,TRUNCi\r
+\t\t  11\'b111x_xx_00111 : op3_feld = {6\'o11,hdo_b,2\'b01,hdr_c,hdr_b, hdl_d,hdl_b,OPREG[23:14],2\'b00,hdl_c,4\'h9,hdo_a};\t// FLOORi\r
+\t\t  11\'b111x_xx_00110 : op3_feld = {6\'o11,       3\'o5,hdr_c,hdr_b, hdl_d,hdl_b,OPREG[23:14],2\'b00,hdl_c,op_cop};\t\t// SEARCH\r
+\t\t  11\'b0x00_0x_10111 : op3_feld = {6\'o11,hdo_b,2\'b11,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2\'b00,hdl_e,4\'hB,hdo_a};\t// ADDf,SUBf\r
+\t\t  11\'bxx00_0x_10110 : op3_feld = {6\'o11,       3\'o7,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2\'b00,hdl_e,op_cop};\t\t// Coprocessor\r
+\t\t  11\'b1000_0x_10111 : op3_feld = {6\'o11,       3\'o7,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2\'b00,hdl_e,4\'hB,hdo_a};\t// DIVf\r
+\t\t  11\'b1100_0x_10111 : op3_feld = {6\'o11,hdo_b,2\'b11,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2\'b00,hdl_e,4\'hB,hdo_a};\t// MULf\r
+\t\t  11\'b0010_0x_1011x : op3_feld = {6\'o11,hdo_b,2\'b10,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2\'b00,hdl_e,4\'hB,hdo_a};\t// CMPf\r
+\t\t  11\'b0001_0x_10111 : op3_feld = {6\'o11,       3\'o1,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2\'b00,hdl_e,4\'hB,hdo_a};\t// MOVf\r
+\t\t  11\'bx101_0x_10111 : op3_feld = {6\'o11,       3\'o1,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2\'b00,hdl_e,4\'hB,hdo_a};\t// NEGf,ABSf\r
+\t\t  11\'b001x_11_00111 : op3_feld = {6\'o11,3\'o1,hdr_a,fsr_r, 2\'b10,2\'b10,OPREG[23:19],5\'b0,2\'b00,3\'o3,8\'h92};\t\t\t// LFSR\r
+\t\t  11\'b110x_11_00111 : op3_feld = {6\'o11,3\'o1,fsr_r,hdr_b, 2\'b10,2\'b10,5\'b0,OPREG[18:14],2\'b00,3\'o3,8\'h9C};\t\t\t// SFSR\r
+\t// MMU opcodes\r
+\t\t  11\'b0010_11_0001x : op3_feld = {6\'o11,3\'o1,hdr_a,temp_h,2\'b10,2\'b10,OPREG[23:19],5\'b0,2\'b00, 3\'o3,8\'h45};\t// LMR\r
+\t\t  11\'b0011_11_0001x : op3_feld = {6\'o11,3\'o1,hdr_m,hdr_a, 2\'b10,2\'b10,5\'b0,OPREG[23:19],2\'b00, 3\'o3,8\'h45};\t// SMR\r
+\t// String opcodes\r
+\t\t  11\'b000x_xx_0000x : op3_feld = {6\'o11,3\'o0,6\'hxx,6\'hxx, 2\'bxx,2\'b10,OPREG[23:14],     2\'b10,hdl_c,hdo_d};\t// MOVS,CMPS\r
+\t\t  11\'b0011_xx_0000x : op3_feld = {6\'o11,3\'o0,6\'hxx,6\'hxx, 2\'bxx,2\'b10,OPREG[23:14],     2\'b10,hdl_c,hdo_d};\t// SKPS\r
+\t// Custom opcodes\r
+\t\t  11\'bxx01_0x_10110 : op3_feld = {6\'o11,       3\'o5,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2\'b00,hdl_e,op_cop};\r
+\t// Integer Divisionen : QUOi REMi DIVi MODi and DEIi + MEIi\r
+\t\t  11\'b11xx_xx_1100x : op3_feld = {6\'o11,3\'o7,hdr_a,hdr_b, hdl_b,hdl_b,OPREG[23:14],2\'b00,hdl_a,4\'h7,hdo_a};\r
+\t\t  11\'b10x1_xx_1100x : op3_feld = {6\'o11,3\'o7,hdr_a,hdr_g, hdl_b,hdl_f,OPREG[23:14],2\'b10,hdl_a,4\'h7,hdo_a};\t// DEI/MEI\r
+\t// Gruppe 2 opcodes\r
+\t\t  11\'b0x11_xx_1010x : op3_feld = {6\'o77,3\'o1,hdr_a,hdr_b, hdl_b,hdl_b,OPREG[23:14],2\'b00,hdl_a,8\'h45};\t\t// MOVUS,MOVSU\r
+\t\t  11\'b000x_xx_1100x : op3_feld = {6\'o66,3\'o0,hdr_a,hdr_b, 2\'bxx,2\'b10,OPREG[23:14],2\'b10,hdl_c, hdo_d};\t\t// MOVM/CMPM\r
+\t\t  11\'b001x_0x_1111x : op3_feld = {6\'o11,3\'o2,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2\'b10,hdl_e,4\'hC,hdo_a};\t// DOTf,POLYf\r
+\t\t  11\'b0101_0x_1111x : op3_feld = {6\'o11,3\'o5,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2\'b00,hdl_e,4\'hB,hdo_e};\t// LOGB\r
+\t\t  11\'b0100_0x_1111x : op3_feld = {6\'o11,3\'o7,hdr_c,hdr_d, hdl_d,hdl_d,OPREG[23:14],2\'b10,hdl_e,4\'hB,hdo_e};\t// SCALB\r
+\t\t  11\'b0011_xx_1100x : op3_feld = {6\'o50,3\'o0,hdr_a,hdr_b, hdl_g,hdl_b,OPREG[23:14],2\'b10,hdl_c,4\'h7,hdo_a};\t// EXTS\r
+\t\t  11\'bxxx0_xx_1110x : op3_feld = {6\'o71,3\'o2,hdr_a,hdr_b, hdl_h,hdl_b,OPREG[23:14],2\'b10,hdl_c,4\'h8,hdo_c};\t// CHECK\r
+\t\t  11\'b0x1x_xx_0100x : op3_feld = (OPREG[18:17] == 2\'b00) ?\t// target is register => standard flow\r
+\t\t\t\t\t\t\t\t\t\t {6\'o11,3\'o3,hdr_a,hdr_b, hdl_b,2\'b10,OPREG[23:14],2\'b00,hdl_a,4\'h6,hdo_a}\t// SBIT/CBIT\r
+\t\t\t\t\t\t\t\t\t   : {6\'o14,3\'o3,hdr_a,hdr_b, hdl_b,2\'b00,OPREG[23:14],2\'b10,hdl_a,4\'h6,hdo_a};\r
+\t\t  11\'b1110_xx_0100x : op3_feld = (OPREG[18:17] == 2\'b00) ?\t// target is register => standard flow\r
+\t\t\t\t\t\t\t\t\t\t {6\'o11,3\'o3,hdr_a,hdr_b, hdl_b,2\'b10,OPREG[23:14],2\'b00,hdl_a,4\'h6,hdo_a}\t// IBIT\r
+\t\t\t\t\t\t\t\t\t   : {6\'o14,3\'o3,hdr_a,hdr_b, hdl_b,2\'b00,OPREG[23:14],2\'b10,hdl_a,4\'h6,hdo_a};\r
+\t\t  11\'b1x11_xx_0100x : op3_feld = {6\'o11,3\'o7,hdr_a,hdr_b, hdl_b,hdl_b,OPREG[23:14],2\'b00,hdl_a,4\'h6,hdo_a}; // ADDP,SUBP\r
+\t\t  11\'bxxx0_xx_0010x : op3_feld = {6\'o40,3\'o0,hdr_a,hdr_b, hdl_g,hdl_b,OPREG[23:14],2\'b10,hdl_c,4\'h8,hdo_c}; // EXT\r
+\t\t  11\'bxxx0_xx_1010x : op3_feld = {6\'o14,3\'o0,hdr_a,hdr_b, hdl_b,2\'b10,OPREG[23:14],2\'b10, 3\'o3,4\'h8,hdo_c}; // INS\r
+\t\t  11\'b0010_xx_1100x : op3_feld = {6\'o14,3\'o0,hdr_a,hdr_b, hdl_b,2\'b10,OPREG[23:14],2\'b10, 3\'o3,4\'h8,hdo_a}; // INSS\r
+\t\t  11\'bxxx0_xx_0110x : op3_feld = {6\'o61,3\'o0,hdr_a,hdr_b, hdl_b,2\'b10,OPREG[23:14],2\'b10, 3\'o3,4\'h8,hdo_c}; // CVTP no Opcode\r
+\t\t  11\'bxxx1_xx_0010x : op3_feld = {6\'o11,3\'o2,hdr_a,hdr_b, hdl_b,hdl_b,OPREG[23:14],2\'b10, 3\'o3,8\'h84};\t\t// INDEX\r
+\t// Gruppe 2 opcodes can have dedicated operation codes. Therefore the operation code definition here is ""don\'t care""\r
+\t\t  11\'b000x_xx_0001x : op3_feld = {6\'o70,3\'o0,hdr_a,hdr_b, 2\'b00,2\'b10,OPREG[23:19],5\'b0,2\'b10,3\'o0,8\'h45};\t// RDVAL+WRVAL \r
+\t\t  11\'b1001_11_0001x : op3_feld = {6\'o11,3\'o1,hdr_a,temp_h,2\'b10,2\'b10,OPREG[23:19],5\'b0,2\'b00,3\'o3,8\'h45};\t// CINV\r
+\t\t\r
+\t\t  default\t \t    : op3_feld = {40\'hxx_xxxx_xxxx,4\'hA,4\'hx};\r
+\t\tendcase\r
+\t\r
+\tassign op_3byte = (valid[2:0] == 3\'b111) & (OPREG[2:0] == 3\'b110) & (op3_feld[7:4] != 4\'hA);\t// valid for all incl. CUSTOM\r
+\t\r
+\t// +++++++++++++  Evaluation for 2 and 3 byte opcodes  ++++++++++++++++++\r
+\r
+\t// for one byte opcodes special treatmant neccessary\r
+\tassign opc_bits = op_3byte ? op3_feld : op2_feld;\r
+\t\r
+\tassign op_ok = (op_1byte | op_12byte | op_2byte | op_3byte | exception) & ~stop;\t// used for computation of USED\r
+\r
+\talways @(posedge BCLK) if (PHASE_0) op_feld_reg\t<= opc_bits;\r
+\tassign op_feld = PHASE_0 ? opc_bits : op_feld_reg;\t// constant for all following cycles\r
+\r
+\t// Evaluation of op_feld :\r
+\r
+\tassign atys\t\t = op_feld[47:45];\t// [2] : TOS=>(SP), [1] : Ri => (Ri), [0] : 1=access of memory\r
+\tassign atyd\t\t = op_feld[44:42];\t// [2] : TOS=>(SP), [1] : Ri => (Ri), [0] : 1=access of memory\r
+\tassign long\t\t = op_feld[41];\r
+\tassign src2_flag = op_feld[40];\r
+\tassign dest_flag = op_feld[39];\r
+\t\r
+\tassign src_1 \t= {1\'b0,op_feld[38:33]};\r
+\tassign src_2 \t= {1\'b0,op_feld[32:27]};\r
+\tassign src1_le \t= op_feld[26:25];\r
+\tassign src2_le \t= op_feld[24:23];\r
+\tassign acc1 \t= (op_feld[22:21] != 2\'b00) | atys[1];\t// external access Source1 or ""addr"" : Reg => (Reg)\r
+\tassign acc2 \t= (op_feld[17:16] != 2\'b00) | atyd[1];\t// external access Source2 or ""addr"" : Reg => (Reg)\r
+\tassign wlor\t\t= dest_flag & ~acc2;\r
+\tassign idx_n \t= {1\'b0,(op_feld[22:20] == 3\'b111)} + {1\'b0,(op_feld[17:15] == 3\'b111)};\t// Index : 0,1 or 2\r
+\tassign idx \t\t= (idx_n != 2\'b00);\t// Index is active\r
+\tassign n_idx\t= idx_n - 2\'b01;\r
+\t\r
+\t// The field otype is used only in Phase 0\r
+\tassign otype\t= exception ? 2\'b11 : ((op_1byte | op_12byte) ? 2\'b01 : opc_bits[12:11]);\t// string opcodes use code 2\'b10\r
+\t\r
+\tassign opera\t= op_feld[10:0];\r
+\t\r
+\tassign dest_r\t= src_2[5:0];\r
+\tassign dest_rl\t= {dest_r[5:1],1\'b0};\r
+\t\r
+\t// +++++++++++++++++++++++++  Coprocessor operations field  ++++++++++++++++++++++++++++++\r
+\t\r
+\talways @(posedge BCLK) if (PHASE_0) COP_OP <= OPREG[23:0];\r
+\t\r
+\t// +++++++++++++++++++++++++  Special signals for LMR and CINV  ++++++++++++++++++++++++++\r
+\t// op_lmr is constant = parameter\r
+\t\r
+\tassign STOP_IC\t= (phase_reg == 8\'h74) | (phase_reg == 8\'h75);\r
+\r
+\t// CINV uses Register x\'30 - x\'37 :  CINV = 110... , LMR = 001... otherwise CFG\r
+\talways @(posedge BCLK) if (PHASE_0) lmrreg <= op_3byte ? {{2{OPREG[13]}},~OPREG[13],OPREG[17:15]} : 6\'h1C;\r
+\r
+\talways @(posedge BCLK) no_init <= (lmrreg[5:4] == 2\'b00) & (lmrreg[3:1] != 3\'b110);\t// LMR waits for INIT at PTB0/1\r
+\t// a_ivar = ""Addresse IVAR0/1""\r
+\talways @(posedge BCLK) a_ivar  <= STOP_IC;\t// Phase 74 & 75, is used at INFO_AU together with IC_READ\r
+\t\r
+\t// CINV detection for IC_CACHE\r
+\talways @(posedge BCLK)\r
+\t\tif (PHASE_0) cinv_flag <= OPREG[13] & (OPREG[7:0] == 8\'h1E);\r
+\t\t\telse cinv_flag <= cinv_flag & ~phase_reg[7];\t// reset at exception\r
+\t\t\t\r
+\tassign ENA_HK = ~(cinv_flag & STOP_IC);\t// always ""1"", if CINV then ""0"" \r
+\t\t\t\r
+\t// +++++++++++++++++++++++++  USER flag for MOVUS & MOVSU  ++++++++++++++++++++++++\r
+\t\r
+\talways @(posedge BCLK)\r
+\t\tif (PHASE_0) m_ussu <= (~OPREG[13] & (OPREG[11:10] == 2\'b11) & (OPREG[7:0] == 8\'hAE));\r
+\t\t\telse m_ussu <= m_ussu & ~phase_reg[7];\t// reset at exception\r
+\t\t\t\r
+\talways @(posedge BCLK) if (PHASE_0) m_usel <= OPREG[12];\r
+\t\r
+\t// +++++++++++++++++++++++++  USER flag for RDVAL & WRVAL  ++++++++++++++++++++++++\r
+\t\r
+\talways @(posedge BCLK)\r
+\t\tif (PHASE_0) rwval_flag <= (OPREG[13:11] == 3\'d0) & (OPREG[7:0] == 8\'h1E);\r
+\t\t\telse rwval_flag <= rwval_flag & ~phase_reg[7];\t// reset at exception\r
+\t\t\t\r
+\talways @(posedge BCLK) if (PHASE_0) wrval_flag <= OPREG[10];\t// Difference RDVAL=0 and WRVAL=1\r
+\t\r
+\t// +++++++++++++++++++++++++  Flags for CBIT/I+SBIT/I+IBIT  +++++++++++++++++++++++\r
+\t\r
+\tassign rw_bit = (op_feld_reg[7:4] == 4\'d6) & ((~op_feld_reg[3] & op_feld_reg[1]) | (op_feld_reg[3:0] == 4\'hE));\r
+\tassign op_ilo = rw_bit & op_feld_reg[0];\t// Interlocked : CBITI and SBITI\r
+\t\r
+\t// +++++++++++++++++++++++++++++  Operations for String processing  +++++++++++++++++\r
+\t// Address field : Size:2 RD WR LDEA FULLACC INDEX:4 SPUPD disp_val:4 POST CLRMSW SRC2SEL:2\r
+\t\r
+\tassign st_src \t= {STRING[1:0],5\'b1010_0,(op_feld_reg[15] & ~kurz_st),STRING[1:0],9\'b0_0000_1000};\t// [15] = BACKWARD\r
+\tassign st_src2\t= {STRING[1:0],5\'b1010_0,(op_feld_reg[15] & ~kurz_st),STRING[1:0],9\'b0_0000_1011};\t// Reuse EA\r
+\tassign st_dest\t= {STRING[1:0],5\'b0110_0,(op_feld_reg[15] & ~kurz_st),STRING[1:0],9\'b0_0000_1011};\t// Reuse EA\r
+\tassign st_trde\t= {2\'b00,      5\'b0110_0, op_feld_reg[15],            2\'b00,      9\'b0_0000_1000};\t// after Translate to Dest\r
+\tassign st_trs2\t= {STRING[1:0],5\'b1010_0, op_feld_reg[15],            STRING[1:0],9\'b0_0000_1000};\t// after Match to SRC2\r
+\tassign st_len\t= {STRING[1:0],17\'b0000_0000_0_0000_0000};\t// length important for qw_flag\r
+\t\r
+\t// Signals of DETOIP go to I_PFAD\r
+\talways @(posedge BCLK) if (PHASE_0) kill_opt <= ~OPREG[7] & (OPREG[17:15] != 3\'b000);\t// watch difference of MOVM and MOVS\r
+\tassign ph_match = (phase_reg[7:4] == 4\'hD) & (phase_reg[2:0] == 3\'d7);\t// Phase D7 and DF\r
+\t\r
+\tassign op_str\t= {op_feld_reg[10:8],6\'b0101_00,op_feld_reg[1],1\'b1}; // Opcode 8\'h51 or 8\'h53;\r
+\tassign op_scp\t= {op_feld_reg[10:8],8\'h41};\t// normal CMPi\r
+\tassign ph_str\t= {4\'hC,op_feld_reg[1],3\'b001};\t// Phase 8\'hC1 (MOVS/M) or 8\'hC9 (CMPS/M)\r
+\t\r
+\talways @(posedge BCLK) kurz_st <= (phase_reg == 8\'h65) | (kurz_st & ~PHASE_0);\t\t\t// Flag for MOVM/CMPM\r
+\talways @(posedge BCLK) if (PHASE_0) cmps_flag <= ~OPREG[7] & (OPREG[11:10] == 2\'b01);\t// Flag for CMPS\r
+\talways @(posedge BCLK) if (PHASE_0) skps_flag <= ~OPREG[7] & (OPREG[11:10] == 2\'b11);\t// Flag for SKPS\r
+\talways @(posedge BCLK) if (PHASE_0) mt_flag <= ~OPREG[7] & (OPREG[17] | OPREG[15]);\t\t// Flag for Match and Translate\r
+\r
+\tassign wstr0\t= {{4{kurz_st}},2\'b00};\r
+\tassign wstr1\t= {{4{kurz_st}},2\'b01};\r
+\tassign wstr2\t= {{4{kurz_st}},2\'b10};\r
+\tassign rstr0\t= {1\'b0,wstr0};\r
+\tassign rstr1\t= {1\'b0,wstr1};\r
+\tassign rstr2\t= {1\'b0,wstr2};\r
+\t\r
+\t// +++++++++++++++++++++++++++++++++++  Index processing  +++++++++++++++++++++++++++++++++++++++++\r
+\t\r
+\tassign phase_idx = (phase_reg == 8\'h02) | (phase_reg == 8\'h50);\r
+\t\r
+\tassign idx_bytes = idx_1[2] ? OPREG[15:0] : {OPREG[7:0],OPREG[7:0]};\t// here last access of OPREG\r
+\talways @(posedge BCLK) if (phase_idx) idx_reg <= idx_bytes;\r
+\tassign idx_feld = (phase_idx) ? idx_bytes : idx_reg;\r
+\t\r
+\t// +++++++++++++++++++++++++++++++++++  The big state machine  ++++++++++++++++++++++++++++++++++++\r
+\t\r
+\t// Hints :\r
+\t// 1. At short-op SRC1 is out of memory to use TEMP\r
+\t// 2. At SRC2 rmw suppresed TOS and changed it to (SP)\r
+\t// 3. The Long-operation path takes the dest_r address to write if WR_REG activ\r
+\t// 4. It is ok, that an extra cycle for the read of the index registers is needed - then data could be written ins Out register\r
+\t\r
+\t// Source 1\r
+\t\r
+\tassign idx_1 = {1\'b0,(op_feld[22:20] == 3\'b111),op_feld[19:18]};\r
+\tassign src1_addr = idx_1[2] ? idx_feld[7:3] : op_feld[22:18];\r
+\tassign stack  = {1\'b0,stack_sel[s_user],3\'b110,s_user,1\'b1};\r
+\tassign usp_1  = src1_addr[0] ? stack : {5\'b0_0110,src1_addr[1:0]};\r
+\tassign src_1l = {src_1[6:1],1\'b0};\r
+\tassign pop_1  = {2\'b00,src1_le,9\'h108};\t// SP update, DISP=0 and POST\r
+\tassign mpoi_1 = (src1_addr[4:2] == 3\'b100) | (src1_addr == 5\'h16);\t// Pointer in memory always DWord\r
+\tassign auop_s = atys[0] ? 4\'b1011 : 4\'b0010;\t// Only make effective address ?\r
+\tassign src1_tos = (op_feld[22:18] == 5\'h17) & ~atys[2] ? 2\'b11 : 2\'b00;\t// Source 1 is true TOS\r
+\t\r
+\t// Nextfield : 11=DISP read\r
+\t// Address field : Size:2 RD WR LDEA FULLACC INDEX:4 SPUPD disp_val:4 POST CLRMSW SRC2SEL:2\r
+\talways @(*)\r
+\t\tcasex (src1_addr)\t//\t RWLF   IDX    ADDR_F NEUP  SRC_REG \t\t      NEXT\r
+\t\t  // Special case which is only valid at INDEX or ""addr"" : REG -> ADDR , DISP=0 : starts immediate at read\r
+\t\t  5\'b00xxx : gen_src1 = {auop_s, idx_1,9\'h000,8\'h07,4\'h0,src1_addr[2:0],3\'b000,atys[0]};\t\r
+\t\t  // Register relativ : 0(R0)\r
+\t\t  5\'b01xxx : gen_src1 = {auop_s, idx_1,9\'h000,8\'h07,4\'h0,src1_addr[2:0],3\'b111,atys[0]};\r
+\t\t  // Memory relativ : 0(0(SB))\r
+\t\t  5\'b100xx : gen_src1 = {4\'b1011,4\'h0, 9\'h000,8\'h06,usp_1,\t\t\t  4\'b1111};\t\t\t// 1. access always full\r
+\t\t  // Immediate\r
+\t\t  5\'b10100 : gen_src1 = (src1_le == 2\'b11) ? \r
+\t\t\t\t\t\t\t\t{4\'h0,   4\'h0, 9\'h000,8\'h0B,src_x,\t\t\t  1\'b1,2\'b10,1\'b0}\t// load in DWord pieces\r
+\t\t\t\t\t\t\t  : {4\'h0,   4\'h0, 9\'h000,8\'h07,src_x,\t\t\t  1\'b1,src1_le,1\'b0};\r
+\t\t  5\'b10101 : gen_src1 = {auop_s, idx_1,9\'h002,8\'h07,src_x,\t\t\t  3\'b111,atys[0]};\t// Absolut Addressing\r
+\t\t  5\'b10110 : gen_src1 = {4\'b1011,4\'h0, 9\'h014,8\'h05,7\'h1F,\t\t\t  4\'b0001};\t\t\t// External with MOD Register +4\r
+\t\t  5\'b10111 : gen_src1 = (idx_1[2] | atys[2]) ?\t\t\t\t\t\t\t\t\t\t\t// Access class ""addr"" ?'b'\r
+\t\t\t\t\t\t\t\t{auop_s, idx_1,9\'h000,8\'h07,stack,\t\t\t  3\'b000,atys[0]}\t// 0(SP) : no TOS flag\r
+\t\t\t\t\t\t\t  : {4\'b1011,pop_1, \t  8\'h07,stack,\t\t\t  4\'b0001};\t\t\t// TOS\r
+\t\t  // Memory Space : 0(SB)\r
+\t\t  5\'b110x0 : gen_src1 = {auop_s, idx_1,9\'h000,8\'h07,5\'b0_0110,src1_addr[1:0],3\'b111,atys[0]};\t// SB+FP\r
+\t\t  5\'b11001 : gen_src1 = {auop_s, idx_1,9\'h000,8\'h07,stack,\t\t\t  3\'b111,atys[0]};\t// SP\r
+\t\t  5\'b11011 : gen_src1 = {auop_s, idx_1,9\'h001,8\'h07,src_x,\t\t\t  3\'b111,atys[0]};\t// PC relativ\r
+\t\t  default  : gen_src1 = 36\'hx_xxxx_xxxx;\t// don\'t care\r
+\t\tendcase\r
+\t\t\r
+\tassign adrd1 = {(mpoi_1 ? 2\'b10 : src1_le),gen_src1[35:19]};\t// Addressfield : 19 Bits\r
+\tassign phrd1 = gen_src1[18:11];\t\t\t\t\t// next phase\r
+\tassign rega1 = gen_src1[10:4];\t\t\t\t\t// Source 1 Register\r
+\tassign irrw1 = {4\'b0,idx_feld[2:0]};\t\t\t// Index-Register\r
+\tassign nxrd1 = gen_src1[3:0];\t\t\t\t\t// Memory/Disp/Immediate operation\r
+\tassign exr11 = {2\'b10  ,4\'b1011,4\'h0 ,9\'h080};\t// 2. access external with Mem.-Pointer + 4* Disp\r
+\tassign exr12 = {src1_le,auop_s,idx_1,9\'h000};\t// for Memory Relative and EXT in last step\r
+\t\r
+\t// Source 2 resp. Destination\r
+\t\r
+\tassign rmw = src2_flag & dest_flag;\r
+\tassign idx_2 = {1\'b0,(op_feld[17:15] == 3\'b111),op_feld[14:13]};\t// 4 bits\r
+\tassign src2_addr = idx_2[2] ? idx_feld[15:11] : op_feld[17:13];\r
+\tassign usp_2 = src2_addr[0] ? stack : {5\'b0_0110,src2_addr[1:0]};\r
+\tassign src_2l = {src_2[6:1],1\'b0};\r
+\tassign mpoi_2 = (src2_addr[4:2] == 3\'b100) | (src2_addr == 5\'h16);\t// Pointer in memory always DWord\r
+\tassign auop_d = atyd[0] ? 4\'b1011 : 4\'b0010;\t// Only make effective address ?\r
+\t\r
+\t// The next assessment processes TOS separated for PUSH and POP\r
+\tassign tos_oper =\t\t\tsrc2_flag ?\r
+\t\t\t\t\t\t\t\t{2\'b00,atyd[0],2\'b01,atyd[0],2\'b00,src2_le,7\'b1_0000_10,\t src1_tos,4\'h7,stack,3\'b0,atyd[0]}\t// POP\r
+\t\t\t\t\t\t\t  : {1\'b0,atyd[0],3\'b001,atyd[0],4\'h0,   1\'b1,2\'b10,src2_le,2\'b0,src1_tos,4\'h7,stack,3\'b0,atyd[0]};\t// PUSH\r
+\r
+\t// Nextfield : 11=DISP read\r
+\t// Address field : Size:2 RD WR LDEA FULLACC INDEX:4 SPUPD disp_val:4 POST CLRMSW SRC2SEL:2\r
+\talways @(*)\r
+\t\tcasex (src2_addr)\t//\t RW:W  RW:R  LF    IDX   ADDR_F NEUP   SRC_REG          NEXT\r
+\t\t  // Special case which is only valid at INDEX or ""addr"" : REG -> ADDR , DISP=0 : starts immediate at read\r
+\t\t  5\'b00xxx : gen_src2 = {1\'b0,atyd[0],auop_d,     idx_2,9\'h000,4\'h7,4\'h0,src2_addr[2:0],3\'b000,atyd[0]};\t\r
+\t\t  // Register relativ : 0(R0)\r
+\t\t  5\'b01xxx : gen_src2 = {1\'b0,atyd[0],auop_d,     idx_2,9\'h000,4\'h7,4\'h0,src2_addr[2:0],3\'b111,atyd[0]};\r
+\t\t  // Memory relativ : 0(0(SB))\r
+\t\t  5\'b100xx : gen_src2 = {2\'b10,2\'b10,2\'b11,4\'h0, 9\'h000,4\'h6,usp_2,\t\t4\'b1111};\t// 1. access always full\r
+\t\t  // Immediate\r
+\t\t  5\'b10100 : gen_src2 = (src2_le == 2\'b11) ? \r
+\t\t\t\t\t\t\t\t{2\'b00,2\'b00,2\'b00,4\'h0, 9\'h000,4\'hB,src_x,\t\t1\'b1,2\'b10,1\'b0}\t// load in DWord pieces\r
+\t\t\t\t\t\t\t  : {2\'b00,2\'b00,2\'b00,4\'h0, 9\'h000,4\'h7,src_x,\t\t1\'b1,src2_le,1\'b0};\r
+\t\t  5\'b10101 : gen_src2 = {1\'b0,atyd[0],auop_d,     idx_2,9\'h002,4\'h7,src_x,\t\t3\'b111,atyd[0]};\t// Absolut with special coding\r
+\t\t  5\'b10110 : gen_src2 = {2\'b10,2\'b10,2\'b11,4\'h0, 9\'h014,4\'h5,7\'h1F,\t\t4\'b0001};\t// External with MOD Register +4\r
+\t\t  5\'b10111 : gen_src2 = (idx_2[2] | rmw | atyd[2]) ?\r
+\t\t\t\t\t\t\t\t{1\'b0,atyd[0],auop_d, idx_2,7\'b0_0000_00,src1_tos,4\'h7,stack,\t3\'b000,atyd[0]}\t// 0(SP) : TOS + DISP=0\r
+\t\t\t\t\t\t\t  : tos_oper;\t// TOS : 2 cases for PUSH and POP\r
+\t\t  // Memory Space\r
+\t\t  5\'b110x0 : gen_src2 = {1\'b0,atyd[0],auop_d,     idx_2,9\'h000,4\'h7,5\'b0_0110,src2_addr[1:0],3\'b111,atyd[0]};\r
+\t\t  5\'b11001 : gen_src2 = {1\'b0,atyd[0],auop_d,     idx_2,9\'h000,4\'h7,stack,\t\t3\'b111,atyd[0]};\r
+\t\t  5\'b11011 : gen_src2 = {1\'b0,atyd[0],auop_d,     idx_2,9\'h001,4\'h7,src_x,\t\t3\'b111,atyd[0]};\t// PC relativ\r
+\t\t  default  : gen_src2 = 34\'hx_xxxx_xxxx;\t// don\'t care\r
+\t\tendcase\r
+\t\t\r
+\tassign adrd2 = {(mpoi_2 ? 2\'b10 : src2_le),gen_src2[31:15]};\r
+\tassign adwr2 = {(mpoi_2 ? 2\'b10 : src2_le),gen_src2[33:32],gen_src2[29:15]};\r
+\tassign phrd2 = {4\'h1,gen_src2[14:11]};\t\t\t\t// Phase for Read Source 2\r
+\tassign phwr2 = {4\'h2,gen_src2[14:11]};\t\t\t\t// Phase for Write Destination\r
+\tassign rega2 = gen_src2[10:4];\r
+\tassign nxrw2 = gen_src2[3:0];\r
+\tassign irrw2 = {4\'b0,idx_feld[10:8]};\r
+\tassign re_wr = {src2_le,4\'b0101,4\'h0, 9\'h003};\t\t// REUSE Address : Write of rmw\r
+\tassign exr22 = {src2_le,atyd[0],1\'b0,1\'b1,atyd[0],idx_2,9\'h000};\t// for Memory Relative and EXT in last step\r
+\tassign exw22 = {src2_le,1\'b0,atyd[0],1\'b1,atyd[0],idx_2,9\'h000};\t// for Memory Relative and EXT in last step\r
+\t\r
+\t// Special case :\r
+\t\r
+\tassign quei1 = acc1 ? imme : src_1l;\t// 8B passing either from register or from extern\r
+\t// 8B is requested from both operands but only to certain times\r
+\tassign qword = (phase_reg[7:4] != 4\'h0) ? (src2_le == 2\'b11) :\t(src1_le == 2\'b11);\r
+\tassign quet1 = acc1 ? temp_h : src_1;\t// select source during calculation\r
+\t\r
+\t// Output data of state machine\t\r
+\t//\t\t\t\t\t\t\tLOAD if\t PULS if\tsimple\r
+\t//\t\t\t\t\tNEXT -> ENABLE\t ENABLE\t\tout\r
+\t//  [66:48] 19\tADDR : \t\t\tX\t\t\t\t\t\t; Op-length REUSE RD/WR etc.\r
+\t//\t[47:40]\t 8\tnew phase\t\tX\r
+\t//\t[39:33]  7\tSRC1\t\t\t\t\t\t\tX\r
+\t//\t[32:26]\t 7\tSRC2\t\t\t\t\t\t\tX\r
+\t//\t   [25]\t 1\tWREN\t\t\t\t\tX\r
+\t//\t[24:19]\t 6\tDEST\t\t\tX\r
+\t// \t [18:8] 11\tOPER\t\t\tX\r
+\t//\t  [7:6]\t 2\tSTART\t\t\t\t\tX\r
+\t//\t  [5:4]  2\tLD_OUT\t\t\t\t\tX\r
+\t//  \t[3]  1\tID Load\t\t\tX\r
+\t//\t  [2:1]\t 2\tID Type \t\tX\t\t\t\t\t\t; 0 = DISP\r
+\t//\t\t[0]  1\tMEM Access\t\tX\r
+\r
+\t// State\t acc2-src2_flag-dest_flag\r
+\t// no SRC2  \tx\t\t0\t\tx\r
+\t// SRC2=REG\t\t0\t\t1\t\t0\t; CMP+TBIT\r
+\t// SRC2=REG\t\t0\t\t1\t\t1\t; all else\r
+\t// SRC2=MEM\t\t1\t\t1\t\t0\t; CMP+TBIT\r
+\t// SRC2=MEM\t\t1\t\t1\t\t1\t; all else\r
+\t\r
+\t// Input data for state machine\r
+\r
+\t//\t8 phase_reg : \tphase of state machine\r
+\t//\t2 otype :\t\tOpcode type\r
+\t\r
+\t//\t1 idx :\t\t\tIndex is available : 1 or 2 , only PHASE_0\r
+\t//\t1 short_op :\tshort opcodes like ADDQ\r
+\t//\t1 long :\t\t""long"" opcode\r
+\t//\t1 qword :\t\t8B access at Source (Exception DEI+MEI)\r
+\r
+\t//\t1 acc1 :\t\tReg/Extern SRC1\r
+\t//\t1 acc2 :\t\tReg/Extern SRC2\r
+\t//\t1 src2_flag :\tthe 2. operand is being read\r
+\t//\t1 dest_flag :\tthere is a target operand : only CMP and TBIT have none\r
+\t\r
+\tassign phase_ein = abbruch ? 8\'h00 : phase_reg;\r
+\t\r
+\talways @(*)\t\t//\t\t   ""_""\t\t\t\t\t\t ""_""\r
+\t\tcasex ({phase_ein,otype, idx,short_def,long,qword, acc1,acc2,src2_flag,dest_flag})\r
+ {8\'h00,10\'b00_1xxx_xxxx}:\t// Index must be loaded : phase 2 : in any case load TEMP for Short-Op and generate LD_OUT\r
+\t\t\t\t\t\t\tnew_op = short_op ?\t// \t\t\t\t\t\t\t\t\t\t   \tSTART LD_OUT\r
+\t\t\t\t\t\t\t\t\t {addr_nop,8\'h02, imme, src_x, 1\'b1,temp_h,\t\top_sho,\t2\'b00,2\'b10,\t1\'b1,n_idx,1\'b0}\r
+\t\t\t\t\t\t\t\t   : {addr_nop,8\'h02, src_1,src_1l,1\'b0,dest_x,\t\topera,\t2\'b00,~src2_flag,2\'b1_1,n_idx,1\'b0};\r
+ {8\'h00,10\'b00_01xx_x0xx}:\t// Short-Op to register, LD_OUT because of CMPQ\r
+\t\t\t\t\t\t\tnew_op = {addr_nop,goacb, imme, src_2,dest_flag,dest_r,\topera,\t2\'b00,2\'b10,\t4\'h0};\r
+ {8\'h00,10\'b00_01xx_x11x}:\t// Short-Op : external operand read : SRC2 ! Data in TEMP ! Here no Index\r
+\t\t\t\t\t\t\tnew_op = {adrd2,   phrd2, imme, rega2, 1\'b1,temp_h,\t\top_mov,\t2\'b00,2\'b00,\tnxrw2};\r
+ {8\'h00,10\'b00_01xx_x10x}:\t// MOVQ to Mem\r
+\t\t\t\t\t\t\tnew_op = {adwr2,   phwr2, imme, rega2, 1\'b0,dest_x,\t\topera,\t2\'b00,2\'b10,\tnxrw2};\r
+ {8\'h00,10\'b00_0000_00xx}:\t// simple register operation : dest_flag controls WREN, LD_OUT for CMP\r
+\t\t\t\t\t\t\tnew_op = {addr_nop,dowait,src_1,src_2, dest_flag,dest_r,opera,\t2\'b00,2\'b10,\t4\'h0};\r
+ {8\'h00,10\'b00_0001_00xx}:\t// ""simple"" Reg-Op of 8B, phase 8 after 2. DWord , not via LONG-path\r
+\t\t\t\t\t\t\tnew_op = {addr_nop,8\'h08, src_1,src_x, 1\'b1,dest_r,\t\topera,\t2\'b00,2\'b00,\t4\'h0};\r
+ {8\'h00,10\'b00_0010_00xx}:\t// long register operation i.e. DIV - phase 31\r
+\t\t\t\t\t\t\tnew_op = {addr_nop,8\'h1F, src_1,src_2, wlor,dest_r,\t\topera,\t2\'b11,2\'b00,\t4\'h0};\r
+ {8\'h00,10\'b00_0011_001x}:\t// long register operation with QWORD - phase 26 then wait\r
+\t\t\t\t\t\t\tnew_op = {addr_nop,8\'h1A, src_1,src_2, 1\'b0,dest_r,\t\topera,\t2\'b01,2\'b00,\t4\'h0};\r
+ {8\'h00,10\'b00_00xx_1xxx}:\t// Source 1 in memory - first to read , here no Index\r
+\t\t\t\t\t\t\tnew_op = {adrd1,   phrd1, src_x,rega1, 1\'b0,dest_x,\t\topera,\t2\'b00,2\'b00,\tnxrd1};\r
+ {8\'h00,10\'b00_00xx_011x}:\t// Source 2 in memory - first to read (Source 1 in register)\r
+\t\t\t\t\t\t\tnew_op = {adrd2,   phrd2, src_x,rega2, 1\'b0,dest_x,\t\topera,\t2\'b00,2\'b00,\tnxrw2};\r
+ {8\'h00,10\'b00_0000_0101}:\t// Source 1 store in Dest : ""pass through"" for MOV,NEG,ABS\r
+\t\t\t\t\t\t\tnew_op = {adwr2,   phwr2, src_1,rega2, 1\'b0,dest_x,\t\topera,\t2\'b00,2\'b10,\tnxrw2};\r
+ {8\'h00,10\'b00_0001_0101}:\t// Source 1 store in Dest : ""pass through"" for MOV,NEG,ABS for Long operands\r
+\t\t\t\t\t\t\tnew_op = //(op_feld[17:13] == 5\'h17) ?\t// TOS : special case , first 8B out of Reg and then read SP\r
+\t\t\t\t\t\t\t\t\t {addr_nop,8\'h1C, src_1,src_1l,1\'b0,dest_x,\t\topera,\t2\'b00,2\'b11,\t4\'h0};\r
+ {8\'h00,10\'b00_0010_0101}:\t// SRC1 -> DEST with short operands \r
+\t\t\t\t\t\t\tnew_op = {addr_nop,8\'h1F, src_1,src_x, 1\'b0,dest_r,\t\topera,\t2\'b11,2\'b00,\t4\'h0};\r
+ {8\'h00,10\'b00_0011_0x01}:\t// SRC1 -> DEST i.e. ROUNDLi\r
+\t\t\t\t\t\t\tnew_op = {addr_nop,8\'h1F, src_1,src_1l,wlor,dest_r,\t\topera,\t2\'b11,2\'b00,\t4\'h0};\r
+\r
+\t\t// Phase 2 : after read of Index nearly everything is repeated from PHASE_0\r
+ {8\'h02,10\'bxx_x1xx_x11x}:\t// Short-Op : external operand read\r
+\t\t\t\t\t\t\tnew_op = {adrd2,   phrd2, irrw2,rega2, 1\'b0,dest_x,\t\topera,\t2\'b00,2\'b00,\tnxrw2};\r
+ {8\'h02,10\'bxx_x1xx_x101}:\t// MOVQ to Mem, data is in Out-Register\r
+\t\t\t\t\t\t\tnew_op = {adwr2,   phwr2, irrw2,rega2, 1\'b0,dest_x,\t\topera,\t2\'b00,2\'b00,\tnxrw2};\r
+ {8\'h02,10\'bxx_x0xx_1xxx}:\t// Source 1 in memory - first to read\r
+\t\t\t\t\t\t\tnew_op = {adrd1,   phrd1, irrw1,rega1, 1\'b0,dest_x,\t\topera,\t2\'b00,2\'b00,\tnxrd1};\r
+ {8\'h02,10\'bxx_x0xx_011x}:\t// Source 2 in memory - first to read\r
+\t\t\t\t\t\t\tnew_op = {adrd2,   phrd2, irrw2,rega2, 1\'b0,dest_x,\t\topera,\t2\'b00,2\'b00,\tnxrw2};\r
+ {8\'h02,10\'bxx_x00x_0101}:\t// Source 1 store in Dest : ""pass through"" , data is already in Out-Register\r
+\t\t\t\t\t\t\tnew_op = {adwr2,   phwr2, irrw2,rega2, 1\'b0,dest_x,\t\topera,\t2\'b00,2\'b00,\tnxrw2};\r
+ {8\'h02,10\'bxx_x010_0101}:\t// SRC1 -> DEST with short operands\r
+\t\t\t\t\t\t\tnew_op = {addr_nop,8\'h1F, src_1,src_x, 1\'b0,dest_x,\t\topera,\t2\'b11,2\'b00,\t4\'h0};\r
+ {8\'h02,10\'bxx_x011_0101}:\t// SRC1 -> DEST i.e. ROUNDLi \r
+\t\t\t\t\t\t\tnew_op = {addr_nop,8\'h1F, src_1,src_1l,1\'b0,dest_x,\t\topera,\t2\'b11,2\'b00,\t4\'h0};\r
+\r
+\t// +++++++++++++++++  SRC1 operand loading  +++++++++++++++++++\r
+\r
+\t\t// Phase 5 : wait for data and Disp2 for External addressing : part 2 EA = (MOD+4)+4*DISP1\r
+\t\t//\t\tnext phase fix : 6\r
+ {8\'h05,10\'bxx_xxxx_xxxx}:\tnew_op = {exr11,   8\'h06, src_x,imme , 1\'b0,dest_x,\t\topera,\t2\'b00,2\'b00,\t4\'b1111};\r
+\t\t// Phase 6 : Memory-Pointer for Memory Relative and last access External\r
+\t\t//\t\tnext phase fix : 7 , add Index\r
+ {8\'h06,10\'bxx_xxxx_xxxx}:\tnew_op = {exr12,   8\'h07, irrw1,imme , 1\'b0,dest_x,\t\topera,\t2\'b00,2\'b00,\t3\'b111,atys[0]};\r
+\r
+\t\t// Phase 7 : wait for final data , direct from PHASE_0 if TOS without Index\r
+\t\t//\t\tnext phase : if 8B data phase 8 is neccessary\r
+\t\t// if SRC2=REG execution started (otherwise store data in TEMP) and PHASE_0\r
+ {8\'h07,10\'bxx_xx00_x0xx}:\t// into Register , short operation execution , but LD_OUT for PSR Update ! dest_flag => WREN\r
+\t\t\t\t\t\t\tnew_op = {addr_nop,endea, imme, src_2, dest_flag,dest_r,opera,\t2\'b00,2\'b10,\tdiacb};\r
+ {8\'h07,10\'bxx_xx01_x0xx}:\t// into Reg but with a step om between for ABSL etc. : phase 8\r
+\t\t\t\t\t\t\tnew_op = {addr_nop,8\'h08, imme, src_x, 1\'b1,dest_r,\t\topera,\t2\'b00,2\'b00,\t4\'h0};\r
+ {8\'h07,10\'bxx_xx10_x0xx}:\t// execute long operation , wait in phase 31\r
+\t\t\t\t\t\t\tnew_op = {addr_nop,8\'h1F, imme, src_2, wlor,dest_r,\t\topera,\t2\'b11,2\'b00,\t4\'h0};\r
+ {8\'h07,10\'bxx_xx11_xx0x}:\t// execute long operation : 2. operand only Dest , load LSD , phase 24 , wait in phase 31\r
+\t\t\t\t\t\t\tnew_op = {addr_nop,8\'h18, imme, src_x, 1\'b1,temp_l,\t\top_mov,\t2\'b01,2\'b00,\t4\'h0};\r
+ {8\'h07,10\'bxx_xx11_x01x}:\t// lange Operation ausfuehren , LSD laden , phase 25 , warten in phase 31\r
+\t\t\t\t\t\t\tnew_op = {addr_nop,8\'h19, imme, src_2, 1\'b0,dest_r,\t\topera,\t2\'b01,2\'b00,\t4\'h0};\r
+ {8\'h07,10\'bxx_xxx0_x11x}:\t// Data into TEMP , read 2. operand , is there Index ? Yes -> phase 15\r
+\t\t\t\t\t\t\tnew_op = idx_2[2] ?\r
+\t\t\t\t\t\t\t\t\t {addr_nop,8\'h0F, imme, src_x, 1\'b1,temp_h,\t\top_mov,\t2\'b00,2\'b00,\t4\'h0}\r
+\t\t\t\t\t\t\t\t   : {adrd2,   phrd2, imme, rega2, 1\'b1,temp_h,\t\top_mov,\t2\'b00,2\'b00,\tnxrw2};\r
+ {8\'h07,10\'bxx_xxx1_x11x}:\t// 8B data in TEMP , step in between then 2. Op read : phase 10 - can only be ""long"" operation\r
+\t\t\t\t\t\t\tnew_op = {addr_nop,8\'h0A, imme, src_x, 1\'b1,temp_h,\t\top_mov,\t2\'b00,2\'b00,\t4\'h0};\r
+ {8\'h07,10\'bxx_xx00_x101}:\t// something like ABSi , execute and store (LD_OUT)\r
+\t\t\t\t\t\t\tnew_op = idx_2[2] ?\r
+\t\t\t\t\t\t\t\t\t {addr_nop,8\'h10, imme, src_x, 1\'b0,dest_x,\t\topera, \t2\'b00,2\'b10,\t4\'h0}\r
+\t\t\t\t\t\t\t\t   : {adwr2,   phwr2, imme, rega2, 1\'b0,dest_x,\t\topera,\t2\'b00,2\'b10,\tnxrw2};\r
+ {8\'h07,10\'bxx_xx01_x101}:\t// ABS etc. : LSD data over SRC2 in 2. OUT-Reg , MSD data see opcode ABS/NEG/MOV , phase 9\r
+\t\t\t\t\t\t\tnew_op = {addr_nop,8\'h09, imme, src_x, 1\'b0,dest_x,\t\topera,\t2\'b00,2\'b10,\t4\'h0};\r
+ {8\'h07,10\'bxx_xx10_x101}:\t// opcodes like MOVFL\r
+\t\t\t\t\t\t\tnew_op = {addr_nop,8\'h1F, imme, src_x, 1\'b0,dest_x,\t\topera,\t2\'b11,2\'b00,\t4\'h0};\r
+\r
+\t\t// Phase 8 : 2. part of 64 bit data : can be reached from PHASE_0 if 8B data\r
+ {8\'h08,10\'bxx_xxxx_xxxx}:\tnew_op = {addr_nop,endea, quei1,src_x, 1\'b1,dest_rl,\top_mov,\t2\'b00,2\'b00,\tdiacb};\r
+\t\t// Phase 9 : step in between to get data in OUT-Reg Low , SRC1 is not possible\r
+ {8\'h09,10\'bxx_xxxx_xxxx}:\t// afterwards to data write\r
+\t\t\t\t\t\t\tnew_op = {addr_nop,8\'h10, src_x,imme , 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b01,\t4\'h0};\r
+\t\t// Phase 10 : LSD data write in TEMP , source can be IMME data to\r
+ {8\'h0A,10\'bxx_xxxx_xxxx}:\t// 8B , after TEMP there can only be a 2. operand\r
+\t\t\t\t\t\t\tnew_op = idx_2[2] ?\r
+\t\t\t\t\t\t\t\t\t {addr_nop,8\'h0F, imme, src_x, 1\'b1,temp_l,\t\top_mov,\t2\'b00,2\'b00,\t4\'h0}\r
+\t\t\t\t\t\t\t\t   : {adrd2,   phrd2, imme, rega2, 1\'b1,temp_l,\t\top_mov,\t2\'b00,2\'b00,\tnxrw2};\r
+\r
+\t\t// Phase 11 : wait for 8B IMME data : switch over at address decoder , qword flag is for sure ""1""\r
+ {8\'h0B,10\'bxx_xx0x_x0xx}:\t// into Reg with step in between for ABSL etc. : phase 12\r
+\t\t\t\t\t\t\tnew_op = {addr_nop,8\'h0C, imme, src_x, 1\'b1,dest_r,\t\topera,\t2\'b00,2\'b00,\t4\'b1100};\r
+ {8\'h0B,10\'bxx_xx1x_x01x}:\t// execute long operation , load LSD , phase 25 , wait in phase 31\r
+\t\t\t\t\t\t\tnew_op = {addr_nop,8\'h19, imme, src_2, 1\'b0,dest_r,\t\topera,\t2\'b01,2\'b00,\t4\'b1100};\r
+ {8\'h0B,10\'bxx_xxxx_x11x}:\t// 8B data into TEMP , step in between then read 2. Op : phase 10 - can only be ""long"" operation\r
+\t\t\t\t\t\t\tnew_op = {addr_nop,8\'h0A, imme, src_x, 1\'b1,temp_h,\t\top_mov,\t2\'b00,2\'b00,\t4\'b1100};\r
+ {8\'h0B,10\'bxx_xx0x_x10x}:\t// ABS etc. : LSD data via SRC2 into 2. OUT-Reg , MSD data see opcode ABS/NEG/MOV , phase 9\r
+\t\t\t\t\t\t\tnew_op = {addr_nop,8\'h09, imme, src_x, 1\'b0,dest_x,\t\topera,\t2\'b00,2\'b10,\t4\'b1100};\r
+ {8\'h0B,10\'bxx_xx1x_xx0x}:\t// MOVLF with 8B IMME data ? Must be possible, the end in phase 24 like SRC1=MEM\r
+\t\t\t\t\t\t\tnew_op = {addr_nop,8\'h18, imme, src_x, 1\'b1,temp_l,\t\top_mov,\t2\'b01,2\'b00,\t4\'b1100};\r
+\t\t// Phase 12 : wait for 2. part of 64 bit IMME data : after phase 0\r
+ {8\'h0C,10\'bxx_xxxx_xxxx}:\tnew_op = {addr_nop,endea, imme ,src_x, 1\'b1,dest_rl,\top_mov,\t2\'b00,2\'b00,\tdiacb};\r
+\r
+\t\t// Phase 15 : secure in TEMP with Index continue and read 2. operand\r
+ {8\'h0F,10\'bxx_xxxx_xxxx}:\tnew_op = {adrd2,   phrd2, irrw2,rega2, 1\'b0,dest_x,\t\topera,\t2\'b00,2\'b00,\tnxrw2};\r
+\t\t// Phase 16 : after LD_OUT continue with Index and store 1. operand\r
+ {8\'h10,10\'bxx_xxxx_xxxx}:\tnew_op = {adwr2,   phwr2, irrw2,rega2, 1\'b0,dest_x,\t\topera,\t2\'b00,2\'b00,\tnxrw2};\r
+\r
+\t// +++++++++++++++++  SRC2 operand loading : phase SRC1 + 16  +++++++++++++++++++\r
+\r
+\t\t// Phase 21 : wait for data and Disp2 for external addressing : part 2 EA = (MOD+4)+4*DISP1\r
+\t\t//\t\tnext phase fix : 22\r
+ {8\'h15,10\'bxx_xxxx_xxxx}:\tnew_op = {exr11,   8\'h16, src_x,imme , 1\'b0,dest_x,\t\topera,\t2\'b00,2\'b00,\t4\'b1111};\r
+\t\t// Phase 22 : Memory-Pointer for Memory Relative and last access external\r
+\t\t//\t\tnext phase fix : 23 , add Index\r
+ {8\'h16,10\'bxx_xxxx_xxxx}:\tnew_op = {exr22,   8\'h17, irrw2,imme , 1\'b0,dest_x,\t\topera,\t2\'b00,2\'b00,\t3\'b111,atyd[0]};\r
+\r
+\t\t// Phase 23 : wait for final data , direct from PHASE_0 if TOS without Index\r
+\t\t//\t\tnext phase : if 8B data phase 24 is used\r
+ {8\'h17,10\'bxx_xx0x_xxx1}:\t// execute short operation and write data into memory , no WREN -> phase 39 ACC_DONE\r
+\t\t\t\t\t\t\tnew_op = {re_wr,   8\'h27, quet1,imme , 1\'b0,dest_r,\t\topera,\t2\'b00,2\'b10,\t4\'b0001};\r
+ {8\'h17,10\'bxx_xx0x_xxx0}:\t// execute short operation , no WREN -> phase 0 , CMP(+TBIT)\r
+\t\t\t\t\t\t\tnew_op = {addr_nop,endea, quet1,imme , 1\'b0,dest_r,\t\topera,\t2\'b00,2\'b10,\tdiacb};\r
+ {8\'h17,10\'bxx_xx10_xxxx}:\t// execute long operation , wait in phase 31\r
+\t\t\t\t\t\t\tnew_op = {addr_nop,8\'h1F, quet1,imme , wlor,dest_r,\t\topera,\t2\'b11,2\'b00,\t4\'h0};\r
+ {8\'h17,10\'bxx_xx11_xxxx}:\t// execute long operation , load LSD in phase 24\r
+\t\t\t\t\t\t\tnew_op = {addr_nop,8\'h18, quet1,imme , 1\'b0,dest_r,\t\topera,\t2\'b01,2\'b00,\t4\'h0};\r
+\t\t// Phase 24 : load 2. part of 64 bit data : with and without wait - from 28 the phase waits , from 23 not\r
+ {8\'h18,10\'bxx_xxxx_0xxx}:\t// execute long operation , wait in phase 31\r
+\t\t\t\t\t\t\tnew_op = {addr_nop,8\'h1F, src_1l,imme, wlor,dest_r,\t\topera,\t2\'b10,2\'b00,\t4\'h0};\r
+ {8\'h18,10\'bxx_xxxx_1xxx}:\t// execute long operation , wait in phase 31 , data from TEMP, used also for ROUNDLi\r
+\t\t\t\t\t\t\tnew_op = {addr_nop,8\'h1F, rtmpl,imme,  wlor,dest_r,\t\topera,\t2\'b10,2\'b00,\t4\'h0};\r
+\t\t// Phase 25 : load 2. part of 64 bit data : SRC1 from memory and SRC2 from Reg\r
+ {8\'h19,10\'bxx_xxxx_xxxx}:\t// execute long operation , wait in phase 31\r
+\t\t\t\t\t\t\tnew_op = {addr_nop,8\'h1F, imme, src_2l,wlor,dest_r,\t\topera,\t2\'b10,2\'b00,\t4\'h0};\r
+\t\t// Phase 26 : load 2. part of 64 bit data : SRC1 from Reg and SRC2 from Reg\r
+ {8\'h1A,10\'bxx_xxxx_xxxx}:\t// execute long operation , wait in phase 31\r
+\t\t\t\t\t\t\tnew_op = {addr_nop,8\'h1F, src_1l,src_2l,wlor,dest_r,\topera,\t2\'b10,2\'b00,\t4\'h0};\r
+\r
+\t\t// Phase 27 : wait for 8B IMME data : switch over at address decoder , qword flag is for sure ""1""\r
+ {8\'h1B,10\'bxx_xxxx_xxxx}:\t// execute long operation , load LSD in phase 24\r
+\t\t\t\t\t\t\tnew_op = {addr_nop,8\'h18, quet1,imme , 1\'b0,dest_r,\t\topera,\t2\'b01,2\'b00,\t4\'b1100};\r
+\t\t\r
+\t// +++++++++++++++++  special case  ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\t\t// Phase 28 : TOS with 8B SRC1 operand , no Index ! Jump to phase 39\r
+ {8\'h1C,10\'bxx_xxxx_xxxx}:\t// store Source 1 in Dest : ""pass through"" for MOV,NEG,ABS\r
+\t\t\t\t\t\t\tnew_op = {adwr2,   phwr2, src_x,rega2, 1\'b0,dest_x,\t\topera,\t2\'b00,2\'b00,\tnxrw2};\r
+\t// +++++++++++++++++  close operation : write out DEST , TOS update  +++++++++++++++++++\r
+\r
+\t\t// Phase 31 : wait for DONE of long operation\r
+ {8\'h1F,10\'bxx_xxxx_xxx0}:\t// CMP done -> phase 0\r
+\t\t\t\t\t\t\tnew_op = {addr_nop,8\'h00, src_x,src_x, 1\'b0,dest_r,\t\topera,\t2\'b00,2\'b10,\t4\'h0};\t// no ACB\r
+ {8\'h1F,10\'bxx_xxxx_x0x1}:\t// operation closed , data into register\r
+\t\t\t\t\t\t\tnew_op = {addr_nop,8\'h00, src_x,src_x, 1\'b0,dest_r,\t\topera,\t2\'b00,2\'b00,\t4\'h0};\t// no ACB\r
+ {8\'h1F,10\'bxx_xxxx_x101}:\t// operation closed , data into memory - first calculate address phase 32+x\r
+\t\t\t\t\t\t\tnew_op = {adwr2,   phwr2, irrw2,rega2, 1\'b0,dest_r,\t\topera,\t2\'b00,2\'b00,\tnxrw2};\r
+ {8\'h1F,10\'bxx_xxxx_x111}:\t// operation closed , data into memory - address reuse phase 39 ACC_DONE\r
+\t\t\t\t\t\t\tnew_op = {re_wr,   8\'h27, src_x,src_x, 1\'b0,dest_r,\t\topera,\t2\'b00,2\'b00,\t4\'b0001};\r
+\t\t  \r
+\t\t// Destination address calculate\r
+\t\t// Phase 37 : wait for data and Disp2 for External addressing : part 2 EA = (MOD+4)+4*DISP1\r
+\t\t//\t\tnext phase fix : 38\r
+ {8\'h25,10\'bxx_xxxx_xxxx}:\tnew_op = {exr11,   8\'h26, src_x,imme , 1\'b0,dest_x,\t\topera,\t2\'b00,2\'b00,\t4\'b1111};\r
+\t\t// Phase 38 : Memory-Pointer for Memory Relative and letzter Zugriff External\r
+\t\t//\t\tnext phase fix : 39 , add Index and write\r
+ {8\'h26,10\'bxx_xxxx_xxxx}:\tnew_op = {exw22,   8\'h27, irrw2,imme , 1\'b0,dest_x,\t\topera,\t2\'b00,2\'b00,\t4\'b1111};\r
+\r
+\t\t// Phase 39 : wait for ACC_DONE : consequent numbering : 7+32\r
+ {8\'h27,10\'bxx_xxxx_xxxx}:\t// now operation closed , only ACB could follow\r
+\t\t\t\t\t\t\tnew_op = {addr_nop,endea, src_x,src_x, 1\'b0,dest_x,\t\topera,\t2\'b00,2\'b00,\tdiacb};\r
+\t\t\t\t\t\t\t\r
+\t// +++++++++++++++ special case : ACB to Reg is to fast ! One wait cycle for ZERO-Flag\r
+ {8\'h28,10\'bxx_xxxx_xxxx}:\tnew_op = {addr_nop,8\'h01,src_x, src_x, 1\'b0,dest_x,\t\topera,\t2\'b00,2\'b00,\t4\'b1110};\r
+\t\t  \r
+\t// +++++++++++++++  The other opcodes are following  ++++++++++++++++++\r
+\r
+ {8\'h00,10\'b01_xxxx_xxxx}:\tnew_op = {new_addr,new_ph,new_regs,\t   1\'b0,dest_x,\t\top_mov,\t\t\t\t\tnew_nx};\t// 1 Byte Opcodes\r
+\r
+\t\t// Phase 1 : used for Bcond and ACB :\r
+ {8\'h01,10\'bxx_xxxx_xxxx}:\tnew_op = (ex_br_op[1] | jsr_flag) ? \t// BSR or JSR ?\r
+\t\t\t\t\t\t\t\t\t {push_op, 8\'h27, imme, stack, 1\'b0,dest_x,\t\top_mov, 2\'b00,2\'b10,\t4\'b0001}\t// wait at end\r
+\t\t\t\t\t\t\t\t   : {addr_nop,8\'h00, src_x,src_x, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b00,\t4\'h0};\r
+ \r
+\t\t// Phase 42 : RET : read of PC from Stack and DIN via SRC1 to PC\r
+ {8\'h2A,10\'bxx_xxxx_xxxx}:  new_op = {adddisp, 8\'h2B, imme, src_x, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b00,\t4\'hE};\r
+\t\t// Phase 43 : RET : Displacement add to Stack. Attention : ""imme"" important to keep source constant for PC\r
+ {8\'h2B,10\'bxx_xxxx_xxxx}:  new_op = {save_sp, 8\'h2C, imme, src_x, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b00,\t4\'h0};\r
+\t\t// Phase 44 : RET : Update of Stack : fixed phase\r
+ {8\'h2C,10\'bxx_xxxx_xxxx}:\tnew_op = {addr_nop,8\'h00, src_x,src_x, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b00,\t4\'h0};\r
+ \r
+\t\t// Phase 45 : ENTER Entry\r
+ {8\'h2D,10\'bxx_xxxx_xxxx}:\tnew_op = {dispmin, 8\'h2E, src_x,src_x, 1\'b1,temp_l,\t\top_adr,\t2\'b00,2\'b00,\t4\'hE};\r
+\t\t// Phase 46 : ENTER Stack longer\r
+ {8\'h2E,10\'bxx_xxxx_xxxx}:\tnew_op = {save_sp ,8\'h31, src_x,src_x, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b00,\t4\'h0};\r
+\t\t// Phase 48 : SAVE/ENTER : Init phase , phases 48 & 49 very similar\r
+ {8\'h30,10\'bxx_xxxx_xxxx}:\tnew_op = save_reg ?\r
+\t\t\t\t\t\t\t\t\t {push_op, 8\'h31, saver,stack, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b10,\t4\'h1}\t// 1. load SP=>EA\r
+\t\t\t\t\t\t\t\t   : {addr_nop,8\'h00, rtmpl,src_x,new_fp,frame[5:0],op_mov,\t2\'b00,2\'b00,\t4\'h0};\t// At ENTER FP Update\r
+\t\t// Phase 49 : SAVE/ENTER : at the same time memory access and detection of next Reg\r
+ {8\'h31,10\'bxx_xxxx_xxxx}:\tnew_op = save_reg ?\r
+\t\t\t\t\t\t\t\t\t {push_ea, 8\'h31, saver,src_x, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b10,\t4\'h1}\t// one more\r
+\t\t\t\t\t\t\t\t   : {addr_nop,8\'h00, rtmpl,src_x,new_fp,frame[5:0],op_mov,\t2\'b00,2\'b00,\t4\'h0};\t// At ENTER FP Update\r
+\r
+\t\t// Phase 50 : RESTORE/EXIT Entry\r
+ {8\'h32,10\'bxx_xxxx_xxxx}:\tnew_op = save_reg ?\r
+\t\t\t\t\t\t\t\t\t {pop_op,  8\'h33, src_x,stack, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b00,\t4\'h1}\r
+\t\t\t\t\t\t\t\t   : {pop_fp,  ppfp,  src_x,frame, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b00,\t3\'h0,new_fp};\r
+\t\t// Phase 51 : RESTORE/EXIT next reg\r
+ {8\'h33,10\'bxx_xxxx_xxxx}:\tnew_op = save_reg ?\r
+\t\t\t\t\t\t\t\t\t {next_po, 8\'h33, imme, src_x, 1\'b1,resto,\t\top_mov,\t2\'b00,2\'b00,\t4\'h1}\r
+\t\t\t\t\t\t\t\t   : {pop_fp,  ppfp,  imme, frame, 1\'b1,resto,\t\top_mov,\t2\'b00,2\'b00,\t3\'h0,new_fp};\r
+\t\t// Phase 52 : EXIT End\r
+ {8\'h34,10\'bxx_xxxx_xxxx}:\tnew_op = {addr_nop,8\'h00, imme, src_x, 1\'b1,frame[5:0],\top_mov,\t2\'b00,2\'b00,\t4\'h0};\r
+\t\t\t\t\t\t\t\t   \r
+\t\t// Phase 53 : CXP Entry : this opcode needs 12 States and 16 cycles minimum ...\r
+ {8\'h35,10\'bxx_xxxx_xxxx}:\tnew_op = {addr_nop,8\'h36, imme, src_x, 1\'b1,temp_h,\t\top_mov,\t2\'b00,2\'b00,\t4\'h0};\r
+\t\t// Phase 54 : CXP : Store Address Link table\r
+ {8\'h36,10\'bxx_xxxx_xxxx}:\tnew_op = {rdltab,  8\'h37, src_x,rtmph, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b00,\t4\'hE};\t// EA Phase : DISP read\r
+\t\t// Phase 55 : CXP : DISP is worked on, the return address => temp_l\r
+ {8\'h37,10\'bxx_xxxx_xxxx}:\tnew_op = {addr_nop,8\'h38, imme, rtmph, 1\'b1,temp_l,\t\top_mov,\t2\'b00,2\'b00,\t4\'h1};\t// Access\r
+\t\t// Phase 56 : CXP : Access to Link table => Result is MOD-Entry => store in temp_h\r
+ {8\'h38,10\'bxx_xxxx_xxxx}:\tnew_op = {addr_nop,8\'h39, imme, src_x, 1\'b1,temp_h,\t\top_mov,\t2\'b00,2\'b00,\t4\'h0};\r
+\t\t// Phase 57 : CXP : store and PUSH MOD prepare , Entry from Exception Processing\r
+ {8\'h39,10\'bxx_xxxx_xxxx}:\tnew_op = {push_op, 8\'h3A, modul,stack, 1\'b0,dest_x,\t\top_wrp,\t2\'b00,2\'b10,\t4\'h1};\r
+\t\t// Phase 58 : CXP : PUSH of MOD ongoing, PUSH PC prepare\r
+ {8\'h3A,10\'bxx_xxxx_xxxx}:\tnew_op = {ea_push, 8\'h3B, rtmpl,src_x, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b10,\t4\'h0};\r
+\t\t// Phase 59 : CXP : New EA for PC\r
+ {8\'h3B,10\'bxx_xxxx_xxxx}:\tnew_op = {save_sp, 8\'h3C, src_x,src_x, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b00,\t4\'h1};\r
+\t\t// Phase 60 : CXP : write of PC, calculate of Offset\r
+ {8\'h3C,10\'bxx_xxxx_xxxx}:\tnew_op = {rmod_8,  8\'h3D, rtmph,rtmph, 1\'b1,temp_l,\t\top_flip,2\'b00,2\'b00,\t4\'h1};\r
+\t\t// Phase 61 : CXP : read from (MOD:New+8)\r
+ {8\'h3D,10\'bxx_xxxx_xxxx}:\tnew_op = {ea_min8, 8\'h3E, imme, rtmpl, 1\'b1,temp_l,\t\top_add,\t2\'b00,2\'b00,\t4\'h0};\t// Reuse of EA\r
+\t\t// Phase 62 : CXP : EA Phase of SB read , new PC calculated\r
+ {8\'h3E,10\'bxx_xxxx_xxxx}:\tnew_op = {addr_nop,8\'h3F, rtmpl,src_x, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b00,\t4\'h1};\r
+\t\t// Phase 63 : CXP : read of SB , new PC to ICache\r
+ {8\'h3F,10\'bxx_xxxx_xxxx}:\tnew_op = {addr_nop,8\'h2F, imme, src_x, 1\'b1,6\'h1A,\t\top_mov,\t2\'b00,2\'b00,\t4\'h0};\t// SB load\r
+\t\t// Phase 47 : CXP : Last phase update of MOD prepare\r
+ {8\'h2F,10\'bxx_xxxx_xxxx}:\tnew_op = {addr_nop,8\'h00, rtmph,src_x, 1\'b1,modul[5:0],\top_mov,\t2\'b00,2\'b00,\t4\'h0};\t// MOD load\r
+\t\t\r
+\t\t// Phase 64 : RXP Entry : POP of PC , full Access\r
+ {8\'h40,10\'bxx_xxxx_xxxx}:\tnew_op = {pop_ru,  8\'h41, imme, src_x, 1\'b1,temp_h,\t\top_mov, 2\'b00,2\'b00,\t4\'h0};\r
+\t\t// Phase 65 : RXP : PC is read, next POP prepare\r
+ {8\'h41,10\'bxx_xxxx_xxxx}:\tnew_op = {adddisp, 8\'h42, src_x,src_x, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b00,\t4\'hF};\r
+\t\t// Phase 66 : RXP : DISP is addeed to Stack and MOD is read\r
+ {8\'h42,10\'bxx_xxxx_xxxx}:\tnew_op = {addr_nop,8\'h43, imme, src_x, 1\'b1,modul[5:0],\top_mov,\t2\'b00,2\'b00,\t4\'h0};\r
+\t\t// Phase 67 : RXP : MOD is new\r
+ {8\'h43,10\'bxx_xxxx_xxxx}:\tnew_op = {rmod_rxp,8\'h44, rtmph,modul, 1\'b0,dest_x,\t\top_mov, 2\'b00,2\'b00,\t4\'h1};\r
+\t\t// Phase 68 : RXP : wait for SB data, parallel SP update\r
+ {8\'h44,10\'bxx_xxxx_xxxx}:\tnew_op = {addr_nop,8\'h00, imme, src_x, 1\'b1,6\'h1A,\t\top_mov,\t2\'b00,2\'b00,\t4\'h0};\t// SB load\r
+\r
+\t\t// Phase 69 : RETI : read of ICU for End-of-Interrupt Cycle , prepare read PC from Stack\r
+ {8\'h45,10\'bxx_xxxx_xxxx}:\tnew_op = {pop_op,  8\'h46, src_x,stack, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b00,\t4\'h1};\r
+\t\t// Phase 70 : RETI/ RETT Entry : POP of PC , full Access\r
+ {8\'h46,10\'bxx_xxxx_xxxx}:\tnew_op = {pop_ru,  8\'h47, imme, src_x, 1\'b1,temp_h,\t\top_mov, 2\'b00,2\'b00,\t4\'h0};\r
+\t\t// Phase 71 : RETI/RETT : PC is read, next POP prepare\r
+ {8\'h47,10\'bxx_xxxx_xxxx}:\tnew_op = {save_sp, 8\'h48, src_x,src_x, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b00,\t4\'h1};\r
+\t\t// Phase 72 : RETI/RETT : DISP is added to Stack , PSR load and MOD is loaded if DE off\r
+ {8\'h48,10\'bxx_xxxx_xxxx}:\tnew_op = {addr_nop,8\'h49, imme, src_x, no_modul,\t\top_ldp,\t2\'b00,2\'b00,\t4\'h0};\r
+\t\t// Phase 73 : RETI/RETT : different paths\r
+ {8\'h49,10\'bxx_xxxx_xxxx}:\tnew_op = de_flag ?\r
+\t\t\t\t\t\t\t\t\t ( reti_flag ?\r
+\t\t\t\t\t\t\t\t     {addr_nop,8\'h4A, rtmph,src_x, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b00,\t4\'h0}\r
+\t\t\t\t\t\t\t\t   : {addr_nop,8\'h4B, src_x,src_x, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b00,\t4\'h0} )\r
+\t\t\t\t\t\t\t\t   : {rmod_rtt,8\'h4B, rtmph,modul, 1\'b0,dest_x,\t\top_mov, 2\'b00,2\'b00,\t4\'h1};\r
+\t\t// Phase 74 : RETI/RETT : one pause cycle if DE on\r
+ {8\'h4A,10\'bxx_xxxx_xxxx}:\tnew_op = {addr_nop,8\'h00, src_x,src_x, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b00,\t4\'h0};\r
+\t\t// Phase 75 : RETI/RETT : SB read if DE off\r
+ {8\'h4B,10\'bxx_xxxx_xxxx}:\tnew_op = reti_flag ?\r
+\t\t\t\t\t\t\t\t\t {addr_nop,8\'h00, imme, src_x, 1\'b1,6\'h1A,\t\top_mov,\t2\'b00,2\'b00,\t4\'h0}\r
+\t\t\t\t\t\t\t\t   : ( de_flag ?\r
+\t\t\t\t\t\t\t\t     {adddispn,8\'h4E, src_x,ttstak,1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b00,\t4\'hE}\r
+\t\t\t\t\t\t\t\t   : {adddispn,8\'h4E, imme, ttstak,1\'b1,6\'h1A,\t\top_mov,\t2\'b00,2\'b00,\t4\'hE} );\r
+\t\t// Phase 78 : RETT : SP update\r
+ {8\'h4E,10\'bxx_xxxx_xxxx}:\tnew_op = {save_sp, 8\'h4A, rtmph,src_x, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b00,\t4\'h0};\r
+\r
+\t// +++++++++++++++  special wait states for PSR and the Cache/MMU system  +++++++++++\r
+\t\r
+\t\t// Phase 76 : PSR in Word case simple delay of 2 cycles : 1. cycle does nothing\r
+ {8\'h4C,10\'bxx_xxxx_xxxx}:\tnew_op = {addr_nop,8\'h4D, src_x,src_x, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b00,\t4\'h0};\r
+\t\t// Phase 77 : PSR in Word case simple delay of 2 cycles : 2. cycle does Restart of instruction processing\r
+ {8\'h4D,10\'bxx_xxxx_xxxx}:\tnew_op = {addr_nop,8\'h00, src_x,src_x, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b00,\t4\'h0};\r
+\t\t// Phase 79 : Wait for INIT_DONE from Cachesystem\r
+ {8\'h4F,10\'bxx_xxxx_xxxx}:\tnew_op = (INIT_DONE | no_init) ?\r
+\t\t\t\t\t\t\t\t\t {addr_nop,8\'h4D, src_x,src_x, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b00,\t4\'h0}\r
+\t\t\t\t\t\t\t\t   : {addr_nop,8\'h4F, src_x,src_x, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b00,\t4\'h0};\r
+\t\t\t\t\t\t\t\t   \r
+\t// +++++++++++++++  Direct Exception procession similar to CXP  ++++++++++++++++++++\r
+\t\r
+\t\t// Phase 121 : CXP : store and PUSH PSR prepare , Entry of Exception Processing\r
+ {8\'h79,10\'bxx_xxxx_xxxx}:\tnew_op = {push_op, 8\'h7A, modul,stack, 1\'b0,dest_x,\t\top_wrp,\t2\'b00,2\'b10,\t4\'h1};\r
+\t\t// Phase 122 : CXP : PUSH of PSR running, PUSH PC prepare - MOD like normal Exception-Flow\r
+ {8\'h7A,10\'bxx_xxxx_xxxx}:\tnew_op = {ea_push, 8\'h7B, rtmpl,src_x, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b10,\t4\'h0};\r
+\t\t// Phase 123 : CXP : New EA for PC , Output of Interrupt-Vector and LOAD_PC generation, continue at standard exit\r
+ {8\'h7B,10\'bxx_xxxx_xxxx}:\tnew_op = {save_sp, 8\'h4A, rtmph,src_x, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b00,\t4\'h1};\r
+ \r
+\t// +++++++++++++++  here comes the general Exception Processing  ++++++++++++++++++\r
+\r
+\t\t// Phase 0 : Entry with saving of PC_ARCHI and PSR\r
+ {8\'h00,10\'b11_xxxx_xxxx}:\tnew_op = {save_pc, 8\'h80, src_x,src_x, 1\'b0,dest_x,\t\top_psr,\t2\'b00,2\'b00,\t4\'h0};\r
+\t\t// Phase 128 : different paths to three cases\r
+ {8\'h80,10\'bxx_xxxx_xxxx}:\tnew_op = abo_int ?\r
+\t\t\t\t\t\t\t\t\t {ai_next[30:4],  src_x,src_x, 1\'b1,temp_l,\t\top_adr,\t2\'b00,2\'b00,\tai_next[3:0]}\r
+\t\t\t\t\t\t\t\t   : {get_vec, 8\'h81, src_x,ibase, 1\'b1,temp_l,\t\top_adr,\t2\'b00,2\'b00,\t4\'h1};\r
+\t\t// Phase 129 : read of Exception-Vectors and store in TEMP_H , then continue at CXP if DE off\r
+ {8\'h81,10\'bxx_xxxx_xxxx}:\tnew_op = de_flag ?\r
+\t\t\t\t\t\t\t\t\t {addr_nop,8\'h79, imme, src_x, 1\'b1,temp_h,\t\top_mov,\t2\'b00,2\'b00,\t4\'h0}\r
+\t\t\t\t\t\t\t\t   : {addr_nop,8\'h39, imme, src_x, 1\'b1,temp_h,\t\top_mov,\t2\'b00,2\'b00,\t4\'h0};\r
+\t\t// Phase 130 : read of Interrupt-Vectors, Zero-Extension of Byte => TEMP_H\r
+ {8\'h82,10\'bxx_xxxx_xxxx}:\tnew_op = {addr_nop,8\'h83, imme, src_x, 1\'b1,temp_h,\t\top_zex,\t2\'b00,2\'b00,\t4\'h0};\r
+\t\t// Phase 131 : access of Exception-Vector\r
+ {8\'h83,10\'bxx_xxxx_xxxx}:\tnew_op = (type_nmi | ~ivec_flag) ?\t// NMI or non-vectored INT ?\r
+\t\t\t\t\t\t\t\t\t {get_vec, 8\'h81, src_x,ibase, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b00,\t4\'h1}\r
+\t\t\t\t\t\t\t\t   : {get_veci,8\'h81, rtmph,ibase, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b00,\t4\'h1};\r
+\t\t\r
+\t\t// Phase 132 : ABORT : store TEAR\r
+ {8\'h84,10\'bxx_xxxx_xxxx}:\tnew_op = {save_msr,8\'h85, src_x,src_x, 1\'b1,w_tear,\t\top_adr, 2\'b00,2\'b00,\t4\'h0};\r
+\t\t// Phase 133 : store MSR\r
+ {8\'h85,10\'bxx_xxxx_xxxx}:\tnew_op = (ssrc_flag | sdest_flag) ?\r
+\t\t\t\t\t\t\t\t\t {addr_nop,rrepa, src_x,src_x, 1\'b1,w_msr,\t\top_adr, 2\'b00,2\'b00,\t4\'h0}\r
+\t\t\t\t\t\t\t\t   : {get_vec ,8\'h81, src_x,ibase, 1\'b1,w_msr,\t\top_adr, 2\'b00,2\'b00,\t4\'h1};\r
+\t\t// Phase 134 : reload of pointers for string opcodes : R2 Dest\r
+ {8\'h86,10\'bxx_xxxx_xxxx}:\tnew_op = {addr_nop,8\'h87, rtmp1,src_x, 1\'b1,6\'h02,\t\top_mov, 2\'b00,2\'b00,\t4\'h0};\r
+\t\t// Phase 135 : reload of pointers for string opcodes : R1 Source\r
+ {8\'h87,10\'bxx_xxxx_xxxx}:\tnew_op = {get_vec ,8\'h81, rtmph,ibase, 1\'b1,6\'h01,\t\top_mov, 2\'b00,2\'b00,\t4\'h1};\r
+\t\t\r
+\t// +++++++++++++++++  WAIT  +++++++++++++++++++++++++++++++++\r
+ {8\'h88,10\'bxx_xxxx_xxxx}:\tnew_op = interrupt ?\r
+\t\t\t\t\t\t\t\t\t {addr_nop,8\'h00, src_x,src_x, 1\'b0,dest_x,\t\top_mov, 2\'b00,2\'b00,\t4\'h0}\t// wait ...\r
+\t\t\t\t\t\t\t\t   : {addr_nop,8\'h88, src_x,src_x, 1\'b0,dest_x,\t\top_mov, 2\'b00,2\'b00,\t4\'h0};\t// Loop\r
+ \r
+\t// +++++++++++++++++  FLAG  +++++++++++++++++++++++++++++++++\r
+ {8\'h89,10\'bxx_xxxx_xxxx}:\tnew_op = flag ?\r
+\t\t\t\t\t\t\t\t\t {save_pc, 8\'h80, src_x,src_x, 1\'b0,dest_x,\t\top_psr,\t2\'b00,2\'b00,\t4\'h0}\t// TRAP\r
+\t\t\t\t\t\t\t\t   : {addr_nop,8\'h00, src_x,src_x, 1\'b0,dest_x,\t\top_mov, 2\'b00,2\'b00,\t4\'h0};\t// continue\r
+\t\t\t\t\t\t\t\t   \r
+\t// +++++++++++++++++  The Opcodes of Gruppe 2  +++++++++++++++\r
+\t\r
+ {8\'h00,10\'b10_0xxx_xxxx}:\tnew_op = state_0;\r
+\t// Now the case with Index , the Long Operand is copied to OUT\r
+ {8\'h00,10\'b10_1xxx_xxxx}:\tnew_op = {addr_nop,8\'h50, src_1,src_1l,1\'b0,dest_x,\t\topera,\t2\'b00,~src2_flag,2\'b1_1,n_idx,1\'b0};\r
+\t\r
+ {8\'h5x,10\'bxx_xxxx_xxxx}:\tnew_op = state_group_50;\t// Gruppe 2 Opcodes\r
+ {8\'h6x,10\'bxx_xxxx_xxxx}:\tnew_op = state_group_60;\t// Gruppe 2 Opcodes\r
+ \r
+ // that is only for CVTP :\r
+ {8\'h73,10\'bxx_xxxx_x0xx}:\tnew_op = {addr_nop,8\'h00, src_x,src_x, 1\'b1,dest_r,\t\top_adr, 2\'b00,2\'b00,\t4\'h0};\r
+ {8\'h73,10\'bxx_xxxx_x1xx}:\tnew_op = {adwr2,   phwr2, irrw2,rega2, 1\'b0,dest_x,\t\top_adr,\t2\'b00,2\'b10,\tnxrw2};\r
+ \r
+ // that is only for LMR and CINV :\r
+ {8\'h74,10\'bxx_xxxx_xxxx}:\tnew_op = (IC_READ | STOP_CINV) ?\r
+\t\t\t\t\t\t\t\t\t {ivar_adr,8\'h74, rtmph,src_x, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b00,\t4\'h0}\t// wait ...\r
+\t\t\t\t\t\t\t\t   : {ivar_adr,8\'h75, rtmph,src_x, 1\'b1,lmrreg,\t\top_lmr, 2\'b00,2\'b00,\t4\'h0};\t// continue\r
+ {8\'h75,10\'bxx_xxxx_xxxx}:\tnew_op = {ivar_adr,8\'h4F, rtmph,src_x, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b00,\t4\'h0};\r
+ \r
+\t// +++++++++++++++++  The String Opcodes  +++++++++++++++++++++\r
+\t\r
+\t\t// Phase 192 : R0=0 ?\r
+ {8\'hC0,10\'bxx_xxxx_xxxx}:\tnew_op = STRING[2] ?\t// Is R0<>0 ?\r
+\t\t\t\t\t\t\t\t\t {st_src,  ph_str,rstr1,rstr1, ~kurz_st,temp_h,\top_mov,\t2\'b00,2\'b00,\t4\'h0}\r
+\t\t\t\t\t\t\t\t   : {addr_nop,8\'h00, src_x,src_x, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b00,\t4\'h0};\r
+\t\t// Phase 193 : 1. part read of SRC-Register => EA\r
+ {8\'hC1,10\'bxx_xxxx_xxxx}:\tnew_op = {st_len,  8\'hC2, src_x,src_x, 1\'b1,wstr1,\t\top_adr,\t2\'b00,2\'b00,\t4\'h1};\r
+\t\t// Phase 194 : memory operation : read\r
+ {8\'hC2,10\'bxx_xxxx_xxxx}:\tnew_op = mt_flag ?\r
+\t\t\t\t\t\t\t\t\t {addr_nop,8\'hD3, imme, src_x, 1\'b1,temp_2, (op_feld_reg[14] ? op_zex : op_mov),\r
+\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t2\'b00,2\'b00,\t4\'h0}\r
+\t\t\t\t\t\t\t\t   : {load_ea, 8\'hC3, imme, rstr2, 1\'b0,dest_x,\t\top_mov, 2\'b00,2\'b10,\t4\'h0};\r
+\t\t// Phase 195 : Data in output register and at the same time R2 to EA\r
+ {8\'hC3,10\'bxx_xxxx_xxxx}:\tnew_op = {st_dest, 8\'hC4, rstr2,imme,  ~kurz_st,temp_1,\top_mov,\t2\'b00,2\'b01,\t4\'h0};\r
+\t\t// Phase 196 : 1. part reuse EA and LSD of 8B data to Out-Register\r
+ {8\'hC4,10\'bxx_xxxx_xxxx}:\tnew_op = {addr_nop,8\'hC5, src_x,src_x, 1\'b1,wstr2,\t\top_adr,\t2\'b00,2\'b00,\t4\'h1};\r
+\t\t// Phase 197 : memory operation : write\r
+ {8\'hC5,10\'bxx_xxxx_xxxx}:\tnew_op = {addr_nop,8\'hC7, rstr0,src_x, 1\'b1,wstr0,\t\top_str, 2\'b00,2\'b00,\t4\'h0};\r
+\t\t// Phase 199 : Test for End and Interrupt\r
+ {8\'hC7,10\'bxx_xxxx_xxxx}:\tnew_op = (interrupt & ~kurz_st) ?\r
+\t\t\t\t\t\t\t\t\t {save_pc, 8\'h80, src_x,src_x, 1\'b0,dest_x,\t\top_psr,\t2\'b00,2\'b00,\t4\'h0}\t// Interrupt !\r
+\t\t\t\t\t\t\t\t   : ( STRING[2] ?\t// Is R0<>0 ?\r
+\t\t\t\t\t\t\t\t\t {st_src,  ph_str,rstr1,rstr1, ~kurz_st,temp_h,\top_mov,\t2\'b00,2\'b00,\t4\'h0}\r
+\t\t\t\t\t\t\t\t   : {addr_nop,8\'h00, src_x,src_x, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b00,\t4\'h0} );\r
+ // String Compare :\r
+\t\t// Phase 201 : 1. part read of SRC-Register => EA\r
+ {8\'hC9,10\'bxx_xxxx_xxxx}:\tnew_op = {st_len,  8\'hCA, src_x,src_x, 1\'b1,wstr1,\t\top_adr,\t2\'b00,2\'b00,\t4\'h1};\r
+\t\t// Phase 202 : memory operation : read\r
+ {8\'hCA,10\'bxx_xxxx_xxxx}:\tnew_op = mt_flag ?\r
+\t\t\t\t\t\t\t\t\t {addr_nop,8\'hDB, imme, src_x, 1\'b1,temp_2, (op_feld_reg[14] ? op_zex : op_mov),\r
+\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t2\'b00,2\'b00,\t4\'h0}\r
+\t\t\t\t\t\t\t\t   : ( skps_flag ?\t// SKPS read only String1\r
+\t\t\t\t\t\t\t\t     {addr_nop,8\'hC7, rstr0,src_x, 1\'b1,wstr0,\t\top_str, 2\'b00,2\'b00,\t4\'h0}\r
+\t\t\t\t\t\t\t\t   : {load_ea, 8\'hCB, imme, rstr2, 1\'b1,temp_2,\t\top_mov, 2\'b00,2\'b00,\t4\'h0} );\r
+\t\t// Phase 203 : Data to output register and at the same time R2 to EA\r
+ {8\'hCB,10\'bxx_xxxx_xxxx}:\tnew_op = {st_src2, 8\'hCC, rstr2,src_x, ~kurz_st,temp_1,\top_mov,\t2\'b00,2\'b00,\t4\'h0};\r
+\t\t// Phase 204 : 1. part reuse EA \r
+ {8\'hCC,10\'bxx_xxxx_xxxx}:\tnew_op = {addr_nop,8\'hCD, src_x,src_x, 1\'b1,wstr2,\t\top_adr,\t2\'b00,2\'b00,\t4\'h1};\r
+\t\t// Phase 205 : memory operation : read and prepare compare\r
+ {8\'hCD,10\'bxx_xxxx_xxxx}:\tnew_op = {addr_nop,8\'hCE, rtmp2,imme,  1\'b0,dest_x,\t\top_scp, 2\'b00,2\'b10,\t4\'h0};\r
+\t\t// Phase 206 : compare of data\r
+ {8\'hCE,10\'bxx_xxxx_xxxx}:\tnew_op = STRING[3] ?\t// Elements equal ? Same as ACB_ZERO without delay of 1 cycle\r
+\t\t\t\t\t\t\t\t     {addr_nop,8\'hC7, rstr0,src_x, 1\'b1,wstr0,\t\top_str, 2\'b00,2\'b00,\t4\'h0}\r
+\t\t\t\t\t\t\t\t   : ( kurz_st ?\t// at CMPM direct end\r
+\t\t\t\t\t\t\t\t\t {addr_nop,8\'h00, src_x,src_x, 1\'b0,dest_x,\t\top_mov,\t2\'b00,2\'b00,\t4\'h0}\r
+\t\t\t\t\t\t\t\t   : {addr_nop,8\'hC8, rtmph,src_x, 1\'b1,6\'h01,\t\top_mov,\t2\'b00,2\'b00,\t4\'h0} );\r
+\t\t// Phase 200 : reload of R1 at CMPS, prepare reload of R2\r
+ {8\'hC8,10\'bxx_xxxx_xxxx}:\tnew_op = {addr_nop,8\'h00, rtmp1,src_x, 1\'b1,6\'h02, \t\top_mov, 2\'b00,2\'b00,\t4\'h0};\r
+ // String Options Match and Translate for MOVS\r
+\t\t// Phase 211 : Test if Translate\r
+ {8\'hD3,10\'bxx_xxxx_xxxx}:\tnew_op = op_feld_reg[14] ?\t// Translate ? Translate Base is Register 3\r
+\t\t\t\t\t\t\t\t     {st_trans,8\'hD4, rtmp2,7\'h03, 1\'b0,dest_x,\t\top_mov, 2\'b00,2\'b00,\t4\'h1}\r
+\t\t\t\t\t\t\t\t   : {addr_nop,8\'hD7, rtmp2,7\'h04, 1\'b0,dest_x,\t\top_scp, 2\'b00,2\'b10,\t4\'h0};\t// Match\r
+\t\t// Phase 212 : memory operation : read\r
+ {8\'hD4,10\'bxx_xxxx_xxxx}:\tnew_op = {addr_nop,8\'hD5, imme, src_x, 1\'b1,temp_2,\t\top_mov, 2\'b00,2\'b10,\t4\'h0};\r
+\t\t// Phase 213 : Test if Match\r
+ {8\'hD5,10\'bxx_xxxx_xxxx}:\tnew_op = op_feld_reg[16] ?\t// Match ? Reference Value is Register 4\r
+\t\t\t\t\t\t\t\t     {addr_nop,8\'hD7, rtmp2,7\'h04, 1\'b0,dest_x,\t\top_scp, 2\'b00,2\'b10,\t4\'h0}\r
+\t\t\t\t\t\t\t\t   : {st_trde, 8\'hC4, 7\'h02,7\'h02, 1\'b1,temp_1,\t\top_mov, 2\'b00,2\'b00,\t4\'h0};\t// back to MOVS\r
+\t\t// Phase 215 : Match result evaluation\r
+ {8\'hD7,10\'bxx_xxxx_xxxx}:\tnew_op = (STRING[3] ^ op_feld_reg[17]) ?\t// Not equal? (op_feld_reg[17] = 1 = UNTIL)\r
+\t\t\t\t\t\t\t\t     {load_ea, 8\'hC3, rtmp2,7\'h02, 1\'b0,dest_x,\t\top_mov, 2\'b00,2\'b10,\t4\'h0}\t// back to MOVS\r
+\t\t\t\t\t\t\t\t   : {addr_nop,8\'h00, rtmph,src_x, 1\'b1,6\'h01, \t\top_mov, 2\'b00,2\'b00,\t4\'h0};\t// Abort, R1 back\r
+ // String Options Match and Translate for CMPS and SKPS - to many options to get it in one state\r
+\t\t// Phase 218 : Test if Translate\r
+ {8\'hDB,10\'bxx_xxxx_xxxx}:\tnew_op = op_feld_reg[14] ?\t// Translate ? Translate Base is Register 3\r
+\t\t\t\t\t\t\t\t     {st_trans,8\'hDC, rtmp2,7\'h03, 1\'b0,dest_x,\t\top_mov, 2\'b00,2\'b00,\t4\'h1}\r
+\t\t\t\t\t\t\t\t   : {addr_nop,8\'hDF, rtmp2,7\'h04, 1\'b0,dest_x,\t\top_scp, 2\'b00,2\'b10,\t4\'h0};\t// Match\r
+\t\t// Phase 220 : memory operation : read\r
+ {8\'hDC,10\'bxx_xxxx_xxxx}:\tnew_op = {addr_nop,8\'hDD, imme, src_x, 1\'b1,temp_2,\t\top_mov, 2\'b00,2\'b10,\t4\'h0};\r
+\t\t// Phase 221 : Test if Match\r
+ {8\'hDD,10\'bxx_xxxx_xxxx}:\tnew_op = op_feld_reg[16] ?\t// Match ? Reference value is Register 4\r
+\t\t\t\t\t\t\t\t     {addr_nop,8\'hDF, rtmp2,7\'h04, 1\'b0,dest_x,\t\top_scp, 2\'b00,2\'b10,\t4\'h0}\r
+\t\t\t\t\t\t\t\t   : ( skps_flag ?\t// SKPS read only String1\r
+\t\t\t\t\t\t\t\t     {addr_nop,8\'hC7, 7\'h00,src_x, 1\'b1,6\'h00,\t\top_str, 2\'b00,2\'b00,\t4\'h0}\t// back to SKPS\r
+\t\t\t\t\t\t\t\t   : {st_trs2, 8\'hCC, 7\'h02,7\'h02, 1\'b1,temp_1,\t\top_mov, 2\'b00,2\'b00,\t4\'h0});\t// back to CMPS\r
+\t\t// Phase 223 : Match result evaluation\r
+ {8\'hDF,10\'bxx_xxxx_xxxx}:\tnew_op = (STRING[3] ^ op_feld_reg[17]) ?\t// Not equal? (op_feld_reg[17] = 1 = UNTIL)\r
+\t\t\t\t\t\t\t\t     ( skps_flag ?\t// SKPS read only String1\r
+\t\t\t\t\t\t\t\t     {addr_nop,8\'hC7, 7\'h00,src_x, 1\'b1,6\'h00,\t\top_str, 2\'b00,2\'b00,\t4\'h0}\t// back to SKPS\r
+\t\t\t\t\t\t\t\t   : {st_trs2, 8\'hCC, 7\'h02,7\'h02, 1\'b1,temp_1,\t\top_mov, 2\'b00,2\'b00,\t4\'h0} )\t// back to CMPS\r
+\t\t\t\t\t\t\t\t   : {addr_nop,8\'h00, rtmph,src_x, 1\'b1,6\'h01, \t\top_mov, 2\'b00,2\'b00,\t4\'h0};\t// Abort, R1 back\r
+\r
+\t\t  default\t\t :  new_op = 67\'hx_xxxx_xxxx_xxxx_xxxx;\r
+\t\tendcase\r
+\r
+\t// ++++++++++++++++++++++++  Deliver data of state machine  ++++++++++++++++++++++++++++\r
+\t\r
+\t// not all new_op bits are evaluated here ...\r
+\t\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) ACC_FELD[11:10] <= 2\'b00;\t// RD WR\r
+\t\t  else if (next) ACC_FELD[11:10] <= new_op[64:63];\r
+\t\t\t\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) spupd_i <= 1\'b0;\t// Stack Pointer Update\r
+\t\t  else if (next) spupd_i <= new_op[56];\r
+\t\t\t\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) oper_i <= 11\'b0;\r
+\t\t  else if (next) oper_i <= new_op[18:8];\r
+\t\t\t\r
+\talways @(posedge BCLK)\r
+\t\tif (next)\r
+\t\t  begin\r
+\t\t\tACC_FELD[13:12] <=  new_op[66:65];\t\t\t\t\t// ASIZ'b""E[1:0]\r
+\t\t\tACC_FELD[8:0]   <= {new_op[61:57],new_op[51:48]};\t// FULLACC INDEX[3:0] POST CLRMSW SRC2SEL[1:0]\r
+\t\t    disp_sel <= new_op[55:52];\r
+\t\t\twradr_i\t <= new_op[24:19];\r
+\t\t  end\r
+\t\t  \r
+\talways @(posedge BCLK) wmaske_i <= src2_le;\t// to simple ?\r
+\t\r
+\talways @(posedge BCLK) index_cmd <= (phase_reg == 8'h60);\t// that only for INDEX\r
+\t\r
+\t// WMASKE : SP always 32 Bit, opcodes in Format 1, Reg-Nr. >31 , INDEX opcodes and the CHECK operand too\r
+\tassign WMASKE = {(spupd | format1 | wradr_i[5] | wmaske_i[1] | index_cmd | (oper_i[7:0] == 8'h83)),wmaske_i[0]};\r
+\tassign WRADR  = spupd ? {~stack[5],stack[4:0]} : wradr_i;\r
+\tassign WREN   = (spupd | wren_i) & no_trap;\r
+\tassign OPER   = spupd ? op_adr\t\t\t\t   : oper_i;\r
+\t\r
+\talways @(posedge BCLK) ACC_FELD[14] <= next & (new_op[64] | new_op[63] | new_op[62]);\t// NEWACC is important\r
+\talways @(posedge BCLK) ACC_FELD[9]  <= next & new_op[62];\t// LDEA is only one pulse\r
+\t\r
+\talways @(posedge BCLK) START  <= next ? new_op[7:6] : 2'b00;\r
+\talways @(posedge BCLK) ldoreg <= next ? new_op[5:4] : 2'b00;\t// [1] = LD_OUT , [0] = LD_LDQ\r
+\talways @(posedge BCLK) wren_i <= next & new_op[25] & ~new_op[7];\t// only if no START[1] from Long-Op\r
+\t\r
+\tassign LD_OUT = {(ldoreg[1] & no_trap),ldoreg[0]};\t// [1] = LD_OUT (for CMP too) , [0] = LD_LDQ\r
+\t\r
+\tassign spupd = spupd_i & ~wren_i & ~ldoreg[1] & ~spu_block;\t// no Stack Update if OUT Register load or already Write-Register\r
+\t\r
+\tassign do_long = new_op[7];\t\t// START[1] for long_reg\r
+\t\r
+\tassign RDAA = {next,new_op[39:33]};\t// Source 1\r
+\tassign RDAB = {next,new_op[32:26]};\t// Source 2\r
+\t\r
+\talways @(posedge BCLK) if (next) WR_REG = new_op[25] & new_op[7];\t// START[1] : if WR then LONG path has register as Destination\r
+\t\r
+\t// special case : example is POLYL F2,TOS\r
+\talways @(posedge BCLK) spu_block <= DONE & WR_REG;\r
+\t\r
+\tassign MMU_UPDATE[1] = (phase_reg == 8'h84) | (phase_reg == 8'h85);\t// serving the MMU at ABORT\r
+\t\r
+\t// only the real access gets USER Status : important for Memory Relative & External\r
+\talways @(posedge BCLK)\t\t\t\t\t\t\t\t\t\t//\t\tMOVUS\t\t\t\t\tMOVSU\t\t\tRDVAL/WRVAL\r
+\t\tif (ACC_FELD[14]) dc_user <= PSR[8] | (m_ussu & (m_usel ? (phase_reg == 8'h07) : (phase_reg == 8'h27))) | RWVAL[1];\r
+\t\t\telse dc_user <= dc_user & ~abort;\r
+\t\t\t\r
+\talways @(posedge BCLK) dc_ilo <= op_ilo &  (phase_reg == 8'h59);\r
+\talways @(posedge BCLK) ILO    <= op_ilo & ((phase_reg == 8'h59) | (phase_reg == 8'h27));\r
+\t\r
+\tassign RWVAL = {dc_ilo,(rwval_flag & (phase_reg == 8'h53)),wrval_flag};\t// is used for DCACHE ILO too\r
+\t\r
+\t// Signals for the I_PATH + Debug\r
+\tassign DETOIP\t= {pc_match,cmps_flag,ph_match,op_feld_reg[17],kill_opt,inss_op,exin_cmd,extract,bit_reg,kurz_st,dw_info,acb_reg,t2p};\r
+\r
+\t// Signals for the ADDR_UNIT : [5]=RMW Signal\r
+\tassign chk_rmw\t= (phase_reg == 8'h17) | (phase_reg == 8'h58) | ((phase_reg == 8'h59) & rw_bit);\t// right Gruppe 2 opcodes\r
+\tassign INFO_AU\t= {no_trap,chk_rmw,(op_feld_reg[40:39] == 2'b11),RWVAL[1],(a_ivar & ~IC_READ),dc_user,disp_ok};\r
+\t\r
+\tassign RESTART = (phase_reg == 8'h4D);\r
+\r
+\t// Signals to generate external STATUS\r
+\tassign GENSTAT[2] = (phase_reg == 8'h88);\t// WAIT Signal\r
+\tassign GENSTAT[1] = (phase_reg == 8'h82);\t// Interrupt Acknowlege Cycle\r
+\tassign GENSTAT[0] = (phase_reg == 8'h45);\t// End-of-Interrupt Cycle\r
+\t\r
+\t// ++++++++++++++++++++ Here is the Sub-Modul for the opcodes of Gruppe 2  ++++++++++++++++\r
+\t\r
+\tGRUPPE_2 reste_ops (.BCLK(BCLK), .PHASE_0(PHASE_0), .OPREG(OPREG[18:0]), .PHASE(phase_ein[3:0]), \r
+\t\t\t\t\t\t.SRC_1(src_1), .SRC_2(src_2), .REGA1(rega1), .REGA2(rega2), .IRRW1(irrw1), .IRRW2(irrw2),\r
+\t\t\t\t\t\t.ADRD1(adrd1), .ADRD2(adrd2), .EXR12(exr12), .EXR22(exr22), .PHRD1(phrd1[3:0]), .PHRD2(phrd2[3:0]),\r
+\t\t\t\t\t\t.NXRD1(nxrd1), .NXRW2(nxrw2), .ACCA({acc1,1'b0,acc2,1'b0}), .OPERA(opera),\r
+\t\t\t\t\t\t.STATE_0(state_0), .STATE_GROUP_50(state_group_50), .STATE_GROUP_60(state_group_60) );\r
+\t\t\t\t\t\t\r
+endmodule\r
+"
+"/*
+ * ALU.
+ *
+ * AI and BI are 8 bit inputs. Result in OUT.
+ * CI is Carry In.
+ * CO is Carry Out.
+ *
+ * op[3:0] is defined as follows:
+ *
+ * 0011   AI + BI
+ * 0111   AI - BI
+ * 1011   AI + AI
+ * 1100   AI | BI
+ * 1101   AI & BI
+ * 1110   AI ^ BI
+ * 1111   AI
+ *
+ */
+
+module ALU( clk, op, right, AI, BI, CI, CO, BCD, OUT, V, Z, N, HC, RDY );
+\tinput clk;
+\tinput right;
+\tinput [3:0] op;\t\t// operation
+\tinput [7:0] AI;
+\tinput [7:0] BI;
+\tinput CI;
+\tinput BCD;\t\t// BCD style carry
+\toutput [7:0] OUT;
+\toutput CO;
+\toutput V;
+\toutput Z;
+\toutput N;
+\toutput HC;
+\tinput RDY;
+
+reg [7:0] OUT;
+reg CO;
+wire V;
+wire Z;
+reg N;
+reg HC;
+
+reg AI7;
+reg BI7;
+reg [8:0] temp_logic;
+reg [7:0] temp_BI;
+reg [4:0] temp_l;
+reg [4:0] temp_h;
+wire [8:0] temp = { temp_h, temp_l[3:0] };
+wire adder_CI = (right | (op[3:2] == 2'b11)) ? 0 : CI;
+
+// calculate the logic operations. The 'case' can be done in 1 LUT per
+// bit. The 'right' shift is a simple mux that can be implemented by
+// F5MUX.
+always @*  begin
+\tcase( op[1:0] )
+\t    2'b00: temp_logic = AI | BI;
+\t    2'b01: temp_logic = AI & BI;
+\t    2'b10: temp_logic = AI ^ BI;
+\t    2'b11: temp_logic = AI;
+\tendcase
+
+\tif( right )
+\t    temp_logic = { AI[0], CI, AI[7:1] };
+end
+
+// Add logic result to BI input. This only makes sense when logic = AI.
+// This stage can be done in 1 LUT per bit, using carry chain logic.
+always @* begin
+\tcase( op[3:2] )
+\t    2'b00: temp_BI = BI;\t// A+B
+\t    2'b01: temp_BI = ~BI;\t// A-B
+\t    2'b10: temp_BI = temp_logic;\t// A+A
+\t    2'b11: temp_BI = 0;\t\t// A+0
+\tendcase\t
+end
+
+// HC9 is the half carry bit when doing BCD add
+wire HC9 = BCD & (temp_l[3:1] >= 3'd5);
+
+// CO9 is the carry-out bit when doing BCD add
+wire CO9 = BCD & (temp_h[3:1] >= 3'd5);
+
+// combined half carry bit
+wire temp_HC = temp_l[4] | HC9;
+
+// perform the addition as 2 separate nibble, so we get
+// access to the half carry flag
+always @* begin
+\ttemp_l = temp_logic[3:0] + temp_BI[3:0] + adder_CI;
+\ttemp_h = temp_logic[8:4] + temp_BI[7:4] + temp_HC;
+end
+
+// calculate the flags 
+always @(posedge clk)
+    if( RDY ) begin
+\tAI7 <= AI[7];
+\tBI7 <= temp_BI[7];
+\tOUT <= temp[7:0];
+\tCO  <= temp[8] | CO9;
+\tN   <= temp[7];
+\tHC  <= temp_HC;
+    end
+
+assign V = AI7 ^ BI7 ^ CO ^ N;
+assign Z = ~|OUT;
+
+endmodule
+"
+"// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+// This file is part of the M32632 project\r
+// http://opencores.org/project,m32632\r
+//\r
+// Filename: TOP_MISC.v\r
+// Version:  1.0\r
+// Date:     30 May 2015\r
+//\r
+// Copyright (C) 2015 Udo Moeller\r
+// \r
+// This source file may be used and distributed without \r
+// restriction provided that this copyright statement is not \r
+// removed from the file and that any derivative work contains \r
+// the original copyright notice and the associated disclaimer.\r
+// \r
+// This source file is free software; you can redistribute it \r
+// and/or modify it under the terms of the GNU Lesser General \r
+// Public License as published by the Free Software Foundation;\r
+// either version 2.1 of the License, or (at your option) any \r
+// later version. \r
+// \r
+// This source is distributed in the hope that it will be \r
+// useful, but WITHOUT ANY WARRANTY; without even the implied \r
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR \r
+// PURPOSE. See the GNU Lesser General Public License for more \r
+// details. \r
+// \r
+// You should have received a copy of the GNU Lesser General \r
+// Public License along with this source; if not, download it \r
+// from http://www.opencores.org/lgpl.shtml \r
+// \r
+// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\tModules contained in this file:\r
+//\t1. IO_SWITCH\tSwitch between ICACHE and DCACHE to IO Path\r
+//\t2. MAKE_STAT\tGenerate Statistic Signals\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t1. IO_SWITCH\tSwitch between ICACHE and DCACHE to IO Path\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module IO_SWITCH ( BCLK, BRESET, I_IOA, D_IOA, I_IORD, D_IORD, D_IOWR, IO_READY, GENSTAT, D_IOBE, ILO_SIG, DCWACC,\r
+\t\t\t\t   IO_A, IO_RD, IO_WR, IO_BE, I_IORDY, D_IORDY, STATUS, ILO );\r
+\r
+\tinput\t\t\tBCLK,BRESET;\r
+\tinput\t[31:0]\tI_IOA,D_IOA;\r
+\tinput\t\t\tI_IORD;\r
+\tinput\t\t\tD_IORD,D_IOWR;\r
+\tinput\t [3:0]\tD_IOBE;\r
+\tinput\t\t\tIO_READY;\r
+\tinput\t [2:0]\tGENSTAT;\r
+\tinput\t\t\tILO_SIG;\r
+\tinput\t [1:0]\tDCWACC;\r
+\t\r
+\toutput\t[31:0]\tIO_A;\r
+\toutput\t\t\tIO_RD,IO_WR;\r
+\toutput\t [3:0]\tIO_BE;\r
+\toutput\t\t\tI_IORDY;\r
+\toutput\t\t\tD_IORDY;\r
+\toutput\t [3:0]\tSTATUS;\r
+\toutput\t\t\tILO;\r
+\t\r
+\treg\t\t [3:0]\tSTATUS;\r
+\treg\t\t [1:0]\tselect;\r
+\treg\t\t\t\tilo_flag;\r
+\t\r
+\twire\t\t\tdaten;\r
+\twire\t\t\tsel_dp;\r
+\twire\t\t\tinterrupt;\r
+\twire\t\t\tilo_keep;\r
+\t\r
+\tassign daten = D_IORD | D_IOWR;\r
+\r
+\t// DCACHE has priority.\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) select <= 2'b0;\r
+\t\t  else\r
+\t\t\tcasex ({I_IORD,D_IORD,D_IOWR,IO_READY,ilo_keep,select})\r
+\t\t\t  7'b000xx_00 : select <= 2'b00;\r
+\t\t\t  7'b1000x_00 : select <= 2'b11;\r
+\t\t\t  7'bx100x_00 : select <= 2'b10;\r
+\t\t\t  7'bxx10x_00 : select <= 2'b10;\r
+\t\t\t// the access has in the same cycle a READY !\r
+\t\t\t  7'b1001x_00 : select <= 2'b00;\r
+\t\t\t  7'bx101x_00 : select <= 2'b00;\r
+\t\t\t  7'bxx11x_00 : select <= 2'b00;\r
+\t\t \t// Datea Access\r
+\t\t\t  7'bxxx0x_10 : select <= 2'b10;\r
+\t\t\t  7'bxxx11_10 : select <= 2'b10;\t// keep because of Interlocked\r
+\t\t\t  7'bxxx10_10 : select <= 2'b00;\r
+\t\t\t// Instruction Access\t  \r
+\t\t\t  7'bxxx0x_11 : select <= 2'b11;\t\r
+\t\t\t  7'bxxx1x_11 : select <= 2'b00;\r
+\t\t\t  default\t  : select <= 2'b00;\r
+\t\t\tendcase\r
+\t\t\t\r
+\tassign sel_dp = (select == 2'b10) | ((select == 2'b00) & daten);\r
+\t\r
+\tassign IO_RD   =  sel_dp ? D_IORD : I_IORD;\r
+\tassign IO_WR   =  sel_dp ? D_IOWR : 1'b0;\r
+\tassign IO_A    =  sel_dp ? D_IOA  : I_IOA;\r
+\tassign IO_BE   =  sel_dp ? D_IOBE : 4'b1111;\t// Instruction read always 32 Bit\r
+\t\r
+\tassign D_IORDY =  sel_dp & IO_READY;\r
+\tassign I_IORDY = ~sel_dp & IO_READY;\r
+\r
+\tassign interrupt = GENSTAT[1] | GENSTAT[0];\r
+\t\r
+\talways @(*)\r
+\t\tcasex ({sel_dp,daten,interrupt,I_IORD})\r
+\t\t  4'b110x : STATUS = 4'hA;\t\t\t\t\t\t// Daten\r
+\t\t  4'b111x : STATUS = GENSTAT[1] ? 4'h4 : 4'h6;\t// Int Ack. : End of Int\r
+\t\t  4'b0xx1 : STATUS = 4'h8;\t\t\t\t\t\t// Programm\r
+\t\t  default : STATUS = {3'd0,GENSTAT[2]};\t\t\t// WAIT or Inactive\r
+\t\tendcase\r
+\r
+\t// +++++++++++  ILO Control  ++++++++++++++++++\r
+\t\r
+\talways @(posedge BCLK)\r
+\t\tif (!ILO_SIG) ilo_flag <= 1'b0; // Flag is set at read and cleared with write\r
+\t\t  else ilo_flag <= (D_IORD & sel_dp) | DCWACC[0] | ilo_keep;\r
+\t\t  \r
+\tassign ilo_keep = ilo_flag & ~D_IOWR & ~DCWACC[1];\r
+\t\t  \r
+\tassign ILO = ILO_SIG & ((D_IORD & sel_dp) | DCWACC[0] | ilo_flag | D_IOWR | DCWACC[1]);\r
+\t\r
+endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t2. MAKE_STAT\tGenerate Statistic Signals\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module MAKE_STAT ( BCLK, READ, DACC_OK, DC_ACC, DPTE_ACC, DC_MDONE, DRAM_WR, IC_READ, IACC_OK, DATA_HOLD,\r
+\t\t\t\t   IC_ACC, IPTE_ACC, IC_MDONE, KOLLISION, STATSIGS );\r
+\r
+\tinput\tBCLK;\r
+\tinput\tREAD,DACC_OK;\r
+\tinput\tDC_ACC,DPTE_ACC,DC_MDONE;\r
+\tinput\tDRAM_WR;\r
+\tinput\tIC_READ,IACC_OK,DATA_HOLD;\r
+\tinput\tIC_ACC,IPTE_ACC,IC_MDONE;\r
+\tinput\tKOLLISION;\r
+\t\r
+\toutput\treg [7:0]\tSTATSIGS;\r
+\r
+\talways @(posedge BCLK)\r
+\t\tbegin\r
+\t\t\tSTATSIGS[7] <= KOLLISION;\t\t\t\t\t\t// 7 : from ICACHE : collisions\r
+\t\t\tSTATSIGS[6] <= IPTE_ACC;\t\t\t\t\t\t// 6 : Instruction PTE access\r
+\t\t\tSTATSIGS[5] <= IC_ACC & IC_MDONE;\t\t\t\t// 5 : Instruction Memory read\r
+\t\t\tSTATSIGS[4] <= IC_READ & IACC_OK & ~DATA_HOLD;\t// 4 : Instruction read , can be IO-Port too !\r
+\t\t\tSTATSIGS[3] <= DRAM_WR;\t\t\t\t\t\t\t// 3 : Data write\r
+\t\t\tSTATSIGS[2] <= DPTE_ACC;\t\t\t\t\t\t// 2 : Data PTE access\r
+\t\t\tSTATSIGS[1] <= DC_ACC & DC_MDONE;\t\t\t\t// 1 : Data Memory read\r
+\t\t\tSTATSIGS[0] <= READ & DACC_OK;\t\t\t\t\t// 0 : Data read , can be IO-Port too !\r
+\t\tend\r
+\t\t\r
+endmodule\r
+\r
+"
+"//////////////////////////////////////////////////////////////////
+//                                                              //
+//  Barrel Shifter for Amber 2 Core                             //
+//                                                              //
+//  This file is part of the Amber project                      //
+//  http://www.opencores.org/project,amber                      //
+//                                                              //
+//  Description                                                 //
+//  Provides 32-bit shifts LSL, LSR, ASR and ROR                //
+//                                                              //
+//  Author(s):                                                  //
+//      - Conor Santifort, csantifort.amber@gmail.com           //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+//                                                              //
+// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
+//                                                              //
+// This source file may be used and distributed without         //
+// restriction provided that this copyright statement is not    //
+// removed from the file and that any derivative work contains  //
+// the original copyright notice and the associated disclaimer. //
+//                                                              //
+// This source file is free software; you can redistribute it   //
+// and/or modify it under the terms of the GNU Lesser General   //
+// Public License as published by the Free Software Foundation; //
+// either version 2.1 of the License, or (at your option) any   //
+// later version.                                               //
+//                                                              //
+// This source is distributed in the hope that it will be       //
+// useful, but WITHOUT ANY WARRANTY; without even the implied   //
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
+// PURPOSE.  See the GNU Lesser General Public License for more //
+// details.                                                     //
+//                                                              //
+// You should have received a copy of the GNU Lesser General    //
+// Public License along with this source; if not, download it   //
+// from http://www.opencores.org/lgpl.shtml                     //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+
+
+module a23_barrel_shift (
+
+input       [31:0]          i_in,
+input                       i_carry_in,
+input       [7:0]           i_shift_amount,     // uses 8 LSBs of Rs, or a 5 bit immediate constant
+input                       i_shift_imm_zero,   // high when immediate shift value of zero selected
+input       [1:0]           i_function,
+
+output      [31:0]          o_out,
+output                      o_carry_out
+
+);
+
+`include ""a23_localparams.vh""
+
+  // MSB is carry out
+wire [32:0] lsl_out;
+wire [32:0] lsr_out;
+wire [32:0] asr_out;
+wire [32:0] ror_out;
+
+
+// Logical shift right zero is redundant as it is the same as logical shift left zero, so
+// the assembler will convert LSR #0 (and ASR #0 and ROR #0) into LSL #0, and allow
+// lsr #32 to be specified.
+
+// lsl #0 is a special case, where the shifter carry out is the old value of the status flags
+// C flag. The contents of Rm are used directly as the second operand.
+assign lsl_out = i_shift_imm_zero         ? {i_carry_in, i_in              } :  // fall through case 
+
+                 i_shift_amount == 8\'d 0  ? {i_carry_in, i_in              } :  // fall through case
+                 i_shift_amount == 8\'d 1  ? {i_in[31],   i_in[30: 0],  1\'d0} :
+                 
+                 i_shift_amount == 8\'d 2  ? {i_in[30],   i_in[29: 0],  2\'d0} :
+                 i_shift_amount == 8\'d 3  ? {i_in[29],   i_in[28: 0],  3\'d0} :
+                 i_shift_amount == 8\'d 4  ? {i_in[28],   i_in[27: 0],  4\'d0} :
+                 i_shift_amount == 8\'d 5  ? {i_in[27],   i_in[26: 0],  5\'d0} :
+                 i_shift_amount == 8\'d 6  ? {i_in[26],   i_in[25: 0],  6\'d0} :
+                 i_shift_amount == 8\'d 7  ? {i_in[25],   i_in[24: 0],  7\'d0} :
+                 i_shift_amount == 8\'d 8  ? {i_in[24],   i_in[23: 0],  8\'d0} :
+                 i_shift_amount == 8\'d 9  ? {i_in[23],   i_in[22: 0],  9\'d0} :
+                 i_shift_amount == 8\'d10  ? {i_in[22],   i_in[21: 0], 10\'d0} :
+                 i_shift_amount == 8\'d11  ? {i_in[21],   i_in[20: 0], 11\'d0} :
+                    
+                 i_shift_amount == 8\'d12  ? {i_in[20],   i_in[19: 0], 12\'d0} :
+                 i_shift_amount == 8\'d13  ? {i_in[19],   i_in[18: 0], 13\'d0} :
+                 i_shift_amount == 8\'d14  ? {i_in[18],   i_in[17: 0], 14\'d0} :
+                 i_shift_amount == 8\'d15  ? {i_in[17],   i_in[16: 0], 15\'d0} :
+                 i_shift_amount == 8\'d16  ? {i_in[16],   i_in[15: 0], 16\'d0} :
+                 i_shift_amount == 8\'d17  ? {i_in[15],   i_in[14: 0], 17\'d0} :
+                 i_shift_amount == 8\'d18  ? {i_in[14],   i_in[13: 0], 18\'d0} :
+                 i_shift_amount == 8\'d19  ? {i_in[13],   i_in[12: 0], 19\'d0} :
+                 i_shift_amount == 8\'d20  ? {i_in[12],   i_in[11: 0], 20\'d0} :
+                 i_shift_amount == 8\'d21  ? {i_in[11],   i_in[10: 0], 21\'d0} :
+
+                 i_shift_amount == 8\'d22  ? {i_in[10],   i_in[ 9: 0], 22\'d0} :
+                 i_shift_amount == 8\'d23  ? {i_in[ 9],   i_in[ 8: 0], 23\'d0} :
+                 i_shift_amount == 8\'d24  ? {i_in[ 8],   i_in[ 7: 0], 24\'d0} :
+                 i_shift_amount == 8\'d25  ? {i_in[ 7],   i_in[ 6: 0], 25\'d0} :
+                 i_shift_amount == 8\'d26  ? {i_in[ 6],   i_in[ 5: 0], 26\'d0} :
+                 i_shift_amount == 8\'d27  ? {i_in[ 5],   i_in[ 4: 0], 27\'d0} :
+                 i_shift_amount == 8\'d28  ? {i_in[ 4],   i_in[ 3: 0], 28\'d0} :
+                 i_shift_amount == 8\'d29  ? {i_in[ 3],   i_in[ 2: 0], 29\'d0} :
+                 i_shift_amount == 8\'d30  ? {i_in[ 2],   i_in[ 1: 0], 30\'d0} :
+                 i_shift_amount == 8\'d31  ? {i_in[ 1],   i_in[ 0: 0], 31\'d0} :
+                 i_shift_amount == 8\'d32  ? {i_in[ 0],   32\'d0             } :  // 32
+                                            {1\'d0,       32\'d0             } ;  // > 32
+                                            
+
+// The form of the shift field which might be expected to correspond to LSR #0 is used
+// to encode LSR #32, which has a zero result with bit 31 of Rm as the carry output. 
+                                           // carry out, < -------- out ---------->
+assign lsr_out = i_shift_imm_zero         ? {i_in[31], 32\'d0             } :
+
+                 i_shift_amount == 8\'d 0  ? {i_carry_in, i_in            } :  // fall through case
+                 i_shift_amount == 8\'d 1  ? {i_in[ 0],  1\'d0, i_in[31: 1]} :
+                 i_shift_amount == 8\'d 2  ? {i_in[ 1],  2\'d0, i_in[31: 2]} :
+                 i_shift_amount == 8\'d 3  ? {i_in[ 2],  3\'d0, i_in[31: 3]} :
+                 i_shift_amount == 8\'d 4  ? {i_in[ 3],  4\'d0, i_in[31: 4]} :
+                 i_shift_amount == 8\'d 5  ? {i_in[ 4],  5\'d0, i_in[31: 5]} :
+                 i_shift_amount == 8\'d 6  ? {i_in[ 5],  6\'d0, i_in[31: 6]} :
+                 i_shift_amount == 8\'d 7  ? {i_in[ 6],  7\'d0, i_in[31: 7]} :
+                 i_shift_amount == 8\'d 8  ? {i_in[ 7],  8\'d0, i_in[31: 8]} :
+                 i_shift_amount == 8\'d 9  ? {i_in[ 8],  9\'d0, i_in[31: 9]} :
+                    
+                 i_shift_amount == 8\'d10  ? {i_in[ 9], 10\'d0, i_in[31:10]} :
+                 i_shift_amount == 8\'d11  ? {i_in[10], 11\'d0, i_in[31:11]} :
+                 i_shift_amount == 8\'d12  ? {i_in[11], 12\'d0, i_in[31:12]} :
+                 i_shift_amount == 8\'d13  ? {i_in[12], 13\'d0, i_in[31:13]} :
+                 i_shift_amount == 8\'d14  ? {i_in[13], 14\'d0, i_in[31:14]} :
+                 i_shift_amount == 8\'d15  ? {i_in[14], 15\'d0, i_in[31:15]} :
+                 i_shift_amount == 8\'d16  ? {i_in[15], 16\'d0, i_in[31:16]} :
+                 i_shift_amount == 8\'d17  ? {i_in[16], 17\'d0, i_in[31:17]} :
+                 i_shift_amount == 8\'d18  ? {i_in[17], 18\'d0, i_in[31:18]} :
+                 i_shift_amount == 8\'d19  ? {i_in[18], 19\'d0, i_in[31:19]} :
+
+                 i_shift_amount == 8\'d20  ? {i_in[19], 20\'d0, i_in[31:20]} :
+                 i_shift_amount == 8\'d21  ? {i_in[20], 21\'d0, i_in[31:21]} :
+                 i_shift_amount == 8\'d22  ? {i_in[21], 22\'d0, i_in[31:22]} :
+                 i_shift_amount == 8\'d23  ? {i_in[22], 23\'d0, i_in[31:23]} :
+                 i_shift_amount == 8\'d24  ? {i_in[23], 24\'d0, i_in[31:24]} :
+                 i_shift_amount == 8\'d25  ? {i_in[24], 25\'d0, i_in[31:25]} :
+                 i_shift_amount == 8\'d26  ? {i_in[25], 26\'d0, i_in[31:26]} :
+                 i_shift_amount == 8\'d27  ? {i_in[26], 27\'d0, i_in[31:27]} :
+                 i_shift_amount == 8\'d28  ? {i_in[27], 28\'d0, i_in[31:28]} :
+                 i_shift_amount == 8\'d29  ? {i_in[28], 29\'d0, i_in[31:29]} :
+
+                 i_shift_amount == 8\'d30  ? {i_in[29], 30\'d0, i_in[31:30]} :
+                 i_shift_amount == 8\'d31  ? {i_in[30], 31\'d0, i_in[31   ]} :
+                 i_shift_amount == 8\'d32  ? {i_in[31], 32\'d0             } :
+                                            {1\'d0,     32\'d0             } ;  // > 32
+
+
+// The form of the shift field which might be expected to give ASR #0 is used to encode
+// ASR #32. Bit 31 of Rm is again used as the carry output, and each bit of operand 2 is
+// also equal to bit 31 of Rm. The result is therefore all ones or all zeros, according to
+// the value of bit 31 of Rm.
+
+                                          // carry out, < -------- out ---------->
+assign asr_out = i_shift_imm_zero         ? {i_in[31], {32{i_in[31]}}             } :
+
+                 i_shift_amount == 8\'d 0  ? {i_carry_in, i_in                     } :  // fall through case
+                 i_shift_amount == 8\'d 1  ? {i_in[ 0], { 2{i_in[31]}}, i_in[30: 1]} :
+                 i_shift_amount == 8\'d 2  ? {i_in[ 1], { 3{i_in[31]}}, i_in[30: 2]} :
+                 i_shift_amount == 8\'d 3  ? {i_in[ 2], { 4{i_in[31]}}, i_in[30: 3]} :
+                 i_shift_amount == 8\'d 4  ? {i_in[ 3], { 5{i_in[31]}}, i_in[30: 4]} :
+                 i_shift_amount == 8\'d 5  ? {i_in[ 4], { 6{i_in[31]}}, i_in[30: 5]} :
+                 i_shift_amount == 8\'d 6  ? {i_in[ 5], { 7{i_in[31]}}, i_in[30: 6]} :
+                 i_shift_amount == 8\'d 7  ? {i_in[ 6], { 8{i_in[31]}}, i_in[30: 7]} :
+                 i_shift_amount == 8\'d 8  ? {i_in[ 7], { 9{i_in[31]}}, i_in[30: 8]} :
+                 i_shift_amount == 8\'d 9  ? {i_in[ 8], {10{i_in[31]}}, i_in[30: 9]} :
+                    
+                 i_shift_amount == 8\'d10  ? {i_in[ 9], {11{i_in[31]}}, i_in[30:10]} :
+                 i_shift_amount == 8\'d11  ? {i_in[10], {12{i_in[31]}}, i_in[30:11]} :
+                 i_shift_amount == 8\'d12  ? {i_in[11], {13{i_in[31]}}, i_in[30:12]} :
+                 i_shift_amount == 8\'d13  ? {i_in[12], {14{i_in[31]}}, i_in[30:13]} :
+                 i_shift_amount == 8\'d14  ? {i_in[13], {15{i_in[31]}}, i_in[30:14]} :
+                 i_shift_amount == 8\'d15  ? {i_in[14], {16{i_in[31]}}, i_in[30:15]} :
+                 i_shift_amount == 8\'d16  ? {i_in[15], {17{i_in[31]}}, i_in[30:16]} :
+                 i_shift_amount == 8\'d17  ? {i_in[16], {18{i_in[31]}}, i_in[30:17]} :
+                 i_shift_amount == 8\'d18  ? {i_in[17], {19{i_in[31]}}, i_in[30:18]} :
+                 i_shift_amount == 8\'d19  ? {i_in[18], {20{i_in[31]}}, i_in[30:19]} :
+
+                 i_shift_amount == 8\'d20  ? {i_in[19], {21{i_in[31]}}, i_in[30:20]} :
+                 i_shift_amount == 8\'d21  ? {i_in[20], {22{i_in[31]}}, i_in[30:21]} :
+                 i_shift_amount == 8\'d22  ? {i_in[21], {23{i_in[31]}}, i_in[30:22]} :
+                 i_shift_amount == 8\'d23  ? {i_in[22], {24{i_in[31]}}, i_in[30:23]} :
+                 i_shift_amount == 8\'d24  ? {i_in[23], {25{i_in[31]}}, i_in[30:24]} :
+                 i_shift_amount == 8\'d25  ? {i_in[24], {26{i_in[31]}}, i_in[30:25]} :
+                 i_shift_amount == 8\'d26  ? {i_in[25], {27{i_in[31]}}, i_in[30:26]} :
+                 i_shift_amount == 8\'d27  ? {i_in[26], {28{i_in[31]}}, i_in[30:27]} :
+                 i_shift_amount == 8\'d28  ? {i_in[27], {29{i_in[31]}}, i_in[30:28]} :
+                 i_shift_amount == 8\'d29  ? {i_in[28], {30{i_in[31]}}, i_in[30:29]} :
+
+                 i_shift_amount == 8\'d30  ? {i_in[29], {31{i_in[31]}}, i_in[30   ]} :
+                 i_shift_amount == 8\'d31  ? {i_in[30], {32{i_in[31]}}             } :
+                                            {i_in[31], {32{i_in[31]}}             } ; // >= 32
+                                            
+
+                                          // carry out, < ------- out --------->
+assign ror_out = i_shift_imm_zero              ? {i_in[ 0], i_carry_in,  i_in[31: 1]} :  // RXR, (ROR w/ imm 0)
+
+                 i_shift_amount[7:0] == 8\'d 0  ? {i_carry_in, i_in                  } :  // fall through case
+                 
+                 i_shift_amount[4:0] == 5\'d 0  ? {i_in[31], i_in                    } :  // Rs > 31
+                 i_shift_amount[4:0] == 5\'d 1  ? {i_in[ 0], i_in[    0], i_in[31: 1]} :
+                 i_shift_amount[4:0] == 5\'d 2  ? {i_in[ 1], i_in[ 1: 0], i_in[31: 2]} :
+                 i_shift_amount[4:0] == 5\'d 3  ? {i_in[ 2], i_in[ 2: 0], i_in[31: 3]} :
+                 i_shift_amount[4:0] == 5\'d 4  ? {i_in[ 3], i_in[ 3: 0], i_in[31: 4]} :
+                 i_shift_amount[4:0] == 5\'d 5  ? {i_in[ 4], i_in[ 4: 0], i_in[31: 5]} :
+                 i_shift_amount[4:0] == 5\'d 6  ? {i_in[ 5], i_in[ 5: 0], i_in[31: 6]} :
+                 i_shift_amount[4:0] == 5\'d 7  ? {i_in[ 6], i_in[ 6: 0], i_in[31: 7]} :
+                 i_shift_amount[4:0] == 5\'d 8  ? {i_in[ 7], i_in[ 7: 0], i_in[31: 8]} :
+                 i_shift_amount[4:0] == 5\'d 9  ? {i_in[ 8], i_in[ 8: 0], i_in[31: 9]} :
+                    
+                 i_shift_amount[4:0] == 5\'d10  ? {i_in[ 9], i_in[ 9: 0], i_in[31:10]} :
+                 i_shift_amount[4:0] == 5\'d11  ? {i_in[10], i_in[10: 0], i_in[31:11]} :
+                 i_shift_amount[4:0] == 5\'d12  ? {i_in[11], i_in[11: 0], i_in[31:12]} :
+                 i_shift_amount[4:0] == 5\'d13  ? {i_in[12], i_in[12: 0], i_in[31:13]} :
+                 i_shift_amount[4:0] == 5\'d14  ? {i_in[13], i_in[13: 0], i_in[31:14]} :
+                 i_shift_amount[4:0] == 5\'d15  ? {i_in[14], i_in[14: 0], i_in[31:15]} :
+                 i_shift_amount[4:0] == 5\'d16  ? {i_in[15], i_in[15: 0], i_in[31:16]} :
+                 i_shift_amount[4:0] == 5\'d17  ? {i_in[16], i_in[16: 0], i_in[31:17]} :
+                 i_shift_amount[4:0] == 5\'d18  ? {i_in[17], i_in[17: 0], i_in[31:18]} :
+                 i_shift_amount[4:0] == 5\'d19  ? {i_in[18], i_in[18: 0], i_in[31:19]} :
+
+                 i_shift_amount[4:0] == 5\'d20  ? {i_in[19], i_in[19: 0], i_in[31:20]} :
+                 i_shift_amount[4:0] == 5\'d21  ? {i_in[20], i_in[20: 0], i_in[31:21]} :
+                 i_shift_amount[4:0] == 5\'d22  ? {i_in[21], i_in[21: 0], i_in[31:22]} :
+                 i_shift_amount[4:0] == 5\'d23  ? {i_in[22], i_in[22: 0], i_in[31:23]} :
+                 i_shift_amount[4:0] == 5\'d24  ? {i_in[23], i_in[23: 0], i_in[31:24]} :
+                 i_shift_amount[4:0] == 5\'d25  ? {i_in[24], i_in[24: 0], i_in[31:25]} :
+                 i_shift_amount[4:0] == 5\'d26  ? {i_in[25], i_in[25: 0], i_in[31:26]} :
+                 i_shift_amount[4:0] == 5\'d27  ? {i_in[26], i_in[26: 0], i_in[31:27]} :
+                 i_shift_amount[4:0] == 5\'d28  ? {i_in[27], i_in[27: 0], i_in[31:28]} :
+                 i_shift_amount[4:0] == 5\'d29  ? {i_in[28], i_in[28: 0], i_in[31:29]} :
+
+                 i_shift_amount[4:0] == 5\'d30  ? {i_in[29], i_in[29: 0], i_in[31:30]} :
+                                                 {i_in[30], i_in[30: 0], i_in[31:31]} ;
+                 
+
+ 
+assign {o_carry_out, o_out} = i_function == LSL ? lsl_out :
+                              i_function == LSR ? lsr_out :
+                              i_function == ASR ? asr_out :
+                                                  ror_out ;
+
+endmodule
+
+
+"
+"/*
+ *  Copyright (c) 2008  Zeus Gomez Marmolejo <zeus@opencores.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+`include ""rom_def.v""
+
+`define IR_SIZE 36
+`define MEM_OP  31
+`define ADD_IP `IR_SIZE\'bx__0__1__0__1__10_001_001__0__01__0__0_1111_xxxx_xxxx_1111_xx
+`define OP_NOP 8\'h90
+`define OP_HLT 8\'hF4
+
+//`define DEBUG         1
+//`define DEBUG_TRACE   1
+"
+"(
+    input rst_b,
+    input p1_clk,
+    input p1_select,
+    input p1_rdnw,
+    input p2_clk,
+    input p2_select,
+    input p2_rdnw,
+    output p2_data_available,
+    output p1_full
+);
+
+   // Initial state: 0 = empty; 1 = full
+   parameter init = 0;
+
+   wire req;
+   reg req_s1;
+   reg req_s2;
+   wire ack;
+   reg ack_s1;
+   reg ack_s2;
+   
+   reg [1:0] p1_state;
+   reg [1:0] p2_state;
+
+   always @ (`p1edge p1_clk or negedge rst_b )   
+     begin
+        if (!rst_b) begin
+          p1_state <= { 1'b0, init };
+          ack_s1 <= 1'b0;
+          ack_s2 <= 1'b0;
+        end else begin
+          ack_s1 <= ack;
+          ack_s2 <= ack_s1;
+          case (p1_state)
+            2'b00:
+              if (p1_select & ! p1_rdnw)
+                p1_state <= 2'b01;
+            2'b01:
+              if (ack_s2)
+                p1_state <= 2'b10;
+            2'b10:
+              if (!ack_s2)
+                p1_state <= 2'b00;
+            default:              
+              p1_state <= 2'b00;
+          endcase
+        end
+      end
+
+   assign req = p1_state[0];
+   
+   assign p1_full = p1_state[0] | p1_state[1];
+
+   always @ (`p2edge p2_clk or negedge rst_b )   
+     begin
+        if (!rst_b) begin
+          p2_state <= { 1'b0, init};
+          req_s1 <= init;
+          req_s2 <= init;
+        end else begin
+          req_s1 <= req;
+          req_s2 <= req_s1;
+          case (p2_state)
+            2'b00:
+              if (req_s2)
+                p2_state <= 2'b01;
+            2'b01:
+              if (p2_select & p2_rdnw)
+                p2_state <= 2'b10;
+            2'b10:
+              if (!req_s2)
+                p2_state <= 2'b00;
+            default:              
+              p2_state <= 2'b00;
+          endcase
+        end
+      end
+      
+    assign ack = p2_state[1];
+      
+    assign p2_data_available = p2_state[0] & !p2_state[1];
+   
+endmodule
+"
+"/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used solely      *
+*     for design, simulation, implementation and creation of design files      *
+*     limited to Xilinx devices or technologies. Use with non-Xilinx           *
+*     devices or technologies is expressly prohibited and immediately          *
+*     terminates your license.                                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION ""AS IS"" SOLELY     *
+*     FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY     *
+*     PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE              *
+*     IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS       *
+*     MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY       *
+*     CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY        *
+*     RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY        *
+*     DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE    *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A    *
+*     PARTICULAR PURPOSE.                                                      *
+*                                                                              *
+*     Xilinx products are not intended for use in life support appliances,     *
+*     devices, or systems.  Use in such applications are expressly             *
+*     prohibited.                                                              *
+*                                                                              *
+*     (c) Copyright 1995-2015 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+// You must compile the wrapper file ph_fifo_core_spartan3.v when simulating
+// the core, ph_fifo_core_spartan3. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the ""CORE Generator Help"".
+
+// The synthesis directives ""translate_off/translate_on"" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+`timescale 1ns/1ps
+
+module ph_fifo_core_spartan3(
+  rst,
+  wr_clk,
+  rd_clk,
+  din,
+  wr_en,
+  rd_en,
+  dout,
+  full,
+  empty
+);
+
+input rst;
+input wr_clk;
+input rd_clk;
+input [7 : 0] din;
+input wr_en;
+input rd_en;
+output [7 : 0] dout;
+output full;
+output empty;
+
+// synthesis translate_off
+
+  FIFO_GENERATOR_V9_3 #(
+    .C_ADD_NGC_CONSTRAINT(0),
+    .C_APPLICATION_TYPE_AXIS(0),
+    .C_APPLICATION_TYPE_RACH(0),
+    .C_APPLICATION_TYPE_RDCH(0),
+    .C_APPLICATION_TYPE_WACH(0),
+    .C_APPLICATION_TYPE_WDCH(0),
+    .C_APPLICATION_TYPE_WRCH(0),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_AXI_ARUSER_WIDTH(1),
+    .C_AXI_AWUSER_WIDTH(1),
+    .C_AXI_BUSER_WIDTH(1),
+    .C_AXI_DATA_WIDTH(64),
+    .C_AXI_ID_WIDTH(4),
+    .C_AXI_RUSER_WIDTH(1),
+    .C_AXI_TYPE(0),
+    .C_AXI_WUSER_WIDTH(1),
+    .C_AXIS_TDATA_WIDTH(64),
+    .C_AXIS_TDEST_WIDTH(4),
+    .C_AXIS_TID_WIDTH(8),
+    .C_AXIS_TKEEP_WIDTH(4),
+    .C_AXIS_TSTRB_WIDTH(4),
+    .C_AXIS_TUSER_WIDTH(4),
+    .C_AXIS_TYPE(0),
+    .C_COMMON_CLOCK(0),
+    .C_COUNT_TYPE(0),
+    .C_DATA_COUNT_WIDTH(5),
+    .C_DEFAULT_VALUE(""BlankString""),
+    .C_DIN_WIDTH(8),
+    .C_DIN_WIDTH_AXIS(1),
+    .C_DIN_WIDTH_RACH(32),
+    .C_DIN_WIDTH_RDCH(64),
+    .C_DIN_WIDTH_WACH(32),
+    .C_DIN_WIDTH_WDCH(64),
+    .C_DIN_WIDTH_WRCH(2),
+    .C_DOUT_RST_VAL(""AA""),
+    .C_DOUT_WIDTH(8),
+    .C_ENABLE_RLOCS(0),
+    .C_ENABLE_RST_SYNC(1),
+    .C_ERROR_INJECTION_TYPE(0),
+    .C_ERROR_INJECTION_TYPE_AXIS(0),
+    .C_ERROR_INJECTION_TYPE_RACH(0),
+    .C_ERROR_INJECTION_TYPE_RDCH(0),
+    .C_ERROR_INJECTION_TYPE_WACH(0),
+    .C_ERROR_INJECTION_TYPE_WDCH(0),
+    .C_ERROR_INJECTION_TYPE_WRCH(0),
+    .C_FAMILY(""spartan3""),
+    .C_FULL_FLAGS_RST_VAL(0),
+    .C_HAS_ALMOST_EMPTY(0),
+    .C_HAS_ALMOST_FULL(0),
+    .C_HAS_AXI_ARUSER(0),
+    .C_HAS_AXI_AWUSER(0),
+    .C_HAS_AXI_BUSER(0),
+    .C_HAS_AXI_RD_CHANNEL(0),
+    .C_HAS_AXI_RUSER(0),
+    .C_HAS_AXI_WR_CHANNEL(0),
+    .C_HAS_AXI_WUSER(0),
+    .C_HAS_AXIS_TDATA(0),
+    .C_HAS_AXIS_TDEST(0),
+    .C_HAS_AXIS_TID(0),
+    .C_HAS_AXIS_TKEEP(0),
+    .C_HAS_AXIS_TLAST(0),
+    .C_HAS_AXIS_TREADY(1),
+    .C_HAS_AXIS_TSTRB(0),
+    .C_HAS_AXIS_TUSER(0),
+    .C_HAS_BACKUP(0),
+    .C_HAS_DATA_COUNT(0),
+    .C_HAS_DATA_COUNTS_AXIS(0),
+    .C_HAS_DATA_COUNTS_RACH(0),
+    .C_HAS_DATA_COUNTS_RDCH(0),
+    .C_HAS_DATA_COUNTS_WACH(0),
+    .C_HAS_DATA_COUNTS_WDCH(0),
+    .C_HAS_DATA_COUNTS_WRCH(0),
+    .C_HAS_INT_CLK(0),
+    .C_HAS_MASTER_CE(0),
+    .C_HAS_MEMINIT_FILE(0),
+    .C_HAS_OVERFLOW(0),
+    .C_HAS_PROG_FLAGS_AXIS(0),
+    .C_HAS_PROG_FLAGS_RACH(0),
+    .C_HAS_PROG_FLAGS_RDCH(0),
+    .C_HAS_PROG_FLAGS_WACH(0),
+    .C_HAS_PROG_FLAGS_WDCH(0),
+    .C_HAS_PROG_FLAGS_WRCH(0),
+    .C_HAS_RD_DATA_COUNT(0),
+    .C_HAS_RD_RST(0),
+    .C_HAS_RST(1),
+    .C_HAS_SLAVE_CE(0),
+    .C_HAS_SRST(0),
+    .C_HAS_UNDERFLOW(0),
+    .C_HAS_VALID(0),
+    .C_HAS_WR_ACK(0),
+    .C_HAS_WR_DATA_COUNT(0),
+    .C_HAS_WR_RST(0),
+    .C_IMPLEMENTATION_TYPE(2),
+    .C_IMPLEMENTATION_TYPE_AXIS(1),
+    .C_IMPLEMENTATION_TYPE_RACH(1),
+    .C_IMPLEMENTATION_TYPE_RDCH(1),
+    .C_IMPLEMENTATION_TYPE_WACH(1),
+    .C_IMPLEMENTATION_TYPE_WDCH(1),
+    .C_IMPLEMENTATION_TYPE_WRCH(1),
+    .C_INIT_WR_PNTR_VAL(0),
+    .C_INTERFACE_TYPE(0),
+    .C_MEMORY_TYPE(2),
+    .C_MIF_FILE_NAME(""BlankString""),
+    .C_MSGON_VAL(1),
+    .C_OPTIMIZATION_MODE(0),
+    .C_OVERFLOW_LOW(0),
+    .C_PRELOAD_LATENCY(0),
+    .C_PRELOAD_REGS(1),
+    .C_PRIM_FIFO_TYPE(""512x36""),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
+    .C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
+    .C_PROG_EMPTY_TYPE(0),
+    .C_PROG_EMPTY_TYPE_AXIS(0),
+    .C_PROG_EMPTY_TYPE_RACH(0),
+    .C_PROG_EMPTY_TYPE_RDCH(0),
+    .C_PROG_EMPTY_TYPE_WACH(0),
+    .C_PROG_EMPTY_TYPE_WDCH(0),
+    .C_PROG_EMPTY_TYPE_WRCH(0),
+    .C_PROG_FULL_THRESH_ASSERT_VAL(31),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
+    .C_PROG_FULL_THRESH_NEGATE_VAL(30),
+    .C_PROG_FULL_TYPE(0),
+    .C_PROG_FULL_TYPE_AXIS(0),
+    .C_PROG_FULL_TYPE_RACH(0),
+    .C_PROG_FULL_TYPE_RDCH(0),
+    .C_PROG_FULL_TYPE_WACH(0),
+    .C_PROG_FULL_TYPE_WDCH(0),
+    .C_PROG_FULL_TYPE_WRCH(0),
+    .C_RACH_TYPE(0),
+    .C_RD_DATA_COUNT_WIDTH(5),
+    .C_RD_DEPTH(32),
+    .C_RD_FREQ(1),
+    .C_RD_PNTR_WIDTH(5),
+    .C_RDCH_TYPE(0),
+    .C_REG_SLICE_MODE_AXIS(0),
+    .C_REG_SLICE_MODE_RACH(0),
+    .C_REG_SLICE_MODE_RDCH(0),
+    .C_REG_SLICE_MODE_WACH(0),
+    .C_REG_SLICE_MODE_WDCH(0),
+    .C_REG_SLICE_MODE_WRCH(0),
+    .C_SYNCHRONIZER_STAGE(2),
+    .C_UNDERFLOW_LOW(0),
+    .C_USE_COMMON_OVERFLOW(0),
+    .C_USE_COMMON_UNDERFLOW(0),
+    .C_USE_DEFAULT_SETTINGS(0),
+    .C_USE_DOUT_RST(1),
+    .C_USE_ECC(0),
+    .C_USE_ECC_AXIS(0),
+    .C_USE_ECC_RACH(0),
+    .C_USE_ECC_RDCH(0),
+    .C_USE_ECC_WACH(0),
+    .C_USE_ECC_WDCH(0),
+    .C_USE_ECC_WRCH(0),
+    .C_USE_EMBEDDED_REG(0),
+    .C_USE_FIFO16_FLAGS(0),
+    .C_USE_FWFT_DATA_COUNT(0),
+    .C_VALID_LOW(0),
+    .C_WACH_TYPE(0),
+    .C_WDCH_TYPE(0),
+    .C_WR_ACK_LOW(0),
+    .C_WR_DATA_COUNT_WIDTH(5),
+    .C_WR_DEPTH(32),
+    .C_WR_DEPTH_AXIS(1024),
+    .C_WR_DEPTH_RACH(16),
+    .C_WR_DEPTH_RDCH(1024),
+    .C_WR_DEPTH_WACH(16),
+    .C_WR_DEPTH_WDCH(1024),
+    .C_WR_DEPTH_WRCH(16),
+    .C_WR_FREQ(1),
+    .C_WR_PNTR_WIDTH(5),
+    .C_WR_PNTR_WIDTH_AXIS(10),
+    .C_WR_PNTR_WIDTH_RACH(4),
+    .C_WR_PNTR_WIDTH_RDCH(10),
+    .C_WR_PNTR_WIDTH_WACH(4),
+    .C_WR_PNTR_WIDTH_WDCH(10),
+    .C_WR_PNTR_WIDTH_WRCH(4),
+    .C_WR_RESPONSE_LATENCY(1),
+    .C_WRCH_TYPE(0)
+  )
+  inst (
+    .RST(rst),
+    .WR_CLK(wr_clk),
+    .RD_CLK(rd_clk),
+    .DIN(din),
+    .WR_EN(wr_en),
+    .RD_EN(rd_en),
+    .DOUT(dout),
+    .FULL(full),
+    .EMPTY(empty),
+    .BACKUP(),
+    .BACKUP_MARKER(),
+    .CLK(),
+    .SRST(),
+    .WR_RST(),
+    .RD_RST(),
+    .PROG_EMPTY_THRESH(),
+    .PROG_EMPTY_THRESH_ASSERT(),
+    .PROG_EMPTY_THRESH_NEGATE(),
+    .PROG_FULL_THRESH(),
+    .PROG_FULL_THRESH_ASSERT(),
+    .PROG_FULL_THRESH_NEGATE(),
+    .INT_CLK(),
+    .INJECTDBITERR(),
+    .INJECTSBITERR(),
+    .ALMOST_FULL(),
+    .WR_ACK(),
+    .OVERFLOW(),
+    .ALMOST_EMPTY(),
+    .VALID(),
+    .UNDERFLOW(),
+    .DATA_COUNT(),
+    .RD_DATA_COUNT(),
+    .WR_DATA_COUNT(),
+    .PROG_FULL(),
+    .PROG_EMPTY(),
+    .SBITERR(),
+    .DBITERR(),
+    .M_ACLK(),
+    .S_ACLK(),
+    .S_ARESETN(),
+    .M_ACLK_EN(),
+    .S_ACLK_EN(),
+    .S_AXI_AWID(),
+    .S_AXI_AWADDR(),
+    .S_AXI_AWLEN(),
+    .S_AXI_AWSIZE(),
+    .S_AXI_AWBURST(),
+    .S_AXI_AWLOCK(),
+    .S_AXI_AWCACHE(),
+    .S_AXI_AWPROT(),
+    .S_AXI_AWQOS(),
+    .S_AXI_AWREGION(),
+    .S_AXI_AWUSER(),
+    .S_AXI_AWVALID(),
+    .S_AXI_AWREADY(),
+    .S_AXI_WID(),
+    .S_AXI_WDATA(),
+    .S_AXI_WSTRB(),
+    .S_AXI_WLAST(),
+    .S_AXI_WUSER(),
+    .S_AXI_WVALID(),
+    .S_AXI_WREADY(),
+    .S_AXI_BID(),
+    .S_AXI_BRESP(),
+    .S_AXI_BUSER(),
+    .S_AXI_BVALID(),
+    .S_AXI_BREADY(),
+    .M_AXI_AWID(),
+    .M_AXI_AWADDR(),
+    .M_AXI_AWLEN(),
+    .M_AXI_AWSIZE(),
+    .M_AXI_AWBURST(),
+    .M_AXI_AWLOCK(),
+    .M_AXI_AWCACHE(),
+    .M_AXI_AWPROT(),
+    .M_AXI_AWQOS(),
+    .M_AXI_AWREGION(),
+    .M_AXI_AWUSER(),
+    .M_AXI_AWVALID(),
+    .M_AXI_AWREADY(),
+    .M_AXI_WID(),
+    .M_AXI_WDATA(),
+    .M_AXI_WSTRB(),
+    .M_AXI_WLAST(),
+    .M_AXI_WUSER(),
+    .M_AXI_WVALID(),
+    .M_AXI_WREADY(),
+    .M_AXI_BID(),
+    .M_AXI_BRESP(),
+    .M_AXI_BUSER(),
+    .M_AXI_BVALID(),
+    .M_AXI_BREADY(),
+    .S_AXI_ARID(),
+    .S_AXI_ARADDR(),
+    .S_AXI_ARLEN(),
+    .S_AXI_ARSIZE(),
+    .S_AXI_ARBURST(),
+    .S_AXI_ARLOCK(),
+    .S_AXI_ARCACHE(),
+    .S_AXI_ARPROT(),
+    .S_AXI_ARQOS(),
+    .S_AXI_ARREGION(),
+    .S_AXI_ARUSER(),
+    .S_AXI_ARVALID(),
+    .S_AXI_ARREADY(),
+    .S_AXI_RID(),
+    .S_AXI_RDATA(),
+    .S_AXI_RRESP(),
+    .S_AXI_RLAST(),
+    .S_AXI_RUSER(),
+    .S_AXI_RVALID(),
+    .S_AXI_RREADY(),
+    .M_AXI_ARID(),
+    .M_AXI_ARADDR(),
+    .M_AXI_ARLEN(),
+    .M_AXI_ARSIZE(),
+    .M_AXI_ARBURST(),
+    .M_AXI_ARLOCK(),
+    .M_AXI_ARCACHE(),
+    .M_AXI_ARPROT(),
+    .M_AXI_ARQOS(),
+    .M_AXI_ARREGION(),
+    .M_AXI_ARUSER(),
+    .M_AXI_ARVALID(),
+    .M_AXI_ARREADY(),
+    .M_AXI_RID(),
+    .M_AXI_RDATA(),
+    .M_AXI_RRESP(),
+    .M_AXI_RLAST(),
+    .M_AXI_RUSER(),
+    .M_AXI_RVALID(),
+    .M_AXI_RREADY(),
+    .S_AXIS_TVALID(),
+    .S_AXIS_TREADY(),
+    .S_AXIS_TDATA(),
+    .S_AXIS_TSTRB(),
+    .S_AXIS_TKEEP(),
+    .S_AXIS_TLAST(),
+    .S_AXIS_TID(),
+    .S_AXIS_TDEST(),
+    .S_AXIS_TUSER(),
+    .M_AXIS_TVALID(),
+    .M_AXIS_TREADY(),
+    .M_AXIS_TDATA(),
+    .M_AXIS_TSTRB(),
+    .M_AXIS_TKEEP(),
+    .M_AXIS_TLAST(),
+    .M_AXIS_TID(),
+    .M_AXIS_TDEST(),
+    .M_AXIS_TUSER(),
+    .AXI_AW_INJECTSBITERR(),
+    .AXI_AW_INJECTDBITERR(),
+    .AXI_AW_PROG_FULL_THRESH(),
+    .AXI_AW_PROG_EMPTY_THRESH(),
+    .AXI_AW_DATA_COUNT(),
+    .AXI_AW_WR_DATA_COUNT(),
+    .AXI_AW_RD_DATA_COUNT(),
+    .AXI_AW_SBITERR(),
+    .AXI_AW_DBITERR(),
+    .AXI_AW_OVERFLOW(),
+    .AXI_AW_UNDERFLOW(),
+    .AXI_AW_PROG_FULL(),
+    .AXI_AW_PROG_EMPTY(),
+    .AXI_W_INJECTSBITERR(),
+    .AXI_W_INJECTDBITERR(),
+    .AXI_W_PROG_FULL_THRESH(),
+    .AXI_W_PROG_EMPTY_THRESH(),
+    .AXI_W_DATA_COUNT(),
+    .AXI_W_WR_DATA_COUNT(),
+    .AXI_W_RD_DATA_COUNT(),
+    .AXI_W_SBITERR(),
+    .AXI_W_DBITERR(),
+    .AXI_W_OVERFLOW(),
+    .AXI_W_UNDERFLOW(),
+    .AXI_B_INJECTSBITERR(),
+    .AXI_W_PROG_FULL(),
+    .AXI_W_PROG_EMPTY(),
+    .AXI_B_INJECTDBITERR(),
+    .AXI_B_PROG_FULL_THRESH(),
+    .AXI_B_PROG_EMPTY_THRESH(),
+    .AXI_B_DATA_COUNT(),
+    .AXI_B_WR_DATA_COUNT(),
+    .AXI_B_RD_DATA_COUNT(),
+    .AXI_B_SBITERR(),
+    .AXI_B_DBITERR(),
+    .AXI_B_OVERFLOW(),
+    .AXI_B_UNDERFLOW(),
+    .AXI_AR_INJECTSBITERR(),
+    .AXI_B_PROG_FULL(),
+    .AXI_B_PROG_EMPTY(),
+    .AXI_AR_INJECTDBITERR(),
+    .AXI_AR_PROG_FULL_THRESH(),
+    .AXI_AR_PROG_EMPTY_THRESH(),
+    .AXI_AR_DATA_COUNT(),
+    .AXI_AR_WR_DATA_COUNT(),
+    .AXI_AR_RD_DATA_COUNT(),
+    .AXI_AR_SBITERR(),
+    .AXI_AR_DBITERR(),
+    .AXI_AR_OVERFLOW(),
+    .AXI_AR_UNDERFLOW(),
+    .AXI_AR_PROG_FULL(),
+    .AXI_AR_PROG_EMPTY(),
+    .AXI_R_INJECTSBITERR(),
+    .AXI_R_INJECTDBITERR(),
+    .AXI_R_PROG_FULL_THRESH(),
+    .AXI_R_PROG_EMPTY_THRESH(),
+    .AXI_R_DATA_COUNT(),
+    .AXI_R_WR_DATA_COUNT(),
+    .AXI_R_RD_DATA_COUNT(),
+    .AXI_R_SBITERR(),
+    .AXI_R_DBITERR(),
+    .AXI_R_OVERFLOW(),
+    .AXI_R_UNDERFLOW(),
+    .AXIS_INJECTSBITERR(),
+    .AXI_R_PROG_FULL(),
+    .AXI_R_PROG_EMPTY(),
+    .AXIS_INJECTDBITERR(),
+    .AXIS_PROG_FULL_THRESH(),
+    .AXIS_PROG_EMPTY_THRESH(),
+    .AXIS_DATA_COUNT(),
+    .AXIS_WR_DATA_COUNT(),
+    .AXIS_RD_DATA_COUNT(),
+    .AXIS_SBITERR(),
+    .AXIS_DBITERR(),
+    .AXIS_OVERFLOW(),
+    .AXIS_UNDERFLOW(),
+    .AXIS_PROG_FULL(),
+    .AXIS_PROG_EMPTY()
+  );
+
+// synthesis translate_on
+
+endmodule
+"
+"//////////////////////////////////////////////////////////////////
+//                                                              //
+//  Co-processor module for Amber 2 Core                        //
+//                                                              //
+//  This file is part of the Amber project                      //
+//  http://www.opencores.org/project,amber                      //
+//                                                              //
+//  Description                                                 //
+//  Co_processor 15 registers and control signals               //                                                           //
+//  Author(s):                                                  //
+//      - Conor Santifort, csantifort.amber@gmail.com           //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+//                                                              //
+// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
+//                                                              //
+// This source file may be used and distributed without         //
+// restriction provided that this copyright statement is not    //
+// removed from the file and that any derivative work contains  //
+// the original copyright notice and the associated disclaimer. //
+//                                                              //
+// This source file is free software; you can redistribute it   //
+// and/or modify it under the terms of the GNU Lesser General   //
+// Public License as published by the Free Software Foundation; //
+// either version 2.1 of the License, or (at your option) any   //
+// later version.                                               //
+//                                                              //
+// This source is distributed in the hope that it will be       //
+// useful, but WITHOUT ANY WARRANTY; without even the implied   //
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
+// PURPOSE.  See the GNU Lesser General Public License for more //
+// details.                                                     //
+//                                                              //
+// You should have received a copy of the GNU Lesser General    //
+// Public License along with this source; if not, download it   //
+// from http://www.opencores.org/lgpl.shtml                     //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+
+
+module a23_coprocessor
+(
+input                       i_clk,
+input                       i_fetch_stall,    // stall all stages of the cpu at the same time
+input       [2:0]           i_copro_opcode1,
+input       [2:0]           i_copro_opcode2,
+input       [3:0]           i_copro_crn,      // Register Number 
+input       [3:0]           i_copro_crm,
+input       [3:0]           i_copro_num,
+input       [1:0]           i_copro_operation,
+input       [31:0]          i_copro_write_data,
+
+input                       i_fault,          // high to latch the fault address and status
+input       [7:0]           i_fault_status,
+input       [31:0]          i_fault_address,  // the address that caused the fault
+
+output reg  [31:0]          o_copro_read_data,
+output                      o_cache_enable,
+output                      o_cache_flush,
+output      [31:0]          o_cacheable_area 
+);
+
+// Bit 0 - Cache on(1)/off
+// Bit 1 - Shared (1) or seperate User/Supervisor address space
+// Bit 2 - address monitor mode(1)
+reg [2:0]  cache_control = 3\'b000;
+
+// Bit 0 - 2MB memory from 0 to 0x01fffff cacheable(1)/not cachable
+// Bit 1 - next 2MB region etc.
+reg [31:0] cacheable_area = 32\'h0;
+
+// Marks memory regions as read only so writes are ignored by the cache
+// Bit 0 - 2MB memory from 0 to 0x01fffff updateable(1)/not updateable
+// Bit 1 - next 2MB region etc.
+reg [31:0] updateable_area = 32\'h0;
+
+// Accesses to a region with a flag set in this register cause the
+// cache to flush
+// Bit 0 - 2MB memory from 0 to 0x01fffff
+// Bit 1 - next 2MB region etc.
+reg [31:0] disruptive_area = 32\'h0;
+
+
+reg [7:0]  fault_status  = \'d0;
+reg [31:0] fault_address = \'d0;  // the address that caused the fault
+
+wire       copro15_reg1_write;
+
+
+// ---------------------------
+// Outputs
+// ---------------------------
+assign o_cache_enable   = cache_control[0];
+assign o_cache_flush    = copro15_reg1_write;
+assign o_cacheable_area = cacheable_area;
+              
+// ---------------------------
+// Capture an access fault address and status
+// ---------------------------
+always @ ( posedge i_clk )
+    if ( !i_fetch_stall )
+        begin
+        if ( i_fault )
+            begin
+            
+            `ifdef A23_COPRO15_DEBUG    
+            $display (""Fault status  set to 0x%08x"", i_fault_status);
+            $display (""Fault address set to 0x%08x"", i_fault_address);
+            `endif        
+            fault_status    <= i_fault_status;
+            fault_address   <= i_fault_address;
+            end
+        end
+
+
+// ---------------------------
+// Register Writes
+// ---------------------------
+always @ ( posedge i_clk )
+    if ( !i_fetch_stall )         
+        begin
+        if ( i_copro_operation == 2\'d2 )
+            case ( i_copro_crn )
+                4\'d2: cache_control   <= i_copro_write_data[2:0];
+                4\'d3: cacheable_area  <= i_copro_write_data[31:0];
+                4\'d4: updateable_area <= i_copro_write_data[31:0];
+                4\'d5: disruptive_area <= i_copro_write_data[31:0];
+            endcase
+        end
+
+// Flush the cache
+assign copro15_reg1_write = !i_fetch_stall && i_copro_operation == 2\'d2 && i_copro_crn == 4\'d1;
+
+
+// ---------------------------
+// Register Reads   
+// ---------------------------
+always @ ( posedge i_clk )        
+    if ( !i_fetch_stall )
+        case ( i_copro_crn )
+            // ID Register - [31:24] Company id, [23:16] Manuf id, [15:8] Part type, [7:0] revision
+            4\'d0:    o_copro_read_data <= 32\'h4156_0300;
+            4\'d2:    o_copro_read_data <= {29\'d0, cache_control}; 
+            4\'d3:    o_copro_read_data <= cacheable_area; 
+            4\'d4:    o_copro_read_data <= updateable_area; 
+            4\'d5:    o_copro_read_data <= disruptive_area; 
+            4\'d6:    o_copro_read_data <= {24\'d0, fault_status };
+            4\'d7:    o_copro_read_data <= fault_address;
+            default: o_copro_read_data <= 32\'d0;
+        endcase
+
+
+
+// ========================================================
+// Debug code - not synthesizable
+// ========================================================
+
+`ifdef A23_COPRO15_DEBUG    
+//synopsys translate_off
+reg [1:0]  copro_operation_d1;
+reg [3:0]  copro_crn_d1;
+
+always @( posedge i_clk )
+    if ( !i_fetch_stall )
+        begin
+        copro_operation_d1  <= i_copro_operation;
+        copro_crn_d1        <= i_copro_crn;
+        end
+
+always @( posedge i_clk )
+    if ( !i_fetch_stall )
+        begin
+        if ( i_copro_operation == 2\'d2 )  // mcr
+            case ( i_copro_crn )
+                4\'d 1: begin `TB_DEBUG_MESSAGE $display (""Write 0x%08h to   Co-Pro 15 #1, Flush Cache"", i_copro_write_data); end
+                4\'d 2: begin `TB_DEBUG_MESSAGE $display (""Write 0x%08h to   Co-Pro 15 #2, Cache Control"", i_copro_write_data); end
+                4\'d 3: begin `TB_DEBUG_MESSAGE $display (""Write 0x%08h to   Co-Pro 15 #3, Cacheable area"", i_copro_write_data); end
+                4\'d 4: begin `TB_DEBUG_MESSAGE $display (""Write 0x%08h to   Co-Pro 15 #4, Updateable area"", i_copro_write_data); end
+                4\'d 5: begin `TB_DEBUG_MESSAGE $display (""Write 0x%08h to   Co-Pro 15 #5, Disruptive area"", i_copro_write_data); end
+            endcase
+            
+        if ( copro_operation_d1 == 2\'d1 ) // mrc
+            case ( copro_crn_d1 )
+                4\'d 0: begin `TB_DEBUG_MESSAGE $display (""Read  0x%08h from Co-Pro 15 #0, ID Register"", o_copro_read_data); end
+                4\'d 2: begin `TB_DEBUG_MESSAGE $display (""Read  0x%08h from Co-Pro 15 #2, Cache control"", o_copro_read_data); end
+                4\'d 3: begin `TB_DEBUG_MESSAGE $display (""Read  0x%08h from Co-Pro 15 #3, Cacheable area"", o_copro_read_data); end
+                4\'d 4: begin `TB_DEBUG_MESSAGE $display (""Read  0x%08h from Co-Pro 15 #4, Updateable area"", o_copro_read_data); end
+                4\'d 5: begin `TB_DEBUG_MESSAGE $display (""Read  0x%08h from Co-Pro 15 #4, Disruptive area"", o_copro_read_data); end
+                4\'d 6: begin `TB_DEBUG_MESSAGE $display (""Read  0x%08h from Co-Pro 15 #6, Fault Status Register"", o_copro_read_data); end
+                4\'d 7: begin `TB_DEBUG_MESSAGE $display (""Read  0x%08h from Co-Pro 15 #7, Fault Address Register"", o_copro_read_data); end
+            endcase
+    end
+//synopsys translate_on
+`endif
+
+endmodule
+
+"
+"//----------------------------------------------------------------------------
+// Wishbone SRAM controller
+//----------------------------------------------------------------------------
+module wb_sram32 #(
+        parameter                  adr_width = 19,   
+        parameter                  latency   = 2    // 0 .. 7
+) (
+        input                      clk,
+        input                      reset,
+        // Wishbone interface
+        input                      wb_stb_i,
+        input                      wb_cyc_i,
+        output reg                 wb_ack_o,
+        input                      wb_we_i,
+        input               [31:0] wb_adr_i,
+        input                [3:0] wb_sel_i,
+        input               [31:0] wb_dat_i,
+        output reg          [31:0] wb_dat_o,
+        // SRAM connection
+        output reg [adr_width-1:0] sram_adr,
+        inout               [31:0] sram_dat,
+        output reg           [1:0] sram_be_n,    // Byte   Enable
+        output reg                 sram_ce_n,    // Chip   Enable
+        output reg                 sram_oe_n,    // Output Enable
+        output reg                 sram_we_n     // Write  Enable
+);
+
+//----------------------------------------------------------------------------
+//
+//----------------------------------------------------------------------------
+
+// Wishbone handling
+wire wb_rd = wb_stb_i & wb_cyc_i & ~wb_we_i & ~wb_ack_o;
+wire wb_wr_word = wb_stb_i & wb_cyc_i & wb_we_i & (wb_sel_i == 4'b1111) & ~wb_ack_o;
+wire wb_wr_byte = wb_stb_i & wb_cyc_i & wb_we_i & (wb_sel_i != 4'b1111) & ~wb_ack_o;
+
+// Translate wishbone address to sram address
+wire [adr_width-1:0] adr = wb_adr_i[adr_width+1:2];
+
+// Tri-State-Driver
+reg [31:0] wdat;
+reg        wdat_oe;
+  
+assign sram_dat = wdat_oe ? wdat : 32'bz;
+
+// Merged data for byte enables writes
+wire [31:0] merged_dat = {(wb_sel_i[3] ? wb_dat_i[31:24] : sram_dat[31:24]),
+                          (wb_sel_i[2] ? wb_dat_i[23:16] : sram_dat[23:16]),
+                          (wb_sel_i[1] ? wb_dat_i[15: 8] : sram_dat[15: 8]),
+                          (wb_sel_i[0] ? wb_dat_i[ 7: 0] : sram_dat[ 7: 0])};
+
+// Latency countdown
+reg  [2:0] lcount;
+
+//----------------------------------------------------------------------------
+// State Machine
+//----------------------------------------------------------------------------
+parameter s_idle              = 0;
+parameter s_read              = 1;
+parameter s_read_modify_write = 2;
+parameter s_write             = 3;
+
+reg [2:0] state;
+
+always @(posedge clk)
+begin
+        if (reset) begin
+                state    <= s_idle;
+                lcount   <= 0;
+                wb_ack_o <= 0;
+        end else begin
+                case (state)
+                s_idle: begin
+                        wb_ack_o <= 0;
+
+                        if (wb_rd) begin
+                                sram_ce_n  <=  0;
+                                sram_oe_n  <=  0;
+                                sram_we_n  <=  1;
+                                sram_adr   <=  adr;
+                                sram_be_n  <=  2'b00;
+                                wdat_oe    <=  0;
+                                lcount     <=  latency;
+                                state      <=  s_read;
+                        end else if (wb_wr_word) begin
+                                sram_ce_n  <=  0;
+                                sram_oe_n  <=  1;
+                                sram_we_n  <=  0;
+                                sram_adr   <=  adr;
+                                sram_be_n  <=  2'b00;
+                                wdat       <=  wb_dat_i;
+                                wdat_oe    <=  1;
+                                lcount     <=  latency;
+                                state      <=  s_write;
+                        end else if (wb_wr_byte) begin
+                                sram_ce_n  <=  0;
+                                sram_oe_n  <=  0;
+                                sram_we_n  <=  1;
+                                sram_adr   <=  adr;
+                                sram_be_n  <=  2'b00;
+                                wdat_oe    <=  0;
+                                lcount     <=  latency;
+                                state      <=  s_read_modify_write;
+                        end else begin
+                                sram_ce_n  <=  1;
+                                sram_oe_n  <=  1;
+                                sram_we_n  <=  1;
+                                wdat_oe    <=  0;
+                        end
+                end
+                s_read: begin
+                        if (lcount != 0) begin
+                                lcount     <= lcount - 1;
+                        end else begin
+                                sram_ce_n  <=  1;
+                                sram_oe_n  <=  1;
+                                sram_we_n  <=  1;
+                                wb_dat_o   <=  sram_dat;
+                                wb_ack_o   <=  1;
+                                state      <=  s_idle;
+                        end
+                end
+                s_read_modify_write: begin
+                        if (lcount != 0) begin
+                                lcount     <= lcount - 1;
+                        end else begin
+                                sram_ce_n  <=  0;
+                                sram_oe_n  <=  1;
+                                sram_we_n  <=  0;
+                                sram_adr   <=  adr;
+                                sram_be_n  <=  2'b00;
+                                wdat       <=  merged_dat;                           
+                                wdat_oe    <=  1;
+                                lcount     <=  latency;
+                                state      <=  s_write;
+                        end
+                end
+                s_write: begin
+                        if (lcount != 0) begin
+                                lcount     <= lcount - 1;
+                        end else begin
+                                sram_ce_n  <=  1;
+                                sram_oe_n  <=  1;
+                                sram_we_n  <=  1;
+                                wb_ack_o   <=  1;       // XXX   We could acknoledge write  XXX
+                                state      <=  s_idle;  // XXX   requests 1 cycle ahead     XXX
+                        end
+                end
+                endcase
+        end
+end
+
+endmodule
+"
+"//----------------------------------------------------------------------------
+// Wishbone Tube controller
+//----------------------------------------------------------------------------
+module wb_tube #(
+        parameter                  latency   = 0    // 0 .. 7
+) (
+        input                      clk,
+        input                      reset,
+        // Wishbone interface
+        input                      wb_stb_i,
+        input                      wb_cyc_i,
+        input                      wb_tga_i,
+        output reg                 wb_ack_o,
+        input                      wb_we_i,
+        input                [2:0] wb_adr_i,
+        input                [1:0] wb_sel_i,
+        input               [15:0] wb_dat_i,
+        output reg          [15:0] wb_dat_o,
+
+        // TUBE connection
+        output reg           [2:0] tube_adr,
+        inout                [7:0] tube_dat,
+        output reg                 tube_cs_n,    // Chip Select
+        output reg                 tube_rd_n,    // Read
+        output reg                 tube_wr_n     // Write
+);
+
+//----------------------------------------------------------------------------
+//
+//----------------------------------------------------------------------------
+
+// Wishbone handling
+wire wb_rd = wb_stb_i & wb_cyc_i & ~wb_we_i & ~wb_ack_o;
+wire wb_wr = wb_stb_i & wb_cyc_i &  wb_we_i & ~wb_ack_o;
+
+// Tri-State-Driver
+reg [7:0] wdat;
+reg       wdat_oe;
+
+assign tube_dat = wdat_oe ? wdat : 8'bz;
+
+
+// Latency countdown
+reg  [2:0] lcount;
+
+//----------------------------------------------------------------------------
+// State Machine
+//----------------------------------------------------------------------------
+parameter s_idle   = 0;
+parameter s_read   = 1;
+parameter s_write  = 2;
+
+reg [2:0] state;
+
+always @(posedge clk)
+begin
+        if (reset) begin
+                state    <= s_idle;
+                lcount   <= 0;
+                wb_ack_o <= 0;
+        end else begin
+                case (state)
+                s_idle: begin
+                        wb_ack_o <= 0;
+
+                        if (wb_rd) begin
+                                tube_cs_n  <=  0;
+                                tube_rd_n  <=  0;
+                                tube_wr_n  <=  1;
+                                tube_adr   <=  wb_adr_i;
+                                wdat_oe    <=  0;
+                                lcount     <=  latency;
+                                state      <=  s_read;
+                        end else if (wb_wr) begin
+                                tube_cs_n  <=  0;
+                                tube_rd_n  <=  1;
+                                tube_wr_n  <=  0;
+                                tube_adr   <=  wb_adr_i;
+                                wdat       <=  wb_dat_i[7:0];
+                                wdat_oe    <=  1;
+                                lcount     <=  latency;
+                                state      <=  s_write;
+                        end else begin
+                                tube_cs_n  <=  1;
+                                tube_rd_n  <=  1;
+                                tube_wr_n  <=  1;
+                                wdat_oe    <=  0;
+                        end
+                end
+                s_read: begin
+                        if (lcount != 0) begin
+                                lcount     <= lcount - 1;
+                        end else begin
+                                tube_cs_n  <=  1;
+                                tube_rd_n  <=  1;
+                                tube_wr_n  <=  1;
+                                wb_dat_o   <=  tube_dat;
+                                wb_ack_o   <=  1;
+                                state      <=  s_idle;
+                        end
+                end
+                s_write: begin
+                        if (lcount != 0) begin
+                                lcount     <= lcount - 1;
+                        end else begin
+                                tube_cs_n  <=  1;
+                                tube_rd_n  <=  1;
+                                tube_wr_n  <=  1;
+                                wb_ack_o   <=  1;       // XXX   We could acknoledge write  XXX
+                                state      <=  s_idle;  // XXX   requests 1 cycle ahead     XXX
+                        end
+                end
+                endcase
+        end
+end
+
+endmodule
+"
+"/*
+ *  Decoder for x86 memory access registers
+ *  Copyright (C) 2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+module zet_memory_regs (
+    input [2:0] rm,
+    input [1:0] mod,
+    input [2:0] sovr_pr,
+
+    output reg [3:0] base,
+    output reg [3:0] index,
+    output     [1:0] seg
+  );
+
+  // Register declaration
+  reg [1:0] s;
+
+  // Continuous assignments
+  assign seg = sovr_pr[2] ? sovr_pr[1:0] : s;
+
+  // Behaviour
+  always @(rm or mod)
+    case (rm)
+      3'b000: begin base <= 4'b0011; index <= 4'b0110; s <= 2'b11; end
+      3'b001: begin base <= 4'b0011; index <= 4'b0111; s <= 2'b11; end
+      3'b010: begin base <= 4'b0101; index <= 4'b0110; s <= 2'b10; end
+      3'b011: begin base <= 4'b0101; index <= 4'b0111; s <= 2'b10; end
+      3'b100: begin base <= 4'b1100; index <= 4'b0110; s <= 2'b11; end
+      3'b101: begin base <= 4'b1100; index <= 4'b0111; s <= 2'b11; end
+      3'b110: begin base <= mod ? 4'b0101 : 4'b1100; index <= 4'b1100;
+                    s <= mod ? 2'b10 : 2'b11; end
+      3'b111: begin base <= 4'b0011; index <= 4'b1100; s <= 2'b11; end
+    endcase
+endmodule
+"
+"/*
+ *  Phase accumulator clock generator:
+ *   Output Frequency Fo = Fc * N / 2^bits
+ *   Output Jitter = 1/Fc
+ *
+ *  Copyright (c) 2009,2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+module clk_gen #(
+    parameter res    = 20,    // bits - bit resolution
+    parameter phase  =  1     // N - phase value for the counter
+  )(
+    input      clk_i, // Fc - input frequency
+    input      rst_i,
+    output     clk_o  // Fo - output frequency
+  );
+
+  // Registers and nets
+  reg [res-1:0] cnt;
+
+  // Continuous assignments
+  assign clk_o = cnt[res-1];
+
+  // Behaviour
+  always @(posedge clk_i)
+    cnt <= rst_i ? {res{1'b0}} : (cnt + phase);
+
+endmodule
+"
+"`define CONFIG_SWITCHES 32'h0
+
+module LX9CoPro32016 (
+    input fastclk,
+
+    // GOP Signals
+    output[8:1] test,
+    input [3:0] sw,
+
+    // Tube signals
+    input h_phi2,
+    input [2:0] h_addr,
+    inout [7:0] h_data,
+    input h_rdnw,
+    input h_cs_b,
+    input h_rst_b,
+    output h_irq_b,
+
+    // Ram Signals
+    output reg ram_ub_b,
+    output reg ram_lb_b,
+    output reg ram_cs,
+    output reg ram_oe,
+    output reg ram_wr,
+    output reg [18:0] ram_addr,
+    inout  [31:0] ram_data
+);
+
+    wire        clk;
+    wire        nclk;
+    reg         rst_reg;
+    reg         nmi_reg;
+    reg         irq_reg;
+
+    wire [2:0]  p_addr;
+    wire        p_cs_b;
+    wire [7:0]  p_data_in;
+    wire [7:0]  p_data_out;
+    wire        p_rd_b;
+    wire        p_wr_b;
+    wire        p_rst_b;
+    wire        p_nmi_b;
+    wire        p_irq_b;
+
+    wire        IO_WR;
+    wire        IO_RD;
+    wire [31:0] IO_A;
+    wire  [3:0] IO_BE;
+    wire [31:0] IO_DI;
+    wire [31:0] IO_Q;
+    wire        IO_READY;
+
+    wire        ram_enable;
+    wire        rom_enable;
+    wire        tube_enable;
+    wire        config_enable;
+
+    reg  [31:0] ram_dout;
+    wire [31:0] rom_dout;
+
+    reg         bootmode;
+    reg         rd_rdy;
+
+    wire [3:0]  status;
+    wire [7:0]  statsigs;
+
+    ICAP_config inst_ICAP_config (
+        .fastclk(fastclk),
+        .sw_in  (sw),
+        .sw_out (),
+        .h_addr (h_addr),
+        .h_cs_b (h_cs_b),
+        .h_data (h_data),
+        .h_phi2 (h_phi2),
+        .h_rdnw (h_rdnw),
+        .h_rst_b(h_rst_b)
+    );
+
+    assign clk = fastclk;
+    assign nclk = ~fastclk;
+
+    M32632 cpu (
+
+        // ++++++++++ Basic Signals
+        .BCLK(clk),                 // input
+        .MCLK(~clk),                // input
+        .WRCFG(1'b1),               // input
+        .BRESET(rst_reg),           // input
+        .NMI_N(nmi_reg),            // input
+        .INT_N(irq_reg),            // input
+        .STATUS(status),            // output
+        .ILO(),                     // output
+        .STATSIGS(statsigs),        // output
+
+        // +++++++++ General Purpose Interface
+        .IO_WR(IO_WR),              // output
+        .IO_RD(IO_RD),              // output
+        .IO_A(IO_A),                // output
+        .IO_BE(IO_BE),              // output
+        .IO_DI(IO_DI),              // output
+        .IO_Q(IO_Q),                // input
+        .IO_READY(IO_READY),        // input
+
+        // +++++++++ DRAM Interface In
+        .ENDRAM(1'b0),              // input
+        .IC_MDONE(1'b0),            // input
+        .DC_MDONE(1'b0),            // input
+        .ENWR(1'b0),                // input
+        .WAMUX(1'b0),               // input
+        .WADDR(10'b0),              // input
+        .DRAM_Q(32'b0),             // input
+        .DWCTRL(3'b0),              // input
+        .IWCTRL(3'b0),              // input
+
+        // +++++++++ DRAM Interface Out
+        .IC_ACC(),
+        .IDRAM_ADR(),               // output
+        .DC_ACC(),                  // output
+        .DC_WR(),                   // output
+        .DRAM_ADR(),                // output
+        .DRAM_DI(),                 // output
+
+        // +++++++++ DMA Interface
+        .HOLD(1'b1),                // input
+        .HLDA(),                    // output
+        .FILLRAM(1'b0),             // input
+        .DMA_AA(24'b0),             // input
+
+        // ++++++++++ Coprocessor Interface
+        .COP_GO(),                  // output
+        .COP_OP(),                  // output
+        .COP_OUT(),                 // output
+        .COP_DONE(1'b0),            // input
+        .COP_IN(64'b0)              // input
+    );
+
+    assign IO_Q = ram_enable    ? ram_dout :
+                  rom_enable    ? rom_dout :
+                  tube_enable   ? {p_data_out, p_data_out, p_data_out, p_data_out} :
+                  config_enable ? 32'b0 :
+                  32'b0;
+
+    // Memory Map during booting
+    // 000000-FFFFFF ROM (32KB, repeating)
+
+    // Memory Map after booting
+    // 000000-1FFFFF RAM (2MB)
+    // F00000-F3FFFF ROM (32KB, repeating)
+    // F90000        Config Switches (A is bit 7, H is bit 0, 1=present)
+    //               A - RSVD;  B - RSVD;  C - RSVD;  D - RSVD;
+    //               E - RSVD;  F - RSVD;  G - MMU;   H - FPU;
+    // FFFFF0-FFFFFE Tube (even bytes)
+
+    assign rom_enable    = (IO_RD)         & ( bootmode | (IO_A[23:18] == 6'b111100));
+    assign ram_enable    = (IO_RD | IO_WR) & (!bootmode & (IO_A[23:21] == 3'b000));
+    assign tube_enable   = (IO_RD | IO_WR) & (!bootmode & (IO_A[23: 4] == 20'hFFFFF));
+    assign config_enable = (IO_RD)         & (!bootmode & (IO_A[23: 4] == 20'hF9000));
+
+    // Internal ROM 8Kx32 bits
+    tuberom_32016 rom(
+        .clk(nclk),
+        .addr(IO_A[14:2]),
+        .data(rom_dout)
+    );
+
+    // Tube
+    assign p_data_in = IO_A[1] ? IO_DI[23:16] : IO_DI[7:0];
+    assign p_cs_b = !tube_enable;
+    assign p_addr = IO_A[3:1];
+    assign p_wr_b = !IO_WR;
+
+    tube tube_inst(
+        .h_addr(h_addr),
+        .h_cs_b(h_cs_b),
+        .h_data(h_data),
+        .h_phi2(h_phi2),
+        .h_rdnw(h_rdnw),
+        .h_rst_b(h_rst_b),
+        .h_irq_b(),
+        .p_addr(p_addr),
+        .p_cs_b(p_cs_b),
+        .p_data_in(p_data_in),
+        .p_data_out(p_data_out),
+        .p_rdnw(p_wr_b),
+        .p_phi2(clk),
+        .p_rst_b(p_rst_b),
+        .p_nmi_b(p_nmi_b),
+        .p_irq_b(p_irq_b)
+    );
+
+    always @(posedge clk)
+        begin
+            rst_reg  <= p_rst_b;
+            nmi_reg  <= p_nmi_b;
+            irq_reg  <= p_irq_b;
+            if (!rst_reg)
+                bootmode <= 1'b1;
+            else if (IO_RD & (IO_A[23:18] == 6'b111100))
+                bootmode <= 1'b0;
+        end
+
+    assign IO_READY = ram_enable ? ram_rdy           :  // Ram controlled by state machine
+                                   (IO_WR | IO_RD);     // Everying else is immediate
+
+    // Note, this signal not actually connected to the tube connector on the PCB
+    assign h_irq_b  = 1;
+
+    //----------------------------------------------------------------------------
+    // State Machine machine performing read-modify-write cycles
+    //----------------------------------------------------------------------------
+
+    // External RAM signals
+    // in spite of the naming, these are all active low
+
+    parameter rd_latency          = 1;    // 0 .. 7, must be odd or m32632 messes up
+    parameter wr_latency          = 1;    // 0 .. 7
+    parameter rmw_rd_latency      = 1;    // 0 .. 7
+    parameter rmw_wr_latency      = 1;    // 0 .. 7
+
+    parameter s_idle              = 0;
+    parameter s_read              = 1;
+    parameter s_read_modify_write = 2;
+    parameter s_write             = 3;
+    parameter s_done              = 4;
+
+    reg [2:0]  state;
+    reg        ram_rdy;
+
+    // Latency countdown
+    reg [2:0]  lcount;
+
+    // Tri-State-Driver
+    reg [31:0] wdat;
+    reg        wdat_oe;
+    assign ram_data = wdat_oe ? wdat : 32'bz;
+
+    // Merged data for byte enables writes
+    wire [31:0] merged_dat = {(IO_BE[3] ? IO_DI[31:24] : ram_data[31:24]),
+                              (IO_BE[2] ? IO_DI[23:16] : ram_data[23:16]),
+                              (IO_BE[1] ? IO_DI[15: 8] : ram_data[15: 8]),
+                              (IO_BE[0] ? IO_DI[ 7: 0] : ram_data[ 7: 0])};
+
+    always @(posedge clk) begin
+        if (~rst_reg) begin
+            state   <= s_idle;
+            lcount  <= 0;
+            ram_rdy <= 0;
+        end else begin
+            case (state)
+            s_idle: begin
+                ram_rdy <= 0;
+                if (ram_enable & IO_RD) begin
+                    ram_cs     <= 0;
+                    ram_oe     <= 0;
+                    ram_wr     <= 1;
+                    ram_addr   <= IO_A[20:2];
+                    ram_ub_b   <= 0;
+                    ram_lb_b   <= 0;
+                    wdat_oe    <= 0;
+                    lcount     <= rd_latency;
+                    state      <= s_read;
+                end else if (ram_enable & IO_WR & (IO_BE == 4'b1111)) begin
+                    ram_cs     <= 0;
+                    ram_oe     <= 1;
+                    ram_wr     <= 0;
+                    ram_addr   <= IO_A[20:2];
+                    ram_ub_b   <= 0;
+                    ram_lb_b   <= 0;
+                    wdat       <= IO_DI;
+                    wdat_oe    <= 1;
+                    lcount     <= wr_latency;
+                    state      <= s_write;
+                end else if (ram_enable & IO_WR) begin
+                    ram_cs     <= 0;
+                    ram_oe     <= 0;
+                    ram_wr     <= 1;
+                    ram_addr   <= IO_A[20:2];
+                    ram_ub_b   <= 0;
+                    ram_lb_b   <= 0;
+                    wdat_oe    <= 0;
+                    lcount     <= rmw_rd_latency;
+                    state      <= s_read_modify_write;
+                end else begin
+                    ram_cs     <= 1;
+                    ram_oe     <= 1;
+                    ram_wr     <= 1;
+                    wdat_oe    <= 0;
+                end
+            end
+            s_read: begin
+                if (lcount != 0) begin
+                    lcount     <= lcount - 1;
+                end else begin
+                    ram_cs     <= 1;
+                    ram_oe     <= 1;
+                    ram_wr     <= 1;
+                    ram_dout   <= ram_data;
+                    ram_rdy    <= 1;
+                    state      <= s_done;
+                end
+            end
+            s_read_modify_write: begin
+                if (lcount != 0) begin
+                    lcount     <= lcount - 1;
+                end else begin
+                    ram_cs     <= 0;
+                    ram_oe     <= 1;
+                    ram_wr     <= 0;
+                    ram_addr   <= IO_A[20:2];
+                    ram_ub_b   <= 0;
+                    ram_lb_b   <= 0;
+                    wdat       <= merged_dat;
+                    wdat_oe    <= 1;
+                    lcount     <= rmw_wr_latency;
+                    state      <= s_write;
+                end
+            end
+            s_write: begin
+                if (lcount != 0) begin
+                    lcount     <= lcount - 1;
+                end else begin
+                    ram_cs     <= 1;
+                    ram_oe     <= 1;
+                    ram_wr     <= 1;
+                    ram_rdy    <= 1;       // XXX   We could acknoledge write  XXX
+                    state      <= s_done;  // XXX   requests 1 cycle ahead     XXX
+                end
+            end
+            s_done: begin
+                ram_rdy    <= 0;
+                state      <= s_idle;
+            end
+            endcase
+        end
+    end
+
+    //----------------------------------------------------------------------------
+    // Test outputs
+    //----------------------------------------------------------------------------
+
+    // default to hi-impedence, to avoid conflicts with
+    // a Raspberry Pi connected to the test connector
+    assign test = 8'bZ;
+
+    //----------------------------------------------------------------------------
+    // Test setups for debugging
+    //----------------------------------------------------------------------------
+
+    // // For Udo's CPU Test Program
+    // assign rom_enable    = (IO_RD)         & (IO_A[23:13] == 11'b00000000000);
+    // assign ram_enable    = (IO_RD | IO_WR) & (IO_A[23:13] != 11'b00000000000);
+    // assign tube_enable   = 0;
+    // assign config_enable = 0;
+
+    // wire [7:0]  trig;
+    // wire fetchc;
+    // wire fetchd;
+    // assign fetchc = IO_RD & (status == 4'b1000);
+    // assign fetchd = IO_RD & (status == 4'b1010);
+    // assign trig[5] = fetchc & (IO_A[23:0] == 24'h000000);
+    // assign trig[4] = fetchc & (IO_A[23:0] == 24'h000A60);
+    // assign trig[3] = fetchc & (IO_A[23:0] == 24'h001C70);
+    // assign trig[2] = fetchc & (IO_A[23:0] == 24'h001CA8);
+    // assign trig[1] = fetchc & (IO_A[23:0] == 24'h001CA9);
+    // assign trig[0] = fetchc & (IO_A[23:0] == 24'h001CB8);
+    // assign test = sw[3] ? {rst_reg, fetchc, IO_A[17:12]} :
+    //               sw[2] ? {rst_reg, fetchc, IO_A[11:6]} :
+    //               sw[1] ? {rst_reg, fetchc, IO_A[5:0]} :
+    //               sw[0] ? {rst_reg, fetchc, trig[5:0]} :
+    //                       {p_irq_b, p_nmi_b, bootmode, IO_RD, IO_WR, ram_enable, rom_enable, tube_enable};
+    // assign test = sw[3] ? {rst_reg, fetchc, fetchd, bootmode,  status} :
+    //               sw[2] ? {rst_reg, fetchc, fetchd, IO_A[14:10]} :
+    //               sw[1] ? {rst_reg, ram_enable, IO_RD, IO_WR, ram_cs, ram_oe, ram_wr, ram_rdy} :
+    //               sw[0] ? {rst_reg, tube_enable, p_cs_b, p_wr_b, p_data_in[3:0]} :
+    //                       {p_irq_b, p_nmi_b, bootmode, IO_RD, IO_WR, ram_enable, rom_enable, tube_enable};
+
+endmodule
+"
+"/*
+ *  16-bit 8-way multiplexor
+ *  Copyright (C) 2008-2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+module zet_mux8_16(sel, in0, in1, in2, in3, in4, in5, in6, in7, out);
+  input  [2:0]  sel;
+  input  [15:0] in0, in1, in2, in3, in4, in5, in6, in7;
+  output [15:0] out;
+
+  reg    [15:0] out;
+
+  always @(sel or in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7)
+    case(sel)
+     3'd0:  out = in0;
+     3'd1:  out = in1;
+     3'd2:  out = in2;
+     3'd3:  out = in3;
+     3'd4:  out = in4;
+     3'd5:  out = in5;
+     3'd6:  out = in6;
+     3'd7:  out = in7;
+    endcase
+endmodule
+"
+"//**************************************************************************
+//    ph_byte.v - single byte buffer for transfers in parasite to host direction
+//   
+//    COPYRIGHT 2010 Richard Evans, Ed Spittles
+// 
+//    This file is part of tube - an Acorn Tube ULA compatible system.
+//   
+//    tube is free software: you can redistribute it and/or modify
+//    it under the terms of the GNU Lesser General Public License as published by
+//    the Free Software Foundation, either version 3 of the License, or
+//    (at your option) any later version.
+//
+//    tube is distributed in the hope that it will be useful,
+//    but WITHOUT ANY WARRANTY; without even the implied warranty of
+//    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//    GNU Lesser General Public License for more details.
+//
+//    You should have received a copy of the GNU Lesser General Public License
+//    along with tube.  If not, see <http://www.gnu.org/licenses/>.
+//
+// **************************************************************************
+`timescale 1ns / 1ns
+
+module ph_byte (
+                input h_rst_b,
+                input h_rd,
+                input h_selectData,
+                input h_phi2,
+                input [7:0] p_data,                  
+                input p_selectData,
+                input p_phi2,
+                input p_rdnw,
+                output [7:0] h_data,                  
+                output h_data_available,
+                output p_full
+                );
+   
+   reg [7:0]           fifo_q_r ;
+   wire [7:0]          fifo_d_r ;
+      
+   assign h_data = fifo_q_r;   
+   assign fifo_d_r = ( p_selectData & !p_rdnw) ? p_data : fifo_q_r;   
+
+   ph_flag_m flag_0 (
+                       .rst_b(h_rst_b),
+                       .p2_rdnw(h_rd),
+                       .p2_select(h_selectData),
+                       .p2_clk(h_phi2),
+                       .p1_select(p_selectData),
+                       .p1_rdnw(p_rdnw),
+                       .p1_clk(p_phi2),                      
+                       .p2_data_available(h_data_available),
+                       .p1_full(p_full)
+                       );
+   
+   // Infer all state
+   always @ ( posedge p_phi2 or negedge h_rst_b )   
+     begin
+        if ( ! h_rst_b)
+          fifo_q_r <= 8'h41;             
+        else
+          fifo_q_r <= fifo_d_r ;             
+     end
+   
+endmodule // ph_byte
+
+   "
+"// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+// This file is part of the M32632 project\r
+// http://opencores.org/project,m32632\r
+//\r
+// Filename: STEUERUNG.v\r
+// Version:  1.0\r
+// Date:     30 May 2015\r
+//\r
+// Copyright (C) 2015 Udo Moeller\r
+// \r
+// This source file may be used and distributed without \r
+// restriction provided that this copyright statement is not \r
+// removed from the file and that any derivative work contains \r
+// the original copyright notice and the associated disclaimer.\r
+// \r
+// This source file is free software; you can redistribute it \r
+// and/or modify it under the terms of the GNU Lesser General \r
+// Public License as published by the Free Software Foundation;\r
+// either version 2.1 of the License, or (at your option) any \r
+// later version. \r
+// \r
+// This source is distributed in the hope that it will be \r
+// useful, but WITHOUT ANY WARRANTY; without even the implied \r
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR \r
+// PURPOSE. See the GNU Lesser General Public License for more \r
+// details. \r
+// \r
+// You should have received a copy of the GNU Lesser General \r
+// Public License along with this source; if not, download it \r
+// from http://www.opencores.org/lgpl.shtml \r
+// \r
+// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\tModules contained in this file:\r
+//\tSTEUERUNG\tThe control logic of M32632\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+module STEUERUNG( BCLK, BRESET, DC_ACC_DONE, ACB_ZERO, DONE, INT_N, NMI_N, DC_ABORT, IC_INIT, DC_INIT, SAVE_PC, CFG,\r
+\t\t\t\t  IACC_STAT, PROT_ERROR, IC_DIN, PC_NEW, PSR, STRING, TRAPS, IC_READ, DATA_HOLD, LD_DIN, LD_IMME,\r
+\t\t\t\t  WREN, WR_REG, GENSTAT, ILO, COP_OP, IC_USER, ACC_FELD, DISP, IC_TEX, IMME_Q, INFO_AU, LD_OUT,\r
+\t\t\t\t  DETOIP, MMU_UPDATE, OPER, PC_ARCHI, PC_ICACHE, RDAA, RDAB, START, WMASKE, WRADR, RWVAL, Y_INIT,\r
+\t\t\t\t  ENA_HK, STOP_CINV );\r
+\r
+input\t\t\tBCLK;\r
+input\t\t\tBRESET;\r
+input\t\t\tDC_ACC_DONE;\r
+input\t\t\tACB_ZERO;\r
+input\t\t\tDONE;\r
+input\t\t\tINT_N;\r
+input\t\t\tNMI_N;\r
+input\t\t\tDC_ABORT;\r
+input\t\t\tIC_INIT;\r
+input\t\t\tDC_INIT;\r
+input\t\t\tSAVE_PC;\r
+input\t\t\tY_INIT;\r
+input\t [8:0]\tCFG;\r
+input\t [3:0]\tIACC_STAT;\r
+input\t\t\tPROT_ERROR;\r
+input\t[31:0]\tIC_DIN;\r
+input\t[31:0]\tPC_NEW;\r
+input\t[11:0]\tPSR;\r
+input\t [4:0]\tSTRING;\r
+input\t [5:0]\tTRAPS;\r
+input\t\t\tSTOP_CINV;\r
+\r
+output\t\t\tIC_READ;\r
+output\t\t\tDATA_HOLD;\r
+output\t\t\tLD_DIN;\r
+output\t\t\tLD_IMME;\r
+output\t\t\tWREN;\r
+output\t\t\tWR_REG;\r
+output\t [2:0]\tGENSTAT;\r
+output\t\t\tIC_USER;\r
+output\t[14:0]\tACC_FELD;\r
+output\t[31:0]\tDISP;\r
+output\t [2:0]\tIC_TEX;\r
+output\t[31:0]\tIMME_Q;\r
+output\t [6:0]\tINFO_AU;\r
+output\t [1:0]\tLD_OUT;\r
+output\t[12:0]\tDETOIP;\r
+output\t [1:0]\tMMU_UPDATE;\r
+output\t[10:0]\tOPER;\r
+output\t[31:0]\tPC_ARCHI;\r
+output\t[31:0]\tPC_ICACHE;\r
+output\t [7:0]\tRDAA;\r
+output\t [7:0]\tRDAB;\r
+output\t [1:0]\tSTART;\r
+output\t [1:0]\tWMASKE;\r
+output\t [5:0]\tWRADR;\r
+output\t [2:0]\tRWVAL;\r
+output\t\t\tENA_HK;\r
+output\t\t\tILO;\r
+output\t[23:0]\tCOP_OP;\r
+\r
+wire\t[55:0]\tOPREG;\r
+wire\t\t\tIC_ABORT;\r
+wire\t\t\tINIT_DONE;\r
+wire\t\t\tUNDEF;\r
+wire\t\t\tILLEGAL;\r
+wire\t [2:0]\tANZ_VAL;\r
+wire\t[31:0]\tPC_SAVE;\r
+wire\t\t\tNEW;\r
+wire\t\t\tRESTART;\r
+wire\t\t\tSTOP_IC;\r
+wire\t [1:0]\tALSB;\r
+wire\t [2:0]\tUSED;\r
+wire\t\t\tNEXT_ADR;\r
+wire\t\t\tNEW_PC;\r
+wire\t\t\tNEXT_PCA;\r
+wire\t\t\tLOAD_PC;\r
+wire\t[31:0]\tDISP_BR;\r
+\r
+DECODER\tBEFEHLS_DEC(\r
+\t.BCLK(BCLK),\r
+\t.BRESET(BRESET),\r
+\t.ACC_DONE(DC_ACC_DONE),\r
+\t.ACB_ZERO(ACB_ZERO),\r
+\t.DONE(DONE),\r
+\t.NMI_N(NMI_N),\r
+\t.INT_N(INT_N),\r
+\t.DC_ABORT(DC_ABORT),\r
+\t.IC_ABORT(IC_ABORT),\r
+\t.INIT_DONE(INIT_DONE),\r
+\t.UNDEF(UNDEF),\r
+\t.ILL(ILLEGAL),\r
+\t.IC_READ(IC_READ),\r
+\t.ANZ_VAL(ANZ_VAL),\r
+\t.CFG(CFG),\r
+\t.OPREG(OPREG),\r
+\t.PC_SAVE(PC_SAVE),\r
+\t.PSR(PSR),\r
+\t.STRING(STRING),\r
+\t.TRAPS(TRAPS),\r
+\t.NEW(NEW),\r
+\t.WREN(WREN),\r
+\t.LD_DIN(LD_DIN),\r
+\t.LD_IMME(LD_IMME),\r
+\t.NEXT_PCA(NEXT_PCA),\r
+\t.WR_REG(WR_REG),\r
+\t.LOAD_PC(LOAD_PC),\r
+\t.GENSTAT(GENSTAT),\r
+\t.RESTART(RESTART),\r
+\t.STOP_IC(STOP_IC),\r
+\t.ACC_FELD(ACC_FELD),\r
+\t.DISP(DISP),\r
+\t.DISP_BR(DISP_BR),\r
+\t.IMME_Q(IMME_Q),\r
+\t.INFO_AU(INFO_AU),\r
+\t.LD_OUT(LD_OUT),\r
+\t.DETOIP(DETOIP),\r
+\t.MMU_UPDATE(MMU_UPDATE),\r
+\t.OPER(OPER),\r
+\t.RDAA(RDAA),\r
+\t.RDAB(RDAB),\r
+\t.START(START),\r
+\t.USED(USED),\r
+\t.WMASKE(WMASKE),\r
+\t.WRADR(WRADR),\r
+\t.RWVAL(RWVAL),\r
+\t.ENA_HK(ENA_HK),\r
+\t.ILO(ILO),\r
+\t.COP_OP(COP_OP),\r
+\t.STOP_CINV(STOP_CINV) );\r
+\r
+ILL_UNDEF\tCHECKER(\r
+\t.USER(PSR[8]),\r
+\t.ANZ_VAL(ANZ_VAL),\r
+\t.CFG(CFG[3:1]),\r
+\t.OPREG(OPREG[23:0]),\r
+\t.ILL(ILLEGAL),\r
+\t.UNDEF(UNDEF));\r
+\r
+OPDEC_REG\tOPC_REG(\r
+\t.BCLK(BCLK),\r
+\t.BRESET(BRESET),\r
+\t.NEW(NEW),\r
+\t.DC_INIT(DC_INIT),\r
+\t.IC_INIT(IC_INIT),\r
+\t.Y_INIT(Y_INIT),\r
+\t.RESTART(RESTART),\r
+\t.STOP_IC(STOP_IC),\r
+\t.ACC_STAT(IACC_STAT),\r
+\t.PROT_ERROR(PROT_ERROR),\r
+\t.ALSB(ALSB),\r
+\t.IC_DIN(IC_DIN),\r
+\t.USED(USED),\r
+\t.IC_READ(IC_READ),\r
+\t.NEXT_ADR(NEXT_ADR),\r
+\t.DATA_HOLD(DATA_HOLD),\r
+\t.NEW_PC(NEW_PC),\r
+\t.ABORT(IC_ABORT),\r
+\t.INIT_DONE(INIT_DONE),\r
+\t.ANZ_VAL(ANZ_VAL),\r
+\t.IC_TEX(IC_TEX),\r
+\t.OPREG(OPREG));\r
+\r
+PROG_COUNTER\tPCS(\r
+\t.BCLK(BCLK),\r
+\t.BRESET(BRESET),\r
+\t.NEXT_ADR(NEXT_ADR),\r
+\t.NEW_PC(NEW_PC),\r
+\t.NEXT_PCA(NEXT_PCA),\r
+\t.NEW(NEW),\r
+\t.LOAD_PC(LOAD_PC),\r
+\t.USER(PSR[8]),\r
+\t.SAVE_PC(SAVE_PC),\r
+\t.FPU_TRAP(TRAPS[0]),\r
+\t.ADIVAR(INFO_AU[3]),\r
+\t.DISP(DISP_BR),\r
+\t.PC_NEW(PC_NEW),\r
+\t.USED(USED),\r
+\t.IC_USER(IC_USER),\r
+\t.ALSB(ALSB),\r
+\t.PC_ARCHI(PC_ARCHI),\r
+\t.PC_ICACHE(PC_ICACHE),\r
+\t.PC_SAVE(PC_SAVE));\r
+\r
+endmodule\r
+"
+"/*
+ *  Zet processor core
+ *  Copyright (C) 2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+`include ""defines.v""
+
+module zet_core (
+    input clk,
+    input rst,
+
+    // interrupts
+    input  intr,
+    output inta,
+    input  nmi,
+    output nmia,
+
+    // interface to wishbone
+    output [19:0] cpu_adr_o,
+    input  [15:0] iid_dat_i,
+    input  [15:0] cpu_dat_i,
+    output [15:0] cpu_dat_o,
+    output        cpu_byte_o,
+    input         cpu_block,
+    output        cpu_mem_op,
+    output        cpu_m_io,
+    output        cpu_we_o,
+
+    output [19:0] pc  // for debugging purposes
+  );
+
+  // Net declarations
+  wire [`IR_SIZE-1:0] ir;
+  wire [15:0] off;
+  wire [15:0] imm;
+  wire        wr_ip0;
+
+  wire [15:0] cs;
+  wire [15:0] ip;
+  wire        of;
+  wire        zf;
+  wire        ifl;
+  wire        iflm;
+  wire        tfl;
+  wire        tflm;
+  wire        iflss;
+  wire        wr_ss;
+  wire        cx_zero;
+  wire        div_exc;
+
+  wire [19:0] addr_exec;
+  wire        byte_fetch;
+  wire        byte_exec;
+
+  // wire decode - microcode
+  wire [`MICRO_ADDR_WIDTH-1:0] seq_addr;
+  wire [3:0] src;
+  wire [3:0] dst;
+  wire [3:0] base;
+  wire [3:0] index;
+  wire [1:0] seg;
+  wire       end_seq;
+  wire [2:0] fdec;
+  wire       div;
+
+  // wires fetch - decode
+  wire [7:0] opcode;
+  wire [7:0] modrm;
+  wire       rep;
+  wire       exec_st;
+  wire       ld_base;
+  wire [2:0] sop_l;
+
+  wire need_modrm;
+  wire need_off;
+  wire need_imm;
+  wire off_size;
+  wire imm_size;
+  wire ext_int;
+
+  // wires fetch - microcode
+  wire [15:0] off_l;
+  wire [15:0] imm_l;
+  wire [15:0] imm_d;
+  wire [`IR_SIZE-1:0] rom_ir;
+  wire [5:0] ftype;
+
+  // wires fetch - exec
+  wire [15:0] imm_f;
+
+  // wires and regs for hlt
+  wire block_or_hlt;
+  wire hlt_op;
+  wire hlt_in;
+  wire hlt_out;
+
+  reg hlt_op_old;
+  reg hlt;
+
+  // regs for nmi
+  reg nmir;
+  reg nmi_old;
+  reg nmia_old;
+  
+  wire use_eintp;
+
+  // Module instantiations
+  zet_fetch fetch (
+    .clk  (clk),
+    .rst  (rst),
+
+    // to decode
+    .opcode  (opcode),
+    .modrm   (modrm),
+    .rep     (rep),
+    .exec_st (exec_st),
+    .ld_base (ld_base),
+    .sop_l   (sop_l),
+
+    // from decode
+    .need_modrm (need_modrm),
+    .need_off   (need_off),
+    .need_imm   (need_imm),
+    .off_size   (off_size),
+    .imm_size   (imm_size),
+    .ext_int    (ext_int),
+    .end_seq    (end_seq),
+
+    // to microcode
+    .off_l (off_l),
+    .imm_l (imm_l),
+
+    // from microcode
+    .ftype (ftype),
+
+    // to exec
+    .imm_f  (imm_f),
+    .wr_ip0 (wr_ip0),
+
+    // from exec
+    .cs      (cs),
+    .ip      (ip),
+    .of      (of),
+    .zf      (zf),
+    .iflm    (iflm),
+    .tflm    (tflm),
+    .iflss   (iflss),
+    .cx_zero (cx_zero),
+    .div_exc (div_exc),
+
+    // to wb
+    .data          (cpu_dat_i),
+    .pc            (pc),
+    .bytefetch     (byte_fetch),
+    .block         (block_or_hlt),
+    .intr          (intr),
+    .nmir          (nmir),
+    
+    .use_eintp     (use_eintp)
+  );
+
+  zet_decode decode (
+    .clk (clk),
+    .rst (rst),
+
+    .opcode  (opcode),
+    .modrm   (modrm),
+    .rep     (rep),
+    .block   (block_or_hlt),
+    .exec_st (exec_st),
+    .div_exc (div_exc),
+    .ld_base (ld_base),
+    .div     (div),
+    .tfl     (tfl),
+    .tflm    (tflm),
+
+    .need_modrm (need_modrm),
+    .need_off   (need_off),
+    .need_imm   (need_imm),
+    .off_size   (off_size),
+    .imm_size   (imm_size),
+
+    .sop_l   (sop_l),
+    .intr    (intr),
+    .ifl     (ifl),
+    .iflm    (iflm),
+    .inta    (inta),
+    .ext_int (ext_int),
+    .nmir    (nmir),
+    .nmia    (nmia),
+    .wr_ss   (wr_ss),
+    .iflss   (iflss),
+
+    .seq_addr (seq_addr),
+    .src      (src),
+    .dst      (dst),
+    .base     (base),
+    .index    (index),
+    .seg      (seg),
+    .f        (fdec),
+
+    .end_seq  (end_seq),
+    
+    .use_eintp     (use_eintp)
+
+  );
+
+  zet_micro_data micro_data (
+    // from decode
+    .n_micro (seq_addr),
+    .off_i   (off_l),
+    .imm_i   (imm_l),
+    .src     (src),
+    .dst     (dst),
+    .base    (base),
+    .index   (index),
+    .seg     (seg),
+    .fdec    (fdec),
+    .div     (div),
+    .end_seq (end_seq),
+
+    // to exec
+    .ir    (rom_ir),
+    .off_o (off),
+    .imm_o (imm_d)
+  );
+
+  zet_exec exec (
+    .clk     (clk),
+    .rst     (rst),
+
+    // from fetch
+    .ir      (ir),
+    .off     (off),
+    .imm     (imm),
+    .wrip0   (wr_ip0),
+
+    // to fetch
+    .cs      (cs),
+    .ip      (ip),
+    .of      (of),
+    .zf      (zf),
+    .ifl     (ifl),
+    .tfl     (tfl),
+    .cx_zero (cx_zero),
+    .div_exc (div_exc),
+
+    .wr_ss   (wr_ss),
+
+    // from wb
+    .memout  (iid_dat_i),
+    .wr_data (cpu_dat_o),
+    .addr    (addr_exec),
+    .we      (cpu_we_o),
+    .m_io    (cpu_m_io),
+    .byteop  (byte_exec),
+    .block   (block_or_hlt)
+  );
+
+  // Assignments
+  assign cpu_adr_o  = exec_st ? addr_exec : pc;
+  assign cpu_byte_o = exec_st ? byte_exec : byte_fetch;
+  assign cpu_mem_op = ir[`MEM_OP];
+
+  assign ir    = exec_st ? rom_ir : `ADD_IP;
+  assign imm   = exec_st ? imm_d  : imm_f;
+  assign ftype = rom_ir[28:23];
+
+  assign hlt_op = ((opcode == `OP_HLT) && exec_st); 
+  assign hlt_in = (hlt_op && !hlt_op_old && !hlt_out);
+  assign hlt_out = (intr & ifl) | nmir;
+  assign block_or_hlt = cpu_block | hlt | hlt_in;
+
+  // Behaviour
+  always @(posedge clk)
+    if (rst)
+      hlt_op_old <= 1\'b0;
+    else
+      if (hlt_op)
+        hlt_op_old <= 1\'b1;
+      else
+        hlt_op_old <= 1\'b0;
+
+  always @(posedge clk)
+    if (rst)
+      hlt <= 1\'b0;
+    else
+      if (hlt_in)
+        hlt <= 1\'b1;
+      else if (hlt_out)
+        hlt <= 1\'b0;
+
+  always @(posedge clk)
+    if (rst)
+    begin
+      nmir <= 1\'b0;
+      nmi_old <= 1\'b0;
+      nmia_old <= 1\'b0;
+    end
+    else
+    begin
+      nmi_old <= nmi;
+      nmia_old <= nmia; 
+      if (nmi & ~nmi_old)
+        nmir <= 1\'b1;
+      else if (nmia_old)
+        nmir <= 1\'b0;
+    end
+
+endmodule
+"
+"//////////////////////////////////////////////////////////////////
+//                                                              //
+//  RAM-based register Bank for Amber Core                      //
+//                                                              //
+//  This file is part of the Amber project                      //
+//  http://www.opencores.org/project,amber                      //
+//                                                              //
+//  Description                                                 //
+//  Contains 37 32-bit registers, 16 of which are visible       //
+//  ina any one operating mode.                                 //
+//  The block is designed using syncronous RAM primitive,       //
+//  and fits well into an FPGA design                           //
+//                                                              //
+//  Author(s):                                                  //
+//      - Dmitry Tarnyagin, dmitry.tarnyagin@lockless.no        //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+//                                                              //
+// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
+//                                                              //
+// This source file may be used and distributed without         //
+// restriction provided that this copyright statement is not    //
+// removed from the file and that any derivative work contains  //
+// the original copyright notice and the associated disclaimer. //
+//                                                              //
+// This source file is free software; you can redistribute it   //
+// and/or modify it under the terms of the GNU Lesser General   //
+// Public License as published by the Free Software Foundation; //
+// either version 2.1 of the License, or (at your option) any   //
+// later version.                                               //
+//                                                              //
+// This source is distributed in the hope that it will be       //
+// useful, but WITHOUT ANY WARRANTY; without even the implied   //
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
+// PURPOSE.  See the GNU Lesser General Public License for more //
+// details.                                                     //
+//                                                              //
+// You should have received a copy of the GNU Lesser General    //
+// Public License along with this source; if not, download it   //
+// from http://www.opencores.org/lgpl.shtml                     //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+
+module a23_ram_register_bank (
+
+input                       i_clk,
+input                       i_fetch_stall,
+
+input       [1:0]           i_mode_exec,            // registered cpu mode from execution stage
+input       [1:0]           i_mode_exec_nxt,        // 1 periods delayed from i_mode_idec
+                                                    // Used for register reads
+input       [1:0]           i_mode_rds_exec,        // Use raw version in this implementation,
+                                                    // includes i_user_mode_regs_store
+input                       i_user_mode_regs_load,
+input       [3:0]           i_rm_sel,
+input       [3:0]           i_rds_sel,
+input       [3:0]           i_rn_sel,
+
+input                       i_pc_wen,
+input       [3:0]           i_reg_bank_wsel,
+
+input       [23:0]          i_pc,                   // program counter [25:2]
+input       [31:0]          i_reg,
+
+input       [3:0]           i_status_bits_flags,
+input                       i_status_bits_irq_mask,
+input                       i_status_bits_firq_mask,
+
+output      [31:0]          o_rm,
+output      [31:0]          o_rs,
+output      [31:0]          o_rd,
+output      [31:0]          o_rn,
+output      [31:0]          o_pc
+
+);
+
+`include ""a23_localparams.vh""
+`include ""a23_functions.vh""
+
+wire  [1:0]  mode_idec;
+wire  [1:0]  mode_exec;
+wire  [1:0]  mode_rds;
+
+wire  [4:0]  rm_addr;
+wire  [4:0]  rds_addr;
+wire  [4:0]  rn_addr;
+wire  [4:0]  wr_addr;
+
+// Register pool in embedded ram memory
+reg   [31:0] reg_ram_n[31:0];
+reg   [31:0] reg_ram_m[31:0];
+reg   [31:0] reg_ram_ds[31:0];
+
+wire  [31:0] rds_out;
+wire  [31:0] rm_out;
+wire  [31:0] rn_out;
+
+// Synchronous ram input buffering
+reg   [4:0]  rm_addr_reg;
+reg   [4:0]  rds_addr_reg;
+reg   [4:0]  rn_addr_reg;
+
+// User Mode Registers
+reg   [23:0] r15 = 24\'hc0_ffee;
+
+wire  [31:0] r15_out_rm;
+wire  [31:0] r15_out_rm_nxt;
+wire  [31:0] r15_out_rn;
+
+// r15 selectors
+reg          rn_15 = 1\'b0;   
+reg          rm_15 = 1\'b0;
+reg          rds_15 = 1\'b0;
+
+// Write Enables from execute stage
+assign mode_idec = i_mode_exec_nxt & ~{2{i_user_mode_regs_load}};
+assign wr_addr = reg_addr(mode_idec, i_reg_bank_wsel);
+
+// Read Enables from stage 1 (fetch)
+assign mode_exec = i_mode_exec_nxt;
+assign rm_addr = reg_addr(mode_exec, i_rm_sel);
+assign rn_addr = reg_addr(mode_exec, i_rn_sel);
+
+// Rds
+assign mode_rds = i_mode_rds_exec;
+assign rds_addr = reg_addr(mode_rds, i_rds_sel);
+
+    
+// ========================================================
+// r15 Register Read based on Mode
+// ========================================================
+assign r15_out_rm     = { i_status_bits_flags, 
+                          i_status_bits_irq_mask, 
+                          i_status_bits_firq_mask, 
+                          r15, 
+                          i_mode_exec};
+
+assign r15_out_rm_nxt = { i_status_bits_flags, 
+                          i_status_bits_irq_mask, 
+                          i_status_bits_firq_mask, 
+                          i_pc, 
+                          i_mode_exec};
+                      
+assign r15_out_rn     = {6\'d0, r15, 2\'d0};
+
+
+// ========================================================
+// Program Counter out
+// ========================================================
+assign o_pc = r15_out_rn;
+
+// ========================================================
+// Rm Selector
+// ========================================================
+assign rm_out = reg_ram_m[rm_addr_reg];
+
+assign o_rm =\trm_15 ?\t\t\t\tr15_out_rm :
+\t\t\t\t\t\trm_out;
+
+// ========================================================
+// Rds Selector
+// ========================================================
+assign rds_out = reg_ram_ds[rds_addr_reg];
+
+assign o_rs =\trds_15  ?\t\t\tr15_out_rn :
+\t\t\t\t\t\trds_out;
+
+// ========================================================
+// Rd Selector
+// ========================================================
+assign o_rd =\trds_15  ? \t\t\tr15_out_rm_nxt :
+\t\t\t\t\t\trds_out;
+
+// ========================================================
+// Rn Selector
+// ========================================================
+assign rn_out = reg_ram_n[rn_addr_reg];
+
+assign o_rn =\trn_15  ?\t\t\tr15_out_rn :
+\t\t\t\t\t\trn_out;
+// ========================================================
+// Register Update
+// ========================================================
+always @ ( posedge i_clk )
+    if (!i_fetch_stall)
+        begin
+
+        // Register write.
+        // Actually the code is synthesed as a syncronous ram
+        // with an additional  pass-through multiplexor for
+        // read-when-write handling.
+        reg_ram_n[wr_addr]      <= i_reg;
+        reg_ram_m[wr_addr]      <= i_reg;
+        reg_ram_ds[wr_addr]     <= i_reg;
+        r15                     <= i_pc_wen ? i_pc : r15;
+
+        // The latching is actually implemented in a hard block.
+        rn_addr_reg             <= rn_addr;
+        rm_addr_reg             <= rm_addr;
+        rds_addr_reg            <= rds_addr;
+
+        rn_15                   <= i_rn_sel == 4\'hF;
+        rm_15                   <= i_rm_sel == 4\'hF;
+        rds_15                  <= i_rds_sel == 4\'hF;
+        end
+    
+// ========================================================
+// Register mapping:
+// ========================================================
+// 0xxxx : r0 - r14
+// 10xxx : r8_firq - r14_firq
+// 110xx : r13_irq - r14_irq
+// 111xx : r13_svc - r14_svc
+
+function [4:0] reg_addr;
+input [1:0] mode;
+input [3:0] sel;
+begin
+\tcasez ({mode, sel}) // synthesis full_case parallel_case
+\t\t6\'b??0???:\treg_addr = {1\'b0, sel};\t\t// r0 - r7
+\t\t6\'b1?1100:\treg_addr = {1\'b0, sel};\t\t// irq and svc r12
+\t\t6\'b001???:\treg_addr = {1\'b0, sel};\t\t// user r8 - r14
+\t\t6\'b011???:\treg_addr = {2\'b10, sel[2:0]};\t// fiq r8-r14
+\t\t6\'b1?10??:\treg_addr = {1\'b0, sel};\t\t// irq and svc r8-r11
+\t\t6\'b101101:\treg_addr = {3\'b110, sel[1:0]};\t// irq r13
+\t\t6\'b101110:\treg_addr = {3\'b110, sel[1:0]};\t// irq r14
+\t\t6\'b101111:\treg_addr = {3\'b110, sel[1:0]};\t// irq r15, just to make the case full
+\t\t6\'b111101:\treg_addr = {3\'b111, sel[1:0]};\t// svc r13
+\t\t6\'b111110:\treg_addr = {3\'b111, sel[1:0]};\t// svc r14
+\t\t6\'b111111:\treg_addr = {3\'b111, sel[1:0]};\t// svc r15, just to make the case full
+\tendcase
+end
+endfunction
+
+// synthesis translate_off
+// To be used as probes...
+wire [31:0] r0;
+wire [31:0] r1;
+wire [31:0] r2;
+wire [31:0] r3;
+wire [31:0] r4;
+wire [31:0] r5;
+wire [31:0] r6;
+wire [31:0] r7;
+wire [31:0] r8;
+wire [31:0] r9;
+wire [31:0] r10;
+wire [31:0] r11;
+wire [31:0] r12;
+wire [31:0] r13;
+wire [31:0] r14;
+wire [31:0] r13_svc;
+wire [31:0] r14_svc;
+wire [31:0] r13_irq;
+wire [31:0] r14_irq;
+wire [31:0] r8_firq;
+wire [31:0] r9_firq;
+wire [31:0] r10_firq;
+wire [31:0] r11_firq;
+wire [31:0] r12_firq;
+wire [31:0] r13_firq;
+wire [31:0] r14_firq;
+wire [31:0] r0_out;
+wire [31:0] r1_out;
+wire [31:0] r2_out;
+wire [31:0] r3_out;
+wire [31:0] r4_out;
+wire [31:0] r5_out;
+wire [31:0] r6_out;
+wire [31:0] r7_out;
+wire [31:0] r8_out;
+wire [31:0] r9_out;
+wire [31:0] r10_out;
+wire [31:0] r11_out;
+wire [31:0] r12_out;
+wire [31:0] r13_out;
+wire [31:0] r14_out;
+
+assign r0  = reg_ram_m[ 0];
+assign r1  = reg_ram_m[ 1];
+assign r2  = reg_ram_m[ 2];
+assign r3  = reg_ram_m[ 3];
+assign r4  = reg_ram_m[ 4];
+assign r5  = reg_ram_m[ 5];
+assign r6  = reg_ram_m[ 6];
+assign r7  = reg_ram_m[ 7];
+assign r8  = reg_ram_m[ 8];
+assign r9  = reg_ram_m[ 9];
+assign r10 = reg_ram_m[10];
+assign r11 = reg_ram_m[11];
+assign r12 = reg_ram_m[12];
+assign r13 = reg_ram_m[13];
+assign r14 = reg_ram_m[14];
+assign r13_svc  = reg_ram_m[29];
+assign r14_svc  = reg_ram_m[30];
+assign r13_irq  = reg_ram_m[25];
+assign r14_irq  = reg_ram_m[26];
+assign r8_firq  = reg_ram_m[16];
+assign r9_firq  = reg_ram_m[17];
+assign r10_firq = reg_ram_m[18];
+assign r11_firq = reg_ram_m[19];
+assign r12_firq = reg_ram_m[20];
+assign r13_firq = reg_ram_m[21];
+assign r14_firq = reg_ram_m[22];
+assign r0_out  = reg_ram_m[reg_addr(mode_exec,  0)];
+assign r1_out  = reg_ram_m[reg_addr(mode_exec,  1)];
+assign r2_out  = reg_ram_m[reg_addr(mode_exec,  2)];
+assign r3_out  = reg_ram_m[reg_addr(mode_exec,  3)];
+assign r4_out  = reg_ram_m[reg_addr(mode_exec,  4)];
+assign r5_out  = reg_ram_m[reg_addr(mode_exec,  5)];
+assign r6_out  = reg_ram_m[reg_addr(mode_exec,  6)];
+assign r7_out  = reg_ram_m[reg_addr(mode_exec,  7)];
+assign r8_out  = reg_ram_m[reg_addr(mode_exec,  8)];
+assign r9_out  = reg_ram_m[reg_addr(mode_exec,  9)];
+assign r10_out = reg_ram_m[reg_addr(mode_exec, 10)];
+assign r11_out = reg_ram_m[reg_addr(mode_exec, 11)];
+assign r12_out = reg_ram_m[reg_addr(mode_exec, 12)];
+assign r13_out = reg_ram_m[reg_addr(mode_exec, 13)];
+assign r14_out = reg_ram_m[reg_addr(mode_exec, 14)];
+// synthesis translate_on
+
+endmodule
+
+
+"
+"//////////////////////////////////////////////////////////////////
+//                                                              //
+//  Barrel Shifter for Amber 2 Core                             //
+//                                                              //
+//  The design is optimized for Altera family of FPGAs,         //
+//  and it can be used directly or adapted other N-to-1 LUT     //
+//  FPGA platforms.                                             //
+//                                                              //
+//  This file is part of the Amber project                      //
+//  http://www.opencores.org/project,amber                      //
+//                                                              //
+//  Description                                                 //
+//  Provides 32-bit shifts LSL, LSR, ASR and ROR                //
+//                                                              //
+//  Author(s):                                                  //
+//      - Dmitry Tarnyagin, dmitry.tarnyagin@lockless.no        //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+//                                                              //
+// Copyright (C) 2010-2013 Authors and OPENCORES.ORG            //
+//                                                              //
+// This source file may be used and distributed without         //
+// restriction provided that this copyright statement is not    //
+// removed from the file and that any derivative work contains  //
+// the original copyright notice and the associated disclaimer. //
+//                                                              //
+// This source file is free software; you can redistribute it   //
+// and/or modify it under the terms of the GNU Lesser General   //
+// Public License as published by the Free Software Foundation; //
+// either version 2.1 of the License, or (at your option) any   //
+// later version.                                               //
+//                                                              //
+// This source is distributed in the hope that it will be       //
+// useful, but WITHOUT ANY WARRANTY; without even the implied   //
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
+// PURPOSE.  See the GNU Lesser General Public License for more //
+// details.                                                     //
+//                                                              //
+// You should have received a copy of the GNU Lesser General    //
+// Public License along with this source; if not, download it   //
+// from http://www.opencores.org/lgpl.shtml                     //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+
+
+module a23_barrel_shift_fpga (
+
+input       [31:0]          i_in,
+input                       i_carry_in,
+input       [7:0]           i_shift_amount,     // uses 8 LSBs of Rs, or a 5 bit immediate constant
+input                       i_shift_imm_zero,   // high when immediate shift value of zero selected
+input       [1:0]           i_function,
+
+output      [31:0]          o_out,
+output                      o_carry_out
+
+);
+
+`include ""a23_localparams.vh""
+
+wire [31:0] rot_prod;                           // Input rotated by the shift amount
+
+wire [1:0]  lsl_out;                            // LSL: {carry, bit_31}
+wire [1:0]  lsr_out;                            // LSR: {carry, bit_31}
+wire [1:0]  asr_out;                            // ASR: {carry, bit_31}
+wire [1:0]  ror_out;                            // ROR: {carry, bit_31}
+
+reg [32:0]  lsl_mask;                           // Left-hand mask
+reg [32:0]  lsr_mask;                           // Right-hand mask
+reg [15:0]  low_mask;                           // Mask calculation helper
+
+reg [4:0]   shift_amount;                       // Shift amount for the low-level shifter
+
+reg [2:0]   lsl_selector;                       // Left shift {shift_32, shift_over, shift_amount[4]}
+reg [2:0]   lsr_selector;                       // Right shift {shift_32, shift_over, shift_amount[4]}
+reg [3:0]   low_selector;                       // {shift_amount[3:0]}
+
+reg         shift_nzero;                        // Amount is not zero
+reg         shift_over;                         // Amount is 32 or higher
+reg         shift_32;                           // Amount is exactly 32
+reg         asr_sign;                           // Sign for ASR shift
+reg         direction;                          // Shift direction
+
+wire [31:0] p_r;                                // 1 bit rotated rot_prod
+wire [31:0] p_l;                                // Alias for the rot_prod 
+
+
+// Implementation details:
+// Design is based on masking of rotated input by a left- and right- hand masks.
+// Rotated product calculation requires 5 levels of combinational logic, and masks
+// must be ready before the product is ready. In fact masks require just 3 to 4 levels
+// of logic cells using 4-to-1/2x3-to-1 Altera.
+
+always @*
+begin
+\tshift_32 = i_shift_amount == 32;
+
+\tshift_over = |i_shift_amount[7:5];
+
+\tshift_nzero = |i_shift_amount[7:0];
+
+\tshift_amount = i_shift_amount[4:0];
+
+\tif (i_shift_imm_zero) begin
+\t\tif (i_function == LSR || i_function == ASR) begin
+\t\t\t// The form of the shift field which might be
+\t\t\t// expected to correspond to LSR #0 is used
+\t\t\t// to encode LSR #32, which has a zero result
+\t\t\t// with bit 31 of Rm as the carry output. 
+\t\t\tshift_nzero = 1\'b1;
+\t\t\tshift_over = 1\'b1;
+\t\t\t// Redundant and can be optimized out
+\t\t\t// shift_32 = 1\'b1;
+\t\tend else if (i_function == ROR) begin
+\t\t\t// RXR, (ROR w/ imm 0)
+\t\t\tshift_amount[0] = 1\'b1;
+\t\t\tshift_nzero = 1\'b1;
+\t\tend
+\tend
+
+\t// LSB sub-selector calculation. Usually it is taken
+\t// directly from the shift_amount, but ROR requires
+\t// no masking at all.
+\tcase (i_function)
+\t\tLSL: low_selector = shift_amount[3:0];
+\t\tLSR: low_selector = shift_amount[3:0];
+\t\tASR: low_selector = shift_amount[3:0];
+\t\tROR: low_selector = 4\'b0000;
+\tendcase
+
+\t// Left-hand MSB sub-selector calculation. Opaque for every function but LSL.
+\tcase (i_function)
+\t\tLSL: lsl_selector = {shift_32, shift_over, shift_amount[4]};
+\t\tLSR: lsl_selector = 3\'b0_1_0; // Opaque mask selector
+\t\tASR: lsl_selector = 3\'b0_1_0; // Opaque mask selector
+\t\tROR: lsl_selector = 3\'b0_1_0; // Opaque mask selector
+\tendcase
+
+\t// Right-hand MSB sub-selector calculation. Opaque for LSL, transparent for ROR.
+\tcase (i_function)
+\t\tLSL: lsr_selector = 3\'b0_1_0; // Opaque mask selector
+\t\tLSR: lsr_selector = {shift_32, shift_over, shift_amount[4]};
+\t\tASR: lsr_selector = {shift_32, shift_over, shift_amount[4]};
+\t\tROR: lsr_selector = 3\'b0_0_0; // Transparent mask selector
+\tendcase
+
+\t// Direction
+\tcase (i_function)
+\t\tLSL: direction = 1\'b0; // Left shift
+\t\tLSR: direction = 1\'b1; // Right shift
+\t\tASR: direction = 1\'b1; // Right shift
+\t\tROR: direction = 1\'b1; // Right shift
+\tendcase
+
+\t// Sign for ASR shift
+\tasr_sign = 1\'b0;
+\tif (i_function == ASR && i_in[31])
+\t\tasr_sign = 1\'b1;
+end
+
+// Generic rotate. Theoretical cost: 32x5 4-to-1 LUTs.
+// Practically a bit higher due to high fanout of ""direction"".
+generate
+genvar i, j;
+\tfor (i = 0; i < 5; i = i + 1)
+\tbegin : netgen
+\t\twire [31:0] in;
+\t\treg [31:0] out;
+\t\tfor (j = 0; j < 32; j = j + 1)
+\t\tbegin : net
+\t\t\talways @*
+\t\t\t\tout[j] = in[j] & (~shift_amount[i] ^ direction) |
+\t\t\t\t\t in[wrap(j, i)] & (shift_amount[i] ^ direction);
+\t\tend
+\tend
+
+\t// Order is reverted with respect to volatile shift_amount[0]
+\tassign netgen[4].in = i_in;
+\tfor (i = 1; i < 5; i = i + 1)
+\tbegin : router
+\t\tassign netgen[i-1].in = netgen[i].out;
+\tend
+endgenerate
+
+// Aliasing
+assign rot_prod = netgen[0].out;
+
+// Submask calculated from LSB sub-selector.
+// Cost: 16 4-to-1 LUTs.
+always @*
+case (low_selector) // synthesis full_case parallel_case
+\t4\'b0000:\tlow_mask = 16\'hffff;
+\t4\'b0001:\tlow_mask = 16\'hfffe;
+\t4\'b0010:\tlow_mask = 16\'hfffc;
+\t4\'b0011:\tlow_mask = 16\'hfff8;
+\t4\'b0100:\tlow_mask = 16\'hfff0;
+\t4\'b0101:\tlow_mask = 16\'hffe0;
+\t4\'b0110:\tlow_mask = 16\'hffc0;
+\t4\'b0111:\tlow_mask = 16\'hff80;
+\t4\'b1000:\tlow_mask = 16\'hff00;
+\t4\'b1001:\tlow_mask = 16\'hfe00;
+\t4\'b1010:\tlow_mask = 16\'hfc00;
+\t4\'b1011:\tlow_mask = 16\'hf800;
+\t4\'b1100:\tlow_mask = 16\'hf000;
+\t4\'b1101:\tlow_mask = 16\'he000;
+\t4\'b1110:\tlow_mask = 16\'hc000;
+\t4\'b1111:\tlow_mask = 16\'h8000;
+endcase
+
+// Left-hand mask calculation.
+// Cost: 33 4-to-1 LUTs.
+always @*
+casez (lsl_selector) // synthesis full_case parallel_case
+\t7\'b1??:\tlsl_mask =  33\'h_1_0000_0000;
+\t7\'b01?:\tlsl_mask =  33\'h_0_0000_0000;
+\t7\'b001:\tlsl_mask = { 1\'h_1, low_mask, 16\'h_0000};
+\t7\'b000:\tlsl_mask = {17\'h_1_ffff, low_mask};
+endcase
+
+// Right-hand mask calculation.
+// Cost: 33 4-to-1 LUTs.
+always @*
+casez (lsr_selector) // synthesis full_case parallel_case
+\t7\'b1??:\tlsr_mask =  33\'h_1_0000_0000;
+\t7\'b01?:\tlsr_mask =  33\'h_0_0000_0000;
+\t7\'b000:\tlsr_mask = { 1\'h_1, bit_swap(low_mask), 16\'h_ffff};
+\t7\'b001:\tlsr_mask = {17\'h_1_0000, bit_swap(low_mask)};
+endcase
+
+// Alias: right-rotated
+assign p_r = {rot_prod[30:0], rot_prod[31]};
+
+// Alias: left-rotated
+assign p_l = rot_prod[31:0];
+
+// ROR MSB, handling special cases
+assign ror_out[0] = i_shift_imm_zero ?\ti_carry_in :
+\t\t\t\t\tp_r[31];
+
+// ROR carry, handling special cases
+assign ror_out[1] = i_shift_imm_zero ?\ti_in[0] :
+\t\t\tshift_nzero ?\tp_r[31] :
+\t\t\t\t\ti_carry_in;
+
+// LSL MSB
+assign lsl_out[0] = \tp_l[31] & lsl_mask[31];
+
+// LSL carry, handling special cases
+assign lsl_out[1] = \tshift_nzero ?\tp_l[0] & lsl_mask[32]:
+\t\t\t\t\ti_carry_in;
+
+// LSR MSB
+assign lsr_out[0] = \tp_r[31] & lsr_mask[31];
+
+// LSR carry, handling special cases
+assign lsr_out[1] = i_shift_imm_zero ?\ti_in[31] :
+\t\t\tshift_nzero ?\tp_r[31] & lsr_mask[32]:
+\t\t\t\t\ti_carry_in;
+
+// ASR MSB
+assign asr_out[0] = \ti_in[31] ?\ti_in[31] :
+\t\t\t\t\tp_r[31] & lsr_mask[31] ;
+
+// LSR carry, handling special cases
+assign asr_out[1] =\tshift_over ?\ti_in[31] :
+\t\t\tshift_nzero ?\tp_r[31] :
+\t\t\t\t\ti_carry_in;
+
+// Carry and MSB are calculated as above
+assign {o_carry_out, o_out[31]} = i_function == LSL ? lsl_out :
+                              i_function == LSR ? lsr_out :
+                              i_function == ASR ? asr_out :
+                                                  ror_out ;
+
+// And the rest of result is the masked rotated input.
+assign o_out[30:0] =\t(p_l[30:0] & lsl_mask[30:0]) |
+\t\t\t(p_r[30:0] & lsr_mask[30:0]) |
+\t\t\t(~lsr_mask[30:0] & {31{asr_sign}});
+
+// Rotate: calculate bit pos for level ""level"" and offset ""pos""
+function [4:0] wrap;
+input integer pos;
+input integer level;
+integer out;
+begin
+\tout = pos - (1 << level);
+\twrap = out[4:0];
+end
+endfunction
+
+// Swap bits in the input 16-bit value
+function [15:0] bit_swap;
+input [15:0] value;
+integer i;
+begin
+\tfor (i = 0; i < 16; i = i + 1)
+\t\tbit_swap[i] = value[15 - i];
+end
+endfunction
+
+endmodule
+"
+"(
+    input rst_b,
+    input p1_clk,
+    input p1_select,
+    input p1_rdnw,
+    input p2_clk,
+    input p2_select,
+    input p2_rdnw,
+    output p2_data_available,
+    output p1_full
+);
+
+   // Initial state: 0 = empty; 1 = full
+   parameter init = 0;
+
+   reg req;
+   reg req_s1;
+   reg req_s2;
+   reg ack;
+   reg ack_s1;
+   reg ack_s2;
+   
+
+   always @ (`p1edge p1_clk or negedge rst_b )   
+     begin
+        if (!rst_b) begin
+          req <= init;
+          ack_s1 <= 1'b0;
+          ack_s2 <= 1'b0;
+        end else begin
+          ack_s1 <= ack;
+          ack_s2 <= ack_s1;\t   
+          case (req)
+            1'b0:
+              if (!ack_s2 & p1_select & !p1_rdnw)
+                req <= 1'b1;
+            1'b1:
+              if (ack_s2)
+                req <= 1'b0;
+          endcase
+        end
+      end
+
+   assign p1_full = req | ack_s2;
+
+   always @ (`p2edge p2_clk or negedge rst_b )   
+     begin
+        if (!rst_b) begin
+          ack <= 1'b0;
+          req_s1 <= init;
+          req_s2 <= init;
+        end else begin
+          req_s1 <= req;
+          req_s2 <= req_s1;
+          case (ack)
+            1'b0:
+              if (req_s2 & p2_select & p2_rdnw)
+                ack <= 1'b1;
+            1'b1:
+              if (!req_s2)
+                ack <= 1'b0;
+          endcase
+        end
+      end
+      
+    assign p2_data_available = !ack & req_s2;
+   
+endmodule
+"
+"/*
+ *  Arithmetic and logical operations for Zet
+ *  Copyright (C) 2008-2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+module zet_arlog (
+    input  [15:0] x,
+    input  [15:0] y,
+    input  [ 2:0] f,
+    output [15:0] o,
+    input         word_op,
+    input         cfi,
+    output        cfo,
+    output        afo,
+    output        ofo
+  );
+
+  // Net declarations
+  wire [15:0] op2;
+  wire [15:0] outadd;
+  wire [15:0] outlog;
+
+  wire ci;
+  wire cfoadd;
+  wire log;
+  wire xs;
+  wire ys;
+  wire os;
+
+  // Module instances
+  zet_fulladd16 fulladd16 ( // We instantiate only one adder
+    .x  (x),                //  to have less hardware
+    .y  (op2),
+    .ci (ci),
+    .co (cfoadd),
+    .z  (outadd),
+    .s  (f[0])
+  );
+
+  // Assignemnts
+  assign op2 = f[0] ? ~y  /* sbb,sub,cmp */
+                    : y;  /* add, adc */
+
+  assign ci  = f[2] | ~f[2] & f[1] & (!f[0] & cfi
+             | f[0] & ~cfi);
+
+  assign log = f[2:0]==3'd1 || f[2:0]==3'd4 || f[2:0]==3'd6;
+  assign afo   = !log & (x[4] ^ y[4] ^ outadd[4]);
+  assign cfo   = !log & (word_op ? cfoadd : (x[8]^y[8]^outadd[8]));
+
+  assign xs  = word_op ? x[15] : x[7];
+  assign ys  = word_op ? y[15] : y[7];
+  assign os  = word_op ? outadd[15] : outadd[7];
+  assign ofo = !log &
+    (f[0] ? (~xs & ys & os | xs & ~ys & ~os)
+          : (~xs & ~ys & os | xs & ys & ~os));
+
+  assign outlog = f[2] ? (f[1] ? x^y : x&y) : x|y;
+  assign o      = log ? outlog : outadd;
+
+endmodule
+"
+"/*
+ *  16-bit bitwise rotate module for Zet
+ *  Copyright (C) 2008-2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+module zet_rxr16 (
+    input      [15:0] x,
+    input             ci,
+    input      [ 4:0] y,
+    input             e,
+    output reg [15:0] w,
+    output reg        co
+  );
+
+  always @(x or ci or y or e)
+    case (y)
+      default: {co,w} <= {ci,x};
+      5'd01: {co,w} <= e ? {x[0], ci, x[15:1]} : {ci, x[0], x[15:1]};
+      5'd02: {co,w} <= e ? {x[ 1:0], ci, x[15: 2]} : {ci, x[ 1:0], x[15: 2]};
+      5'd03: {co,w} <= e ? {x[ 2:0], ci, x[15: 3]} : {ci, x[ 2:0], x[15: 3]};
+      5'd04: {co,w} <= e ? {x[ 3:0], ci, x[15: 4]} : {ci, x[ 3:0], x[15: 4]};
+      5'd05: {co,w} <= e ? {x[ 4:0], ci, x[15: 5]} : {ci, x[ 4:0], x[15: 5]};
+      5'd06: {co,w} <= e ? {x[ 5:0], ci, x[15: 6]} : {ci, x[ 5:0], x[15: 6]};
+      5'd07: {co,w} <= e ? {x[ 6:0], ci, x[15: 7]} : {ci, x[ 6:0], x[15: 7]};
+      5'd08: {co,w} <= e ? {x[ 7:0], ci, x[15: 8]} : {ci, x[ 7:0], x[15: 8]};
+      5'd09: {co,w} <= e ? {x[ 8:0], ci, x[15: 9]} : {ci, x[ 8:0], x[15: 9]};
+      5'd10: {co,w} <= e ? {x[ 9:0], ci, x[15:10]} : {ci, x[ 9:0], x[15:10]};
+      5'd11: {co,w} <= e ? {x[10:0], ci, x[15:11]} : {ci, x[10:0], x[15:11]};
+      5'd12: {co,w} <= e ? {x[11:0], ci, x[15:12]} : {ci, x[11:0], x[15:12]};
+      5'd13: {co,w} <= e ? {x[12:0], ci, x[15:13]} : {ci, x[12:0], x[15:13]};
+      5'd14: {co,w} <= e ? {x[13:0], ci, x[15:14]} : {ci, x[13:0], x[15:14]};
+      5'd15: {co,w} <= e ? {x[14:0], ci, x[15]} : {ci, x[14:0], x[15]};
+      5'd16: {co,w} <= {x,ci};
+    endcase
+endmodule
+"
+"//**************************************************************************
+//    ph_bytequad.v - wrapper for 4 FIFOs in the parasite to host direction
+//   
+//    COPYRIGHT 2010 Richard Evans, Ed Spittles
+// 
+//    This file is part of tube - an Acorn Tube ULA compatible system.
+//   
+//    tube is free software: you can redistribute it and/or modify
+//    it under the terms of the GNU Lesser General Public License as published by
+//    the Free Software Foundation, either version 3 of the License, or
+//    (at your option) any later version.
+//
+//    tube is distributed in the hope that it will be useful,
+//    but WITHOUT ANY WARRANTY; without even the implied warranty of
+//    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//    GNU Lesser General Public License for more details.
+//
+//    You should have received a copy of the GNU Lesser General Public License
+//    along with tube.  If not, see <http://www.gnu.org/licenses/>.
+//
+// ============================================================================
+`timescale 1ns / 1ns
+
+module ph_bytequad (
+                    input h_rst_b,
+                    input h_rd,
+                    input [3:0] h_selectData,
+                    input h_phi2,
+                    
+                    input [7:0] p_data,                  
+                    input [3:0] p_selectData,
+                    input p_phi2,
+                    input p_rdnw,
+                    input one_byte_mode,
+                    output ph_zero_r3_bytes_avail,
+                    output [7:0] h_data,                  
+                    output [3:0] h_data_available,
+                    output [3:0] p_full
+                    );
+   
+   reg [7:0]  h_datamux_r;           
+   wire [3:0] p_full_pre_w;
+   wire [7:0] fifo0_w,
+              fifo1_w,
+              fifo2_w,
+              fifo3_w;   
+   
+   // assign primary IOs
+   assign h_data = h_datamux_r;   
+   assign p_full = p_full_pre_w;
+
+   // Combinatorial selection of data output
+   always @ (fifo0_w or
+             fifo1_w or
+             fifo2_w or
+             fifo3_w or
+             h_selectData
+             )
+     casex (h_selectData)
+       4'bxxx1: h_datamux_r = fifo0_w;
+       4'bxx1x: h_datamux_r = fifo1_w;
+       4'bx1xx: h_datamux_r = fifo2_w;
+       4'b1xxx: h_datamux_r = fifo3_w;
+       default: h_datamux_r = 8'bx;
+     endcase // case h_selectData
+
+   
+   ph_fifo    ph_reg1 ( 
+                        .h_rst_b(h_rst_b),
+                        .h_rd(h_rd),
+                        .h_selectData(h_selectData[0]),
+                        .h_phi2(h_phi2),
+                        .p_selectData(p_selectData[0]),
+                        .p_phi2(p_phi2),
+                        .p_rdnw(p_rdnw),
+                        .p_data(p_data),
+                        .h_data(fifo0_w),
+                        .h_data_available(h_data_available[0]),
+                        .p_full(p_full_pre_w[0])
+                       ); 
+   
+   
+   ph_byte    ph_reg2 (
+                       .h_rst_b(h_rst_b),
+                       .h_rd(h_rd),
+                       .h_selectData(h_selectData[1]),
+                       .h_phi2(h_phi2),
+                       .p_selectData(p_selectData[1]),
+                       .p_phi2(p_phi2),
+                       .p_rdnw(p_rdnw),
+                       .p_data(p_data),
+                       .h_data(fifo1_w),
+                       .h_data_available(h_data_available[1]),
+                       .p_full(p_full_pre_w[1])
+                       ); 
+   
+   ph_reg3    ph_reg3 (
+                       .h_rst_b(h_rst_b),
+                       .h_rd(h_rd),
+                       .h_selectData(h_selectData[2]),
+                       .h_phi2(h_phi2),
+                       .p_data(p_data),
+                       .p_selectData(p_selectData[2]),
+                       .p_phi2(p_phi2),
+                       .p_rdnw(p_rdnw),
+                       .one_byte_mode(one_byte_mode),
+                       .h_data(fifo2_w),
+                       .h_data_available(h_data_available[2]),
+                       .p_empty(ph_zero_r3_bytes_avail),
+                       .p_full(p_full_pre_w[2])
+                       );
+
+   ph_byte    ph_reg4 (
+                       .h_rst_b(h_rst_b),
+                       .h_rd(h_rd),
+                       .h_selectData(h_selectData[3]),
+                       .h_phi2(h_phi2),
+                       .p_selectData(p_selectData[3]),
+                       .p_phi2(p_phi2),
+                       .p_rdnw(p_rdnw),
+                       .p_data(p_data),
+                       .h_data(fifo3_w),
+                       .h_data_available(h_data_available[3]),
+                       .p_full(p_full_pre_w[3])
+                       ); 
+
+   
+endmodule // ph_byte
+
+   
+"
+"/*
+ *  Zet processor top level file
+ *  Copyright (c) 2008-2010  Zeus Gomez Marmolejo <zeus@opencores.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+`timescale 1ns/10ps
+
+`include ""defines.v""
+
+module zet (
+    // Wishbone master interface
+    input         wb_clk_i,
+    input         wb_rst_i,
+    input  [15:0] wb_dat_i,
+    output [15:0] wb_dat_o,
+    output [19:1] wb_adr_o,
+    output        wb_we_o,
+    output        wb_tga_o,  // io/mem
+    output [ 1:0] wb_sel_o,
+    output        wb_stb_o,
+    output        wb_cyc_o,
+    input         wb_ack_i,
+    input         wb_tgc_i,  // intr
+    output        wb_tgc_o,  // inta
+    input         nmi,
+    output        nmia,
+
+    output [19:0] pc  // for debugging purposes
+  );
+
+  // Net declarations
+  wire [15:0] cpu_dat_o;
+  wire        cpu_block;
+  wire [19:0] cpu_adr_o;
+
+  wire        cpu_byte_o;
+  wire        cpu_mem_op;
+  wire        cpu_m_io;
+  wire [15:0] cpu_dat_i;
+  wire        cpu_we_o;
+  wire [15:0] iid_dat_i;
+
+  // Module instantiations
+  zet_core core (
+    .clk (wb_clk_i),
+    .rst (wb_rst_i),
+
+    .intr (wb_tgc_i),
+    .inta (wb_tgc_o),
+    .nmi  (nmi),
+    .nmia (nmia),
+
+    .cpu_adr_o  (cpu_adr_o),
+    .iid_dat_i  (iid_dat_i),
+    .cpu_dat_i  (cpu_dat_i),
+    .cpu_dat_o  (cpu_dat_o),
+    .cpu_byte_o (cpu_byte_o),
+    .cpu_block  (cpu_block),
+    .cpu_mem_op (cpu_mem_op),
+    .cpu_m_io   (cpu_m_io),
+    .cpu_we_o   (cpu_we_o),
+
+    .pc (pc)
+  );
+
+  zet_wb_master wb_master (
+    .cpu_byte_o (cpu_byte_o),
+    .cpu_memop  (cpu_mem_op),
+    .cpu_m_io   (cpu_m_io),
+    .cpu_adr_o  (cpu_adr_o),
+    .cpu_block  (cpu_block),
+    .cpu_dat_i  (cpu_dat_i),
+    .cpu_dat_o  (cpu_dat_o),
+    .cpu_we_o   (cpu_we_o),
+
+    .wb_clk_i  (wb_clk_i),
+    .wb_rst_i  (wb_rst_i),
+    .wb_dat_i  (wb_dat_i),
+    .wb_dat_o  (wb_dat_o),
+    .wb_adr_o  (wb_adr_o),
+    .wb_we_o   (wb_we_o),
+    .wb_tga_o  (wb_tga_o),
+    .wb_sel_o  (wb_sel_o),
+    .wb_stb_o  (wb_stb_o),
+    .wb_cyc_o  (wb_cyc_o),
+    .wb_ack_i  (wb_ack_i)
+  );
+
+  // Assignments
+  assign iid_dat_i  = (wb_tgc_o | nmia) ? wb_dat_i : cpu_dat_i;
+
+endmodule
+"
+"//////////////////////////////////////////////////////////////////////////////////\r
+//\r
+// This file is part of the NextZ80 project\r
+// http://www.opencores.org/cores/nextz80/\r
+//\r
+// Filename: NextZ80Regs.v\r
+// Description: Implementation of Z80 compatible CPU - registers\r
+// Version 1.0\r
+// Creation date: 28Jan2011 - 18Mar2011\r
+//\r
+// Author: Nicolae Dumitrache \r
+// e-mail: ndumitrache@opencores.org\r
+//\r
+/////////////////////////////////////////////////////////////////////////////////\r
+// \r
+// Copyright (C) 2011 Nicolae Dumitrache\r
+// \r
+// This source file may be used and distributed without \r
+// restriction provided that this copyright statement is not \r
+// removed from the file and that any derivative work contains \r
+// the original copyright notice and the associated disclaimer.\r
+// \r
+// This source file is free software; you can redistribute it \r
+// and/or modify it under the terms of the GNU Lesser General \r
+// Public License as published by the Free Software Foundation;\r
+// either version 2.1 of the License, or (at your option) any \r
+// later version. \r
+// \r
+// This source is distributed in the hope that it will be \r
+// useful, but WITHOUT ANY WARRANTY; without even the implied \r
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR \r
+// PURPOSE. See the GNU Lesser General Public License for more \r
+// details. \r
+// \r
+// You should have received a copy of the GNU Lesser General \r
+// Public License along with this source; if not, download it \r
+// from http://www.opencores.org/lgpl.shtml \r
+// \r
+///////////////////////////////////////////////////////////////////////////////////\r
+`timescale 1ns / 1ps\r
+\r
+module Z80Reg(\r
+\tinput wire [7:0]rstatus,\t// 0=af-af', 1=exx, 2=hl-de, 3=hl'-de',4=hl-ixy, 5=ix-iy, 6=IFF1, 7=IFF2\r
+\tinput wire M1,\r
+\tinput wire [5:0]WE,\t\t\t// 5 = flags, 4 = PC, 3 = SP, 2 = tmpHI, 1 = hi, 0 = lo\r
+\tinput wire CLK,\r
+\tinput wire [15:0]ALU8OUT,\t// CPU data out bus (output of alu8)\r
+\tinput wire [7:0]DI,\t\t\t// CPU data in bus\r
+\toutput reg [7:0]DO,\t\t\t// CPU data out bus\r
+\tinput wire [15:0]ADDR,\t\t// CPU addr bus\r
+\tinput wire [7:0]CONST,\r
+\toutput reg [7:0]ALU80,\r
+\toutput reg [7:0]ALU81,\r
+\toutput reg [15:0]ALU160,\r
+\toutput wire[7:0]ALU161,\r
+\tinput wire [7:0]ALU8FLAGS,\t\t\t\r
+\toutput wire [7:0]FLAGS,\r
+\t\r
+\tinput wire [1:0]DO_SEL,\t\t// select DO betwen ALU8OUT lo and th register\r
+\tinput wire ALU160_sel,\t\t// 0=REG_RSEL, 1=PC\r
+\tinput wire [3:0]REG_WSEL,\t// rdow:    \t[3:1] 0=BC, 1=DE, 2=HL, 3=A-TL, 4=I-x  ----- [0] = 0HI,1LO\r
+\tinput wire [3:0]REG_RSEL,\t// mux_rdor:   [3:1] 0=BC, 1=DE, 2=HL, 3=A-TL, 4=I-R, 5=SP, 7=tmpSP   ----- [0] = 0HI, 1LO\r
+\tinput wire DINW_SEL,\t\t\t// select RAM write data between (0)ALU8OUT, and 1(DI)\r
+\tinput wire XMASK,\t\t\t\t// 0 if REG_WSEL should not use IX, IY, even if rstatus[4] == 1\r
+\tinput wire [2:0]ALU16OP,\t// ALU16OP\r
+\tinput wire WAIT\t\t\t\t// wait\r
+\t);\r
+\t\r
+// latch registers\r
+\treg [15:0]pc=0;\t\t\t\t// program counter\r
+\treg [15:0]sp;\t\t\t\t\t// stack pointer\r
+\treg [7:0]r;\t\t\t\t\t\t// refresh\r
+\treg [15:0]flg = 0;\r
+\treg [7:0]th;\t\t\t\t\t// temp high\r
+\r
+// internal wires\t\r
+\twire [15:0]rdor;\t\t// R out from RAM\r
+\twire [15:0]rdow;\t\t// W out from RAM\r
+\twire [3:0]SELW;\t\t// RAM W port sel\r
+\twire [3:0]SELR;\t\t// RAM R port sel\r
+\treg  [15:0]DIN;\t\t// RAM W in data\r
+\treg [15:0]mux_rdor;\t// (3)A reversed mixed with TL, (4)I mixed with R (5)SP\r
+\t\r
+//------------------------------------ RAM block registers ----------------------------------\r
+// 0:BC, 1:DE, 2:HL, 3:A-x, 4:I-x, 5:IX, 6:IY, 7:x-x, 8:BC', 9:DE', 10:HL', 11:A'-x, 12: tmpSP, 13:zero\r
+   RAM16X8D_regs regs_lo (\r
+      .DPO(rdor[7:0]),   // Read-only data output\r
+      .SPO(rdow[7:0]),   // R/W data output\r
+      .A(SELW),       \t // R/W address\r
+      .D(DIN[7:0]),      // Write data input\r
+      .DPRA(SELR), \t\t // Read-only address\r
+      .WCLK(CLK),   \t\t // Write clock input\r
+      .WE(WE[0] & !WAIT) // Write enable input\r
+   );\r
+\r
+   RAM16X8D_regs regs_hi (\r
+      .DPO(rdor[15:8]),  // Read-only data output\r
+      .SPO(rdow[15:8]),  // R/W data output\r
+      .A(SELW),       \t // R/W address\r
+      .D(DIN[15:8]),     // Write data input\r
+      .DPRA(SELR), \t\t // Read-only address\r
+      .WCLK(CLK),   \t\t // Write clock input\r
+      .WE(WE[1] & !WAIT) // Write enable input\r
+   );\r
+\r
+\twire [15:0]ADDR1 = ADDR + !ALU16OP[2]; // address post increment\r
+\twire [7:0]flgmux = {ALU8FLAGS[7:3], SELR[3:0] == 4'b0100 ? rstatus[7] : ALU8FLAGS[2], ALU8FLAGS[1:0]}; // LD A, I/R IFF2 flag on parity\r
+\talways @(posedge CLK)\r
+\t\tif(!WAIT) begin\r
+\t\t\tif(WE[2]) th <= DI;\r
+\t\t\tif(WE[3]) sp <= ADDR1;\r
+\t\t\tif(WE[4]) pc <= ADDR1;\r
+\t\t\tif({REG_WSEL, WE[0]} == 5'b10011) r <= ALU8OUT[7:0]; \r
+\t\t\telse if(M1) r[6:0] <= r[6:0] + 1;\r
+\t\t\tif(WE[5])\r
+\t\t\t\tif(rstatus[0]) flg[15:8] <= flgmux;\r
+\t\t\t\telse flg[7:0] <= flgmux;\r
+\t\tend\r
+\t\r
+\tassign ALU161 = th;\r
+\tassign FLAGS = rstatus[0] ? flg[15:8] : flg[7:0];\r
+\t\r
+\talways @* begin\r
+\t\tDIN = DINW_SEL ? {DI, DI} : ALU8OUT;\r
+\t\tALU80 = REG_WSEL[0] ? rdow[7:0] : rdow[15:8];\r
+\t\tALU81 = REG_RSEL[0] ? mux_rdor[7:0] : mux_rdor[15:8];\r
+\t\tALU160 = ALU160_sel ? pc : mux_rdor;\r
+\t\r
+\t\tcase({REG_WSEL[3], DO_SEL})\r
+\t\t\t0:\tDO = ALU80;\r
+\t\t\t1:\tDO = th;\r
+\t\t\t2: DO = FLAGS;\r
+\t\t\t3: DO = ALU8OUT[7:0];\r
+\t\t\t4: DO = pc[15:8];\r
+\t\t\t5: DO = pc[7:0];\r
+\t\t\t6:\tDO = sp[15:8];\r
+\t\t\t7: DO = sp[7:0];\r
+\t\tendcase\r
+\t\tcase({ALU16OP == 4, REG_RSEL[3:0]})\r
+\t\t\t5'b01001, 5'b11001:\t\t\t\t\t\t\t\tmux_rdor = {rdor[15:8], r};\r
+\t\t\t5'b01010, 5'b01011: \t\t\t\t\t\t\t\tmux_rdor = sp;\r
+\t\t\t5'b01100, 5'b01101, 5'b11100, 5'b11101:\tmux_rdor = {8'b0, CONST};\r
+\t\t\tdefault:\t\tmux_rdor = rdor;\r
+\t\tendcase \r
+\tend\r
+\t\r
+\tRegSelect WSelectW(.SEL(REG_WSEL[3:1]), .RAMSEL(SELW), .rstatus({rstatus[5], rstatus[4] & XMASK, rstatus[3:0]}));\r
+\tRegSelect WSelectR(.SEL(REG_RSEL[3:1]), .RAMSEL(SELR), .rstatus(rstatus[5:0]));\r
+\r
+endmodule\r
+\r
+\r
+module RegSelect(\r
+\tinput [2:0]SEL,\r
+\toutput reg [3:0]RAMSEL,\r
+\tinput [5:0]rstatus\t\t\t// 0=af-af', 1=exx, 2=hl-de, 3=hl'-de',4=hl-ixy, 5=ix-iy\r
+\t);\r
+\t\r
+\talways @* begin\r
+\t\tRAMSEL = 4'bxxxx;\r
+\t\tcase(SEL)\r
+\t\t\t0: RAMSEL = {rstatus[1], 3'b000};\t// BC\r
+\t\t\t1:  //DE\r
+\t\t\t\tif(rstatus[{1'b1, rstatus[1]}]) RAMSEL = {rstatus[1], 3'b010};\t\t//\tHL\r
+\t\t\t\telse RAMSEL = {rstatus[1], 3'b001};\t\t\t\t// DE\r
+\t\t\t2:\t// HL\r
+\t\t\t\tcase({rstatus[5:4], rstatus[{1'b1, rstatus[1]}]})\r
+\t\t\t\t\t0,4: \tRAMSEL = {rstatus[1], 3'b010}; \t\t// HL\r
+\t\t\t\t\t1,5: \tRAMSEL = {rstatus[1], 3'b001};\t\t// DE\r
+\t\t\t\t\t2,3:\tRAMSEL = 4'b0101;  \t//\tIX\r
+\t\t\t\t\t6,7:\tRAMSEL = 4'b0110;\t\t// IY\r
+\t\t\t\tendcase\r
+\t\t\t3: RAMSEL = {rstatus[0], 3'b011}; // A-TL\r
+\t\t\t4:\tRAMSEL = 4; // I-R\r
+\t\t\t5: RAMSEL = 12;\t// tmp SP\r
+\t\t\t6: RAMSEL = 13;\t// zero\r
+\t\t\t7: RAMSEL = 7;\t// temp reg for BIT/SET/RES\r
+\t\tendcase\r
+\tend\r
+endmodule\t\r
+\r
+module RAM16X8D_regs(\r
+      output [7:0]DPO,     // Read-only data output\r
+      output [7:0]SPO,     // R/W data output\r
+      input [3:0]A,       \t// R/W address \r
+      input [7:0]D,        // Write data input\r
+      input [3:0]DPRA, \t\t// Read-only address\r
+      input WCLK,   \t\t\t// Write clock\r
+      input WE        \t\t// Write enable\r
+   );\r
+\t\r
+\treg [7:0]data[15:0];\r
+\tassign DPO = data[DPRA];\r
+\tassign SPO = data[A];\r
+\t\r
+\talways @(posedge WCLK)\r
+\t\tif(WE) data[A] <= D;\t\t\r
+\r
+endmodule\r
+"
+"// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+// This file is part of the M32632 project\r
+// http://opencores.org/project,m32632\r
+//\r
+// Filename: CACHE_LOGIK.v\r
+// Version:  1.1 bug fix\r
+// History:  1.0 first release of 30 Mai 2015\r
+// Date:     7 October 2015\r
+//\r
+// Copyright (C) 2015 Udo Moeller\r
+// \r
+// This source file may be used and distributed without \r
+// restriction provided that this copyright statement is not \r
+// removed from the file and that any derivative work contains \r
+// the original copyright notice and the associated disclaimer.\r
+// \r
+// This source file is free software; you can redistribute it \r
+// and/or modify it under the terms of the GNU Lesser General \r
+// Public License as published by the Free Software Foundation;\r
+// either version 2.1 of the License, or (at your option) any \r
+// later version. \r
+// \r
+// This source is distributed in the hope that it will be \r
+// useful, but WITHOUT ANY WARRANTY; without even the implied \r
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR \r
+// PURPOSE. See the GNU Lesser General Public License for more \r
+// details. \r
+// \r
+// You should have received a copy of the GNU Lesser General \r
+// Public License along with this source; if not, download it \r
+// from http://www.opencores.org/lgpl.shtml \r
+// \r
+// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\tModules contained in this file:\r
+//\t1. DEBUG_AE  \tDebug unit for address compare in data cache\r
+//\t2. MMU_UP\t\tMMU memory update and initalization controller\r
+//\t3. DCA_CONTROL\tData cache valid memory update and initalization controller\r
+//\t4. MMU_MATCH\tMMU virtual address match detector\r
+//\t5. CA_MATCH\t\tCache tag match detector\r
+//\t6. DCACHE_SM\tData cache state machine\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t1. DEBUG_AE  \tDebug unit for address compare in data cache\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module DEBUG_AE ( DBG_IN, READ, WRITE, USER, VIRTUELL, ACC_OK, VADR_R, MMU_Q, ENBYTE, DBG_HIT );\r
+\r
+\tinput\t[40:2]\tDBG_IN;\r
+\t\r
+\tinput\t\t\tREAD,WRITE;\r
+\tinput\t\t\tUSER;\r
+\tinput\t\t\tVIRTUELL;\r
+\tinput\t\t\tACC_OK;\r
+\tinput\t[31:2]\tVADR_R;\r
+\tinput\t[19:0]\tMMU_Q;\r
+\tinput\t [3:0]\tENBYTE;\r
+\t\r
+\toutput\t \t\tDBG_HIT;\r
+\t\r
+\twire\t\t\tsd,ud,crd,cwr,vnp;\r
+\twire\t\t\tmake;\r
+\twire\t\t\tvirt_adr,real_adr,page_adr;\r
+\twire\t\t\tbyte_en;\r
+\t\r
+\tassign sd  = DBG_IN[40];\r
+\tassign ud  = DBG_IN[39];\r
+\tassign crd = DBG_IN[38];\r
+\tassign cwr = DBG_IN[37];\r
+\tassign vnp = DBG_IN[36];\r
+\t\r
+\tassign make =  ((ud & USER) | (sd & ~USER))\t\t// compare USER or SUPERVISOR\r
+\t\t\t\t & (VIRTUELL == vnp)\t\t\t\t// compare real or virtual address\r
+\t\t\t\t & ((cwr & WRITE) | (crd & READ));\t// compare READ or WRITE\r
+\t\r
+\tassign virt_adr = (MMU_Q \t\t == DBG_IN[31:12]);\r
+\tassign real_adr = (VADR_R[31:12] == DBG_IN[31:12]);\r
+\tassign page_adr = (VADR_R[11:2]\t == DBG_IN[11:2]);\r
+\t\r
+\tassign byte_en  = |(ENBYTE & DBG_IN[35:32]);\r
+\t\r
+\tassign DBG_HIT  =  ACC_OK\t\t// all valid\r
+\t\t\t\t\t & make\t\t\t// selection is valid\r
+\t\t\t\t\t & (VIRTUELL ? virt_adr : real_adr)\t& page_adr\t// address\r
+\t\t\t\t\t & byte_en;\t\t// Byte Enable\r
+\t\t\t\t\t \r
+endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t2. MMU_UP\t\tMMU memory update and initalization controller\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module MMU_UP ( BCLK, BRESET, NEW_PTB, PTB1, IVAR, WR_MRAM, VADR, VADR_R, MVALID, UPDATE,\r
+\t\t\t\tWE_MV, WADR_MV, RADR_MV, DAT_MV, NEW_PTB_RUN );\r
+\r
+\tinput\t\t\tBCLK;\r
+\tinput\t\t\tBRESET;\t\r
+\tinput\t\t\tNEW_PTB;\t// the MMU memory is cleared. Pulse of one BCLK cycle, Op-Dec is waiting\r
+\tinput\t\t\tPTB1;\t\t// which one\r
+\tinput\t\t\tIVAR;\r
+\tinput\t\t\tWR_MRAM;\t// BCLK : update MRAM and MMU_VAL\r
+\tinput  [19:16]\tVADR,VADR_R;\t// For update\r
+\tinput\t[31:0]\tMVALID,UPDATE;\r
+\t\r
+\toutput\t\t\tWE_MV;\t\t// Write Enable MMU Valid\r
+\toutput\t [3:0]\tWADR_MV,RADR_MV;\r
+\toutput\t[31:0]\tDAT_MV;\r
+\toutput\t\t\tNEW_PTB_RUN;\r
+\t\r
+\treg\t\t\t\tneue_ptb,wr_flag,old_rst,run_over;\r
+\treg\t\t [3:0]\tcount;\r
+\t\r
+\twire\t[15:0]\tnew_val;\r
+\t\r
+\tassign WE_MV   = wr_flag | WR_MRAM | IVAR;\t// write on falling edge BCLK\r
+\tassign RADR_MV = run_over ? count : VADR;\r
+\tassign WADR_MV = wr_flag ? (count - 4\'b0001) : VADR_R;\r
+\tassign DAT_MV  = wr_flag ? {MVALID[31:16],new_val} : UPDATE;\t// Only the matching entries are cleared : PTB0/PTB1\r
+\r
+\t// [31:16] Address-Space memory, [15:0] Valid memory\r
+\tassign new_val = neue_ptb ? (PTB1 ? (MVALID[15:0] & ~MVALID[31:16]) : (MVALID[15:0] & MVALID[31:16])) : 16\'h0;\r
+\t\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) neue_ptb <= 1\'b0;\r
+\t\t\telse neue_ptb <= NEW_PTB | (neue_ptb & run_over);\r
+\t\t\t\r
+\talways @(posedge BCLK) old_rst <= BRESET;\t// after Reset all will be set to 0 \r
+\t\r
+\talways @(posedge BCLK) run_over <= ((~old_rst | NEW_PTB) | (run_over & (count != 4\'hF))) & BRESET;\r
+\t\r
+\talways @(posedge BCLK) count <= run_over ? count + 4\'h1 : 4\'h0;\r
+\t\r
+\talways @(posedge BCLK) wr_flag <= run_over;\r
+\r
+\tassign NEW_PTB_RUN = wr_flag;\t// Info to Op-Dec\r
+\t\r
+endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t3. DCA_CONTROL\tData cache valid memory update and initalization controller\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module DCA_CONTROL ( BCLK, MCLK, BRESET, CUPDATE, DRAM_ACC, CA_SET, HIT_ALL, WRCFG, VADR_R, UPDATE, INVAL_A, WRITE,\r
+\t\t\t\t\t WCTRL, KILL, WRCRAM0, WRCRAM1, WE_CV, WADR_CV, DAT_CV, INIT_CA_RUN, WRSET0, WRSET1 );\r
+\r
+\tinput\t\t\tBCLK;\r
+\tinput\t\t\tMCLK;\r
+\tinput\t\t\tBRESET;\r
+\tinput\t\t\tCUPDATE;\t// State CUPDATE : Cache is filled from DRAM\r
+\tinput\t\t\tDRAM_ACC;\r
+\tinput\t\t\tCA_SET;\r
+\tinput\t\t\tHIT_ALL;\t// a complete cache hit !\r
+\tinput\t\t\tWRCFG;\t\t// static signal : GND or VDD\r
+\tinput\t[11:7]\tVADR_R;\r
+\tinput\t[23:0]\tUPDATE;\r
+\tinput\t\t\tINVAL_A;\r
+\tinput\t\t\tWRITE;\r
+\tinput\t [1:0]\tWCTRL;\t\t// [1] : Read Burst Signal from DRAM controller, MCLK aligned. [0] : Cache inhibit\r
+\tinput\t\t\tKILL;\t\t// valid Ram must be updated because of collision ... or CINV\r
+\t\r
+\toutput\t\t\tWRCRAM0,WRCRAM1;\r
+\toutput\t\t\tWE_CV;\r
+\toutput\t [4:0]\tWADR_CV;\r
+\toutput\t[23:0]\tDAT_CV;\r
+\toutput\t\t\tINIT_CA_RUN;\r
+\toutput\t\t\tWRSET0,WRSET1;\r
+\t\r
+\treg\t\t [1:0]\tstate;\r
+\treg\t\t [4:0]\tacount;\r
+\treg\t\t\t\tca_set_d;\r
+\r
+\treg\t\t\t\tdly_bclk,zero,wr_puls;\r
+\treg\t\t [2:0]\tcount,refer;\r
+\t\r
+\twire\t\t\tcountf;\r
+\t\r
+\t// physical address is stored in TAG-RAM\r
+\r
+\tassign WRCRAM0 = (CUPDATE & ~WCTRL[0]) & ~CA_SET;\r
+\tassign WRCRAM1 = (CUPDATE & ~WCTRL[0]) &  CA_SET;\r
+\t\r
+\t// Load Valid RAM :\r
+\t\r
+\tassign WE_CV   = state[1] | HIT_ALL | (CUPDATE & ~WCTRL[0]) | KILL; // Hit All for ""Last"" Update\r
+\tassign WADR_CV = state[1] ? acount : VADR_R;\r
+\tassign DAT_CV  = state[1] ? 24\'h0 : UPDATE;\t\r
+\r
+\t// Clear of Cache-Valid RAMs : 32 clocks of BCLK\r
+\t\r
+\tassign countf = (acount == 5\'h1F);\r
+\t\r
+\talways @(posedge BCLK)\r
+\t\tcasex ({BRESET,INVAL_A,countf,state[1:0]})\r
+\t\t  5\'b0xx_xx : state <= 2\'b01;\r
+\t\t  5\'b1xx_01 : state <= 2\'b10;\t\t// start counter\r
+\t\t  5\'b10x_00 : state <= 2\'b00;\t\t// wait ...\r
+\t\t  5\'b11x_00 : state <= 2\'b10;\r
+\t\t  5\'b1x0_10 : state <= 2\'b10;\r
+\t\t  5\'b1x1_10 : state <= 2\'b00;\r
+\t\t  default   : state <= 2\'b0;\r
+\t\tendcase\r
+\t\r
+\talways @(posedge BCLK) if (!state[1]) acount <= 5\'h0; else acount <= acount + 5\'h01;\r
+\r
+\tassign INIT_CA_RUN = state[1];\r
+\t\r
+\talways @(posedge BCLK) if (DRAM_ACC) ca_set_d <= CA_SET;\r
+\t\r
+\t// WRITE Control in data RAMs\r
+\tassign WRSET0 = ( ~CA_SET & WRITE & HIT_ALL & wr_puls) | (WCTRL[1] & ~ca_set_d);\r
+\tassign WRSET1 = (  CA_SET & WRITE & HIT_ALL & wr_puls) | (WCTRL[1] &  ca_set_d);\r
+\t\r
+\t// ++++++++++++ Special circuit for Timing of write pulse for data RAM of data cache +++++++++\r
+\t\r
+\talways @(negedge MCLK) dly_bclk <= BCLK;\r
+\t\r
+\talways @(negedge MCLK) zero <= BCLK & ~dly_bclk;\r
+\t\r
+\talways @(posedge MCLK) if (zero) count <= 3\'d0; else count <= count + 3\'d1;\r
+\t\r
+\t//    count at zero , ref Wert\r
+\t// 1 : --- always on\t5 : 100  001\r
+\t// 2 : 001  000\t\t\t6 : 101  010\r
+\t// 3 : 010  010\t\t\t7 : 110  011\r
+\t// 4 : 011  000\t\t\t8 : 111  100\r
+\talways @(posedge MCLK) if (zero) refer <= {(count == 3\'d7),((count == 3\'d5) | (count[1:0] == 2\'b10)),(count[2] & ~count[0])};\r
+\t\r
+\talways @(posedge MCLK) wr_puls <= (count == refer) | WRCFG;\r
+\t\r
+endmodule\r
+\t\t\t\t\t\t\t\t\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t4. MMU_MATCH\tMMU virtual address match detector\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module MMU_MATCH ( USER, READ, WRITE, RMW, MCR_FLAGS, MVALID, VADR_R, MMU_VA, IVAR,\r
+\t\t\t\t   VIRTUELL, MMU_HIT , UPDATE, PROT_ERROR, CI, SEL_PTB1 );\r
+\r
+\tinput\t\t\tUSER;\r
+\tinput\t\t\tREAD;\r
+\tinput\t\t\tWRITE;\r
+\tinput\t\t\tRMW;\r
+\tinput\t [2:0]\tMCR_FLAGS;\r
+\tinput\t[31:0]\tMVALID;\r
+\tinput  [31:12]\tVADR_R;\r
+\tinput  [31:16]\tMMU_VA;\r
+\tinput\t [1:0]\tIVAR;\t// Invalidate Entry\r
+\t\r
+\toutput\t\t\tVIRTUELL;\t// only for Adress-Mux\r
+\toutput\t\t\tMMU_HIT;\r
+\toutput\t[31:0]\tUPDATE;\r
+\toutput\treg\t\tPROT_ERROR;\t// if valid must suppress write in Write Buffer and cache\r
+\toutput\t\t\tCI,SEL_PTB1;\r
+\t\r
+\treg\t\t[15:0]\tmaske;\r
+\r
+\twire\t\t\tadr_space,as_sorte,match,alles_ok;\r
+\twire\t[15:0]\tval_bits,as_bits;\r
+\twire\t\t\tena_prot;\r
+\twire\t\t\tzugriff;\r
+\t\r
+\tassign zugriff = READ | WRITE;\r
+\t\r
+\talways @(VADR_R)\r
+\t\tcase (VADR_R[15:12])\r
+\t\t  4\'h0 : maske = 16\'h0001;\r
+\t\t  4\'h1 : maske = 16\'h0002;\r
+\t\t  4\'h2 : maske = 16\'h0004;\r
+\t\t  4\'h3 : maske = 16\'h0008;\r
+\t\t  4\'h4 : maske = 16\'h0010;\r
+\t\t  4\'h5 : maske = 16\'h0020;\r
+\t\t  4\'h6 : maske = 16\'h0040;\r
+\t\t  4\'h7 : maske = 16\'h0080;\r
+\t\t  4\'h8 : maske = 16\'h0100;\r
+\t\t  4\'h9 : maske = 16\'h0200;\r
+\t\t  4\'hA : maske = 16\'h0400;\r
+\t\t  4\'hB : maske = 16\'h0800;\r
+\t\t  4\'hC : maske = 16\'h1000;\r
+\t\t  4\'hD : maske = 16\'h2000;\r
+\t\t  4\'hE : maske = 16\'h4000;\r
+\t\t  4\'hF : maske = 16\'h8000;\r
+\t\tendcase\r
+\t\t\r
+\tassign VIRTUELL = USER ? MCR_FLAGS[0] : MCR_FLAGS[1];\r
+\t\r
+\tassign adr_space = IVAR[1] ? IVAR[0] : (MCR_FLAGS[2] & USER);\t// adr_space = IVARx ? 1 or 0 : DualSpace & TU\r
+\t\r
+\tassign as_sorte = ((MVALID[31:16] & maske) != 16\'h0);\r
+\t\t  \r
+\tassign match = (VADR_R[31:20] == MMU_VA[31:20]) & (adr_space == as_sorte) & ((MVALID[15:0] & maske) != 16\'h0000);\r
+\t\r
+\tassign alles_ok = match & ( ~WRITE | MMU_VA[17] ) & ~PROT_ERROR;\t// Modified - Flag : reload the PTE\r
+\t\r
+\t// if MMU_HIT = 0 then there is no Write-Buffer access abd no update of cache !\r
+\tassign MMU_HIT = zugriff ? ( VIRTUELL ? alles_ok : 1\'b1 ) : 1\'b0 ;\t// MMU off : then always HIT\r
+\r
+\tassign val_bits = IVAR[1] ? (MVALID[15:0] & (match ? ~maske : 16\'hFFFF)) : (MVALID[15:0] | maske);\r
+\tassign as_bits  = IVAR[1] ? MVALID[31:16] : (adr_space ? (MVALID[31:16] | maske) : (MVALID[31:16] & ~maske));\r
+\t\r
+\tassign UPDATE = {as_bits,val_bits};\r
+\r
+\tassign ena_prot = zugriff & VIRTUELL & match;\r
+\t\r
+\t// A Protection error must suppress write in WB and cache\r
+\talways @(ena_prot or MMU_VA or USER or WRITE or RMW)\r
+\t\tcase ({ena_prot,MMU_VA[19:18]})\r
+\t\t   3\'b100 : PROT_ERROR = USER | WRITE | RMW;\t// Only Supervisor READ\r
+\t\t   3\'b101 : PROT_ERROR = USER;\t\t\t\t\t// no USER access\r
+\t\t   3\'b110 : PROT_ERROR = USER & (WRITE | RMW);\t// USER only READ\r
+\t\t  default : PROT_ERROR = 1\'b0;\r
+\t\tendcase\r
+\t\t\r
+\tassign CI = VIRTUELL & MMU_VA[16];\r
+\tassign SEL_PTB1 = adr_space;\t\t// For PTE update\r
+\t\t\r
+endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t5. CA_MATCH\t\tCache tag match detector\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module CA_MATCH ( CVALID, IOSEL, ADDR, TAG0, TAG1, CFG, WRITE, MMU_HIT, CI, INVAL_L, KDET, ENDRAM, DC_ILO,\r
+\t\t\t\t  CA_HIT, CA_SET, UPDATE, IO_SPACE, USE_CA, WB_ACC, KILL );\r
+\r
+\tinput\t[23:0]\tCVALID;\r
+\tinput\t [3:0]\tIOSEL;\r
+\tinput\t[27:4]\tADDR;\r
+\tinput  [27:12]\tTAG0,TAG1;\r
+\tinput\t [1:0]\tCFG;\t// LDC , DC\r
+\tinput\t\t\tWRITE;\r
+\tinput\t\t\tMMU_HIT;\r
+\tinput\t\t\tCI;\r
+\tinput\t\t\tINVAL_L;\t// invalid cache line\r
+\tinput\t\t\tKDET;\r
+\tinput\t\t\tENDRAM;\r
+\tinput\t\t\tDC_ILO;\t\t// CBITI/SBITI special case\r
+\t\r
+\toutput\t\t\tCA_HIT;\r
+\toutput\t\t\tCA_SET;\t// if no Hit then says SET where to store\r
+\toutput\t[23:0]\tUPDATE;\t// Update Information for CVALID memory \r
+\toutput\t\t\tIO_SPACE;\r
+\toutput\t\t\tUSE_CA;\r
+\toutput\t\t\tWB_ACC;\r
+\toutput\t\t\tKILL;\r
+\t\r
+\treg\t\t [7:0]\tmaske;\r
+\t\r
+\twire\t\t\tmatch_0,match_1;\r
+\twire\t\t\tvalid_0,valid_1;\r
+\twire\t\t\tselect;\r
+\twire\t\t\tclear;\r
+\twire\t [7:0]\tupdate_0,update_1,lastinfo;\r
+\twire\t\t\tsel_dram;\r
+\t\r
+\talways @(ADDR)\r
+\t\tcase (ADDR[6:4])\r
+\t\t  3\'h0 : maske = 8\'h01;\r
+\t\t  3\'h1 : maske = 8\'h02;\r
+\t\t  3\'h2 : maske = 8\'h04;\r
+\t\t  3\'h3 : maske = 8\'h08;\r
+\t\t  3\'h4 : maske = 8\'h10;\r
+\t\t  3\'h5 : maske = 8\'h20;\r
+\t\t  3\'h6 : maske = 8\'h40;\r
+\t\t  3\'h7 : maske = 8\'h80;\r
+\t\tendcase\r
+\t\t\r
+\tassign valid_0 = (( CVALID[7:0] & maske) != 8\'h00);\r
+\tassign valid_1 = ((CVALID[15:8] & maske) != 8\'h00);\r
+\t\r
+\tassign match_0 = ( TAG0 == ADDR[27:12] );\t// 4KB\r
+\tassign match_1 = ( TAG1 == ADDR[27:12] );\t// 4KB\r
+\r
+\tassign CA_HIT = ((valid_0 & match_0) | (valid_1 & match_1)) & ~DC_ILO & CFG[0];\r
+\t\r
+\t// which SET is written in cache miss ? If both are valid the last used is not taken\r
+\tassign select = (valid_1 & valid_0) ? ~((CVALID[23:16] & maske) != 8\'h00) : valid_0;\t// Last-used field = CVALID[23:16]\r
+\t\r
+\tassign CA_SET = CA_HIT ? (valid_1 & match_1) : select;\r
+\t\r
+\tassign clear = INVAL_L | KDET;\t// INVAL_L is from CINV\r
+ \r
+\tassign update_0 = CA_SET ? CVALID[7:0] : (clear ? (CVALID[7:0] & ~maske) : (CVALID[7:0] | maske));\r
+\tassign update_1 = CA_SET ? (clear ? (CVALID[15:8] & ~maske) : (CVALID[15:8] | maske)) : CVALID[15:8];\r
+\t\r
+\tassign lastinfo = CA_HIT ? (CA_SET ? (CVALID[23:16] | maske) : (CVALID[23:16] & ~maske)) : CVALID[23:16];\r
+\t\r
+\tassign UPDATE = {lastinfo,update_1,update_0};\r
+\t\r
+\tassign KILL = clear & CA_HIT & ~CFG[1];\t\t// only if cache is not locked\r
+\t\r
+\tassign sel_dram = (IOSEL == 4\'b0000) & ENDRAM;\t// at the moment the first 256 MB of memory\r
+\tassign IO_SPACE = ~sel_dram;\t\t\t\t\t// not DRAM or DRAM ist off\r
+\tassign USE_CA   = ~CI & ~DC_ILO & CFG[0] & ~CFG[1];\t// CI ? ILO ? Cache on ? Locked Cache ? \r
+\tassign WB_ACC   = WRITE & MMU_HIT & sel_dram;\r
+\t\r
+endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t6. DCACHE_SM\tData cache state machine\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module DCACHE_SM ( BCLK, BRESET, IO_SPACE, MDONE, IO_READY, MMU_HIT, CA_HIT, READ, WRITE, ZTEST, RMW, CAPDAT, VADR_R, IC_VA, \r
+\t\t\t\t   USE_CA, PTB_WR, PTB_SEL, SEL_PTB1, CPU_OUT, USER, PROT_ERROR, WB_ACC, ENWR, ADR_EQU, IC_PREQ, FILLRAM, ICTODC,\r
+\t\t\t\t   RWVAL, VIRTUELL, QWATWO,\r
+\t\t\t\t   DRAM_ACC, DRAM_WR, IO_ACC, IO_RD, IO_WR, PTE_MUX, PD_MUX, PKEEP, PTE_ADR, PTE_DAT, HIT_ALL, ACC_OK,\r
+\t\t\t\t   ABORT, PROTECT, IACC_STAT, ABO_LEVEL1, WR_MRAM, CUPDATE, AUX_DAT, NEW_PTB, PTB_ONE, MMU_DIN, IC_SIGS, KOMUX,\r
+\t\t\t\t   KDET, DMA_MUX, HLDA, RWVFLAG, PTE_STAT );\r
+\r
+\tinput\t\t\tBCLK;\r
+\tinput\t\t\tBRESET;\r
+\tinput\t\t\tIO_SPACE;\r
+\tinput\t\t\tMDONE;\t\t// Memory Done : feedback from DRAM Controller, BCLK aligned !\r
+\tinput\t\t\tIO_READY;\r
+\tinput\t\t\tMMU_HIT,CA_HIT;\r
+\tinput\t\t\tREAD,WRITE,ZTEST,RMW;\r
+\tinput\t[31:0]\tCAPDAT;\r
+\tinput  [31:12]\tVADR_R,IC_VA;\r
+\tinput\t\t\tUSE_CA;\r
+\tinput\t\t\tPTB_WR,PTB_SEL;\r
+\tinput\t\t\tSEL_PTB1;\r
+\tinput  [27:12]\tCPU_OUT;\t// used for PTB0/1\r
+\tinput\t\t\tUSER;\r
+\tinput\t\t\tPROT_ERROR;\r
+\tinput\t\t\tWB_ACC;\r
+\tinput\t\t\tENWR;\t\t// Enable WRITE from DRAM\r
+\tinput\t\t\tADR_EQU;\r
+\tinput\t\t\tIC_PREQ;\r
+\tinput\t\t\tFILLRAM;\r
+\tinput\t [3:0]\tICTODC;\t\t// multiple signals from ICACHE, especially DMA\r
+\tinput\t [1:0]\tRWVAL;\t\t// RDVAL+WRVAL Operation\r
+\tinput\t\t\tVIRTUELL;\t// for RDVAL/WRVAL\r
+\tinput\t\t\tQWATWO;\r
+\t\r
+\toutput\treg\t\tDRAM_ACC,DRAM_WR;\r
+\toutput\t\t\tIO_ACC,IO_RD,IO_WR;\r
+\toutput\t\t\tPTE_MUX,PD_MUX,PKEEP;\r
+\toutput\t[27:0]\tPTE_ADR;\r
+\toutput\t[19:0]\tPTE_DAT;\r
+\toutput\t\t\tHIT_ALL;\r
+\toutput\t\t\tACC_OK;\r
+\toutput\t\t\tABORT,PROTECT;\r
+\toutput\t [3:1]\tIACC_STAT;\r
+\toutput\t\t\tABO_LEVEL1;\r
+\toutput\t\t\tWR_MRAM;\r
+\toutput\t\t\tCUPDATE;\r
+\toutput\t\t\tAUX_DAT;\r
+\toutput\treg\t\tNEW_PTB;\r
+\toutput\treg\t\tPTB_ONE;\r
+\toutput\t[23:0]\tMMU_DIN;\r
+\toutput\t [1:0]\tIC_SIGS;\r
+\toutput\t\t\tKOMUX;\r
+\toutput\t\t\tKDET;\t\t// Signal for detection of collision\r
+\toutput\t\t\tDMA_MUX;\r
+\toutput\t\t\tHLDA;\t\t// active low\r
+\toutput\t\t\tRWVFLAG;\t// RDVAL/WRVAL result\r
+\toutput\t [1:0]\tPTE_STAT;\r
+\t\r
+\treg\t\t\t\tIO_WR,IO_RD;\r
+\treg\t\t [1:0]\tpl_dat;\r
+\treg\t\t [6:0]\tnew_state;\r
+\treg\t\t [2:0]\tcap_dat;\t// only for analyse of timing\r
+\treg\t\t\t\tmem_done;\r
+\treg\t\t\t\trd_done;\r
+\treg\t\t [2:0]\tpstate;\r
+\treg\t\t\t\tpte_run_wr;\r
+\treg\t\t [1:0]\tprot_level1;\r
+\treg\t\t\t\tcard_flag;\r
+\treg\t   [27:12]\tptb0,ptb1;\r
+\treg\t\t\t\twrite_ok;\r
+\treg\t\t\t\ticp_acc;\r
+\treg\t\t\t\tpte_modi;\r
+\treg\t\t [2:0]\tko_state;\r
+\treg\t\t\t\tdma_run;\r
+\treg\t\t\t\tdma_kdet;\r
+\treg\t\t\t\trwv_bit;\r
+\treg\t\t\t\tprot_i;\r
+\treg\t\t\t\trd_rdy;\r
+\t\r
+\twire   [27:12]\tptb10;\r
+\twire   [31:12]\tvirtual_adr;\r
+\twire\t\t\tio_busy;\r
+\twire\t\t\tdram_go;\r
+\twire\t\t\tpte_sel;\r
+\twire\t\t\tpte_acc;\r
+\twire\t\t\tdo_ca_rd,pte_go,do_ic_p;\r
+\twire\t\t\tvalid,valid_a,refer,modi;\r
+\twire\t\t\tlevel1,level2;\r
+\twire\t\t\trd_level2;\r
+\twire\t\t\twr_req;\r
+\twire\t\t\twr_dram;\r
+\twire\t\t\twr_icmram;\r
+\twire\t\t\trd_ende;\r
+\twire\t\t\tpte_dat_8;\r
+\twire\t\t\tpte_wr_sig;\r
+\twire\t\t\trun_dc;\r
+\twire\t\t\tkostart;\r
+\twire\t\t\tdma;\r
+\twire\t\t\tdma_go;\r
+\twire\t\t\tzugriff;\r
+\twire\t\t\tmmu_hit_i;\r
+\twire\t\t\tdo_zt;\r
+\twire\t\t\tzt_ok;\r
+\twire\t [1:0]\tacc_level;\r
+\twire\t\t\tuser_ptw,wr_ptw;\r
+\twire\t\t\tpte_puls;\r
+\t\r
+\talways @(posedge BCLK) cap_dat <= CAPDAT[2:0];\r
+\t\r
+\t// if USER not virtual then ZTEST is quickly done\r
+\tassign zugriff = READ | WRITE | (ZTEST & VIRTUELL);\r
+\tassign mmu_hit_i = MMU_HIT & ~ZTEST;\r
+\t\r
+\t// WB_ACC is a successful WRITE access, ICTODC[0] is coherent Logik release : >=3 entries in FIFO\r
+\tassign wr_req = WB_ACC & ((ENWR & ICTODC[0]) | (DRAM_WR & ADR_EQU));\t// release done by DRAM signal ENWR\r
+\r
+\tassign rd_ende = CA_HIT | rd_rdy;\t// CA_HIT only when Cache activ !\r
+\t\r
+\talways @(\t zugriff \t// READ or WRITE or ZTEST , global control\r
+\t\t\t  or PROT_ERROR\t// must not be\r
+\t\t\t//\r
+\t\t\t  or IO_SPACE\t// access of IO world\r
+\t\t\t  or io_busy\t// is access already running ?\r
+\t\t\t//\r
+\t\t\t  or mmu_hit_i\t// Hit in MMU , now only a READ can happen\r
+\t\t\t  or READ\r
+\t\t\t  or wr_req\r
+\t\t\t  or rd_ende\t// Cache Hit\r
+\t\t\t//\r
+\t\t\t  or DRAM_ACC \t// DRAM Access : shows an active state\r
+\t\t\t  or pte_acc \t// PTE access is running\r
+\t\t\t//\r
+\t\t\t  or IC_PREQ \t// PTE Request from ICACHE\r
+\t\t\t//\r
+\t\t\t  or dma\t\t// DMA Request\r
+\t\t\t  or dma_run )\t// DMA running\r
+\t\t\t//\t\t\t\t\t #_#\t\t\t  #_#\t\t\t\t\t\t    #_#\t\t\t\t\t    #_#\r
+\t\tcasex ({zugriff,PROT_ERROR,IO_SPACE,io_busy,mmu_hit_i,READ,wr_req,rd_ende,DRAM_ACC,pte_acc,IC_PREQ,dma,dma_run})\r
+\t\t// MMU Miss : PTE load from memory , valid too if WRITE and M=0\r
+\t\t  13\'b10_xx_0xxx_x0_x_x0 : new_state = 7\'b0001010;\t// start PTE access\r
+\t  \t// IO-Address selected : external access starts if not busy because of WRITE\r
+\t\t  13\'b10_10_1xxx_x0_x_x0 : new_state = 7\'b0000001;\r
+\t\t// DRAM access : Cache Miss at READ : \r
+\t\t  13\'b10_0x_1100_00_x_x0 : new_state = 7\'b0010010;\r
+\t\t// DRAM access : WRITE\r
+\t\t  13\'b10_0x_101x_x0_x_x0 : new_state = 7\'b0000100;\r
+\t\t// PTE Request ICACHE , IO access with WRITE is stored - parallel DRAM access possible\r
+\t\t  13\'b0x_xx_xxxx_x0_1_00 : new_state = 7\'b0101010;\t// no access\r
+\t\t  13\'b10_0x_1101_x0_1_x0 : new_state = 7\'b0101010;\t// if successful READ a PTE access can happen in parallel\r
+\t\t// DMA access. Attention : no IO-Write access in background and no ICACHE PTE access !\r
+\t\t  13\'b0x_x0_xxxx_xx_0_10 : new_state = 7\'b1000000;\t// DMA access is started\r
+\t\t  default \t\t\t\t : new_state = 7\'b0;\r
+\t\tendcase\r
+\t\t\r
+\tassign IO_ACC   = new_state[0];\t// to load registers for data, addr und BE, signal one pulse\r
+\tassign dram_go  = new_state[1] | rd_level2 ;\r
+\tassign wr_dram  = new_state[2];\t// pulse only\r
+\tassign pte_go   = new_state[3];\r
+\tassign do_ca_rd = new_state[4];\r
+\tassign do_ic_p\t= new_state[5];\r
+\tassign dma_go\t= new_state[6];\r
+\r
+\t// ZTEST logic is for the special case when a write access is crossing page boundaries\r
+\t\r
+\tassign do_zt = ZTEST & ~icp_acc;\r
+\t\r
+\t// 0 is pass , 1 is blocked. RWVAL[0] is 1 if WRVAL. Level 1 can only be blocked, otherwise ABORT or Level 2 is following.\r
+\talways @(posedge BCLK) if (mem_done) rwv_bit <= level2 ? ~(cap_dat[2] & (~RWVAL[0] | cap_dat[1])) : 1\'b1;\r
+\t\r
+\tassign RWVFLAG = VIRTUELL & rwv_bit;\r
+\t\r
+\tassign zt_ok = mem_done & (RWVAL[1] ? (~cap_dat[2] | (RWVAL[0] & ~cap_dat[1]) | level2)\t// Level 2 always ok\r
+\t\t\t\t\t\t\t\t\t\t: (cap_dat[0] & ~prot_i & level2) );\t// ""normal"" access\r
+\r
+\t// PTE access logic, normal state machine\r
+\t// Updates to the PTEs are normal WRITE request to DRAM, therefore no MDONE at Write\r
+\t\r
+\tassign modi  = ~CAPDAT[8] & WRITE & write_ok & ~icp_acc;\t// is ""1"" if the Modified Bit must be set\r
+\tassign refer = CAPDAT[7] | do_zt;\t// Assumption ""R"" Bit is set if RDVAL/WRVAL and page border test\r
+\tassign valid = (do_zt & RWVAL[1]) ? (cap_dat[2] & (cap_dat[1] | ~RWVAL[0]) & cap_dat[0] & level1)\r
+\t\t\t\t\t\t\t\t\t  : (cap_dat[0] & ~prot_i);\r
+\t\r
+\talways @(posedge BCLK) mem_done <= MDONE & pte_acc;\r
+\t\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) pstate <= 3\'h0;\r
+\t\t  else\r
+\t\t\tcasex ({pte_go,mem_done,valid,refer,modi,pte_run_wr,pstate})\r
+\t\t\t  9\'b0x_xxxx_000 : pstate <= 3\'d0;\t// nothing to do\r
+\t\t\t  9\'b1x_xxxx_000 : pstate <= 3\'d4;\t// start\r
+\t\t\t  9\'bx0_xxxx_100 : pstate <= 3\'d4;\t// wait for Level 1\r
+\t\t\t  9\'bx1_0xxx_100 : pstate <= 3\'d0;\t// THAT\'S ABORT ! \r
+\t\t\t  9\'bx1_11xx_100 : pstate <= 3\'d6;\t// PTE Level 1 was referenced , next is Level 2\r
+\t\t\t  9\'bx1_10xx_100 : pstate <= 3\'d5;\t// for writing of modified Level 1 : R=1\r
+\t\t\t  9\'bxx_xxx0_101 : pstate <= 3\'d5;\t// write must wait\r
+\t\t\t  9\'bxx_xxx1_101 : pstate <= 3\'d6;\t// one wait cycle\r
+\t\t\t  9\'bx0_xxxx_110 : pstate <= 3\'d6;\t// wait for Level 2\r
+\t\t\t  9\'bx1_0xxx_110 : pstate <= 3\'d0;\t// THAT\'S ABORT !\r
+\t\t\t  9\'bx1_10xx_110 : pstate <= 3\'d7;\t// Update neccesary : R=0\r
+\t\t\t  9\'bx1_110x_110 : pstate <= 3\'d0;\t// all ok - end\r
+\t\t\t  9\'bx1_111x_110 : pstate <= 3\'d7;\t// Update neccesary : M=0\r
+\t\t\t  9\'bxx_xxx0_111 : pstate <= 3\'d7;\t// write must wait\r
+\t\t\t  9\'bxx_xxx1_111 : pstate <= 3\'d0;\t// continues to end of DRAM write\r
+\t\t\t  default\t     : pstate <= 3\'d0;\r
+\t\t\tendcase\r
+\t\t\t\r
+\tassign pte_acc =  pstate[2];\r
+\tassign level1  = ~pstate[1];\r
+\tassign level2  =  pstate[1];\r
+\t\r
+\tassign valid_a = (ZTEST & RWVAL[1]) ? (cap_dat[2] & (cap_dat[1] | ~RWVAL[0]) & ~cap_dat[0] & level1)\r
+\t\t\t\t\t\t\t\t\t\t: ~cap_dat[0];\t// not do_zt because of icp_acc in ABORT\r
+\r
+\tassign ABORT   =   mem_done & valid_a & ~icp_acc;\r
+\tassign PROTECT = ((mem_done & prot_i  & ~icp_acc) | PROT_ERROR) & ~(ZTEST & RWVAL[1]);\t// no Protection-Error at RDVAL/WRVAL\r
+\r
+\tassign IACC_STAT[1] = mem_done & ~cap_dat[0] & icp_acc;\r
+\tassign IACC_STAT[2] = level1;\r
+\tassign IACC_STAT[3] = mem_done & prot_i & icp_acc;\r
+\r
+\tassign ABO_LEVEL1 = level1;\t// is stored in case of ABORT in ADDR_UNIT\r
+\t\r
+\tassign rd_level2 = (pstate == 3\'d5) | (mem_done & (pstate == 3\'d4) & refer & valid);\r
+\r
+\tassign WR_MRAM   = mem_done &  (pstate == 3\'d6) & valid & ~icp_acc & ~ZTEST;\r
+\tassign wr_icmram = mem_done &  (pstate == 3\'d6) & valid &  icp_acc;\r
+\t\r
+\t// Signals to the Instruction Cache\r
+\t// pte_acc combined with icp_acc for STATISTIK.\r
+\tassign IC_SIGS = {(pte_acc & icp_acc),wr_icmram};\r
+\t\r
+\tassign PTE_MUX = pte_go | (pte_acc & ~pstate[1]);\r
+\r
+\tassign pte_puls = mem_done & pte_acc & ~pstate[1];\r
+\tassign PTE_STAT = {(pte_puls & icp_acc),(pte_puls & ~icp_acc)};\t// only for statistic\r
+\t\r
+\tassign PD_MUX =  ((pstate == 3\'d4) & mem_done & valid & ~refer)\t\t// switch data-MUX, write level 1 too\r
+\t\t\t\t   | ((pstate == 3\'d6) & mem_done & valid & (~refer | modi))\t// write level 2\r
+\t\t\t\t   | (((pstate == 3\'d5) | (pstate == 3\'d7)) & ~pte_run_wr);\r
+\r
+\tassign pte_wr_sig = ENWR & PD_MUX;\r
+\t\r
+\talways @(posedge BCLK) pte_run_wr <= pte_wr_sig;\t// Ok-Signal for pstate State-machine\r
+\t\r
+\tassign PKEEP = (pstate == 3\'d6) | ((pstate == 3\'d7) & ~pte_run_wr);\t// keep the DRAM address\r
+\t\r
+\t// If there is a PTE still in the data cache it must be deleted. If MMU Bits are set by the pte engine a following\r
+\t// READ would deliver wrong data if cache hit. Therefore access of the Tags.\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) ko_state <= 3\'b000;\r
+\t\t  else\r
+\t\t\tcasex ({kostart,ko_state})\r
+\t\t\t  4\'b0_000 : ko_state <= 3\'b000;\r
+\t\t\t  4\'b1_000 : ko_state <= 3\'b110;\r
+\t\t\t  4\'bx_110 : ko_state <= 3\'b111;\r
+\t\t\t  4\'bx_111 : ko_state <= 3\'b100;\r
+\t\t\t  4\'bx_100 : ko_state <= 3\'b000;\r
+\t\t\t  default  : ko_state <= 3\'b000;\r
+\t\t\tendcase\r
+\t\t\t\r
+\tassign kostart = pte_go | rd_level2;\r
+\t\r
+\t// ko_state[2] suppresses ACC_OK at READ\r
+\tassign run_dc = (~ko_state[2] | QWATWO) & ~dma_run;\t// Bugfix of 7.10.2015\r
+\tassign KOMUX  =   ko_state[1] \t\t\t|  DMA_MUX;\r
+\tassign KDET   =   ko_state[0] \t\t\t|  dma_kdet;\r
+\t  \r
+\tassign HIT_ALL = MMU_HIT & CA_HIT & run_dc & ~pte_acc;\t// for Update ""Last-Set"" , MMU_HIT contains ZUGRIFF\r
+\t\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) card_flag <= 1\'b0;\r
+\t\t\telse card_flag <= (do_ca_rd & ~rd_rdy) | (card_flag & ~MDONE);\r
+\t\r
+\tassign CUPDATE = card_flag & USE_CA & MDONE;\r
+\r
+\talways @(posedge BCLK) rd_rdy <= card_flag & MDONE;\r
+\t\r
+\t// The cache RAM can not provide fast enough the data after an Update. In this case a secondary data path is activated\r
+\tassign AUX_DAT = rd_rdy;\r
+\t\r
+\t// DRAM interface :\r
+\r
+\talways @(posedge BCLK)\t\t\t\tDRAM_WR  <= wr_dram | pte_wr_sig; // pulse\r
+\talways @(posedge BCLK) if (dram_go) DRAM_ACC <= 1\'b1;\r
+\t\t\t\t\t\t\t else\r
+\t\t\t\t\t\t\t\tDRAM_ACC <= DRAM_ACC & ~MDONE & BRESET;\r
+\t// IO interface :\r
+\t\r
+\talways @(posedge BCLK)\r
+\t  begin\r
+\t\tif (IO_ACC) IO_RD <= READ;  else IO_RD <= IO_RD & ~IO_READY & BRESET;\r
+\t\tif (IO_ACC) IO_WR <= WRITE; else IO_WR <= IO_WR & ~IO_READY & BRESET;\r
+\t  end\r
+\t  \r
+\tassign io_busy = IO_RD | IO_WR | rd_done;\t// access is gone in next clock cycle, therefore blocked with ""rd_done""\r
+\t\r
+\talways @(posedge BCLK) rd_done <= IO_RD & IO_READY;\t// For READ one clock later 'b""for data to come through\r
+\t\r
+\tassign dma = ICTODC[2];\t// external request HOLD after FF in ICACHE\r
+\t\r
+\talways @(posedge BCLK) dma_run <= (dma_go | (dma_run & dma)) & BRESET;\t// stops the data access until HOLD becomes inactive\r
+\t\r
+\tassign HLDA = ~(ICTODC[1] & dma_run);\t// Signal for system that the CPU has stopped accesses\r
+\t\r
+\talways @(posedge BCLK) dma_kdet <= FILLRAM;\r
+\tassign DMA_MUX = FILLRAM | dma_kdet;\r
+\t\r
+\t// global feedback to ADDR_UNIT, early feedback to Op-Dec : you can continue\r
+\t\r
+\tassign ACC_OK = ZTEST ? (~VIRTUELL | zt_ok)\r
+\t\t\t\t\t\t  : (IO_SPACE ? ((IO_ACC & WRITE) | rd_done) : (wr_dram | (READ & MMU_HIT & rd_ende & run_dc)) );\r
+\t\t\t\t\t\t  \r
+\t// PTB1 and PTB0\r
+\t\r
+\talways @(posedge BCLK) if (PTB_WR && !PTB_SEL) ptb0 <= CPU_OUT[27:12];\r
+\talways @(posedge BCLK) if (PTB_WR &&  PTB_SEL) ptb1 <= CPU_OUT[27:12];\r
+\t\r
+\talways @(posedge BCLK) NEW_PTB <= PTB_WR;\t\t\t// to MMU Update Block\r
+\talways @(posedge BCLK) if (PTB_WR) PTB_ONE <= PTB_SEL;\r
+\t\r
+\tassign ptb10 = SEL_PTB1 ? ptb1 : ptb0;\r
+\t\r
+\t// Address multiplex between ICACHE=1 and DCACHE=0 :\r
+\talways @(posedge BCLK) if (pte_go) icp_acc <= do_ic_p;\r
+\t\t\t\t\r
+\tassign pte_sel = pte_go ? do_ic_p : icp_acc;\r
+\t\r
+\tassign virtual_adr = pte_sel ? IC_VA : VADR_R;\r
+\t\r
+\t// The 2 Address-LSB's : no full access : USE_CA = 0\t\r
+\tassign PTE_ADR = rd_level2 ? {CAPDAT[27:12],virtual_adr[21:12],2'b00} : {ptb10,virtual_adr[31:22],2'b00};\r
+\t\r
+\t// PTE_DAT[8] is used for update of MMU_RAM.\r
+\tassign pte_dat_8 = (level2 & WRITE & write_ok & ~icp_acc) | CAPDAT[8];\r
+\talways @(posedge BCLK) pte_modi = pte_dat_8;\r
+\tassign PTE_DAT = {4'h3,CAPDAT[15:9],pte_modi,1'b1,CAPDAT[6:0]};\t// the top 4 bits are Byte-Enable\r
+\t\r
+\t// The data for the MMU-RAM : 24 Bits , [6]=Cache Inhibit\r
+\tassign MMU_DIN = {pl_dat,pte_dat_8,CAPDAT[6],CAPDAT[31:12]};\r
+\t\r
+\t// Protection field\r
+\t\r
+\talways @(posedge BCLK) if (mem_done && (pstate[2:0] == 3'd4)) prot_level1 <= cap_dat[2:1];\r
+\r
+\talways @(prot_level1 or cap_dat)\t\r
+\t\tcasex ({prot_level1,cap_dat[2]})\r
+\t\t  3'b11_x : pl_dat = cap_dat[2:1];\r
+\t\t  3'b10_1 : pl_dat = 2'b10;\r
+\t\t  3'b10_0 : pl_dat = cap_dat[2:1];\r
+\t\t  3'b01_1 : pl_dat = 2'b01;\r
+\t\t  3'b01_0 : pl_dat = cap_dat[2:1];\r
+\t\t  3'b00_x : pl_dat = 2'b00;\r
+\t\tendcase\r
+\t\t\r
+\talways @(USER or pl_dat)\t// is used if no PTE update is neccesary for M-Bit if writing is not allowed\r
+\t\tcasex ({USER,pl_dat})\r
+\t\t  3'b1_11 : write_ok = 1'b1;\r
+\t\t  3'b0_1x : write_ok = 1'b1;\r
+\t\t  3'b0_01 : write_ok = 1'b1;\r
+\t\t  default : write_ok = 1'b0;\r
+\t\tendcase\r
+\t\t\r
+\tassign acc_level = level2 ? pl_dat : cap_dat[2:1];\r
+\tassign user_ptw = icp_acc ? ICTODC[3] : USER;\r
+\tassign wr_ptw = ~icp_acc & (WRITE | RMW | (ZTEST & ~RWVAL[1]));\t// only data cache can write\r
+\t\r
+\talways @(acc_level or user_ptw or wr_ptw)\r
+\t\tcase (acc_level)\r
+\t\t\t2'b00 : prot_i = user_ptw | wr_ptw;\r
+\t\t\t2'b01 : prot_i = user_ptw;\r
+\t\t\t2'b10 : prot_i = user_ptw & wr_ptw;\r
+\t\t\t2'b11 : prot_i = 1'b0;\r
+\t\tendcase\r
+\t\t\r
+endmodule\r
+\r
+"
+"//**************************************************************************
+//    hp_bytequad.v - wrapper for 4 FIFOs in the host to parasite direction.
+//   
+//    COPYRIGHT 2010 Richard Evans, Ed Spittles
+// 
+//    This file is part of tube - an Acorn Tube ULA compatible system.
+//   
+//    tube is free software: you can redistribute it and/or modify
+//    it under the terms of the GNU Lesser General Public License as published by
+//    the Free Software Foundation, either version 3 of the License, or
+//    (at your option) any later version.
+//
+//    tube is distributed in the hope that it will be useful,
+//    but WITHOUT ANY WARRANTY; without even the implied warranty of
+//    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//    GNU Lesser General Public License for more details.
+//
+//    You should have received a copy of the GNU Lesser General Public License
+//    along with tube.  If not, see <http://www.gnu.org/licenses/>.
+//
+// ============================================================================
+`timescale 1ns / 1ns
+
+module hp_bytequad (
+                  input h_rst_b,
+                  input h_we_b,
+                  input [3:0] h_selectData,
+                  input h_phi2,
+                  input [7:0] h_data,                  
+                  input [3:0] p_selectData,
+                  input p_phi2,
+                  input p_rdnw,
+                  input one_byte_mode,
+                  output [7:0] p_data,
+                  output [3:0] p_data_available,
+                  output p_r3_two_bytes_available,
+                  output [3:0] h_full
+                  );
+
+   // Declare registers and wires
+   reg [7:0]  p_datamux_r;        
+   wire [3:0] h_full_pre_w;
+   wire [7:0] fifo0_w,
+              fifo1_w,
+              fifo2_w,
+              fifo3_w;   
+
+   
+   // assign primary IOs
+   assign p_data = p_datamux_r;   
+   assign h_full = h_full_pre_w;
+
+   // Combinatorial code for the data output
+   always @ (fifo0_w or
+             fifo1_w or
+             fifo2_w or
+             fifo3_w or
+             p_selectData
+             )
+     casex (p_selectData)
+       4'bxxx1: p_datamux_r = fifo0_w;
+       4'bxx1x: p_datamux_r = fifo1_w;
+       4'bx1xx: p_datamux_r = fifo2_w;
+       4'b1xxx: p_datamux_r = fifo3_w;
+       default: p_datamux_r = 8'bx;
+     endcase // case p_selectData
+   
+
+   // module instances
+   hp_byte    reg1 (
+                    .h_rst_b(h_rst_b),
+                    .h_we_b(h_we_b),
+                    .h_selectData(h_selectData[0]),
+                    .h_phi2(h_phi2),
+                    .h_data(h_data),
+                    .p_selectData(p_selectData[0]),
+                    .p_phi2(p_phi2),
+                    .p_rdnw(p_rdnw),
+                    .p_data(fifo0_w),
+                    .p_data_available(p_data_available[0]),
+                    .h_full(h_full_pre_w[0])
+                    );
+   
+   hp_byte    reg2 (
+                    .h_rst_b(h_rst_b),
+                    .h_we_b(h_we_b),
+                    .h_selectData(h_selectData[1]),
+                    .h_phi2(h_phi2),
+                    .h_data(h_data),
+                    .p_selectData(p_selectData[1]),
+                    .p_phi2(p_phi2),
+                    .p_rdnw(p_rdnw),
+                    .p_data(fifo1_w),
+                    .p_data_available(p_data_available[1]),
+                    .h_full(h_full_pre_w[1])
+                    );
+
+   hp_reg3 reg3 (
+                 .h_rst_b(h_rst_b),
+                 .h_we_b(h_we_b),
+                 .h_selectData( h_selectData[2]),
+                 .h_phi2(h_phi2),
+                 .h_data( h_data ),                 
+                 .p_selectData( p_selectData[2]),
+                 .p_phi2(p_phi2),
+                 .p_rdnw(p_rdnw), 
+                 .one_byte_mode(one_byte_mode),
+                 .p_data(fifo2_w),
+                 .p_data_available(p_data_available[2]),
+                 .p_two_bytes_available( p_r3_two_bytes_available),
+                 .h_full(h_full_pre_w[2])
+                 );
+
+   hp_byte    reg4 (
+                    .h_rst_b(h_rst_b),
+                    .h_we_b(h_we_b),
+                    .h_selectData(h_selectData[3]),
+                    .h_phi2(h_phi2),
+                    .h_data(h_data),
+                    .p_selectData(p_selectData[3]),
+                    .p_phi2(p_phi2),
+                    .p_rdnw(p_rdnw),
+                    .p_data(fifo3_w),
+                    .p_data_available(p_data_available[3]),
+                    .h_full(h_full_pre_w[3])
+                    );
+
+   
+endmodule // hp_byte
+
+   "
+"module ICAP_reboot (
+  input        fastclk,
+  input [3:0]  sw,
+  output [8:1] test
+  );
+
+   ICAP_core instance_core (
+      .fastclk(fastclk),
+      .design_num({1'b0, sw}),
+      .reconfigure(1'b1),
+      .powerup(1'b1),
+      .sw_in(sw),
+      .sw_out(),
+      .pwr_out(),
+      .initialized(),
+      .test(test)
+      );
+           
+endmodule
+"
+"/*
+ *  Bitwise 8 and 16 bit shifter and rotator for Zet
+ *  Copyright (C) 2008-2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+module zet_shrot (
+    input  [15:0] x,
+    input  [ 7:0] y,
+    output [15:0] out,
+    input  [ 2:0] func,  // 0: rol, 1: ror, 2: rcl, 3: rcr,
+                         // 4: shl/sal, 5: shr, 6: sar
+    input         word_op,
+    input         cfi,
+    input         ofi,
+    output        cfo,
+    output        ofo
+  );
+
+  // Net declarations
+  wire [4:0] ror16;
+  wire [4:0] rol16;
+  wire [4:0] rcr16;
+  wire [4:0] rcl16;
+  wire [4:0] rot16;
+
+  wire [15:0] sal;
+  wire [15:0] sar;
+  wire [15:0] shr;
+  wire [15:0] sal16;
+  wire [15:0] sar16;
+  wire [15:0] shr16;
+
+  wire [7:0] sal8;
+  wire [7:0] sar8;
+  wire [7:0] shr8;
+
+  wire [3:0] ror8;
+  wire [3:0] rol8;
+  wire [3:0] rcr8;
+  wire [3:0] rcl8;
+  wire [3:0] rot8;
+
+  wire [ 7:0] outr8;
+  wire [15:0] outr16;
+  wire [15:0] rot;
+
+  wire cor8;
+  wire cor16;
+  wire unchanged;
+
+  wire ofo_sal;
+  wire ofo_sar;
+  wire ofo_shr;
+  wire cfo_sal;
+  wire cfo_sal8;
+  wire cfo_sal16;
+  wire cfo_sar;
+  wire cfo_sar8;
+  wire cfo_sar16;
+  wire cfo_shr;
+  wire cfo_shr8;
+  wire cfo_shr16;
+
+  wire ofor;
+  wire cfor;
+
+  // Module instantiation
+  zet_rxr8 rxr8 (
+    .x  (x[7:0]),
+    .ci (cfi),
+    .y  (rot8),
+    .e  (func[1]),
+    .w  (outr8),
+    .co (cor8)
+  );
+
+  zet_rxr16 rxr16 (
+    .x  (x),
+    .ci (cfi),
+    .y  (rot16),
+    .e  (func[1]),
+    .w  (outr16),
+    .co (cor16)
+  );
+
+  // Continous assignments
+  assign unchanged = word_op ? (y[4:0]==8'b0)
+                             : (y[3:0]==4'b0);
+
+  // rotates
+  assign ror16 = { 1'b0, y[3:0] };
+  assign rol16 = { 1'b0, -y[3:0] };
+  assign ror8  = { 1'b0, y[2:0] };
+  assign rol8  = { 1'b0, -y[2:0] };
+
+  assign rcr16 = (y[4:0] <= 5'd16) ? y[4:0] : { 1'b0, y[3:0] - 4'b1 };
+  assign rcl16 = (y[4:0] <= 5'd17) ? 5'd17 - y[4:0] : 5'd2 - y[4:0];
+  assign rcr8  = y[3:0] <= 4'd8 ? y[3:0] : { 1'b0, y[2:0] - 3'b1 };
+  assign rcl8  = y[3:0] <= 4'd9 ? 4'd9 - y[3:0] : 4'd2 - y[3:0];
+
+  assign rot8 = func[1] ? (func[0] ? rcr8 : rcl8 )
+                        : (func[0] ? ror8 : rol8 );
+  assign rot16 = func[1] ? (func[0] ? rcr16 : rcl16 )
+                         : (func[0] ? ror16 : rol16 );
+
+  assign rot = word_op ? outr16 : { x[15:8], outr8 };
+
+  // shifts
+  assign { cfo_sal16, sal16 } = x << y;
+  assign { sar16, cfo_sar16 } = (y > 5'd16) ? 17'h1ffff
+    : (({x,1'b0} >> y) | (x[15] ? (17'h1ffff << (17 - y))
+                                     : 17'h0));
+  assign { shr16, cfo_shr16 } = ({x,1'b0} >> y);
+
+  assign { cfo_sal8, sal8 } = x[7:0] << y;
+  assign { sar8, cfo_sar8 } = (y > 5'd8) ? 9'h1ff
+    : (({x[7:0],1'b0} >> y) | (x[7] ? (9'h1ff << (9 - y))
+                                         : 9'h0));
+  assign { shr8, cfo_shr8 } = ({x[7:0],1'b0} >> y);
+
+  assign sal     = word_op ? sal16 : { 8'd0, sal8 };
+  assign shr     = word_op ? shr16 : { 8'd0, shr8 };
+  assign sar     = word_op ? sar16 : { {8{sar8[7]}}, sar8 };
+
+  // overflows
+  assign ofor = func[0] ? // right
+                  (word_op ? out[15]^out[14] : out[7]^out[6])
+              : // left
+                  (word_op ? cfo^out[15] : cfo^out[7]);
+
+  assign ofo_sal = word_op ? (out[15] != cfo) : (out[7] != cfo);
+  assign ofo_sar = 1'b0;
+  assign ofo_shr = word_op ? x[15] : x[7];
+
+  assign ofo = unchanged ? ofi
+             : (func[2] ? (func[1] ? ofo_sar : (func[0] ? ofo_shr : ofo_sal))
+                        : ofor);
+
+  // carries
+  assign cfor = func[1] ? (word_op ? cor16 : cor8)
+                        : (func[0] ? (word_op ? out[15] : out[7])
+                                   : out[0]);
+
+  assign cfo_sal = word_op ? cfo_sal16 : cfo_sal8;
+  assign cfo_shr = word_op ? cfo_shr16 : cfo_shr8;
+  assign cfo_sar = word_op ? cfo_sar16 : cfo_sar8;
+
+  assign cfo = unchanged ? cfi
+    : (func[2] ? (func[1] ? cfo_sar
+                          : (func[0] ? cfo_shr : cfo_sal))
+                : cfor);
+
+  // output
+  assign out = func[2] ? (func[1] ? sar : (func[0] ? shr : sal)) : rot;
+endmodule
+"
+"// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+// This file is part of the M32632 project\r
+// http://opencores.org/project,m32632\r
+//\r
+// Filename: example_mods.v\r
+// Version:  1.0\r
+// Date:     30 May 2015\r
+//\r
+// Copyright (C) 2015 Udo Moeller\r
+// \r
+// This source file may be used and distributed without \r
+// restriction provided that this copyright statement is not \r
+// removed from the file and that any derivative work contains \r
+// the original copyright notice and the associated disclaimer.\r
+// \r
+// This source file is free software; you can redistribute it \r
+// and/or modify it under the terms of the GNU Lesser General \r
+// Public License as published by the Free Software Foundation;\r
+// either version 2.1 of the License, or (at your option) any \r
+// later version. \r
+// \r
+// This source is distributed in the hope that it will be \r
+// useful, but WITHOUT ANY WARRANTY; without even the implied \r
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR \r
+// PURPOSE. See the GNU Lesser General Public License for more \r
+// details. \r
+// \r
+// You should have received a copy of the GNU Lesser General \r
+// Public License along with this source; if not, download it \r
+// from http://www.opencores.org/lgpl.shtml \r
+// \r
+// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\tModules contained in this file:\r
+//\t1. ex_io_bus_ctrl\tInput/Output Bus controller\r
+//\t2. ex_in_reg\t \tInput Register\r
+//\t3. ex_out_reg\t\tOutput Register\r
+//\t4. ex_boot_rom\t\tBoot ROM\r
+//\t5. ex_statcou\t\tStatistic Counters \r
+//\t6. ex_copro\t\t\tCoprocessor\r
+//\t7. ex_dram_emul\t\tDRAM Emulator\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t1. ex_io_bus_ctrl\tInput/Output Bus controller\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module ex_io_bus_ctrl( CLK, RESET_N, RST_N, IO_WR, IO_RD, IO_A, IO_BE, IO_Q, IO_READY,\r
+\t\t\t\t\t   W_OUT_REG, IN_DAT, BOOT_DAT, STAT_DAT, ENDRAM );\r
+\r
+input\t\t\tCLK;\r
+input\t\t\tRESET_N;\r
+input\t\t\tIO_WR,IO_RD;\r
+input  [31:28]\tIO_A;\r
+input\t [3:0]\tIO_BE;\r
+\r
+input\t[31:0]\tBOOT_DAT;\r
+input\t [7:0]\tIN_DAT;\r
+input\t[31:0]\tSTAT_DAT;\r
+\r
+output\treg\t[31:0]\tIO_Q;\r
+output\treg\t\tRST_N;\r
+output\treg\t\tENDRAM;\r
+output\t\t\tIO_READY;\r
+output\t\t\tW_OUT_REG;\r
+\r
+reg\t\t\t\trd_rdy;\r
+reg\t\t [3:0]\tinit_cou;\r
+\r
+\talways @(posedge CLK) rd_rdy <= IO_RD & ~rd_rdy;\r
+\t\r
+\tassign IO_READY = IO_WR | rd_rdy;\r
+\r
+\talways @(IO_A or BOOT_DAT or IN_DAT or STAT_DAT)\r
+\t  casex({IO_A})\r
+\t\t4\'b000x : IO_Q = BOOT_DAT;\t// Boot-ROM\r
+\t\t4\'b0010 : IO_Q = {24\'d0,IN_DAT};\r
+\t\t4\'b0011 : IO_Q = STAT_DAT;\r
+\t\tdefault : IO_Q = 32\'hxxxxxxxx;\r
+\t  endcase\r
+\t\r
+\tassign W_OUT_REG = IO_WR & (IO_A == 4\'h2) & IO_BE[0];\r
+\t\r
+\t// ++++++++++++++++++++++++++ RESET Signal ++++++++++++++++++++++++++\r
+\r
+\talways @(posedge CLK or negedge RESET_N)\r
+\t\tif (!RESET_N) init_cou <= 4\'h0;\r
+\t\t  else init_cou <= init_cou + 4\'h1;\r
+\t\t  \r
+\talways @(posedge CLK or negedge RESET_N)\r
+\t\tif (!RESET_N) RST_N <= 1\'b0;\r
+\t\t  else\r
+\t\t\tif (init_cou == 4\'hF) RST_N <= 1\'b1;\r
+\t\t\t\r
+\t// Reading from Boot ROM switches DRAM on! You must read program code - not data.\r
+\talways @(posedge CLK) ENDRAM <= (ENDRAM | (IO_RD & (IO_A == 4\'h1))) & RST_N;\r
+\r
+endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t2. ex_in_reg\t \tInput Register\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module ex_in_reg( CLK, IN_REG, IN_DAT);\r
+\r
+parameter\tin_width = 7;\r
+\r
+input\t\t\tCLK;\r
+input\t [in_width:0]\tIN_REG;\r
+\r
+output\t reg\t[in_width:0]\tIN_DAT;\r
+\r
+reg\t\t [in_width:0]\tmeta_reg;\r
+\r
+\talways @(posedge CLK)\r
+\t\tbegin\r
+\t\t\tmeta_reg <= IN_REG;\r
+\t\t\tIN_DAT   <= meta_reg;\r
+\t\tend\r
+\r
+endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t3. ex_out_reg\t\tOutput Register\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module ex_out_reg( CLK, W_OUT_REG, DIN, OUT_REG);\r
+\r
+parameter\tout_width = 7;\r
+\r
+input\t\t\tCLK;\r
+input\t\t\tW_OUT_REG;\r
+input\t[31:0]\tDIN;\r
+\r
+output\treg [out_width:0]\tOUT_REG;\r
+\r
+\talways @(posedge CLK) if (W_OUT_REG) OUT_REG <= DIN[out_width:0];\r
+\t\r
+endmodule\r
+\t\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t4. ex_boot_rom\t\tBoot ROM\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module ex_boot_rom( CLK, ADDR, DATA);\r
+\r
+input\t\t\tCLK;\r
+input\t [9:2]\tADDR;\r
+\r
+output\treg\t[31:0]\tDATA;\r
+\r
+reg\t\t[31:0]\tBOOT_ROM [0:255];\t// 1 kByte\r
+\r
+initial\r
+\tbegin\r
+\t\t$readmemh(""boot_rom.txt"", BOOT_ROM);\r
+\tend\r
+\t\r
+\talways @(posedge CLK) DATA <= BOOT_ROM[ADDR[9:2]];\t\r
+\r
+endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t5. ex_statcou\t\tStatistic Counters \r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module ex_statcou( CLK, RST_N, STATSIGS, ADDR, DATA);\r
+\r
+input\t\t\tCLK;\r
+input\t\t\tRST_N;\r
+input\t [7:0]\tSTATSIGS;\r
+input\t [2:0]\tADDR;\r
+\r
+output\t[31:0]\tDATA;\r
+\r
+integer \t\ti;\r
+\r
+reg\t\t[31:0]\tcounter\t[0:7];\r
+\r
+\talways @(posedge CLK or negedge RST_N)\r
+\t\tfor (i=0; i<=7; i=i+1)\r
+\t\t\tif (!RST_N) counter[i] <= 32\'d0;\r
+\t\t\t\telse counter[i] <= counter[i] + {31\'d0,STATSIGS[i]};\r
+\r
+\tassign DATA = counter[ADDR];\r
+\r
+endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t6. ex_copro\t\t\tCoprocessor\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module ex_copro( CLK, COP_GO, COP_OP, COP_INP, COP_DONE, COP_OUTP);\r
+\r
+input\t\t\tCLK;\r
+input\t\t\tCOP_GO;\r
+input\t[23:0]\tCOP_OP;\r
+input  [127:0]\tCOP_INP;\r
+\r
+output\treg\t\tCOP_DONE;\r
+output\treg\t[63:0]\tCOP_OUTP;\r
+\r
+\talways @(posedge CLK)\r
+\t\tCOP_OUTP <= COP_OP[8] ? {COP_INP[71:64],COP_INP[79:72],COP_INP[87:80],COP_INP[95:88],32\'d0}\r
+\t\t\t\t\t: {COP_INP[7:0],COP_INP[15:8],COP_INP[23:16],COP_INP[31:24],COP_INP[71:64],COP_INP[79:72],COP_INP[87:80],COP_INP[95:88]};\r
+\t\t\t\t\t\r
+\talways @(posedge CLK) COP_DONE <= COP_GO;\r
+\t\r
+endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t7. ex_dram_emul\t\tDRAM Emulator\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module ex_dram_emul ( MCLK, RST_N, IC_ACC, IDRAM_ADR, DC_ACC, DC_WR, DRAM_ADR, DRAM_DI,\r
+\t\t\t\t\t IC_MDONE, DC_MDONE, ENWR, WAMUX, WADDR, MEM_Q, IWCTRL, DWCTRL );\r
+\r
+input\t\t\tMCLK;\r
+input\t\t\tRST_N;\r
+input\t\t\tIC_ACC;\r
+input\t[27:0]\tIDRAM_ADR;\r
+input\t\t\tDC_ACC;\r
+input\t\t\tDC_WR;\r
+input\t[27:0]\tDRAM_ADR;\r
+input\t[35:0]\tDRAM_DI;\r
+\r
+output\treg\t\tIC_MDONE;\r
+output\treg\t\tDC_MDONE;\r
+output\t\t\tENWR;\r
+output\treg\t\tWAMUX;\r
+output\t[11:2]\tWADDR;\r
+output\treg  [2:0]\tIWCTRL;\r
+output\treg\t [2:0]\tDWCTRL;\r
+\r
+output\treg\t[31:0]\tMEM_Q;\r
+\r
+// +++++++++++++++++++ Memories ++++++++++++++++++++\r
+\r
+parameter addr_msb = 13;\t// total memory is 16 kBytes\r
+\r
+reg\t \t[31:0]\tEDRAM [0:2**(addr_msb-1)-1];\r
+reg\t [addr_msb+34:0]\tFIFO\t[0:15];\r
+\r
+reg\t [addr_msb+34:0]\tfifo_q;\r
+reg\t\t [1:0]\tstate;\r
+reg\t\t [1:0]\tnibble,lsb;\r
+reg\t [addr_msb:4]\taddr;\r
+reg\t\t \t\tuse_cache;\r
+reg\t\t\t\tselect;\r
+reg\t\t [3:0]\tw_poi,r_poi,r_zeiger;\r
+reg\t\t\t\twr_next;\r
+\r
+wire\t [7:0]\tdin_0,din_1,din_2,din_3;\r
+wire [addr_msb:2]\traddr;\r
+wire\t\t\tfrei;\r
+wire\t\t\tstart;\r
+wire\t\t\twr_req;\r
+wire\t\t\tca_req;\r
+wire\t\t\twrite;\r
+\r
+// +++++++++++++++++++++++++  Datapath  +++++++++++++++++++\r
+\r
+\talways @(negedge MCLK) if (DC_WR) FIFO[w_poi] <= {DRAM_ADR[addr_msb:2],DRAM_DI};\r
+\t\r
+\talways @(posedge MCLK or negedge RST_N)\r
+\t\tif (!RST_N) w_poi <= 4\'d0;\r
+\t\t\telse w_poi <= w_poi + {3\'d0,DC_WR};\r
+\r
+\talways @(posedge MCLK or negedge RST_N)\r
+\t\tif (!RST_N) r_poi <= 4\'d0;\r
+\t\t\telse r_poi <= r_poi + {3\'d0,write};\r
+\r
+\talways @(negedge MCLK or negedge RST_N)\r
+\t\tif (!RST_N) r_zeiger <= 4\'d0;\r
+\t\t\telse r_zeiger <= r_zeiger + {3\'d0,write};\r
+\r
+\talways @(posedge MCLK) fifo_q <= FIFO[r_zeiger];\r
+\t\r
+\talways @(negedge MCLK) MEM_Q <= EDRAM[raddr];\t// READ on falling edge\r
+\t\r
+\tassign din_0 = fifo_q[32] ? fifo_q[7:0]   : MEM_Q[7:0];\r
+\tassign din_1 = fifo_q[33] ? fifo_q[15:8]  : MEM_Q[15:8];\r
+\tassign din_2 = fifo_q[34] ? fifo_q[23:16] : MEM_Q[23:16];\r
+\tassign din_3 = fifo_q[35] ? fifo_q[31:24] : MEM_Q[31:24];\r
+\t\r
+\talways @(posedge MCLK) if (write) EDRAM[raddr] <= {din_3,din_2,din_1,din_0};\t// WRITE on rising edge\t\r
+\r
+// +++++++++++++++++++++++++  Controllogic  +++++++++++++++++++\r
+\r
+\tassign ca_req = DC_ACC | IC_ACC;\t// Cache Read Request\r
+\tassign wr_req = (w_poi != r_poi);\t// Write Request\r
+\t\r
+\tassign write = (wr_req & ~ca_req & frei) | wr_next;\r
+\t\r
+\talways @(posedge MCLK or negedge RST_N)\r
+\t\tif (!RST_N) wr_next <= 1\'b0;\r
+\t\t\telse wr_next <= write & (w_poi != (r_poi + 4\'d1));\r
+\t\r
+\talways @(posedge MCLK or negedge RST_N)\r
+\t\tif (!RST_N) state <= 2\'d0;\r
+\t\t  else\r
+\t\t    if (frei) state <= (ca_req & ~wr_next) ? 2\'b01 : 2\'d0;\r
+\t\t\t  else state <= state + 2\'b01;\r
+\t\t\t  \r
+\tassign frei = (state == 2\'d0);\r
+\t\r
+\tassign start = ca_req & frei & ~wr_next;\r
+\t\r
+\talways @(negedge MCLK)\r
+\t\tif (start)\r
+\t\t\tbegin\r
+\t\t\t\taddr\t   <= DC_ACC ? DRAM_ADR[addr_msb:4] : IDRAM_ADR[addr_msb:4];\r
+\t\t\t\tuse_cache  <= DC_ACC ? DRAM_ADR[1] : IDRAM_ADR[1];\r
+\t\t\t\tselect\t   <= DC_ACC;\r
+\t\t\tend\r
+\t\t\t\r
+\talways @(negedge MCLK)\r
+\t\tif (start) nibble <= DC_ACC ? {DRAM_ADR[3],~DRAM_ADR[2]} : {IDRAM_ADR[3],~IDRAM_ADR[2]};\r
+\t\t  else\r
+\t\t    if (state == 2\'b01) nibble <= {~nibble[1],1\'b0};\r
+\t\t\t  else\r
+\t\t\t\tif (state[1]) nibble <= {nibble[1],~nibble[0]};\r
+\r
+\tassign raddr = write ? fifo_q[addr_msb+34:36] : (start ? (DC_ACC ? DRAM_ADR[addr_msb:2] : IDRAM_ADR[addr_msb:2]) : {addr,nibble});\r
+\t\r
+\talways @(negedge MCLK) lsb <= raddr[3:2];\r
+\t\r
+\tassign ENWR = 1\'b1;\t// always active\r
+\t\r
+\talways @(posedge MCLK)\r
+\t\tbegin\r
+\t\t  WAMUX \t<= start | ~frei;\r
+\t\t  \r
+\t\t  DC_MDONE  <=  select & (state == 2\'b01);\r
+\t\t  DWCTRL[2] <=  select &  start;\r
+\t\t  DWCTRL[1] <=  select & (start | ~frei) & use_cache;\r
+\t\t  DWCTRL[0] <=  select & ~use_cache;\r
+\r
+\t\t  IC_MDONE  <= ~select & (state == 2\'b10);\t// must be late to cover all cases\r
+\t\t  IWCTRL[2] <= ~select &  start;\r
+\t\t  IWCTRL[1] <= ~select & (start | ~frei) & use_cache;\r
+\t\t  IWCTRL[0] <= ~select & ~use_cache;\r
+\t\tend\r
+\r
+\tassign WADDR = {addr[11:4],lsb};\r
+\t\r
+endmodule\r
+"
+"/*
+ *  Module for performing other ALU operations
+ *  Copyright (C) 2008-2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+module zet_othop (x, y, seg, off, iflags, func, word_op, out, oflags);
+  // IO ports
+  input [15:0] x, y, off, seg, iflags;
+  input [2:0] func;
+  input word_op;
+  output [19:0] out;
+  output [8:0] oflags;
+
+  // Net declarations
+  wire [15:0] deff, deff2, outf, clcm, setf, intf, strf;
+  wire [19:0] dcmp, dcmp2; 
+  wire dfi;
+
+  // Module instantiations
+  zet_mux8_16 mux8_16 (func, dcmp[15:0], dcmp2[15:0], deff, outf, clcm, setf, 
+                       intf, strf, out[15:0]);
+  assign out[19:16] = func ? dcmp2[19:16] : dcmp[19:16];
+
+  // Assignments
+  assign dcmp  = (seg << 4) + deff;
+  assign dcmp2 = (seg << 4) + deff2;
+  assign deff  = x + y + off;
+  assign deff2 = x + y + off + 16'd2;
+  assign outf  = y;
+  assign clcm  = y[2] ? (y[1] ? /* -1: clc */ {iflags[15:1], 1'b0} 
+                         : /* 4: cld */ {iflags[15:11], 1'b0, iflags[9:0]})
+                     : (y[1] ? /* 2: cli */ {iflags[15:10], 1'b0, iflags[8:0]}
+                       : /* 0: cmc */ {iflags[15:1], ~iflags[0]});
+  assign setf  = y[2] ? (y[1] ? /* -1: stc */ {iflags[15:1], 1'b1} 
+                         : /* 4: std */ {iflags[15:11], 1'b1, iflags[9:0]})
+                     : (y[1] ? /* 2: sti */ {iflags[15:10], 1'b1, iflags[8:0]}
+                       : /* 0: outf */ iflags);
+
+  assign intf = {iflags[15:10], 2'b0, iflags[7:0]};
+  assign dfi  = iflags[10];
+  assign strf = dfi ? (x - y) : (x + y);
+
+  assign oflags = word_op ? { out[11:6], out[4], out[2], out[0] }
+                           : { iflags[11:8], out[7:6], out[4], out[2], out[0] };
+endmodule
+"
+"/*
+ *  Next state calculation for fetch FSM
+ *  Copyright (C) 2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+module zet_nstate (
+    input [2:0] state,
+    input prefix,
+    input need_modrm,
+    input need_off,
+    input need_imm,
+    input end_seq,
+    input [5:0] ftype,
+    input of,
+    input next_in_opco,
+    input next_in_exec,
+    input block,
+    input div_exc,
+    input tflm,
+    input intr,
+    input iflm,
+    input nmir,
+    input iflss,
+    output [2:0] next_state
+  );
+
+  // Net declarations
+  parameter opcod_st = 3'h0;
+  parameter modrm_st = 3'h1;
+  parameter offse_st = 3'h2;
+  parameter immed_st = 3'h3;
+  parameter execu_st = 3'h4;
+  wire into, end_instr, end_into;
+  wire [2:0] n_state;
+  wire       intr_iflm;
+  wire       intrs_tni;
+
+  // Assignments
+  assign into = (ftype==6'b111_010);
+  assign end_into = into ? ~of : end_seq;
+  assign end_instr = !div_exc && !intrs_tni && end_into && !next_in_exec;
+  assign intr_iflm = intr & iflm;
+  assign intrs_tni = (tflm | nmir | intr_iflm) & iflss;
+
+  assign n_state = (state == opcod_st) ? (prefix ? opcod_st
+                         : (next_in_opco ? opcod_st
+                         : (need_modrm ? modrm_st
+                         : (need_off ? offse_st
+                         : (need_imm ? immed_st : execu_st)))))
+                     : (state == modrm_st) ? (need_off ? offse_st
+                                           : (need_imm ? immed_st : execu_st))
+                     : (state == offse_st) ? (need_imm ? immed_st : execu_st)
+                     : (state == immed_st) ? (execu_st)
+   /* state == execu_st */ : (end_instr ? opcod_st : execu_st);
+
+  assign next_state = block ? state : n_state;
+endmodule
+"
+"`define MICRO_DATA_WIDTH 50
+`define MICRO_ADDR_WIDTH 10
+
+`define MOVRRB\t10'b0000000000
+`define MOVRRW\t10'b0000000001
+`define MOVRMB\t10'b0000000010
+`define MOVRMW\t10'b0000000011
+`define MOVAMB\t10'b0000000100
+`define MOVAMW\t10'b0000000101
+`define MOVMRB\t10'b0000000110
+`define MOVMRW\t10'b0000000111
+`define MOVMAB\t10'b0000001000
+`define MOVMAW\t10'b0000001001
+`define MOVIRB\t10'b0000001010
+`define MOVIRW\t10'b0000001011
+`define MOVIMB\t10'b0000001100
+`define MOVIMW\t10'b0000001110
+`define PUSHR\t10'b0000010000
+`define PUSHM\t10'b0000010011
+`define PUSHI\t10'b0000010110
+`define LEAVE\t10'b0000011001
+`define ENTER\t10'b0000011100
+`define POPR\t10'b0000100000
+`define POPM\t10'b0000100011
+`define INIB\t10'b0000100110
+`define INIW\t10'b0000100111
+`define INRB\t10'b0000101000
+`define INRW\t10'b0000101001
+`define OUTIB\t10'b0000101010
+`define OUTIW\t10'b0000101011
+`define OUTRB\t10'b0000101100
+`define OUTRW\t10'b0000101101
+`define LAHF\t10'b0000101110
+`define SAHF\t10'b0000101111
+`define LDS\t10'b0000110000
+`define LEA\t10'b0000110011
+`define LES\t10'b0000110100
+`define PUSHF\t10'b0000110111
+`define POPF\t10'b0000111010
+`define XCHRRB\t10'b0000111101
+`define XCHRRW\t10'b0001000000
+`define XCHRMB\t10'b0001000011
+`define XCHRMW\t10'b0001000110
+`define XLAT\t10'b0001001001
+`define AAA\t10'b0001001011
+`define AAS\t10'b0001001100
+`define AAM\t10'b0001001101
+`define AAD\t10'b0001010000
+`define DAA\t10'b0001010101
+`define DAS\t10'b0001010110
+`define CBW\t10'b0001010111
+`define CWD\t10'b0001011000
+`define INCRB\t10'b0001011001
+`define INCRW\t10'b0001011010
+`define INCMB\t10'b0001011011
+`define INCMW\t10'b0001011110
+`define DECRB\t10'b0001100001
+`define DECRW\t10'b0001100010
+`define DECMB\t10'b0001100011
+`define DECMW\t10'b0001100110
+`define MULRB\t10'b0001101001
+`define MULRW\t10'b0001101100
+`define MULMB\t10'b0001101111
+`define MULMW\t10'b0001110011
+`define IMULRB\t10'b0001110111
+`define IMULRW\t10'b0001111010
+`define IMULMB\t10'b0001111101
+`define IMULMW\t10'b0010000001
+`define IMULIR\t10'b0010000101
+`define IMULIM\t10'b0010001000
+`define DIVRB\t10'b0010001100
+`define DIVRW\t10'b0010001111
+`define DIVMB\t10'b0010010010
+`define DIVMW\t10'b0010010110
+`define IDIVRB\t10'b0010011010
+`define IDIVRW\t10'b0010011101
+`define IDIVMB\t10'b0010100000
+`define IDIVMW\t10'b0010100100
+`define NEGRB\t10'b0010101000
+`define NEGRW\t10'b0010101001
+`define NEGMB\t10'b0010101010
+`define NEGMW\t10'b0010101101
+`define LOGRRB\t10'b0010110000
+`define LOGRRW\t10'b0010110001
+`define LOGRMB\t10'b0010110010
+`define LOGRMW\t10'b0010110101
+`define LOGMRB\t10'b0010111000
+`define LOGMRW\t10'b0010111010
+`define LOGIRB\t10'b0010111100
+`define LOGIRW\t10'b0010111101
+`define LOGIMB\t10'b0010111110
+`define LOGIMW\t10'b0011000001
+`define NOTRB\t10'b0011000100
+`define NOTRW\t10'b0011000101
+`define NOTMB\t10'b0011000110
+`define NOTMW\t10'b0011001001
+`define RSH1RB\t10'b0011001100
+`define RSH1RW\t10'b0011001101
+`define RSHCRB\t10'b0011001110
+`define RSHCRW\t10'b0011001111
+`define RSH1MB\t10'b0011010000
+`define RSH1MW\t10'b0011010011
+`define RSHCMB\t10'b0011010110
+`define RSHCMW\t10'b0011011001
+`define RSHIRB\t10'b0011011100
+`define RSHIRW\t10'b0011011101
+`define RSHIMB\t10'b0011011110
+`define RSHIMW\t10'b0011100001
+`define TSTRRB\t10'b0011100100
+`define TSTRRW\t10'b0011100101
+`define TSTMRB\t10'b0011100110
+`define TSTMRW\t10'b0011101000
+`define TSTIRB\t10'b0011101010
+`define TSTIRW\t10'b0011101011
+`define TSTIMB\t10'b0011101100
+`define TSTIMW\t10'b0011101110
+`define CALLN\t10'b0011110000
+`define CALLNR\t10'b0011110011
+`define CALLNM\t10'b0011110111
+`define CALLF\t10'b0011111011
+`define CALLFM\t10'b0100000000
+`define JCC\t10'b0100000110
+`define JCXZ\t10'b0100000111
+`define JMPI\t10'b0100001000
+`define JMPR\t10'b0100001001
+`define JMPM\t10'b0100001010
+`define LJMPI\t10'b0100001011
+`define LJMPM\t10'b0100001101
+`define LOOP\t10'b0100001111
+`define LOOPE\t10'b0100010001
+`define LOOPNE\t10'b0100010011
+`define RETN0\t10'b0100010101
+`define RETNV\t10'b0100010111
+`define RETF0\t10'b0100011010
+`define RETFV\t10'b0100011110
+`define CMPSB\t10'b0100100011
+`define CMPSW\t10'b0100101001
+`define CMPSBR\t10'b0100101111
+`define CMPSWR\t10'b0100110110
+`define LODSB\t10'b0100111101
+`define LODSW\t10'b0100111111
+`define LODSBR\t10'b0101000001
+`define LODSWR\t10'b0101000100
+`define MOVSB\t10'b0101000111
+`define MOVSW\t10'b0101001011
+`define MOVSBR\t10'b0101001111
+`define MOVSWR\t10'b0101010100
+`define SCASB\t10'b0101011001
+`define SCASW\t10'b0101011100
+`define SCASBR\t10'b0101011111
+`define SCASWR\t10'b0101100011
+`define STOSB\t10'b0101100111
+`define STOSW\t10'b0101101001
+`define STOSBR\t10'b0101101011
+`define STOSWR\t10'b0101101110
+`define INT3\t10'b0101110001
+`define INT\t10'b0101111100
+`define INTD\t10'b0110000111
+`define INTT\t10'b0110010000
+`define EINT\t10'b0110011010
+`define EINTP\t10'b0110100101
+`define INTO\t10'b0110110000
+`define IRET\t10'b0110111100
+`define NOP\t10'b0111000011
+`define CLC\t10'b0111000100
+`define CLD\t10'b0111000101
+`define CLI\t10'b0111000110
+`define CMC\t10'b0111000111
+`define STC\t10'b0111001000
+`define STD\t10'b0111001001
+`define STI\t10'b0111001010
+`define ESCRW\t10'b0111001011
+`define ESCMW\t10'b0111001100
+`define PUSHA\t10'b0111001110
+`define POPA\t10'b0111011011
+`define INVOP\t10'b0111100110
+`define INSB\t10'b0111110011
+`define INSW\t10'b0111110110
+`define INSBR\t10'b0111111001
+`define INSWR\t10'b0111111101
+`define OUTSB\t10'b1000000001
+`define OUTSW\t10'b1000000100
+`define OUTSBR\t10'b1000000111
+`define OUTSWR\t10'b1000001011
+"
+"//----------------------------------------------------------------------------
+// Wishbone Tube controller
+//----------------------------------------------------------------------------
+module wb_tube #(
+        parameter                  latency   = 0    // 0 .. 7
+) (
+        input                      clk,
+        input                      reset,
+        // Wishbone interface
+        input                      wb_stb_i,
+        input                      wb_cyc_i,
+        output reg                 wb_ack_o,
+        input                      wb_we_i,
+        input                [2:0] wb_adr_i,
+        input                [3:0] wb_sel_i,
+        input               [31:0] wb_dat_i,
+        output reg          [31:0] wb_dat_o,
+
+        // TUBE connection
+        output reg           [2:0] tube_adr,
+        inout                [7:0] tube_dat,
+        output reg                 tube_cs_n,    // Chip Select
+        output reg                 tube_rd_n,    // Read
+        output reg                 tube_wr_n     // Write
+);
+
+//----------------------------------------------------------------------------
+//
+//----------------------------------------------------------------------------
+
+// Wishbone handling
+wire wb_rd = wb_stb_i & wb_cyc_i & ~wb_we_i & ~wb_ack_o;
+wire wb_wr = wb_stb_i & wb_cyc_i &  wb_we_i & ~wb_ack_o;
+
+// Tri-State-Driver
+reg [7:0] wdat;
+reg       wdat_oe;
+
+assign tube_dat = wdat_oe ? wdat : 8'bz;
+
+
+// Latency countdown
+reg  [2:0] lcount;
+
+//----------------------------------------------------------------------------
+// State Machine
+//----------------------------------------------------------------------------
+parameter s_idle   = 0;
+parameter s_read   = 1;
+parameter s_write  = 2;
+
+reg [2:0] state;
+
+always @(posedge clk)
+begin
+        if (reset) begin
+                state    <= s_idle;
+                lcount   <= 0;
+                wb_ack_o <= 0;
+        end else begin
+                case (state)
+                s_idle: begin
+                        wb_ack_o <= 0;
+
+                        if (wb_rd) begin
+                                tube_cs_n  <=  0;
+                                tube_rd_n  <=  0;
+                                tube_wr_n  <=  1;
+                                tube_adr   <=  wb_adr_i;
+                                wdat_oe    <=  0;
+                                lcount     <=  latency;
+                                state      <=  s_read;
+                        end else if (wb_wr) begin
+                                tube_cs_n  <=  0;
+                                tube_rd_n  <=  1;
+                                tube_wr_n  <=  0;
+                                tube_adr   <=  wb_adr_i;
+                                wdat       <=  wb_dat_i[7:0];
+                                wdat_oe    <=  1;
+                                lcount     <=  latency;
+                                state      <=  s_write;
+                        end else begin
+                                tube_cs_n  <=  1;
+                                tube_rd_n  <=  1;
+                                tube_wr_n  <=  1;
+                                wdat_oe    <=  0;
+                        end
+                end
+                s_read: begin
+                        if (lcount != 0) begin
+                                lcount     <= lcount - 1;
+                        end else begin
+                                tube_cs_n  <=  1;
+                                tube_rd_n  <=  1;
+                                tube_wr_n  <=  1;
+                                wb_dat_o   <=  tube_dat;
+                                wb_ack_o   <=  1;
+                                state      <=  s_idle;
+                        end
+                end
+                s_write: begin
+                        if (lcount != 0) begin
+                                lcount     <= lcount - 1;
+                        end else begin
+                                tube_cs_n  <=  1;
+                                tube_rd_n  <=  1;
+                                tube_wr_n  <=  1;
+                                wb_ack_o   <=  1;       // XXX   We could acknoledge write  XXX
+                                state      <=  s_idle;  // XXX   requests 1 cycle ahead     XXX
+                        end
+                end
+                endcase
+        end
+end
+
+endmodule
+"
+"/*
+ *  Arithmetic Logic Unit for Zet
+ *  Copyright (C) 2008-2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+`timescale 1ns/10ps
+
+module zet_alu (
+    input  [31:0] x,
+    input  [15:0] y,
+    output [31:0] out,
+    input  [ 2:0] t,
+    input  [ 2:0] func,
+    input  [15:0] iflags,
+    output [ 8:0] oflags,
+    input         word_op,
+    input  [15:0] seg,
+    input  [15:0] off,
+    input         clk,
+    output        div_exc
+  );
+
+  // Net declarations
+  wire [15:0] add, log, rot;
+  wire [15:0] arl;
+  wire  [8:0] othflags;
+  wire [19:0] oth;
+  wire [31:0] cnv, mul;
+  wire af_add, af_cnv, af_arl;
+  wire cf_cnv, cf_add, cf_mul, cf_log, cf_arl, cf_rot;
+  wire of_cnv, of_add, of_mul, of_log, of_arl, of_rot;
+  wire ofi, sfi, zfi, afi, pfi, cfi;
+  wire ofo, sfo, zfo, afo, pfo, cfo;
+  wire flags_unchanged;
+  wire dexc;
+
+  // Module instances
+  zet_addsub addsub (x[15:0], y, add, func, word_op, cfi, cf_add, af_add, of_add);
+
+  zet_conv conv (
+    .x      (x[15:0]),
+    .func   (func),
+    .out    (cnv),
+    .iflags ({afi, cfi}),
+    .oflags ({af_cnv, of_cnv, cf_cnv})
+  );
+
+  zet_muldiv muldiv (
+    .x       (x),
+    .y       (y),
+    .o       (mul),
+    .f       (func),
+    .word_op (word_op),
+    .cfo     (cf_mul),
+    .ofo     (of_mul),
+    .clk     (clk),
+    .exc     (dexc)
+  );
+
+  zet_bitlog bitlog (
+    .x   (x[15:0]),
+    .o   (log),
+    .cfo (cf_log),
+    .ofo (of_log)
+  );
+
+  zet_arlog arlog (
+    .x       (x[15:0]),
+    .y       (y),
+    .f       (func),
+    .o       (arl),
+    .word_op (word_op),
+    .cfi     (cfi),
+    .cfo     (cf_arl),
+    .afo     (af_arl),
+    .ofo     (of_arl)
+  );
+
+  zet_shrot  shrot (
+    .x       (x[15:0]),
+    .y       (y[7:0]),
+    .out     (rot),
+    .func    (func),
+    .word_op (word_op),
+    .cfi     (cfi),
+    .ofi     (ofi),
+    .cfo     (cf_rot),
+    .ofo     (of_rot)
+  );
+
+  zet_othop  othop (x[15:0], y, seg, off, iflags, func, word_op, oth, othflags);
+
+  zet_mux8_16 m0(t, {8'd0, y[7:0]}, add, cnv[15:0],
+                 mul[15:0], log, arl, rot, oth[15:0], out[15:0]);
+  zet_mux8_16 m1(t, 16'd0, 16'd0, cnv[31:16], mul[31:16],
+                 16'd0, 16'd0, 16'd0, {12'b0,oth[19:16]}, out[31:16]);
+  zet_mux8_1  a1(t, 1'b0, cf_add, cf_cnv, cf_mul, cf_log, cf_arl, cf_rot, 1'b0, cfo);
+  zet_mux8_1  a2(t, 1'b0, af_add, af_cnv, 1'b0, 1'b0, af_arl, afi, 1'b0, afo);
+  zet_mux8_1  a3(t, 1'b0, of_add, of_cnv, of_mul, of_log, of_arl, of_rot, 1'b0, ofo);
+
+  // Flags
+  assign pfo = flags_unchanged ? pfi : ^~ out[7:0];
+  assign zfo = flags_unchanged ? zfi
+             : ((word_op && (t!=3'd2)) ? ~|out[15:0] : ~|out[7:0]);
+  assign sfo = flags_unchanged ? sfi
+             : ((word_op && (t!=3'd2)) ? out[15] : out[7]);
+
+  assign oflags = (t == 3'd7) ? othflags 
+                 : { ofo, iflags[10:8], sfo, zfo, afo, pfo, cfo };
+
+  assign ofi = iflags[11];
+  assign sfi = iflags[7];
+  assign zfi = iflags[6];
+  assign afi = iflags[4];
+  assign pfi = iflags[2];
+  assign cfi = iflags[0];
+
+  assign flags_unchanged = (t == 3'd4
+                         || t == 3'd6 && (!func[2] || func[2]&&y[4:0]==5'h0));
+
+  assign div_exc = func[1] && (t==3'd3) && dexc;
+
+endmodule
+"
+"/*
+ *  Copyright (c) 2008  Zeus Gomez Marmolejo <zeus@opencores.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+`timescale 1ns/10ps
+
+`include ""defines.v""
+
+module zet_regfile (
+    output [15:0] a,
+    output [15:0] b,
+    output [15:0] c,
+    output [15:0] cs,
+    output [15:0] ip,
+    input  [31:0] d,
+    output [15:0] s,
+
+    output reg [8:0] flags,
+
+    input         wr,
+    input         wrfl,
+    input         wrhi,
+    input         clk,
+    input         rst,
+    input  [ 3:0] addr_a,
+    input  [ 3:0] addr_b,
+    input  [ 3:0] addr_c,
+    input  [ 3:0] addr_d,
+    input  [ 1:0] addr_s,
+    input  [ 8:0] iflags,
+    input         word_op,
+    input         a_byte,
+    input         b_byte,
+    input         c_byte,
+    output        cx_zero,
+    input         wr_ip0
+  );
+
+  // Net declarations
+  reg [15:0] r[15:0];
+  wire [7:0] a8, b8, c8;
+  wire [3:0] addr_a_8;
+  wire [3:0] addr_b_8;
+  wire [3:0] addr_c_8;
+
+  // Assignments
+  assign addr_a_8 = { 2\'b00, addr_a[1:0] };
+  assign addr_b_8 = { 2\'b00, addr_b[1:0] };
+  assign addr_c_8 = { 2\'b00, addr_c[1:0] };
+
+  assign a = (a_byte & ~addr_a[3]) ? { {8{a8[7]}}, a8} : r[addr_a];
+  assign a8 = addr_a[2] ? r[addr_a_8][15:8] : r[addr_a][7:0];
+
+  assign b = (b_byte & ~addr_b[3]) ? { {8{b8[7]}}, b8} : r[addr_b];
+  assign b8 = addr_b[2] ? r[addr_b_8][15:8] : r[addr_b][7:0];
+
+  assign c = (c_byte & ~addr_c[3]) ? { {8{c8[7]}}, c8} : r[addr_c];
+  assign c8 = addr_c[2] ? r[addr_c_8][15:8] : r[addr_c][7:0];
+
+  assign s = r[{2\'b10,addr_s}];
+
+  assign cs = r[9];
+  assign cx_zero = (addr_d==4\'d1) ? (d==16\'d0) : (r[1]==16\'d0);
+
+  assign ip = r[15];
+
+  // Behaviour
+  always @(posedge clk)
+    if (rst) begin
+      r[0]  <= 16\'d0; r[1]  <= 16\'d0;
+      r[2]  <= 16\'d0; r[3]  <= 16\'d0;
+      r[4]  <= 16\'d0; r[5]  <= 16\'d0;
+      r[6]  <= 16\'d0; r[7]  <= 16\'d0;
+      r[8]  <= 16\'d0; r[9]  <= 16\'hf000;
+      r[10] <= 16\'d0; r[11] <= 16\'d0;
+      r[12] <= 16\'d0; r[13] <= 16\'d0;
+      r[14] <= 16\'d0; r[15] <= 16\'hfff0;
+      flags <= 9\'d0;
+    end else
+      begin
+        if (wr) begin
+          if (word_op | addr_d[3:2]==2\'b10)
+             r[addr_d] <= word_op ? d[15:0] : {{8{d[7]}},d[7:0]};
+          else if (addr_d[3]~^addr_d[2]) r[addr_d][7:0] <= d[7:0];
+          else r[{2\'b0,addr_d[1:0]}][15:8] <= d[7:0];
+        end
+        if (wrfl) flags <= iflags;
+        if (wrhi) r[4\'d2] <= d[31:16];
+        if (wr_ip0) r[14] <= ip;
+      end
+endmodule"
+"// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+// This file is part of the M32632 project\r
+// http://opencores.org/project,m32632\r
+//\r
+// Filename: REGISTERS.v\r
+// Version:  1.0\r
+// Date:     30 May 2015\r
+//\r
+// Copyright (C) 2015 Udo Moeller\r
+// \r
+// This source file may be used and distributed without \r
+// restriction provided that this copyright statement is not \r
+// removed from the file and that any derivative work contains \r
+// the original copyright notice and the associated disclaimer.\r
+// \r
+// This source file is free software; you can redistribute it \r
+// and/or modify it under the terms of the GNU Lesser General \r
+// Public License as published by the Free Software Foundation;\r
+// either version 2.1 of the License, or (at your option) any \r
+// later version. \r
+// \r
+// This source is distributed in the hope that it will be \r
+// useful, but WITHOUT ANY WARRANTY; without even the implied \r
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR \r
+// PURPOSE. See the GNU Lesser General Public License for more \r
+// details. \r
+// \r
+// You should have received a copy of the GNU Lesser General \r
+// Public License along with this source; if not, download it \r
+// from http://www.opencores.org/lgpl.shtml \r
+// \r
+// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\tModules contained in this file:\r
+//\t1. CONFIG_REGS\tConfiguration and Debug Registers\r
+//\t2. FP_STAT_REG\tFloating Point Status Register\r
+//\t3. REGISTER\t\tGeneral Purpose Registers\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t1. CONFIG_REGS\tConfiguration and Debug Registers\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module CONFIG_REGS ( BCLK, BRESET, WREN, LD_OUT, OPCODE, SRC1, WRADR, PC_ARCHI, USER, PCMATCH, DBG_HIT, READ,\r
+\t\t\t\t\t CFG, MCR, PTB_WR, PTB_SEL, IVAR, CINV, Y_INIT, DSR, DBG_TRAPS, DBG_IN );\r
+\r
+\tinput\t\t\tBCLK,BRESET;\r
+\tinput\t\t\tWREN,LD_OUT;\r
+\tinput\t [7:0]\tOPCODE;\r
+\tinput\t[31:0]\tSRC1;\r
+\tinput\t [5:0]\tWRADR;\r
+\tinput\t[31:0]\tPC_ARCHI;\r
+\tinput\t\t\tUSER;\r
+\tinput\t\t\tPCMATCH;\r
+\tinput\t\t\tDBG_HIT;\r
+\tinput\t\t\tREAD;\r
+\t\r
+\toutput\t[12:0]\tCFG;\r
+\toutput\t [3:0]\tMCR;\r
+\toutput\t\t\tPTB_WR;\r
+\toutput\t\t\tPTB_SEL;\r
+\toutput\t [1:0]\tIVAR;\r
+\toutput\t [3:0]\tCINV;\r
+\toutput\t\t\tY_INIT;\r
+\toutput\t [3:0]\tDSR;\r
+\toutput\t [2:0]\tDBG_TRAPS;\r
+\toutput\t[40:2]\tDBG_IN;\r
+\t\r
+\treg\t\t [3:0]\tMCR;\r
+\treg\t\t[12:0]\tCFG;\r
+\treg\t\t [1:0]\told_cfg;\r
+\treg\t\t\t\tPTB_WR,PTB_SEL;\r
+\treg\t\t\t\tivarreg;\r
+\treg\t\t [1:0]\tci_all,ci_line;\r
+\treg\t\t\t\tcheck_y;\r
+\r
+\twire\t\t\tld_cfg,ld_mcr,do_cinv;\r
+\twire\t\t\tinit_ic,init_dc;\r
+\twire\t\t\top_ok;\r
+\r
+\tassign op_ok = (OPCODE == 8\'h6A);\t// Special Opcode - for security reason\r
+\t\r
+\tassign ld_cfg  = op_ok & (WRADR == 6\'h1C)\t   & WREN;\r
+\tassign ld_mcr  = op_ok & (WRADR == 6\'d9)\t   & WREN;\r
+\tassign do_cinv = op_ok & (WRADR[5:4] == 2\'b11) & WREN;\r
+\t\r
+\t// PF is not implemented\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) CFG <= 13\'h0;\r
+\t\t\telse if (ld_cfg) CFG <= SRC1[12:0];\r
+\t\t\t\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) MCR <= 4\'h0;\r
+\t\t\telse if (ld_mcr) MCR <= SRC1[3:0];\r
+\r
+\talways @(posedge BCLK) ivarreg <= op_ok & (WRADR[5:1] == 5\'d7) & WREN;\t// IVAR0/1 = Reg. Nr. 14/15\r
+\tassign IVAR = {ivarreg,PTB_SEL};\r
+\t\r
+\talways @(posedge BCLK) PTB_WR  <= op_ok & (WRADR[5:1] == 5\'d6) & WREN;\t// PTB0/1 = Reg. Nr. 12/13\r
+\talways @(posedge BCLK) PTB_SEL <= WRADR[0];\r
+\t\r
+\t// The Cache content will be invalid if the Enable-Bit is set to 0\r
+\talways @(posedge BCLK) old_cfg <= {CFG[11],CFG[9]};\r
+\t\r
+\t// Cache Invalidate : the Flags are coming out of the Short-field which is otherwise used for Register selection\r
+\talways @(posedge BCLK) ci_all  <= do_cinv &  WRADR[2] ? WRADR[1:0] : 2\'b0;\t// clear all\r
+\talways @(posedge BCLK) ci_line <= do_cinv & ~WRADR[2] ? WRADR[1:0] : 2\'b0;\t// clear cache line\r
+\t\r
+\tassign init_ic = old_cfg[1] & (~CFG[11] | ci_all[1]);\r
+\tassign init_dc = old_cfg[0] & (~CFG[9]  | ci_all[0]);\r
+\t\r
+\tassign CINV = {init_ic,ci_line[1],init_dc,ci_line[0]};\r
+\t\r
+\t// Y_INIT is neccessary if nothing has changed and therefore no DC/IC_INIT is generated\r
+\talways @(posedge BCLK) check_y <= ld_cfg | do_cinv;\r
+\tassign Y_INIT = check_y & ~init_ic & ~init_dc;\t// goes to register ""old_init""\r
+\t\r
+\t// +++++++++++++  DEBUG Unit  +++++++++++++++\r
+\r
+\treg\t\t [3:0]\tDSR;\r
+\treg\t\t[12:0]\tdcr;\r
+\treg\t\t[31:0]\tbpc;\r
+\treg\t\t[31:2]\tcar;\r
+\t\r
+\twire\t\t\top_dbg,ld_dcr,ld_bpc,ld_dsr,ld_car;\r
+\twire\t\t\tenable;\r
+\t\r
+\tassign op_dbg = (OPCODE == 8\'h76);\r
+\t\r
+\tassign ld_dcr = op_dbg & (WRADR == 6\'h11) & WREN;\r
+\tassign ld_bpc = op_dbg & (WRADR == 6\'h12) & WREN;\r
+\tassign ld_dsr = op_dbg & (WRADR == 6\'h13) & WREN;\r
+\tassign ld_car = op_dbg & (WRADR == 6\'h14) & WREN;\r
+\r
+\tassign enable = dcr[12] & (USER ? dcr[10] : dcr[11]);\t// DEN & (USER ? UD : SD)\r
+\t\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) dcr <= 13\'d0;\r
+\t\t\telse if (ld_dcr) dcr <= {SRC1[23:19],SRC1[7:0]};\r
+\t\t\t\r
+\talways @(posedge BCLK) if (ld_bpc) bpc <= SRC1;\r
+\talways @(posedge BCLK) if (ld_car) car <= SRC1[31:2];\r
+\t\r
+\t//\t\t\t\t\tDEN\t\t  SD        DEN       UD       CAE      CRD      CAE      CWR    VNP/CBE  CAR\r
+\tassign DBG_IN = {(dcr[12] & dcr[11]),(dcr[12] & dcr[10]),(dcr[7] & dcr[6]),(dcr[7] & dcr[5]),dcr[4:0],car};\r
+\t\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) DSR <= 4\'d0;\r
+\t\t  else\r
+\t\t\tif (ld_dsr) DSR <= SRC1[31:28];\r
+\t\t\t  else\r
+\t\t\t\tbegin\r
+\t\t\t\t  DSR[3] <= DBG_HIT ? READ : DSR[3];\r
+\t\t\t\t  DSR[2] <= DSR[2] | PCMATCH;\r
+\t\t\t\t  DSR[1] <= DSR[1];\r
+\t\t\t\t  DSR[0] <= DSR[0] | DBG_HIT;\r
+\t\t\t\tend\r
+\r
+\tassign DBG_TRAPS[0] = enable & dcr[9] & (PC_ARCHI == bpc);\t// dcr[9]=PCE\r
+\tassign DBG_TRAPS[1] = DBG_HIT;\t// Compare Adress Hit\r
+\tassign DBG_TRAPS[2] = dcr[8];\t// TR, Trap enable\r
+\r
+endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t2. FP_STAT_REG\tFloating Point Status Register\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module FP_STAT_REG ( BCLK, BRESET, LFSR, UP_SP, UP_DP, TT_SP, TT_DP, WREN, WRADR, DIN, FSR, TWREN, FPU_TRAP, SAVE_PC);\r
+\t\r
+\tinput\t\t\tBCLK;\r
+\tinput\t\t\tBRESET;\r
+\tinput\t\t\tLFSR;\t// Load by LFSR opcode\r
+\tinput\t\t\tUP_SP,UP_DP;\t// update if calculation operation\r
+\tinput \t [4:0]\tTT_SP,TT_DP;\r
+\tinput\t\t\tWREN;\t// for RMB and LFSR\r
+\tinput\t [5:4]\tWRADR;\r
+\tinput \t[16:0] \tDIN;\t// Data for LFSR opcode\r
+\t\r
+\toutput\t[31:0] \tFSR;\r
+\toutput\t\t\tTWREN;\r
+\toutput\treg\t\tFPU_TRAP;\r
+\toutput\t\t\tSAVE_PC;\r
+\t\r
+\treg\t\t [4:3]\ttrap_d;\r
+\treg\t\t\t\tupdate_d;\r
+\treg\t\t\t\tset_rm_d;\r
+\treg\t\t[10:0]\tset_bits;\r
+\treg\t\t [4:0]\tflags;\r
+\treg\t\t\t\trm_bit;\r
+\t\r
+\twire\t\t\tload_fsr;\r
+\twire\t\t\tupdate,update_i;\r
+\twire\t [4:0]\ttrap;\r
+\twire\t\t\tuflag,iflag,rmflag;\r
+\r
+\tassign load_fsr = LFSR & WREN;\r
+\t\r
+\tassign trap = UP_SP ? TT_SP : TT_DP;\r
+\t\r
+\t// This signal suppresses write into registers if FPU Trap, timing critical signal !\r
+\tassign TWREN = ~((UP_SP & (TT_SP[2:0] != 3\'b0)) | (UP_DP & (TT_DP[2:0] != 3\'b0)));\r
+\t\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) FPU_TRAP <= 1\'b0;\r
+\t\t  else FPU_TRAP <= ~FPU_TRAP & ~TWREN;\t// one pulse of one cycle informs the Opcode Decoder\r
+\t\t\t\t\r
+\tassign update_i = (UP_SP | UP_DP) & ~FPU_TRAP;\t// unfortunately one FPU opcode may follow !\r
+\talways @(posedge BCLK) update_d\t<= update_i;\r
+\talways @(posedge BCLK) trap_d\t<= trap[4:3];\r
+\talways @(posedge BCLK) set_rm_d\t<= WREN & (WRADR == 2\'b10);\r
+\tassign update = update_d & ~FPU_TRAP;\r
+\t\r
+\t// The Flags are set and stay ""1"" \r
+\tassign iflag  = (update & trap_d[4]) | flags[4];\t// Inexact Result\r
+\tassign uflag  = (update & trap_d[3]) | flags[3];\t// Underflow\r
+\tassign rmflag = (set_rm_d & ~FPU_TRAP) | rm_bit;\t// Register Modify\r
+\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) flags[4:3] <= 2\'b0;\t// Inexact = Bit6, Underflow = Bit4\r
+\t\t  else\r
+\t\t  begin\r
+\t\t\tif (load_fsr) flags[4:3] <= {DIN[6],DIN[4]};\r
+\t\t\t  else\r
+\t\t\t\tif (update) flags[4:3] <= {iflag,uflag};\r
+\t\t  end\r
+\t\t  \r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) flags[2:0] <= 3\'b0;\t// TT Field = Bit2-0\r
+\t\t  else\r
+\t\t  begin\r
+\t\t\tif (load_fsr) flags[2:0] <= DIN[2:0];\r
+\t\t\t  else\r
+\t\t\t\tif (update_i) flags[2:0] <= trap[2:0];\r
+\t\t  end\r
+\t\t  \r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) rm_bit <= 1\'b0;\t// Register Modify Bit\r
+\t\t  else\r
+\t\t  begin\r
+\t\t\tif (load_fsr) rm_bit <= DIN[16];\r
+\t\t\t  else\r
+\t\t\t\tif (set_rm_d & ~FPU_TRAP) rm_bit <= 1\'b1;\t// in case of TRAP there is no writing to Register\r
+\t\t  end\r
+\t\t\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) set_bits <= 11\'b0;\t// all other Bits\r
+\t\t  else\r
+\t\t\tif (load_fsr) set_bits <= {DIN[15:7],DIN[5],DIN[3]};\r
+\r
+\tassign FSR = {15\'h0,rmflag,set_bits[10:2],iflag,set_bits[1],uflag,set_bits[0],flags[2:0]};\r
+\t\r
+\tassign SAVE_PC = (UP_SP | UP_DP) & ~FPU_TRAP;\t// Store the correct PC for FPU Trap\r
+\t\r
+endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t3. REGISTER\t\tGeneral Purpose Registers\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module REGISTER( BCLK, ENWR, DOWR, BYDIN, DIN, RADR, WADR, WMASKE, DOUT, SELI );\r
+\r
+input\t\t\tBCLK;\r
+input\t\t\tDOWR,ENWR;\r
+input\t[31:0]\tBYDIN,DIN;\r
+input\t [7:0]\tRADR;\r
+input\t [5:0]\tWADR;\r
+input\t [1:0]\tWMASKE;\r
+\r
+output\t[31:0]\tDOUT;\r
+output reg \t\tSELI;\r
+\r
+reg\t \t [2:0] \tMX;\r
+\r
+wire\t [3:0]\tBE;\r
+wire\t\t\teq_rw;\r
+\r
+// +++++++++++++++++++ Memories ++++++++++++++++++++\r
+\r
+reg\t \t [7:0]\tREGFILE_D [0:63];\r
+reg\t \t [7:0]\tREGFILE_C [0:63];\r
+reg\t \t [7:0]\tREGFILE_B [0:63];\r
+reg\t \t [7:0]\tREGFILE_A [0:63];\r
+reg\t\t[31:0]\tRF;\r
+\r
+assign\tBE = {WMASKE[1],WMASKE[1],(WMASKE[1] | WMASKE[0]),1\'b1};\r
+\r
+assign\teq_rw = ENWR & (RADR[5:0] == WADR);\r
+\r
+always @(posedge BCLK) if (RADR[7]) MX[2:0] <= BE[2:0] & {{3{eq_rw}}};\r
+\r
+always @(posedge BCLK) if (RADR[7]) SELI <= RADR[6];\r
+\r
+assign DOUT[31:16] = MX[2] ? BYDIN[31:16] : RF[31:16];\r
+assign DOUT[15:8]  = MX[1] ? BYDIN[15:8]  : RF[15:8];\r
+assign DOUT[7:0]   = MX[0] ? BYDIN[7:0]   : RF[7:0];\r
+\t\r
+// ++++++++++++++++ Register File 64 * 32 Bits ++++++++++++\r
+\r
+always @(posedge BCLK)\r
+\tif (RADR[7])\r
+\t\tbegin\r
+\t\t\tRF[31:24] <= REGFILE_D[RADR[5:0]];\r
+\t\t\tRF[23:16] <= REGFILE_C[RADR[5:0]];\r
+\t\t\tRF[15:8]  <= REGFILE_B[RADR[5:0]];\r
+\t\t\tRF[7:0]   <= REGFILE_A[RADR[5:0]];\r
+\t\tend\r
+\r
+always @(posedge BCLK)\r
+\tif (DOWR)\r
+\t\tbegin\r
+\t\t\tif (BE[3]) REGFILE_D[WADR] <= DIN[31:24];\r
+\t\t\tif (BE[2]) REGFILE_C[WADR] <= DIN[23:16];\r
+\t\t\tif (BE[1]) REGFILE_B[WADR] <= DIN[15:8];\r
+\t\t\tif (BE[0]) REGFILE_A[WADR] <= DIN[7:0];\r
+\t\tend\r
+\r
+endmodule\r
+\r
+"
+"module tuberom_32016 (
+    input             clk,
+    input [12:0]      addr,
+    output reg [31:0] data
+);
+
+    reg  [31:0] rom[0:8191];
+   
+    always @(posedge clk)
+        begin
+            data <= rom[addr];  
+        end
+  
+    initial $readmemh(""tuberom_32016_200.dat"", rom);
+
+endmodule
+"
+"/*
+ *  Single channel counter of 8254 timer simplified for Zet SoC
+ *  Copyright (c) 2010  YS <ys05@mail.ru>
+ *  Copyright (C) 2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ *  This module uses:
+ *   - Modes (binary) 2 and 3 only
+ *  Assumptions:
+ *   1. clkt is asynchronous simple wire (1.193182 MHz by default)
+ *   2. gate is synchronous (comes from Wishbone controlled register)
+ *   3. clkrw read/write clock (derived from Wishbone clock) is running
+ *      always and it has much higher frequency than clkt
+ */
+
+module timer_counter(
+  input [1:0] cntnum,       // Counter Number constant 0/1/2
+  input [5:0] cw0,          // Initial Control Word constant
+  input [15:0] cr0,         // Initial Constant Register constant
+  input clkrw,              // Read/Write System Clock
+  input rst,                // Reset
+  input wrc,                // Write Command 1 clock pulse
+  input wrd,                // Write Data 1 clock pulse
+  input rdd,                // Read Data full cycle strobe
+  input [7:0] data_i,       // Input Data
+  output reg [7:0] data_o,  // Output Data
+  input clkt,               // Timer Clock (asynchronous to clkrw)
+  input gate,               // Timer Gate (synchronous to clkrw)
+  output out                // Timer Out (synchronous to clkrw)
+  );
+
+  localparam
+          DATL = 2'd0,
+          DATH = 2'd1,
+          STAT = 2'd2;
+
+  reg [15:0] rCounter;      // Timer Counter
+  reg [15:0] rConstant;     // Constant Register
+  reg [5:0] rControl;       // Control Word Register
+  reg [15:0] rLatchD;       // Output Data Latch
+  reg [7:0] rLatchS;        // Output State Latch
+  reg bOut;                     
+  reg bFn;
+
+  reg clcd, clcs;           // Latch Data and Latch State command pulses
+
+  reg fWroteLow;
+  reg fWroteHigh;
+
+  reg fCount;
+  reg bCurrentClk;
+  reg bFilterClk1;
+  reg bFilterClk2;
+
+  reg fLatchData;
+  reg fLatchStat;
+
+  reg rdd1;
+  reg [1:0] outmux;
+  reg fToggleHigh;
+
+  wire fReadEnd;
+
+  wire [2:0] rbc_cnt_mask = data_i[3:1];
+
+  wire fMode3 = (rControl[2:1] == 2'b11);
+
+  wire fRWLow = rControl[4];
+  wire fRWHigh = rControl[5];
+
+  assign out = bOut;
+
+  // Write to Control Word Register
+  always @(posedge clkrw)
+  begin
+    if (rst)
+    begin
+      rControl <= cw0;
+      clcd <= 1'b0;
+      clcs <= 1'b0;
+    end
+    else
+    begin
+      if (wrc && data_i[7:6] == cntnum)
+      begin
+        if (data_i[5:4] == 2'b00) 
+          clcd <= 1'b1;            // CLC
+        else
+          rControl <= data_i[5:0]; // WRC
+      end
+      else if (wrc && data_i[7:6] == 2'b11 && rbc_cnt_mask[cntnum])
+      begin
+        clcd <= ~data_i[5];        // RBC
+        clcs <= ~data_i[4];
+      end
+
+      if (clcd)
+        clcd <= 1'b0;  // 1 clock pulse clcd
+
+      if (clcs)
+        clcs <= 1'b0;  // 1 clock pulse clcs
+    end
+  end
+
+  // Write to Constant Register
+  always @(posedge clkrw)
+  begin
+    if (rst)
+    begin
+      rConstant <= cr0;
+      fWroteLow <= 1'b0;
+      fWroteHigh <= 1'b0;
+    end
+    else
+    begin
+      if (fWroteHigh || wrc)
+      begin
+        fWroteLow <= 1'b0;
+        fWroteHigh <= 1'b0;
+      end
+      if (wrd) // need 1 clock pulse wrd!!!
+      begin
+        if (!fWroteLow)
+        begin
+          if (fRWLow)
+            rConstant[7:0] <= data_i[7:0];
+          fWroteLow <= 1'b1;
+          if (!fRWHigh)
+          begin
+            rConstant[15:8] <= 8'b00000000;
+            fWroteHigh <= 1'b1;
+          end
+        end
+        if (!fWroteHigh && (fWroteLow || !fRWLow))
+        begin
+          if (fRWHigh)
+            rConstant[15:8] <= data_i[7:0];
+          fWroteHigh <= 1'b1;
+          if (!fRWLow)
+          begin
+            rConstant[7:0] <= 8'b00000000;
+            fWroteLow <= 1'b1;
+          end
+        end
+      end // if (wrd)
+    end
+  end
+
+  // Synchronizing Count Clock with Wishbone Clock
+  always @(posedge clkrw)
+  begin
+    if (rst)
+    begin
+      fCount <= 1'b0;
+      bCurrentClk <= 1'b0;
+      bFilterClk1 <= 1'b0;
+      bFilterClk2 <= 1'b0;
+    end
+    else
+    begin
+      bFilterClk1 <= clkt;
+      bFilterClk2 <= bFilterClk1;
+      if ((bFilterClk1 == bFilterClk2) && (bCurrentClk != bFilterClk2))
+      begin
+        bCurrentClk <= bFilterClk2;
+        if (bCurrentClk == 1'b1) // falling edge of clkt
+          fCount <= 1'b1;
+      end
+      if (fCount)
+        fCount <= 1'b0; // 1 clock pulse fCount
+    end
+  end  
+
+  // Timer Counter in mode 2 or mode 3
+  always @(posedge clkrw)
+  begin
+    if (rst)
+    begin
+      bOut <= 1'b1;
+      rCounter <= cr0 & ((cw0[2:1] == 2'b11) ? 16'hFFFE : 16'hFFFF); // (mode==3) ? :
+      bFn <= 1'b0;
+    end
+    else
+    begin
+      if (fWroteHigh)
+      begin
+        rCounter <= rConstant & ((fMode3) ? 16'hFFFE : 16'hFFFF);
+        bOut <= 1'b1;
+      end
+      else if (fCount && gate) // tclk_i && gate_i
+      begin
+        if ((fMode3) ? (bOut == 1'b0 && rCounter == 16'h0002) : (bOut == 1'b0))
+        begin
+          rCounter <= rConstant & ((fMode3) ? 16'hFFFE : 16'hFFFF);
+          bOut <= 1'b1;
+        end
+        else if (fMode3 && bOut == 1'b1 && rCounter == ((rConstant[0]) ? 16'h0000 : 16'h0002))
+        begin
+          rCounter <= rConstant & 16'hFFFE;
+          bOut <= 1'b0;
+        end
+        else if (!fMode3 && rCounter == 16'h0002)
+          bOut <= 1'b0;
+        else
+          rCounter <= rCounter - ((fMode3) ? 16'h0002 : 16'h0001);
+      end
+    end
+  end
+
+  // Output Latch Control
+  always @(posedge clkrw)
+  begin
+    if (rst)
+    begin
+      fLatchData <= 1'b0;
+      fLatchStat <= 1'b0;
+      rLatchD <= 16'b0;
+      rLatchS <= 8'b0;
+    end
+    else
+    begin
+      if (!fLatchData)
+        rLatchD <= rCounter;
+      if (!fLatchStat)
+        rLatchS <= {bOut, bFn, rControl};
+      if (clcd)
+        fLatchData <= 1'b1;
+      if (clcs)
+        fLatchStat <= 1'b1;
+      if (fReadEnd)
+      begin
+        if (fLatchStat)
+          fLatchStat <= 1'b0;
+        else if (fLatchData)
+          fLatchData <= 1'b0;
+      end
+    end
+  end
+
+  // Output Mux
+  always @(outmux or rLatchS or rLatchD)
+  begin
+    case (outmux)
+      STAT: data_o = rLatchS;
+      DATH: data_o = rLatchD[15:8];
+      DATL: data_o = rLatchD[7:0];
+    endcase
+  end
+
+  assign fReadEnd = !rdd && rdd1; // 1 clock pulse after read
+
+  // Read Data/State
+  always @(posedge clkrw)
+  begin
+    if (rst)
+    begin
+      rdd1 <= 1'b0;
+      outmux <= DATL;
+      fToggleHigh <= 1'b0;
+    end
+    else
+    begin
+      // Helper for fReadEnd
+      rdd1 <= rdd;
+
+      // Output Mux Control
+      if (fLatchStat)
+        outmux <= STAT;
+      else if ((fRWHigh && !fRWLow) || (fRWHigh && fToggleHigh))
+        outmux <= DATH;
+      else
+        outmux <= DATL;
+
+      if (wrc)
+        fToggleHigh <= 1'b0;
+      else if (fReadEnd && !fLatchStat)
+        fToggleHigh <= !fToggleHigh;
+    end
+  end
+
+endmodule
+"
+"/*
+ *  Wishbone switch and address decoder
+ *  Copyright (C) 2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *  Copyright (C) 2008, 2009 Sebastien Bourdeauducq - http://lekernel.net
+ *  Copyright (C) 2000 Johny Chi - chisuhua@yahoo.com.cn
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+module wb_switch #(
+    parameter s0_addr_1 = 20'h00000,  // Default Values
+    parameter s0_mask_1 = 20'h00000,
+    parameter s1_addr_1 = 20'h00000,
+    parameter s1_mask_1 = 20'h00000,
+    parameter s1_addr_2 = 20'h00000,
+    parameter s1_mask_2 = 20'h00000,
+    parameter s1_addr_3 = 20'h00000,
+    parameter s1_mask_3 = 20'h00000,
+    parameter s1_addr_4 = 20'h00000,
+    parameter s1_mask_4 = 20'h00000,
+    parameter s2_addr_1 = 20'h00000,
+    parameter s2_mask_1 = 20'h00000,
+    parameter s3_addr_1 = 20'h00000,
+    parameter s3_mask_1 = 20'h00000,
+    parameter s4_addr_1 = 20'h00000,
+    parameter s4_mask_1 = 20'h00000,
+    parameter s5_addr_1 = 20'h00000,
+    parameter s5_mask_1 = 20'h00000,
+    parameter s6_addr_1 = 20'h00000,
+    parameter s6_mask_1 = 20'h00000,
+    parameter s7_addr_1 = 20'h00000,
+    parameter s7_mask_1 = 20'h00000,
+    parameter s8_addr_1 = 20'h00000,
+    parameter s8_mask_1 = 20'h00000,
+    parameter s9_addr_1 = 20'h00000,
+    parameter s9_mask_1 = 20'h00000,
+    parameter sA_addr_1 = 20'h00000,
+    parameter sA_mask_1 = 20'h00000,
+    parameter sA_addr_2 = 20'h00000,
+    parameter sA_mask_2 = 20'h00000
+  )(
+    // Master interface
+    input  [15:0] m_dat_i,
+    output [15:0] m_dat_o,
+    input  [20:1] m_adr_i,
+    input  [ 1:0] m_sel_i,
+    input         m_we_i,
+    input         m_cyc_i,
+    input         m_stb_i,
+    output        m_ack_o,
+
+    // Slave 0 interface
+    input  [15:0] s0_dat_i,
+    output [15:0] s0_dat_o,
+    output [20:1] s0_adr_o,
+    output [ 1:0] s0_sel_o,
+    output        s0_we_o,
+    output        s0_cyc_o,
+    output        s0_stb_o,
+    input         s0_ack_i,
+
+    // Slave 1 interface
+    input  [15:0] s1_dat_i,
+    output [15:0] s1_dat_o,
+    output [20:1] s1_adr_o,
+    output [ 1:0] s1_sel_o,
+    output        s1_we_o,
+    output        s1_cyc_o,
+    output        s1_stb_o,
+    input         s1_ack_i,
+
+    // Slave 2 interface
+    input  [15:0] s2_dat_i,
+    output [15:0] s2_dat_o,
+    output [20:1] s2_adr_o,
+    output [ 1:0] s2_sel_o,
+    output        s2_we_o,
+    output        s2_cyc_o,
+    output        s2_stb_o,
+    input         s2_ack_i,
+
+    // Slave 3 interface
+    input  [15:0] s3_dat_i,
+    output [15:0] s3_dat_o,
+    output [20:1] s3_adr_o,
+    output [ 1:0] s3_sel_o,
+    output        s3_we_o,
+    output        s3_cyc_o,
+    output        s3_stb_o,
+    input         s3_ack_i,
+
+    // Slave 4 interface
+    input  [15:0] s4_dat_i,
+    output [15:0] s4_dat_o,
+    output [20:1] s4_adr_o,
+    output [ 1:0] s4_sel_o,
+    output        s4_we_o,
+    output        s4_cyc_o,
+    output        s4_stb_o,
+    input         s4_ack_i,
+
+    // Slave 5 interface
+    input  [15:0] s5_dat_i,
+    output [15:0] s5_dat_o,
+    output [20:1] s5_adr_o,
+    output [ 1:0] s5_sel_o,
+    output        s5_we_o,
+    output        s5_cyc_o,
+    output        s5_stb_o,
+    input         s5_ack_i,
+
+    // Slave 6 interface
+    input  [15:0] s6_dat_i,
+    output [15:0] s6_dat_o,
+    output [20:1] s6_adr_o,
+    output [ 1:0] s6_sel_o,
+    output        s6_we_o,
+    output        s6_cyc_o,
+    output        s6_stb_o,
+    input         s6_ack_i,
+
+    // Slave 7 interface
+    input  [15:0] s7_dat_i,
+    output [15:0] s7_dat_o,
+    output [20:1] s7_adr_o,
+    output [ 1:0] s7_sel_o,
+    output        s7_we_o,
+    output        s7_cyc_o,
+    output        s7_stb_o,
+    input         s7_ack_i,
+
+    // Slave 8 interface
+    input  [15:0] s8_dat_i,
+    output [15:0] s8_dat_o,
+    output [20:1] s8_adr_o,
+    output [ 1:0] s8_sel_o,
+    output        s8_we_o,
+    output        s8_cyc_o,
+    output        s8_stb_o,
+    input         s8_ack_i,
+
+    // Slave 9 interface
+    input  [15:0] s9_dat_i,
+    output [15:0] s9_dat_o,
+    output [20:1] s9_adr_o,
+    output [ 1:0] s9_sel_o,
+    output        s9_we_o,
+    output        s9_cyc_o,
+    output        s9_stb_o,
+    input         s9_ack_i,
+
+    // Slave A interface - masked default
+    input  [15:0] sA_dat_i,
+    output [15:0] sA_dat_o,
+    output [20:1] sA_adr_o,
+    output [ 1:0] sA_sel_o,
+    output        sA_we_o,
+    output        sA_cyc_o,
+    output        sA_stb_o,
+    input         sA_ack_i,
+
+    // Slave B interface - default
+    input  [15:0] sB_dat_i,
+    output [15:0] sB_dat_o,
+    output [20:1] sB_adr_o,
+    output [ 1:0] sB_sel_o,
+    output        sB_we_o,
+    output        sB_cyc_o,
+    output        sB_stb_o,
+    input         sB_ack_i
+
+  );
+
+`define mbusw_ls  20 + 2 + 16 + 1 + 1 + 1  // address + byte select + data + cyc + we + stb
+
+wire [11:0] slave_sel;
+wire [15:0] i_dat_s;   // internal shared bus, slave data to master
+wire        i_bus_ack; // internal shared bus, ack signal
+
+wire [`mbusw_ls -1:0] i_bus_m;    // internal shared bus, master data and control to slave
+
+assign m_dat_o = i_dat_s;
+assign m_ack_o = i_bus_ack;
+
+// Bus Acknowlegement
+assign i_bus_ack =   s0_ack_i | s1_ack_i | s2_ack_i | s3_ack_i | s4_ack_i | s5_ack_i | s6_ack_i |
+          s7_ack_i | s8_ack_i | s9_ack_i | sA_ack_i | sB_ack_i;
+
+assign i_dat_s =   ({16{slave_sel[ 0]}} & s0_dat_i)
+          |({16{slave_sel[ 1]}} & s1_dat_i)
+          |({16{slave_sel[ 2]}} & s2_dat_i)
+          |({16{slave_sel[ 3]}} & s3_dat_i)
+          |({16{slave_sel[ 4]}} & s4_dat_i)
+          |({16{slave_sel[ 5]}} & s5_dat_i)
+          |({16{slave_sel[ 6]}} & s6_dat_i)
+          |({16{slave_sel[ 7]}} & s7_dat_i)
+          |({16{slave_sel[ 8]}} & s8_dat_i)
+          |({16{slave_sel[ 9]}} & s9_dat_i)
+          |({16{slave_sel[10]}} & sA_dat_i)
+          |({16{slave_sel[11]}} & sB_dat_i)
+        ;
+
+// Bus Selection logic
+assign slave_sel[ 0] =  ((m_adr_i & s0_mask_1) == s0_addr_1);
+assign slave_sel[ 1] =  ((m_adr_i & s1_mask_1) == s1_addr_1) | ((m_adr_i & s1_mask_2) == s1_addr_2) | ((m_adr_i & s1_mask_3) == s1_addr_3) | ((m_adr_i & s1_mask_4) == s1_addr_4);
+assign slave_sel[ 2] =  ((m_adr_i & s2_mask_1) == s2_addr_1);
+assign slave_sel[ 3] =  ((m_adr_i & s3_mask_1) == s3_addr_1);
+assign slave_sel[ 4] =  ((m_adr_i & s4_mask_1) == s4_addr_1);
+assign slave_sel[ 5] =  ((m_adr_i & s5_mask_1) == s5_addr_1);
+assign slave_sel[ 6] =  ((m_adr_i & s6_mask_1) == s6_addr_1);
+assign slave_sel[ 7] =  ((m_adr_i & s7_mask_1) == s7_addr_1);
+assign slave_sel[ 8] =  ((m_adr_i & s8_mask_1) == s8_addr_1);
+assign slave_sel[ 9] =  ((m_adr_i & s9_mask_1) == s9_addr_1);
+assign slave_sel[10] = (((m_adr_i & sA_mask_1) == sA_addr_1) | (( m_adr_i & sA_mask_2)== sA_addr_2)) & ~(|slave_sel[9:0]);
+assign slave_sel[11] = ~(|slave_sel[10:0]);
+
+assign i_bus_m = {m_adr_i, m_sel_i, m_dat_i, m_we_i, m_cyc_i, m_stb_i};
+
+assign {s0_adr_o, s0_sel_o, s0_dat_o, s0_we_o, s0_cyc_o}  = i_bus_m[`mbusw_ls -1:1];  // slave 0
+assign  s0_stb_o = i_bus_m[1] & i_bus_m[0] & slave_sel[0];     // stb_o = cyc_i & stb_i & slave_sel
+
+assign {s1_adr_o, s1_sel_o, s1_dat_o, s1_we_o, s1_cyc_o} = i_bus_m[`mbusw_ls -1:1];    // slave 1
+assign  s1_stb_o = i_bus_m[1] & i_bus_m[0] & slave_sel[1];
+
+assign {s2_adr_o, s2_sel_o, s2_dat_o, s2_we_o, s2_cyc_o} = i_bus_m[`mbusw_ls -1:1];    // slave 2
+assign  s2_stb_o = i_bus_m[1] & i_bus_m[0] & slave_sel[2];
+
+assign {s3_adr_o, s3_sel_o, s3_dat_o, s3_we_o, s3_cyc_o} = i_bus_m[`mbusw_ls -1:1];    // slave 3
+assign  s3_stb_o = i_bus_m[1] & i_bus_m[0] & slave_sel[3];
+
+assign {s4_adr_o, s4_sel_o, s4_dat_o, s4_we_o, s4_cyc_o} = i_bus_m[`mbusw_ls -1:1];    // slave 4
+assign  s4_stb_o = i_bus_m[1] & i_bus_m[0] & slave_sel[4];
+
+assign {s5_adr_o, s5_sel_o, s5_dat_o, s5_we_o, s5_cyc_o} = i_bus_m[`mbusw_ls -1:1];    // slave 5
+assign  s5_stb_o = i_bus_m[1] & i_bus_m[0] & slave_sel[5];
+
+assign {s6_adr_o, s6_sel_o, s6_dat_o, s6_we_o, s6_cyc_o} = i_bus_m[`mbusw_ls -1:1];    // slave 6
+assign  s6_stb_o = i_bus_m[1] & i_bus_m[0] & slave_sel[6];
+
+assign {s7_adr_o, s7_sel_o, s7_dat_o, s7_we_o, s7_cyc_o} = i_bus_m[`mbusw_ls -1:1];    // slave 7
+assign  s7_stb_o = i_bus_m[1] & i_bus_m[0] & slave_sel[7];
+
+assign {s8_adr_o, s8_sel_o, s8_dat_o, s8_we_o, s8_cyc_o} = i_bus_m[`mbusw_ls -1:1];    // slave 8
+assign  s8_stb_o = i_bus_m[1] & i_bus_m[0] & slave_sel[8];
+
+assign {s9_adr_o, s9_sel_o, s9_dat_o, s9_we_o, s9_cyc_o} = i_bus_m[`mbusw_ls -1:1];    // slave 9
+assign  s9_stb_o = i_bus_m[1] & i_bus_m[0] & slave_sel[9];
+
+assign {sA_adr_o, sA_sel_o, sA_dat_o, sA_we_o, sA_cyc_o} = i_bus_m[`mbusw_ls -1:1];    // slave A
+assign  sA_stb_o = i_bus_m[1] & i_bus_m[0] & slave_sel[10];
+
+assign {sB_adr_o, sB_sel_o, sB_dat_o, sB_we_o, sB_cyc_o} = i_bus_m[`mbusw_ls -1:1];    // slave B
+assign  sB_stb_o = i_bus_m[1] & i_bus_m[0] & slave_sel[11];
+
+endmodule
+"
+"/*
+ *  Zet SoC top level file for Altera DE1 board
+ *  Copyright (C) 2009, 2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+module CoPro80186 (
+
+        input \t      fastclk,
+        
+        // GOP Signals
+        output [6:1]  test,
+        output [8:2]  tp,
+        input [2:1]   sw,
+        output \t      fcs,
+\t\t   
+        // Tube signals (use 16 out of 22 DIL pins)
+        input \t      h_phi2,
+        input [2:0]   h_addr,
+        inout [7:0]   h_data,
+        input \t      h_rdnw,
+        input \t      h_cs_b,
+        input \t      h_rst_b,
+        output \t      h_irq_b,
+
+        // Ram Signals
+        output \t      ram_cs,
+        output \t      ram_oe,
+        output \t      ram_wr,
+        output [18:0] ram_addr,
+        inout [7:0]   ram_data
+);
+
+  // Registers and nets
+  wire        clk;
+  wire        rst_lck;
+  wire [15:0] dat_o;
+  wire [15:0] dat_i;
+  wire [19:1] adr;
+  wire        we;
+  wire        tga;
+  wire [ 1:0] sel;
+  wire        stb;
+  wire        cyc;
+  wire        ack;
+  wire        lock;
+
+  // wires to BIOS ROM
+  wire [15:0] rom_dat_o;
+  wire [15:0] rom_dat_i;
+  wire        rom_tga_i;
+  wire [19:1] rom_adr_i;
+  wire [ 1:0] rom_sel_i;
+  wire        rom_we_i;
+  wire        rom_cyc_i;
+  wire        rom_stb_i;
+  wire        rom_ack_o;
+  
+    // wires to RAM
+  wire [15:0] ram_dat_o;
+  wire [15:0] ram_dat_i;
+  wire        ram_tga_i;
+  wire [19:1] ram_adr_i;
+  wire [ 1:0] ram_sel_i;
+  wire        ram_we_i;
+  wire        ram_cyc_i;
+  wire        ram_stb_i;
+  wire        ram_ack_o;
+
+  // wires to Tube
+  wire [15:0] tube_dat_o;
+  wire [15:0] tube_dat_i;
+  wire        tube_tga_i;
+  wire [19:1] tube_adr_i;
+  wire [ 1:0] tube_sel_i;
+  wire        tube_we_i;
+  wire        tube_cyc_i;
+  wire        tube_stb_i;
+  wire        tube_ack_o;
+
+
+  wire        drq;
+  wire        dack_b;
+  
+  wire [2:0]  p_addr;
+  wire        p_cs_b; 
+  wire [7:0]  p_data; 
+  wire        p_rd_b; 
+  wire        p_wr_b;
+  wire        p_rst_b;
+  wire        p_nmi_b;
+  wire        p_irq_b;
+
+
+  // unused slaves
+  wire        s3_cyc_i;
+  wire        s3_stb_i;
+  wire        s4_cyc_i;
+  wire        s4_stb_i;
+  wire        s5_cyc_i;
+  wire        s5_stb_i;
+  wire        s6_cyc_i;
+  wire        s6_stb_i;
+  wire        s7_cyc_i;
+  wire        s7_stb_i;
+  wire        s9_cyc_i;
+  wire        s9_stb_i;
+  wire        sa_cyc_i;
+  wire        sa_stb_i;
+  wire        def_cyc_i;
+  wire        def_stb_i;
+
+
+  // wires to default stb/ack
+  wire [15:0] sw_dat_o;
+
+  wire [ 7:0] intv;
+  wire [ 2:0] iid;
+  wire        intr;
+  wire        inta;
+
+  wire        nmi;
+  wire        nmia;
+
+// Instantiate the module
+dcm_49_16 instance_name (
+    .CLKIN_IN(fastclk), 
+    .CLK0_OUT(clk), 
+    .CLK0_OUT1(), 
+    .CLK2X_OUT()
+    );
+    
+
+  wire rst;
+  assign rst = !p_rst_b;
+
+
+  bootrom bootrom (
+    .clk (clk),            // Wishbone slave interface
+    .rst (rst),
+    .wb_dat_i (rom_dat_i),
+    .wb_dat_o (rom_dat_o),
+    .wb_adr_i (rom_adr_i),
+    .wb_we_i  (rom_we_i ),
+    .wb_tga_i (rom_tga_i),
+    .wb_stb_i (rom_stb_i),
+    .wb_cyc_i (rom_cyc_i),
+    .wb_sel_i (rom_sel_i),
+    .wb_ack_o (rom_ack_o)
+  );
+  
+wb_sram16 wb_sram16 (
+    .clk(clk), 
+    .reset(rst), 
+    .wb_dat_i(ram_dat_i), 
+    .wb_dat_o(ram_dat_o), 
+    .wb_adr_i(ram_adr_i), 
+    .wb_we_i(ram_we_i),
+    .wb_tga_i(ram_tga_i),
+    .wb_stb_i(ram_stb_i), 
+    .wb_cyc_i(ram_cyc_i), 
+    .wb_sel_i(ram_sel_i), 
+    .wb_ack_o(ram_ack_o),
+    
+    .sram_adr(ram_addr), 
+    .sram_dat(ram_data), 
+    .sram_be_n({ram_ub_b, ram_lb_b}), 
+    .sram_ce_n(ram_cs), 
+    .sram_oe_n(ram_oe), 
+    .sram_we_n(ram_wr)
+    );
+
+wb_tube wb_tube_inst(
+    .clk(clk), 
+    .reset(rst), 
+    .wb_stb_i(tube_stb_i), 
+    .wb_cyc_i(tube_cyc_i), 
+    .wb_ack_o(tube_ack_o), 
+    .wb_we_i(tube_we_i),
+    .wb_tga_i(tube_tga_i),
+    .wb_adr_i(tube_adr_i[3:1]), 
+    .wb_sel_i(tube_sel_i), 
+    .wb_dat_i(tube_dat_i), 
+    .wb_dat_o(tube_dat_o), 
+    .tube_adr(p_addr), 
+    .tube_dat(p_data), 
+    .tube_cs_n(p_cs_b), 
+    .tube_rd_n(p_rd_b), 
+    .tube_wr_n(p_wr_b)
+    );
+    
+tube tube_inst(
+    .h_addr(h_addr), 
+    .h_cs_b(h_cs_b), 
+    .h_data(h_data), 
+    .h_phi2(h_phi2), 
+    .h_rdnw(h_rdnw), 
+    .h_rst_b(h_rst_b), 
+    .h_irq_b(h_irq_b), 
+    .drq(drq), 
+    .dack_b(dack_b), 
+    .p_addr(p_addr), 
+    .p_cs_b(p_cs_b), 
+    .p_data(p_data), 
+    .p_rd_b(p_rd_b), 
+    .p_wr_b(p_wr_b), 
+    .p_rst_b(p_rst_b), 
+    .p_nmi_b(p_nmi_b), 
+    .p_irq_b(p_irq_b)
+    );
+
+  simple_pic pic0 (
+    .clk  (clk),
+    .rst  (rst),
+    .intv (intv),
+    .inta (inta),
+    .intr (intr),
+    .iid  (iid)
+  );
+
+
+  zet zet (
+    .pc (),
+
+    // Wishbone master interface
+    .wb_clk_i (clk),
+    .wb_rst_i (rst),
+    .wb_dat_i (dat_i),
+    .wb_dat_o (dat_o),
+    .wb_adr_o (adr),
+    .wb_we_o  (we),
+    .wb_tga_o (tga),
+    .wb_sel_o (sel),
+    .wb_stb_o (stb),
+    .wb_cyc_o (cyc),
+    .wb_ack_i (ack),
+    .wb_tgc_i (intr),
+    .wb_tgc_o (inta),
+    .nmi      (nmi),
+    .nmia     (nmia)
+  );
+
+
+  // Interrupt Control Registers (0x20-0x3E)
+  // &0FF22 - EOI Register
+  // &0FF38 - INT0 Control Register                 
+
+  // Timer Control Registers (0x50-0x66)
+  // &0FF52                  
+  // &0FF56                  
+  // &0FF60                  
+  // &0FF62                  
+  // &0FF66
+
+  // Chip Select Control Registers (0xA0-0xA8)   
+  // &0FFA0                  
+  // &0FFA2                  
+  // &0FFA4                  
+  // &0FFA6                  
+  // &0FFA8                  
+
+  // DMA Channel 0 (0xC0 - 0xCA)
+  // &0FFC0                  
+  // &0FFC2                  
+  // &0FFC4                  
+  // &0FFC6                  
+  // &0FFCA
+  
+  wb_switch #(
+    .s0_addr_1 (20'b0_1100_0000_0000_0000_000), // bios boot mem 0xc0000 - 0xfffff
+    .s0_mask_1 (20'b1_1100_0000_0000_0000_000), // bios boot ROM Memory
+
+    .s1_addr_1 (20'b0_0000_0000_0000_0000_000), // mem 0x00000-0x7ffff
+    .s1_mask_1 (20'b1_1000_0000_0000_0000_000), // main memory
+
+    .s1_addr_2 (20'b0_1000_0000_0000_0000_000), // mem 0x80000-0xbffff
+    .s1_mask_2 (20'b1_1100_0000_0000_0000_000), // main memory
+
+    .s2_addr_1 (20'b1_0000_1111_1111_0010_000), // io 0xFF20 - 0xFF3E
+    .s2_mask_1 (20'b1_0000_1111_1111_1110_000), // Interrupt Control Registers
+
+    .s3_addr_1 (20'b1_0000_1111_1111_0101_000), // io 0xFF50 - 0xFF56
+    .s3_mask_1 (20'b1_0000_1111_1111_1111_100), // Timer Control 0 Registers
+
+    .s4_addr_1 (20'b1_0000_1111_1111_0101_100), // io 0xFF58 - 0xFF5E
+    .s4_mask_1 (20'b1_0000_1111_1111_1111_100), // Timer Control 1 Registers
+
+    .s5_addr_1 (20'b1_0000_1111_1111_0110_000), // io 0xFF60 - 0xFF66
+    .s5_mask_1 (20'b1_0000_1111_1111_1111_100), // Timer Control 2 Registers
+\t      
+    .s6_addr_1 (20'b1_0000_1111_1111_1010_000), // io 0xFFA0 - 0xFFAF
+    .s6_mask_1 (20'b1_0000_1111_1111_1111_000), // Chip Select Control Registers
+
+    .s7_addr_1 (20'b1_0000_1111_1111_1100_000), // io 0xFFC0 - 0xFFCf
+    .s7_mask_1 (20'b1_0000_1111_1111_1111_000), // DMA Channel 0
+
+    .s8_addr_1 (20'b1_0000_0000_0000_1000_000), // io 0x0080 - 0x008E
+    .s8_mask_1 (20'b1_0000_1111_1111_1111_000), // Tube ULA
+
+    .s9_addr_1 (20'b1_0000_0000_0000_0000_000), // Unused
+    .s9_mask_1 (20'b1_0000_1111_1111_1111_000), //
+
+    .sA_addr_1 (20'b1_0000_0000_0000_0000_000), // Unused
+    .sA_mask_1 (20'b1_0000_1111_1111_1111_000), //
+
+    .sA_addr_2 (20'b1_0000_0000_0000_0000_000), // Unused
+    .sA_mask_2 (20'b1_0000_1111_1111_1111_000)  //
+
+    ) wbs (
+
+    // Master interface
+    .m_dat_i (dat_o),
+    .m_dat_o (sw_dat_o),
+    .m_adr_i ({tga,adr}),
+    .m_sel_i (sel),
+    .m_we_i  (we),
+    .m_cyc_i (cyc),
+    .m_stb_i (stb),
+    .m_ack_o (ack),
+
+    // Slave 0 interface - bios rom
+    .s0_dat_i (rom_dat_o),
+    .s0_dat_o (rom_dat_i),
+    .s0_adr_o ({rom_tga_i,rom_adr_i}),
+    .s0_sel_o (rom_sel_i),
+    .s0_we_o  (rom_we_i),
+    .s0_cyc_o (rom_cyc_i),
+    .s0_stb_o (rom_stb_i),
+    .s0_ack_i (rom_ack_o),
+
+     // Slave 1 interface - main memory
+    .s1_dat_i (ram_dat_o),
+    .s1_dat_o (ram_dat_i),
+    .s1_adr_o ({ram_tga_i,ram_adr_i}),
+    .s1_sel_o (ram_sel_i),
+    .s1_we_o  (ram_we_i),
+    .s1_cyc_o (ram_cyc_i),
+    .s1_stb_o (ram_stb_i),
+    .s1_ack_i (ram_ack_o),
+
+    // Slave 2 interface - Interrupt Control
+    .s2_dat_i (16'h0000),
+    .s2_dat_o (),
+    .s2_adr_o (),
+    .s2_sel_o (),
+    .s2_we_o  (),
+    .s2_cyc_o (s2_cyc_i),
+    .s2_stb_o (s2_stb_i),
+    .s2_ack_i (s2_cyc_i && s2_stb_i),
+
+    // Slave 3 interface - Timer Control 0
+    .s3_dat_i (16'h0000),
+    .s3_dat_o (),
+    .s3_adr_o (),
+    .s3_sel_o (),
+    .s3_we_o  (),
+    .s3_cyc_o (s3_cyc_i),
+    .s3_stb_o (s3_stb_i),
+    .s3_ack_i (s3_cyc_i && s3_stb_i),
+
+    // Slave 4 interface - Timer Control 1
+    .s4_dat_i (16'h0000),
+    .s4_dat_o (),
+    .s4_adr_o (),
+    .s4_sel_o (),
+    .s4_we_o  (),
+    .s4_cyc_o (s4_cyc_i),
+    .s4_stb_o (s4_stb_i),
+    .s4_ack_i (s4_cyc_i && s4_stb_i),
+
+    // Slave 5 interface - Timer Control 2
+    .s5_dat_i (16'h0000),
+    .s5_dat_o (),
+    .s5_adr_o (),
+    .s5_sel_o (),
+    .s5_we_o  (),
+    .s5_cyc_o (s5_cyc_i),
+    .s5_stb_o (s5_stb_i),
+    .s5_ack_i (s5_cyc_i && s5_stb_i),
+
+    // Slave 6 interface - Chip Select Registers
+    .s6_dat_i (16'h0000),
+    .s6_dat_o (),
+    .s6_adr_o (),
+    .s6_sel_o (),
+    .s6_we_o  (),
+    .s6_cyc_o (s6_cyc_i),
+    .s6_stb_o (s6_stb_i),
+    .s6_ack_i (s6_cyc_i && s6_stb_i),
+
+    // Slave 7 interface - DMA Channel 0
+    .s7_dat_i (16'h0000),
+    .s7_dat_o (),
+    .s7_adr_o (),
+    .s7_sel_o (),
+    .s7_we_o  (),
+    .s7_cyc_o (s7_cyc_i),
+    .s7_stb_o (s7_stb_i),
+    .s7_ack_i (s7_cyc_i && s7_stb_i),
+
+    // Slave 8 interface - Tube
+    .s8_dat_i (tube_dat_o),
+    .s8_dat_o (tube_dat_i),
+    .s8_adr_o ({tube_tga_i,tube_adr_i}),
+    .s8_sel_o (tube_sel_i),
+    .s8_we_o  (tube_we_i),
+    .s8_cyc_o (tube_cyc_i),
+    .s8_stb_o (tube_stb_i),
+    .s8_ack_i (tube_ack_o),
+
+    // Slave 9 interface - not connected
+    .s9_dat_i (16'h0000),
+    .s9_dat_o (),
+    .s9_adr_o (),
+    .s9_sel_o (),
+    .s9_we_o  (),
+    .s9_cyc_o (s9_cyc_i),
+    .s9_stb_o (s9_stb_i),
+    .s9_ack_i (s9_cyc_i && s9_stb_i),
+
+    // Slave A interface - not connected
+    .sA_dat_i (16'h0000),
+    .sA_dat_o (),
+    .sA_adr_o (),
+    .sA_sel_o (),
+    .sA_we_o  (),
+    .sA_cyc_o (sa_cyc_i),
+    .sA_stb_o (sa_stb_i),
+    .sA_ack_i (sa_cyc_i && sa_stb_i),
+
+    // Slave B interface - default
+    .sB_dat_i (16'h0000),
+    .sB_dat_o (),
+    .sB_adr_o (),
+    .sB_sel_o (),
+    .sB_we_o  (),
+    .sB_cyc_o (def_cyc_i),
+    .sB_stb_o (def_stb_i),
+    .sB_ack_i (def_cyc_i & def_stb_i)
+  );
+
+  assign nmi = 0;
+  assign intv[0] = ~p_irq_b;
+  assign intv[4:1] = 0;
+  
+  assign dat_i = nmia ? 16'h0002 :
+                (inta ? { 13'b0000_0000_0000_1, iid } :
+                        sw_dat_o);
+                        
+  assign test = 0;
+  
+  assign dack_b = 1;
+  
+  assign fcs = 0;
+
+  assign tp = 0;
+   
+
+
+endmodule
+"
+"//////////////////////////////////////////////////////////////////
+//                                                              //
+//  Amber 2 Core top-Level module                               //
+//                                                              //
+//  This file is part of the Amber project                      //
+//  http://www.opencores.org/project,amber                      //
+//                                                              //
+//  Description                                                 //
+//  Instantiates the core consisting of fetch, instruction      //
+//  decode, execute, and co-processor.                          //
+//                                                              //
+//  Author(s):                                                  //
+//      - Conor Santifort, csantifort.amber@gmail.com           //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+//                                                              //
+// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
+//                                                              //
+// This source file may be used and distributed without         //
+// restriction provided that this copyright statement is not    //
+// removed from the file and that any derivative work contains  //
+// the original copyright notice and the associated disclaimer. //
+//                                                              //
+// This source file is free software; you can redistribute it   //
+// and/or modify it under the terms of the GNU Lesser General   //
+// Public License as published by the Free Software Foundation; //
+// either version 2.1 of the License, or (at your option) any   //
+// later version.                                               //
+//                                                              //
+// This source is distributed in the hope that it will be       //
+// useful, but WITHOUT ANY WARRANTY; without even the implied   //
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
+// PURPOSE.  See the GNU Lesser General Public License for more //
+// details.                                                     //
+//                                                              //
+// You should have received a copy of the GNU Lesser General    //
+// Public License along with this source; if not, download it   //
+// from http://www.opencores.org/lgpl.shtml                     //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+
+
+module a23_core
+(
+input                       i_clk,
+
+input                       i_irq,              // Interrupt request, active high
+input                       i_firq,             // Fast Interrupt request, active high
+
+input                       i_system_rdy,       // Amber is stalled when this is low
+
+// Wishbone Master I/F
+output      [31:0]          o_wb_adr,
+output      [3:0]           o_wb_sel,
+output                      o_wb_we,
+input       [31:0]          i_wb_dat,
+output      [31:0]          o_wb_dat,
+output                      o_wb_cyc,
+output                      o_wb_stb,
+input                       i_wb_ack,
+input                       i_wb_err
+
+);
+
+wire      [31:0]          execute_address;
+wire                      execute_address_valid;
+wire      [31:0]          execute_address_nxt;  // un-registered version of execute_address to the cache rams
+wire      [31:0]          write_data;
+wire                      write_enable;
+wire      [31:0]          read_data;
+wire                      priviledged;
+wire                      exclusive_exec;
+wire                      data_access_exec;
+wire      [3:0]           byte_enable;
+wire                      data_access;          // high for data petch, low for instruction fetch
+wire                      exclusive;            // swap access
+wire                      cache_enable;         // Enabel the cache
+wire                      cache_flush;          // Flush the cache
+wire      [31:0]          cacheable_area;
+
+wire                      fetch_stall;          // when this is asserted all registers in all 3 pipeline 
+                                                // stages are held
+                                                // at their current values
+wire     [1:0]            status_bits_mode;               
+wire                      status_bits_irq_mask;           
+wire                      status_bits_firq_mask;           
+wire                      status_bits_flags_wen;          
+wire                      status_bits_mode_wen;           
+wire                      status_bits_irq_mask_wen;       
+wire                      status_bits_firq_mask_wen;       
+wire     [31:0]           execute_status_bits;
+                 
+wire     [31:0]           imm32;                   
+wire     [4:0]            imm_shift_amount; 
+wire                      shift_imm_zero;      
+wire     [3:0]            condition;               
+wire     [31:0]           read_data_s2;            
+wire     [4:0]            read_data_alignment;     
+
+wire     [3:0]            rm_sel;                  
+wire     [3:0]            rds_sel;                 
+wire     [3:0]            rn_sel;                  
+wire     [3:0]            rm_sel_nxt;
+wire     [3:0]            rds_sel_nxt;
+wire     [3:0]            rn_sel_nxt;
+wire     [1:0]            barrel_shift_amount_sel; 
+wire     [1:0]            barrel_shift_data_sel;   
+wire     [1:0]            barrel_shift_function; 
+wire                      use_carry_in;  
+wire     [8:0]            alu_function;            
+wire     [1:0]            multiply_function;       
+wire     [2:0]            interrupt_vector_sel;    
+wire     [3:0]            address_sel;             
+wire     [1:0]            pc_sel;                  
+wire     [1:0]            byte_enable_sel;         
+wire     [2:0]            status_bits_sel;                
+wire     [2:0]            reg_write_sel;           
+wire                      user_mode_regs_load;     
+wire                      user_mode_regs_store_nxt;    
+wire                      firq_not_user_mode;
+
+wire                      write_data_wen;          
+wire                      copro_write_data_wen;          
+wire                      base_address_wen;        
+wire                      pc_wen;                  
+wire     [14:0]           reg_bank_wen;            
+wire     [3:0]            reg_bank_wsel;            
+
+wire     [2:0]            copro_opcode1;
+wire     [2:0]            copro_opcode2;
+wire     [3:0]            copro_crn;    
+wire     [3:0]            copro_crm;
+wire     [3:0]            copro_num;
+wire     [1:0]            copro_operation;
+wire     [31:0]           copro_read_data;
+wire     [31:0]           copro_write_data;
+wire                      multiply_done;
+
+wire                      decode_fault;
+wire                      iabt_trigger;
+wire                      dabt_trigger;
+
+wire     [7:0]            decode_fault_status;
+wire     [7:0]            iabt_fault_status;
+wire     [7:0]            dabt_fault_status;
+
+wire     [31:0]           decode_fault_address;
+wire     [31:0]           iabt_fault_address;
+wire     [31:0]           dabt_fault_address;
+
+wire                      adex;
+
+
+// data abort has priority
+assign decode_fault_status  = dabt_trigger ? dabt_fault_status  : iabt_fault_status;
+assign decode_fault_address = dabt_trigger ? dabt_fault_address : iabt_fault_address;
+assign decode_fault         = dabt_trigger | iabt_trigger;
+
+
+a23_fetch u_fetch (
+    .i_clk                              ( i_clk                             ),
+
+    .i_address                          ( {execute_address[31:2], 2'd0}     ),
+    .i_address_valid                    ( execute_address_valid             ), 
+    .i_address_nxt                      ( execute_address_nxt               ),
+    .i_write_data                       ( write_data                        ),
+    .i_write_enable                     ( write_enable                      ),
+    .o_read_data                        ( read_data                         ),
+    .i_priviledged                      ( priviledged                       ),
+    .i_byte_enable                      ( byte_enable                       ),
+    .i_data_access                      ( data_access                       ),      
+    .i_exclusive                        ( exclusive                         ),
+    .i_cache_enable                     ( cache_enable                      ),     
+    .i_cache_flush                      ( cache_flush                       ), 
+    .i_cacheable_area                   ( cacheable_area                    ),
+
+    .i_system_rdy                       ( i_system_rdy                      ),
+    .o_fetch_stall                      ( fetch_stall                       ),
+    
+    .o_wb_adr                           ( o_wb_adr                          ),
+    .o_wb_sel                           ( o_wb_sel                          ),
+    .o_wb_we                            ( o_wb_we                           ),
+    .i_wb_dat                           ( i_wb_dat                          ),
+    .o_wb_dat                           ( o_wb_dat                          ),
+    .o_wb_cyc                           ( o_wb_cyc                          ),
+    .o_wb_stb                           ( o_wb_stb                          ),
+    .i_wb_ack                           ( i_wb_ack                          ),
+    .i_wb_err                           ( i_wb_err                          )
+);
+
+
+a23_decode u_decode (
+    .i_clk                              ( i_clk                             ),
+    
+    // Instruction fetch or data read signals
+    .i_read_data                        ( read_data                         ),                                          
+    .i_execute_address                  ( execute_address                   ),
+    .i_adex                             ( adex                              ),
+    .i_iabt                             ( 1'd0                              ),
+    .i_dabt                             ( 1'd0                              ),
+    .i_abt_status                       ( 8'd0                              ),                                          
+    
+    .o_read_data                        ( read_data_s2                      ),                                          
+    .o_read_data_alignment              ( read_data_alignment               ),                                          
+    
+    .i_irq                              ( i_irq                             ),                                          
+    .i_firq                             ( i_firq                            ),                                          
+    .i_fetch_stall                      ( fetch_stall                       ),                                          
+    .i_execute_status_bits              ( execute_status_bits               ),                                          
+    .i_multiply_done                    ( multiply_done                     ),                                          
+    
+    .o_status_bits_mode                 ( status_bits_mode                  ),
+    .o_status_bits_irq_mask             ( status_bits_irq_mask              ),  
+    .o_status_bits_firq_mask            ( status_bits_firq_mask             ),  
+    .o_imm32                            ( imm32                             ),
+    .o_imm_shift_amount                 ( imm_shift_amount                  ),
+    .o_shift_imm_zero                   ( shift_imm_zero                    ),
+    .o_condition                        ( condition                         ),
+    .o_exclusive_exec                   ( exclusive_exec                    ), 
+    .o_data_access_exec                 ( data_access_exec                  ),
+    .o_rm_sel                           ( rm_sel                            ),
+    .o_rds_sel                          ( rds_sel                           ),
+    .o_rn_sel                           ( rn_sel                            ),
+    .o_rm_sel_nxt                       ( rm_sel_nxt                        ),
+    .o_rds_sel_nxt                      ( rds_sel_nxt                       ),
+    .o_rn_sel_nxt                       ( rn_sel_nxt                        ),
+    .o_barrel_shift_amount_sel          ( barrel_shift_amount_sel           ),
+    .o_barrel_shift_data_sel            ( barrel_shift_data_sel             ),
+    .o_barrel_shift_function            ( barrel_shift_function             ),
+    .o_use_carry_in                     ( use_carry_in                      ),
+    .o_alu_function                     ( alu_function                      ),
+    .o_multiply_function                ( multiply_function                 ),
+    .o_interrupt_vector_sel             ( interrupt_vector_sel              ),
+    .o_address_sel                      ( address_sel                       ),
+    .o_pc_sel                           ( pc_sel                            ),
+    .o_byte_enable_sel                  ( byte_enable_sel                   ),
+    .o_status_bits_sel                  ( status_bits_sel                   ),
+    .o_reg_write_sel                    ( reg_write_sel                     ),
+    .o_user_mode_regs_load              ( user_mode_regs_load               ),
+    .o_user_mode_regs_store_nxt         ( user_mode_regs_store_nxt          ),
+    .o_firq_not_user_mode               ( firq_not_user_mode                ),
+    .o_write_data_wen                   ( write_data_wen                    ),
+    .o_base_address_wen                 ( base_address_wen                  ),
+    .o_pc_wen                           ( pc_wen                            ),
+    .o_reg_bank_wen                     ( reg_bank_wen                      ),
+    .o_reg_bank_wsel                    ( reg_bank_wsel                     ),
+    .o_status_bits_flags_wen            ( status_bits_flags_wen             ),
+    .o_status_bits_mode_wen             ( status_bits_mode_wen              ),
+    .o_status_bits_irq_mask_wen         ( status_bits_irq_mask_wen          ),
+    .o_status_bits_firq_mask_wen        ( status_bits_firq_mask_wen         ),
+    
+    .o_copro_opcode1                    ( copro_opcode1                     ),                                        
+    .o_copro_opcode2                    ( copro_opcode2                     ),                                        
+    .o_copro_crn                        ( copro_crn                         ),                                        
+    .o_copro_crm                        ( copro_crm                         ),                                        
+    .o_copro_num                        ( copro_num                         ),                                        
+    .o_copro_operation                  ( copro_operation                   ), 
+    .o_copro_write_data_wen             ( copro_write_data_wen              ),                                        
+    
+    .o_iabt_trigger                     ( iabt_trigger                      ),
+    .o_iabt_address                     ( iabt_fault_address                ),
+    .o_iabt_status                      ( iabt_fault_status                 ),
+    .o_dabt_trigger                     ( dabt_trigger                      ),
+    .o_dabt_address                     ( dabt_fault_address                ),
+    .o_dabt_status                      ( dabt_fault_status                 ) 
+);
+
+
+a23_execute u_execute (
+    .i_clk                              ( i_clk                             ),
+    
+    .i_read_data                        ( read_data_s2                      ),
+    .i_read_data_alignment              ( read_data_alignment               ), 
+    .i_copro_read_data                  ( copro_read_data                   ),
+    
+    .o_write_data                       ( write_data                        ),
+    .o_copro_write_data                 ( copro_write_data                  ),
+    .o_address                          ( execute_address                   ),
+    .o_address_valid                    ( execute_address_valid             ),
+    .o_address_nxt                      ( execute_address_nxt               ),
+    .o_adex                             ( adex                              ),
+
+    .o_byte_enable                      ( byte_enable                       ),
+    .o_data_access                      ( data_access                       ),
+    .o_write_enable                     ( write_enable                      ),
+    .o_exclusive                        ( exclusive                         ),
+    .o_priviledged                      ( priviledged                       ),
+    .o_status_bits                      ( execute_status_bits               ),
+    .o_multiply_done                    ( multiply_done                     ),
+
+    .i_fetch_stall                      ( fetch_stall                       ),   
+    .i_status_bits_mode                 ( status_bits_mode                  ),   
+    .i_status_bits_irq_mask             ( status_bits_irq_mask              ),   
+    .i_status_bits_firq_mask            ( status_bits_firq_mask             ),   
+    .i_imm32                            ( imm32                             ),   
+    .i_imm_shift_amount                 ( imm_shift_amount                  ),   
+    .i_shift_imm_zero                   ( shift_imm_zero                    ),   
+    .i_condition                        ( condition                         ),   
+    .i_exclusive_exec                   ( exclusive_exec                    ),   
+    .i_data_access_exec                 ( data_access_exec                  ),   
+    .i_rm_sel                           ( rm_sel                            ),   
+    .i_rds_sel                          ( rds_sel                           ),   
+    .i_rn_sel                           ( rn_sel                            ),   
+    .i_rm_sel_nxt                       ( rm_sel_nxt                        ),
+    .i_rds_sel_nxt                      ( rds_sel_nxt                       ),
+    .i_rn_sel_nxt                       ( rn_sel_nxt                        ),
+    .i_barrel_shift_amount_sel          ( barrel_shift_amount_sel           ),   
+    .i_barrel_shift_data_sel            ( barrel_shift_data_sel             ),   
+    .i_barrel_shift_function            ( barrel_shift_function             ),   
+    .i_use_carry_in                     ( use_carry_in                      ),
+    .i_alu_function                     ( alu_function                      ),   
+    .i_multiply_function                ( multiply_function                 ),   
+    .i_interrupt_vector_sel             ( interrupt_vector_sel              ),   
+    .i_address_sel                      ( address_sel                       ),   
+    .i_pc_sel                           ( pc_sel                            ),   
+    .i_byte_enable_sel                  ( byte_enable_sel                   ),   
+    .i_status_bits_sel                  ( status_bits_sel                   ),   
+    .i_reg_write_sel                    ( reg_write_sel                     ),   
+    .i_user_mode_regs_load              ( user_mode_regs_load               ),   
+    .i_user_mode_regs_store_nxt         ( user_mode_regs_store_nxt          ),   
+    .i_firq_not_user_mode               ( firq_not_user_mode                ),   
+    .i_write_data_wen                   ( write_data_wen                    ),   
+    .i_base_address_wen                 ( base_address_wen                  ),   
+    .i_pc_wen                           ( pc_wen                            ),   
+    .i_reg_bank_wen                     ( reg_bank_wen                      ),   
+    .i_reg_bank_wsel                    ( reg_bank_wsel                     ),
+    .i_status_bits_flags_wen            ( status_bits_flags_wen             ),   
+    .i_status_bits_mode_wen             ( status_bits_mode_wen              ),   
+    .i_status_bits_irq_mask_wen         ( status_bits_irq_mask_wen          ),   
+    .i_status_bits_firq_mask_wen        ( status_bits_firq_mask_wen         ),   
+    .i_copro_write_data_wen             ( copro_write_data_wen              )
+);
+
+
+a23_coprocessor u_coprocessor (
+    .i_clk                              ( i_clk                             ),
+    
+    .i_fetch_stall                      ( fetch_stall                       ),
+    .i_copro_opcode1                    ( copro_opcode1                     ),
+    .i_copro_opcode2                    ( copro_opcode2                     ),
+    .i_copro_crn                        ( copro_crn                         ),    
+    .i_copro_crm                        ( copro_crm                         ),
+    .i_copro_num                        ( copro_num                         ),
+    .i_copro_operation                  ( copro_operation                   ),
+    .i_copro_write_data                 ( copro_write_data                  ),
+    
+    .i_fault                            ( decode_fault                      ),
+    .i_fault_status                     ( decode_fault_status               ),
+    .i_fault_address                    ( decode_fault_address              ), 
+    
+    .o_copro_read_data                  ( copro_read_data                   ),
+    .o_cache_enable                     ( cache_enable                      ),
+    .o_cache_flush                      ( cache_flush                       ),
+    .o_cacheable_area                   ( cacheable_area                    )
+);
+
+
+endmodule
+
+"
+"//////////////////////////////////////////////////////////////////
+//                                                              //
+//  Wrapper for Xilinx Spartan-6 RAM Block                      //
+//                                                              //
+//  This file is part of the Amber project                      //
+//  http://www.opencores.org/project,amber                      //
+//                                                              //
+//  Description                                                 //
+//  256 words x 21 bits with a single write enable              //
+//                                                              //
+//  Author(s):                                                  //
+//      - Conor Santifort, csantifort.amber@gmail.com           //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+//                                                              //
+// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
+//                                                              //
+// This source file may be used and distributed without         //
+// restriction provided that this copyright statement is not    //
+// removed from the file and that any derivative work contains  //
+// the original copyright notice and the associated disclaimer. //
+//                                                              //
+// This source file is free software; you can redistribute it   //
+// and/or modify it under the terms of the GNU Lesser General   //
+// Public License as published by the Free Software Foundation; //
+// either version 2.1 of the License, or (at your option) any   //
+// later version.                                               //
+//                                                              //
+// This source is distributed in the hope that it will be       //
+// useful, but WITHOUT ANY WARRANTY; without even the implied   //
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
+// PURPOSE.  See the GNU Lesser General Public License for more //
+// details.                                                     //
+//                                                              //
+// You should have received a copy of the GNU Lesser General    //
+// Public License along with this source; if not, download it   //
+// from http://www.opencores.org/lgpl.shtml                     //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+
+
+module xs6_sram_256x21_line_en
+#(
+parameter DATA_WIDTH         = 21,
+parameter INITIALIZE_TO_ZERO = 0,
+parameter ADDRESS_WIDTH      = 8
+)
+
+(
+input                           i_clk,
+input      [DATA_WIDTH-1:0]     i_write_data,
+input                           i_write_enable,
+input      [ADDRESS_WIDTH-1:0]  i_address,
+output     [DATA_WIDTH-1:0]     o_read_data
+);                                                     
+
+
+wire [15:0] read_data_lo, read_data_hi;
+
+assign o_read_data = { read_data_hi[12:8], read_data_hi[4:0],
+                       read_data_lo[12:8], read_data_lo[5:0] };
+ 
+RAMB8BWER #(
+    .DATA_WIDTH_A        ( 36                   ),
+    .DATA_WIDTH_B        ( 36                   ),
+    .RAM_MODE            ( ""SDP""                ),
+    .SIM_COLLISION_CHECK ( ""GENERATE_X_ONLY""    ),
+    .WRITE_MODE_A        ( ""READ_FIRST""         ),
+    .WRITE_MODE_B        ( ""READ_FIRST""         )
+ ) 
+u_ramb8bwer (
+    .CLKAWRCLK      ( i_clk                                                   ),      
+    .CLKBRDCLK      ( i_clk                                                   ),
+    .ADDRAWRADDR    ( {i_address, 5\'d0}                                       ),
+    .ADDRBRDADDR    ( {i_address, 5\'d0}                                       ),
+    .ENAWREN        ( i_write_enable                                          ),       
+    .ENBRDEN        ( ~i_write_enable                                         ),
+    .WEAWEL         ( {2{i_write_enable}}                                     ),  
+    .WEBWEU         ( {2{i_write_enable}}                                     ),
+    .DIADI          ( {3\'d0, i_write_data[10: 6], 2\'d0, i_write_data[ 5: 0] } ), 
+    .DOADO          ( read_data_lo                                            ),
+    .DIBDI          ( {3\'d0, i_write_data[20:16], 3\'d0, i_write_data[15:11] } ),
+    .DOBDO          ( read_data_hi                                            ),
+
+    // These guys are not used, so they are just tied off
+    // ----------------------------------------------------
+    .DIPBDIP        ( 2\'d0                                                    ),
+    .DIPADIP        ( 2\'d0                                                    ), 
+    .DOPADOP        (                                                         ),
+    .DOPBDOP        (                                                         ),
+  
+    .REGCEA         ( 1\'d0                                                    ),
+    .REGCEBREGCE    ( 1\'d0                                                    ),
+    .RSTA           ( 1\'d0                                                    ),
+    .RSTBRST        ( 1\'d0                                                    )
+);
+
+
+//synopsys translate_off
+initial
+    begin
+    if ( DATA_WIDTH    != 21  ) $display(""%M Warning: Incorrect parameter DATA_WIDTH"");
+    if ( ADDRESS_WIDTH != 8   ) $display(""%M Warning: Incorrect parameter ADDRESS_WIDTH"");
+    end
+//synopsys translate_on
+
+endmodule
+
+
+"
+"module LX9Co_BIST (
+
+\toutput [18:0] ram_addr,
+\tinout [31:0] ram_data,
+\toutput reg ram_wr,
+\toutput reg ram_oe,
+\toutput ram_cs,
+\toutput ram_ub_b,
+\toutput ram_lb_b,
+\t
+\tinput [2:0] h_addr,
+\tinout [7:0] h_data,
+\tinput h_phi2,
+\tinput h_cs_b,
+\tinput h_pwr,
+\tinput h_rdnw,
+\tinput h_rst_b,
+\t
+    input fastclk,
+    output [8:1] test,
+    input [3:0] sw,
+\toutput h_irq_b
+  );
+
+   parameter TOP_ADDR = 19'h07ffff;\t\t// Maximum RAM value (512k words)
+
+  dcm_32_16 dcm (
+    .CLKIN_IN(fastclk), 
+    .CLK0_OUT(CLK0_OUT), 
+    .CLK0_OUT1(), 
+    .CLK2X_OUT()
+    );
+\t
+\t
+reg [18:0] addr_cnt =19'h000000;
+wire [31:0] test_data;
+wire [7:0] test_out;
+reg cnt_rst;
+reg w_rst;
+reg r_rst;
+
+assign ram_cs = 1'b0;
+assign ram_ub_b = 1'b0;
+assign ram_lb_b = 1'b0;
+assign ram_addr = addr_cnt;
+assign test_out = (state == 4) ? 8'h55 : addr_cnt[18:11];\t\t\t\t\t\t\t\t// Display 01010101 whilst zeroing RAM out for visual confirmation
+assign test_data = (state == 4) ? 32'h000000000000 : {addr_cnt[15:0],addr_cnt[15:0]}; \t// State 4 zeros memory : state 2 fills with a pattern based on the address
+assign ram_data = (state == 2 || state == 4) ? test_data : 32'hzzzzzzzz;\t\t\t\t// state 2 and state 4 we're writing to RAM, else HiZ
+assign test = (sw[3]==1'b0) ? test_out: tubes[sw[2:0]] ;\t\t\t\t\t\t\t\t// Either show RAM test progress OR show one of the Tube registers on the LEDs
+  
+//////
+// RAM test - other than the MUX to the LEDs there is no connection to the Tube registers
+//////
+  
+reg [4:0]     state = 0;
+reg [4:0]     next_state;
+always @(loop or addr_cnt or state or pass)
+   begin: COMB
+
+      case (state)
+      
+         1:\t\t\t\t\t\t\t\t\t// Idle
+            begin
+               if (loop==4'b1111)
+                  begin
+                     next_state  = 2;
+\t\t\t\t\t cnt_rst = 0;
+\t\t\t\t\t w_rst = 0;\t\t\t\t// Stop resetting the write state machine.
+\t\t\t\t\t r_rst = 1;
+                  end
+               else
+                  begin
+                     next_state  = 1;
+\t\t\t\t\t cnt_rst = 1;
+\t\t\t\t\t w_rst = 1;
+\t\t\t\t\t r_rst = 1;
+                  end
+            end
+            
+         2:\t\t\t\t\t\t\t\t\t// Filling memory
+            begin
+               if (addr_cnt==TOP_ADDR)\t\t// If the counter has completed, reset it and move to reading back
+                  begin
+                     next_state  = 3;
+\t\t\t\t\t cnt_rst = 1;
+\t\t\t\t\t w_rst = 1;
+\t\t\t\t\t r_rst = 1;
+                  end
+               else
+                  begin
+                     next_state  = 2;
+\t\t\t\t\t cnt_rst = 0;
+\t\t\t\t\t w_rst = 0;\t\t\t\t// Stop resetting the write state machine.
+\t\t\t\t\t r_rst = 1;
+                  end
+            end
+
+         3:\t\t\t\t\t\t\t\t\t// Reading back
+            begin
+\t\t\tif (addr_cnt==TOP_ADDR)\t\t// If the counter has completed, reset it and proceed to Zero memory
+                  begin
+                     next_state  = 4;
+\t\t\t\t\t cnt_rst = 1;
+\t\t\t\t\t w_rst = 1;
+\t\t\t\t\t r_rst = 1;
+                  end
+               else
+\t\t\t     begin
+\t\t\t\t  if (pass == 1'b1)
+                  begin\t\t\t\t\t\t// Continue to verify
+                     next_state  = 3;
+\t\t\t\t\t cnt_rst = 0;
+\t\t\t\t\t w_rst = 1;\t\t\t\t
+\t\t\t\t\t r_rst = 0;\t\t\t\t// Stop resetting the read state machine.
+                  end else begin\t\t\t// Read back borked, proceed to NOT OK
+\t\t\t\t     next_state  = 5;
+\t\t\t\t\t cnt_rst = 0;
+\t\t\t\t\t w_rst = 1;\t\t\t\t
+\t\t\t\t\t r_rst = 1;\t\t\t\t
+\t\t\t\t  end
+\t\t\t\t end
+            end
+
+\t\t4:\t\t\t\t\t\t\t\t\t// Readback was OK, now zero out
+\t\t\tbegin
+               if (addr_cnt==TOP_ADDR)\t\t// If the counter has completed, reset it and move to refilling with data
+                  begin
+                     next_state  = 1;
+\t\t\t\t\t cnt_rst = 1;
+\t\t\t\t\t w_rst = 1;
+\t\t\t\t\t r_rst = 1;
+                  end
+               else
+                  begin
+                     next_state  = 4;
+\t\t\t\t\t cnt_rst = 0;
+\t\t\t\t\t w_rst = 0;\t\t\t\t// Stop resetting the write state machine.
+\t\t\t\t\t r_rst = 1;
+                  end
+\t\t\tend
+\t\t5:\t\t\t\t\t\t\t\t\t// NOT OK
+\t\t\tbegin
+\t\t\t\tnext_state  = 5;
+\t\t\t\tcnt_rst = 0;
+\t\t\t\tw_rst = 1;
+\t\t\t\tr_rst = 1;
+\t\t\tend
+          
+        default:
+            begin
+                     next_state  = 1;
+\t\t\t\t\t cnt_rst = 1;
+\t\t\t\t\t w_rst = 1;
+\t\t\t\t\t r_rst = 1;
+            end
+
+      endcase
+   end
+
+
+
+always@(posedge CLK0_OUT)\t\t\t
+begin
+\tif (cnt_rst)
+\tbegin
+\t\taddr_cnt <= 19'h000000;
+\tend\telse begin
+\t\tif (w_inc || r_inc)
+\t\tbegin
+\t\t\taddr_cnt <= addr_cnt + 19'h000001;
+\t\tend else begin
+\t\t\tcase (state)
+\t\t\t//4:
+\t\t\t//\taddr_cnt <= 19'h555555;\t\t// OK pattern
+\t\t\t5:
+\t\t\t\taddr_cnt <= 19'h333333;\t\t// Fail pattern
+\t\t\tdefault:
+\t\t\t\taddr_cnt <= addr_cnt;
+\t\t\tendcase
+\t\tend
+\tend\t
+end
+
+reg pass;
+reg r_inc;
+reg [1:0] r_delay;
+always@(posedge CLK0_OUT)\t\t\t// 4 phase read memory\t\t\t
+begin
+\tif (r_rst)
+\tbegin
+\t\tr_inc <= 1'b0;
+\t\tr_delay <= 2'b00;
+\t\tram_oe <= 1'b1;
+\t\tpass <= 1'b1;
+\tend\telse begin
+\t\tr_delay <= r_delay + 2'b01;
+\t\tcase (r_delay)
+\t\t2'b00:\t\t\t\t// Allow A and D to settle
+\t\t\tbegin
+\t\t\t\tram_oe <= 1'b1;
+\t\t\t\tr_inc <= 1'b0;
+\t\t\t\tpass <= pass;
+\t\t\tend
+\t\t2'b01:\t\t\t\t// Pulse OE low
+\t\t\tbegin
+\t\t\t\tram_oe <= 1'b0;
+\t\t\t\tr_inc <= 1'b0;
+\t\t\t\tpass <= pass;
+\t\t\tend
+\t\t2'b10:\t\t\t\t// Bring WE high
+\t\t\tbegin
+\t\t\t\tram_oe <= 1'b1;
+\t\t\t\tr_inc <= 1'b0;
+\t\t\t\tif (ram_data == test_data)\t\t// Read Data OK or fail ?
+\t\t\t\t//if (ram_data[15:0] == test_data[15:0])
+\t\t\t\t\tpass <= pass;
+\t\t\t\telse
+\t\t\t\t\tpass <= 1'b0;
+\t\t\tend
+\t\t2'b11:
+\t\t\tbegin\t\t\t// Advance address
+\t\t\t\tram_oe <= 1'b1;
+\t\t\t\tr_inc <= 1'b1;
+\t\t\t\tpass <= pass;
+\t\t\tend
+\t\tendcase
+\tend\t
+end
+
+reg w_inc;
+reg [1:0] w_delay;
+always@(posedge CLK0_OUT)\t\t\t// 4 phase write memory\t\t\t
+begin
+\tif (w_rst)
+\tbegin
+\t\tw_inc <= 1'b0;
+\t\tw_delay <= 2'b00;
+\t\tram_wr <= 1'b1;
+\tend\telse begin
+\t\tw_delay <= w_delay + 2'b01;
+\t\tcase (w_delay)
+\t\t2'b00:\t\t\t\t// Allow A and D to settle
+\t\t\tbegin
+\t\t\t\tram_wr <= 1'b1;
+\t\t\t\tw_inc <= 1'b0;
+\t\t\tend
+\t\t2'b01:\t\t\t\t// Pulse WE low
+\t\t\tbegin
+\t\t\t\tram_wr <= 1'b0;
+\t\t\t\tw_inc <= 1'b0;
+\t\t\tend
+\t\t2'b10:\t\t\t\t// Bring WE high
+\t\t\tbegin
+\t\t\t\tram_wr <= 1'b1;
+\t\t\t\tw_inc <= 1'b0;
+\t\t\tend
+\t\t2'b11:
+\t\t\tbegin\t\t\t// Advance address
+\t\t\t\tram_wr <= 1'b1;
+\t\t\t\tw_inc <= 1'b1;
+\t\t\tend
+\t\tendcase
+\tend\t
+end
+
+
+reg [3:0] loop = 4'b0000;
+always@(posedge CLK0_OUT)\t\t\t// Give a bit of delay before starting the statemachine
+begin
+\tif (loop!= 4'b1111)
+\tbegin
+\t\tloop <= loop + 4'b0001;
+\t\tstate <= 1;
+\tend\telse begin
+\t\tstate <= next_state;
+\tend
+\t
+end
+
+
+//////
+// Tube registers - other than the MUX to the LEDs there is no connection to the RAM test
+//////
+
+reg [7:0] tubes [0:7];\t\t// 8 registers that just cache values for testing the host interface
+
+// Data out for reads\t
+assign h_data = (h_rdnw == 1 && h_cs_b == 0 && h_phi2) ? tubes[h_addr] : 8'hzz;
+
+// Data in for writes
+always@(negedge h_phi2)
+begin
+\tif (h_rdnw == 0 && h_cs_b == 0)
+\t\tif (h_addr == 3'b000)
+\t\t  tubes[h_addr] <= 8'hfe;\t\t// Otherwise the Beeb won't boot
+\t\telse 
+\t\t  tubes[h_addr] <= h_data;
+\telse
+\t\ttubes[h_addr] <= tubes[h_addr];\t
+end        
+
+assign h_irq_b = 1'bz;
+        
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+"
+"/*
+ *  8-bit rotate module for Zet
+ *  Copyright (C) 2008-2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+module zet_rxr8 (
+    input      [7:0] x,
+    input            ci,
+    input      [3:0] y,
+    input            e,
+    output reg [7:0] w,
+    output reg       co
+  );
+
+  always @(x or ci or y or e)
+    case (y)
+      default: {co,w} <= {ci,x};
+      5'd01: {co,w} <= e ? {x[0], ci, x[7:1]} : {ci, x[0], x[7:1]};
+      5'd02: {co,w} <= e ? {x[1:0], ci, x[7:2]} : {ci, x[1:0], x[7:2]};
+      5'd03: {co,w} <= e ? {x[2:0], ci, x[7:3]} : {ci, x[2:0], x[7:3]};
+      5'd04: {co,w} <= e ? {x[3:0], ci, x[7:4]} : {ci, x[3:0], x[7:4]};
+      5'd05: {co,w} <= e ? {x[4:0], ci, x[7:5]} : {ci, x[4:0], x[7:5]};
+      5'd06: {co,w} <= e ? {x[5:0], ci, x[7:6]} : {ci, x[5:0], x[7:6]};
+      5'd07: {co,w} <= e ? {x[6:0], ci, x[7]} : {ci, x[6:0], x[7]};
+      5'd08: {co,w} <= {x,ci};
+    endcase
+endmodule
+"
+"`timescale 1ns / 1ns
+
+module ph_fifo (
+                input h_rst_b,
+                input h_rd,
+                input h_selectData,
+                input h_phi2,
+                input [7:0] p_data,                  
+                input p_selectData,
+                input p_phi2,
+                input p_rdnw,
+                output [7:0] h_data,                  
+                output h_data_available,
+                output p_full
+                );
+   
+wire fifo_rst;
+wire fifo_wr_clk; 
+wire fifo_rd_clk; 
+wire [7:0] fifo_din; 
+wire fifo_wr_en; 
+wire fifo_rd_en; 
+wire [7:0] fifo_dout; 
+wire fifo_full;
+wire fifo_empty;
+
+`ifdef SPARTAN3
+ph_fifo_core_spartan3 ph_fifo_core (
+`else
+ph_fifo_core_spartan6 ph_fifo_core (
+`endif
+  .rst(fifo_rst),       // input rst
+  .wr_clk(fifo_wr_clk), // input wr_clk
+  .rd_clk(fifo_rd_clk), // input rd_clk
+  .din(fifo_din),       // input [7 : 0] din
+  .wr_en(fifo_wr_en),   // input wr_en
+  .rd_en(fifo_rd_en),   // input rd_en
+  .dout(fifo_dout),     // output [7 : 0] dout
+  .full(fifo_full),     // output full
+  .empty(fifo_empty)    // output empty
+);
+
+assign fifo_rst = ~h_rst_b;
+
+// Parasite
+assign fifo_din = p_data;
+assign p_full = fifo_full;
+assign fifo_wr_clk = p_phi2;
+assign fifo_wr_en = p_selectData & ~p_rdnw;
+
+// Host
+assign fifo_rd_clk = ~h_phi2;
+assign fifo_rd_en = h_selectData & h_rd;
+assign h_data = fifo_empty ? 8'hAA : fifo_dout;
+assign h_data_available = ~fifo_empty;
+
+endmodule // ph_fifo
+
+   
+"
+"//////////////////////////////////////////////////////////////////////////////////\r
+//\r
+// This file is part of the NextZ80 project
+// http://www.opencores.org/cores/nextz80/
+//\r
+// Filename: NextZ80ALU.v\r
+// Description: Implementation of Z80 compatible CPU - ALU\r
+// Version 1.0\r
+// Creation date: 28Jan2011 - 18Mar2011\r
+//\r
+// Author: Nicolae Dumitrache \r
+// e-mail: ndumitrache@opencores.org\r
+//
+/////////////////////////////////////////////////////////////////////////////////
+// 
+// Copyright (C) 2011 Nicolae Dumitrache
+// 
+// This source file may be used and distributed without 
+// restriction provided that this copyright statement is not 
+// removed from the file and that any derivative work contains 
+// the original copyright notice and the associated disclaimer.
+// 
+// This source file is free software; you can redistribute it 
+// and/or modify it under the terms of the GNU Lesser General 
+// Public License as published by the Free Software Foundation;
+// either version 2.1 of the License, or (at your option) any 
+// later version. 
+// 
+// This source is distributed in the hope that it will be 
+// useful, but WITHOUT ANY WARRANTY; without even the implied 
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
+// PURPOSE. See the GNU Lesser General Public License for more 
+// details. 
+// 
+// You should have received a copy of the GNU Lesser General 
+// Public License along with this source; if not, download it 
+// from http://www.opencores.org/lgpl.shtml 
+// \r
+///////////////////////////////////////////////////////////////////////////////////\r
+\r
+//FLAGS: S Z X1 N X2 PV N C\r
+//\tOP[4:0]\r
+//\t00000\t-\tADD\tD0,D1\r
+//\t00001\t-\tADC\tD0,D1\r
+//\t00010\t-\tSUB\tD0,D1\r
+//\t00011\t-\tSBC\tD0,D1\r
+//\t00100\t-\tAND\tD0,D1\r
+//\t00101\t-\tXOR\tD0,D1\r
+//\t00110\t-\tOR\t\tD0,D1\r
+//\t00111\t-\tCP\t\tD0,D1\r
+//\t01000\t-\tINC\tD0\r
+//\t01001\t-\tCPL\tD0\r
+// 01010\t-\tDEC\tD0\r
+//\t01011\t-\tRRD\r
+// 01100\t-\tRLD\r
+//\t01101\t-\tDAA\r
+//\t01110\t-\tINC16\r
+//\t01111\t-  DEC16\r
+// 10000\t-\tADD16LO\r
+//\t10001\t-\tADD16HI\r
+//\t10010\t-\t\r
+//\t10011\t-\t\r
+//\t10100\t-\tCCF, pass D0\r
+// 10101\t-\tSCF, pass D0\r
+// 10110\t-\t\r
+//\t10111\t-\t\r
+//\t11000\t-\tRLCA\tD0\r
+//\t11001\t-\tRRCA\tD0\r
+//\t11010\t-\tRLA\tD0\r
+//\t11011\t- \tRRA\tD0\r
+//\t11100\t-\t{ROT, BIT, SET, RES} D0,EXOP \r
+//\t\t\t\t  RLC\t\tD0\t\t\tC <-- D0 <-- D0[7]\r
+//            RRC\t\tD0\t\t\tD0[0] --> D0 --> C\r
+//            RL\t\tD0\t\t\tC <-- D0 <-- C\r
+//            RR\t\tD0\t\t\tC --> D0 --> C\r
+//            SLA\t\tD0\t\t\tC <-- D0 <-- 0\r
+//            SRA\t\tD0\t\t\tD0[7] --> D0 --> C\r
+//            SLL\t\tD0\t\t\tC <-- D0 <-- 1\r
+//            SRL\t\tD0\t\t\t0 --> D0 --> C\r
+//\t11101\t-\tIN, pass D1\r
+//\t11110\t-\tFLAGS <- D0\r
+//\t11111\t-\tNEG\tD1\t\r
+///////////////////////////////////////////////////////////////////////////////////\r
+`timescale 1ns / 1ps\r
+\r
+module ALU8(\r
+    input [7:0] D0,\r
+    input [7:0] D1,\r
+\t input [7:0] FIN,\r
+    output reg[7:0] FOUT,\r
+    output reg [15:0] ALU8DOUT,\r
+    input [4:0] OP,\r
+\t input [5:0] EXOP, // EXOP[5:4] = 2'b11 for CPI/D/R\r
+\t input LDIFLAGS,\t // zero HF and NF on inc/dec16\r
+\t input DSTHI\t\t // destination lo\r
+    );\r
+\t\r
+\twire [7:0] daaadjust;\r
+\twire cdaa, hdaa;\r
+\tdaa daa_adjust(.flags(FIN), .val(D0), .adjust(daaadjust), .cdaa(cdaa), .hdaa(hdaa));\r
+\t\r
+\twire parity = ~^ALU8DOUT[15:8];\r
+\twire zero = ALU8DOUT[15:8] == 0;\r
+\treg csin, cin;\r
+\twire [7:0]d0mux = OP[4:1] == 4'b1111 ? 0 : D0;\r
+\treg [7:0]_d1mux;\r
+\twire [7:0]d1mux = OP[1] ? ~_d1mux : _d1mux;\r
+\twire [8:0]sum;\r
+\twire hf;\r
+\tassign {hf, sum[3:0]} = d0mux[3:0] + d1mux[3:0] + cin;\r
+\tassign sum[8:4] = d0mux[7:4] + d1mux[7:4] + hf;\r
+\twire overflow = (d0mux[7] & d1mux[7] & !sum[7]) | (!d0mux[7] & !d1mux[7] & sum[7]);\r
+\treg [7:0]dbit;\r
+\r
+\talways @* begin\r
+\t\tALU8DOUT = 16'hxxxx;\r
+\t\tFOUT = 8'hxx;\r
+\t\tcase({OP[4:2]})\r
+\t\t\t0,1,4,7: _d1mux = D1;\r
+\t\t\t2: _d1mux = 1;\r
+\t\t\t3: _d1mux = daaadjust;\t\t// DAA\r
+\t\t\t6,5: _d1mux = 8'hxx;\r
+\t\tendcase\r
+\t\tcase({OP[2:0], FIN[0]})\r
+\t\t\t0,1,2,7,8,9,10,11,12,13:\tcin = 0;\r
+\t\t\t3,4,5,6,14,15: cin = 1;\r
+\t\tendcase\r
+\t\tcase(EXOP[3:0])\r
+\t\t\t0: dbit =  8'b11111110;\r
+\t\t\t1: dbit =  8'b11111101;\r
+\t\t\t2: dbit =  8'b11111011;\r
+\t\t\t3: dbit =  8'b11110111;\r
+\t\t\t4: dbit =  8'b11101111;\r
+\t\t\t5: dbit =  8'b11011111;\r
+\t\t\t6: dbit =  8'b10111111;\r
+\t\t\t7: dbit =  8'b01111111;\r
+\t\t\t8: dbit =  8'b00000001;\r
+\t\t\t9: dbit =  8'b00000010;\r
+\t\t\t10: dbit = 8'b00000100;\r
+\t\t\t11: dbit = 8'b00001000;\r
+\t\t\t12: dbit = 8'b00010000;\r
+\t\t\t13: dbit = 8'b00100000;\r
+\t\t\t14: dbit = 8'b01000000;\r
+\t\t\t15: dbit = 8'b10000000;\r
+\t\tendcase\r
+\t\tcase(OP[3] ? EXOP[2:0] : OP[2:0])\r
+\t\t\t0,5:\tcsin = D0[7];\r
+\t\t\t1: \tcsin = D0[0];\r
+\t\t\t2,3:\tcsin = FIN[0];\r
+\t\t\t4,7:\tcsin = 0;\r
+\t\t\t6:\t\tcsin = 1;\r
+\t\tendcase\r
+\t\tcase(OP[4:0])\r
+\t\t\t0,1,2,3,8,10:\tbegin\t\t// ADD, ADC, SUB, SBC, INC, DEC\r
+\t\t\t\tALU8DOUT[15:8] = sum[7:0];\r
+\t\t\t\tALU8DOUT[7:0] = sum[7:0];\r
+\t\t\t\tFOUT[0] = OP[3] ? FIN[0] : (sum[8] ^ OP[1]); // inc/dec\r
+\t\t\t\tFOUT[1] = OP[1];\r
+\t\t\t\tFOUT[2] = overflow;\r
+\t\t\t\tFOUT[3] = ALU8DOUT[11];\r
+\t\t\t\tFOUT[4] = hf ^ OP[1];\r
+\t\t\t\tFOUT[5] = ALU8DOUT[13];\r
+\t\t\t\tFOUT[6] = zero & (FIN[6] | ~EXOP[5] | ~DSTHI | OP[3]); //(EXOP[5] & DSTHI) ? (zero & FIN[6]) : zero;\t\t\t\t// adc16/sbc16\r
+\t\t\t\tFOUT[7] = ALU8DOUT[15];\r
+\t\t\tend\r
+\t\t\t16,17:\tbegin\t\t// ADD16LO, ADD16HI\r
+\t\t\t\tALU8DOUT[15:8] = sum[7:0];\r
+\t\t\t\tALU8DOUT[7:0] = sum[7:0];\r
+\t\t\t\tFOUT[0] = sum[8];\r
+\t\t\t\tFOUT[1] = OP[1];\r
+\t\t\t\tFOUT[2] = FIN[2];\r
+\t\t\t\tFOUT[3] = ALU8DOUT[11];\r
+\t\t\t\tFOUT[4] = hf ^ OP[1];\r
+\t\t\t\tFOUT[5] = ALU8DOUT[13];\r
+\t\t\t\tFOUT[6] = FIN[6];\r
+\t\t\t\tFOUT[7] = FIN[7];\r
+\t\t\tend\r
+\t\t\t7: begin\t\t// CP\r
+\t\t\t\tALU8DOUT[15:8] = sum[7:0];\r
+\t\t\t\tFOUT[0] = EXOP[5] ? FIN[0] : !sum[8]; // CPI/D/R\r
+\t\t\t\tFOUT[1] = OP[1];\r
+\t\t\t\tFOUT[2] = overflow;\r
+\t\t\t\tFOUT[3] = D1[3];\r
+\t\t\t\tFOUT[4] = !hf;\r
+\t\t\t\tFOUT[5] = D1[5];\r
+\t\t\t\tFOUT[6] = zero;\r
+\t\t\t\tFOUT[7] = ALU8DOUT[15];\r
+\t\t\tend\r
+\t\t\t31:\tbegin\t\t// NEG\r
+\t\t\t\tALU8DOUT[15:8] = sum[7:0];\r
+\t\t\t\tFOUT[0] = !sum[8];\r
+\t\t\t\tFOUT[1] = OP[1];\r
+\t\t\t\tFOUT[2] = overflow;\r
+\t\t\t\tFOUT[3] = ALU8DOUT[11];\r
+\t\t\t\tFOUT[4] = !hf;\r
+\t\t\t\tFOUT[5] = ALU8DOUT[13];\r
+\t\t\t\tFOUT[6] = zero;\r
+\t\t\t\tFOUT[7] = ALU8DOUT[15];\r
+\t\t\tend\r
+\t\t\t4: begin\t\t\t// AND\r
+\t\t\t\tALU8DOUT[15:8] = D0 & D1;\r
+\t\t\t\tFOUT[0] = 0;\r
+\t\t\t\tFOUT[1] = 0;\r
+\t\t\t\tFOUT[2] = parity;\r
+\t\t\t\tFOUT[3] = ALU8DOUT[11];\r
+\t\t\t\tFOUT[4] = 1;\r
+\t\t\t\tFOUT[5] = ALU8DOUT[13];\r
+\t\t\t\tFOUT[6] = zero;\r
+\t\t\t\tFOUT[7] = ALU8DOUT[15];\r
+\t\t\tend\r
+\t\t\t5,6: begin\t\t//XOR, OR\r
+\t\t\t\tALU8DOUT[15:8] = OP[0] ? (D0 ^ D1) : (D0 | D1);\r
+\t\t\t\tFOUT[0] = 0;\r
+\t\t\t\tFOUT[1] = 0;\r
+\t\t\t\tFOUT[2] = parity;\r
+\t\t\t\tFOUT[3] = ALU8DOUT[11];\r
+\t\t\t\tFOUT[4] = 0;\r
+\t\t\t\tFOUT[5] = ALU8DOUT[13];\r
+\t\t\t\tFOUT[6] = zero;\r
+\t\t\t\tFOUT[7] = ALU8DOUT[15];\r
+\t\t\tend\r
+\t\t\t9: begin\t\t\t// CPL\r
+\t\t\t\tALU8DOUT[15:8] = ~D0;\r
+\t\t\t\tFOUT[0] = FIN[0];\r
+\t\t\t\tFOUT[1] = 1;\r
+\t\t\t\tFOUT[2] = FIN[2];\r
+\t\t\t\tFOUT[3] = ALU8DOUT[11];\r
+\t\t\t\tFOUT[4] = 1;\r
+\t\t\t\tFOUT[5] = ALU8DOUT[13];\r
+\t\t\t\tFOUT[7:6] = FIN[7:6];\r
+\t\t\tend\r
+\t\t\t11,12: begin\t\t\t\t\t// RLD, RRD\r
+\t\t\t\tif(OP[0]) ALU8DOUT = {D0[7:4], D1[3:0], D0[3:0], D1[7:4]};\r
+\t\t\t\telse ALU8DOUT = {D0[7:4], D1[7:0], D0[3:0]};\r
+\t\t\t\tFOUT[0] = FIN[0];\r
+\t\t\t\tFOUT[1] = 0;\r
+\t\t\t\tFOUT[2] = parity;\r
+\t\t\t\tFOUT[3] = ALU8DOUT[11];\r
+\t\t\t\tFOUT[4] = 0;\r
+\t\t\t\tFOUT[5] = ALU8DOUT[13];\r
+\t\t\t\tFOUT[6] = zero;\r
+\t\t\t\tFOUT[7] = ALU8DOUT[15];\r
+\t\t\tend\t\t\t\r
+\t\t\t13: begin\t// DAA\r
+\t\t\t\tALU8DOUT[15:8] = sum[7:0];\r
+\t\t\t\tFOUT[0] = cdaa;\r
+\t\t\t\tFOUT[1] = FIN[1];\r
+\t\t\t\tFOUT[2] = parity;\r
+\t\t\t\tFOUT[3] = ALU8DOUT[11];\r
+\t\t\t\tFOUT[4] = hdaa;\r
+\t\t\t\tFOUT[5] = ALU8DOUT[13];\r
+\t\t\t\tFOUT[6] = zero;\r
+\t\t\t\tFOUT[7] = ALU8DOUT[15];\r
+\t\t\tend\r
+\t\t\t14,15: begin\t// inc/dec 16\r
+\t\t\t\tALU8DOUT = {D0, D1} + (OP[0] ? 16'hffff : 16'h0001);\r
+\t\t\t\tFOUT[0] = FIN[0];\r
+\t\t\t\tFOUT[1] = LDIFLAGS ? 1'b0 : FIN[1];\r
+\t\t\t\tFOUT[2] = ALU8DOUT != 0;\r
+\t\t\t\tFOUT[3] = FIN[3];\r
+\t\t\t\tFOUT[4] = LDIFLAGS ? 1'b0 : FIN[4];\r
+\t\t\t\tFOUT[5] = FIN[5];\r
+\t\t\t\tFOUT[6] = FIN[6];\r
+\t\t\t\tFOUT[7] = FIN[7];\r
+\t\t\tend\r
+\t\t\t20,21: begin\t\t// CCF, SCF\r
+\t\t\t\tALU8DOUT[15:8] = D0;\r
+\t\t\t\tFOUT[0] = OP[0] ? 1'b1 : !FIN[0];\r
+\t\t\t\tFOUT[1] = 1'b0;\r
+\t\t\t\tFOUT[2] = FIN[2];\r
+\t\t\t\tFOUT[3] = ALU8DOUT[11];\r
+\t\t\t\tFOUT[4] = OP[0] ? 1'b0 : FIN[0];\r
+\t\t\t\tFOUT[5] = ALU8DOUT[13];\r
+\t\t\t\tFOUT[6] = FIN[6];\r
+\t\t\t\tFOUT[7] = FIN[7];\t\t\t\t\r
+\t\t\tend\r
+\t\t\t24,25,26,27, 28: begin \t\t\t\t\t\t\t// ROT, BIT, RES, SET\r
+\t\t\t\tcase({OP[2], EXOP[4:3]})\r
+\t\t\t\t\t0,1,2,3,4:\t// rot - shift\r
+\t\t\t\t\t\tif(OP[2] ? EXOP[0] : OP[0]){ALU8DOUT[15:8], FOUT[0]} = {csin, D0};\t\t// right\r
+\t\t\t\t\t\telse\t\t\t\t\t\t\t \t{FOUT[0], ALU8DOUT[15:8]} = {D0, csin};\t\t// left\r
+\t\t\t\t\t5,6: begin\t// BIT, RES \r
+\t\t\t\t\t\tFOUT[0] = FIN[0]; \r
+\t\t\t\t\t\tALU8DOUT[15:8] = D0 & dbit; \r
+\t\t\t\t\tend\t\t\r
+\t\t\t\t\t7: begin \t// SET\r
+\t\t\t\t\t\tFOUT[0] = FIN[0]; \r
+\t\t\t\t\t\tALU8DOUT[15:8] = D0 | dbit; \r
+\t\t\t\t\tend\t\t\t\r
+\t\t\t\tendcase\r
+\t\t\t\tALU8DOUT[7:0] = ALU8DOUT[15:8];\r
+\t\t\t\tFOUT[1] = 0;\r
+\t\t\t\tFOUT[2] = OP[2] ? (EXOP[3] ? zero : parity) : FIN[2];\r
+\t\t\t\tFOUT[3] = ALU8DOUT[11];\r
+\t\t\t\tFOUT[4] = OP[2] & EXOP[3];\r
+\t\t\t\tFOUT[5] = ALU8DOUT[13];\r
+\t\t\t\tFOUT[6] = OP[2] ? zero : FIN[6];\r
+\t\t\t\tFOUT[7] = OP[2] ? ALU8DOUT[15] : FIN[7];\r
+\t\t\tend\r
+\t\t\t29:\tbegin\t\t// IN, pass D1\r
+\t\t\t\tALU8DOUT = {D1, D1};\r
+\t\t\t\tFOUT[0] = FIN[0];\r
+\t\t\t\tFOUT[1] = 0;\r
+\t\t\t\tFOUT[2] = parity;\r
+\t\t\t\tFOUT[3] = ALU8DOUT[11];\r
+\t\t\t\tFOUT[4] = 0;\r
+\t\t\t\tFOUT[5] = ALU8DOUT[13];\r
+\t\t\t\tFOUT[6] = zero;\r
+\t\t\t\tFOUT[7] = ALU8DOUT[15];\r
+\t\t\tend\r
+\t\t\t30: FOUT = D0;\t\t// FLAGS <- D0\r
+\t\t\tdefault:;\r
+\t\tendcase\r
+\tend\r
+endmodule\r
+\r
+module daa (\r
+\tinput [7:0]flags,\r
+\tinput [7:0]val,\r
+\toutput wire [7:0]adjust,\r
+\toutput reg cdaa,\r
+\toutput reg hdaa\r
+\t);\r
+\t\r
+\twire h08 = val[7:4] < 9;\r
+\twire h09 = val[7:4] < 10;\r
+\twire l05 = val[3:0] < 6;
+\twire l09 = val[3:0] < 10;\r
+\treg [1:0]aa;\r
+\tassign adjust = ({1'b0, aa[1], aa[1], 2'b0, aa[0], aa[0], 1'b0} ^ {8{flags[1]}}) + flags[1];\r
+\t\r
+\talways @* begin\r
+\t\tcase({flags[0], h08, h09, flags[4], l09})\r
+\t\t\t5'b00101, 5'b01101:\taa = 0;\r
+\t\t\t5'b00111, 5'b01111, 5'b01000, 5'b01010, 5'b01100, 5'b01110:\taa = 1;\r
+\t\t\t5'b00001, 5'b01001, 5'b10001, 5'b10101, 5'b11001, 5'b11101:\taa = 2;\r
+\t\t\tdefault: aa = 3;\r
+\t\tendcase\r
+\t\tcase({flags[0], h08, h09, l09})\r
+\t\t\t4'b0011, 4'b0111, 4'b0100, 4'b0110:\tcdaa = 0;\r
+\t\t\tdefault: cdaa = 1;\r
+\t\tendcase\r
+\t\tcase({flags[1], flags[4], l05, l09})\r
+\t\t\t4'b0000, 4'b0010, 4'b0100, 4'b0110, 4'b1110, 4'b1111:\thdaa = 1;\r
+\t\t\tdefault:\thdaa = 0;\r
+\t\tendcase\r
+\tend\r
+endmodule\r
+\r
+\r
+module ALU16(\r
+    input [15:0] D0,\r
+    input [7:0] D1,\r
+    output wire[15:0] DOUT,\r
+    input [2:0]OP\t// 0-NOP, 1-INC, 2-INC2, 3-ADD, 4-NOP, 5-DEC, 6-DEC2\r
+    );\r
+\t\r
+\treg [15:0] mux;\r
+\talways @*\r
+\t\tcase(OP)\r
+\t\t\t0: mux = 0;\t\t\t\t// post inc\r
+\t\t\t1: mux = 1;\t\t\t\t// post inc\r
+\t\t\t2: mux = 2;\t\t\t\t// post inc\r
+\t\t\t3: mux = {D1[7], D1[7], D1[7], D1[7], D1[7], D1[7], D1[7], D1[7], D1[7:0]};\t// post inc\r
+\t\t\t4: mux = 0;\t\t\t\t// no post inc\t\t\t\r
+\t\t\t5: mux = 16'hffff;\t// no post inc\r
+\t\t\t6: mux = 16'hfffe;\t// no post inc\r
+\t\t\tdefault: mux = 16'hxxxx;\r
+\t\tendcase\r
+\t\r
+\tassign DOUT = D0 + mux;\r
+endmodule\r
+"
+"//////////////////////////////////////////////////////////////////////////////////\r
+//\r
+// This file is part of the NextZ80 project
+// http://www.opencores.org/cores/nextz80/
+//\r
+// Filename: NextZ80CPU.v\r
+// Description: Implementation of Z80 compatible CPU\r
+// Version 1.0\r
+// Creation date: 28Jan2011 - 18Mar2011\r
+//\r
+// Author: Nicolae Dumitrache \r
+// e-mail: ndumitrache@opencores.org\r
+//
+/////////////////////////////////////////////////////////////////////////////////
+// 
+// Copyright (C) 2011 Nicolae Dumitrache
+// 
+// This source file may be used and distributed without 
+// restriction provided that this copyright statement is not 
+// removed from the file and that any derivative work contains 
+// the original copyright notice and the associated disclaimer.
+// 
+// This source file is free software; you can redistribute it 
+// and/or modify it under the terms of the GNU Lesser General 
+// Public License as published by the Free Software Foundation;
+// either version 2.1 of the License, or (at your option) any 
+// later version. 
+// 
+// This source is distributed in the hope that it will be 
+// useful, but WITHOUT ANY WARRANTY; without even the implied 
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
+// PURPOSE. See the GNU Lesser General Public License for more 
+// details. 
+// 
+// You should have received a copy of the GNU Lesser General 
+// Public License along with this source; if not, download it 
+// from http://www.opencores.org/lgpl.shtml 
+// \r
+///////////////////////////////////////////////////////////////////////////////////\r
+//\r
+// Comments:\r
+// This project was developed and tested on a XILINX Spartan3AN board.\r
+//\r
+//\tNextZ80 processor features:
+//\t\tAll documented/undocumented intstructions are implemented
+//\t\tAll documented/undocumented flags are implemented
+//\t\tAll (doc/undoc)flags are changed accordingly by all (doc/undoc)instructions. \r
+//\t\t\tThe block instructions (LDx, CPx, INx, OUTx) have only the documented effects on flags. \r
+//\t\t\tThe Bit n,(IX/IY+d) and BIT n,(HL) undocumented flags XF and YF are implemented like the BIT n,r and not actually like on the real Z80 CPU.
+//\t\tAll interrupt modes implemented: NMI, IM0, IM1, IM2
+//\t\tR register available
+//\t\tFast conditional jump/call/ret takes only 1 T state if not executed
+//\t\tFast block instructions: LDxR - 3 T states/byte, INxR/OTxR - 2 T states/byte, CPxR - 4 T states / byte
+//\t\tEach CPU machine cycle takes (mainly) one clock T state. This makes this processor over 4 times faster than a Z80 at the same \r
+//\t\t\tclock frequency (some instructions are up to 10 times faster). 
+//\t\tWorks at ~40MHZ on Spartan XC3S700AN speed grade -4)
+//\t\tSmall size ( ~12%  ~700 slices - on Spartan XC3S700AN )
+//\t\tTested with ZEXDOC (fully compliant).\r
+//\t\tTested with ZEXALL (all OK except CPx(R), LDx(R), BIT n, (IX/IY+d), BIT n, (HL) - fail because of the un-documented XF and YF flags).\r
+// \r
+///////////////////////////////////////////////////////////////////////////////////\r
+`timescale 1ns / 1ps\r
+\r
+module NextZ80\r
+(\r
+\t\tinput wire[7:0] DI,\r
+\t\toutput wire[7:0] DO,\r
+\t\toutput wire[15:0] ADDR,\r
+\t\toutput reg WR,\r
+\t\toutput reg MREQ,\r
+\t\toutput reg IORQ,\r
+\t\toutput reg HALT,\r
+\t\toutput reg M1,\r
+\t\tinput wire CLK,\r
+\t\tinput wire RESET,\r
+\t\tinput wire INT,\r
+\t\tinput wire NMI,\r
+\t\tinput wire WT\r
+);\r
+\r
+// connections and registers\r
+\treg\t[9:0] CPUStatus = 0;\t// 0=AF-AF', 1=HL-HL', 2=DE-HL, 3=DE'-HL', 4=HL-X, 5=IX-IY, 6=IFF1,7=IFF2, 9:8=IMODE\r
+\twire\t[7:0] ALU8FLAGS;\r
+\twire\t[7:0]\tFLAGS;\r
+\twire \t[7:0] ALU80;\r
+\twire \t[7:0] ALU81;\r
+\twire \t[15:0]ALU160;\r
+\twire \t[7:0] ALU161;\r
+\twire\t[15:0]ALU8OUT;\r
+\r
+\treg \t[9:0]\tFETCH = 0;\r
+\treg \t[2:0]\tSTAGE = 0;\r
+\twire\t[5:0]\topd;\r
+\twire\t[2:0] op16;\r
+\twire\top0mem = FETCH[2:0] == 6;\r
+\twire\top1mem = FETCH[5:3] == 6;\r
+\treg\t[1:0]fetch98;\r
+\r
+// stage status\r
+\treg\t[1:0]DO_SEL;\t\t\t// ALU80 - th - flags - ALU8OUT[7:0]\r
+\treg\tALU160_SEL;\t\t\t\t// regs - pc\r
+\treg\tDINW_SEL;\t\t\t\t// ALU8OUT - DI\r
+\treg \t[5:0]WE;\t\t\t\t\t// 5 = flags, 4 = PC, 3 = SP, 2 = tmpHI, 1 = hi, 0 = lo\r
+\treg \t[4:0] ALU8OP;\r
+\treg \t[2:0] ALU16OP;\r
+\treg \tnext_stage;\r
+\treg \t[3:0]REG_WSEL;\r
+\treg \t[3:0]REG_RSEL;\r
+\treg\t[11:0]status;\t\t\t// 0=AF-AF', 1=HL-HL', 2=DE-HL, 3=DE'-HL', 4=HL-X, 5=IX-IY, 7:6=IFFVAL, 9:8=imode, 10=setIMODE, 11=set IFFVAL\r
+// FETCH[5:3]: 000 NZ, 001 Z, 010 NC, 011 C, 100 PO, 101 PE, 110 P, 111 M\r
+\twire\t[7:0]FlagMux = {FLAGS[7], !FLAGS[7], FLAGS[2], !FLAGS[2], FLAGS[0], !FLAGS[0], FLAGS[6], !FLAGS[6]};\r
+\treg\ttzf;\r
+\treg \tFNMI = 0, SNMI = 0;\r
+\treg \tSRESET = 0;\r
+\treg\tSINT = 0;\r
+\twire\t[2:0]intop = FETCH[1] ? 4 : (FETCH[0] ? 5 : 6);\r
+\treg \txmask;\r
+\r
+\tZ80Reg CPU_REGS (\r
+\t\t .rstatus(CPUStatus[7:0]), \r
+\t\t .M1(M1), \r
+\t\t .WE(WE), \r
+\t\t .CLK(CLK), \r
+\t\t .ALU8OUT(ALU8OUT), \r
+\t\t .DI(DI), \r
+\t\t .DO(DO), \r
+\t\t .ADDR(ADDR), \t\t\t\t\t\t\t\t\t\r
+\t\t .CONST(FETCH[7] ? {2'b00, FETCH[5:3], 3'b000} : 8'h66),\t// RST/NMI address\r
+\t\t .ALU80(ALU80), \r
+\t\t .ALU81(ALU81), \r
+\t\t .ALU160(ALU160), \r
+\t\t .ALU161(ALU161), \r
+\t\t .ALU8FLAGS(ALU8FLAGS), \r
+\t\t .FLAGS(FLAGS),\r
+\t\t .DO_SEL(DO_SEL), \r
+\t\t .ALU160_sel(ALU160_SEL), \r
+\t\t .REG_WSEL(REG_WSEL), \r
+\t\t .REG_RSEL(REG_RSEL), \r
+\t\t .DINW_SEL(DINW_SEL),\r
+\t\t .XMASK(xmask),\r
+\t\t .ALU16OP(ALU16OP),\t\t\t// used for post increment for ADDR, SP mux re-direct\r
+\t\t .WAIT(WT)\r
+\t\t );\r
+\r
+\tALU8 CPU_ALU8 (\r
+\t\t .D0(ALU80), \r
+\t\t .D1(ALU81), \r
+\t\t .FIN(FLAGS), \r
+\t\t .FOUT(ALU8FLAGS), \r
+\t\t .ALU8DOUT(ALU8OUT), \r
+\t\t .OP(ALU8OP),\r
+\t\t .EXOP(FETCH[8:3]),\r
+\t\t .LDIFLAGS(REG_WSEL[2]),\t// inc16 HL\r
+\t\t .DSTHI(!REG_WSEL[0])\r
+\t\t );\r
+\r
+\tALU16 CPU_ALU16 (\r
+\t\t .D0(ALU160), \r
+\t\t .D1(ALU161), \r
+\t\t .DOUT(ADDR), \r
+\t\t .OP(ALU16OP)\r
+\t\t );\r
+\r
+\talways @(posedge CLK)\r
+\t\tif(!WT) begin\r
+\t\t\tSRESET <= RESET;\r
+\t\t\tSNMI <= NMI;\r
+\t\t\tSINT <= INT;\r
+\t\t\tif(!SNMI) FNMI <= 0; \r
+\t\t\tif(SRESET) FETCH <= 10'b1110000000;\r
+\t\t\telse \r
+\t\t\t\tif(FETCH[9:6] == 4'b1110) {FETCH[9:7]} <= 3'b000;\t// exit RESET state\r
+\t\t\t\telse begin \r
+\t\t\t\t\tif(M1)\r
+\t\t\t\t\t\tcase({MREQ, CPUStatus[9:8]})\r
+\t\t\t\t\t\t\t3'b000, 3'b001, 3'b100, 3'b101, 3'b110, 3'b111: FETCH <= {fetch98, DI};\r
+\t\t\t\t\t\t\t3'b010: FETCH <= {fetch98, 8'hff};\t// IM1 - RST38\r
+\t\t\t\t\t\t\t3'b011: ; // IM2 - get addrLO\r
+\t\t\t\t\t\tendcase\r
+\t\t\t\t\tif(~|{next_stage, fetch98[1:0], status[4]})\t\t\t\t// INT or NMI sample\r
+\t\t\t\t\t\tif(SNMI & !FNMI) begin\t\t\t\t\t\t// NMI posedge\r
+\t\t\t\t\t\t\t{FETCH[9:6], FETCH[1:0]} <= {4'b1101, HALT, M1};\r
+\t\t\t\t\t\t\tFNMI <= 1;\t// NMI acknowledged\r
+\t\t\t\t\t\tend else if(SINT & CPUStatus[6] & !status[11]) {FETCH[9:6], FETCH[1:0]} <= {4'b1100, HALT, M1};\t// INT request\r
+\t\t\t\tend\r
+\t\t\tif(next_stage) STAGE <= STAGE + 3'b001;\r
+\t\t\telse STAGE <= 0;\r
+\t\t\tif(status[4]) CPUStatus[5:4] <= status[5:4];\r
+\t\t\telse if(~|{next_stage, fetch98[1]} | fetch98[0]) CPUStatus[4] <= 1'b0;\t\t// clear X\r
+\t\t\tCPUStatus[3:0] <= CPUStatus[3:0] ^ status[3:0];\r
+\t\t\tif(status[11]) CPUStatus[7:6] <= status[7:6]; \t// IFF2:1\r
+\t\t\tif(status[10]) CPUStatus[9:8] <= status[9:8];\t// IMM\r
+\t\t\ttzf <= ALU8FLAGS[6];\r
+\t\tend\r
+\r
+\tassign opd[0] = FETCH[0] ^ &FETCH[2:1];\r
+\tassign opd[2:1] = FETCH[2:1];\r
+\tassign opd[3] = FETCH[3] ^ &FETCH[5:4];\r
+\tassign opd[5:4] = FETCH[5:4];\r
+\tassign op16[2:0] = &FETCH[5:4] ? 3'b101 : {1'b0, FETCH[5:4]};\r
+\r
+\talways @* begin\r
+\t\tDO_SEL\t= 2'bxx;\t\t\t\t\t\t// ALU80 - th - flags - ALU8OUT[7:0]\r
+\t\tALU160_SEL = 1'bx;\t\t\t\t\t// regs - pc\r
+\t\tDINW_SEL = 1'bx;\t\t\t\t\t\t// ALU8OUT - DI\r
+\t\tWE \t\t= 6'bxxxxxx;\t\t\t\t// 5 = flags, 4 = PC, 3 = SP, 2 = tmpHI, 1 = hi, 0 = lo\r
+\t\tALU8OP\t= 5'bxxxxx;\r
+\t\tALU16OP\t= 3'b000;\t\t\t\t\t// NOP, post inc\r
+\t\tnext_stage = 0;\r
+\t\tREG_WSEL\t= 4'bxxxx;\r
+\t\tREG_RSEL\t= 4'bxxxx;\r
+\t\tM1 \t\t= 1;\r
+\t\tMREQ\t\t= 1;\r
+\t\tWR\t\t\t= 0;\r
+\r
+\t\tHALT = 0;\r
+\t\tIORQ = 0;\r
+\t\tstatus\t= 12'b00xxxxx00000;\r
+\t\tfetch98 = 2'b00;\r
+\t\t\r
+\t\tcase({FETCH[7:6], op1mem, op0mem})\r
+\t\t\t4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b1000, 4'b1100: xmask = 1;\r
+\t\t\tdefault: xmask = 0;\r
+\t\tendcase\r
+\t\t\r
+\t\tcase(FETCH[9:6])\t\r
+//------------------------------------------- block 00 ----------------------------------------------------\r
+\t\t\t4'b0000:\r
+\t\t\t\tcase(FETCH[3:0])\r
+//\t\t\t\t-----------------------\t\tNOP, EX AF, AF', DJNZ, JR, JR c --------------------\r
+\t\t\t\t\t4'b0000, 4'b1000:\t\r
+\t\t\t\t\t\tcase(FETCH[5:4])\r
+\t\t\t\t\t\t\t2'b00: begin\t\t\t\t\t// NOP, EX AF, AF'\r
+\t\t\t\t\t\t\t\tDO_SEL\t= 2'bxx;\t\t\t\r
+\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t// PC\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t// PC\r
+\t\t\t\t\t\t\t\tstatus[0] = FETCH[3];\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t2'b01:\t\t\t\t\r
+\t\t\t\t\t\t\t\tif(!STAGE[0]) begin\t\t// DJNZ, JR - stage1\r
+\t\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\t\tWE \t\t= 6'b010100;\t\t// PC, tmpHI\r
+\t\t\t\t\t\t\t\t\tif(!FETCH[3]) begin\r
+\t\t\t\t\t\t\t\t\t\tALU8OP\t= 5'b01010;\t\t\t// DEC, for tzf only\r
+\t\t\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b0000;\t\t\t// B\r
+\t\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\tend else if(FETCH[3]) begin\t// JR - stage2\r
+\t\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t\t// PC\r
+\t\t\t\t\t\t\t\t\tALU16OP\t= 3;\t\t\t\t\t// ADD\r
+\t\t\t\t\t\t\t\tend else begin\t\t\t\t// DJNZ - stage2\r
+\t\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\t\tDINW_SEL = 0;\t\t\t\t\t// ALU8OUT\r
+\t\t\t\t\t\t\t\t\tWE \t\t= 6'b010x10;\t\t// PC, hi\r
+\t\t\t\t\t\t\t\t\tALU8OP\t= 5'b01010;\t\t\t// DEC\r
+\t\t\t\t\t\t\t\t\tALU16OP\t= tzf ? 3'd0 : 3'd3;\t\t// NOP/ADD\r
+\t\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b0000;\t\t\t// B\r
+\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t2'b10, 2'b11: \t\t\t\t\t\t\t// JR cc, stage1, stage2\r
+\t\t\t\t\t\t\t\tcase({STAGE[0], FlagMux[{1'b0, FETCH[4:3]}]})\r
+\t\t\t\t\t\t\t\t\t2'b00, 2'b11: begin\r
+\t\t\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t\t// PC\r
+\t\t\t\t\t\t\t\t\t\tALU16OP\t= STAGE[0] ? 3'd3 : 3'd1;\t\t// ADD/ INC, post inc\r
+\t\t\t\t\t\t\t\t\tend \r
+\t\t\t\t\t\t\t\t\t2'b01: begin\r
+\t\t\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\t\t\tWE \t\t= 6'b010100;\t\t// PC, tmpHI\r
+\t\t\t\t\t\t\t\t\t\tnext_stage = 1; \r
+\t\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\tendcase\r
+\t\t\t\t\t\tendcase\r
+//\t\t\t\t-----------------------\t\tLD rr,nn  --------------------\r
+\t\t\t\t\t4'b0001: \t\t\t// LD rr,nn, stage1\r
+\t\t\t\t\t\tcase({STAGE[1:0], op16[2]})\r
+\t\t\t\t\t\t\t3'b00_0, 3'b00_1, 3'b01_0, 3'b01_1: begin\t\t\t// LD rr,nn, stage1,2\r
+\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t// pc\r
+\t\t\t\t\t\t\t\tDINW_SEL = 1;\t\t\t\t// DI\r
+\t\t\t\t\t\t\t\tWE \t\t= {4'b010x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};\t// PC, lo/HI\r
+\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\tREG_WSEL\t= {op16, 1'bx}; \r
+\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t3'b10_0, 3'b11_1: begin\t\t// BC, DE, HL, stage3, SP stage4\r
+\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t// pc\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t// PC\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t3'b10_1: begin\t\t\t\t// SP stage3\r
+\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t// regs\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b001x00;\t// SP\r
+\t\t\t\t\t\t\t\tALU16OP\t= 4;\t\t\t\t// NOP\r
+\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b101x;\t\t// tmpSP\r
+\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\tMREQ\t\t= 0;\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\tendcase\r
+//\t\t\t\t-----------------------\t\tLD (BC) A -  LD (DE) A - LD (nn) HL, LD (nn),A   --------------------\r
+//\t\t\t\t-----------------------\t\tLD A (BC) -  LD A (DE) - LD HL (nn), LD A (nn)   --------------------\r
+\t\t\t\t\t4'b0010,\t4'b1010:\r
+\t\t\t\t\t\tcase(STAGE[2:0])\r
+\t\t\t\t\t\t\t3'b000:\r
+\t\t\t\t\t\t\t\tif(FETCH[5] == 0) begin\t\t\t// LD (BC) A, LD (DE) A - stage1\r
+\t\t\t\t\t\t\t\t\tif(FETCH[3]) DINW_SEL = 1;\t\t// DI\r
+\t\t\t\t\t\t\t\t\telse DO_SEL\t= 2'b00;\t\t\t\t// ALU80\r
+\t\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\t\tWE \t\t= {4'b000x, FETCH[3], 1'bx};\t\t// hi\r
+\t\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\t\tREG_WSEL\t= FETCH[3] ? 4'b011x : 4'b0110;\t// A\r
+\t\t\t\t\t\t\t\t\tREG_RSEL\t= {op16, 1'bx};\r
+\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\t\tWR = !FETCH[3];\r
+\t\t\t\t\t\t\t\tend else begin\t\t\t\t\t\t// LD (nn) A - LD (nn) HL - stage 1\r
+\t\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t// PC\r
+\t\t\t\t\t\t\t\t\tDINW_SEL = 1;\t\t\t\t\t// DI\r
+\t\t\t\t\t\t\t\t\tWE \t\t= 6'b010xx1;\t\t// PC, lo\r
+\t\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b111x;\r
+\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t3'b001:\r
+\t\t\t\t\t\t\t\tif(FETCH[5] == 0) begin\t\t\t// LD (BC), A, LD (DE), A - stage2\r
+\t\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t\t// PC\r
+\t\t\t\t\t\t\t\tend else begin\t\t\t\t\t\t// LD (nn),A  - LH (nn),HL - stage 2\r
+\t\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\t\tDINW_SEL = 1;\t\t\t\t\t// DI\r
+\t\t\t\t\t\t\t\t\tWE \t\t= 6'b010x10;\t\t// PC, hi\r
+\t\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b111x;\r
+\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t3'b010: begin\t\t\t\t\t\r
+\t\t\t\t\t\t\t\tALU160_SEL = 1'b0;\t\t// regs\r
+\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b111x;\r
+\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\tWR\t\t\t= !FETCH[3];\r
+\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\tif(FETCH[3]) begin\t\t// LD A (nn)  - LD HL (nn) - stage 3\r
+\t\t\t\t\t\t\t\t\tDINW_SEL = 1;\t\t\t\t// DI\r
+\t\t\t\t\t\t\t\t\tWE \t\t= {4'b000x, FETCH[4] ? 1'b1 : 1'bx, FETCH[4] ? 1'bx : 1'b1};\t// lo/hi\r
+\t\t\t\t\t\t\t\t\tREG_WSEL = FETCH[4] ? 4'b011x : 4'b010x;\t// A or L\r
+\t\t\t\t\t\t\t\tend else begin\t\t\t\t// LD (nn),A  - LD (nn),HL - stage 3\r
+\t\t\t\t\t\t\t\t\tDO_SEL\t= 2'b00;\t\t\t// ALU80\r
+\t\t\t\t\t\t\t\t\tWE \t\t= 6'b000x00;\t// nothing\r
+\t\t\t\t\t\t\t\t\tREG_WSEL = FETCH[4] ? 4'b0110 : 4'b0101;\t// A or L\r
+\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t3'b011:\r
+\t\t\t\t\t\t\t\tif(FETCH[4]) begin\t\t\t// LD (nn),A - stage 4\r
+\t\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t// pc\r
+\t\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t// PC\r
+\t\t\t\t\t\t\t\tend else begin\t\t\t\t\t\r
+\t\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b111x;\r
+\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\t\tWR\t\t\t= !FETCH[3];\r
+\t\t\t\t\t\t\t\t\tALU160_SEL = 1'b0;\t\t// regs\r
+\t\t\t\t\t\t\t\t\tALU16OP\t= 1;\t\t\t\t// INC\r
+\t\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\t\tif(FETCH[3]) begin\t// LD HL (nn) - stage 4\r
+\t\t\t\t\t\t\t\t\t\tDINW_SEL = 1;\t\t\t\t// DI\r
+\t\t\t\t\t\t\t\t\t\tWE \t\t= 6'b000x10;\t// hi\r
+\t\t\t\t\t\t\t\t\t\tREG_WSEL = 4'b010x;\t\t// H\r
+\t\t\t\t\t\t\t\t\tend else begin\t\t\t// LD (nn),HL - stage 4\r
+\t\t\t\t\t\t\t\t\t\tDO_SEL\t= 2'b00;\t\t\t// ALU80\r
+\t\t\t\t\t\t\t\t\t\tWE \t\t= 6'b000x00;\t// nothing\r
+\t\t\t\t\t\t\t\t\t\tREG_WSEL = 4'b0100;\t\t// H\r
+\t\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t3'b100: begin\t\t\t\t// LD (nn),HL - stage 5\r
+\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t// pc\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t// PC\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\tendcase\r
+//\t\t\t\t-----------------------\t\tinc/dec rr   --------------------\r
+\t\t\t\t\t4'b0011, 4'b1011:\r
+\t\t\t\t\t\tif(!STAGE[0])\r
+\t\t\t\t\t\t\tif(op16[2]) begin\t\t\t\t// SP - stage1\r
+\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t// regs\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b001x00;\t// SP\r
+\t\t\t\t\t\t\t\tALU16OP\t= {FETCH[3], 1'b0, FETCH[3]};\t\t// post inc, dec\r
+\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b101x;\t\t// sp\r
+\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\tMREQ\t\t= 0;\r
+\t\t\t\t\t\t\tend else begin\t\t\t\t\t// BC, DE, HL - stage 1\r
+\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t// pc\r
+\t\t\t\t\t\t\t\tDINW_SEL = 0;\t\t\t\t// ALU8OUT\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b010x11;\t// PC, hi, lo\r
+\t\t\t\t\t\t\t\tALU8OP\t= {4'b0111, FETCH[3]};\t\t\t// INC16 / DEC16\r
+\t\t\t\t\t\t\t\tREG_WSEL\t= {op16, 1'b0};\t// hi\r
+\t\t\t\t\t\t\t\tREG_RSEL\t= {op16, 1'b1};\t// lo\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\telse \tbegin\t\t\t\t// SP, stage2\r
+\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t// pc\r
+\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t// PC\r
+\t\t\t\t\t\tend\r
+//\t\t\t\t-----------------------\t\tinc/dec 8  --------------------\r
+\t\t\t\t\t4'b0100, 4'b0101, 4'b1100, 4'b1101: \r
+\t\t\t\t\t\tif(!op1mem) begin\t\t\t\t\t\t//regs\r
+\t\t\t\t\t\t\tDINW_SEL = 0;\t\t\t\t\t\t// ALU8OUT\r
+\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// pc\r
+\t\t\t\t\t\t\tWE \t\t= opd[3] ? 6'b110x01 : 6'b110x10;\t// flags, PC, hi/lo\r
+\t\t\t\t\t\t\tALU8OP\t= {3'b010, FETCH[0], 1'b0};\t\t// inc / dec\r
+\t\t\t\t\t\t\tREG_WSEL\t= {1'b0, opd[5:3]};\r
+\t\t\t\t\t\tend else case({STAGE[1:0], CPUStatus[4]})\r
+\t\t\t\t\t\t\t3'b00_0, 3'b01_1: begin\t\t\t\t// (HL) - stage1, (X) - stage2\r
+\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\tDINW_SEL = 1;\t\t\t\t\t\t// DI\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b000001;\t\t\t// lo\r
+\t\t\t\t\t\t\t\tALU16OP\t= CPUStatus[4] ? 3'd3 : 3'd0;\r
+\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b011x;\t\t\t\t// tmpLO\r
+\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b010x;\t\t\t\t// HL\r
+\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t3'b00_1:\tbegin\t\t\t\t\t\t\t// (X) - stage1\r
+\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b010100;\t\t\t// PC, tmpHI\r
+\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\tend \r
+\t\t\t\t\t\t\t3'b01_0, 3'b10_1: begin\t\t\t\t\t// (HL) stage2, (X) - stage3\r
+\t\t\t\t\t\t\t\tDO_SEL\t= 2'b11;\t\t\t\t\t\t// ALU80OUT\r
+\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b100x0x;\t\t\t\t// flags\r
+\t\t\t\t\t\t\t\tALU8OP\t= {3'b010, FETCH[0], 1'b0};\t\t// inc / dec\r
+\t\t\t\t\t\t\t\tALU16OP\t= CPUStatus[4] ? 3'd3 : 3'd0;\r
+\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b0111;\t\t\t\t\t// tmpLO\r
+\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b010x;\t\t\t\t\t// HL\r
+\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\tWR\t\t\t= 1;\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t3'b10_0, 3'b11_1: begin\t\t\t\t\t// (HL) - stage3, (X) - stage 4\r
+\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t\t\t\t// PC\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\tendcase\r
+//\t\t\t\t-----------------------\t\tld r/(HL-X), n  --------------------\t\t\t\t\t\t\r
+\t\t\t\t\t4'b0110, 4'b1110: \t\t\t\t\r
+\t\t\t\t\t\tcase({STAGE[1:0], CPUStatus[4], op1mem})\r
+\t\t\t\t\t\t\t4'b00_0_0, 4'b00_0_1, 4'b00_1_0, 4'b01_1_1: begin\t\t// r, (HL) - stage1, (X) - stage2 (read n)\r
+\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\tDINW_SEL = 1;\t\t\t\t\t\t// DI\r
+\t\t\t\t\t\t\t\tWE \t\t= opd[3] ? 6'b010001 : 6'b010010;\t\t\t// PC, hi/lo\r
+\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\tREG_WSEL\t= {1'b0, opd[5:4], 1'bx};\r
+\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t4'b01_0_0, 4'b01_1_0, 4'b10_0_1, 4'b11_1_1: begin\t\t// r - stage2, (HL) - stage3, (X) - stage4\r
+\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t\t\t\t// PC\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t4'b01_0_1, 4'b10_1_1: begin\t\t\t// (HL) - stage2, (X) - stage3\r
+\t\t\t\t\t\t\t\tDO_SEL\t= 2'b00;\t\t\t\t\t\t// ALU80\r
+\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b000x0x;\t\t\t\t// nothing\r
+\t\t\t\t\t\t\t\tALU16OP\t= CPUStatus[4] ? 3'd3 : 3'd0;\r
+\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b0111;\t\t\t\t\t// tmpLO\r
+\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b010x;\t\t\t\t\t// HL\r
+\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\tWR\t\t\t= 1;\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t4'b00_1_1: begin\t\t\t\t\t\t\t// (X) - stage1\r
+\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b010100;\t\t\t\t// PC, tmpHI\r
+\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\tendcase\r
+//\t\t\t\t-----------------------\t\trlca, rrca, rla, rra, daa, cpl, scf, ccf  --------------------\t\t\t\t\t\t\r
+\t\t\t\t\t4'b0111, 4'b1111: \t\t\t\t\r
+\t\t\t\t\t\tcase(FETCH[5:3])\r
+\t\t\t\t\t\t\t3'b000, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101: begin\t\t// rlca, rrca, rla, rra, daa, cpl\r
+\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\tDINW_SEL = 0;\t\t\t\t\t\t// ALU8OUT\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b110x1x;\t\t\t// flags, PC, hi\r
+\t\t\t\t\t\t\t\tALU8OP\t= FETCH[5] ? {2'b01, !FETCH[3], 2'b01} : {3'b110, FETCH[4:3]};\r
+\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b0110;\t\t\t\t// A\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t3'b110, 3'b111:\tbegin\t\t\t\t// scf, ccf\r
+\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\tDINW_SEL = 0;\t\t\t\t\t\t// ALU8OUT\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b110x0x;\t\t\t// flags, PC\r
+\t\t\t\t\t\t\t\tALU8OP\t= {4'b1010, !FETCH[3]};\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\tendcase\r
+//\t\t\t\t-----------------------\t\tadd 16  --------------------\t\t\t\t\t\t\r
+\t\t\t\t\t4'b1001: \r
+\t\t\t\t\t\tif(!STAGE[0]) begin\r
+\t\t\t\t\t\t\tDINW_SEL = 0;\t\t\t\t\t\t// ALU8OUT\r
+\t\t\t\t\t\t\tWE \t\t= 6'b100x01;\t\t\t// flags, lo\r
+\t\t\t\t\t\t\tALU8OP\t= 5'b10000;\t\t\t\t// ADD16LO\r
+\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\tREG_WSEL\t= 4'b0101;\t\t\t\t// L\r
+\t\t\t\t\t\t\tREG_RSEL\t= {op16, 1'b1};\r
+\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\tMREQ\t\t= 0;\r
+\t\t\t\t\t\tend else begin\r
+\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// pc\r
+\t\t\t\t\t\t\tDINW_SEL = 0;\t\t\t\t\t\t// ALU8OUT\r
+\t\t\t\t\t\t\tWE \t\t= 6'b110x10;\t\t\t// flags, PC, hi\r
+\t\t\t\t\t\t\tALU8OP\t= 5'b10001;\t\t\t\t// ADD16HI\r
+\t\t\t\t\t\t\tREG_WSEL\t= 4'b0100;\t\t\t\t// H\r
+\t\t\t\t\t\t\tREG_RSEL\t= {op16, 1'b0};\r
+\t\t\t\t\t\tend\r
+\t\t\t\tendcase\r
+\r
+// ---------------------------------------------- block 01 LD8 ---------------------------------------------------\r
+\t\t\t4'b0001:\t\r
+\t\t\t\tcase({STAGE[1:0], CPUStatus[4], op1mem, op0mem})\r
+\t\t\t\t\t5'b00_0_00, 5'b00_1_00,\t\t// LD r, r 1st stage\r
+\t\t\t\t\t5'b01_0_01,\t\t\t\t\t\t// LD r, (HL) 2nd stage\r
+\t\t\t\t\t5'b10_1_01:\t\t\t\t\t\t// LD r, (X) 3rd stage\r
+\t\t\t\t\tbegin\t\r
+\t\t\t\t\t\tALU160_SEL = 1;\t\t\t// PC\r
+\t\t\t\t\t\tDINW_SEL\t  = 0;\t\t\t// ALU8\r
+\t\t\t\t\t\tWE = opd[3] ? 6'b010x01 : 6'b010x10;\t// PC and LO or HI\r
+\t\t\t\t\t\tALU8OP = 29;\t\t\t\t// PASS D1\r
+\t\t\t\t\t\tREG_WSEL = {1'b0, opd[5:4], 1'bx};\r
+\t\t\t\t\t\tREG_RSEL = {1'b0, opd[2:0]};\r
+\t\t\t\t\tend\r
+\t\t\t\t\t5'b00_0_01,\t\t\t\t\t\t// LD r, (HL) 1st stage\r
+\t\t\t\t\t5'b01_1_01:\t\t\t\t\t\t// LD r, (X) 2nd stage\r
+\t\t\t\t\tbegin\t\r
+\t\t\t\t\t\tALU160_SEL = 0;\t\t\t// regs\r
+\t\t\t\t\t\tDINW_SEL = 1;\t\t\t\t// DI\t\t\r
+\t\t\t\t\t\tWE \t\t= 6'b000x01;\t// LO\r
+\t\t\t\t\t\tALU16OP\t= CPUStatus[4] ? 3'd3 : 3'd0;\t\t// ADD - NOP\r
+\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\tREG_WSEL\t= 4'b011x;\t\t// A - tmpLO\r
+\t\t\t\t\t\tREG_RSEL = 4'b010x;\t\t// HL\r
+\t\t\t\t\t\tM1 = 0;\r
+\t\t\t\t\tend\r
+\t\t\t\t\t5'b00_1_01,\t\t\t\t\t\t// LD r, (X) 1st stage\r
+\t\t\t\t\t5'b00_1_10:\t\t\t\t\t\t// LD (X), r 1st stage\r
+\t\t\t\t\tbegin\r
+\t\t\t\t\t\tALU160_SEL = 1;\t\t\t// pc\r
+\t\t\t\t\t\tWE \t\t= 6'b010100;\t// PC, tmpHI\r
+\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\tend\r
+\t\t\t\t\t5'b00_0_10, \t\t\t\t\t// LD (HL), r 1st stage\r
+\t\t\t\t\t5'b01_1_10:\t\t\t\t\t\t// LD (X), r 2nd stage\r
+\t\t\t\t\tbegin\t\r
+\t\t\t\t\t\tDO_SEL\t= 0;\t\t\t\t// ALU80\r
+\t\t\t\t\t\tALU160_SEL = 0;\t\t\t// regs\r
+\t\t\t\t\t\tWE \t\t= 6'b000x00;\t// no write\r
+\t\t\t\t\t\tALU16OP\t= CPUStatus[4] ? 3'd3 : 3'd0;\t\t\t// ADD - NOP\r
+\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\tREG_WSEL\t= {1'b0, opd[2:0]};\r
+\t\t\t\t\t\tREG_RSEL\t= 4'b010x;\t\t// HL\r
+\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\tWR\t\t\t= 1;\t\t\t\r
+\t\t\t\t\tend\r
+\t\t\t\t\t5'b01_0_10, \t\t\t\t\t// LD (HL), r 2nd stage\r
+\t\t\t\t\t5'b10_1_10:\t\t\t\t\t\t// LD (X), r 3rd stage\r
+\t\t\t\t\tbegin\t\r
+\t\t\t\t\t\tALU160_SEL = 1;\t\t\t// pc\r
+\t\t\t\t\t\tWE \t\t= 6'b010x00;\t// PC\r
+\t\t\t\t\tend\r
+\t\t\t\t\t5'b00_0_11, 5'b00_1_11: begin\t// HALT\r
+\t\t\t\t\t\tWE \t\t= 6'b000x00;\t// no write\r
+\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\tMREQ\t\t= 0;\r
+\t\t\t\t\t\tHALT \t\t= 1;\r
+\t\t\t\t\tend\r
+\t\t\t\tendcase\r
+// ---------------------------------------------- block 10 arith8 ---------------------------------------------------\r
+\t\t\t4'b0010:\t\r
+\t\t\t\tcase({STAGE[1:0], CPUStatus[4], op0mem})\r
+\t\t\t\t\t4'b00_0_0, 4'b00_1_0,\t\t// OP r,r 1st stage\r
+\t\t\t\t\t4'b01_0_1,\t\t\t\t\t\t// OP r, (HL) 2nd stage\r
+\t\t\t\t\t4'b10_1_1:\t\t\t\t\t\t// OP r, (X) 3rd stage\r
+\t\t\t\t\tbegin\r
+\t\t\t\t\t\tALU160_SEL = 1;\t\t\t// pc\r
+\t\t\t\t\t\tDINW_SEL = 0;\t\t\t\t// ALU8OUT\r
+\t\t\t\t\t\tWE \t\t= {4'b110x, ~&FETCH[5:3], 1'bx};\t// flags, PC, hi\r
+\t\t\t\t\t\tALU8OP\t= {2'b00, FETCH[5:3]};\r
+\t\t\t\t\t\tREG_WSEL\t= 4'b0110;\t\t// A\r
+\t\t\t\t\t\tREG_RSEL\t= {1'b0, opd[2:0]};\r
+\t\t\t\t\tend\r
+\t\t\t\t\t4'b00_0_1,\t\t\t\t\t\t// OP r, (HL) 1st stage\r
+\t\t\t\t\t4'b01_1_1:\t\t\t\t\t\t// OP r, (X) 2nd stage\r
+\t\t\t\t\tbegin\r
+\t\t\t\t\t\tALU160_SEL = 0;\t\t\t// HL\r
+\t\t\t\t\t\tDINW_SEL = 1;\t\t\t\t// DI\r
+\t\t\t\t\t\tWE \t\t= 6'b000x01;\t// lo\r
+\t\t\t\t\t\tALU16OP\t= CPUStatus[4] ? 3'd3 : 3'd0;\t\t\t// ADD - NOP\r
+\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\tREG_WSEL\t= 4'b011x;\t\t// A-tmpLO\r
+\t\t\t\t\t\tREG_RSEL\t= 4'b010x;\t\t// HL\r
+\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\tend\r
+\t\t\t\t\t4'b00_1_1:\t\t\t\t\t\t// OP r, (X) 1st stage\r
+\t\t\t\t\tbegin\r
+\t\t\t\t\t\tALU160_SEL = 1;\t\t\t// pc\r
+\t\t\t\t\t\tWE \t\t= 6'b010100;\t// PC, tmpHI\r
+\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\tend\r
+\t\t\t\tendcase\r
+//------------------------------------------- block 11 ----------------------------------------------------\r
+\t\t\t4'b0011:\r
+\t\t\t\tcase(FETCH[3:0])\r
+//\t\t\t\t-----------------------\t\tRET cc --------------------\r
+\t\t\t\t\t4'b0000, 4'b1000:\r
+\t\t\t\t\t\tcase(STAGE[1:0])\r
+\t\t\t\t\t\t\t2'b00, 2'b01:\t\t\t// stage1, stage2\r
+\t\t\t\t\t\t\t\tif(FlagMux[FETCH[5:3]]) begin\t// POP addr\r
+\t\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\t\tDINW_SEL = 1;\t\t\t\t\t// DI\r
+\t\t\t\t\t\t\t\t\tWE \t\t= {4'b001x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};\t\t// SP, lo/hi\r
+\t\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b111x;\t\t\t// tmp16\r
+\t\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b101x;\t\t\t// SP\r
+\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\tend else begin\r
+\t\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t\t// PC\r
+\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t2'b10: begin\t\t\t// stage3\r
+\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t\t\t// PC\r
+\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b111x;\t\t\t\t// tmp16\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\tendcase\r
+//\t\t\t\t-----------------------\t\tPOP --------------------\r
+\t\t\t\t\t4'b0001:\r
+\t\t\t\t\t\tcase(STAGE[1:0])\r
+\t\t\t\t\t\t\t2'b00, 2'b01: begin\r
+\t\t\t\t\t\t\t\tif(op16[2]) begin\t// AF\r
+\t\t\t\t\t\t\t\t\tWE \t\t= STAGE[0] ? 6'b101x1x : 6'b001xx1;\t\t// flags, SP, lo/hi\r
+\t\t\t\t\t\t\t\t\tREG_WSEL\t= {3'b011, STAGE[0] ? 1'b1 : 1'bx};\r
+\t\t\t\t\t\t\t\t\tif(STAGE[0]) ALU8OP\t= 30;\t\t\t\t\t\t// FLAGS <- D0\r
+\t\t\t\t\t\t\t\tend else begin\t\t// r16\r
+\t\t\t\t\t\t\t\t\tWE \t\t= STAGE[0] ? 6'b001x10 : 6'b001xx1;\t\t// SP, lo/hi\r
+\t\t\t\t\t\t\t\t\tREG_WSEL\t= {1'b0, FETCH[5:4], 1'bx};\r
+\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t// regs\r
+\t\t\t\t\t\t\t\tDINW_SEL = 1;\t\t\t\t// DI\r
+\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b101x;\t\t// SP\r
+\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t2'b10: begin\t\t\t\t\t// stage3\r
+\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t// PC\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t// PC\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\tendcase\r
+//\t\t\t\t-----------------------\t\tJP cc --------------------\r
+\t\t\t\t\t4'b0010, 4'b1010:\r
+\t\t\t\t\t\tcase(STAGE[1:0])\r
+\t\t\t\t\t\t\t2'b00, 2'b01:\tbegin\t\t\t\t// stage1,2\r
+\t\t\t\t\t\t\t\tif(FlagMux[FETCH[5:3]]) begin\r
+\t\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\t\tDINW_SEL = 1;\t\t\t\t\t\t// DI\r
+\t\t\t\t\t\t\t\t\tWE \t\t= {4'b010x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};\t\t// PC, hi/lo\r
+\t\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b111x;\t\t\t\t// tmp7\r
+\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\tend else begin\r
+\t\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t\t\t// PC\r
+\t\t\t\t\t\t\t\t\tALU16OP\t= 2;\t\t\t\t\t\t// add2\r
+\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t2'b10: begin\t\t\t\t\t\t// stage3\r
+\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t\t\t// PC\r
+\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b111x;\t\t\t\t// tmp7\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\tendcase\r
+//\t\t\t\t-----------------------\t\tJP, OUT (n) A, EX (SP) HL, DI --------------------\r
+\t\t\t\t\t4'b0011:\r
+\t\t\t\t\t\tcase(FETCH[5:4])\r
+\t\t\t\t\t\t\t2'b00:\t\t\t\t\t// JP\r
+\t\t\t\t\t\t\t\tcase(STAGE[1:0])\r
+\t\t\t\t\t\t\t\t\t2'b00, 2'b01:\tbegin\t\t\t\t// stage1,2 - read addr\r
+\t\t\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\t\t\tDINW_SEL = 1;\t\t\t\t\t\t// DI\r
+\t\t\t\t\t\t\t\t\t\tWE \t\t= {4'b010x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};\t\t// PC, hi/lo\r
+\t\t\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b111x;\t\t\t\t// tmp7\r
+\t\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\t\t2'b10: begin\t\t\t\t\t\t// stage3\r
+\t\t\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t\t\t// PC\r
+\t\t\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b111x;\t\t\t\t// tmp7\r
+\t\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\tendcase\r
+\t\t\t\t\t\t\t2'b01: \t\t\t\t\t// OUT (n), a - stage1 - read n\r
+\t\t\t\t\t\t\t\tcase(STAGE[1:0])\r
+\t\t\t\t\t\t\t\t\t2'b00: begin\r
+\t\t\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\t\t\tDINW_SEL = 1;\t\t\t\t\t\t// DI\r
+\t\t\t\t\t\t\t\t\t\tWE \t\t= 6'b010x01;\t\t\t// PC, lo\r
+\t\t\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b011x;\t\t\t\t// tmpLO\r
+\t\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\t\t2'b01: begin\t\t// stage2 - OUT\r
+\t\t\t\t\t\t\t\t\t\tDO_SEL\t= 2'b00;\t\t\t\t\t// ALU80\r
+\t\t\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\t\t\tWE \t\t= 6'b000x00;\t\t\t// nothing\r
+\t\t\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b0110;\t\t\t\t// A\r
+\t\t\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b011x;\t\t\t\t// A-tmpLO\r
+\t\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\t\t\tMREQ\t\t= 0;\r
+\t\t\t\t\t\t\t\t\t\tWR \t\t= 1;\r
+\t\t\t\t\t\t\t\t\t\tIORQ\t\t= 1;\r
+\t\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\t\t2'b10: begin\t\t// stage3 - fetch\r
+\t\t\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t// PC\r
+\t\t\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t// PC\r
+\t\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\tendcase\r
+\t\t\t\t\t\t\t2'b10:\t\t\t\t// EX (SP), HL\r
+\t\t\t\t\t\t\t\tcase(STAGE[2:0])\r
+\t\t\t\t\t\t\t\t\t3'b000, 3'b001:\tbegin\t\t\t// stage1,2 - pop tmp16\r
+\t\t\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\t\t\tDINW_SEL = 1;\t\t\t\t\t\t// DI\r
+\t\t\t\t\t\t\t\t\t\tWE \t\t= {4'b001x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};\t\t\t// SP, lo/hi\r
+\t\t\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b111x;\t\t\t\t// tmp16\r
+\t\t\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b101x;\t\t\t\t// SP\r
+\t\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\t\t3'b010, 3'b011: begin\t\t\t// stage3,4 - push hl\r
+\t\t\t\t\t\t\t\t\t\tDO_SEL\t= 2'b00;\t\t\t\t\t// ALU80\r
+\t\t\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\t\t\tWE \t\t= 6'b001x00;\t\t\t// SP\r
+\t\t\t\t\t\t\t\t\t\tALU16OP\t= 5;\t\t\t\t\t\t// dec\r
+\t\t\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\t\t\tREG_WSEL\t= {3'b010, STAGE[0]};// H/L\t\r
+\t\t\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b101x;\t\t\t\t// SP\r
+\t\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\t\t\tWR\t\t\t= 1;\r
+\t\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\t\t3'b100, 3'b101: begin\t\t// stage5,6\r
+\t\t\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\t\t\tDINW_SEL = 0;\t\t\t\t\t\t// ALU8OUT\r
+\t\t\t\t\t\t\t\t\t\tWE \t\t= {1'b0, STAGE[0], 2'b0x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};\t// PC, lo/hi\r
+\t\t\t\t\t\t\t\t\t\tALU8OP\t= 29;\t\t// pass D1\r
+\t\t\t\t\t\t\t\t\t\tnext_stage = !STAGE[0];\r
+\t\t\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b010x;\t\t// HL\r
+\t\t\t\t\t\t\t\t\t\tREG_RSEL\t= {3'b111, !STAGE[0]};\t\t// tmp16\r
+\t\t\t\t\t\t\t\t\t\tM1 \t\t= STAGE[0];\r
+\t\t\t\t\t\t\t\t\t\tMREQ\t\t= STAGE[0];\r
+\t\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\tendcase\r
+\t\t\t\t\t\t\t2'b11:\tbegin\t\t\t// DI\r
+\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t// PC\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t// PC\r
+\t\t\t\t\t\t\t\tstatus[11] = 1'b1;\t\t// set IFF flags\r
+\t\t\t\t\t\t\t\tstatus[7:6] = 2'b00;\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\tendcase\r
+//\t\t\t\t-----------------------\t\tCALL cc --------------------\r
+\t\t\t\t\t4'b0100, 4'b1100:\t\r
+\t\t\t\t\t\tcase(STAGE[2:0])\r
+\t\t\t\t\t\t\t3'b000, 3'b001:\t\t// stage 1,2 - load addr\r
+\t\t\t\t\t\t\t\tif(FlagMux[FETCH[5:3]]) begin\r
+\t\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\t\tDINW_SEL = 1;\t\t\t\t\t\t// DI\r
+\t\t\t\t\t\t\t\t\tWE \t\t= {4'b010x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};\t\t// PC, hi/lo\r
+\t\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b111x;\t\t\t\t// tmp7\r
+\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\tend else begin\r
+\t\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t\t\t// PC\r
+\t\t\t\t\t\t\t\t\tALU16OP\t= 2;\t\t\t\t\t\t// add2\r
+\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t3'b010, 3'b011: begin\t\t// stage 3,4 - push pc\r
+\t\t\t\t\t\t\t\tDO_SEL\t= {1'b0, STAGE[0]};\t// pc hi/lo\r
+\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b001x00;\t\t\t// SP\r
+\t\t\t\t\t\t\t\tALU16OP\t= 5;\t\t\t\t\t\t// DEC\r
+\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b1xxx;\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b101x;\t\t\t\t// sp\r
+\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\tWR\t\t\t= 1;\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t3'b100:\tbegin\t// stage5\r
+\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t\t\t// PC\r
+\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b111x;\t\t\t\t// tmp7\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\tendcase\r
+//\t\t\t\t-----------------------\t\tPUSH --------------------\r
+\t\t\t\t\t4'b0101: \r
+\t\t\t\t\t\tcase(STAGE[1:0])\r
+\t\t\t\t\t\t\t2'b00, 2'b01: begin\t\t\t// stage1,2\r
+\t\t\t\t\t\t\t\tDO_SEL\t= {STAGE[0] & op16[2], 1'b0};\t\t// FLAGS/ALU80\r
+\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b001x00;\t\t// SP\r
+\t\t\t\t\t\t\t\tALU16OP\t= 5;  \t\t\t\t// dec\r
+\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\tREG_WSEL\t= {1'b0, FETCH[5:4], STAGE[0]};\r
+\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b101x;\t\t\t\t// SP\r
+\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\tWR\t\t\t= 1;\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t2'b10: begin\t\t\t\t\t//stage3\r
+\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t// PC\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t\t// PC\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\tendcase\r
+//\t\t\t\t-----------------------\t\top A, n  --------------------\r
+\t\t\t\t\t4'b0110, 4'b1110:\r
+\t\t\t\t\t\tif(!STAGE[0]) begin\t\t\t// stage1, read n\r
+\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// pc\r
+\t\t\t\t\t\t\tDINW_SEL = 1;\t\t\t\t\t\t// DI\r
+\t\t\t\t\t\t\tWE \t\t= 6'b010x01;\t\t\t// PC, lo\r
+\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\tREG_WSEL\t= 4'b011x;\t\t\t\t// tmpLO\r
+\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\tend else begin\t\t\t\t\t// stage 2\r
+\t\t\t\t\t\t\tDINW_SEL = 0;\t\t\t\t\t\t// ALU8OUT[7:0]\r
+\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// pc\r
+\t\t\t\t\t\t\tWE \t\t= {4'b110x, ~&FETCH[5:3], 1'bx};\t\t\t// flags, PC, hi\r
+\t\t\t\t\t\t\tALU8OP\t= {2'b00, FETCH[5:3]};\r
+\t\t\t\t\t\t\tREG_WSEL\t= 4'b0110;\t\t\t\t// A\r
+\t\t\t\t\t\t\tREG_RSEL\t= 4'b0111;\t\t\t\t// tmpLO\r
+\t\t\t\t\t\tend\r
+//\t\t\t\t-----------------------\t\tRST  --------------------\r
+\t\t\t\t\t4'b0111, 4'b1111:\r
+\t\t\t\t\t\tcase(STAGE[1:0])\r
+\t\t\t\t\t\t\t2'b00, 2'b01: begin\t\t// stage 1,2 - push pc\r
+\t\t\t\t\t\t\t\tDO_SEL\t= {1'b0, STAGE[0]};\t// pc hi/lo\r
+\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b001x00;\t\t\t// SP\r
+\t\t\t\t\t\t\t\tALU16OP\t= 5;\t\t\t\t\t\t// DEC\r
+\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b1xxx;\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b101x;\t\t\t\t// sp\r
+\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\tWR\t\t\t= 1;\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t2'b10:\tbegin\t\t\t\t// stage3\r
+\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t\t\t// PC\r
+\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b110x;\t\t\t\t// const\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\tendcase\r
+//\t\t\t\t-----------------------\t\tRET, EXX, JP (HL), LD SP HL --------------------\r
+\t\t\t\t\t4'b1001:\t\r
+\t\t\t\t\t\tcase(FETCH[5:4])\t\r
+\t\t\t\t\t\t\t2'b00: \t\t\t\t// RET\r
+\t\t\t\t\t\t\t\tcase(STAGE[1:0])\r
+\t\t\t\t\t\t\t\t\t2'b00, 2'b01:\tbegin\t\t// stage1, stage2 - pop addr\r
+\t\t\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\t\t\tDINW_SEL = 1;\t\t\t\t\t// DI\r
+\t\t\t\t\t\t\t\t\t\tWE \t\t= {4'b001x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};\t\t// SP, lo/hi\r
+\t\t\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b111x;\t\t\t// tmp16\r
+\t\t\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b101x;\t\t\t// SP\r
+\t\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\t\tend\t\t\r
+\t\t\t\t\t\t\t\t\t2'b10: begin\t\t\t// stage3 - jump\r
+\t\t\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t\t\t// PC\r
+\t\t\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b111x;\t\t\t\t// tmp16\r
+\t\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\tendcase\r
+\t\t\t\t\t\t\t2'b01: begin\t\t\t// EXX\r
+\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t// PC\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t// PC\r
+\t\t\t\t\t\t\t\tstatus[1] = 1;\t\t\t\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t2'b10:\tbegin\t\t// JP (HL)\r
+\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t\t\t// PC\r
+\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b010x;\t\t\t\t// HL\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t2'b11: begin\t// LD SP,HL\t\r
+\t\t\t\t\t\t\t\tif(!STAGE[0]) begin\t\t\t// stage1\r
+\t\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\t\tWE \t\t= 6'b001x00;\t\t// SP\r
+\t\t\t\t\t\t\t\t\tALU16OP\t= 4;\t\t\t\t\t// NOP, no post inc\r
+\t\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b010x;\t\t\t// HL\r
+\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\t\tMREQ\t\t= 0;\r
+\t\t\t\t\t\t\t\tend else begin\t\t\t\t\t\t// stage2\r
+\t\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t\t// PC\r
+\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\tendcase\r
+//\t\t\t\t-----------------------\t\tCB, IN A (n), EX DE HL, EI --------------------\r
+\t\t\t\t\t4'b1011:\r
+\t\t\t\t\t\tcase(FETCH[5:4])\r
+\t\t\t\t\t\t\t2'b00:  \t\t\t\t\t// CB prefix\r
+\t\t\t\t\t\t\t\tcase({STAGE[0], CPUStatus[4]})\r
+\t\t\t\t\t\t\t\t\t2'b00, 2'b11: begin\r
+\t\t\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t// PC\r
+\t\t\t\t\t\t\t\t\t\tWE \t\t= 6'b010000;\t// PC\r
+\t\t\t\t\t\t\t\t\t\tfetch98 = 2'b10;\t\t\r
+\t\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\t\t2'b01: begin\r
+\t\t\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t// PC\r
+\t\t\t\t\t\t\t\t\t\tWE \t\t= 6'b010100;\t// PC, tmpHI\r
+\t\t\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\tendcase\r
+\t\t\t\t\t\t\t2'b01:\t\t\t\t\t// IN A, (n)\r
+\t\t\t\t\t\t\t\tcase(STAGE[1:0])\r
+\t\t\t\t\t\t\t\t\t2'b00: begin\t\t//stage1 - read n\r
+\t\t\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\t\t\tDINW_SEL = 1;\t\t\t\t\t// DI\r
+\t\t\t\t\t\t\t\t\t\tWE \t\t= 6'b010x01;\t\t// PC, lo\r
+\t\t\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b011x;\t\t\t// tmpLO\r
+\t\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\t\t2'b01: begin\t\t// stage2 - IN\r
+\t\t\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\t\t\tDINW_SEL = 1;\t\t\t\t\t// DI\r
+\t\t\t\t\t\t\t\t\t\tWE \t\t= 6'b000x1x;\t\t// hi\r
+\t\t\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b011x;\t\t\t// A\r
+\t\t\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b011x;\t\t\t// A - tmpLO\r
+\t\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\t\t\tMREQ\t\t= 0;\r
+\t\t\t\t\t\t\t\t\t\tIORQ\t\t= 1;\r
+\t\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\t\t2'b10: begin\t\t// stage3 - fetch\r
+\t\t\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t// PC\r
+\t\t\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t// PC\r
+\t\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\tendcase\r
+\t\t\t\t\t\t\t2'b10: begin\t\t\t// EX DE, HL\r
+\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t// PC\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t// PC\r
+\t\t\t\t\t\t\t\tif(CPUStatus[1]) status[3] = 1;\t\r
+\t\t\t\t\t\t\t\telse status[2] = 1;\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t2'b11: begin\t\t\t// EI\r
+\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t// PC\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t// PC\r
+\t\t\t\t\t\t\t\tstatus[11] = 1'b1;\r
+\t\t\t\t\t\t\t\tstatus[7:6] = 2'b11;\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\tendcase\r
+//\t\t\t\t-----------------------\t\tCALL , IX, ED, IY --------------------\r
+\t\t\t\t\t4'b1101:\t\r
+\t\t\t\t\t\tcase(FETCH[5:4])\r
+\t\t\t\t\t\t\t2'b00: \t\t\t\t\t// CALL\r
+\t\t\t\t\t\t\t\tcase(STAGE[2:0])\r
+\t\t\t\t\t\t\t\t\t3'b000, 3'b001: begin\t\t// stage 1,2 - load addr\r
+\t\t\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\t\t\tDINW_SEL = 1;\t\t\t\t\t\t// DI\r
+\t\t\t\t\t\t\t\t\t\tWE \t\t= {4'b010x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};\t\t// PC, hi/lo\r
+\t\t\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b111x;\t\t\t\t// tmp7\r
+\t\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\t\t3'b010, 3'b011: begin\t\t// stage 3,4 - push pc\r
+\t\t\t\t\t\t\t\t\t\tDO_SEL\t= {1'b0, STAGE[0]};\t// pc hi/lo\r
+\t\t\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\t\t\tWE \t\t= 6'b001x00;\t\t\t// SP\r
+\t\t\t\t\t\t\t\t\t\tALU16OP\t= 5;\t\t\t\t\t\t// DEC\r
+\t\t\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b1xxx;\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b101x;\t\t\t\t// sp\r
+\t\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\t\t\tWR\t\t\t= 1;\r
+\t\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\t\t3'b100:\tbegin\t// stage5 - jump\r
+\t\t\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t\t\t// PC\r
+\t\t\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b111x;\t\t\t\t// tmp7\r
+\t\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\tendcase\r
+\t\t\t\t\t\t\t2'b01: begin\t\t\t// DD - IX\r
+\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t// PC\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t// PC\r
+\t\t\t\t\t\t\t\tstatus[5:4] = 2'b01;\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t2'b10: begin\t\t\t// ED prefix\r
+\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t// PC\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t// PC\r
+\t\t\t\t\t\t\t\tfetch98 = 2'b01;\t\t\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t2'b11:\tbegin\t\t\t// FD - IY\r
+\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t// PC\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t// PC\r
+\t\t\t\t\t\t\t\tstatus[5:4]\t= 2'b11;\t\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\tendcase\r
+\t\t\t\tendcase\r
+\r
+//\t------------------------------------------- ED + opcode ----------------------------------------------------\r
+\t\t\t4'b0100, 4'b0111: begin\t\t// ED + 2'b00, ED + 2'b11 \t\t= NOP\r
+\t\t\t\tALU160_SEL = 1;\t\t\t// PC\r
+\t\t\t\tWE \t\t= 6'b010x00;\t// PC\r
+\t\t\tend\r
+\t\t\t4'b0101:\r
+\t\t\t\tcase(FETCH[2:0])\r
+//\t\t\t\t-----------------------\t\tin r (C)  --------------------\r
+\t\t\t\t\t3'b000:\r
+\t\t\t\t\t\tif(!STAGE[0]) begin\r
+\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\tDINW_SEL = 1;\t\t\t\t\t\t// DI\r
+\t\t\t\t\t\t\tWE \t\t= {4'b000x, !opd[3], opd[3]} ;\t// hi/lo\r
+\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\tREG_WSEL\t= {1'b0, opd[5:4], 1'bx};\r
+\t\t\t\t\t\t\tREG_RSEL\t= 4'b000x;\t\t\t\t// BC\r
+\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\tMREQ\t\t= 0;\r
+\t\t\t\t\t\t\tIORQ \t\t= 1;\r
+\t\t\t\t\t\tend else begin\r
+\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// pc\r
+\t\t\t\t\t\t\tWE \t\t= 6'b110x00;\t\t\t// flags, PC\r
+\t\t\t\t\t\t\tALU8OP\t= 29;\t\t\t\t\t\t// IN\r
+\t\t\t\t\t\t\tREG_RSEL\t= {1'b0, opd[5:3]};\t// reg\r
+\t\t\t\t\t\tend\r
+//\t\t\t\t-----------------------\t\tout (C) r  --------------------\r
+\t\t\t\t\t3'b001:\r
+\t\t\t\t\t\tif(!STAGE[0]) begin\r
+\t\t\t\t\t\t\tDO_SEL\t= 2'b00;\t\t\t\t\t// ALU80\r
+\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\tWE \t\t= 6'b000x00;\t\t\t// nothing\r
+\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\tREG_WSEL\t= &opd[5:3] ? 4'b110x : {1'b0, opd[5:3]}; // zero/reg\r
+\t\t\t\t\t\t\tREG_RSEL\t= 4'b000x;\t\t\t\t// BC\r
+\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\tMREQ\t\t= 0;\r
+\t\t\t\t\t\t\tWR\t\t\t= 1;\r
+\t\t\t\t\t\t\tIORQ \t\t= 1;\r
+\t\t\t\t\t\tend else begin\r
+\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// pc\r
+\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t\t\t// PC\r
+\t\t\t\t\t\tend\r
+//\t\t\t\t-----------------------\t\tSBC16, ADC16  --------------------\r
+\t\t\t\t\t3'b010:\r
+\t\t\t\t\t\tif(!STAGE[0]) begin\t\t\t// stage1\r
+\t\t\t\t\t\t\tDINW_SEL = 0;\t\t\t\t\t\t// ALU8OUT\r
+\t\t\t\t\t\t\tWE \t\t= 6'b100x01;\t\t\t// flags, lo\r
+\t\t\t\t\t\t\tALU8OP\t= {3'b000, !FETCH[3], 1'b1};\t// SBC/ADC\r
+\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\tREG_WSEL\t= 4'b0101;\t\t\t\t// L\t\t\t\r
+\t\t\t\t\t\t\tREG_RSEL\t= {op16, 1'b1};\r
+\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\tMREQ\t\t= 0;\r
+\t\t\t\t\t\tend else begin\r
+\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// pc\r
+\t\t\t\t\t\t\tDINW_SEL = 0;\t\t\t\t\t\t// ALU8OUT\r
+\t\t\t\t\t\t\tWE \t\t= 6'b110x10;\t\t\t// flags, PC, hi\r
+\t\t\t\t\t\t\tALU8OP\t= {3'b000, !FETCH[3], 1'b1};\r
+\t\t\t\t\t\t\tREG_WSEL\t= 4'b0100;\t\t\t\t// H\r
+\t\t\t\t\t\t\tREG_RSEL\t= {op16, 1'b0};\r
+\t\t\t\t\t\tend\r
+//\t\t\t\t-----------------------\t\tLD (nn) r16, ld r16 (nn)  --------------------\r
+\t\t\t\t\t3'b011:\r
+\t\t\t\t\t\tcase(STAGE[2:1])\r
+\t\t\t\t\t\t\t2'b00:\tbegin // stage 1,2 - read address\r
+\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\tDINW_SEL = 1;\t\t\t\t\t// DI\r
+\t\t\t\t\t\t\t\tWE \t\t= {4'b010x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};\t// PC, hi/lo\r
+\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b111x;\t\t\t// tmp16\r
+\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t2'b01: begin\r
+\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t// regs\r
+\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\tALU16OP\t= {2'b00, STAGE[0]};\t\t\t\t\r
+\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b111x;\t\t// tmp16\r
+\t\t\t\t\t\t\t\tREG_WSEL\t= {op16, !STAGE[0]};\r
+\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\tif(FETCH[3]) begin\t// LD rr, (nn) - stage3,4\r
+\t\t\t\t\t\t\t\t\tDINW_SEL = 1;\t\t\t\t// DI\r
+\t\t\t\t\t\t\t\t\tWE \t\t= {4'b000x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};\t// lo\r
+\t\t\t\t\t\t\t\tend else begin\t\t\t// LD (nn), rr - stage3,4\r
+\t\t\t\t\t\t\t\t\tDO_SEL\t= op16[2] ? {1'b1, !STAGE[0]} : 2'b00;\t\t\t\t// ALU80/sp\r
+\t\t\t\t\t\t\t\t\tWE \t\t= 6'b000x00;\t\t// nothing\r
+\t\t\t\t\t\t\t\t\tWR\t\t\t= 1;\r
+\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t2'b10:\t\t// stage5 \r
+\t\t\t\t\t\t\t\tif(FETCH[3] & op16[2] & !STAGE[0]) begin\t// LD sp, (nn) - stage5\r
+\t\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\t\tWE \t\t= 6'b001x00;\t\t\t// SP\r
+\t\t\t\t\t\t\t\t\tALU16OP\t= 4;\t\t\t\t\t\t// NOP\r
+\t\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b101x;\t\t\t\t// tmp SP\r
+\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\t\tMREQ\t\t= 0;\r
+\t\t\t\t\t\t\t\tend else begin\r
+\t\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t\t\t// PC\r
+\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\tendcase\r
+//\t\t\t\t-----------------------\t\tNEG  --------------------\r
+\t\t\t\t\t3'b100: begin\r
+\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// pc\r
+\t\t\t\t\t\tDINW_SEL = 0;\t\t\t\t\t\t// ALU8OUT\r
+\t\t\t\t\t\tWE \t\t= 6'b110x10;\t\t\t// flags, PC, hi\r
+\t\t\t\t\t\tALU8OP\t= 5'b11111;\t\t\t\t// NEG\r
+\t\t\t\t\t\tREG_WSEL\t= 4'b011x;\t\t\t\t// A\r
+\t\t\t\t\t\tREG_RSEL\t= 4'b0110;\t\t\t\t// A\r
+\t\t\t\t\tend\r
+//\t\t\t\t-----------------------\t\tRETN, RETI  --------------------\r
+\t\t\t\t\t3'b101:\r
+\t\t\t\t\t\tcase(STAGE[1:0])\r
+\t\t\t\t\t\t\t2'b00, 2'b01:\tbegin\t\t// stage1, stage2 - pop addr\r
+\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\tDINW_SEL = 1;\t\t\t\t\t// DI\r
+\t\t\t\t\t\t\t\tWE \t\t= {4'b001x, STAGE[0] ? 1'b1 : 1'bx, !STAGE[0]};\t\t// SP, lo/hi\r
+\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b111x;\t\t\t// tmp16\r
+\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b101x;\t\t\t// SP\r
+\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\tend\t\t\r
+\t\t\t\t\t\t\t2'b10: begin\t\t\t// stage3 - jump\r
+\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t\t\t// PC\r
+\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b111x;\t\t\t\t// tmp16\r
+\t\t\t\t\t\t\t\tstatus[11] = 1'b1;\r
+\t\t\t\t\t\t\t\tstatus[7:6] = {CPUStatus[7], CPUStatus[7]};\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\tendcase\r
+//\t\t\t\t-----------------------\t\tIM  --------------------\r
+\t\t\t\t\t3'b110: begin\r
+\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// PC\r
+\t\t\t\t\t\tWE \t\t= 6'b010x00;\t\t\t// PC\r
+\t\t\t\t\t\tstatus[10:8] = {1'b1, FETCH[4:3]};\r
+\t\t\t\t\tend\r
+//\t\t\t\t-----------------------\t\tLD I A, LD R A, LD A I, LD A R, RRD, RLD  --------------------\r
+\t\t\t\t\t3'b111:\r
+\t\t\t\t\t\tcase(FETCH[5:4])\r
+\t\t\t\t\t\t\t2'b00: begin\t// LD I/R A\r
+\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\tDINW_SEL = 1'b0;\t\t\t\t\t// ALU8OUT\r
+\t\t\t\t\t\t\t\tWE \t\t= {4'b010x, !FETCH[3], FETCH[3]};\t// PC, hi/lo\r
+\t\t\t\t\t\t\t\tALU8OP\t= 29;\t\t\t\t\t\t// pass D1\r
+\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b1001;\t\t\t\t// IR, write r\r
+\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b0110;\t\t\t\t// A\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t2'b01: begin\t// LD A I/R\r
+\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\tDINW_SEL = 1'b0;\t\t\t\t\t// ALU8OUT\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b110x1x;\t\t\t// flags, PC, hi\r
+\t\t\t\t\t\t\t\tALU8OP\t= 29;\t\t\t\t\t\t// PASS D1\r
+\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b011x;\t\t\t\t// A\r
+\t\t\t\t\t\t\t\tREG_RSEL\t= {3'b100, FETCH[3]};// I/R\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t2'b10: \t\t\t// RRD, RLD\r
+\t\t\t\t\t\t\t\tcase(STAGE[1:0])\r
+\t\t\t\t\t\t\t\t\t2'b00:begin\t\t// stage1, read data\r
+\t\t\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\t\t\tDINW_SEL = 1;\t\t\t\t\t\t// DI\r
+\t\t\t\t\t\t\t\t\t\tWE \t\t= 6'b000x01;\t\t\t// lo\r
+\t\t\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b011x;\t\t\t\t// tmpLO\r
+\t\t\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b010x;\t\t\t\t// HL\r
+\t\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\t\t2'b01: begin\t// stage2, shift data\r
+\t\t\t\t\t\t\t\t\t\tDINW_SEL = 0;\t\t\t\t\t\t// ALU8OUT\r
+\t\t\t\t\t\t\t\t\t\tWE \t\t= 6'b100x11;\t\t\t// flags, hi, lo\r
+\t\t\t\t\t\t\t\t\t\tALU8OP\t= FETCH[3] ? 5'b01100 : 5'b01011;\t// RRD/RLD\r
+\t\t\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b0110;\t\t\t\t// A\r
+\t\t\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b0111;\t\t\t\t// tmpLO\r
+\t\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\t\t\tMREQ\t\t= 0;\r
+\t\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\t\t2'b10: begin // stage3 - write\r
+\t\t\t\t\t\t\t\t\t\tDO_SEL\t= 2'b00;\t\t\t\t\t// ALU80\r
+\t\t\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\t\t\tWE \t\t= 6'b000x0x;\t\t\t// nothing\r
+\t\t\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b0111;\t\t\t\t// tmpLO\r
+\t\t\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b010x;\t\t\t\t// HL\r
+\t\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\t\t\tWR\t\t\t= 1;\r
+\t\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\t\t2'b11: begin\r
+\t\t\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// PC\r
+\t\t\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t\t\t// PC\r
+\t\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\tendcase\r
+\t\t\t\t\t\t\t2'b11: begin\t// NOP\r
+\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// PC\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t\t\t// PC\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\tendcase\r
+\t\t\t\tendcase\r
+//\t\t\t\t-----------------------\t\tblock instructions  --------------------\r
+\t\t\t4'b0110:\r
+\t\t\t\tif({FETCH[5], FETCH[2]} == 4'b10)\r
+\t\t\t\t\tcase(FETCH[1:0])\r
+\t\t\t\t\t\t2'b00:\t// LDI, LDD, LDIR, LDDR\r
+\t\t\t\t\t\t\tcase(STAGE[1:0])\r
+\t\t\t\t\t\t\t\t2'b00:\tbegin\t\t\t// stage1, read data, inc/dec HL\r
+\t\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\t\tDINW_SEL = 0;\t\t\t\t\t\t// ALU8OUT\r
+\t\t\t\t\t\t\t\t\tWE \t\t= 6'b100111;\t\t\t// flags, tmpHI, hi, lo\r
+\t\t\t\t\t\t\t\t\tALU8OP\t= {4'b0111, FETCH[3]};\t// INC/DEC16\r
+\t\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b0100;\t\t\t\t// H\r
+\t\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b0101;\t\t\t\t// L\r
+\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\t2'b01:\tbegin\t\t\t// stage2, dec BC\r
+\t\t\t\t\t\t\t\t\tDINW_SEL = 0;\t\t\t\t\t\t// ALU8OUT\r
+\t\t\t\t\t\t\t\t\tWE \t\t= 6'b100011;\t\t\t// flags, hi, lo (affects PF only)\r
+\t\t\t\t\t\t\t\t\tALU8OP\t= 5'b01111;\t\t\t\t// DEC\r
+\t\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b0000;\t\t\t\t// B\r
+\t\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b0001;\t\t\t\t// C\r
+\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\t\tMREQ\t\t= 0;\r
+\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\t2'b10:\tbegin\t\t\t// stage2, write data, inc/dec DE\r
+\t\t\t\t\t\t\t\t\tDO_SEL\t= 2'b01;\t\t\t\t\t// th\r
+\t\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\t\tDINW_SEL = 0;\t\t\t\t\t\t// ALU8OUT\r
+\t\t\t\t\t\t\t\t\tWE \t\t= 6'b000x11;\t\t\t// hi, lo\r
+\t\t\t\t\t\t\t\t\tALU8OP\t= {4'b0111, FETCH[3]};\t// INC / DEC\r
+\t\t\t\t\t\t\t\t\tnext_stage = FETCH[4] ? !FLAGS[2] : 1'b1;\r
+\t\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b0010;\t\t\t\t// D\r
+\t\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b0011;\t\t\t\t// E\r
+\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\t\tWR\t\t\t= 1;\r
+\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\t2'b11: begin\r
+\t\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// PC\r
+\t\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t\t\t// PC\r
+\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\tendcase\r
+\t\t\t\t\t\t2'b01:\t// CPI, CPD, CPIR, CPDR\r
+\t\t\t\t\t\t\tcase(STAGE[1:0])\r
+\t\t\t\t\t\t\t\t2'b00: begin\t\t\t// stage1, load data\r
+\t\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\t\tDINW_SEL = 1;\t\t\t\t\t\t// DI\r
+\t\t\t\t\t\t\t\t\tWE \t\t= 6'b000x01;\t\t\t// lo\r
+\t\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b011x;\t\t\t\t// tmpLO\r
+\t\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b010x;\t\t\t\t// HL\r
+\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\t2'b01: begin\t\t\t// stage2, CP\r
+\t\t\t\t\t\t\t\t\tWE \t\t= 6'b100x0x;\t\t\t// flags\r
+\t\t\t\t\t\t\t\t\tALU8OP\t= 7;\t\t\t\t\t\t// CP\r
+\t\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b0110;\t\t\t\t// A\r
+\t\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b0111;\t\t\t\t// tmpLO\r
+\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\t\tMREQ\t\t= 0;\r
+\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\t2'b10: begin\t\t\t// stage3, dec BC\r
+\t\t\t\t\t\t\t\t\tDINW_SEL = 0;\t\t\t\t\t\t// ALU8OUT\r
+\t\t\t\t\t\t\t\t\tWE \t\t= 6'b100x11;\t\t\t// flags, hi, lo\r
+\t\t\t\t\t\t\t\t\tALU8OP\t= 5'b01111;\t\t\t\t// DEC16\r
+\t\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b0000;\t\t\t\t// B\r
+\t\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b0001;\t\t\t\t// C\r
+\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\t\tMREQ\t\t= 0;\r
+\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\t2'b11: begin\t\t\t// stage4, inc/dec HL\r
+\t\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\t\tDINW_SEL = 0;\t\t\t\t\t\t// ALU8OUT\r
+\t\t\t\t\t\t\t\t\tM1 \t\t= FETCH[4] ? (!FLAGS[2] || FLAGS[6])""b"" : 1'b1;\r
+\t\t\t\t\t\t\t\t\tWE \t\t= {1'b0, M1, 4'b0x11};\t// PC, hi, lo\r
+\t\t\t\t\t\t\t\t\tALU8OP\t= {4'b0111, FETCH[3]};\t// INC / DEC\r
+\t\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b0100;\t\t\t\t// H\r
+\t\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b0101;\t\t\t\t// L\r
+\t\t\t\t\t\t\t\t\tMREQ\t\t= M1;\r
+\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\tendcase\r
+\t\t\t\t\t\t2'b10:\t// INI, IND, INIR, INDR\r
+\t\t\t\t\t\t\tcase(STAGE[1:0])\r
+\t\t\t\t\t\t\t\t2'b00: \tbegin\t\t\t// stage1, in data, dec B\r
+\t\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\t\tDINW_SEL = 0;\t\t\t\t\t\t// ALU8OUT\r
+\t\t\t\t\t\t\t\t\tWE \t\t= 6'b100110;\t\t\t// flags, tmpHI, hi\r
+\t\t\t\t\t\t\t\t\tALU8OP\t= 10;\t\t\t\t\t\t// DEC\r
+\t\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b0000;\t\t\t\t// B\r
+\t\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b000x;\t\t\t\t// BC\r
+\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\t\tMREQ\t\t= 0;\r
+\t\t\t\t\t\t\t\t\tIORQ\t\t= 1;\r
+\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\t2'b01:\tbegin\t\t\t// stage2, write data, inc/dec HL\r
+\t\t\t\t\t\t\t\t\tDO_SEL\t= 2'b01;\t\t\t\t\t// th\r
+\t\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\t\tDINW_SEL = 0;\t\t\t\t\t\t// ALU8OUT\r
+\t\t\t\t\t\t\t\t\tWE \t\t= 6'b000x11;\t\t\t// hi, lo\r
+\t\t\t\t\t\t\t\t\tALU8OP\t= {4'b0111, FETCH[3]};\t// INC / DEC\r
+\t\t\t\t\t\t\t\t\tnext_stage = FETCH[4] ? FLAGS[6] : 1'b1;\r
+\t\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b0100;\t\t\t\t// H\r
+\t\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b0101;\t\t\t\t// L\r
+\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\t\tWR\t\t\t= 1;\r
+\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\t2'b10:\tbegin\t\t\t// stage3\r
+\t\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t\t\t// PC\r
+\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\tendcase\r
+\t\t\t\t\t\t2'b11:\t// OUTI/OUTD/OTIR/OTDR\r
+\t\t\t\t\t\t\tcase(STAGE[1:0])\r
+\t\t\t\t\t\t\t\t2'b00:\tbegin\t\t\t// stage1, load data, inc/dec HL\r
+\t\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\t\tDINW_SEL = 0;\t\t\t\t\t\t// ALU8OUT\r
+\t\t\t\t\t\t\t\t\tWE \t\t= 6'b000111;\t\t\t// tmpHI, hi, lo\r
+\t\t\t\t\t\t\t\t\tALU8OP\t= {4'b0111, FETCH[3]};\t// INC / DEC\r
+\t\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b0100;\t\t\t\t// H\r
+\t\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b0101;\t\t\t\t// L\r
+\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\t2'b01: \tbegin\t\t\t// stage2, out data, dec B\r
+\t\t\t\t\t\t\t\t\tDO_SEL\t= 2'b01;\t\t\t\t\t// th\r
+\t\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\t\tDINW_SEL = 0;\t\t\t\t\t\t// ALU8OUT\r
+\t\t\t\t\t\t\t\t\tWE \t\t= 6'b100x10;\t\t\t// flags, hi\r
+\t\t\t\t\t\t\t\t\tALU8OP\t= 10;\t\t\t\t\t\t// DEC\r
+\t\t\t\t\t\t\t\t\tnext_stage = FETCH[4] ? (ALU80 == 8'b00000001) : 1'b1;\r
+\t\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b0000;\t\t\t\t// B\r
+\t\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b000x;\t\t\t\t// BC\r
+\t\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\t\tMREQ\t\t= 0;\r
+\t\t\t\t\t\t\t\t\tIORQ\t\t= 1;\r
+\t\t\t\t\t\t\t\t\tWR\t\t\t= 1;\r
+\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t\t2'b10:\tbegin\t\t\t// stage3\r
+\t\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t\t\t// PC\r
+\t\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\tendcase\r
+\t\t\t\t\tendcase\r
+\t\t\t\telse begin\t\t\t// NOP\r
+\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// PC\r
+\t\t\t\t\tWE \t\t= 6'b010x00;\t\t\t// PC\r
+\t\t\t\tend\r
+//------------------------------------------- CB + opcode ----------------------------------------------------\r
+\t\t\t4'b1000, 4'b1001, 4'b1010, 4'b1011:\t\t\t\t\t\t\t\t\t\t// CB class (rot/shift, bit/res/set)\r
+\t\t\t\tcase({STAGE[1:0], CPUStatus[4], op0mem})\t\t\t\t\r
+\t\t\t\t\t4'b00_0_0: begin\t\t\t\t\t\t// execute reg-reg\r
+\t\t\t\t\t\tDINW_SEL = 0;\t\t\t\t\t\t// ALU8OUT\r
+\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// pc\r
+\t\t\t\t\t\tWE \t\t= {!FETCH[7], 3'b10x, FETCH[7:6] == 2'b01 ? 2'b00 : {!opd[0], opd[0]}};\t// flags, hi/lo\r
+\t\t\t\t\t\tALU8OP\t= 28;\t\t\t\t\t// BIT\r
+\t\t\t\t\t\tREG_WSEL\t= {1'b0, opd[2:0]};\r
+\t\t\t\t\tend\r
+\t\t\t\t\t4'b00_0_1, 4'b00_1_0, 4'b00_1_1: begin\t\t\t\t// stage1, (HL-X) - read data\r
+\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t// regs\r
+\t\t\t\t\t\tDINW_SEL = 1;\t\t\t\t\t// DI\r
+\t\t\t\t\t\tWE \t\t= opd[0] ? 6'b000001 : 6'b000010;\t// lo/hi\r
+\t\t\t\t\t\tALU16OP\t= CPUStatus[4] ? 3'd3 : 3'd0;\t\t\t\t\t// ADD - NOP\r
+\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\tREG_WSEL = FETCH[7:6] == 2'b01 ? 4'b111x : {1'b0, opd[2:0]};\t// dest, tmp16 for BIT\r
+\t\t\t\t\t\tREG_RSEL\t= 4'b010x;\t\t\t// HL\r
+\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\tend\r
+\t\t\t\t\t4'b01_0_1, 4'b01_1_0, 4'b01_1_1:\t\t// stage2 (HL-X) - execute, write\r
+\t\t\t\t\t\tcase(FETCH[7:6])\r
+\t\t\t\t\t\t\t2'b00, 2'b10, 2'b11: begin\t\t// exec + write\r
+\t\t\t\t\t\t\t\tDINW_SEL = 0;\t\t\t\t\t// ALU8OUT\r
+\t\t\t\t\t\t\t\tDO_SEL\t= 2'b11;\t\t\t\t// ALU8OUT[7:0]\r
+\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\tWE \t\t= {!FETCH[7], 3'b00x, !opd[0], opd[0]};\t// flags, hi/lo\r
+\t\t\t\t\t\t\t\tALU8OP\t= 28;\r
+\t\t\t\t\t\t\t\tALU16OP\t= CPUStatus[4] ? 3'd3 : 3'd0;\r
+\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\tREG_WSEL\t= {1'b0, opd[2:0]};\r
+\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b010x;\t\t\t\t// HL\r
+\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\tWR\t\t\t= 1;\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t2'b01: begin\t\t\t\t\t\t\t// BIT, no write\r
+\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b110xxx;\t\t\t// flags, PC\r
+\t\t\t\t\t\t\t\tALU8OP\t= 28;\t\t\t\t\t\t// BIT\r
+\t\t\t\t\t\t\t\tREG_WSEL\t= {3'b111, opd[0]};\t// tmp\r
+\t\t\t\t\t\t\tend \r
+\t\t\t\t\t\tendcase\r
+\t\t\t\t\t4'b10_0_1, 4'b10_1_0, 4'b10_1_1: begin\t// (HL-X) - load next op\r
+\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t\t\t// pc\r
+\t\t\t\t\t\tWE \t\t= 6'b010x00;\t\t\t\t\t// PC\r
+\t\t\t\t\tend\r
+\t\t\t\tendcase\r
+//------------------------------------------- // RST, NMI, INT ----------------------------------------------------\r
+\t\t\t4'b1110: begin \t\t\t// RESET: IR <- 0, IM <- 0, IFF1,IFF2 <- 0, pC <- 0\r
+\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\tDINW_SEL = 0;\t\t\t\t\t\t// ALU8OUT\r
+\t\t\t\t\tWE \t\t= 6'bx1xx11;\t\t\t// PC, hi, lo\r
+\t\t\t\t\tALU8OP\t= 29;\t\t\t\t\t\t// pass D1\r
+\t\t\t\t\tALU16OP\t= 4;\t\t\t\t\t\t// NOP\r
+\t\t\t\t\tREG_WSEL\t= 4'b1001;\t\t\t\t// IR, write r\r
+\t\t\t\t\tREG_RSEL\t= 4'b110x;\t\t\t\t// const\r
+\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\tMREQ\t\t= 0;\r
+\t\t\t\t\tstatus[11:6] = 6'b110000;\t\t// IM0, DI\r
+\t\t\t\tend \r
+\t\t\t4'b1101:\t\t\t\t\t\t// NMI\r
+\t\t\t\tcase(STAGE[1:0])\r
+\t\t\t\t\t2'b00: begin\t\t\r
+\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t// pc\r
+\t\t\t\t\t\tWE \t\t= 6'b010x00;\t\t// PC\r
+\t\t\t\t\t\tALU16OP\t= intop;\t\t\t\t// DEC/DEC2 (if block instruction interrupted)\r
+\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\tMREQ\t\t= 0;\r
+\t\t\t\t\tend\r
+\t\t\t\t\t2'b01, 2'b10: begin\r
+\t\t\t\t\t\tDO_SEL\t= {1'b0, !STAGE[0]};\t// pc hi/lo\r
+\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\tWE \t\t= 6'b001x00;\t\t\t// SP\r
+\t\t\t\t\t\tALU16OP\t= 5;\t\t\t\t\t\t// DEC\r
+\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\tREG_WSEL\t= 4'b1xxx;\t\t\t\t// pc\r
+\t\t\t\t\t\tREG_RSEL\t= 4'b101x;\t\t\t\t// sp\r
+\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\tWR\t\t\t= 1;\r
+\t\t\t\t\t\tstatus[11]\t= 1'b1;\r
+\t\t\t\t\t\tstatus[7:6] = {CPUStatus[7], 1'b0};\t// reset IFF1\r
+\t\t\t\t\tend\r
+\t\t\t\t\t2'b11: begin\r
+\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\tWE \t\t= 6'b010x00;\t\t\t// PC\r
+\t\t\t\t\t\tREG_RSEL\t= 4'b110x;\t\t\t\t// const\r
+\t\t\t\t\tend\r
+\t\t\t\tendcase\r
+\t\t\t4'b1100:\t\t\t\t// INT\r
+\t\t\t\tcase(CPUStatus[9:8])\r
+\t\t\t\t\t2'b00, 2'b01, 2'b10: begin\t\t// IM0, IM1\t\r
+\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t\t// pc\r
+\t\t\t\t\t\tWE \t\t= 6'b010x00;\t\t\t// PC\r
+\t\t\t\t\t\tALU16OP\t= intop;\t\t\t\t\t// DEC/DEC2 (if block instruction interrupted)\r
+\t\t\t\t\t\tMREQ\t\t= 0;\r
+\t\t\t\t\t\tIORQ\t\t= 1;\r
+\t\t\t\t\t\tstatus[11]\t= 1'b1;\r
+\t\t\t\t\t\tstatus[7:6] = 2'b0;\t\t\t\t// reset IFF1, IFF2\r
+\t\t\t\t\tend\r
+\t\t\t\t\t2'b11: \t\t\t\t\t\t\t\t// IM2\r
+\t\t\t\t\t\tcase(STAGE[2:0])\r
+\t\t\t\t\t\t\t3'b000: begin\r
+\t\t\t\t\t\t\t\tALU160_SEL = 1;\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\tDINW_SEL = 1;\t\t\t\t\t// DI\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b010x01;\t\t// PC, lo\r
+\t\t\t\t\t\t\t\tALU16OP\t= intop;\t\t\t\t// DEC/DEC2 (if block instruction interrupted)\r
+\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b1000;\t\t\t// Itmp, no write r\r
+\t\t\t\t\t\t\t\tMREQ\t\t= 0;\r
+\t\t\t\t\t\t\t\tIORQ\t\t= 1;\r
+\t\t\t\t\t\t\t\tstatus[11]\t= 1'b1;\r
+\t\t\t\t\t\t\t\tstatus[7:6] = 2'b0;\t\t\t// reset IFF1, IFF2\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t3'b001, 3'b010: begin\t\t\t// push pc\r
+\t\t\t\t\t\t\t\tDO_SEL\t= {1'b0, !STAGE[0]};\t// pc hi/lo\r
+\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b001x00;\t\t\t// SP\r
+\t\t\t\t\t\t\t\tALU16OP\t= 5;\t\t\t\t\t\t// DEC\r
+\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b1xxx;\t\t\t\t// pc\r
+\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b101x;\t\t\t\t// sp\r
+\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\t\tWR\t\t\t= 1;\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t3'b011, 3'b100:\tbegin\t\t\t// read address\r
+\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\tDINW_SEL = 1;\t\t\t\t\t\t// DI\r
+\t\t\t\t\t\t\t\tWE \t\t= {4'b0x0x, STAGE[0] ? 1'bx : 1'b1, STAGE[0]};\t\t\t\t// hi/lo\r
+\t\t\t\t\t\t\t\tALU16OP\t= {2'b00, !STAGE[0]};// NOP/INC\r
+\t\t\t\t\t\t\t\tnext_stage = 1;\r
+\t\t\t\t\t\t\t\tREG_WSEL\t= 4'b111x;\t\t\t\t// tmp16\r
+\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b1000;\t\t\t\t// I-Itmp\r
+\t\t\t\t\t\t\t\tM1 \t\t= 0;\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\t\t3'b101: begin\t\t\t\t\t\t// jump\r
+\t\t\t\t\t\t\t\tALU160_SEL = 0;\t\t\t\t\t// regs\r
+\t\t\t\t\t\t\t\tWE \t\t= 6'b010x00;\t\t\t// PC\r
+\t\t\t\t\t\t\t\tREG_RSEL\t= 4'b111x;\t\t\t\t// tmp16\r
+\t\t\t\t\t\t\tend\r
+\t\t\t\t\t\tendcase\r
+\t\t\t\tendcase\r
+\t\tendcase\t\r
+\tend\r
+\r
+endmodule\r
+"
+"// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+// This file is part of the M32632 project\r
+// http://opencores.org/project,m32632\r
+//\r
+// Filename: example.v\r
+// Version:  1.0\r
+// Date:     30 May 2015\r
+//\r
+// Copyright (C) 2015 Udo Moeller\r
+// \r
+// This source file may be used and distributed without \r
+// restriction provided that this copyright statement is not \r
+// removed from the file and that any derivative work contains \r
+// the original copyright notice and the associated disclaimer.\r
+// \r
+// This source file is free software; you can redistribute it \r
+// and/or modify it under the terms of the GNU Lesser General \r
+// Public License as published by the Free Software Foundation;\r
+// either version 2.1 of the License, or (at your option) any \r
+// later version. \r
+// \r
+// This source is distributed in the hope that it will be \r
+// useful, but WITHOUT ANY WARRANTY; without even the implied \r
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR \r
+// PURPOSE. See the GNU Lesser General Public License for more \r
+// details. \r
+// \r
+// You should have received a copy of the GNU Lesser General \r
+// Public License along with this source; if not, download it \r
+// from http://www.opencores.org/lgpl.shtml \r
+// \r
+// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\tModules contained in this file:\r
+//\texample\t\tYour first system with the M32632 CPU\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+module example ( CLK, RESET_N, NMI_N, INT_N, IN_REG, OUT_REG);\r
+\r
+input\t\t\tCLK;\r
+input\t\t\tRESET_N;\r
+input\t\t\tNMI_N;\r
+input\t\t\tINT_N;\r
+\r
+input\t [7:0]\tIN_REG;\r
+\r
+output\t [7:0]\tOUT_REG;\r
+\r
+reg\t\t\t\tnmi_reg,int_reg;\r
+\r
+wire\t\t\tIC_MDONE;\r
+wire\t\t\tDC_MDONE;\r
+wire\t\t\tENWR;\r
+wire\t\t\tWAMUX;\r
+wire\t[11:2]\tWADDR;\r
+wire\t[31:0]\tDRAM_Q;\r
+wire\t [2:0]\tIWCTRL;\r
+wire\t [2:0]\tDWCTRL;\r
+wire\t\t\tIC_ACC;\r
+wire\t[27:0]\tIDRAM_ADR;\r
+wire\t\t\tDC_ACC;\r
+wire\t\t\tDC_WR;\r
+wire\t[27:0]\tDRAM_ADR;\r
+wire\t[35:0]\tDRAM_DI;\r
+\r
+wire\t[31:0]\tIO_A;\r
+wire\t[31:0]\tIO_DI;\r
+wire\t [3:0]\tIO_BE;\r
+wire\t\t\tIO_RD;\r
+wire\t\t\tIO_WR;\r
+wire\t\t\tIO_READY;\r
+wire\t\t\tENDRAM;\r
+wire\t[31:0]\tIO_Q;\r
+wire\t\t\tW_OUT_REG;\r
+wire\t\t\tRST_N;\r
+\r
+wire\t[31:0]\tBOOT_DAT;\r
+wire\t[31:0]\tSTAT_DAT;\r
+wire\t [7:0]\tIN_DAT;\r
+\r
+wire\t [7:0]\tSTATSIGS;\r
+wire\t\t\tCOP_GO;\r
+wire\t[23:0]\tCOP_OP;\r
+wire   [127:0]\tCOP_OUT;\r
+wire\t\t\tCOP_DONE;\r
+wire\t[63:0]\tCOP_IN;\r
+\r
+M32632\tCPU(\r
+\t// ++++++++++ Basic Signals\r
+\t.BCLK(CLK),\r
+\t.MCLK(~CLK),\r
+\t.WRCFG(1'b1),\r
+\t.BRESET(RST_N),\r
+\t.NMI_N(nmi_reg),\r
+\t.INT_N(int_reg),\r
+\t.STATUS(),\r
+\t.ILO(),\r
+\t.STATSIGS(STATSIGS),\r
+\t// +++++++++ General Purpose Interface\r
+\t.IO_WR(IO_WR),\r
+\t.IO_RD(IO_RD),\r
+\t.IO_A(IO_A),\r
+\t.IO_BE(IO_BE),\r
+\t.IO_DI(IO_DI),\r
+\t.IO_Q(IO_Q),\r
+\t.IO_READY(IO_READY),\r
+\t// +++++++++ DRAM Interface In\r
+\t.ENDRAM(ENDRAM),\r
+\t.IC_MDONE(IC_MDONE),\r
+\t.DC_MDONE(DC_MDONE),\r
+\t.ENWR(ENWR),\r
+\t.WAMUX(WAMUX),\r
+\t.WADDR(WADDR),\r
+\t.DRAM_Q(DRAM_Q),\r
+\t.DWCTRL(DWCTRL),\r
+\t.IWCTRL(IWCTRL),\r
+\t// +++++++++ DRAM Interface Out\r
+\t.IC_ACC(IC_ACC),\r
+\t.IDRAM_ADR(IDRAM_ADR),\r
+\t.DC_ACC(DC_ACC),\r
+\t.DC_WR(DC_WR),\r
+\t.DRAM_ADR(DRAM_ADR),\r
+\t.DRAM_DI(DRAM_DI),\r
+\t// ++++++++++ DMA Interface\r
+\t.HOLD(1'b1),\r
+\t.HLDA(),\r
+\t.FILLRAM(1'b0),\r
+\t.DMA_AA(24'd0),\r
+\t// ++++++++++ Coprocessor Interface\r
+\t.COP_GO(COP_GO),\r
+\t.COP_OP(COP_OP),\r
+\t.COP_OUT(COP_OUT),\r
+\t.COP_DONE(COP_DONE),\r
+\t.COP_IN(COP_IN));\r
+\t\r
+ex_io_bus_ctrl u_bus_ctrl(\r
+\t.CLK(CLK),\r
+\t.RESET_N(RESET_N),\r
+\t.RST_N(RST_N),\r
+\t.ENDRAM(ENDRAM),\r
+\t.IO_WR(IO_WR),\r
+\t.IO_RD(IO_RD),\r
+\t.IO_A(IO_A[31:28]),\r
+\t.IO_BE(IO_BE),\r
+\t.IO_Q(IO_Q),\r
+\t.IO_READY(IO_READY),\r
+\t.W_OUT_REG(W_OUT_REG),\r
+\t.IN_DAT(IN_DAT),\r
+\t.BOOT_DAT(BOOT_DAT),\r
+\t.STAT_DAT(STAT_DAT));\r
+\r
+ex_in_reg u_in_reg(\r
+\t.CLK(CLK),\r
+\t.IN_REG(IN_REG),\r
+\t.IN_DAT(IN_DAT));\r
+\t\r
+ex_out_reg u_out_reg(\r
+\t.CLK(CLK),\r
+\t.OUT_REG(OUT_REG),\r
+\t.W_OUT_REG(W_OUT_REG),\r
+\t.DIN(IO_DI));\r
+\t\r
+ex_boot_rom u_boot_rom(\r
+\t.CLK(CLK),\r
+\t.ADDR(IO_A[9:2]),\r
+\t.DATA(BOOT_DAT));\r
+\r
+ex_statcou u_statcou(\r
+\t.CLK(CLK),\r
+\t.RST_N(RST_N),\r
+\t.STATSIGS(STATSIGS),\r
+\t.ADDR(IO_A[4:2]),\r
+\t.DATA(STAT_DAT));\r
+\r
+ex_copro u_copro(\r
+\t.CLK(CLK),\r
+\t.COP_GO(COP_GO),\r
+\t.COP_OP(COP_OP),\r
+\t.COP_INP(COP_OUT),\r
+\t.COP_DONE(COP_DONE),\r
+\t.COP_OUTP(COP_IN));\r
+\t\r
+ex_dram_emul u_dram_emul(\r
+\t.MCLK(CLK),\r
+\t.RST_N(RST_N),\r
+\t.IC_ACC(IC_ACC),\r
+\t.IDRAM_ADR(IDRAM_ADR),\r
+\t.DC_ACC(DC_ACC),\r
+\t.DC_WR(DC_WR),\r
+\t.DRAM_ADR(DRAM_ADR),\r
+\t.DRAM_DI(DRAM_DI),\r
+\t.IC_MDONE(IC_MDONE),\r
+\t.DC_MDONE(DC_MDONE),\r
+\t.ENWR(ENWR),\r
+\t.WAMUX(WAMUX),\r
+\t.WADDR(WADDR),\r
+\t.MEM_Q(DRAM_Q),\r
+\t.DWCTRL(DWCTRL),\r
+\t.IWCTRL(IWCTRL) );\r
+\r
+\talways @(posedge CLK)\t// recommended to synchronize this signals\r
+\t\tbegin\r
+\t\t\tnmi_reg <= NMI_N;\r
+\t\t\tint_reg <= INT_N;\r
+\t\tend\r
+\r
+endmodule\r
+"
+"/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  Non-restoring unsigned divider                             ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2002 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS\'\' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: div_uu.v,v 1.3 2003/09/17 13:08:53 rherveille Exp $
+//
+//  $Date: 2003/09/17 13:08:53 $
+//  $Revision: 1.3 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: div_uu.v,v $
+//               Revision 1.3  2003/09/17 13:08:53  rherveille
+//               Fixed a bug in the remainder output. Changed a hard value into the required parameter.
+//               Fixed a bug in the testbench.
+//
+//               Revision 1.2  2002/10/31 13:54:58  rherveille
+//               Fixed a bug in the remainder output of div_su.v
+//
+//               Revision 1.1.1.1  2002/10/29 20:29:10  rherveille
+//
+//
+//
+
+//synopsys translate_off
+`timescale 1ns/10ps
+//synopsys translate_on
+
+module zet_div_uu(clk, ena, z, d, q, s, div0, ovf);
+
+\t//
+\t// parameters
+\t//
+\tparameter z_width = 16;
+\tparameter d_width = z_width /2;
+\t
+\t//
+\t// inputs & outputs
+\t//
+\tinput clk;               // system clock
+\tinput ena;               // clock enable
+
+\tinput  [z_width -1:0] z; // divident
+\tinput  [d_width -1:0] d; // divisor
+\toutput [d_width -1:0] q; // quotient
+\toutput [d_width -1:0] s; // remainder
+\toutput div0;
+\toutput ovf;
+\treg [d_width-1:0] q;
+\treg [d_width-1:0] s;
+\treg div0;
+\treg ovf;
+
+\t//\t
+\t// functions
+\t//
+\tfunction [z_width:0] gen_s;
+\t\tinput [z_width:0] si;
+\t\tinput [z_width:0] di;
+\tbegin
+\t  if(si[z_width])
+\t    gen_s = {si[z_width-1:0], 1\'b0} + di;
+\t  else
+\t    gen_s = {si[z_width-1:0], 1\'b0} - di;
+\tend
+\tendfunction
+
+\tfunction [d_width-1:0] gen_q;
+\t\tinput [d_width-1:0] qi;
+\t\tinput [z_width:0] si;
+\tbegin
+\t  gen_q = {qi[d_width-2:0], ~si[z_width]};
+\tend
+\tendfunction
+
+\tfunction [d_width-1:0] assign_s;
+\t\tinput [z_width:0] si;
+\t\tinput [z_width:0] di;
+\t\treg [z_width:0] tmp;
+\tbegin
+\t  if(si[z_width])
+\t    tmp = si + di;
+\t  else
+\t    tmp = si;
+
+\t  assign_s = tmp[z_width-1:z_width-d_width];
+\tend
+\tendfunction
+
+\t//
+\t// variables
+\t//
+\treg [d_width-1:0] q_pipe  [d_width-1:0];
+\treg [z_width:0] s_pipe  [d_width:0];
+\treg [z_width:0] d_pipe  [d_width:0];
+
+\treg [d_width:0] div0_pipe, ovf_pipe;
+\t//
+\t// perform parameter checks
+\t//
+\t// synopsys translate_off
+\tinitial
+\tbegin
+\t  if(d_width !== z_width / 2)
+\t    $display(""div.v parameter error (d_width != z_width/2)."");
+\tend
+\t// synopsys translate_on
+
+\tinteger n0, n1, n2, n3;
+
+\t// generate divisor (d) pipe
+\talways @(d)
+\t  d_pipe[0] <= {1\'b0, d, {(z_width-d_width){1\'b0}} };
+
+\talways @(posedge clk)
+\t  if(ena)
+\t    for(n0=1; n0 <= d_width; n0=n0+1)
+\t       d_pipe[n0] <= d_pipe[n0-1];
+
+\t// generate internal remainder pipe
+\talways @(z)
+\t  s_pipe[0] <= z;
+
+\talways @(posedge clk)
+\t  if(ena)
+\t    for(n1=1; n1 <= d_width; n1=n1+1)
+\t       s_pipe[n1] <= gen_s(s_pipe[n1-1], d_pipe[n1-1]);
+
+\t// generate quotient pipe
+\talways @(posedge clk)
+\t  q_pipe[0] <= 0;
+
+\talways @(posedge clk)
+\t  if(ena)
+\t    for(n2=1; n2 < d_width; n2=n2+1)
+\t       q_pipe[n2] <= gen_q(q_pipe[n2-1], s_pipe[n2]);
+
+
+\t// flags (divide_by_zero, overflow)
+\talways @(z or d)
+\tbegin
+\t  ovf_pipe[0]  <= !(z[z_width-1:d_width] < d);
+\t  div0_pipe[0] <= ~|d;
+\tend
+
+\talways @(posedge clk)
+\t  if(ena)
+\t    for(n3=1; n3 <= d_width; n3=n3+1)
+\t    begin
+\t        ovf_pipe[n3] <= ovf_pipe[n3-1];
+\t        div0_pipe[n3] <= div0_pipe[n3-1];
+\t    end
+
+\t// assign outputs
+\talways @(posedge clk)
+\t  if(ena)
+\t    ovf <= ovf_pipe[d_width];
+
+\talways @(posedge clk)
+\t  if(ena)
+\t    div0 <= div0_pipe[d_width];
+
+\talways @(posedge clk)
+\t  if(ena)
+\t    q <= gen_q(q_pipe[d_width-1], s_pipe[d_width]);
+
+\talways @(posedge clk)
+\t  if(ena)
+\t    s <= assign_s(s_pipe[d_width], d_pipe[d_width]);
+endmodule
+
+
+
+"
+"/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used solely      *
+*     for design, simulation, implementation and creation of design files      *
+*     limited to Xilinx devices or technologies. Use with non-Xilinx           *
+*     devices or technologies is expressly prohibited and immediately          *
+*     terminates your license.                                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION ""AS IS"" SOLELY     *
+*     FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY     *
+*     PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE              *
+*     IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS       *
+*     MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY       *
+*     CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY        *
+*     RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY        *
+*     DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE    *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A    *
+*     PARTICULAR PURPOSE.                                                      *
+*                                                                              *
+*     Xilinx products are not intended for use in life support appliances,     *
+*     devices, or systems.  Use in such applications are expressly             *
+*     prohibited.                                                              *
+*                                                                              *
+*     (c) Copyright 1995-2015 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+// You must compile the wrapper file ph_fifo_core_spartan6.v when simulating
+// the core, ph_fifo_core_spartan6. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the ""CORE Generator Help"".
+
+// The synthesis directives ""translate_off/translate_on"" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+`timescale 1ns/1ps
+
+module ph_fifo_core_spartan6(
+  rst,
+  wr_clk,
+  rd_clk,
+  din,
+  wr_en,
+  rd_en,
+  dout,
+  full,
+  empty
+);
+
+input rst;
+input wr_clk;
+input rd_clk;
+input [7 : 0] din;
+input wr_en;
+input rd_en;
+output [7 : 0] dout;
+output full;
+output empty;
+
+// synthesis translate_off
+
+  FIFO_GENERATOR_V9_3 #(
+    .C_ADD_NGC_CONSTRAINT(0),
+    .C_APPLICATION_TYPE_AXIS(0),
+    .C_APPLICATION_TYPE_RACH(0),
+    .C_APPLICATION_TYPE_RDCH(0),
+    .C_APPLICATION_TYPE_WACH(0),
+    .C_APPLICATION_TYPE_WDCH(0),
+    .C_APPLICATION_TYPE_WRCH(0),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_AXI_ARUSER_WIDTH(1),
+    .C_AXI_AWUSER_WIDTH(1),
+    .C_AXI_BUSER_WIDTH(1),
+    .C_AXI_DATA_WIDTH(64),
+    .C_AXI_ID_WIDTH(4),
+    .C_AXI_RUSER_WIDTH(1),
+    .C_AXI_TYPE(0),
+    .C_AXI_WUSER_WIDTH(1),
+    .C_AXIS_TDATA_WIDTH(64),
+    .C_AXIS_TDEST_WIDTH(4),
+    .C_AXIS_TID_WIDTH(8),
+    .C_AXIS_TKEEP_WIDTH(4),
+    .C_AXIS_TSTRB_WIDTH(4),
+    .C_AXIS_TUSER_WIDTH(4),
+    .C_AXIS_TYPE(0),
+    .C_COMMON_CLOCK(0),
+    .C_COUNT_TYPE(0),
+    .C_DATA_COUNT_WIDTH(5),
+    .C_DEFAULT_VALUE(""BlankString""),
+    .C_DIN_WIDTH(8),
+    .C_DIN_WIDTH_AXIS(1),
+    .C_DIN_WIDTH_RACH(32),
+    .C_DIN_WIDTH_RDCH(64),
+    .C_DIN_WIDTH_WACH(32),
+    .C_DIN_WIDTH_WDCH(64),
+    .C_DIN_WIDTH_WRCH(2),
+    .C_DOUT_RST_VAL(""AA""),
+    .C_DOUT_WIDTH(8),
+    .C_ENABLE_RLOCS(0),
+    .C_ENABLE_RST_SYNC(1),
+    .C_ERROR_INJECTION_TYPE(0),
+    .C_ERROR_INJECTION_TYPE_AXIS(0),
+    .C_ERROR_INJECTION_TYPE_RACH(0),
+    .C_ERROR_INJECTION_TYPE_RDCH(0),
+    .C_ERROR_INJECTION_TYPE_WACH(0),
+    .C_ERROR_INJECTION_TYPE_WDCH(0),
+    .C_ERROR_INJECTION_TYPE_WRCH(0),
+    .C_FAMILY(""spartan6""),
+    .C_FULL_FLAGS_RST_VAL(0),
+    .C_HAS_ALMOST_EMPTY(0),
+    .C_HAS_ALMOST_FULL(0),
+    .C_HAS_AXI_ARUSER(0),
+    .C_HAS_AXI_AWUSER(0),
+    .C_HAS_AXI_BUSER(0),
+    .C_HAS_AXI_RD_CHANNEL(0),
+    .C_HAS_AXI_RUSER(0),
+    .C_HAS_AXI_WR_CHANNEL(0),
+    .C_HAS_AXI_WUSER(0),
+    .C_HAS_AXIS_TDATA(0),
+    .C_HAS_AXIS_TDEST(0),
+    .C_HAS_AXIS_TID(0),
+    .C_HAS_AXIS_TKEEP(0),
+    .C_HAS_AXIS_TLAST(0),
+    .C_HAS_AXIS_TREADY(1),
+    .C_HAS_AXIS_TSTRB(0),
+    .C_HAS_AXIS_TUSER(0),
+    .C_HAS_BACKUP(0),
+    .C_HAS_DATA_COUNT(0),
+    .C_HAS_DATA_COUNTS_AXIS(0),
+    .C_HAS_DATA_COUNTS_RACH(0),
+    .C_HAS_DATA_COUNTS_RDCH(0),
+    .C_HAS_DATA_COUNTS_WACH(0),
+    .C_HAS_DATA_COUNTS_WDCH(0),
+    .C_HAS_DATA_COUNTS_WRCH(0),
+    .C_HAS_INT_CLK(0),
+    .C_HAS_MASTER_CE(0),
+    .C_HAS_MEMINIT_FILE(0),
+    .C_HAS_OVERFLOW(0),
+    .C_HAS_PROG_FLAGS_AXIS(0),
+    .C_HAS_PROG_FLAGS_RACH(0),
+    .C_HAS_PROG_FLAGS_RDCH(0),
+    .C_HAS_PROG_FLAGS_WACH(0),
+    .C_HAS_PROG_FLAGS_WDCH(0),
+    .C_HAS_PROG_FLAGS_WRCH(0),
+    .C_HAS_RD_DATA_COUNT(0),
+    .C_HAS_RD_RST(0),
+    .C_HAS_RST(1),
+    .C_HAS_SLAVE_CE(0),
+    .C_HAS_SRST(0),
+    .C_HAS_UNDERFLOW(0),
+    .C_HAS_VALID(0),
+    .C_HAS_WR_ACK(0),
+    .C_HAS_WR_DATA_COUNT(0),
+    .C_HAS_WR_RST(0),
+    .C_IMPLEMENTATION_TYPE(2),
+    .C_IMPLEMENTATION_TYPE_AXIS(1),
+    .C_IMPLEMENTATION_TYPE_RACH(1),
+    .C_IMPLEMENTATION_TYPE_RDCH(1),
+    .C_IMPLEMENTATION_TYPE_WACH(1),
+    .C_IMPLEMENTATION_TYPE_WDCH(1),
+    .C_IMPLEMENTATION_TYPE_WRCH(1),
+    .C_INIT_WR_PNTR_VAL(0),
+    .C_INTERFACE_TYPE(0),
+    .C_MEMORY_TYPE(2),
+    .C_MIF_FILE_NAME(""BlankString""),
+    .C_MSGON_VAL(1),
+    .C_OPTIMIZATION_MODE(0),
+    .C_OVERFLOW_LOW(0),
+    .C_PRELOAD_LATENCY(0),
+    .C_PRELOAD_REGS(1),
+    .C_PRIM_FIFO_TYPE(""512x36""),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
+    .C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
+    .C_PROG_EMPTY_TYPE(0),
+    .C_PROG_EMPTY_TYPE_AXIS(0),
+    .C_PROG_EMPTY_TYPE_RACH(0),
+    .C_PROG_EMPTY_TYPE_RDCH(0),
+    .C_PROG_EMPTY_TYPE_WACH(0),
+    .C_PROG_EMPTY_TYPE_WDCH(0),
+    .C_PROG_EMPTY_TYPE_WRCH(0),
+    .C_PROG_FULL_THRESH_ASSERT_VAL(31),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
+    .C_PROG_FULL_THRESH_NEGATE_VAL(30),
+    .C_PROG_FULL_TYPE(0),
+    .C_PROG_FULL_TYPE_AXIS(0),
+    .C_PROG_FULL_TYPE_RACH(0),
+    .C_PROG_FULL_TYPE_RDCH(0),
+    .C_PROG_FULL_TYPE_WACH(0),
+    .C_PROG_FULL_TYPE_WDCH(0),
+    .C_PROG_FULL_TYPE_WRCH(0),
+    .C_RACH_TYPE(0),
+    .C_RD_DATA_COUNT_WIDTH(5),
+    .C_RD_DEPTH(32),
+    .C_RD_FREQ(1),
+    .C_RD_PNTR_WIDTH(5),
+    .C_RDCH_TYPE(0),
+    .C_REG_SLICE_MODE_AXIS(0),
+    .C_REG_SLICE_MODE_RACH(0),
+    .C_REG_SLICE_MODE_RDCH(0),
+    .C_REG_SLICE_MODE_WACH(0),
+    .C_REG_SLICE_MODE_WDCH(0),
+    .C_REG_SLICE_MODE_WRCH(0),
+    .C_SYNCHRONIZER_STAGE(2),
+    .C_UNDERFLOW_LOW(0),
+    .C_USE_COMMON_OVERFLOW(0),
+    .C_USE_COMMON_UNDERFLOW(0),
+    .C_USE_DEFAULT_SETTINGS(0),
+    .C_USE_DOUT_RST(1),
+    .C_USE_ECC(0),
+    .C_USE_ECC_AXIS(0),
+    .C_USE_ECC_RACH(0),
+    .C_USE_ECC_RDCH(0),
+    .C_USE_ECC_WACH(0),
+    .C_USE_ECC_WDCH(0),
+    .C_USE_ECC_WRCH(0),
+    .C_USE_EMBEDDED_REG(0),
+    .C_USE_FIFO16_FLAGS(0),
+    .C_USE_FWFT_DATA_COUNT(0),
+    .C_VALID_LOW(0),
+    .C_WACH_TYPE(0),
+    .C_WDCH_TYPE(0),
+    .C_WR_ACK_LOW(0),
+    .C_WR_DATA_COUNT_WIDTH(5),
+    .C_WR_DEPTH(32),
+    .C_WR_DEPTH_AXIS(1024),
+    .C_WR_DEPTH_RACH(16),
+    .C_WR_DEPTH_RDCH(1024),
+    .C_WR_DEPTH_WACH(16),
+    .C_WR_DEPTH_WDCH(1024),
+    .C_WR_DEPTH_WRCH(16),
+    .C_WR_FREQ(1),
+    .C_WR_PNTR_WIDTH(5),
+    .C_WR_PNTR_WIDTH_AXIS(10),
+    .C_WR_PNTR_WIDTH_RACH(4),
+    .C_WR_PNTR_WIDTH_RDCH(10),
+    .C_WR_PNTR_WIDTH_WACH(4),
+    .C_WR_PNTR_WIDTH_WDCH(10),
+    .C_WR_PNTR_WIDTH_WRCH(4),
+    .C_WR_RESPONSE_LATENCY(1),
+    .C_WRCH_TYPE(0)
+  )
+  inst (
+    .RST(rst),
+    .WR_CLK(wr_clk),
+    .RD_CLK(rd_clk),
+    .DIN(din),
+    .WR_EN(wr_en),
+    .RD_EN(rd_en),
+    .DOUT(dout),
+    .FULL(full),
+    .EMPTY(empty),
+    .BACKUP(),
+    .BACKUP_MARKER(),
+    .CLK(),
+    .SRST(),
+    .WR_RST(),
+    .RD_RST(),
+    .PROG_EMPTY_THRESH(),
+    .PROG_EMPTY_THRESH_ASSERT(),
+    .PROG_EMPTY_THRESH_NEGATE(),
+    .PROG_FULL_THRESH(),
+    .PROG_FULL_THRESH_ASSERT(),
+    .PROG_FULL_THRESH_NEGATE(),
+    .INT_CLK(),
+    .INJECTDBITERR(),
+    .INJECTSBITERR(),
+    .ALMOST_FULL(),
+    .WR_ACK(),
+    .OVERFLOW(),
+    .ALMOST_EMPTY(),
+    .VALID(),
+    .UNDERFLOW(),
+    .DATA_COUNT(),
+    .RD_DATA_COUNT(),
+    .WR_DATA_COUNT(),
+    .PROG_FULL(),
+    .PROG_EMPTY(),
+    .SBITERR(),
+    .DBITERR(),
+    .M_ACLK(),
+    .S_ACLK(),
+    .S_ARESETN(),
+    .M_ACLK_EN(),
+    .S_ACLK_EN(),
+    .S_AXI_AWID(),
+    .S_AXI_AWADDR(),
+    .S_AXI_AWLEN(),
+    .S_AXI_AWSIZE(),
+    .S_AXI_AWBURST(),
+    .S_AXI_AWLOCK(),
+    .S_AXI_AWCACHE(),
+    .S_AXI_AWPROT(),
+    .S_AXI_AWQOS(),
+    .S_AXI_AWREGION(),
+    .S_AXI_AWUSER(),
+    .S_AXI_AWVALID(),
+    .S_AXI_AWREADY(),
+    .S_AXI_WID(),
+    .S_AXI_WDATA(),
+    .S_AXI_WSTRB(),
+    .S_AXI_WLAST(),
+    .S_AXI_WUSER(),
+    .S_AXI_WVALID(),
+    .S_AXI_WREADY(),
+    .S_AXI_BID(),
+    .S_AXI_BRESP(),
+    .S_AXI_BUSER(),
+    .S_AXI_BVALID(),
+    .S_AXI_BREADY(),
+    .M_AXI_AWID(),
+    .M_AXI_AWADDR(),
+    .M_AXI_AWLEN(),
+    .M_AXI_AWSIZE(),
+    .M_AXI_AWBURST(),
+    .M_AXI_AWLOCK(),
+    .M_AXI_AWCACHE(),
+    .M_AXI_AWPROT(),
+    .M_AXI_AWQOS(),
+    .M_AXI_AWREGION(),
+    .M_AXI_AWUSER(),
+    .M_AXI_AWVALID(),
+    .M_AXI_AWREADY(),
+    .M_AXI_WID(),
+    .M_AXI_WDATA(),
+    .M_AXI_WSTRB(),
+    .M_AXI_WLAST(),
+    .M_AXI_WUSER(),
+    .M_AXI_WVALID(),
+    .M_AXI_WREADY(),
+    .M_AXI_BID(),
+    .M_AXI_BRESP(),
+    .M_AXI_BUSER(),
+    .M_AXI_BVALID(),
+    .M_AXI_BREADY(),
+    .S_AXI_ARID(),
+    .S_AXI_ARADDR(),
+    .S_AXI_ARLEN(),
+    .S_AXI_ARSIZE(),
+    .S_AXI_ARBURST(),
+    .S_AXI_ARLOCK(),
+    .S_AXI_ARCACHE(),
+    .S_AXI_ARPROT(),
+    .S_AXI_ARQOS(),
+    .S_AXI_ARREGION(),
+    .S_AXI_ARUSER(),
+    .S_AXI_ARVALID(),
+    .S_AXI_ARREADY(),
+    .S_AXI_RID(),
+    .S_AXI_RDATA(),
+    .S_AXI_RRESP(),
+    .S_AXI_RLAST(),
+    .S_AXI_RUSER(),
+    .S_AXI_RVALID(),
+    .S_AXI_RREADY(),
+    .M_AXI_ARID(),
+    .M_AXI_ARADDR(),
+    .M_AXI_ARLEN(),
+    .M_AXI_ARSIZE(),
+    .M_AXI_ARBURST(),
+    .M_AXI_ARLOCK(),
+    .M_AXI_ARCACHE(),
+    .M_AXI_ARPROT(),
+    .M_AXI_ARQOS(),
+    .M_AXI_ARREGION(),
+    .M_AXI_ARUSER(),
+    .M_AXI_ARVALID(),
+    .M_AXI_ARREADY(),
+    .M_AXI_RID(),
+    .M_AXI_RDATA(),
+    .M_AXI_RRESP(),
+    .M_AXI_RLAST(),
+    .M_AXI_RUSER(),
+    .M_AXI_RVALID(),
+    .M_AXI_RREADY(),
+    .S_AXIS_TVALID(),
+    .S_AXIS_TREADY(),
+    .S_AXIS_TDATA(),
+    .S_AXIS_TSTRB(),
+    .S_AXIS_TKEEP(),
+    .S_AXIS_TLAST(),
+    .S_AXIS_TID(),
+    .S_AXIS_TDEST(),
+    .S_AXIS_TUSER(),
+    .M_AXIS_TVALID(),
+    .M_AXIS_TREADY(),
+    .M_AXIS_TDATA(),
+    .M_AXIS_TSTRB(),
+    .M_AXIS_TKEEP(),
+    .M_AXIS_TLAST(),
+    .M_AXIS_TID(),
+    .M_AXIS_TDEST(),
+    .M_AXIS_TUSER(),
+    .AXI_AW_INJECTSBITERR(),
+    .AXI_AW_INJECTDBITERR(),
+    .AXI_AW_PROG_FULL_THRESH(),
+    .AXI_AW_PROG_EMPTY_THRESH(),
+    .AXI_AW_DATA_COUNT(),
+    .AXI_AW_WR_DATA_COUNT(),
+    .AXI_AW_RD_DATA_COUNT(),
+    .AXI_AW_SBITERR(),
+    .AXI_AW_DBITERR(),
+    .AXI_AW_OVERFLOW(),
+    .AXI_AW_UNDERFLOW(),
+    .AXI_AW_PROG_FULL(),
+    .AXI_AW_PROG_EMPTY(),
+    .AXI_W_INJECTSBITERR(),
+    .AXI_W_INJECTDBITERR(),
+    .AXI_W_PROG_FULL_THRESH(),
+    .AXI_W_PROG_EMPTY_THRESH(),
+    .AXI_W_DATA_COUNT(),
+    .AXI_W_WR_DATA_COUNT(),
+    .AXI_W_RD_DATA_COUNT(),
+    .AXI_W_SBITERR(),
+    .AXI_W_DBITERR(),
+    .AXI_W_OVERFLOW(),
+    .AXI_W_UNDERFLOW(),
+    .AXI_B_INJECTSBITERR(),
+    .AXI_W_PROG_FULL(),
+    .AXI_W_PROG_EMPTY(),
+    .AXI_B_INJECTDBITERR(),
+    .AXI_B_PROG_FULL_THRESH(),
+    .AXI_B_PROG_EMPTY_THRESH(),
+    .AXI_B_DATA_COUNT(),
+    .AXI_B_WR_DATA_COUNT(),
+    .AXI_B_RD_DATA_COUNT(),
+    .AXI_B_SBITERR(),
+    .AXI_B_DBITERR(),
+    .AXI_B_OVERFLOW(),
+    .AXI_B_UNDERFLOW(),
+    .AXI_AR_INJECTSBITERR(),
+    .AXI_B_PROG_FULL(),
+    .AXI_B_PROG_EMPTY(),
+    .AXI_AR_INJECTDBITERR(),
+    .AXI_AR_PROG_FULL_THRESH(),
+    .AXI_AR_PROG_EMPTY_THRESH(),
+    .AXI_AR_DATA_COUNT(),
+    .AXI_AR_WR_DATA_COUNT(),
+    .AXI_AR_RD_DATA_COUNT(),
+    .AXI_AR_SBITERR(),
+    .AXI_AR_DBITERR(),
+    .AXI_AR_OVERFLOW(),
+    .AXI_AR_UNDERFLOW(),
+    .AXI_AR_PROG_FULL(),
+    .AXI_AR_PROG_EMPTY(),
+    .AXI_R_INJECTSBITERR(),
+    .AXI_R_INJECTDBITERR(),
+    .AXI_R_PROG_FULL_THRESH(),
+    .AXI_R_PROG_EMPTY_THRESH(),
+    .AXI_R_DATA_COUNT(),
+    .AXI_R_WR_DATA_COUNT(),
+    .AXI_R_RD_DATA_COUNT(),
+    .AXI_R_SBITERR(),
+    .AXI_R_DBITERR(),
+    .AXI_R_OVERFLOW(),
+    .AXI_R_UNDERFLOW(),
+    .AXIS_INJECTSBITERR(),
+    .AXI_R_PROG_FULL(),
+    .AXI_R_PROG_EMPTY(),
+    .AXIS_INJECTDBITERR(),
+    .AXIS_PROG_FULL_THRESH(),
+    .AXIS_PROG_EMPTY_THRESH(),
+    .AXIS_DATA_COUNT(),
+    .AXIS_WR_DATA_COUNT(),
+    .AXIS_RD_DATA_COUNT(),
+    .AXIS_SBITERR(),
+    .AXIS_DBITERR(),
+    .AXIS_OVERFLOW(),
+    .AXIS_UNDERFLOW(),
+    .AXIS_PROG_FULL(),
+    .AXIS_PROG_EMPTY()
+  );
+
+// synthesis translate_on
+
+endmodule
+"
+"//**************************************************************************
+//    ph_reg3.v - 2 byte FIFO for 16b transfers in parasite to host direction
+//
+//    COPYRIGHT 2019 David Banks, Richard Evans, Ed Spittles
+//
+//    This file is part of tube - an Acorn Tube ULA compatible system.
+//
+//    tube is free software: you can redistribute it and/or modify
+//    it under the terms of the GNU Lesser General Public License as published by
+//    the Free Software Foundation, either version 3 of the License, or
+//    (at your option) any later version.
+//
+//    tube is distributed in the hope that it will be useful,
+//    but WITHOUT ANY WARRANTY; without even the implied warranty of
+//    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//    GNU Lesser General Public License for more details.
+//
+//    You should have received a copy of the GNU Lesser General Public License
+//    along with tube.  If not, see <http://www.gnu.org/licenses/>.
+//
+// ============================================================================
+`timescale 1ns / 1ns
+
+module bin_gray_counter #
+  (
+   parameter N = 0,     // Width of counters
+   parameter INIT = 0   // Initial value of binary counter
+   )
+   (
+    input              clk,
+    input              rst,
+    input              inc,
+    output reg [N-1:0] binary,
+    output reg [N-1:0] gray
+    );
+
+   wire [N-1:0]        next_binary = binary + 1'b1;
+   wire [N-1:0]        next_gray = next_binary ^ (next_binary >> 1);
+
+   always @(posedge clk or posedge rst) begin
+      if (rst) begin
+         binary <= INIT;
+         gray <= INIT ^ (INIT >> 1);
+      end else if (inc) begin
+         binary <= next_binary;
+         gray <= next_gray;
+      end
+   end
+
+endmodule
+
+module async_fifo #
+  (
+   parameter D_WIDTH = 0,    // FIFO data width
+   parameter A_WIDTH = 0,    // Log(2) of the FIFO depth
+   parameter INIT_WADDR = 0, // Inital write address
+   parameter INIT_RADDR = 0  // Initial read addrtess
+   )
+   (
+    input        rst,      // asynchrous reset
+    input        wr_clk,   // write clock
+    input        wr_en,    // write enable
+    input [7:0]  wr_data,  // write data
+    input        rd_clk,   // read clock
+    input        rd_en,    // read enable
+    output [7:0] rd_data,  // read data (value at the HEAD of the FIFO)
+    output       rd_empty, // empty flag, synchronised to the read domain
+    output       rd_full,  // full flag, synchronised to the read domain
+    output       wr_empty, // empty flag, synchronised to the write domain
+    output       wr_full   // full flag, synchronised to the write domain
+    );
+
+   // The read and write addresses are N+1 bits (where 2^N is the FIFO size)
+   // The purpose of the additional bit is to distingish the full/empty cases
+
+   // Write address
+   wire [A_WIDTH:0] waddr;     // binary encoded
+   wire [A_WIDTH:0] waddr_g;   // gray coded
+   reg [A_WIDTH:0]  waddr_g1;  // gray coded, part synchronised to read domain
+   reg [A_WIDTH:0]  waddr_g2;  // gray coded, fully synchronised to read domain
+
+   // Read address
+   wire [A_WIDTH:0] raddr;     // binary encoded
+   wire [A_WIDTH:0] raddr_g;   // gray coded
+   reg [A_WIDTH:0]  raddr_g1;  // gray coded, part synchronised to write domain
+   reg [A_WIDTH:0]  raddr_g2;  // gray coded, fully synchronised to write domain
+
+   // FIFO Data RAM
+   reg [D_WIDTH-1:0] data[0:2^A_WIDTH-1];
+
+   // Counter blocks for write address
+   // - binary-coded output used for RAM write address
+   // - gray-coded output used for flag logic
+   bin_gray_counter #
+     (
+      .N(A_WIDTH+1),
+      .INIT(INIT_WADDR)
+      )
+   waddr_counter
+     (
+      .clk(wr_clk),
+      .rst(rst),
+      .inc(wr_en && !wr_full),
+      .binary(waddr),
+      .gray(waddr_g)
+      );
+
+   // Counter blocks for read address
+   // - binary-coded output used for RAM read address
+   // - gray-coded output used for flag logic
+   bin_gray_counter #
+     (
+      .N(A_WIDTH+1),
+      .INIT(INIT_RADDR)
+      )
+   addr_counter
+     (
+      .clk(rd_clk),
+      .rst(rst),
+      .inc(rd_en && !rd_empty),
+      .binary(raddr),
+      .gray(raddr_g)
+      );
+
+   // Synchronise the gray-coded read address to the write clock domain
+   always @(posedge wr_clk) begin
+      raddr_g1 <= raddr_g;
+      raddr_g2 <= raddr_g1;
+   end
+
+   // Synchronise the gray-coded write address to the read clock domain
+   always @(posedge rd_clk) begin
+      waddr_g1 <= waddr_g;
+      waddr_g2 <= waddr_g1;
+   end
+
+   // Write logic
+   always @(posedge wr_clk) begin
+      if (wr_en && !wr_full) begin
+         data[waddr[A_WIDTH-1:0]] <= wr_data;
+      end
+   end
+
+   // Read logic
+   assign rd_data = data[raddr[A_WIDTH-1:0]];
+
+   // Full/Empty flags are generated from the gray coded addresses.
+   //
+   // The wr_ prefixed versions are valid in the write clock domain.
+   // The rd_ prefixed versions are valid in the read clock domain.
+   //
+   // The addresses contain one extra bit to distinguish the full and empty cases.
+   //
+   // If the pointers match exacty, then the FIFO is empty.
+   //
+   // If they match, apart from the MS two bits, then the FIFO is full. I've
+   // not seem this formulation used before. But by inspection it seems to be
+   // correct. Caveat Emptor!
+   assign wr_empty = (waddr_g ^ raddr_g2) == 0;
+   assign rd_empty = (raddr_g ^ waddr_g2) == 0;
+   assign wr_full  = (waddr_g ^ raddr_g2) == 3 << (A_WIDTH-1);
+   assign rd_full  = (raddr_g ^ waddr_g2) == 3 << (A_WIDTH-1);
+
+endmodule
+
+module ph_reg3
+  (
+   input        h_rst_b,
+   input        h_rd,
+   input        h_selectData,
+   input        h_phi2,
+
+   input [7:0]  p_data,
+   input        p_selectData,
+   input        p_phi2,
+   input        p_rdnw,
+   input        one_byte_mode,
+   output [7:0] h_data,
+   output       h_data_available,
+   output       p_empty,
+   output       p_full
+   );
+
+   // Internal flags
+   wire         rd_empty;    // empty flag, synchronised to the read domain
+   wire         rd_full;     // full flag, synchronised to the read domain
+   wire         wr_empty;    // empty flag, synchronised to the write domain
+   wire         wr_full;     // full flag, synchronised to the write domain
+
+   async_fifo #
+     (
+      .D_WIDTH(8),
+      .A_WIDTH(1),
+      .INIT_WADDR(1),
+      .INIT_RADDR(0)
+      )
+   ph_reg3_fifo
+     (
+      .rst(!h_rst_b),
+      .wr_clk(p_phi2),
+      .wr_en(p_selectData && !p_rdnw),
+      .wr_data(p_data),
+      .rd_clk(!h_phi2),
+      .rd_en(h_selectData && h_rd),
+      .rd_data(h_data),
+      .rd_empty(rd_empty),
+      .rd_full(rd_full),
+      .wr_empty(wr_empty),
+      .wr_full(wr_full)
+      );
+
+   // Register 3 is intended to enable high speed transfers of large blocks of data across the tube.
+   // It can operate in one or two byte mode, depending on the V flag. In one byte mode the status
+   // bits make each FIFO appear to be a single byte latch - after one byte is written the register
+   // appears to be full. In two byte mode the data available flag will only be asserted when two bytes have
+   // been entered, and the not full flag will only be asserted when both bytes have been removed. Thus data
+   // available going active means that two bytes are available, but it will remain active until both bytes
+   // have been removed. Not full going active means that the register is empty, but it will remain active
+   // until both bytes have been entered. PNMI, N and DRQ also remain active until the full two
+   // byte operation is completed
+
+   assign p_empty          = wr_empty;
+   assign p_full           = one_byte_mode ? wr_full   : !wr_empty;
+   assign h_data_available = one_byte_mode ? !rd_empty : rd_full;
+
+endmodule
+"
+"/*
+ *  Copyright (c) 2008  Zeus Gomez Marmolejo <zeus@opencores.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+`timescale 1ns/10ps
+
+module zet_jmp_cond (
+    input [4:0]  logic_flags,
+    input [3:0]  cond,
+    input        is_cx,
+    input [15:0] cx,
+    output reg   jmp
+  );
+
+  // Net declarations
+  wire of, sf, zf, pf, cf;
+  wire cx_zero;
+
+  // Assignments
+  assign of = logic_flags[4];
+  assign sf = logic_flags[3];
+  assign zf = logic_flags[2];
+  assign pf = logic_flags[1];
+  assign cf = logic_flags[0];
+  assign cx_zero = ~(|cx);
+
+  // Behaviour
+  always @(cond or is_cx or cx_zero or zf or of or cf or sf or pf)
+    if (is_cx) case (cond)
+        4'b0000: jmp <= cx_zero;         /* jcxz   */
+        4'b0001: jmp <= ~cx_zero;        /* loop   */
+        4'b0010: jmp <= zf & ~cx_zero;   /* loopz  */
+        default: jmp <= ~zf & ~cx_zero; /* loopnz */
+      endcase
+    else case (cond)
+      4'b0000: jmp <= of;
+      4'b0001: jmp <= ~of;
+      4'b0010: jmp <= cf;
+      4'b0011: jmp <= ~cf;
+      4'b0100: jmp <= zf;
+      4'b0101: jmp <= ~zf;
+      4'b0110: jmp <= cf | zf;
+      4'b0111: jmp <= ~cf & ~zf;
+
+      4'b1000: jmp <= sf;
+      4'b1001: jmp <= ~sf;
+      4'b1010: jmp <= pf;
+      4'b1011: jmp <= ~pf;
+      4'b1100: jmp <= (sf ^ of);
+      4'b1101: jmp <= (sf ^~ of);
+      4'b1110: jmp <= zf | (sf ^ of);
+      4'b1111: jmp <= ~zf & (sf ^~ of);
+    endcase
+endmodule
+"
+"//////////////////////////////////////////////////////////////////
+//                                                              //
+// Decompiler for Amber 2 Core                                  //
+//                                                              //
+//  This file is part of the Amber project                      //
+//  http://www.opencores.org/project,amber                      //
+//                                                              //
+//  Description                                                 //
+//  Decompiler for debugging core - not synthesizable           //
+//  Shows instruction in Execute Stage at last clock of         //
+//  the instruction                                             //
+//                                                              //
+//  Author(s):                                                  //
+//      - Conor Santifort, csantifort.amber@gmail.com           //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+//                                                              //
+// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
+//                                                              //
+// This source file may be used and distributed without         //
+// restriction provided that this copyright statement is not    //
+// removed from the file and that any derivative work contains  //
+// the original copyright notice and the associated disclaimer. //
+//                                                              //
+// This source file is free software; you can redistribute it   //
+// and/or modify it under the terms of the GNU Lesser General   //
+// Public License as published by the Free Software Foundation; //
+// either version 2.1 of the License, or (at your option) any   //
+// later version.                                               //
+//                                                              //
+// This source is distributed in the hope that it will be       //
+// useful, but WITHOUT ANY WARRANTY; without even the implied   //
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
+// PURPOSE.  See the GNU Lesser General Public License for more //
+// details.                                                     //
+//                                                              //
+// You should have received a copy of the GNU Lesser General    //
+// Public License along with this source; if not, download it   //
+// from http://www.opencores.org/lgpl.shtml                     //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+
+`include ""global_timescale.vh""
+`include ""global_defines.vh""
+`include ""a23_config_defines.vh""
+
+module a23_decompile
+(
+input                       i_clk,
+input                       i_fetch_stall,
+input       [31:0]          i_instruction,
+input                       i_instruction_valid,
+input                       i_instruction_undefined,
+input                       i_instruction_execute,
+input       [2:0]           i_interrupt,            // non-zero value means interrupt triggered
+input                       i_interrupt_state,
+input       [31:0]          i_instruction_address,
+input       [1:0]           i_pc_sel,
+input                       i_pc_wen
+
+);
+
+`include ""a23_localparams.vh""
+        
+`ifdef A23_DECOMPILE
+
+integer i;
+
+wire    [31:0]         imm32;
+wire    [7:0]          imm8;
+wire    [11:0]         offset12;
+wire    [7:0]          offset8;
+wire    [3:0]          reg_n, reg_d, reg_m, reg_s;
+wire    [4:0]          shift_imm;
+wire    [3:0]          opcode;
+wire    [3:0]          condition;
+wire    [3:0]          itype;
+wire                   opcode_compare;
+wire                   opcode_move;
+wire                   no_shift;
+wire                   shift_op_imm;
+wire    [1:0]          mtrans_itype;
+wire                   s_bit;
+
+reg     [(5*8)-1:0]    xINSTRUCTION_EXECUTE;
+reg     [(5*8)-1:0]    xINSTRUCTION_EXECUTE_R = ""---   "";
+wire    [(8*8)-1:0]    TYPE_NAME;
+reg     [3:0]          fchars;
+reg     [31:0]         execute_address = \'d0;
+reg     [2:0]          interrupt_d1;
+reg     [31:0]         execute_instruction = \'d0;
+reg                    execute_now = \'d0;
+reg                    execute_valid = \'d0;
+reg                    execute_undefined = \'d0;
+
+
+// ========================================================
+// Delay instruction to Execute stage
+// ========================================================
+always @( posedge i_clk )
+    if ( !i_fetch_stall && i_instruction_valid )
+        begin
+        execute_instruction <= i_instruction;
+        execute_address     <= i_instruction_address;
+        execute_undefined   <= i_instruction_undefined;
+        execute_now         <= 1\'d1;
+        end
+    else
+        execute_now         <= 1\'d0;
+
+
+always @ ( posedge i_clk )
+    if ( !i_fetch_stall )
+        execute_valid <= i_instruction_valid;
+    
+// ========================================================
+// Open File
+// ========================================================
+integer decompile_file;
+
+initial 
+    #1 decompile_file = $fopen(`A23_DECOMPILE_FILE, ""w"");
+
+
+// ========================================================
+// Fields within the instruction
+// ========================================================
+assign opcode      = execute_instruction[24:21];
+assign condition   = execute_instruction[31:28];
+assign s_bit       = execute_instruction[20];
+assign reg_n       = execute_instruction[19:16];
+assign reg_d       = execute_instruction[15:12];
+assign reg_m       = execute_instruction[3:0];
+assign reg_s       = execute_instruction[11:8];
+assign shift_imm   = execute_instruction[11:7];
+assign offset12    = execute_instruction[11:0];
+assign offset8     = {execute_instruction[11:8], execute_instruction[3:0]};
+assign imm8        = execute_instruction[7:0];
+
+assign no_shift    = execute_instruction[11:4] == 8\'h0;
+assign mtrans_itype = execute_instruction[24:23];
+
+
+assign opcode_compare =
+            opcode == CMP || 
+            opcode == CMN || 
+            opcode == TEQ || 
+            opcode == TST ;
+            
+assign opcode_move =
+            opcode == MOV || 
+            opcode == MVN ;
+            
+assign shift_op_imm = itype == REGOP && execute_instruction[25] == 1\'d1;
+
+assign imm32 =  execute_instruction[11:8] == 4\'h0 ? {            24\'h0, imm8[7:0] } :
+                execute_instruction[11:8] == 4\'h1 ? { imm8[1:0], 24\'h0, imm8[7:2] } :
+                execute_instruction[11:8] == 4\'h2 ? { imm8[3:0], 24\'h0, imm8[7:4] } :
+                execute_instruction[11:8] == 4\'h3 ? { imm8[5:0], 24\'h0, imm8[7:6] } :
+                execute_instruction[11:8] == 4\'h4 ? { imm8[7:0], 24\'h0            } :
+                execute_instruction[11:8] == 4\'h5 ? { 2\'h0,  imm8[7:0], 22\'h0 }     :
+                execute_instruction[11:8] == 4\'h6 ? { 4\'h0,  imm8[7:0], 20\'h0 }     :
+                execute_instruction[11:8] == 4\'h7 ? { 6\'h0,  imm8[7:0], 18\'h0 }     :
+                execute_instruction[11:8] == 4\'h8 ? { 8\'h0,  imm8[7:0], 16\'h0 }     :
+                execute_instruction[11:8] == 4\'h9 ? { 10\'h0, imm8[7:0], 14\'h0 }     :
+                execute_instruction[11:8] == 4\'ha ? { 12\'h0, imm8[7:0], 12\'h0 }     :
+                execute_instruction[11:8] == 4\'hb ? { 14\'h0, imm8[7:0], 10\'h0 }     :
+                execute_instruction[11:8] == 4\'hc ? { 16\'h0, imm8[7:0], 8\'h0  }     :
+                execute_instruction[11:8] == 4\'hd ? { 18\'h0, imm8[7:0], 6\'h0  }     :
+                execute_instruction[11:8] == 4\'he ? { 20\'h0, imm8[7:0], 4\'h0  }     :
+                                                    { 22\'h0, imm8[7:0], 2\'h0  }     ;
+
+
+// ========================================================
+// Instruction decode
+// ========================================================
+// the order of these matters
+assign itype = 
+    {execute_instruction[27:23], execute_instruction[21:20], execute_instruction[11:4] } == { 5\'b00010, 2\'b00, 8\'b00001001 } ? SWAP     :  // Before REGOP
+    {execute_instruction[27:22], execute_instruction[7:4]                              } == { 6\'b000000, 4\'b1001           } ? MULT     :  // Before REGOP
+    {execute_instruction[27:26]                                                        } == { 2\'b00                        } ? REGOP    :    
+    {execute_instruction[27:26]                                                        } == { 2\'b01                        } ? TRANS    :
+    {execute_instruction[27:25]                                                        } == { 3\'b100                       } ? MTRANS   :
+    {execute_instruction[27:25]                                                        } == { 3\'b101                       } ? BRANCH   :
+    {execute_instruction[27:25]                                                        } == { 3\'b110                       } ? CODTRANS :
+    {execute_instruction[27:24], execute_instruction[4]                                } == { 4\'b1110, 1\'b0                } ? COREGOP  :
+    {execute_instruction[27:24], execute_instruction[4]                                } == { 4\'b1110, 1\'b1                } ? CORTRANS :
+                                                                                                                               SWI      ;
+
+                                                                                                                 
+//
+// Convert some important signals to ASCII
+// so their values can easily be displayed on a waveform viewer
+//
+assign TYPE_NAME    = itype == REGOP    ? ""REGOP   "" :
+                      itype == MULT     ? ""MULT    "" :
+                      itype == SWAP     ? ""SWAP    "" :
+                      itype == TRANS    ? ""TRANS   "" : 
+                      itype == MTRANS   ? ""MTRANS  "" : 
+                      itype == BRANCH   ? ""BRANCH  "" : 
+                      itype == CODTRANS ? ""CODTRANS"" : 
+                      itype == COREGOP  ? ""COREGOP "" : 
+                      itype == CORTRANS ? ""CORTRANS"" : 
+                      itype == SWI      ? ""SWI     "" : 
+                                         ""UNKNOWN "" ;
+                                           
+
+always @*
+    begin
+    
+    if ( !execute_now ) 
+        begin 
+        xINSTRUCTION_EXECUTE =  xINSTRUCTION_EXECUTE_R; 
+        end // stalled
+
+    else if ( itype == REGOP    && opcode == ADC                                                          ) xINSTRUCTION_EXECUTE = ""adc  "";
+    else if ( itype == REGOP    && opcode == ADD                                                          ) xINSTRUCTION_EXECUTE = ""add  "";
+    else if ( itype == REGOP    && opcode == AND                                                          ) xINSTRUCTION_EXECUTE = ""and  "";
+    else if ( itype == BRANCH   && execute_instruction[24] == 1\'b0                                        ) xINSTRUCTION_EXECUTE = ""b    "";
+    else if ( itype == REGOP    && opcode == BIC                                                          ) xINSTRUCTION_EXECUTE = ""bic  "";
+    else if ( itype == BRANCH   && execute_instruction[24] == 1\'b1                                        ) xINSTRUCTION_EXECUTE = ""bl   "";
+    else if ( itype == COREGOP                                                                            ) xINSTRUCTION_EXECUTE = ""cdp  "";
+    else if ( itype == REGOP    && opcode == CMN                                                          ) xINSTRUCTION_EXECUTE = ""cmn  "";
+    else if ( itype == REGOP    && opcode == CMP                                                          ) xINSTRUCTION_EXECUTE = ""cmp  "";
+    else if ( itype == REGOP    && opcode == EOR                                                          ) xINSTRUCTION_EXECUTE = ""eor  "";
+    else if ( itype == CODTRANS && execute_instruction[20] == 1\'b1                                        ) xINSTRUCTION_EXECUTE = ""ldc  "";
+    else if ( itype == MTRANS   && execute_instruction[20] == 1\'b1                                        ) xINSTRUCTION_EXECUTE = ""ldm  "";
+    else if ( itype == TRANS    && {execute_instruction[22],execute_instruction[20]}    == {1\'b0, 1\'b1}   ) xINSTRUCTION_EXECUTE = ""ldr  "";
+    else if ( itype == TRANS    && {execute_instruction[22],execute_instruction[20]}    == {1\'b1, 1\'b1}   ) xINSTRUCTION_EXECUTE = ""ldrb "";
+    else if ( itype == CORTRANS && execute_instruction[20] == 1\'b0                                        ) xINSTRUCTION_EXECUTE = ""mcr  "";
+    else if ( itype == MULT     && execute_instruction[21] == 1\'b1                                        ) xINSTRUCTION_EXECUTE = ""mla  "";
+    else if ( itype == REGOP    && opcode == MOV                                                          ) xINSTRUCTION_EXECUTE = ""mov  "";
+    else if ( itype == CORTRANS && execute_instruction[20] == 1\'b1                                        ) xINSTRUCTION_EXECUTE = ""mrc  "";
+    else if ( itype == MULT     && execute_instruction[21] == 1\'b0                                        ) xINSTRUCTION_EXECUTE = ""mul  "";
+    else if ( itype == REGOP    && opcode == MVN                                                          ) xINSTRUCTION_EXECUTE = ""mvn  "";
+    else if ( itype == REGOP    && opcode == ORR                                                          ) xINSTRUCTION_EXECUTE = ""orr  "";
+    else if ( itype == REGOP    && opcode == RSB                                                          ) xINSTRUCTION_EXECUTE = ""rsb  "";
+    else if ( itype == REGOP    && opcode == RSC                                                          ) xINSTRUCTION_EXECUTE = ""rsc  "";
+    else if ( itype == REGOP    && opcode == SBC                                                          ) xINSTRUCTION_EXECUTE = ""sbc  "";
+    else if ( itype == CODTRANS && execute_instruction[20] == 1\'b0                                        ) xINSTRUCTION_EXECUTE = ""stc  "";
+    else if ( itype == MTRANS   && execute_instruction[20] == 1\'b0                                        ) xINSTRUCTION_EXECUTE = ""stm  "";
+    else if ( itype == TRANS    && {execute_instruction[22],execute_instruction[20]}    == {1\'b0, 1\'b0}   ) xINSTRUCTION_EXECUTE = ""str  "";
+    else if ( itype == TRANS    && {execute_instruction[22],execute_instruction[20]}    == {1\'b1, 1\'b0}   ) xINSTRUCTION_EXECUTE = ""strb "";
+    else if ( itype == REGOP    && opcode == SUB                                                          ) xINSTRUCTION_EXECUTE = ""sub  "";  
+    else if ( itype == SWI                                                                                ) xINSTRUCTION_EXECUTE = ""swi  "";  
+    else if ( itype == SWAP     && execute_instruction[22] == 1\'b0                                        ) xINSTRUCTION_EXECUTE = ""swp  "";  
+    else if ( itype == SWAP     && execute_instruction[22] == 1\'b1                                        ) xINSTRUCTION_EXECUTE = ""swpb "";  
+    else if ( itype == REGOP    && opcode == TEQ                                                          ) xINSTRUCTION_EXECUTE = ""teq  "";  
+    else if ( itype == REGOP    && opcode == TST                                                          ) xINSTRUCTION_EXECUTE = ""tst  "";  
+    else                                                                                                   xINSTRUCTION_EXECUTE = ""unkow"";  
+    end
+
+always @ ( posedge i_clk )
+    xINSTRUCTION_EXECUTE_R <= xINSTRUCTION_EXECUTE;
+
+always @( posedge i_clk )
+    if ( execute_now )
+        begin
+        
+            // Interrupts override instructions that are just starting
+        if ( interrupt_d1 == 3\'d0 || interrupt_d1 == 3\'d7 )
+            begin
+            $fwrite(decompile_file,""%09d  "", `U_TB.clk_count);
+            
+            // Right justify the address
+            if      ( execute_address < 32\'h10)        $fwrite(decompile_file,""       %01x:  "", {execute_address[ 3:1], 1\'d0});
+            else if ( execute_address < 32\'h100)       $fwrite(decompile_file,""      %02x:  "",  {execute_address[ 7:1], 1\'d0}); 
+            else if ( execute_address < 32\'h1000)      $fwrite(decompile_file,""     %03x:  "",   {execute_address[11:1], 1\'d0}); 
+            else if ( execute_address < 32\'h10000)     $fwrite(decompile_file,""    %04x:  "",    {execute_address[15:1], 1\'d0});
+            else if ( execute_address < 32\'h100000)    $fwrite(decompile_file,""   %05x:  "",     {execute_address[19:1], 1\'d0});
+            else if ( execute_address < 32\'h1000000)   $fwrite(decompile_file,""  %06x:  "",      {execute_address[23:1], 1\'d0});
+            else if ( execute_address < 32\'h10000000)  $fwrite(decompile_file,"" %07x:  "",       {execute_address[27:1], 1\'d0});
+            else                                       $fwrite(decompile_file,""%8x:  "",         {execute_address[31:1], 1\'d0});
+            
+            // Mark that the instruction is not being executed 
+            // condition field in execute stage allows instruction to execute ?
+            if (!i_instruction_execute)
+                begin
+                $fwrite(decompile_file,""-"");
+                if ( itype == SWI )
+                    $display (""Cycle %09d  SWI not taken *************"", `U_TB.clk_count);
+                end
+            else     
+                $fwrite(decompile_file,"" "");
+                
+            // ========================================
+            // print the instruction name
+            // ========================================
+            case (numchars( xINSTRUCTION_EXECUTE ))
+                4\'d1: $fwrite(decompile_file,""%s"", xINSTRUCTION_EXECUTE[39:32] );
+                4\'d2: $fwrite(decompile_file,""%s"", xINSTRUCTION_EXECUTE[39:24] );
+                4\'d3: $fwrite(decompile_file,""%s"", xINSTRUCTION_EXECUTE[39:16] );
+                4\'d4: $fwrite(decompile_file,""%s"", xINSTRUCTION_EXECUTE[39: 8] );
+            default:  $fwrite(decompile_file,""%s"", xINSTRUCTION_EXECUTE[39: 0] );
+            endcase
+
+            fchars = 8 - numchars(xINSTRUCTION_EXECUTE);
+        
+            // Print the Multiple transfer itype
+            if (itype   == MTRANS )
+                begin
+                w_mtrans_type;           
+                fchars = fchars - 2;
+                end
+
+            // Print the s bit
+           if ( ((itype == REGOP && !opcode_compare) || itype == MULT ) && s_bit == 1\'b1 )
+                begin
+                $fwrite(decompile_file,""s"");
+                fchars = fchars - 1;
+                end
+
+            // Print the p bit
+           if ( itype == REGOP && opcode_compare && s_bit == 1\'b1 && reg_d == 4\'d15 )
+                begin
+                $fwrite(decompile_file,""p"");
+                fchars = fchars - 1;
+                end
+
+            // Print the condition code
+            if ( condition != AL )
+                begin
+                wcond;
+                fchars = fchars - 2;
+                end
+                            
+            // Align spaces after instruction    
+            case ( fchars )
+                4\'d0: $fwrite(decompile_file,"""");
+                4\'d1: $fwrite(decompile_file,"" "");
+                4\'d2: $fwrite(decompile_file,""  "");
+                4\'d3: $fwrite(decompile_file,""   "");
+                4\'d4: $fwrite(decompile_file,""    "");
+                4\'d5: $fwrite(decompile_file,""     "");
+                4\'d6: $fwrite(decompile_file,""      "");
+                4\'d7: $fwrite(decompile_file,""       "");
+                4\'d8: $fwrite(decompile_file,""        "");
+            default:  $fwrite(decompile_file,""         "");
+            endcase
+        
+            // ========================================
+            // print the arguments for the instruction
+            // ========================================
+            case ( itype )
+                REGOP:     regop_args;
+                TRANS:     trans_args;
+                MTRANS:    mtrans_args;
+                BRANCH:    branch_args;
+                MULT:      mult_args;
+                SWAP:      swap_args;
+                CODTRANS:  codtrans_args; 
+                COREGOP:   begin 
+                           // `TB_ERROR_MESSAGE
+                           $write(""Coregop not implemented in decompiler yet\
+""); 
+                           end
+                CORTRANS:  cortrans_args; 
+                SWI:       $fwrite(decompile_file,""#0x%06h"", execute_instruction[23:0]);
+                default: begin
+                         `TB_ERROR_MESSAGE
+                         $write(""Unknown Instruction Type ERROR\
+"");
+                         end                     
+            endcase
+            
+            $fwrite( decompile_file,""\
+"" );
+            end
+
+        // Undefined Instruction Interrupts    
+        if ( i_instruction_execute && execute_undefined )
+            begin
+            $fwrite( decompile_file,""%09d              interrupt undefined instruction"", `U_TB.clk_count );
+            $fwrite( decompile_file,"", return addr "" );
+            $fwrite( decompile_file,""%08x\
+"",  pcf(get_reg_val(5\'d21)-4\'d4) );
+            end
+            
+        // Software Interrupt  
+        if ( i_instruction_execute && itype == SWI )    
+            begin
+            $fwrite( decompile_file,""%09d              interrupt swi"", `U_TB.clk_count );
+            $fwrite( decompile_file,"", return addr "" );
+            $fwrite( decompile_file,""%08x\
+"",  pcf(get_reg_val(5\'d21)-4\'d4) );
+            end
+        end
+
+
+always @( posedge i_clk )
+    if ( !i_fetch_stall )
+        begin
+        interrupt_d1 <= i_interrupt;
+        
+        // Asynchronous Interrupts    
+        if ( interrupt_d1 != 3\'d0 && i_interrupt_state )
+            begin
+            $fwrite( decompile_file,""%09d              interrupt "", `U_TB.clk_count );
+            case ( interrupt_d1 )
+                3\'d1:    $fwrite( decompile_file,""data abort"" );
+                3\'d2:    $fwrite( decompile_file,""firq"" );
+                3\'d3:    $fwrite( decompile_file,""irq"" );
+                3\'d4:    $fwrite( decompile_file,""address exception"" );
+                3\'d5:    $fwrite( decompile_file,""instruction abort"" );
+                default: $fwrite( decompile_file,""unknown itype"" );
+            endcase
+            $fwrite( decompile_file,"", return addr "" );
+            
+            case ( interrupt_d1 )
+                3\'d1:    $fwrite(decompile_file,""%08h\
+"",  pcf(get_reg_val(5\'d16)));
+                3\'d2:    $fwrite(decompile_file,""%08h\
+"",  pcf(get_reg_val(5\'d17)));
+                3\'d3:    $fwrite(decompile_file,""%08h\
+"",  pcf(get_reg_val(5\'d18)));
+                3\'d4:    $fwrite(decompile_file,""%08h\
+"",  pcf(get_reg_val(5\'d19)));
+                3\'d5:    $fwrite(decompile_file,""%08h\
+"",  pcf(get_reg_val(5\'d19)));
+                3\'d7:    $fwrite(decompile_file,""%08h\
+"",  pcf(get_reg_val(5\'d20)));
+                default: ;
+            endcase
+            end
+        end
+
+
+// jump
+// Dont print a jump message for interrupts
+always @( posedge i_clk )
+        if ( 
+             i_pc_sel != 2\'d0 && 
+             i_pc_wen &&
+             !i_fetch_stall && 
+             i_instruction_execute && 
+             i_interrupt == 3\'d0 &&
+             !execute_undefined &&
+             itype != SWI &&
+             execute_address != get_32bit_signal(0)  // Don\'t print jump to same address
+             )
+            begin
+            $fwrite(decompile_file,""%09d              jump    from "", `U_TB.clk_count);
+            fwrite_hex_drop_zeros(decompile_file,  pcf(execute_address));
+            $fwrite(decompile_file,"" to "");
+            fwrite_hex_drop_zeros(decompile_file,  pcf(get_32bit_signal(0)) ); // u_execute.pc_nxt
+            $fwrite(decompile_file,"", r0 %08h, "",  get_reg_val ( 5\'d0 ));
+            $fwrite(decompile_file,""r1 %08h\
+"",    get_reg_val ( 5\'d1 ));
+            end
+
+// =================================================================================
+// Memory Writes - Peek into fetch module
+// =================================================================================
+
+reg [31:0] tmp_address;
+
+    // Data access
+always @( posedge i_clk )
+    // Data Write    
+    if ( get_1bit_signal(0) && !get_1bit_signal(1) )
+        begin
+        
+        $fwrite(decompile_file, ""%09d              write   addr "", `U_TB.clk_count);
+        tmp_address = get_32bit_signal(2);
+        fwrite_hex_drop_zeros(decompile_file, {tmp_address [31:2], 2\'d0} );
+                  
+        $fwrite(decompile_file, "", data %08h, be %h"", 
+                get_32bit_signal(3),    // u_cache.i_write_data
+                get_4bit_signal (0));   // u_cache.i_byte_enable
+                                       
+        if ( get_1bit_signal(2) ) // Abort! address translation failed
+            $fwrite(decompile_file, "" aborted!\
+"");
+        else                                 
+            $fwrite(decompile_file, ""\
+"");
+        end
+    
+    // Data Read    
+    else if (get_1bit_signal(3) && !get_1bit_signal(0)  && !get_1bit_signal(1))     
+        begin
+        
+        $fwrite(decompile_file, ""%09d              read    addr "", `U_TB.clk_count);
+        tmp_address = get_32bit_signal(2);
+        fwrite_hex_drop_zeros(decompile_file, {tmp_address[31:2], 2\'d0} );    
+                     
+        $fwrite(decompile_file, "", data %08h"", get_32bit_signal(4));  // u_decode.i_read_data
+                                      
+        if ( get_1bit_signal(2) ) // Abort! address translation failed
+            $fwrite(decompile_file, "" aborted!\
+"");
+        else                                 
+            $fwrite(decompile_file, ""\
+"");
+        end
+
+
+// =================================================================================
+// Tasks
+// =================================================================================
+
+// Write Condition field
+task wcond;
+    begin
+    case( condition)
+        4\'h0:    $fwrite(decompile_file,""eq"");
+        4\'h1:    $fwrite(decompile_file,""ne"");
+        4\'h2:    $fwrite(decompile_file,""cs"");
+        4\'h3:    $fwrite(decompile_file,""cc"");
+        4\'h4:    $fwrite(decompile_file,""mi"");
+        4\'h5:    $fwrite(decompile_file,""pl"");
+        4\'h6:    $fwrite(decompile_file,""vs"");
+        4\'h7:    $fwrite(decompile_file,""vc"");
+        4\'h8:    $fwrite(decompile_file,""hi"");
+        4\'h9:    $fwrite(decompile_file,""ls""); 
+        4\'ha:    $fwrite(decompile_file,""ge""); 
+        4\'hb:    $fwrite(decompile_file,""lt"");
+        4\'hc:    $fwrite(decompile_file,""gt"");
+        4\'hd:    $fwrite(decompile_file,""le""); 
+        4\'he:    $fwrite(decompile_file,""  "");  // Always
+        default: $fwrite(decompile_file,""nv"");  // Never
+    endcase    
+    end
+endtask
+
+// ldm and stm types
+task w_mtrans_type;
+    begin
+    case( mtrans_itype )
+        4\'h0:    $fwrite(decompile_file,""da"");
+        4\'h1:    $fwrite(decompile_file,""ia"");
+        4\'h2:    $fwrite(decompile_file,""db"");
+        4\'h3:    $fwrite(decompile_file,""ib"");
+        default: $fwrite(decompile_file,""xx"");
+    endcase    
+    end
+endtask
+
+// e.g. mrc\t15, 0, r9, cr0, cr0, {0}
+task cortrans_args;
+    begin
+    // Co-Processor Number
+    $fwrite(decompile_file,""%1d, "", execute_instruction[11:8]);
+    // opcode1
+    $fwrite(decompile_file,""%1d, "", execute_instruction[23:21]);
+    // Rd [15:12]
+    warmreg(reg_d); 
+    // CRn [19:16]
+    $fwrite(decompile_file,"", cr%1d"", execute_instruction[19:16]);
+    // CRm [3:0]
+    $fwrite(decompile_file,"", cr%1d"", execute_instruction[3:0]);
+    // Opcode2 [7:5]
+    $fwrite(decompile_file,"", {%1d}"",   execute_instruction[7:5]);
+    end
+endtask
+
+
+// ldc\t15, 0, r9, cr0, cr0, {0}
+task codtrans_args;
+    begin
+    // Co-Processor Number
+    $fwrite(decompile_file,""%1d, "", execute_instruction[11:8]);
+    // CRd [15:12]
+    $fwrite(decompile_file,""cr%1d, "", execute_instruction[15:12]);
+    // Rd [19:16]
+    warmreg(reg_n); 
+    end
+endtask
+
+
+task branch_args;
+reg [31:0] shift_amount;
+    begin
+    if (execute_instruction[23]) // negative
+        shift_amount = {~execute_instruction[23:0] + 24\'d1, 2\'d0};
+    else
+        shift_amount = {execute_instruction[23:0], 2\'d0};
+
+    if (execute_instruction[23]) // negative
+        fwrite_hex_drop_zeros ( decompile_file, get_reg_val( 5\'d21 ) - shift_amount );
+    else             
+        fwrite_hex_drop_zeros ( decompile_file, get_reg_val( 5\'d21 ) + shift_amount );
+    end
+endtask
+
+
+task mult_args;
+    begin
+    warmreg(reg_n);  // Rd is in the Rn position for MULT instructions
+    $fwrite(decompile_file,"", "");
+    warmreg(reg_m);
+    $fwrite(decompile_file,"", "");
+    warmreg(reg_s); 
+
+    if (execute_instruction[21]) // MLA
+        begin
+        $fwrite(decompile_file,"", "");
+        warmreg(reg_d); 
+        end
+    end
+endtask
+
+
+task swap_args;
+    begin
+    warmreg(reg_d);
+    $fwrite(decompile_file,"", "");
+    warmreg(reg_m);
+    $fwrite(decompile_file,"", ["");
+    warmreg(reg_n); 
+    $fwrite(decompile_file,""]"");
+    end
+endtask
+
+
+task regop_args;
+    begin
+    if (!opcode_compare)
+        warmreg(reg_d);
+        
+    if (!opcode_move )
+        begin
+        if (!opcode_compare)
+            begin
+            $fwrite(decompile_file,"", "");
+            if (reg_d < 4\'d10 || reg_d > 4\'d12) 
+                $fwrite(decompile_file,"" "");
+            end
+        warmreg(reg_n);
+        $fwrite(decompile_file,"", "");
+        if (reg_n < 4\'d10 || reg_n > 4\'d12) 
+            $fwrite(decompile_file,"" "");
+        end
+    else
+        begin
+        $fwrite(decompile_file,"", "");
+        if (reg_d < 4\'d10 || reg_d > 4\'d12) 
+            $fwrite(decompile_file,"" "");
+        end    
+            
+    if (shift_op_imm)  
+        begin
+        if (|imm32[31:15])
+            $fwrite(decompile_file,""#0x%08h"", imm32);
+        else
+            $fwrite(decompile_file,""#%1d"", imm32);
+        end        
+    else // Rm
+        begin
+        warmreg(reg_m);
+        if (execute_instruction[4]) 
+            // Register Shifts
+            wshiftreg;
+        else 
+            // Immediate shifts
+            wshift;
+        end       
+    end
+endtask
+
+
+task trans_args;
+    begin
+    warmreg(reg_d);   // Destination register
+
+    casez ({execute_instruction[25:23], execute_instruction[21], no_shift, offset12==12\'d0})
+           6\'b0100?0 : begin $fwrite(decompile_file,"", [""); warmreg(reg_n); $fwrite(decompile_file,"", #-%1d]"" , offset12); end
+           6\'b0110?0 : begin $fwrite(decompile_file,"", [""); warmreg(reg_n); $fwrite(decompile_file,"", #%1d]""  , offset12); end
+           6\'b0100?1 : begin $fwrite(decompile_file,"", [""); warmreg(reg_n); $fwrite(decompile_file,""]""); end
+           6\'b0110?1 : begin $fwrite(decompile_file,"", [""); warmreg(reg_n); $fwrite(decompile_file,""]""); end
+           6\'b0101?? : begin $fwrite(decompile_file,"", [""); warmreg(reg_n); $fwrite(decompile_file,"", #-%1d]!"", offset12); end
+           6\'b0111?? : begin $fwrite(decompile_file,"", [""); warmreg(reg_n); $fwrite(decompile_file,"", #%1d]!"" , offset12); end
+
+           6\'b0000?0 : begin $fwrite(decompile_file,"", [""); warmreg(reg_n); $fwrite(decompile_file,""], #-%1d"", offset12); end
+           6\'b0010?0 : begin $fwrite(decompile_file,"", [""); warmreg(reg_n); $fwrite(decompile_file,""], #%1d"" , offset12); end
+           6\'b0001?0 : begin $fwrite(decompile_file,"", [""); warmreg(reg_n); $fwrite(decompile_file,""], #-%1d"", offset12); end
+           6\'b0011?0 : begin $fwrite(decompile_file,"", [""); warmreg(reg_n); $fwrite(decompile_file,""], #%1d"" , offset12); end
+     
+           6\'b0000?1 : begin $fwrite(decompile_file,"", [""); warmreg(reg_n); $fwrite(decompile_file,""]""); end
+           6\'b0010?1 : begin $fwrite(decompile_file,"", [""); warmreg(reg_n); $fwrite(decompile_file,""]""); end
+           6\'b0001?1 : begin $fwrite(decompile_file,"", [""); warmreg(reg_n); $fwrite(decompile_file,""]""); end
+           6\'b0011?1 : begin $fwrite(decompile_file,"", [""); warmreg(reg_n); $fwrite(decompile_file,""]""); end
+
+           6\'b11001? : begin $fwrite(decompile_file,"", [""); warmreg(reg_n); $fwrite(decompile_file,"", -"");  warmreg(reg_m); $fwrite(decompile_file,""]"");  end
+           6\'b11101? : begin $fwrite(decompile_file,"", [""); warmreg(reg_n); $fwrite(decompile_file,"", "");   warmreg(reg_m); $fwrite(decompile_file,""]"");  end
+           6\'b11011? : begin $fwrite(decompile_file,"", [""); warmreg(reg_n); $fwrite(decompile_file,"", -"");  warmreg(reg_m); $fwrite(decompile_file,""]!""); end
+           6\'b11111? : begin $fwrite(decompile_file,"", [""); warmreg(reg_n); $fwrite(decompile_file,"", "");   warmreg(reg_m); $fwrite(decompile_file,""]!""); end
+
+           6\'b10001? : begin $fwrite(decompile_file,"", [""); warmreg(reg_n); $fwrite(decompile_file,""], -""); warmreg(reg_m);  end
+           6\'b10101? : begin $fwrite(decompile_file,"", [""); warmreg(reg_n); $fwrite(decompile_file,""], "");  warmreg(reg_m);  end
+           6\'b10011? : begin $fwrite(decompile_file,"", [""); warmreg(reg_n); $fwrite(decompile_file,""], -""); warmreg(reg_m);  end
+           6\'b10111? : begin $fwrite(decompile_file,"", [""); warmreg(reg_n); $fwrite(decompile_file,""], "");  warmreg(reg_m);  end
+
+           6\'b11000? : begin $fwrite(decompile_file,"", [""); warmreg(reg_n); $fwrite(decompile_file,"", -"");  warmreg(reg_m); wshift; $fwrite(decompile_file,""]""); end
+           6\'b11100? : begin $fwrite(decompile_file,"", [""); warmreg(reg_n); $fwrite(decompile_file,"", "");   warmreg(reg_m); wshift; $fwrite(decompile_file,""]""); end
+           6\'b11010? : begin $fwrite(decompile_file,"", [""); warmreg(reg_n); $fwrite(decompile_file,"", -"");  warmreg(reg_m); wshift; $fwrite(decompile_file,""]!"");end
+           6\'b11110? : begin $fwrite(decompile_file,"", [""); warmreg(reg_n); $fwrite(decompile_file,"", "");   warmreg(reg_m); wshift; $fwrite(decompile_file,""]!"");end
+
+           6\'b10000? : begin $fwrite(decompile_file,"", [""); warmreg(reg_n); $fwrite(decompile_file,""], -""); warmreg(reg_m); wshift; end
+           6\'b10100? : begin $fwrite(decompile_file,"", [""); warmreg(reg_n); $fwrite(decompile_file,""], "");  warmreg(reg_m); wshift; end
+           6\'b10010? : begin $fwrite(decompile_file,"", [""); warmreg(reg_n); $fwrite(decompile_file,""], -""); warmreg(reg_m); wshift; end
+           6\'b10110? : begin $fwrite(decompile_file,"", [""); warmreg(reg_n); $fwrite(decompile_file,""], "");  warmreg(reg_m); wshift; end
+
+    endcase       
+    end
+endtask
+
+
+task mtrans_args;
+    begin
+    warmreg(reg_n);
+    if (execute_instruction[21]) $fwrite(decompile_file,""!"");
+    $fwrite(decompile_file,"", {"");
+    for (i=0;i<16;i=i+1)
+        if (execute_instruction[i])  
+            begin 
+            warmreg(i); 
+            if (more_to_come(execute_instruction[15:0], i))
+                $fwrite(decompile_file,"", ""); 
+            end
+    $fwrite(decompile_file,""}"");
+    // SDM: store the user mode registers, when in priviledged mode     
+    if (execute_instruction[22:20] == 3\'b100)  
+        $fwrite(decompile_file,""^"");
+    end
+endtask
+
+
+task wshift;
+    begin                                                                                                        
+    // Check that its a valid shift operation. LSL by #0 is the null operator                                    
+    if (execute_instruction[6:5] != LSL || shift_imm != 5\'d0)                                                    
+        begin                                                                                                    
+        case(execute_instruction[6:5])                                                                           
+            2\'d0: $fwrite(decompile_file,"", lsl"");                                                               
+            2\'d1: $fwrite(decompile_file,"", lsr"");                                                               
+            2\'d2: $fwrite(decompile_file,"", asr"");                                                               
+            2\'d3: if (shift_imm == 5\'d0) $fwrite(decompile_file,"", rrx""); else $fwrite(decompile_file,"", ror"");  
+        endcase                                                                                                  
+
+       if (execute_instruction[6:5] != 2\'d3 || shift_imm != 5\'d0)                                                
+           $fwrite(decompile_file,"" #%1d"", shift_imm);                                                           
+       end                                                                                                       
+    end                                                                                                          
+endtask
+
+
+task wshiftreg;
+    begin
+    case(execute_instruction[6:5])
+        2\'d0: $fwrite(decompile_file,"", lsl "");
+        2\'d1: $fwrite(decompile_file,"", lsr "");
+        2\'d2: $fwrite(decompile_file,"", asr "");
+        2\'d3: $fwrite(decompile_file,"", ror ""); 
+    endcase
+
+    warmreg(reg_s); 
+    end
+endtask
+
+
+task warmreg;
+input [3:0] regnum;
+    begin
+    if (regnum < 4\'d12)
+        $fwrite(decompile_file,""r%1d"", regnum);
+    else
+    case (regnum)
+        4\'d12   : $fwrite(decompile_file,""ip"");
+        4\'d13   : $fwrite(decompile_file,""sp"");
+        4\'d14   : $fwrite(decompile_file,""lr"");
+        4\'d15   : $fwrite(decompile_file,""pc"");
+    endcase
+    end
+endtask
+
+
+task fwrite_hex_drop_zeros;
+input [31:0] file;
+input [31:0] num;
+    begin
+    if (num[31:28] != 4\'d0) 
+        $fwrite(file, ""%x"", num);
+    else if (num[27:24] != 4\'d0) 
+        $fwrite(file, ""%x"", num[27:0]);
+    else if (num[23:20] != 4\'d0) 
+        $fwrite(file, ""%x"", num[23:0]);
+    else if (num[19:16] != 4\'d0) 
+        $fwrite(file, ""%x"", num[19:0]);
+    else if (num[15:12] != 4\'d0) 
+        $fwrite(file, ""%x"", num[15:0]);
+    else if (num[11:8] != 4\'d0) 
+        $fwrite(file, ""%x"", num[11:0]);
+    else if (num[7:4] != 4\'d0) 
+        $fwrite(file, ""%x"", num[7:0]);
+    else
+        $fwrite(file, ""%x"", num[3:0]);
+        
+    end
+endtask
+
+
+
+// =================================================================================
+// Functions
+// =================================================================================
+
+// Get current value of register
+function [31:0] get_reg_val;
+input [4:0] regnum;
+begin
+    case (regnum)
+        5\'d0   : get_reg_val = `U_REGISTER_BANK.r0_out;
+        5\'d1   : get_reg_val = `U_REGISTER_BANK.r1_out; 
+        5\'d2   : get_reg_val = `U_REGISTER_BANK.r2_out; 
+        5\'d3   : get_reg_val = `U_REGISTER_BANK.r3_out; 
+        5\'d4   : get_reg_val = `U_REGISTER_BANK.r4_out; 
+        5\'d5   : get_reg_val = `U_REGISTER_BANK.r5_out; 
+        5\'d6   : get_reg_val = `U_REGISTER_BANK.r6_out; 
+        5\'d7   : get_reg_val = `U_REGISTER_BANK.r7_out; 
+        5\'d8   : get_reg_val = `U_REGISTER_BANK.r8_out; 
+        5\'d9   : get_reg_val = `U_REGISTER_BANK.r9_out; 
+        5\'d10  : get_reg_val = `U_REGISTER_BANK.r10_out; 
+        5\'d11  : get_reg_val = `U_REGISTER_BANK.r11_out; 
+        5\'d12  : get_reg_val = `U_REGISTER_BANK.r12_out; 
+        5\'d13  : get_reg_val = `U_REGISTER_BANK.r13_out; 
+        5\'d14  : get_reg_val = `U_REGISTER_BANK.r14_out; 
+        5\'d15  : get_reg_val = `U_REGISTER_BANK.r15_out_rm; // the version of pc with status bits 
+        
+        5\'d16  : get_reg_val = `U_REGISTER_BANK.r14_svc;
+        5\'d17  : get_reg_val = `U_REGISTER_BANK.r14_firq;
+        5\'d18  : get_reg_val = `U_REGISTER_BANK.r14_irq;
+        5\'d19  : get_reg_val = `U_REGISTER_BANK.r14_svc;
+        5\'d20  : get_reg_val = `U_REGISTER_BANK.r14_svc;
+        5\'d21  : get_reg_val = `U_REGISTER_BANK.r15_out_rn; // the version of pc without status bits 
+    endcase
+end
+endfunction
+
+
+function [31:0] get_32bit_signal;
+input [2:0] num;
+begin
+    case (num)
+        3\'d0: get_32bit_signal = `U_EXECUTE.pc_nxt;
+        3\'d1: get_32bit_signal = `U_FETCH.i_address;
+        3\'d2: get_32bit_signal = `U_FETCH.i_address;
+        3\'d3: get_32bit_signal = `U_CACHE.i_write_data;
+        3\'d4: get_32bit_signal = `U_DECODE.i_read_data;
+    endcase
+end
+endfunction
+
+
+function get_1bit_signal;
+input [2:0] num;
+begin
+    case (num)
+        3\'d0: get_1bit_signal = `U_FETCH.i_write_enable;
+        3\'d1: get_1bit_signal = `U_AMBER.fetch_stall;
+        3\'d2: get_1bit_signal = 1\'d0;
+        3\'d3: get_1bit_signal = `U_FETCH.i_data_access;
+    endcase
+end
+endfunction
+
+
+function [3:0] get_4bit_signal;
+input [2:0] num;
+begin
+    case (num)
+        3\'d0: get_4bit_signal = `U_CACHE.i_byte_enable;
+    endcase
+end
+endfunction
+
+
+function [3:0] numchars;
+input [(5*8)-1:0] xINSTRUCTION_EXECUTE;
+begin
+     if (xINSTRUCTION_EXECUTE[31:0] == ""    "")
+    numchars = 4\'d1;
+else if (xINSTRUCTION_EXECUTE[23:0] == ""   "")
+    numchars = 4\'d2;
+else if (xINSTRUCTION_EXECUTE[15:0] == ""  "")
+    numchars = 4\'d3;
+else if (xINSTRUCTION_EXECUTE[7:0]  == "" "")
+    numchars = 4\'d4;
+else    
+    numchars = 4\'d5;
+end
+endfunction
+
+
+function more_to_come;
+input [15:0] regs;
+input [31:0] i;
+begin
+case (i)
+    15 : more_to_come = 1\'d0;
+    14 : more_to_come =  regs[15]    ? 1\'d1 : 1\'d0;
+    13 : more_to_come = |regs[15:14] ? 1\'d1 : 1\'d0;
+    12 : more_to_come = |regs[15:13] ? 1\'d1 : 1\'d0;
+    11 : more_to_come = |regs[15:12] ? 1\'d1 : 1\'d0;
+    10 : more_to_come = |regs[15:11] ? 1\'d1 : 1\'d0;
+     9 : more_to_come = |regs[15:10] ? 1\'d1 : 1\'d0;
+     8 : more_to_come = |regs[15: 9] ? 1\'d1 : 1\'d0;
+     7 : more_to_come = |regs[15: 8] ? 1\'d1 : 1\'d0;
+     6 : more_to_come = |regs[15: 7] ? 1\'d1 : 1\'d0;
+     5 : more_to_come = |regs[15: 6] ? 1\'d1 : 1\'d0;
+     4 : more_to_come = |regs[15: 5] ? 1\'d1 : 1\'d0;
+     3 : more_to_come = |regs[15: 4] ? 1\'d1 : 1\'d0;
+     2 : more_to_come = |regs[15: 3] ? 1\'d1 : 1\'d0;
+     1 : more_to_come = |regs[15: 2] ? 1\'d1 : 1\'d0;
+     0 : more_to_come = |regs[15: 1] ? 1\'d1 : 1\'d0;
+endcase
+end
+endfunction
+
+`endif
+
+endmodule
+
+"
+"//**************************************************************************
+//    hp_reg3.v - 2 byte FIFO for 16b transfers in host to parasite direction
+//   
+//    COPYRIGHT 2010 Richard Evans, Ed Spittles
+// 
+//    This file is part of tube - an Acorn Tube ULA compatible system.
+//   
+//    tube is free software: you can redistribute it and/or modify
+//    it under the terms of the GNU Lesser General Public License as published by
+//    the Free Software Foundation, either version 3 of the License, or
+//    (at your option) any later version.
+//
+//    tube is distributed in the hope that it will be useful,
+//    but WITHOUT ANY WARRANTY; without even the implied warranty of
+//    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//    GNU Lesser General Public License for more details.
+//
+//    You should have received a copy of the GNU Lesser General Public License
+//    along with tube.  If not, see <http://www.gnu.org/licenses/>.
+//
+// ============================================================================
+`timescale 1ns / 1ns
+
+module hp_reg3 (
+                input h_rst_b,
+                input h_we_b,
+                input h_selectData,
+                input h_phi2,
+                input [7:0] h_data,
+                
+                input       p_selectData,
+                input p_phi2,
+                input p_rdnw,
+                input       one_byte_mode,
+                
+                output [7:0] p_data,
+                output       p_data_available,
+                output       p_two_bytes_available,
+                output       h_full
+);
+
+   wire [1:0]    h_full_w;   
+   wire [1:0]    p_data_available_w;
+   reg [7:0]     byte0_q_r ;
+   reg [7:0]     byte1_q_r ;   
+   wire [7:0]    byte0_d_w ;
+   wire [7:0]    byte1_d_w ;   
+
+   // assign primary IOs
+   assign p_data = ( p_data_available_w[0] ) ? byte0_q_r: byte1_q_r;
+   // assign p_data = byte0_q_r;
+   assign p_two_bytes_available = !(one_byte_mode) & ( &p_data_available_w );   
+
+   // Compute D and resets for state bits
+   assign byte0_d_w = ( h_selectData & (!h_full_w[0] | one_byte_mode) & !h_we_b ) ? h_data : byte0_q_r;
+   assign byte1_d_w = ( h_selectData & ( h_full_w[0] & !one_byte_mode) & !h_we_b ) ? h_data : byte1_q_r;
+   
+// Register 3 is intended to enable high speed transfers of large blocks of data across the tube. 
+// It can operate in one or two byte mode, depending on the V flag. In one byte mode the status 
+// bits make each FIFO appear to be a single byte latch - after one byte is written the register 
+// appears to be full. In two byte mode the data available flag will only be asserted when two bytes have 
+// been entered, and the not full flag will only be asserted when both bytes have been removed. Thus data 
+// available going active means that two bytes are available, but it will remain active until both bytes 
+// have been removed. Not full going active means that the register is empty, but it will remain active 
+// until both bytes have been entered. PNMI, N and DRQ also remain active until the full two 
+// byte operation is completed
+   assign p_data_available = (p_data_available_w[0] & one_byte_mode) | p_data_available_w[1];
+   assign h_full = ( one_byte_mode ) ? h_full_w[0] : h_full_w[1];
+   
+   // Instance the appropriate flag logic
+
+   
+   hp_flag_m flag_0 (
+                       .rst_b(h_rst_b),
+                       .p1_rdnw( h_we_b),
+                       .p1_select(h_selectData & (!h_full_w[0] | one_byte_mode)),
+                       .p1_clk(h_phi2),
+                       .p2_select(p_selectData & (p_data_available_w[0] | one_byte_mode)),
+                       .p2_rdnw(p_rdnw),
+                       .p2_clk(p_phi2),                      
+                       .p2_data_available(p_data_available_w[0]),
+                       .p1_full(h_full_w[0])
+                       );
+
+   hp_flag_m flag_1 (
+                       .rst_b(h_rst_b),
+                       .p1_rdnw( h_we_b),
+                       .p1_select(h_selectData & (h_full_w[0] & !one_byte_mode)),
+                       .p1_clk(h_phi2),
+                       .p2_select(p_selectData & (!p_data_available_w[0] & !one_byte_mode)),
+                       .p2_rdnw(p_rdnw),
+                       .p2_clk(p_phi2),                      
+                       .p2_data_available(p_data_available_w[1]),
+                       .p1_full(h_full_w[1])
+                       );
+   
+   always @ ( negedge h_phi2 or negedge h_rst_b )
+     begin
+        if ( ! h_rst_b)
+          begin
+             byte0_q_r <= 8'h0;
+             byte1_q_r <= 8'h0;
+          end        
+        else
+          begin
+             byte0_q_r <= byte0_d_w ;
+             byte1_q_r <= byte1_d_w ;             
+          end
+        
+     end
+   
+endmodule // hp_reg3
+
+   "
+"/*
+ *  Fetch FSM helper for next state
+ *  Copyright (C) 2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+module zet_next_or_not (
+    input [1:0] prefix,
+    input [7:1] opcode,
+    input cx_zero,
+    input zf,
+    input ext_int,
+    output next_in_opco,
+    output next_in_exec,
+    output use_eintp
+  );
+
+  // Net declarations
+  wire exit_z, cmp_sca, exit_rep, valid_ops;
+
+  // Assignments
+  assign cmp_sca = opcode[7] & opcode[2] & opcode[1];
+  assign exit_z = prefix[0] ? /* repz */ (cmp_sca ? ~zf : 1'b0 )
+                            : /* repnz */ (cmp_sca ? zf : 1'b0 );
+  assign exit_rep = cx_zero | exit_z;
+  assign valid_ops = (opcode[7:1]==7'b1010_010   // movs
+                   || opcode[7:1]==7'b1010_011   // cmps
+                   || opcode[7:1]==7'b1010_101   // stos
+                   || opcode[7:1]==7'b0110_110   // ins
+                   || opcode[7:1]==7'b0110_111   // outs
+                   || opcode[7:1]==7'b1010_110   // lods
+                   || opcode[7:1]==7'b1010_111); // scas
+  assign next_in_exec = prefix[1] && valid_ops && !exit_rep && !ext_int;
+  assign next_in_opco = prefix[1] && valid_ops && cx_zero;
+  assign use_eintp    = prefix[1] && valid_ops && !exit_z;
+  
+endmodule
+"
+"/*
+ *  Add / substract unit for Zet
+ *  Copyright (C) 2008-2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+module zet_addsub (
+    input  [15:0] x,
+    input  [15:0] y,
+    output [15:0] out,
+    input  [ 2:0] f,
+    input         word_op,
+    input         cfi,
+    output        cfo,
+    output        afo,
+    output        ofo
+  );
+
+  // Net declarations
+  wire [15:0] op2;
+
+  wire ci;
+  wire cfoadd;
+  wire xs, ys, os;
+
+  // Module instances
+  zet_fulladd16 fulladd16 ( // We instantiate only one adder
+    .x  (x),                //  to have less hardware
+    .y  (op2),
+    .ci (ci),
+    .co (cfoadd),
+    .z  (out),
+    .s  (f[2])
+  );
+
+  // Assignments
+  assign op2 = f[2] ? ~y
+             : ((f[1:0]==2'b11) ? { 8'b0, y[7:0] } : y);
+  assign ci  = f[2] & f[1] | f[2] & ~f[0] & ~cfi
+             | f[2] & f[0] | (f==3'b0) & cfi;
+  assign afo = f[1] ? (f[2] ? &out[3:0] : ~|out[3:0] )
+                    : (x[4] ^ y[4] ^ out[4]);
+  assign cfo = f[1] ? cfi /* inc, dec */
+             : (word_op ? cfoadd : (x[8]^y[8]^out[8]));
+
+  assign xs  = word_op ? x[15] : x[7];
+  assign ys  = word_op ? y[15] : y[7];
+  assign os  = word_op ? out[15] : out[7];
+  assign ofo = f[2] ? (~xs & ys & os | xs & ~ys & ~os)
+                    : (~xs & ~ys & os | xs & ys & ~os);
+endmodule
+"
+"/*
+ *  Wishbone Compatible BIOS ROM core using megafunction ROM
+ *  Copyright (C) 2010  Donna Polehn <dpolehn@verizon.net>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+// The following is to get rid of the warning about not initializing the ROM
+// altera message_off 10030
+
+module bootrom (
+    input clk,
+    input rst,
+
+    // Wishbone slave interface
+    input  [15:0] wb_dat_i,
+    output [15:0] wb_dat_o,
+    input  [19:1] wb_adr_i,
+    input         wb_we_i,
+    input         wb_tga_i,
+    input         wb_stb_i,
+    input         wb_cyc_i,
+    input  [ 1:0] wb_sel_i,
+    output        wb_ack_o
+  );
+
+  // Net declarations
+  reg  [15:0] rom[0:8191];  // Instantiate the ROM
+
+  wire [ 12:0] rom_addr;
+  wire        stb;
+
+  // Combinatorial logic
+  assign rom_addr = wb_adr_i[13:1];
+  assign stb      = wb_stb_i & wb_cyc_i;
+  assign wb_ack_o = stb;
+  assign wb_dat_o = rom[rom_addr];
+
+  initial $readmemh(""bootrom.dat"", rom);
+
+endmodule
+"
+"//////////////////////////////////////////////////////////////////
+//                                                              //
+//  Wrapper for Xilinx Spartan-6 DSP48 Block                    //
+//                                                              //
+//  This file is part of the Amber project                      //
+//  http://www.opencores.org/project,amber                      //
+//                                                              //
+//  Description                                                 //
+//  DSP block configured as an N-bit adder and substractor      //
+//                                                              //
+//  Author(s):                                                  //
+//      - Conor Santifort, csantifort.amber@gmail.com           //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+//                                                              //
+// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
+//                                                              //
+// This source file may be used and distributed without         //
+// restriction provided that this copyright statement is not    //
+// removed from the file and that any derivative work contains  //
+// the original copyright notice and the associated disclaimer. //
+//                                                              //
+// This source file is free software; you can redistribute it   //
+// and/or modify it under the terms of the GNU Lesser General   //
+// Public License as published by the Free Software Foundation; //
+// either version 2.1 of the License, or (at your option) any   //
+// later version.                                               //
+//                                                              //
+// This source is distributed in the hope that it will be       //
+// useful, but WITHOUT ANY WARRANTY; without even the implied   //
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
+// PURPOSE.  See the GNU Lesser General Public License for more //
+// details.                                                     //
+//                                                              //
+// You should have received a copy of the GNU Lesser General    //
+// Public License along with this source; if not, download it   //
+// from http://www.opencores.org/lgpl.shtml                     //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+
+
+module xs6_addsub_n #(
+parameter WIDTH=32
+)(
+input [WIDTH-1:0]   i_a,
+input [WIDTH-1:0]   i_b,
+input               i_cin,
+input               i_sub,
+
+output [WIDTH-1:0]  o_sum,
+output              o_co
+);
+
+
+wire [7:0]  opmode;
+wire [47:0] in_a, in_b;
+wire [47:0] out;
+
+assign opmode = {i_sub, 1\'d0, i_cin, 1\'d0, 2\'d3, 2\'d3 };
+assign in_a   = {{48-WIDTH{1\'d0}}, i_a};
+assign in_b   = {{48-WIDTH{1\'d0}}, i_b};
+assign o_sum  = out[WIDTH-1:0];
+assign o_co   = out[WIDTH];
+
+
+DSP48A1  #(
+    // Enable registers
+    .A1REG          ( 0         ),
+    .B0REG          ( 0         ),
+    .B1REG          ( 0         ),
+    .CARRYINREG     ( 0         ),
+    .CARRYOUTREG    ( 0         ),
+    .CREG           ( 0         ),
+    .DREG           ( 0         ),
+    .MREG           ( 0         ),
+    .OPMODEREG      ( 0         ),
+    .PREG           ( 0         ),
+    .CARRYINSEL     (""OPMODE5""  ),
+    .RSTTYPE        ( ""SYNC""    )
+)
+
+u_dsp48 (
+    // Outputs
+    .BCOUT         (                        ),
+    .CARRYOUT      (                        ),
+    .CARRYOUTF     (                        ), 
+    .M             (                        ),
+    .P             ( out                    ),
+    .PCOUT         (                        ),
+                                           
+    // Inputs
+    .CLK           ( 1\'d0                   ),
+                                           
+    .A             (         in_b[35:18]    ),
+    .B             (         in_b[17:00]    ),
+    .C             (         in_a           ),
+    .D             ( {6\'d0,  in_b[47:36]}   ),
+
+    .CARRYIN       ( 1\'d0                   ),  // uses opmode bit 5 for carry in
+    .OPMODE        ( opmode                 ),
+    .PCIN          ( 48\'d0                  ),
+
+    // Clock enables
+    .CEA           ( 1\'d1                   ),
+    .CEB           ( 1\'d1                   ),
+    .CEC           ( 1\'d1                   ),
+    .CED           ( 1\'d1                   ),
+    .CEM           ( 1\'d1                   ),
+    .CEP           ( 1\'d1                   ),
+    .CECARRYIN     ( 1\'d1                   ),
+    .CEOPMODE      ( 1\'d1                   ),
+    
+    // Register Resets
+    .RSTA          ( 1\'d0                   ),
+    .RSTB          ( 1\'d0                   ),
+    .RSTC          ( 1\'d0                   ),
+    .RSTCARRYIN    ( 1\'d0                   ),
+    .RSTD          ( 1\'d0                   ),
+    .RSTM          ( 1\'d0                   ),
+    .RSTOPMODE     ( 1\'d0                   ),
+    .RSTP          ( 1\'d0                   )
+    );
+    
+    
+endmodule
+"
+"`timescale 1ns / 1ns
+
+`define p1edge posedge
+`define p2edge negedge
+
+module ph_flag_m
+\t\t  
+`include ""gen_flag_v3.v"""
+"/*
+ *  8254 timer simplified for Zet SoC
+ *  Copyright (c) 2010  YS <ys05@mail.ru>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ *  This module uses:
+ *   - Wishbone interface
+ *   - Modes (binary) 2 and 3 only
+ *   - Common clock for all 3 Timers (tclk_i)
+ *   - Gate input for Timer2 only (gate2_i)
+ *  Assumptions:
+ *   1. tclk_i is asynchronous simple wire (1.193182 MHz by default)
+ *   2. gate2_i is synchronous (comes from Wishbone controlled register)
+ *   3. Wishbone clock wb_clk_i is running always and it has much higher
+ *      frequency than tclk_i
+ */
+
+`define WB_UNBUFFERED_8254
+
+module timer
+  (
+    // Wishbone slave interface
+    input             wb_clk_i,
+    input             wb_rst_i,
+    input             wb_adr_i,
+    input      [1:0]  wb_sel_i,
+    input      [15:0] wb_dat_i,
+    output reg [15:0] wb_dat_o,
+    input             wb_stb_i,
+    input             wb_cyc_i,
+    input             wb_we_i,
+    output            wb_ack_o,
+    output reg        wb_tgc_o,   // intr
+
+    // CLK 
+    input             tclk_i,     // 1.193182 MHz = (14.31818/12) MHz
+    // SPEAKER
+    input             gate2_i,
+    output            out2_o
+  );
+
+`ifdef WB_UNBUFFERED_8254
+  wire [15:0] data_ib;
+  wire wr_cyc1;
+  wire rd_cyc1;
+  wire [1:0] datasel;
+`else
+  reg [15:0] data_ib;
+  reg wr_cyc1;
+  reg rd_cyc1, rd_cyc2;
+  reg [1:0] datasel;
+`endif
+
+  wire intr, refresh;
+  reg intr1;
+  //reg [7:0] dat_o;
+
+  wire wrc, wrd0, wrd1, wrd2, rdd0, rdd1, rdd2;
+  wire [7:0] data0;
+  wire [7:0] data1;
+  wire [7:0] data2;
+
+  // Making 1 clock pulse on wb_tgc_o from intr
+  // unnecessary for real 8259A -> subj to remove later
+  always @(posedge wb_clk_i)
+  begin
+    intr1 <= wb_rst_i ? 1'b0 : intr;
+    wb_tgc_o <= wb_rst_i ? 1'b0 : (!intr1 & intr);
+  end
+
+  // 8-bit interface via wb_dat low byte (2-bit [2:1]??? wb_addr_i , no wb_sel_i)
+  /*
+  assign wb_ack_o = wb_stb_i & wb_cyc_i;
+
+  assign wrc = wb_ack_o & wb_we_i & (wb_adr_i == 2'b11);
+
+  assign wrd0 = wb_ack_o & wb_we_i & (wb_adr_i == 2'b00);
+  assign wrd1 = wb_ack_o & wb_we_i & (wb_adr_i == 2'b01);
+  assign wrd2 = wb_ack_o & wb_we_i & (wb_adr_i == 2'b10);
+
+  assign rdd0 = wb_ack_o & ~wb_we_i & (wb_adr_i == 2'b00);
+  assign rdd1 = wb_ack_o & ~wb_we_i & (wb_adr_i == 2'b01);
+  assign rdd2 = wb_ack_o & ~wb_we_i & (wb_adr_i == 2'b10);
+
+  always @(wb_adr_i or data0 or data1 or data2)
+    case (wb_adr_i)
+      2'b00: wb_dat_o = { 8'h0, data0 };
+      2'b01: wb_dat_o = { 8'h0, data1 };
+      2'b10: wb_dat_o = { 8'h0, data2 };
+    endcase
+
+  timer_counter cnt0(0, 6'h36, 16'hFFFF, wb_clk_i, wb_rst_i, wrc, wrd0, rdd0, wb_dat_i, data0, tclk_i, 1'b1, intr);    // 16-bit 55 ms Mode 3
+  timer_counter cnt1(1, 6'h14, 16'h0012, wb_clk_i, wb_rst_i, wrc, wrd1, rdd1, wb_dat_i, data1, tclk_i, 1'b1, refresh); // 8-bit  15 us Mode 2
+  timer_counter cnt2(2, 6'h36, 16'h04A9, wb_clk_i, wb_rst_i, wrc, wrd2, rdd2, wb_dat_i, data2, tclk_i, gate2_i, out2_o);  // 16-bit  1 ms Mode 3
+  */
+
+  // 16-bit interface via wb_dat both bytes (1-bit wb_addr_i, 2-bit [1:0] wb_sel_i)
+  // assumes opposite wb_sel_i only: 2'b10 or 2'b01
+
+  reg [7:0] data_i;
+  reg [15:0] data_ob;
+
+  always @(datasel or data0 or data1 or data2)
+    case (datasel)
+      2'b00: data_ob = { 8'h0, data0 };
+      2'b01: data_ob = { data1, 8'h0 };
+      2'b10: data_ob = { 8'h0, data2 };
+      2'b11: data_ob = { 8'h0, 8'h0 }; // not checked yet!
+    endcase
+
+  always @(datasel or data_ib)
+    case (datasel)
+      2'b00: data_i = data_ib[7:0];
+      2'b01: data_i = data_ib[15:8];
+      2'b10: data_i = data_ib[7:0];
+      2'b11: data_i = data_ib[15:8];
+    endcase
+
+  assign wrc = wr_cyc1 & (datasel == 2'b11);
+
+  assign wrd0 = wr_cyc1 & (datasel == 2'b00);
+  assign wrd1 = wr_cyc1 & (datasel == 2'b01);
+  assign wrd2 = wr_cyc1 & (datasel == 2'b10);
+
+  assign rdd0 = rd_cyc1 & (datasel == 2'b00);
+  assign rdd1 = rd_cyc1 & (datasel == 2'b01);
+  assign rdd2 = rd_cyc1 & (datasel == 2'b10);
+
+  `ifdef WB_UNBUFFERED_8254
+  // 1 clock write, 1 clock read
+
+  assign wb_ack_o = wb_stb_i & wb_cyc_i;
+
+  assign wr_cyc1 = wb_ack_o & wb_we_i;
+  assign rd_cyc1 = wb_ack_o & ~wb_we_i;
+  assign datasel = {wb_adr_i,wb_sel_i[1]};
+
+  //assign wb_dat_o = data_ob;
+  always @(data_ob)
+    wb_dat_o = data_ob;
+  assign data_ib = wb_dat_i;
+
+  `else
+  // 2 clocks write, 3 clocks read
+
+  assign wb_ack_o = wr_cyc1 | rd_cyc2;
+
+  always @(posedge wb_clk_i)
+  begin
+    wr_cyc1 <= (wr_cyc1) ? 1'b0 : wb_stb_i & wb_cyc_i & wb_we_i;            // single clock write pulse
+    rd_cyc1 <= (rd_cyc1 | rd_cyc2) ? 1'b0 : wb_stb_i & wb_cyc_i & ~wb_we_i; // single clock read pulse
+    rd_cyc2 <= rd_cyc1;                                                     // delayed single clock read pulse
+    datasel <= {wb_adr_i,wb_sel_i[1]};
+
+    wb_dat_o <= data_ob;
+    data_ib <= wb_dat_i;
+  end
+
+  `endif //def WB_UNBUFFERED_8254
+
+  // Module instantiations
+
+  timer_counter cnt0 (
+    .cntnum (2'd0),
+    .cw0    (6'h36),      // 16-bit Mode 3
+    .cr0    (16'hFFFF),   // 55 ms
+    .clkrw  (wb_clk_i),
+    .rst    (wb_rst_i),
+    .wrc    (wrc),
+    .wrd    (wrd0),
+    .rdd    (rdd0),
+    .data_i (data_i),
+    .data_o (data0),
+    .clkt   (tclk_i),
+    .gate   (1'b1),
+    .out    (intr)
+    );
+
+  timer_counter cnt1 (
+    .cntnum (2'd1),
+    .cw0    (6'h14),      // 8-bit Mode 2
+    .cr0    (16'h0012),   // 15 us
+    .clkrw  (wb_clk_i),
+    .rst    (wb_rst_i),
+    .wrc    (wrc),
+    .wrd    (wrd1),
+    .rdd    (rdd1),
+    .data_i (data_i),
+    .data_o (data1),
+    .clkt   (tclk_i),
+    .gate   (1'b1),
+    .out    (refresh)
+    );
+
+  timer_counter cnt2 (
+    .cntnum (2'd2),
+    .cw0    (6'h36),      // 16-bit Mode 3
+    .cr0    (16'h04A9),   // 1 ms
+    .clkrw  (wb_clk_i),
+    .rst    (wb_rst_i),
+    .wrc    (wrc),
+    .wrd    (wrd2),
+    .rdd    (rdd2),
+    .data_i (data_i),
+    .data_o (data2),
+    .clkt   (tclk_i),
+    .gate   (gate2_i),
+    .out    (out2_o)
+    );
+
+endmodule
+"
+"/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  Non-restoring signed by unsigned divider                   ////
+////  Uses the non-restoring unsigned by unsigned divider        ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2002 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: div_su.v,v 1.2 2002/10/31 13:54:58 rherveille Exp $
+//
+//  $Date: 2002/10/31 13:54:58 $
+//  $Revision: 1.2 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: div_su.v,v $
+//               Revision 1.2  2002/10/31 13:54:58  rherveille
+//               Fixed a bug in the remainder output of div_su.v
+//
+//               Revision 1.1.1.1  2002/10/29 20:29:09  rherveille
+//
+//
+//
+
+//synopsys translate_off
+`timescale 1ns/10ps
+//synopsys translate_on
+
+module zet_div_su (clk, ena, z, d, q, s, ovf);
+
+  //
+  // parameters
+  //
+  parameter z_width = 16;
+  parameter d_width = z_width /2;
+  
+  //
+  // inputs & outputs
+  //
+  input clk;              // system clock
+  input ena;              // clock enable
+
+  input  [z_width-1:0] z; // divident
+  input  [d_width-1:0] d; // divisor
+  output [d_width  :0] q; // quotient
+  output [d_width  :0] s; // remainder
+  output ovf;
+
+  reg [d_width:0] q, s;
+  reg ovf;
+
+  //
+  // variables
+  //
+  reg [z_width -1:0] iz;
+  reg [d_width -1:0] id;
+  reg [d_width +1:0] szpipe, sdpipe;
+
+  wire [d_width -1:0] iq, is;
+  wire                idiv0, iovf;
+
+  //
+  // module body
+  //
+
+  // check d, take abs value
+  always @(posedge clk)
+    if (ena)
+      if (d[d_width-1])
+         id <= ~d +1'h1;
+      else
+         id <= d;
+
+  // check z, take abs value
+  always @(posedge clk)
+    if (ena)
+      if (z[z_width-1])
+         iz <= ~z +1'h1;
+      else
+         iz <= z;
+
+  // generate szpipe (z sign bit pipe)
+  integer n;
+  always @(posedge clk)
+    if(ena)
+    begin
+        szpipe[0] <= z[z_width-1];
+
+        for(n=1; n <= d_width+1; n=n+1)
+           szpipe[n] <= szpipe[n-1];
+    end
+
+  // generate sdpipe (d sign bit pipe)
+  integer m;
+  always @(posedge clk)
+    if(ena)
+    begin
+        sdpipe[0] <= d[d_width-1];
+
+        for(m=1; m <= d_width+1; m=m+1)
+           sdpipe[m] <= sdpipe[m-1];
+    end
+
+  // hookup non-restoring divider
+  zet_div_uu #(z_width, d_width)
+  divider (
+    .clk(clk),
+    .ena(ena),
+    .z(iz),
+    .d(id),
+    .q(iq),
+    .s(is),
+    .div0(idiv0),
+    .ovf(iovf)
+  );
+
+  // correct divider results if 'd' was negative
+  always @(posedge clk)
+    if(ena)
+      begin
+         q <= (szpipe[d_width+1]^sdpipe[d_width+1]) ?
+              ((~iq) + 1'h1) : ({1'b0, iq});
+         s <= (szpipe[d_width+1]) ?
+              ((~is) + 1'h1) : ({1'b0, is});
+      end
+
+  // delay flags same as results
+  always @(posedge clk)
+    if(ena)
+    begin
+        ovf  <= iovf;
+    end
+endmodule
+"
+"// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+// This file is part of the M32632 project\r
+// http://opencores.org/project,m32632\r
+//\r
+// Filename: I_PFAD.v\r
+// Version:  1.2 bug fix\r
+// Version:  1.1 bug fix release of 7 November 2015\r
+// History:  1.0 first release of 30 Mai 2015\r
+// Date:     4 February 2016\r
+//\r
+// Copyright (C) 2016 Udo Moeller\r
+// \r
+// This source file may be used and distributed without \r
+// restriction provided that this copyright statement is not \r
+// removed from the file and that any derivative work contains \r
+// the original copyright notice and the associated disclaimer.\r
+// \r
+// This source file is free software; you can redistribute it \r
+// and/or modify it under the terms of the GNU Lesser General \r
+// Public License as published by the Free Software Foundation;\r
+// either version 2.1 of the License, or (at your option) any \r
+// later version. \r
+// \r
+// This source is distributed in the hope that it will be \r
+// useful, but WITHOUT ANY WARRANTY; without even the implied \r
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR \r
+// PURPOSE. See the GNU Lesser General Public License for more \r
+// details. \r
+// \r
+// You should have received a copy of the GNU Lesser General \r
+// Public License along with this source; if not, download it \r
+// from http://www.opencores.org/lgpl.shtml \r
+// \r
+// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\tModules contained in this file:\r
+//\t1. BITMASK  \tMask Generator , was a ROM on falling edge in early days\r
+//\t2. MULFILTER \tFilter for Multiplier Input Data\r
+//\t3. SIGNMUL\t\tSigned Multiplier for Integer Multiplication\r
+//\t4. SHIFTER\t\tBarrel Shifter for all Shift Opcodes\r
+//\t5. FFS_LOGIK\tLogic for FFS opcode \r
+//\t6. SCHALE\t\tEnclosure for Adder/Subtractor\r
+//\t7. I_PFAD\t\tThe Integer Datapath\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t1. BITMASK  \tMask Generator , was a ROM on falling edge in early days\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module BITMASK (AA, DOUT);\r
+\r
+//\t0    :   FFFFFFFF;\tMasktype 1 , Zero from right\r
+//\t1    :   FFFFFFFE;\r
+//\t2    :   FFFFFFFC;\r
+//\t3    :   FFFFFFF8;\r
+//\t.    :   ...\r
+//\t32   :   00000001;\tMasktype 2 , Decoder\r
+//\t33   :   00000002;\r
+//\t34   :   00000004;\r
+//\t35   :   00000008;\r
+//\t..   :   ...\r
+//\t64   :   00000001;\tMasktyte 3 , One from right\r
+//\t65   :   00000003;\r
+//\t66   :   00000007;\r
+//\t67   :   0000000F;\r
+//\t..   :   ...\r
+//\t96   :   FFFFFFFF;\tMasktype 4 , like Masktype 3 but AA-1\r
+//\t97   :   00000001;\r
+//\t98   :   00000003;\r
+//\t99   :   00000007;\r
+//\t..   :   ...\r
+\r
+\tinput\t \t[6:0]\tAA;\r
+\t\r
+\toutput\treg\t[31:0]\tDOUT;\r
+\t\r
+\treg\t\t[7:0]\tdec_bit;\r
+\t\r
+\twire\t [4:0]\tcode;\r
+\twire\t\t\thigh,low;\r
+\t\r
+\t\r
+\tassign code = AA[4:0] - {4\'d0,&AA[6:5]};\r
+\t\r
+\tassign high = (AA[6:5] == 2\'d0);\r
+\tassign low  =  AA[6];\r
+\t\r
+\talways @(code or high or low)\r
+\t\tcase (code[2:0])\r
+\t\t  3\'b000 : dec_bit = {{7{high}},1\'b1         };\r
+\t\t  3\'b001 : dec_bit = {{6{high}},1\'b1,   low  };\r
+\t\t  3\'b010 : dec_bit = {{5{high}},1\'b1,{2{low}}};\r
+\t\t  3\'b011 : dec_bit = {{4{high}},1\'b1,{3{low}}};\r
+\t\t  3\'b100 : dec_bit = {{3{high}},1\'b1,{4{low}}};\r
+\t\t  3\'b101 : dec_bit = {{2{high}},1\'b1,{5{low}}};\r
+\t\t  3\'b110 : dec_bit = {   high  ,1\'b1,{6{low}}};\r
+\t\t  3\'b111 : dec_bit = {          1\'b1,{7{low}}};\r
+\t\tendcase\r
+\r
+\talways @(code or high or low or dec_bit)\r
+\t\tcase (code[4:3])\r
+\t\t  2\'b00 : DOUT = {{24{high}},dec_bit\t\t  };\r
+\t\t  2\'b01 : DOUT = {{16{high}},dec_bit,{ 8{low}}};\r
+\t\t  2\'b10 : DOUT = {{ 8{high}},dec_bit,{16{low}}};\r
+\t\t  2\'b11 : DOUT = {           dec_bit,{24{low}}};\r
+\t\tendcase\r
+\t\t\r
+endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t2. MULFILTER \tFilter for Multiplier Input Data\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module MULFILTER (BWD, FLOAT, SRC1, SRC2, DEST1, DEST2);\r
+\r
+\tinput\t [1:0]\tBWD;\r
+\tinput\t\t\tFLOAT;\r
+\tinput\t[31:0]\tSRC1,SRC2;\r
+\toutput\t[31:0]\tDEST1,DEST2;\r
+\r
+\twire\t\t\tsign1,sign2;\r
+\treg\t\t[31:0]\tDEST1,DEST2;\r
+\t\r
+\tassign sign1 = BWD[0] ? SRC1[15] : SRC1[7];\r
+\t\t  \r
+\talways @(FLOAT or BWD or SRC1 or sign1)\r
+\t\tcasex ({FLOAT,BWD,sign1})\r
+\t\t  4\'b0_00_0 : DEST1 = {24\'h000000, SRC1[7:0]};\r
+\t\t  4\'b0_00_1 : DEST1 = {24\'hFFFFFF, SRC1[7:0]};\r
+\t\t  4\'b0_01_0 : DEST1 = {  16\'h0000,SRC1[15:0]};\r
+\t\t  4\'b0_01_1 : DEST1 = {  16\'hFFFF,SRC1[15:0]};\r
+\t\t  4\'b1_xx_x : DEST1 = {    9\'h001,SRC1[22:0]};\r
+\t\t  default\t: DEST1 = SRC1;\r
+\t\tendcase\r
+\t\t\r
+\tassign sign2 = BWD[0] ? SRC2[15] : SRC2[7];\r
+\t\t  \r
+\talways @(FLOAT or BWD or SRC2 or sign2)\r
+\t\tcasex ({FLOAT,BWD,sign2})\r
+\t\t  4\'b0_00_0 : DEST2 = {24\'h000000, SRC2[7:0]};\r
+\t\t  4\'b0_00_1 : DEST2 = {24\'hFFFFFF, SRC2[7:0]};\r
+\t\t  4\'b0_01_0 : DEST2 = {  16\'h0000,SRC2[15:0]};\r
+\t\t  4\'b0_01_1 : DEST2 = {  16\'hFFFF,SRC2[15:0]};\r
+\t\t  4\'b1_xx_x : DEST2 = {    9\'h001,SRC2[22:0]};\r
+\t\t  default\t: DEST2 = SRC2;\r
+\t\tendcase\r
+\t\t\r
+endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t3. SIGNMUL\t\tSigned Multiplier for Integer Multiplication\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module SIGNMUL (dataa, datab, result);\r
+\r
+\tinput\tsigned\t[31:0]\tdataa,datab;\r
+\toutput\tsigned\t[63:0]\tresult;\r
+\t\r
+\tassign result = dataa * datab;\r
+\t\r
+endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t4. SHIFTER\t\tBarrel Shifter for all Shift Opcodes\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module SHIFTER ( MASKE,ROT,LSH,ASH,SIZE,SH_VAL,SH_DAT,SH_OUT,MASK_SEL);\r
+\r
+\tinput  [31:0] MASKE;\r
+\tinput\t      ROT,LSH,ASH;\r
+\tinput   [1:0] SIZE;\r
+\tinput   [7:0] SH_VAL;\r
+\tinput  [31:0] SH_DAT;\r
+\toutput [31:0] SH_OUT;\r
+\toutput  [4:0] MASK_SEL;\r
+\r
+\treg  [31:0] sh_dat_in;\r
+\twire [31:0] sh_dat_0,sh_dat_1,sh_dat_2,sh_dat_3,sh_dat_4;\r
+\twire  [4:0] shift;\r
+\treg\t\t    msb;\r
+\twire  [1:0] mask_code;\r
+\treg  [31:0] SH_OUT;\r
+\treg   [4:0] MASK_SEL;\r
+\t\r
+\t// Inputstage : prepare for ROT opcode :\r
+\t\r
+\talways @(ROT or SIZE or SH_DAT)\r
+\t  casex ({ROT,SIZE})\r
+\t\t3\'b100  : sh_dat_in = {SH_DAT[31:16],SH_DAT[7:0],SH_DAT[7:0]};\t// Byte copy to left\r
+\t\t3\'b101  : sh_dat_in = {SH_DAT[15:0],SH_DAT[15:0]};\t// Word copy to left\r
+\t\tdefault : sh_dat_in = SH_DAT;\r
+\t  endcase\r
+\t\r
+\t// Special case for ROT and BYTE : this way less logic\r
+\t\r
+\tassign shift = (ROT & (SIZE == 2\'b00)) ? {2\'b11,SH_VAL[2:0]} : SH_VAL[4:0];\r
+\t\r
+\t// Rotation logic\r
+\t\r
+\tassign sh_dat_0 = shift[0] ? {sh_dat_in[30:0],sh_dat_in[31]} : sh_dat_in;\t// Rotation of 1 bit position\r
+\tassign sh_dat_1 = shift[1] ? {sh_dat_0[29:0],sh_dat_0[31:30]} : sh_dat_0;\t// 2\r
+\tassign sh_dat_2 = shift[2] ? {sh_dat_1[27:0],sh_dat_1[31:28]} : sh_dat_1;\t// 4\r
+\tassign sh_dat_3 = shift[3] ? {sh_dat_2[23:0],sh_dat_2[31:24]} : sh_dat_2;\t// 8\r
+\tassign sh_dat_4 = shift[4] ? {sh_dat_3[15:0],sh_dat_3[31:16]} : sh_dat_3;\t// 16\r
+\r
+\t// Detection of negativ data\t\r
+\r
+\talways @(SIZE or SH_DAT)\r
+\t  casex (SIZE)\r
+\t\t2\'b00   : msb = SH_DAT[7];\t// Byte\r
+\t\t2\'b01   : msb = SH_DAT[15];\t// Word\r
+\t\tdefault : msb = SH_DAT[31];\t// Double = 11\r
+\t  endcase\r
+\t\r
+\t// needs mask for output data : SH_VAL[7] says negativ number and ""right"" shift\r
+\t\r
+\tassign mask_code[1] = ROT | (SH_VAL[7] &   ASH &  msb);\r
+\tassign mask_code[0] = ROT | (SH_VAL[7] & ((ASH & ~msb) | LSH));\r
+\r
+\talways @(SH_VAL or SIZE)\r
+\t  casex ({SH_VAL[7],SIZE})\r
+\t\t3\'b100  : MASK_SEL = {2\'b00,SH_VAL[2:0]};\t// special mask for Byte at right-shift\r
+\t\t3\'b101  : MASK_SEL = {1\'b0,SH_VAL[3:0]};\t// special mask for Word at right-shift\r
+\t\tdefault : MASK_SEL = SH_VAL[4:0];\r
+\t  endcase\r
+\r
+\talways @(mask_code or sh_dat_4 or MASKE)\t// top bits of MASKE are ""1"", lower bits are ""0""\r
+\t  casex (mask_code)\r
+\t\t  2\'b00 : SH_OUT = sh_dat_4 &  MASKE;\t// LSH and ASH with positiv shift count\r
+\t\t  2\'b01 : SH_OUT = sh_dat_4 & ~MASKE;\t// Negativ shift count : LSH or ASH with positiv data\r
+\t\t  2\'b10 : SH_OUT = sh_dat_4 |  MASKE;\t// ASH with negativ shift count and negativ input data\r
+\t\tdefault : SH_OUT = sh_dat_4;\t\t\t// ROT\r
+\t  endcase\r
+\r
+endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t5. FFS_LOGIK\tLogic for FFS opcode \r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module FFS_LOGIK  (SRC1, SRC2, BWD, FLAG, DOUT);\r
+\r
+\tinput\t[31:0]\tSRC1;\r
+\tinput\t [4:0]\tSRC2;\r
+\tinput\t [1:0]\tBWD;\r
+\toutput\treg\t\tFLAG;\r
+\toutput\t [4:0]\tDOUT;\r
+\r
+\treg\t\t [6:0]\tmaske;\r
+\treg\t\t [7:0]\tbyte_1,byte_2;\r
+\t\r
+\twire\t [7:0]\tbyte_0,byte_3;\r
+\twire\t[15:0]\tmdat_0;\r
+\twire\t [7:0]\tmdat_1;\r
+\twire\t [3:0]\tmdat_2;\r
+\twire\t [1:0]\tmdat_3;\r
+\twire\t [4:0]\tobits;\r
+\t\r
+\talways @(*)\r
+\t\tcase (SRC2[2:0])\r
+\t\t  3\'d0 : maske = 7\'h7F;\r
+\t\t  3\'d1 : maske = 7\'h7E;\r
+\t\t  3\'d2 : maske = 7\'h7C;\r
+\t\t  3\'d3 : maske = 7\'h78;\r
+\t\t  3\'d4 : maske = 7\'h70;\r
+\t\t  3\'d5 : maske = 7\'h60;\r
+\t\t  3\'d6 : maske = 7\'h40;\r
+\t\t  3\'d7 : maske = 7\'h00;\r
+\t\tendcase\r
+\t\t\r
+\tassign byte_0 = (SRC2[4:3] == 2\'b00) ? {SRC1[7],(SRC1[6:0] & maske)} : 8\'h00;\r
+\t\r
+\talways @(*)\r
+\t\tcasex (SRC2[4:3])\r
+\t\t  2\'b00 : byte_1 = SRC1[15:8];\r
+\t\t  2\'b01 : byte_1 = {SRC1[15],(SRC1[14:8] & maske)}; \r
+\t\t  2\'b1x : byte_1 = 8\'h00;\r
+\t\tendcase\r
+\t\t\r
+\talways @(*)\r
+\t\tcasex (SRC2[4:3])\r
+\t\t  2\'b0x : byte_2 = SRC1[23:16];\r
+\t\t  2\'b10 : byte_2 = {SRC1[23],(SRC1[22:16] & maske)}; \r
+\t\t  2\'b11 : byte_2 = 8\'h00;\r
+\t\tendcase\r
+\t\t\r
+\tassign byte_3 = (SRC2[4:3] == 2\'b11) ? {SRC1[31],(SRC1[30:24] & maske)} : SRC1[31:24];\r
+\r
+\tassign obits[4] = ({byte_1,byte_0} == 16\'h0);\r
+\tassign mdat_0\t= obits[4] ? {byte_3,byte_2} : {byte_1,byte_0};\t// 16 Bit\r
+\r
+\tassign obits[3]\t= (mdat_0[7:0] == 8\'h0);\r
+\tassign mdat_1\t= obits[3] ? mdat_0[15:8] : mdat_0[7:0];\r
+\r
+\tassign obits[2] = (mdat_1[3:0] == 4\'h0);\r
+\tassign mdat_2\t= obits[2] ? mdat_1[7:4] : mdat_1[3:0];\r
+\t\r
+\tassign obits[1] = (mdat_2[1:0] == 2\'b0);\r
+\tassign mdat_3\t= obits[1] ? mdat_2[3:2] : mdat_2[1:0];\r
+\t\r
+\tassign obits[0] = ~mdat_3[0];\r
+\t\r
+\talways @(BWD or obits or mdat_3)\r
+\t\tcasex ({BWD,obits[4:3]})\r
+\t\t  4\'b00_x1 : FLAG = 1;\t// Byte Overflow => nothing found\r
+\t\t  4\'b00_10 : FLAG = 1;\t// Byte Overflow => nothing found\r
+\t\t  4\'b01_1x : FLAG = 1;\t// Word Overflow => nothing found\r
+\t\t  default  : FLAG = (mdat_3 == 2\'b00);\r
+\t\tendcase\r
+\r
+\tassign DOUT = FLAG ? 5\'h0 : obits;\r
+\t\r
+endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t6. SCHALE\t\tEnclosure for Adder/Subtractor\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module SCHALE (dataa, datab, cin, add_sub, bwd, result, cout, overflow);\r
+\r
+\tinput\t[31:0]\tdataa,datab;\r
+\tinput\t\t\tcin;\r
+\tinput\t\t\tadd_sub;\t// 1 = Addition , 0 = Subtraction\r
+\tinput\t [1:0]\tbwd;\r
+\t\r
+\toutput\t[31:0]\tresult;\r
+\toutput\t\t\tcout,overflow;\r
+\t\r
+\treg\t\t [2:0]\tseldat;\r
+\treg\t\t\t\toverflow;\r
+\r
+\twire\t[32:0]\tsumme;\r
+\t\r
+\tassign summe = {1\'b0,dataa} + {1\'b0,(add_sub ? datab : ~datab)} + {32\'d0,cin};\r
+\t\r
+\talways @(bwd or dataa or datab or summe)\r
+\t\tcase (bwd)\r
+\t\t  2\'b00   : seldat = {summe[7], dataa[7], datab[7]};\r
+\t\t  2\'b01   : seldat = {summe[15],dataa[15],datab[15]};\r
+\t\t  default : seldat = {summe[31],dataa[31],datab[31]};\r
+\t\tendcase\r
+\t\t  \r
+\talways @(seldat or add_sub)\r
+\t\tcase (seldat[1:0])\r
+\t\t  2\'b00 : overflow = add_sub ?  seldat[2] : 1\'b0;\r
+\t\t  2\'b01 : overflow = add_sub ? 1\'b0 :  seldat[2];\r
+\t\t  2\'b10 : overflow = add_sub ? 1\'b0 : ~seldat[2];\r
+\t\t  2\'b11 : overflow = add_sub ? ~seldat[2] : 1\'b0;\r
+\t\tendcase\r
+\r
+\tassign cout = add_sub ? summe[32] : ~summe[32];\r
+\tassign result = summe[31:0];\r
+\t\r
+endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t7. I_PFAD\t\tThe Integer Datapath\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module I_PFAD ( BCLK, BRESET, SFP_DAT, FSR, DP_OUT, SRC1, SRC2, BMASKE, ADDR, MRESULT, OPCODE, BWD, FL, SP_CMP, DP_CMP, LD_OUT,\r
+\t\t\t\tWREN, WRADR, RDAA, DETOIP, BITSEL, OVF_BCD, DISP, RWVFLAG, DSR, I_OUT, PSR, BMCODE, OV_FLAG, ACB_ZERO, STRING);\r
+\r
+\tinput\t\t\tBCLK,BRESET;\r
+\tinput\t[31:0]\tSFP_DAT,FSR,DP_OUT;\r
+\tinput\t[31:0]\tSRC1,SRC2;\r
+\tinput\t[31:0]\tBMASKE;\r
+\tinput\t[31:0]\tADDR;\r
+\tinput\t[63:0]\tMRESULT;\r
+\tinput\t [7:0]\tOPCODE;\r
+\tinput\t [1:0]\tBWD;\r
+\tinput\t\t\tFL;\r
+\tinput\t [2:0]\tSP_CMP;\r
+\tinput\t [2:0]\tDP_CMP;\r
+\tinput\t\t\tLD_OUT;\r
+\tinput\t\t\tWREN;\r
+\tinput\t [5:0]\tWRADR;\r
+\tinput\t [7:0]\tRDAA;\r
+\tinput\t[11:0]\tDETOIP;\r
+\tinput\t [2:0]\tBITSEL;\r
+\tinput\t [3:0]\tOVF_BCD;\r
+\tinput\t [4:0]\tDISP;\r
+\tinput\t\t\tRWVFLAG;\r
+\tinput\t [3:0]\tDSR;\r
+\t\r
+\toutput\t[31:0]\tI_OUT;\r
+\toutput\t[11:0]\tPSR;\r
+\toutput\t [6:0]\tBMCODE;\t// ROM Address for BITMASK\r
+\toutput\treg\t\tOV_FLAG;\r
+\toutput\t\t\tACB_ZERO;\r
+\toutput\t [4:0]\tSTRING;\r
+\t\r
+\treg\t\t[31:0]\tI_OUT;\r
+\treg\t\t[31:0]\tpfad_7,pfad_6,pfad_8,pfad_4a;\r
+\twire\t[31:0]\tpfad_4,pfad_5,pfad_11;\r
+\t\r
+\treg\t\t[31:0]\tbwd_daten1,bwd_daten2;\r
+\twire\t[31:0]\taddsub_q;\r
+\r
+\t// +++++++++++++  Global Output Multiplexer  ++++++++++++++++++++++++++++\r
+\t\r
+\talways @(OPCODE or pfad_4 or pfad_5 or pfad_6 or pfad_7 or pfad_8 or DP_OUT or FL or SFP_DAT or FSR or pfad_11)\r
+\t\tcasex (OPCODE[7:3])\r
+\t\t  5\'b0100_x : I_OUT = pfad_4;\r
+\t\t  5\'b0101_x : I_OUT = pfad_5;\t// String opcodes\r
+\t\t  5\'b0110_x : I_OUT = pfad_6;\t\r
+\t\t  5\'b0111_x : I_OUT = pfad_7;\r
+\t\t  5\'b1000_x : I_OUT = pfad_8;\r
+\t\t  5\'b1001_0 : I_OUT = DP_OUT;\t// SP_FPU has higher priority ! LFSR has no output\r
+\t\t  // SFSR : ROUND,TRUNC,FLOOR Integer Data : SP or DP Block\r
+\t\t  5\'b1001_1 : I_OUT = (OPCODE[2:1] == 2\'b10) ? FSR : (FL ? SFP_DAT : DP_OUT);\t\r
+\t\t  5\'b1011_x : I_OUT = pfad_11;\r
+\t\t  5\'b1101_x : I_OUT = DP_OUT;\t// Coprocessor\r
+\t\t  default\t: I_OUT = 32\'hxxxx_xxxx; \t// don\'t care\r
+\t\tendcase\r
+\t\t\r
+\t// ++++++++++++++ PSR Register :\t I  P S U / N Z F V - L T C\r
+\t//\t\t\t\t\t\t\t\t\t11 10 9 8   7 6 5 4 3 2 1 0\r
+\t\r
+\treg\t\t [3:0]\tpsr_high;\r
+\treg\t\t [7:0]\tpsr_low,psr_new;\r
+\treg\t\t[11:0]\tpush_psr;\t// true Register\r
+\treg\t\t[11:0]\tcalc_psr;\t// only verilog case\r
+\treg\t\t [1:0]\tnl_int;\r
+\t\r
+\twire\t\t\tld_psr_l,ld_psr_h,up_psr;\r
+\twire\t\t\tcmp_op,bit_op,ari_op,neg_op,ffs_op,str_op,chk_op,abs_op,rwv_op;\r
+\twire\t [1:0]\tfp_nz;\r
+\twire\t\t\tf_flag,z_flag;\r
+\twire\t [1:0]\tnl_flags;\r
+\twire\t\t\tover_flow,cy_out;\r
+\twire\t\t\tffs_flag;\t// FLAG result of FFS\r
+\twire\t\t\tchk_flag;\t// FLAG result of CHECK\r
+\twire\t\t\tsave_psr,pop_psr;\r
+\twire\t [4:0]\tselbits;\r
+\t// Bits from DETOIP;\r
+\twire\t\t\tcmps_op,ph_match,until,kill_opt,inss_op,exin_cmd,extract,bit_reg,kurz_st,dw_info,acb_reg,t2p;\r
+\twire\t\t\tbcd_op,bcd_carry;\r
+\t\r
+\tassign cmps_op\t= DETOIP[11];\t// for CMPS\r
+\tassign ph_match\t= DETOIP[10];\t// MATCH phase\r
+\tassign until\t= DETOIP[9];\t// UNITL Flag for String\r
+\tassign kill_opt\t= DETOIP[8];\t// optimized execution of MOVS/MOVM\r
+\tassign inss_op\t= DETOIP[7];\t// 1=INSS\r
+\tassign exin_cmd = DETOIP[6];\t// for EXT/INS\r
+\tassign extract  = DETOIP[5] & exin_cmd;\t// 1=EXT\r
+\tassign bit_reg  = DETOIP[4];\t// for Bit opcodes\r
+\tassign kurz_st  = DETOIP[3];\t// for MOVM/CMPM\r
+\tassign dw_info  = DETOIP[2];\t// at ADJSPi is SP=SRC2 always 32 Bit\r
+\tassign acb_reg  = DETOIP[1];\t// suppresses Carry-Set at ACB\r
+\tassign t2p\t    = DETOIP[0];\t// Pulse to Load Trace-Bit to Pending-Trace-Bit\r
+\t\r
+\tassign bcd_op    = OVF_BCD[1];\t// ADDPi,SUBPi - from DP_FPU\r
+\tassign bcd_carry = OVF_BCD[0];\r
+\t\r
+\tassign ld_psr_l = ((WRADR == 6\'h1D) | (WRADR == 6\'h10)) & WREN;\t// Register PSR & UPSR\r
+\tassign ld_psr_h =  (WRADR == 6\'h1D) & (BWD != 2\'b00) & WREN;\t// Register PSR\r
+\t// LD_OUT[1] is coming out of DECODER for this purpose\r
+\tassign up_psr = bcd_op | ((cmp_op | bit_op | ari_op | neg_op | ffs_op | chk_op) & LD_OUT);\r
+\t\r
+\tassign cmp_op = (OPCODE == 8\'h41) | ((OPCODE == 8\'hB2) & (FL ? ~SP_CMP[2] : ~DP_CMP[2]));\t// CMPi or (CMPf & ~NAN)\r
+\tassign bit_op =   ((OPCODE[7:4] == 4\'h6) & ((~OPCODE[3] & OPCODE[1]) | OPCODE[3:0] == 4\'hE))\t// the last term is for IBIT\r
+\t\t\t\t\t| (OPCODE == 8\'h4D) | str_op | rwv_op;\t// TBIT or CMPS or RDVAL/WRVAL\r
+\tassign ari_op = (OPCODE[7:4] == 4\'h4) & (OPCODE[1:0] == 2\'b0) & ~dw_info;\t// ADDi,ADDCi,SUBi,SUBCi - special case ADJSPi no flags\r
+\tassign neg_op = (OPCODE[7:4] == 4\'h6) & (OPCODE[3] & (OPCODE[1:0] == 2\'b0));\t// ABSi,NEGi  \r
+\tassign ffs_op = (OPCODE \t == 8\'h85);\t// FFS\r
+\tassign chk_op = (OPCODE \t == 8\'h83);\t// CHECK\r
+\tassign str_op = (OPCODE[7:4] == 4\'h5) & (OPCODE[3:2] == 2\'b0) & ~kurz_st;\t// String-""S"" opcodes : F-Flag to 0, at start always\r
+\tassign abs_op = (OPCODE \t == 8\'h6C);\t// ABSi : Carry is not affected !\r
+\tassign rwv_op = (OPCODE[7:4] == 4\'hE) & (OPCODE[3:1] == 3\'b0);\t// RDVAL + WRVAL\r
+\t\r
+\talways @(bwd_daten1 or bwd_daten2 or addsub_q)\t// SRC1 > SRC2 ?\r
+\t\tcase ({bwd_daten2[31],bwd_daten1[31]})\r
+\t\t  2\'b00 : nl_int = {addsub_q[31],addsub_q[31]};\t// MSB = N , LSB = L\r
+\t\t  2\'b01 : nl_int = {   1\'b0     ,    1\'b1    };\r
+\t\t  2\'b10 : nl_int = {   1\'b1     ,    1\'b0    };\r
+\t\t  2\'b11 : nl_int = {addsub_q[31],addsub_q[31]};\r
+\t\tendcase\r
+\t\t\r
+\tassign ACB_ZERO = (addsub_q == 32\'h0);\t// is used for ACBi opcode too\r
+\tassign f_flag = str_op ? 1\'b0 : (rwv_op ? RWVFLAG : (bit_op ? SRC2[selbits] : (acb_reg ? PSR[5] : over_flow)));\r
+\tassign fp_nz  = FL ? SP_CMP[1:0] : DP_CMP[1:0];\r
+\tassign z_flag =   OPCODE[1] ?  fp_nz[0] : ACB_ZERO;\r
+\tassign nl_flags = OPCODE[1] ? {fp_nz[1],1\'b0} : nl_int;\r
+\t\r
+\talways @(*)\t// Bits : N Z F V - L T C\r
+\t\tcasex ({cmp_op,bcd_op,bit_op,(ffs_op | chk_op)})\r
+\t\t  4\'b0000 : psr_new = {PSR[7:6],          f_flag,PSR[4:1],((acb_reg | abs_op) ? PSR[0] : cy_out)};\t// arithmetic Op : CY and F\r
+\t\t  4\'b0001 : psr_new = {PSR[7:6],(ffs_op ? ffs_flag : chk_flag),PSR[4:0]};\t\t// FFS or CHECK\r
+\t\t  4\'b001x : psr_new = (cmps_op & str_op) ?\r
+\t\t\t\t\t\t\t  {2\'b01,             f_flag,PSR[4:3],1\'b0,PSR[1:0]}\t\t// Init CMPS\r
+\t\t\t\t\t\t\t: {PSR[7:6],          f_flag,PSR[4:0]};\t\t\t\t\t\t// Bit opcode\r
+\t\t  4\'b01xx : psr_new = {PSR[7:6],          1\'b0,  PSR[4:1],bcd_carry};\t\t\t// BCD opcode\r
+\t\t  4\'b1xxx : psr_new = ph_match ?\r
+\t\t\t\t\t\t\t  {PSR[7:6], ~(ACB_ZERO ^ until), PSR[4:0]}\t\t\t\t\t// Until/While Option at String-""S"" opcodes\r
+\t\t\t\t\t\t\t: {nl_flags[1],z_flag,PSR[5:3],   nl_flags[0],PSR[1:0]};\t// CMP f or i\r
+\t\tendcase\r
+\t\t\r
+\talways @(save_psr or pop_psr or OPCODE or PSR or SRC1)\r
+\t\tcasex ({save_psr,pop_psr,OPCODE[6],OPCODE[2]})\r
+\t\t  4\'b10xx : calc_psr = PSR & {~OPCODE[0],11\'h0ED};\t// clear P S U V T and the I-Bit at Interrupt & ABORT\r
+\t\t  4\'b11xx : calc_psr = SRC1[27:16];\r
+\t\t  4\'b0x00 : calc_psr = PSR & ~SRC1[11:0];\t// BICPSR : Opcode = h32\r
+\t\t  4\'b0x01 : calc_psr = PSR |  SRC1[11:0];\t// BISPSR\t\t\t h36\r
+\t\t  default : calc_psr = SRC1[11:0];\t\t\t// LPR PSR\t\t\t h76\r
+\t\tendcase\r
+\r
+\t// Special case Exception Handling : Code x\'89-x\'8F\r
+\tassign save_psr = (OPCODE[7:3] == 5\'b1000_1);\r
+\tassign pop_psr  = (OPCODE[2:0] == 3\'b000);\r
+\r
+\talways @(posedge BCLK or negedge BRESET)\t// central memory for PSR low\r
+\t\tif (!BRESET) psr_low <= 8\'h0;\r
+\t\t  else\r
+\t\t  begin\r
+\t\t\tif (ld_psr_l || save_psr) psr_low <= calc_psr[7:0];\r
+\t\t\t  else\r
+\t\t\t\tif (up_psr) psr_low <= psr_new;\t// the Status result of a normal opcode\r
+\t\t  end\r
+\t\t  \r
+\talways @(posedge BCLK or negedge BRESET)\t// central memory for PSR high\r
+\t\tif (!BRESET) psr_high <= 4\'h0;\r
+\t\t  else\r
+\t\t  begin\r
+\t\t\tif (ld_psr_h || save_psr)  psr_high <= calc_psr[11:8];\t// only at WORD access\r
+\t\t\t  else\t// t2p : copy T-Bit into P-Bit at the beginning of opcode\r
+\t\t\t\tif (t2p) psr_high <= {psr_high[3],psr_low[1],psr_high[1:0]};\r
+\t\t  end\r
+\t\t  \r
+\t// Register for storage of PSR at Entry of Exception\r
+\talways @(posedge BCLK) if (save_psr) push_psr <= {PSR[11],(~OPCODE[1] & PSR[10]),PSR[9:0]};\t// P-Flag modified\r
+\t\t\r
+\tassign PSR = {psr_high,psr_low};\r
+\t\r
+\t// ++++++++++++++  Overflow Detection  ++++++++++++++++++++++++++++++++++++++\r
+\r
+\treg\t\t\t\tovf_mul,ovf_ash;\r
+\twire\t[31:0]\tshdat;\r
+\t\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) OV_FLAG <= 1\'b0;\r
+\t\t  else\r
+\t\t\tif (OVF_BCD[3]) OV_FLAG <= OVF_BCD[2];\t// DEI,QUO,DIV\r
+\t\t\t  else\r
+\t\t\t\tif (LD_OUT)\r
+\t\t\t\t  case (OPCODE)\r
+\t\t\t\t\t 8\'h78 : OV_FLAG <= ovf_mul;\r
+\t\t\t\t\t 8\'h61 : OV_FLAG <= ovf_ash;\r
+\t\t\t\t\t 8\'h40 : OV_FLAG <= over_flow & acb_reg;\t// ADD Opcode at ACB\r
+\t\t\t\t   default : OV_FLAG <= 1\'b0;\r
+\t\t\t\t  endcase\r
+\t\t\r
+\talways @(BWD or MRESULT)\r
+\t\tcasex (BWD)\r
+\t\t\t2\'b00 : ovf_mul = ~((MRESULT[15:7]  ==  9\'d0) | (MRESULT[15:7]  ==  9\'h1FF));\r
+\t\t\t2\'b01 : ovf_mul = ~((MRESULT[31:15] == 17\'d0) | (MRESULT[31:15] == 17\'h1FFFF));\r
+\t\t  default : ovf_mul = ~((MRESULT[63:31] == 33\'d0) | (MRESULT[63:31] == 33\'h1FFFFFFFF));\r
+\t\tendcase\r
+\t\t\r
+\talways @(BWD or SRC2 or shdat)\r
+\t\tcasex (BWD)\r
+\t\t\t2\'b00 : ovf_ash = (SRC2[7]  != shdat[7]);\r
+\t\t\t2\'b01 : ovf_ash = (SRC2[15] != shdat[15]);\r
+\t\t  default : ovf_ash = (SRC2[31] != shdat[31]);\r
+\t\tendcase\r
+\t\r
+\t// ++++++++++++++ Format 4 Opcodes : Basic Integer Opcodes, MOVi is special case  +++++++++++++\r
+\r
+\treg\t\t\t\tcy_in;\r
+\treg\t\t\t\tget_psr,rd_psr,rd_dsr,get_mod;\r
+\twire\t\t\tadd_flag;\r
+\t\r
+\talways @(BWD or SRC1)\r
+\t\tcasex (BWD)\r
+\t\t\t2\'b00 : bwd_daten1 = {{24{SRC1[7]}}, SRC1[7:0]};\t// Sign Extension\r
+\t\t\t2\'b01 : bwd_daten1 = {{16{SRC1[15]}},SRC1[15:0]};\r
+\t\t  default : bwd_daten1 = SRC1;\r
+\t\tendcase\r
+\t\t\r
+\tassign add_flag = ~OPCODE[3] & ~OPCODE[1] & ~OPCODE[0];\t// Only ADDi and ADDCi otherwise subtract in SCHALE\r
+\t\r
+\talways @(PSR or OPCODE)\t// more effort due to ABSi und NEGi : Format 6\r
+\t\tcasex ({OPCODE[5],OPCODE[3:2]})\r
+\t\t   3\'b000 : cy_in = OPCODE[0];\t// ADD + CMP\r
+\t\t   3\'b001 : cy_in =  PSR[0];\t// ADDC\r
+\t\t   3\'b011 : cy_in = ~PSR[0];\t// SUBC\r
+\t\t  default : cy_in = 1\'b1;\t\t// SUB + ABS + NEG : BORROW must be 1 for normal Adder \r
+\t\tendcase\r
+\t\t\r
+\tSCHALE     addsub_ipfad  (.dataa(bwd_daten2), .datab(bwd_daten1), .cin(cy_in), .add_sub(add_flag), .bwd(BWD),\r
+\t\t\t\t\t\t\t  .result(addsub_q), .cout(cy_out), .overflow(over_flow) );\r
+\t\t\t\t\t\t\t  \r
+\talways @(posedge BCLK) get_psr <= (RDAA == 8\'h9D) | (RDAA == 8\'h90) | (RDAA == 8\'h93);\t// PSR or US or DSR is read\r
+\talways @(posedge BCLK) rd_psr  <= (RDAA[1:0] == 2\'b01);\r
+\talways @(posedge BCLK) rd_dsr  <= (RDAA[1:0] == 2\'b11);\r
+\talways @(posedge BCLK) get_mod <= (RDAA == 8\'h9F);\r
+\t\r
+\talways @(OPCODE or SRC1 or SRC2 or get_psr or rd_psr or rd_dsr or get_mod or DSR or PSR or ADDR)\r
+\t\tcasex (OPCODE[3:1])\r
+\t\t   3\'b001 : pfad_4a = SRC2 & ~SRC1;\t// BIC\r
+\t\t   3\'bx10 : pfad_4a = get_psr ? {({4{rd_dsr}} & DSR),16\'d0,({4{rd_psr}} & PSR[11:8]),({8{~rd_dsr}} & PSR[7:0])}\t// MOV\r
+\t\t\t\t\t\t\t\t\t  : (get_mod ? {16\'d0,SRC1[15:0]} : SRC1);\r
+\t\t   3\'b011 : pfad_4a = SRC2 |  SRC1;\t// OR\r
+\t\t   3\'b101 : pfad_4a = SRC2 &  SRC1;\t// AND\r
+\t\t   3\'b111 : pfad_4a = SRC2 ^  SRC1;\t// XOR\r
+\t\t  default : pfad_4a = ADDR;\t\t\t// ADDR, comes from ADDR_UNIT\r
+\t\tendcase\r
+\t\t\r
+\tassign pfad_4 = (OPCODE[1:0] == 2\'b00) ? addsub_q : pfad_4a;\t// ADD,ADDC,SUB,SUBC have extra path\r
+\t\r
+\t// ++++++++++++++ Format 5 Opcodes : Strings MOVS , CMPS und SKPS  +++++++++++++++++++++++++++++++\r
+\r
+\treg\t\t[11:0]\tspointer,dpointer;\r
+\treg\t\t [9:0]\ttodo;\r
+\treg\t\t [9:4]\ttodo_reg;\r
+\treg\t\t\t\tdis_opt;\r
+\twire\t[31:0]\tdiff_poi;\r
+\twire\t\t\tmehr,weiter,op_str,no_opt;\r
+\t\r
+\tassign op_str = (OPCODE[7:3] == 5\'b0101_0);\r
+\t\r
+\tassign diff_poi = SRC2 - SRC1;\t// Special Case\r
+\t\r
+\talways @(posedge BCLK) if (op_str && OPCODE[2]) dis_opt <= (diff_poi[31:3] == 29\'d0);\r
+\t\r
+\t// This logic is for detection if an accelerated MOVS/MOVM inside a page is possible - Backward is not possible\r
+\talways @(posedge BCLK)\r
+\t\tif (op_str)\r
+\t\t\tbegin\r
+\t\t\t\tspointer <= OPCODE[2] ? SRC1[11:0] : (spointer + {8\'h00,todo[3:0]});\t// Source\r
+\t\t\t\tdpointer <= OPCODE[2] ? SRC2[11:0] : (dpointer + {8\'h00,todo[3:0]});\t// Destination\r
+\t\t\tend\r
+\t\t\t\r
+\tassign no_opt = OPCODE[1] | ((spointer[11:3] == 9\'h1FF) & (spointer[2:0] != 3\'b000))\r
+\t\t\t\t   | kill_opt | ((dpointer[11:3] == 9\'h1FF) & (dpointer[2:0] != 3\'b000))\r
+\t\t\t\t   | dis_opt;\r
+\t\t\t\r
+\tassign pfad_5 = SRC1 - {28\'h0,todo_reg[7:4]};\r
+\r
+\tassign mehr = (pfad_5[31:4] != 28\'h0);\r
+\t\r
+\talways @(no_opt or BWD or mehr or pfad_5)\r
+\t\tcasex ({no_opt,BWD,mehr,pfad_5[3:0]})\r
+\t\t  8\'b000_1xxxx : todo = 10\'h388;\t// Byte\r
+\t\t  8\'b000_01xxx : todo = 10\'h388;\r
+\t\t  8\'b000_001xx : todo = 10\'h244;\r
+\t\t  8\'b000_0001x : todo = 10\'h122;\r
+\t\t  8\'b000_00001 : todo = 10\'h011;\r
+\t\t//\r
+\t\t  8\'b001_1xxxx : todo = 10\'h348;\t// Word\r
+\t\t  8\'b001_01xxx : todo = 10\'h348;\r
+\t\t  8\'b001_001xx : todo = 10\'h348;\r
+\t\t  8\'b001_0001x : todo = 10\'h224;\r
+\t\t  8\'b001_00001 : todo = 10\'h112;\r
+\t\t//\r
+\t\t  8\'b01x_1xxxx : todo = 10\'h328;\t// DWord\r
+\t\t  8\'b01x_01xxx : todo = 10\'h328;\r
+\t\t  8\'b01x_001xx : todo = 10\'h328;\r
+\t\t  8\'b01x_0001x : todo = 10\'h328;\r
+\t\t  8\'b01x_00001 : todo = 10\'h214;\r
+\t\t//\r
+\t\t  8\'b100_xxxxx : todo = 10\'h011;\t// the opcodes CMPS and SKPS work on a single element\r
+\t\t  8\'b101_xxxxx : todo = 10\'h112;\r
+\t\t  8\'b11x_xxxxx : todo = 10\'h214;\r
+\t\t  default\t   : todo = 10\'hxxx;\r
+\t\tendcase\r
+\t\r
+\talways @(posedge BCLK) if (op_str) todo_reg <= {todo[9:8],(OPCODE[2] ? 4\'d0 : todo[7:4])};\t// store for next phase 51\r
+\t\t  \r
+\tassign weiter = mehr | (pfad_5[3:0] != 4\'h0);\r
+\t\r
+\tassign STRING = {1\'b0,ACB_ZERO,weiter,( op_str ? todo[9:8] : todo_reg[9:8] )};\t// ACB_ZERO is delayed 1 cycle extern\r
+\t\r
+\t// +++++++++++++  Format 6 opcodes : ADDP + SUBP are done in DP_FPU  ++++++++++++++++++++\r
+\r
+\twire\t\t\trot,ash,lsh,eis_op;\r
+\twire\t [7:0]\tsh_count;\r
+\twire\t [4:0]\tshcode;\t\t// comes from SHIFTER\r
+\t\r
+\treg\t\t [4:0]\tdisp_reg;\t// for EXT/INS\r
+\treg\t\t [2:0]\toffs_reg;\t// for INSS\r
+\twire\t\t\texin_op,exin_op2;\r
+\twire\t [4:0]\tshval_ei;\r
+\twire\t [7:0]\tsh_exin;\r
+\t\r
+\tassign rot = (OPCODE[3:0] == 4\'h0);\r
+\tassign ash = (OPCODE[3:0] == 4\'h1);\r
+\tassign lsh = (OPCODE[3:1] == 3\'b010);\t// 5 is LSH , but 4 is Trap(UND) and is used for right-shift of Offset !\r
+\t\r
+\tassign eis_op = (OPCODE == 8\'h73) | (OPCODE[7] & ~OPCODE[1] & inss_op);\t// EXTSi | INSSi at OPCODE=80h\r
+\tassign exin_op  = exin_cmd & (OPCODE[7:4] == 4\'h8);\t\t\t\t// identifies EXT/INS\r
+\tassign exin_op2 = (exin_cmd | inss_op) & (OPCODE[7:4] == 4\'h6);\t// identifies LSH\r
+\r
+\talways @(posedge BCLK) disp_reg <= DISP;\t// at EXT the path via ADDR is already used for DEST !!!\r
+\talways @(posedge BCLK) if (OPCODE[7]) offs_reg <= SRC1[7:5];\t// for INSS , OPCODE=80h\r
+\t\r
+\t// Byte for external Bit source, Double for Register\r
+\tassign selbits = (bit_reg | eis_op | exin_op) ? (exin_op ? disp_reg : SRC1[4:0]) : {2\'b00,BITSEL};\r
+\t\r
+\tassign shval_ei = inss_op ? {2\'b00,offs_reg} : (bit_reg ? SRC1[4:0] : {2\'b00,SRC1[2:0]});\r
+\tassign sh_exin[4:0] = extract ? (5\'d0 - shval_ei) : shval_ei;\t\t// EXT : right shift, INS : left shift\r
+\tassign sh_exin[7:5] = (shval_ei == 5\'d0) ? 3\'b000 : {3{extract}};\t// Special case : 0 has no negativ s'b""ign !\r
+\r
+\t// LSH shift by 16 bit to right\r
+\tassign sh_count = (OPCODE[3:0] == 4'h4) ? 8'hF0 : (exin_op2 ? sh_exin : SRC1[7:0]);\r
+\t\r
+\tassign BMCODE = (bit_op | eis_op | exin_op) ? {(eis_op | exin_op),(bit_op | exin_op),selbits} : {2'b00,shcode};\r
+\t\r
+\tSHIFTER  shift_inst (.MASKE(BMASKE), .ROT(rot), .ASH(ash), .LSH(lsh), .SH_DAT(SRC2), .SH_VAL(sh_count),\r
+\t\t\t\t\t\t .MASK_SEL(shcode), .SIZE(BWD), .SH_OUT(shdat) );\r
+\t\r
+\talways @(BWD or SRC2 or neg_op or dw_info)\r
+\t\tcasex ({neg_op,(dw_info | BWD[1]),BWD[0]})\t\t\t\t// special case ADJSPi\r
+\t\t   3'b000 : bwd_daten2 = {{24{SRC2[7]}}, SRC2[7:0]};\t// Sign Extension\r
+\t\t   3'b001 : bwd_daten2 = {{16{SRC2[15]}},SRC2[15:0]};\r
+\t\t   3'b1xx : bwd_daten2 = 32'h0;\t\t\t\t\t\t\t// is used for ABSi and NEGi\r
+\t\t  default : bwd_daten2 = SRC2;\r
+\t\tendcase\r
+\t\t\r
+\talways @(OPCODE or SRC2 or BMASKE or addsub_q or bwd_daten1 or SRC1 or shdat or DP_OUT)\r
+\t\tcasex (OPCODE[3:0])\r
+\t\t  4'b001x : pfad_6 = SRC2 & ~BMASKE;\t\t// CBIT & CBITI\r
+\t\t  4'b011x : pfad_6 = SRC2 |  BMASKE;\t\t// SBIT & SBITI\r
+\t\t  4'b1000 : pfad_6 = addsub_q;\t\t\t\t// NEG\r
+\t\t  4'b1001 : pfad_6 = {SRC1[31:1],~SRC1[0]};\t// NOT\r
+\t\t  4'b1010 : pfad_6 = SRC1;\t\t\t\t\t// Special case 6A : not used normal -> op_lmr !\r
+\t\t  4'b1100 : pfad_6 = bwd_daten1[31] ? addsub_q : SRC1;\t// ABS\r
+\t\t  4'b1101 : pfad_6 = ~SRC1;\t\t\t\t\t// COM\r
+\t\t  4'b1110 : pfad_6 = SRC2 ^  BMASKE;\t\t// IBIT\r
+\t\t  4'b1x11_: pfad_6 = DP_OUT;\t\t\t\t// ADDP + SUBP\r
+\t\t  default : pfad_6 = shdat;\t\t\t\t\t// Result of Barrelshifter\r
+\t\tendcase\r
+\t\t\r
+\t// ++++++++++++++  Format 7 : MUL  +++++++++++++++++++++++\r
+\r
+\t// This Condition-Code Decoder is written twice ... see DECODER\r
+\t\r
+\treg\t\t\t\tsc_bit;\r
+\twire\t\t\tsc_negativ,sc_zero,sc_flag,sc_larger,sc_carry_psr;\r
+\t\r
+\tassign sc_negativ\t= PSR[7];\r
+\tassign sc_zero      = PSR[6];\r
+\tassign sc_flag\t\t= PSR[5];\r
+\tassign sc_larger\t= PSR[2];\r
+\tassign sc_carry_psr = PSR[0];\r
+\t\r
+\talways @(SRC1 or sc_zero or sc_carry_psr or sc_larger or sc_negativ or sc_flag)\r
+\t\tcase (SRC1[3:0])\r
+\t\t  4'h0 : sc_bit =  sc_zero;\t\t\t// EQual\r
+\t\t  4'h1 : sc_bit = ~sc_zero;\t\t\t// Not Equal\r
+\t\t  4'h2 : sc_bit =  sc_carry_psr;\t// Carry Set\r
+\t\t  4'h3 : sc_bit = ~sc_carry_psr;\t// Carry Clear\r
+\t\t  4'h4 : sc_bit =  sc_larger;\t\t// Higher\r
+\t\t  4'h5 : sc_bit = ~sc_larger;\t\t// Lower or Same\r
+\t\t  4'h6 : sc_bit =  sc_negativ;\t\t// Greater Than\r
+\t\t  4'h7 : sc_bit = ~sc_negativ;\t\t// Less or Equal\r
+\t\t  4'h8 : sc_bit =  sc_flag;\t\t\t// Flag Set\r
+\t\t  4'h9 : sc_bit = ~sc_flag;\t\t\t// Flag Clear\r
+\t\t  4'hA : sc_bit = ~sc_larger  & ~sc_zero;\t// LOwer\r
+\t\t  4'hB : sc_bit =  sc_larger  |  sc_zero;\t// Higher or Same\r
+\t\t  4'hC : sc_bit = ~sc_negativ & ~sc_zero;\t// Less Than\r
+\t\t  4'hD : sc_bit =  sc_negativ |  sc_zero;\t// Greater or Equal\r
+\t\t  4'hE : sc_bit = 1'b1;\t\t\t\t// True\r
+\t\t  4'hF : sc_bit = 1'b0;\t\t\t\t// False\r
+\t\tendcase\r
+\t\t\r
+\treg\t\t [3:0]  bytes2anz;\r
+\twire\t[23:0]\tand_src1;\r
+\twire\t[31:0]\tmovxz_dat;\r
+\twire\t [4:0]\tkurz_anz;\r
+\twire\t[31:0]\text_sh4,ext_sh2;\r
+\t\r
+\tassign and_src1  = {{16{BWD[1]}},{8{BWD[0]}}} & SRC1[31:8];\t// for MOVZ\r
+\t\r
+\tassign movxz_dat = (OPCODE[1] ^ OPCODE[0]) ? {and_src1,SRC1[7:0]} : bwd_daten1;\t// MOVZ.. ?\r
+\t\r
+\talways @(ADDR or BWD)\r
+\t\tcasex (BWD[1:0])\r
+\t\t  2'b00 : bytes2anz = ADDR[3:0];\r
+\t\t  2'b01 : bytes2anz = {1'b0,ADDR[3:1]};\r
+\t\t  2'b1x : bytes2anz = {2'b0,ADDR[3:2]};\r
+\t\tendcase\r
+\t\t\r
+\tassign kurz_anz = {1'b0,bytes2anz} + 5'h01;\t// count for MOVM/CMPM\r
+\t\r
+\tassign ext_sh4 = SRC1[7] ? {4'h0,SRC2[31:4]}    : SRC2;\t\t// EXTSi\r
+\tassign ext_sh2 = SRC1[6] ? {2'b0,ext_sh4[31:2]} : ext_sh4;\r
+\t\r
+\talways @(*)\r
+\t\tcasex (OPCODE[3:0])\r
+\t\t  4'b0011 : pfad_7 = (SRC1[5] ? {1'b0,ext_sh2[31:1]} : ext_sh2) & BMASKE;\t// EXTSi\r
+\t\t  4'b01xx : pfad_7 = movxz_dat;\t\t\t// MOVXBW, MOVZBW, MOVZiD, MOVXiD\r
+\t\t  4'b1000 : pfad_7 = MRESULT[31:0];\t\t// MULi\r
+\t\t  4'b1010 : pfad_7 = {27'h0,(kurz_st ? kurz_anz : {4'h0,sc_bit})};\t// SCond or start of MOVM/CMPM\r
+\t\t  default : pfad_7 = DP_OUT;\t\t\t// DIV etc.\r
+\t\tendcase\r
+\t\t\r
+\t// ++++++++++++++  Format 8 : multiple opcodes  +++++++++++++++++++++++\r
+\t\r
+\treg\t\t\t\tchk_p1;\r
+\treg\t\t[31:0]\tins_maske;\r
+\t\r
+\twire\t [4:0]\tffs_out;\r
+\twire\t[15:0]\tlow_bou,upp_bou,zeiger,chk_upp,chk_low;\r
+\twire\t\t\tflag_up,flag_lo;\r
+\t\r
+\tFFS_LOGIK ffs_unit (.SRC1(SRC1), .SRC2(SRC2[4:0]), .BWD(BWD), .FLAG(ffs_flag), .DOUT(ffs_out) );\r
+\t\r
+\t// CHECK : SRC1 are the Bounds\r
+\tassign low_bou = BWD[0] ? SRC1[31:16] : {{8{SRC1[15]}},SRC1[15:8]};\r
+\tassign upp_bou = BWD[0] ? SRC1[15:0]  : {{8{SRC1[7]}}, SRC1[7:0]};\r
+\tassign zeiger  = BWD[0] ? SRC2[15:0]  : {{8{SRC2[7]}}, SRC2[7:0]};\r
+\t\r
+\tassign chk_upp = upp_bou - zeiger;\t// F=1 if upp_bou < zeiger\r
+\tassign chk_low = zeiger - low_bou;\t// F=1 if zeiger < low_bou\r
+\t\r
+\tassign flag_up = (upp_bou[15] == zeiger[15]) ? chk_upp[15] : upp_bou[15];\t// See NL Definition\r
+\tassign flag_lo = (low_bou[15] == zeiger[15]) ? chk_low[15] : zeiger[15];\r
+\t\r
+\talways @(posedge BCLK) chk_p1 <= chk_op & BWD[1];\t// CHECKD needs 2 cycles to execute\r
+\t\r
+\tassign chk_flag = BWD[1] ? (chk_p1 ? (nl_int[1] | psr_low[5]) : nl_int[1]) : (flag_up | flag_lo);\r
+\t\r
+\talways @(posedge BCLK) ins_maske <= shdat;\t// expensive solution in terms of LEs ! \r
+\t\r
+\talways @(*)\r
+\t\tcasex (OPCODE[3:0])\t\t// CVTP (81) has no OPCODE !\r
+\t\t  4'b000x : pfad_8 = (extract ? SRC2 : 32'hFFFF_FFFF) & BMASKE;\t// EXT, the other form is for INS to get the mask\r
+\t\t  4'b0010 : pfad_8 = (SRC1 & ins_maske) | (SRC2 & ~ins_maske);\t// INS ins_maske[] ? SRC1[] : SRC2[]\r
+\t\t  4'b0011 : pfad_8 = BWD[1] ? addsub_q : {16'h0,chk_low};\r
+\t\t  4'b0101 : pfad_8 = {24'hxx_xxxx,3'b000,ffs_out};\r
+\t\t  default : pfad_8 = {4'hx,push_psr,SRC1[15:0]};\t// Opcode x'87-x'8F is used at CXP and therefore in Exception-Processing\r
+\t\tendcase\r
+\t\t\r
+\t// ++++++++++++++ Format 11 : Floating-Point Datapath  +++++++++++++++++++++++++++++++\r
+\r
+\tassign pfad_11 = (OPCODE[1:0] == 2'b01) ? \r
+\t\t\t\t\t\t{((OPCODE[3:2] == 2'b11) ? 1'b0 : (SRC1[31] ^ OPCODE[2])),SRC1[30:0]}\t// ABSf , NEGf + MOVf\r
+\t\t\t\t\t\t\t\t\t\t\t: DP_OUT;\r
+\t \r
+endmodule\r
+"
+"module ICAP_config
+  (
+   input        fastclk,
+   output [7:0] test,
+
+   // DIP switches in and out
+   input [3:0]  sw_in,
+   output [3:0] sw_out,
+
+   // Tube interface
+   input [2:0]  h_addr,
+   input        h_cs_b,
+   inout [7:0]  h_data,
+   input        h_phi2,
+   input        h_rdnw,
+   input        h_rst_b
+  );
+
+   reg          reconfigure_sw_changed = 1'b0;
+   reg          reconfigure_hw_changed = 1'b0;
+   reg          reconfigure = 1'b0;
+   reg  [4:0]   design_num;
+   wire [3:0]   pwr_out;
+   wire         initialized;
+   reg          p_rst_b = 1'b1;
+   reg          h_cs_b1;
+   reg [2:0]    h_addr1;
+   reg          h_rdnw1;
+
+   ICAP_core instance_core
+     (
+      .fastclk(fastclk),
+      .design_num(design_num),
+      .reconfigure(reconfigure),
+      .powerup(1'b0),
+      .sw_in(sw_in),
+      .sw_out(sw_out),
+      .pwr_out(pwr_out),
+      .initialized(initialized),
+      .test(test)
+      );
+
+   always @(posedge fastclk) begin
+      if (!p_rst_b || !h_rst_b) begin
+         reconfigure <= reconfigure_sw_changed || reconfigure_hw_changed;
+      end
+   end
+
+   // Latch control signals on the rising egge of Phi2
+   // (avoids hold time issues, we do the same in the tube)
+   always @(posedge h_phi2) begin
+      h_cs_b1 <= h_cs_b;
+      h_addr1 <= h_addr;
+      h_rdnw1 <= h_rdnw;
+   end
+
+   always @(negedge h_phi2) begin
+      // Mirror the reset bit of register FEE0, and allow this to reconfigure
+      if (!h_cs_b1 && !h_rdnw1 && h_addr1 == 3'b000) begin
+        if (h_data[6] && h_data[7]) begin
+            // Setting the T bit (bit 6) clears all tube registers
+            p_rst_b <= 1'b1;
+        end else if (h_data[5]) begin
+            // Setting the S bit (bit 5) asserts the parasite reset
+            // Clearing the S bit (bit 5) de-asserts the parasite reset
+            p_rst_b <= !h_data[7];
+        end
+      end
+      // Implement a write only register at FEE6 to change the current design
+      if (!h_cs_b1 && !h_rdnw1 && h_addr1 == 3'b110) begin
+         design_num <= h_data[4:0];
+         reconfigure_sw_changed <= 1'b1;
+      end
+      // Detect changes in the DIP Switches, and invoke the multi boot loader as for a power up
+      if (initialized) begin
+         if (sw_in != pwr_out) begin
+            // Someone has moved the hardware DIP switches
+            design_num <= 5'b10000;
+            reconfigure_hw_changed <= 1'b1;
+         end else begin
+            // Someone has moved them back again
+            reconfigure_hw_changed <= 1'b0;
+         end
+      end
+   end
+
+
+endmodule
+"
+"/*
+ *  Integer multiply/divide module for Zet
+ *  Copyright (C) 2008-2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+module zet_muldiv (
+    input  [31:0] x,  // 16 MSb for division
+    input  [15:0] y,
+    output [31:0] o,
+    input  [ 2:0] f,
+    input         word_op,
+    output        cfo,
+    output        ofo,
+    input         clk,
+    output        exc
+  );
+
+  // Net declarations
+  wire as, bs, cfs, cfu;
+  wire [16:0] a, b;
+  wire [33:0] p;
+  wire div0, over, ovf, mint;
+
+  wire [33:0] zi;
+  wire [16:0] di;
+  wire [17:0] q;
+  wire [17:0] s;
+
+  // Module instantiations
+  zet_signmul17 signmul17 (
+    .clk (clk),
+    .a   (a),
+    .b   (b),
+    .p   (p)
+  );
+
+  zet_div_su #(
+    .z_width(34)
+    ) div_su (
+    .clk  (clk),
+    .ena  (1'b1),
+    .z    (zi),
+    .d    (di),
+    .q    (q),
+    .s    (s),
+    .ovf  (ovf)
+  );
+
+  // Sign ext. for imul
+  assign as  = f[0] & (word_op ? x[15] : x[7]);
+  assign bs  = f[0] & (word_op ? y[15] : y[7]);
+  assign a   = word_op ? { as, x[15:0] }
+                       : { {9{as}}, x[7:0] };
+  assign b   = word_op ? { bs, y } : { {9{bs}}, y[7:0] };
+
+  assign zi  = f[2] ? { 26'h0, x[7:0] }
+               : (word_op ? (f[0] ? { {2{x[31]}}, x }
+                               : { 2'b0, x })
+                       : (f[0] ? { {18{x[15]}}, x[15:0] }
+                               : { 18'b0, x[15:0] }));
+
+  assign di  = word_op ? (f[0] ? { y[15], y } : { 1'b0, y })
+                       : (f[0] ? { {9{y[7]}}, y[7:0] }
+                               : { 9'h000, y[7:0] });
+
+  assign o   = f[2] ? { 16'h0, q[7:0], s[7:0] }
+               : (f[1] ? ( word_op ? {s[15:0], q[15:0]}
+                                : {16'h0, s[7:0], q[7:0]})
+                    : p[31:0]);
+
+  assign ofo = f[1] ? 1'b0 : cfo;
+  assign cfo = f[1] ? 1'b0 : !(f[0] ? cfs : cfu);
+  assign cfu = word_op ? (o[31:16] == 16'h0)
+                       : (o[15:8] == 8'h0);
+  assign cfs = word_op ? (o[31:16] == {16{o[15]}})
+                       : (o[15:8] == {8{o[7]}});
+
+  // Exceptions
+  assign over = word_op ? (f[0] ? (q[17:16]!={2{q[15]}})
+                                : (q[17:16]!=2'b0) )
+                        : (f[0] ? (q[17:8]!={10{q[7]}})
+                                : (q[17:8]!=10'h000));
+  assign mint = f[0] & (word_op ? (x==32'h80000000)
+                                : (x==16'h8000));
+  assign div0 = ~|di;
+  assign exc  = div0 | (!f[2] & (ovf | over | mint));
+endmodule
+"
+"// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+// This file is part of the M32632 project\r
+// http://opencores.org/project,m32632\r
+//\r
+// Filename: ALIGNER.v\r
+// Version:  1.0\r
+// Date:     30 May 2015\r
+//\r
+// Copyright (C) 2015 Udo Moeller\r
+// \r
+// This source file may be used and distributed without \r
+// restriction provided that this copyright statement is not \r
+// removed from the file and that any derivative work contains \r
+// the original copyright notice and the associated disclaimer.\r
+// \r
+// This source file is free software; you can redistribute it \r
+// and/or modify it under the terms of the GNU Lesser General \r
+// Public License as published by the Free Software Foundation;\r
+// either version 2.1 of the License, or (at your option) any \r
+// later version. \r
+// \r
+// This source is distributed in the hope that it will be \r
+// useful, but WITHOUT ANY WARRANTY; without even the implied \r
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR \r
+// PURPOSE. See the GNU Lesser General Public License for more \r
+// details. \r
+// \r
+// You should have received a copy of the GNU Lesser General \r
+// Public License along with this source; if not, download it \r
+// from http://www.opencores.org/lgpl.shtml \r
+// \r
+// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\tModules contained in this file:\r
+//\t1. WR_ALINGER\talignes write data to cache and external devices\r
+//\t2. RD_ALINGER\talignes read data for the data path\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t1. WR_ALINGER\talignes write data to cache and external devices\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module WR_ALIGNER ( PACKET, DP_Q, SIZE, WRDATA, ENBYTE );\r
+\r
+\tinput\t [3:0]\tPACKET;\t// [3:2] Paketnumber , [1:0] Startaddress\r
+\tinput\t[63:0]\tDP_Q;\r
+\tinput\t [1:0]\tSIZE;\r
+\toutput\t[31:0]\tWRDATA;\r
+\toutput\t [3:0]\tENBYTE;\r
+\r
+\treg\t\t [3:0]\tENBYTE;\r
+\treg\t\t [7:0]\tdbyte0,dbyte1,dbyte2,dbyte3;\r
+\twire\t\t\tswitch;\r
+\t\r
+// Data packet \t[ B7 ],[ B6 ],[ B5 ],[ B4 ],[ B3 ],[ B2 ],[ B1 ],[ B0 ]\r
+// Address , i.e. 001 : one DWORD\r
+// gives  2 packets : 1. packet             [-B6-----B5-----B4-]\r
+// 2. packet, Address + 4           \t\t\t\t\t\t\t [-B7-]\r
+// Addresse , i.e. 010 : one QWORD\r
+// gives  3 packets : 1. packet             [-B1-----B0-]\r
+// 2. packet, Address + 4 \t\t\t\t\t[-B5-----B4-----B3-----B2-]\r
+// 3. packet, Address + 8 \t\t\t\t\t\t\t\t  [-B7-----B6-]\r
+\r
+//\tSIZE PACKET ADR : Outputbus \r
+//\t\t00\t00\t00\t\t x  x  x B4\r
+//\t\t00\t00\t01\t\t x  x B4  x\r
+//\t\t00\t00\t10\t\t x B4  x  x\r
+//\t\t00\t00\t11\t\tB4  x  x  x\r
+\r
+//\t\t01\t00\t00\t\t x  x B5 B4\r
+//\t\t01\t00\t01\t\t x B5 B4  x\r
+//\t\t01\t00\t10\t\tB5 B4  x  x\r
+//\t\t01\t00\t11\t\tB4  x  x  x\r
+//\t\t01\t10\t11\t\t x  x  x B5\r
+\r
+//\t\t10\t00\t00\t\tB7 B6 B5 B4\r
+//\t\t10\t00\t01\t\tB6 B5 B4  x\r
+//\t\t10\t10\t01\t\t x  x  x B7\r
+//\t\t10\t00\t10\t\tB5 B4  x  x\r
+//\t\t10\t10\t10\t\t x  x B7 B6\r
+//\t\t10\t00\t11\t\tB4  x  x  x\r
+//\t\t10\t10\t11\t\t x B7 B6 B5\r
+\r
+//\t\t11\t00\t00\t\tB3 B2 B1 B0\r
+//\t\t11\t10\t00\t\tB7 B6 B5 B4\r
+//\t\t11\t00\t01\t\tB2 B1 B0  x\r
+//\t\t11\t01\t01\t\tB6 B5 B4 B3\r
+//\t\t11\t10\t01\t\t x  x  x B7\r
+//\t\t11\t00\t10\t\tB1 B0  x  x\r
+//\t\t11\t01\t10\t\tB5 B4 B3 B2\r
+//\t\t11\t10\t10\t\t x  x B7 B6\r
+//\t\t11\t00\t11\t\tB0  x  x  x\r
+//\t\t11\t01\t11\t\tB4 B3 B2 B1\r
+//\t\t11\t10\t11\t\t x B7 B6 B5\r
+\r
+\tassign switch = (SIZE == 2'b11) & (PACKET[3:2] == 2'b00);\r
+\t\r
+\talways @(DP_Q or switch or PACKET)\r
+\t\tcase (PACKET[1:0])\r
+\t\t  2'b00 : dbyte0 =    switch ?   DP_Q[7:0] : DP_Q[39:32];\r
+\t\t  2'b01 : dbyte0 = PACKET[3] ? DP_Q[63:56] : DP_Q[31:24];\r
+\t\t  2'b10 : dbyte0 = PACKET[3] ? DP_Q[55:48] : DP_Q[23:16];\r
+\t\t  2'b11 : dbyte0 = PACKET[3] ? DP_Q[47:40] :  DP_Q[15:8];\r
+\t\tendcase\r
+\t\t\r
+\talways @(DP_Q or switch or PACKET)\r
+\t\tcase (PACKET[1:0])\r
+\t\t  2'b00 : dbyte1 =    switch ?  DP_Q[15:8] : DP_Q[47:40];\r
+\t\t  2'b01 : dbyte1 =    switch ?   DP_Q[7:0] : DP_Q[39:32];\r
+\t\t  2'b10 : dbyte1 = PACKET[3] ? DP_Q[63:56] : DP_Q[31:24];\r
+\t\t  2'b11 : dbyte1 = PACKET[3] ? DP_Q[55:48] : DP_Q[23:16];\r
+\t\tendcase\r
+\t\t\r
+\talways @(DP_Q or switch or PACKET)\r
+\t\tcase (PACKET[1:0])\r
+\t\t  2'b00 : dbyte2 =    switch ? DP_Q[23:16] : DP_Q[55:48];\r
+\t\t  2'b01 : dbyte2 =    switch ?  DP_Q[15:8] : DP_Q[47:40];\r
+\t\t  2'b10 : dbyte2 =    switch ?   DP_Q[7:0] : DP_Q[39:32];\r
+\t\t  2'b11 : dbyte2 = PACKET[3] ? DP_Q[63:56] : DP_Q[31:24];\r
+\t\tendcase\r
+\r
+\talways @(DP_Q or switch or PACKET)\r
+\t\tcase (PACKET[1:0])\r
+\t\t  2'b00 : dbyte3 =    switch ? DP_Q[31:24] : DP_Q[63:56];\r
+\t\t  2'b01 : dbyte3 =    switch ? DP_Q[23:16] : DP_Q[55:48];\r
+\t\t  2'b10 : dbyte3 =    switch ?  DP_Q[15:8] : DP_Q[47:40];\r
+\t\t  2'b11 : dbyte3 =    switch ?   DP_Q[7:0] : DP_Q[39:32];\r
+\t\tendcase\r
+\t\t\r
+\tassign WRDATA = {dbyte3,dbyte2,dbyte1,dbyte0};\r
+\r
+\talways @(SIZE or PACKET)\r
+\t\tcasex ({SIZE,PACKET})\r
+\t\t  6'b00_xx_00 : ENBYTE = 4'b0001;\t// BYTE\r
+\t\t  6'b00_xx_01 : ENBYTE = 4'b0010;\r
+\t\t  6'b00_xx_10 : ENBYTE = 4'b0100;\r
+\t\t  6'b00_xx_11 : ENBYTE = 4'b1000;\r
+\t\t //\r
+\t\t  6'b01_xx_00 : ENBYTE = 4'b0011;\t// WORD\r
+\t\t  6'b01_xx_01 : ENBYTE = 4'b0110;\r
+\t\t  6'b01_xx_10 : ENBYTE = 4'b1100;\r
+\t\t  6'b01_0x_11 : ENBYTE = 4'b1000;\r
+\t\t  6'b01_1x_11 : ENBYTE = 4'b0001;\r
+\t\t //\r
+\t\t  6'b11_xx_00 : ENBYTE = 4'b1111;\t// QWORD\r
+\t\t  6'b11_00_01 : ENBYTE = 4'b1110;\r
+\t\t  6'b11_01_01 : ENBYTE = 4'b1111;\r
+\t\t  6'b11_1x_01 : ENBYTE = 4'b0001;\r
+\t\t  6'b11_00_10 : ENBYTE = 4'b1100;\r
+\t\t  6'b11_01_10 : ENBYTE = 4'b1111;\r
+\t\t  6'b11_1x_10 : ENBYTE = 4'b0011;\r
+\t\t  6'b11_00_11 : ENBYTE = 4'b1000;\r
+\t\t  6'b11_01_11 : ENBYTE = 4'b1111;\r
+\t\t  6'b11_1x_11 : ENBYTE = 4'b0111;\r
+\t\t //\t\r
+\t\t  6'b10_xx_00 : ENBYTE = 4'b1111;\t// DWORD\r
+\t\t  6'b10_0x_01 : ENBYTE = 4'b1110;\r
+\t\t  6'b10_1x_01 : ENBYTE = 4'b0001;\r
+\t\t  6'b10_0x_10 : ENBYTE = 4'b1100;\r
+\t\t  6'b10_1x_10 : ENBYTE = 4'b0011;\r
+\t\t  6'b10_0x_11 : ENBYTE = 4'b1000;\r
+\t\t  6'b10_1x_11 : ENBYTE = 4'b0111;\r
+\t\tendcase\r
+\t\t  \r
+endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t2. RD_ALINGER\talignes read data for the data path\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module RD_ALIGNER ( BCLK, ACC_OK, PACKET, SIZE, REG_OUT, RDDATA, CA_HIT, DP_DI, AUX_QW );\r
+\r
+\tinput\t\t\tBCLK;\r
+\tinput\t\t\tACC_OK;\r
+\tinput\t [3:0]\tPACKET;\t// [3:2] Paketnumber , [1:0] Startaddress\r
+\tinput\t [1:0]\tSIZE;\r
+\tinput\t\t\tREG_OUT;\r
+\tinput\t[31:0]\tRDDATA;\r
+\tinput\t\t\tCA_HIT;\r
+\t\r
+\toutput\t[31:0]\tDP_DI;\r
+\toutput\treg\t\tAUX_QW;\r
+\t\r
+\treg\t\t [6:0]\tenable;\r
+\treg\t\t [7:0]\tdreg_0,dreg_1,dreg_2,dreg_3,dreg_4,dreg_5,dreg_6;\r
+\treg\t\t [7:0]\tout_0,out_1,out_2,out_3;\r
+\t\r
+// RD_ALIGNER principal working : 10 is last packet , 01 is packet in between\r
+\r
+// Not aligned QWORD  : ADR[1:0] = 3 i.e.\r
+// Bytes to datapath  :\t. - . - 4 - 4\r
+// Bytes from memory  :\t1 - 4 - 3 - .\r
+// ACC_DONE\t\t   \t  :\t_______/----\\__\r
+//\t+ 1 cycle\t\t\t\t\t____/--\r
+// at the end 2 cycles lost. ACC_DONE informs the Op-Dec that data is available and sent one clock cycle later\r
+// the LSD of QWORD access. (ACC_DONE -> REG_OUT is happening in ADDR_UNIT.)\r
+//\r
+// SIZE PACKET ADR :\tOutput data \t\t\t\t\t ACC_OK\r
+//\t\t00\t--\t00\t\t x  x  x B0\t\tByte\t\t\t\t1\r
+//\t\t00\t--\t01\t\t x  x  x B1\t\t\t\t\t\t\t1\r
+//\t\t00\t--\t10\t\t x  x  x B2\t\t\t\t\t\t\t1\r
+//\t\t00\t--\t11\t\t x  x  x B3\t\t\t\t\t\t\t1\r
+\r
+//\t\t01\t00\t00\t\t x  x B1 B0\t\tWord\t\t\t\t1\r
+//\t\t01\t00\t01\t\t x  x B2 B1\t\t\t\t\t\t\t1\r
+//\t\t01\t00\t10\t\t x  x B3 B2\t\t\t\t\t\t\t1\r
+//\t\t01\t00\t11\t\tB3  x  x  x\t-> Reg : R4  -  -  -\t0\r
+//\t\t01\t10\t11\t\t x  x B0 R4\t\t\t\t\t\t\t1\r
+\r
+//\t\t10\t00\t00\t\tB3 B2 B1 B0\t\tDWORD\t\t\t\t1\r
+//\t\t10\t00\t01\t\tB3 B2 B1  x\t-> Reg : R6 R5 R4  -\t0\r
+//\t\t10\t10\t01\t\tB0 R6 R5 R4\t\t\t\t\t\t\t1\r
+//\t\t10\t00\t10\t\tB3 B2  x  x -> Reg : R5 R4  -  -\t0\r
+//\t\t10\t10\t10\t\tB1 B0 R5 R4\t\t\t\t\t\t\t1\r
+//\t\t10\t00\t11\t\tB3  x  x  x -> Reg : R4  -  -  -\t0\r
+//\t\t10\t10\t11\t\tB2 B1 B0 R4\t\t\t\t\t\t\t1\r
+\r
+//\t\t11\t00\t00\t\tB3 B2 B1 B0\t\tQWORD\t\t\t\t1\tMSD\r
+//\t\t11\t01\t00\t\tB3 B2 B1 B0\t\tnot out of Reg!\t\t0\tLSD\r
+//\t\t11\t00\t01\t\tB3 B2 B1  x -> Reg : R2 R1 R0  -\t0\r
+//\t\t11\t01\t01\t\tB3 B2 B1 B0 -> Reg : R6 R5 R4 R3\t0\r
+//\t\t11\t10\t01\t\tB0 R6 R5 R4\t\t\t\t\t\t\t1\tMSD\r
+//\tnext cycle:\t\t\tR3 R2 R1 R0\t\t\t\t\t\t\t\tLSD\r
+//\t\t11\t00\t10\t\tB3 B2  x  x -> Reg : R1 R0  -  -\t0\r
+//\t\t11\t01\t10\t\tB3 B2 B1 B0 -> Reg : R5 R4 R3 R2\t0\r
+//\t\t11\t10\t10\t\tB1 B0 R5 R4\t\t\t\t\t\t\t1\tMSD\r
+//\tnext cycle:\t\t\tR3 R2 R1 R0\t\t\t\t\t\t\t\tLSD\r
+//\t\t11\t00\t11\t\tB3  x  x  x -> Reg : R0  -  -  -\t0\r
+//\t\t11\t01\t11\t\tB3 B2 B1 B0 -> Reg : R4 R3 R2 R1\t0\r
+//\t\t11\t10\t11\t\tB2 B1 B0 R4\t\t\t\t\t\t\t1\tMSD\r
+//\tnext cycle:\t\t\tR3 R2 R1 R0\t\t\t\t\t\t\t\tLSD\r
+\r
+// IO_ACCESS QWORD :\r
+//\t\t11\t00\t00\t\tB3 B2 B1 B0 -> Reg : R3 R2 R1 R0\t0\r
+//\t\t11\t01\t00\t\tR3 R2 R1 R0 -> Reg : R3 R2 R1 R0\t1\tMSD\r
+//\tnext cycle:\t\t\tR3 R2 R1 R0\t\t\t\t\t\t\t\tLSD\r
+\r
+\talways @(ACC_OK or SIZE or PACKET)\r
+\t\tcasex ({ACC_OK,SIZE,PACKET})\r
+\t\t  7'b1_xx_0x_00 : enable = 7'b000_1111;\t\r
+\t\t  7'b1_01_0x_11 : enable = 7'b001_0000;\r
+\t\t  7'b1_10_0x_01 : enable = 7'b111_0000;\r
+\t\t  7'b1_10_0x_10 : enable = 7'b011_0000;\r
+\t\t  7'b1_10_0x_11 : enable = 7'b001_0000;\r
+\t\t  7'b1_11_00_01 : enable = 7'b000_0111;\t// QWORD\r
+\t\t  7'b1_11_01_01 : enable = 7'b111_1000;\r
+\t\t  7'b1_11_00_10 : enable = 7'b000_0011;\r
+\t\t  7'b1_11_01_10 : enable = 7'b011_1100;\r
+\t\t  7'b1_11_00_11 : enable = 7'b000_0001;\r
+\t\t  7'b1_11_01_11 : enable = 7'b001_1110;\r
+\t\t  default\t\t: enable = 7'b000_0000;\r
+\t\tendcase\r
+\t\t\r
+// Register for inbetween data: simple multiplexer\r
+\r
+\talways @(posedge BCLK)\r
+\t\tif (enable[0])\r
+\t\t\tcase (PACKET[1:0])\r
+\t\t\t  2'b01 : dreg_0 <= RDDATA[15:8];\r
+\t\t\t  2'b10 : dreg_0 <= RDDATA[23:16];\r
+\t\t\t  2'b11 : dreg_0 <= RDDATA[31:24];\r
+\t\t\tdefault : dreg_0 <= RDDATA[7:0];\r
+\t\t\tendcase\r
+\r
+\talways @(posedge BCLK)\r
+\t\tif (enable[1])\r
+\t\t\tcase (PACKET[1:0])\r
+\t\t\t  2'b01 : dreg_1 <= RDDATA[23:16];\r
+\t\t\t  2'b10 : dreg_1 <= RDDATA[31:24];\r
+\t\t\t  2'b11 : dreg_1 <= RDDATA[7:0];\r
+\t\t\tdefault : dreg_1 <= RDDATA[15:8];\r
+\t\t\tendcase\r
+\r
+\talways @(posedge BCLK)\r
+\t\tif (enable[2])\r
+\t\t\tcase (PACKET[1:0])\r
+\t\t\t  2'b01 : dreg_2 <= RDDATA[31:24];\r
+\t\t\t  2'b10 : dreg_2 <= RDDATA[7:0];\r
+\t\t\t  2'b11 : dreg_2 <= RDDATA[15:8];\r
+\t\t\tdefault : dreg_2 <= RDDATA[23:16];\r
+\t\t\tendcase\r
+\r
+\talways @(posedge BCLK)\r
+\t\tif (enable[3])\r
+\t\t\tcase (PACKET[1:0])\r
+\t\t\t  2'b01 : dreg_3 <= RDDATA[7:0];\r
+\t\t\t  2'b10 : dreg_3 <= RDDATA[15:8];\r
+\t\t\t  2'b11 : dreg_3 <= RDDATA[23:16];\r
+\t\t\tdefault : dreg_3 <= RDDATA[31:24];\r
+\t\t\tendcase\r
+\r
+\talways @(posedge BCLK)\r
+\t\tif (enable[4])\r
+\t\t\tcase (PACKET[1:0])\r
+\t\t\t  2'b01 : dreg_4 <= RDDATA[15:8];\r
+\t\t\t  2'b10 : dreg_4 <= RDDATA[23:16];\r
+\t\t\t  2'b11 : dreg_4 <= RDDATA[31:24];\r
+\t\t\tdefault : dreg_4 <= dreg_4;\r
+\t\t\tendcase\r
+\r
+\talways @(posedge BCLK) if (enable[5]) dreg_5 <= PACKET[1] ? RDDATA[31:24] : RDDATA[23:16];\r
+\t\r
+\talways @(posedge BCLK) if (enable[6]) dreg_6 <= RDDATA[31:24];\r
+\r
+\t// +++++++++++++++++++++++\r
+\t\r
+\talways @(SIZE or PACKET or RDDATA or dreg_0 or dreg_4)\r
+\t\tcasex ({SIZE,PACKET[3],PACKET[1:0]})\r
+\t\t  5'b0x_0_01 : out_0 = RDDATA[15:8];\r
+\t\t  5'b0x_0_10 : out_0 = RDDATA[23:16];\r
+\t\t  5'b00_0_11 : out_0 = RDDATA[31:24];\r
+\t\t  5'b01_1_11 : out_0 = dreg_4;\r
+\t\t  5'b1x_1_01 : out_0 = dreg_4;\r
+\t\t  5'b1x_1_1x : out_0 = dreg_4;\r
+\t\t  default\t : out_0 = RDDATA[7:0];\r
+\t\tendcase\r
+\r
+\talways @(SIZE or PACKET or RDDATA or dreg_1 or dreg_5)\r
+\t\tcasex ({SIZE,PACKET[3],PACKET[1:0]})\r
+\t\t  5'b01_0_01 : out_1 = RDDATA[23:16];\r
+\t\t  5'b01_0_10 : out_1 = RDDATA[31:24];\r
+\t\t  5'bxx_x_11 : out_1 = RDDATA[7:0];\r
+\t\t  5'b1x_1_01 : out_1 = dreg_5;\r
+\t\t  5'b1x_1_10 : out_1 = dreg_5;\r
+\t\t  default\t : out_1 = RDDATA[15:8];\r
+\t\tendcase\r
+\t\t\r
+\talways @(SIZE or PACKET or RDDATA or dreg_2 or dreg_6)\r
+\t\tcase ({SIZE[1],PACKET[3],PACKET[1:0]})\r
+\t\t  4'b1_1_01 : out_2 = dreg_6;\r
+\t\t  4'b1_1_10 : out_2 = RDDATA[7:0];\r
+\t\t  4'b1_1_11 : out_2 = RDDATA[15:8];\r
+\t\t  default\t: out_2 = RDDATA[23:16];\r
+\t\tendcase\r
+\t\t\r
+\talways @(SIZE or PACKET or RDDATA or dreg_3)\r
+\t\tcase ({SIZE[1],PACKET[3],PACKET[1:0]})\r
+\t\t  4'b1_1_01 : out_3 = RDDATA[7:0];\r
+\t\t  4'b1_1_10 : out_3 = RDDATA[15:8];\r
+\t\t  4'b1_1_11 : out_3 = RDDATA[23:16];\r
+\t\t  default\t: out_3 = RDDATA[31:24];\r
+\t\tendcase\r
+\t\t\r
+\tassign DP_DI = REG_OUT ? {dreg_3,dreg_2,dreg_1,dreg_0} : {out_3,out_2,out_1,out_0};\r
+\t\r
+\t// ++++++++++++++++ Special case QWord if cache switched off +++++++++++++++++++\r
+\t\r
+\talways @(posedge BCLK) AUX_QW <= ACC_OK & ~CA_HIT & (SIZE == 2'b11) & PACKET[3];\r
+\t\r
+endmodule\r
+"
+"//////////////////////////////////////////////////////////////////
+//                                                              //
+//  L1 Cache for Amber 2 Core                                   //
+//                                                              //
+//  This file is part of the Amber project                      //
+//  http://www.opencores.org/project,amber                      //
+//                                                              //
+//  Description                                                 //
+//  Synthesizable L1 Unified Data and Instruction Cache         //
+//  Cache is 4-way, 256 line and 16 bytes per line for          //
+//  a total of 16KB. The cache policy is write-through and      //
+//  read allocate. For swap instructions (SWP and SWPB) the     //
+//  location is evicted from the cache and read from main       //
+//  memory.                                                     //
+//                                                              //
+//  Author(s):                                                  //
+//      - Conor Santifort, csantifort.amber@gmail.com           //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+//                                                              //
+// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
+//                                                              //
+// This source file may be used and distributed without         //
+// restriction provided that this copyright statement is not    //
+// removed from the file and that any derivative work contains  //
+// the original copyright notice and the associated disclaimer. //
+//                                                              //
+// This source file is free software; you can redistribute it   //
+// and/or modify it under the terms of the GNU Lesser General   //
+// Public License as published by the Free Software Foundation; //
+// either version 2.1 of the License, or (at your option) any   //
+// later version.                                               //
+//                                                              //
+// This source is distributed in the hope that it will be       //
+// useful, but WITHOUT ANY WARRANTY; without even the implied   //
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
+// PURPOSE.  See the GNU Lesser General Public License for more //
+// details.                                                     //
+//                                                              //
+// You should have received a copy of the GNU Lesser General    //
+// Public License along with this source; if not, download it   //
+// from http://www.opencores.org/lgpl.shtml                     //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+`include ""global_defines.vh""
+`include ""a23_config_defines.vh""
+
+module a23_cache 
+#(
+
+// ---------------------------------------------------------
+// Cache Configuration
+
+// Limited to Linux 4k page sizes -> 256 lines
+parameter CACHE_LINES          = 256,  
+
+// This cannot be changed without some major surgeory on
+// this module                                       
+parameter CACHE_WORDS_PER_LINE = 4,
+
+// Changing this parameter is the recommended
+// way to change the overall cache size; 2, 4 and 8 ways are supported.
+//   2 ways -> 8KB  cache
+//   4 ways -> 16KB cache
+//   8 ways -> 32KB cache
+parameter WAYS              = `A23_CACHE_WAYS ,
+
+// derived configuration parameters
+parameter CACHE_ADDR_WIDTH  = log2 ( CACHE_LINES ),                        // = 8
+parameter WORD_SEL_WIDTH    = log2 ( CACHE_WORDS_PER_LINE ),               // = 2
+parameter TAG_ADDR_WIDTH    = 32 - CACHE_ADDR_WIDTH - WORD_SEL_WIDTH - 2,  // = 20
+parameter TAG_WIDTH         = TAG_ADDR_WIDTH + 1,                          // = 21, including Valid flag
+parameter CACHE_LINE_WIDTH  = CACHE_WORDS_PER_LINE * 32,                   // = 128
+parameter TAG_ADDR32_LSB    = CACHE_ADDR_WIDTH + WORD_SEL_WIDTH + 2,       // = 12
+parameter CACHE_ADDR32_MSB  = CACHE_ADDR_WIDTH + WORD_SEL_WIDTH + 2 - 1,   // = 11
+parameter CACHE_ADDR32_LSB  =                    WORD_SEL_WIDTH + 2    ,   // = 4
+parameter WORD_SEL_MSB      = WORD_SEL_WIDTH + 2 - 1,                      // = 3
+parameter WORD_SEL_LSB      =                  2                           // = 2
+// ---------------------------------------------------------
+)
+
+
+(
+input                               i_clk,
+
+// Read / Write requests from core
+input                               i_select,
+input                               i_exclusive,        // exclusive access, part of swap instruction
+input      [31:0]                   i_write_data,
+input                               i_write_enable,     // core issued write request
+input      [31:0]                   i_address,          // registered address from execute
+input      [31:0]                   i_address_nxt,      // un-registered version of address from execute stage
+input      [3:0]                    i_byte_enable,
+input                               i_cache_enable,     // from co-processor 15 configuration register
+input                               i_cache_flush,      // from co-processor 15 register
+
+output      [31:0]                  o_read_data,                                                       
+input                               i_core_stall,
+output                              o_stall,
+
+// WB Read Request                                                          
+output                              o_wb_req,          // Read Request
+input      [31:0]                   i_wb_address,      // wb bus                                 
+input      [31:0]                   i_wb_read_data,    // wb bus                              
+input                               i_wb_stall         // wb_stb && !wb_ack
+);
+
+`include ""a23_localparams.vh""
+`include ""a23_functions.vh""
+
+// One-hot encoded
+localparam       C_INIT   = 0,
+                 C_CORE   = 1,
+                 C_FILL   = 2,
+                 C_INVA   = 3,
+                 C_STATES = 4;
+                 
+localparam [3:0] CS_INIT            = 4\'d0,
+                 CS_IDLE            = 4\'d1,
+                 CS_FILL1           = 4\'d2,
+                 CS_FILL2           = 4\'d3,
+                 CS_FILL3           = 4\'d4,
+                 CS_FILL4           = 4\'d5,
+                 CS_FILL_COMPLETE   = 4\'d6,
+                 CS_TURN_AROUND     = 4\'d7,
+                 CS_WRITE_HIT1      = 4\'d8,
+                 CS_EX_DELETE       = 4\'d9;
+                 
+
+reg  [3:0]                  c_state    = CS_IDLE;
+reg  [C_STATES-1:0]         source_sel = 1\'d1 << C_CORE;
+reg  [CACHE_ADDR_WIDTH:0]   init_count = \'d0;
+                 
+wire [TAG_WIDTH-1:0]        tag_rdata_way [WAYS-1:0];
+wire [CACHE_LINE_WIDTH-1:0] data_rdata_way[WAYS-1:0];
+wire [WAYS-1:0]             data_wenable_way;
+wire [WAYS-1:0]             data_hit_way;
+wire [WAYS-1:0]             tag_wenable_way;
+reg  [WAYS-1:0]             select_way = \'d0;
+wire [WAYS-1:0]             next_way;
+reg  [WAYS-1:0]             valid_bits_r = \'d0;
+
+reg  [3:0]                  random_num = 4\'hf;
+
+wire [CACHE_ADDR_WIDTH-1:0] tag_address;
+wire [TAG_WIDTH-1:0]        tag_wdata;
+wire                        tag_wenable;
+
+wire [CACHE_LINE_WIDTH-1:0] read_miss_wdata;
+wire [CACHE_LINE_WIDTH-1:0] write_hit_wdata;
+wire [CACHE_LINE_WIDTH-1:0] data_wdata;
+wire [CACHE_ADDR_WIDTH-1:0] data_address;
+wire [31:0]                 write_data_word;
+
+wire                        hit;
+wire                        read_miss;
+wire                        write_miss;
+wire                        write_hit;
+
+reg  [31:0]                 miss_address = \'d0;
+wire [CACHE_LINE_WIDTH-1:0] hit_rdata;
+
+wire                        write_stall;
+wire                        cache_busy_stall;
+wire                        read_stall;
+
+wire                        enable;
+wire [CACHE_ADDR_WIDTH-1:0] address;
+
+reg  [CACHE_LINE_WIDTH-1:0] wb_rdata_burst = \'d0;
+reg                         wb_read_buf_valid = \'d0;
+reg  [31:0]                 wb_read_buf_address = \'d0;
+reg  [31:0]                 wb_read_buf_data = \'d0;
+wire                        wb_read_buf_hit;
+
+wire                        exclusive_access;
+wire                        ex_read_hit;
+reg                         ex_read_hit_r = \'d0;
+reg  [WAYS-1:0]             ex_read_hit_way = \'d0;
+reg  [CACHE_ADDR_WIDTH-1:0] ex_read_address;
+wire                        ex_read_hit_clear;
+wire                        ex_read_cache_busy;
+
+genvar                      i;
+
+// ======================================
+// Address to use for cache access
+// ======================================
+// If currently stalled then the address for the next
+// cycle will be the same as it is in the current cycle
+//
+assign address = i_core_stall ? i_address    [CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] :
+                                i_address_nxt[CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] ;
+
+// ======================================
+// Outputs
+// ======================================
+assign o_read_data      = wb_read_buf_hit                              ? wb_read_buf_data   :
+                          i_address[WORD_SEL_MSB:WORD_SEL_LSB] == 2\'d0 ? hit_rdata [31:0]   :
+                          i_address[WORD_SEL_MSB:WORD_SEL_LSB] == 2\'d1 ? hit_rdata [63:32]  :
+                          i_address[WORD_SEL_MSB:WORD_SEL_LSB] == 2\'d2 ? hit_rdata [95:64]  :
+                                                                         hit_rdata [127:96] ;
+
+// Don\'t allow the cache to stall the wb i/f for an exclusive access
+// The cache needs a couple of cycles to flush a potential copy of the exclusive
+// address, but the wb can do the access in parallel. So there is no
+// stall in the state CS_EX_DELETE, even though the cache is out of action. 
+// This works fine as long as the wb is stalling the core
+assign o_stall          = read_stall || write_stall || cache_busy_stall || ex_read_cache_busy;
+
+assign o_wb_req        = (( read_miss || write_miss ) && c_state == CS_IDLE ) || 
+                          c_state == CS_WRITE_HIT1;
+
+     
+// ======================================
+// Cache State Machine
+// ======================================
+
+// Little State Machine to Flush Tag RAMS
+always @ ( posedge i_clk )
+    if ( i_cache_flush )
+        begin
+        c_state     <= CS_INIT;
+        source_sel  <= 1\'d1 << C_INIT;
+        init_count  <= \'d0;
+        `ifdef A23_CACHE_DEBUG  
+        `TB_DEBUG_MESSAGE  
+        $display(""Cache Flush"");
+        `endif            
+        end
+    else    
+        case ( c_state )
+            CS_INIT :
+                if ( init_count < CACHE_LINES [CACHE_ADDR_WIDTH:0] )
+                    begin
+                    init_count  <= init_count + 1\'d1;
+                    source_sel  <= 1\'d1 << C_INIT;
+                    end
+                else
+                    begin
+                    source_sel  <= 1\'d1 << C_CORE;
+                    c_state     <= CS_TURN_AROUND;
+                    end 
+                       
+             CS_IDLE :
+                begin
+                source_sel  <= 1\'d1 << C_CORE;
+                
+                if ( ex_read_hit || ex_read_hit_r )
+                    begin
+                    select_way  <= data_hit_way | ex_read_hit_way;
+                    c_state     <= CS_EX_DELETE;        
+                    source_sel  <= 1\'d1 << C_INVA;
+                    end
+                else if ( read_miss ) 
+                    begin
+                    // wb read request asserted, wait for ack
+                    if ( !i_wb_stall )   
+                        c_state <= CS_FILL1; 
+                    end           
+                else if ( write_hit )
+                    c_state <= CS_WRITE_HIT1;        
+               end
+                   
+                   
+             CS_FILL1 :
+                begin
+                // wb read request asserted, wait for ack
+                if ( !i_wb_stall )
+                    c_state <= CS_FILL2;
+                end
+                
+                
+             CS_FILL2 :
+                // first read of burst of 4
+                // wb read request asserted, wait for ack
+                if ( !i_wb_stall )
+                    c_state <= CS_FILL3;
+
+
+             CS_FILL3 :
+                // second read of burst of 4
+                // wb read request asserted, wait for ack
+                if ( !i_wb_stall )
+                    c_state <= CS_FILL4;
+                
+                
+             CS_FILL4 :
+                // third read of burst of 4
+                // wb read request asserted, wait for ack
+                if ( !i_wb_stall ) 
+                    begin
+                    c_state     <= CS_FILL_COMPLETE;
+                    source_sel  <= 1\'d1 << C_FILL;
+                
+                    // Pick a way to write the cache update into
+                    // Either pick one of the invalid caches, or if all are valid, then pick
+                    // one randomly
+                    
+                    select_way  <= next_way; 
+                    random_num  <= {random_num[2], random_num[1], random_num[0], 
+                                     random_num[3]^random_num[2]};
+                    end
+
+
+             // Write the read fetch data in this cycle
+             CS_FILL_COMPLETE : 
+                // fourth read of burst of 4
+                // wb read request asserted, wait for ack
+                if ( !i_wb_stall )
+                    begin
+                    // Back to normal cache operations, but
+                    // use physical address for first read as
+                    // address moved before the stall was asserted for the read_miss
+                    // However don\'t use it if its a non-cached address!
+                    source_sel  <= 1\'d1 << C_CORE;              
+                    c_state     <= CS_TURN_AROUND;    
+                    end                                 
+                                                        
+
+             // Ignore the tag read data in this cycle   
+             // Wait 1 cycle to pre-read the cache and return to normal operation                 
+             CS_TURN_AROUND : 
+                begin
+                c_state     <= CS_IDLE;
+                end
+                
+
+             // Flush the entry matching an exclusive access         
+             CS_EX_DELETE:       
+                begin
+                `ifdef A23_CACHE_DEBUG    
+                `TB_DEBUG_MESSAGE
+                $display(""Cache deleted Locked entry"");
+                `endif    
+                c_state    <= CS_TURN_AROUND;
+                source_sel <= 1\'d1 << C_CORE;
+                end
+                
+                                 
+             CS_WRITE_HIT1:
+                begin
+                // wait for an ack on the wb bus to complete the write
+                if ( !i_wb_stall )           
+                    c_state     <= CS_IDLE;
+                    
+                end
+        endcase                       
+
+
+// ======================================
+// Capture WB Block Read - burst of 4 words
+// ======================================
+always @ ( posedge i_clk )
+    if ( !i_wb_stall )
+        wb_rdata_burst <= {i_wb_read_data, wb_rdata_burst[127:32]};
+
+
+// ======================================
+// WB Read Buffer
+// ======================================
+always @ ( posedge i_clk )
+    begin
+    if ( c_state == CS_FILL1 || c_state == CS_FILL2 || 
+         c_state == CS_FILL3 || c_state == CS_FILL4 )
+        begin
+        if ( !i_wb_stall )
+            begin
+            wb_read_buf_valid   <= 1\'d1;
+            wb_read_buf_address <= i_wb_address;
+            wb_read_buf_data    <= i_wb_read_data;
+            end
+        end
+    else    
+        wb_read_buf_valid   <= 1\'d0;
+    end
+        
+
+// ======================================
+// Miss Address
+// ======================================
+always @ ( posedge i_clk )
+    if ( o_wb_req )
+        miss_address <= i_address;
+        
+
+// ======================================
+// Remember Read-Modify-Write Hit
+// ======================================
+assign ex_read_hit_clear = c_state == CS_EX_DELETE;
+
+always @ ( posedge i_clk )
+    if ( ex_read_hit_clear )
+        begin
+        ex_read_hit_r   <= 1\'d0;
+        ex_read_hit_way <= \'d0;
+        end
+    else if ( ex_read_hit )
+        begin
+        
+        `ifdef A23_CACHE_DEBUG
+            `TB_DEBUG_MESSAGE
+            $display (""Exclusive access cache hit address 0x%08h"", i_address);
+        `endif
+        
+        ex_read_hit_r   <= 1\'d1;
+        ex_read_hit_way <= data_hit_way;
+        end
+    else if ( c_state == CS_FILL_COMPLETE && ex_read_hit_r )
+        ex_read_hit_way <= select_way;
+
+        
+always @ (posedge i_clk)
+    if ( ex_read_hit )
+        ex_read_address <= i_address[CACHE_ADDR32_MSB:CACHE_ADDR32_LSB];
+
+
+assign tag_address      = source_sel[C_FILL] ? miss_address      [CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] :
+                          source_sel[C_INVA] ? ex_read_address                                       :
+                          source_sel[C_INIT] ? init_count[CACHE_ADDR_WIDTH-1:0]                      :
+                          source_sel[C_CORE] ? address                                               :
+                                               {CACHE_ADDR_WIDTH{1\'d0}}                              ;
+
+
+assign data_address     = write_hit          ? i_address   [CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] :
+                          source_sel[C_FILL] ? miss_address[CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] : 
+                          source_sel[C_CORE] ? address                                         :
+                                               {CACHE_ADDR_WIDTH{1\'d0}}                        ;
+
+                                                          
+assign tag_wdata        = source_sel[C_FILL] ? {1\'d1, miss_address[31:TAG_ADDR32_LSB]} :
+                                               {TAG_WIDTH{1\'d0}}                       ;
+
+
+    // Data comes in off the WB bus in wrap4 with the missed data word first
+assign data_wdata       = write_hit && c_state == CS_IDLE ? write_hit_wdata : read_miss_wdata;
+
+assign read_miss_wdata  = miss_address[3:2] == 2\'d0 ? wb_rdata_burst                              :
+                          miss_address[3:2] == 2\'d1 ? { wb_rdata_burst[95:0], wb_rdata_burst[127:96] }:
+                          miss_address[3:2] == 2\'d2 ? { wb_rdata_burst[63:0], wb_rdata_burst[127:64] }:
+                                                      { wb_rdata_burst[31:0], wb_rdata_burst[127:32] };
+
+
+assign write_hit_wdata  = i_address[3:2] == 2\'d0 ? {hit_rdata[127:32], write_data_word                   } :
+                          i_address[3:2] == 2\'d1 ? {hit_rdata[127:64], write_data_word, hit_rdata[31:0]  } :
+                          i_address[3:2] == 2\'d2 ? {hit_rdata[127:96], write_data_word, hit_rdata[63:0]  } :
+                                                   {                   write_data_word, hit_rdata[95:0]  } ;
+
+// Use Byte Enables
+assign write_data_word  = i_byte_enable == 4\'b0001 ? { o_read_data[31: 8], i_write_data[ 7: 0]                   } :
+                          i_byte_enable == 4\'b0010 ? { o_read_data[31:16], i_write_data[15: 8], o_read_data[ 7:0]} :
+                          i_byte_enable == 4\'b0100 ? { o_read_data[31:24], i_write_data[23:16], o_read_data[15:0]} :
+                          i_byte_enable == 4\'b1000 ? {                     i_write_data[31:24], o_read_data[23:0]} :
+                          i_byte_enable == 4\'b0011 ? { o_read_data[31:16], i_write_data[15: 0]                   } :
+                          i_byte_enable == 4\'b1100 ? {                     i_write_data[31:16], o_read_data[15:0]} :
+                                                     i_write_data                                                  ;
+                          
+
+assign tag_wenable      = source_sel[C_INVA] ? 1\'d1  :
+                          source_sel[C_FILL] ? 1\'d1  :
+                          source_sel[C_INIT] ? 1\'d1  :
+                          source_sel[C_CORE] ? 1\'d0  :
+                                               1\'d0  ;
+
+                          
+assign enable           = i_select && i_cache_enable;
+
+assign exclusive_access = i_exclusive && i_cache_enable;
+
+
+                          // the wb read buffer returns data directly from the wb bus to the
+                          // core during a read miss operation
+assign wb_read_buf_hit  = enable && wb_read_buf_address == i_address && wb_read_buf_valid;
+
+assign hit              = |data_hit_way;
+
+assign write_hit        = enable &&  i_write_enable && hit;
+                                                           
+assign write_miss       = enable &&  i_write_enable && !hit && c_state != CS_WRITE_HIT1;
+                                                           
+assign read_miss        = enable && !i_write_enable && !(hit || wb_read_buf_hit);
+
+                          // Exclusive read hit
+assign ex_read_hit      = exclusive_access && !i_write_enable && (hit || wb_read_buf_hit);
+
+                          // Added to fix rare swap bug which occurs when the cache starts
+                          // a fill just as the swap instruction starts to execute. The cache
+                          // fails to check for a read hit on the swap read cycle.
+                          // This signal stalls the core in that case until after the
+                          // fill has completed.
+assign ex_read_cache_busy = exclusive_access && !i_write_enable && c_state != CS_IDLE;
+
+                          // Need to stall for a write miss to wait for the current wb 
+                          // read miss access to complete. Also for a write hit, need 
+                          // to stall for 1 cycle while the data cache is being written to
+assign write_stall      = ( write_hit  && c_state != CS_WRITE_HIT1 ) ||
+                          ( write_miss && ( c_state != CS_IDLE ) )   ||
+                           i_wb_stall                                ;
+
+assign read_stall       = read_miss;
+
+                          // Core may or may not be trying to access cache memory during
+                          // this phase of the read fetch. It could be doing e.g. a wb access
+assign cache_busy_stall = ((c_state == CS_TURN_AROUND || c_state == CS_FILL1) && enable) ||
+                           c_state == CS_INIT;
+
+
+// ======================================
+// Instantiate RAMS
+// ======================================
+
+generate
+    for ( i=0; i<WAYS;i=i+1 ) begin : rams
+
+        // Tag RAMs 
+        `ifdef XILINX_SPARTAN6_FPGA
+        xs6_sram_256x21_line_en
+        `endif
+
+        `ifdef XILINX_VIRTEX6_FPGA
+        xv6_sram_256x21_line_en
+        `endif
+
+        `ifndef XILINX_FPGA
+        generic_sram_line_en 
+        `endif
+
+            #(
+            .DATA_WIDTH                 ( TAG_WIDTH             ),
+            .INITIALIZE_TO_ZERO         ( 1                     ),
+            .ADDRESS_WIDTH              ( CACHE_ADDR_WIDTH      ))
+        u_tag (
+            .i_clk                      ( i_clk                 ),
+            .i_write_data               ( tag_wdata             ),
+            .i_write_enable             ( tag_wenable_way[i]    ),
+            .i_address                  ( tag_address           ),
+
+            .o_read_data                ( tag_rdata_way[i]      )
+            );
+            
+        // Data RAMs 
+        `ifdef XILINX_SPARTAN6_FPGA
+        xs6_sram_256x128_byte_en
+        `endif
+
+        `ifdef XILINX_VIRTEX6_FPGA
+        xv6_sram_256x128_byte_en
+        `endif
+
+        `ifndef XILINX_FPGA
+        generic_sram_byte_en
+        `endif
+
+            #(
+            .DATA_WIDTH    ( CACHE_LINE_WIDTH) ,
+            .ADDRESS_WIDTH ( CACHE_ADDR_WIDTH) )
+        u_data (
+            .i_clk                      ( i_clk                         ),
+            .i_write_data               ( data_wdata                    ),
+            .i_write_enable             ( data_wenable_way[i]           ),
+            .i_address                  ( data_address                  ),
+            .i_byte_enable              ( {CACHE_LINE_WIDTH/8{1\'d1}}    ),
+            .o_read_data                ( data_rdata_way[i]             )
+            );                                                     
+
+
+        // Per tag-ram write-enable
+        assign tag_wenable_way[i]  = tag_wenable && ( select_way[i] || source_sel[C_INIT] );
+
+        // Per data-ram write-enable
+        assign data_wenable_way[i] = (source_sel[C_FILL] && select_way[i]) || 
+                                     (write_hit && data_hit_way[i] && c_state == CS_IDLE);
+        // Per data-ram hit flag
+        assign data_hit_way[i]     = tag_rdata_way[i][TAG_WIDTH-1] &&                                                  
+                                     tag_rdata_way[i][TAG_ADDR_WIDTH-1:0] == i_address[31:TAG_ADDR32_LSB] &&  
+                                     c_state == CS_IDLE;                                                               
+    end                                                         
+endgenerate
+
+
+// ======================================
+// Register Valid Bits
+// ======================================
+generate
+if ( WAYS == 2 ) begin : valid_bits_2ways
+
+    always @ ( posedge i_clk )
+        if ( c_state == CS_IDLE )
+            valid_bits_r <= {tag_rdata_way[1][TAG_WIDTH-1], 
+                             tag_rdata_way[0][TAG_WIDTH-1]};
+                           
+end
+else if ( WAYS == 3 ) begin : valid_bits_3ways
+
+    always @ ( posedge i_clk )
+        if ( c_state == CS_IDLE )
+            valid_bits_r <= {tag_rdata_way[2][TAG_WIDTH-1], 
+                             tag_rdata_way[1][TAG_WIDTH-1], 
+                             tag_rdata_way[0][TAG_WIDTH-1]};
+                           
+end
+else if ( WAYS == 4 ) begin : valid_bits_4ways
+
+    always @ ( posedge i_clk )
+        if ( c_state == CS_IDLE )
+            valid_bits_r <= {tag_rdata_way[3][TAG_WIDTH-1], 
+                             tag_rdata_way[2][TAG_WIDTH-1], 
+                             tag_rdata_way[1][TAG_WIDTH-1], 
+                             tag_rdata_way[0][TAG_WIDTH-1]};
+                           
+end
+else begin : valid_bits_8ways
+
+    always @ ( posedge i_clk )
+        if ( c_state == CS_IDLE )
+            valid_bits_r <= {tag_rdata_way[7][TAG_WIDTH-1], 
+                             tag_rdata_way[6][TAG_WIDTH-1], 
+                             tag_rdata_way[5][TAG_WIDTH-1], 
+                             tag_rdata_way[4][TAG_WIDTH-1], 
+                             tag_rdata_way[3][TAG_WIDTH-1], 
+                             tag_rdata_way[2][TAG_WIDTH-1], 
+                             tag_rdata_way[1][TAG_WIDTH-1], 
+                             tag_rdata_way[0][TAG_WIDTH-1]};
+                           
+end
+endgenerate
+
+
+// ======================================
+// Select read hit data
+// ======================================
+generate
+if ( WAYS == 2 ) begin : read_data_2ways
+
+    assign hit_rdata    = data_hit_way[0] ? data_rdata_way[0] :
+                          data_hit_way[1] ? data_rdata_way[1] :
+                                     {CACHE_LINE_WIDTH{1\'d1}} ;  // all 1\'s for debug
+                           
+end
+else if ( WAYS == 3 ) begin : read_data_3ways
+
+    assign hit_rdata    = data_hit_way[0] ? data_rdata_way[0] :
+                          data_hit_way[1] ? data_rdata_way[1] :
+                          data_hit_way[2] ? data_rdata_way[2] :
+                                     {CACHE_LINE_WIDTH{1\'d1}} ;  // all 1\'s for debug
+                           
+end
+else if ( WAYS == 4 ) begin : read_data_4ways
+
+    assign hit_rdata    = data_hit_way[0] ? data_rdata_way[0] :
+                          data_hit_way[1] ? data_rdata_way[1] :
+                          data_hit_way[2] ? data_rdata_way[2] :
+                          data_hit_way[3] ? data_rdata_way[3] :
+                                     {CACHE_LINE_WIDTH{1\'d1}} ;  // all 1\'s for debug
+                           
+end
+else begin : read_data_8ways
+
+    assign hit_rdata    = data_hit_way[0] ? data_rdata_way[0] :
+                          data_hit_way[1] ? data_rdata_way[1] :
+                          data_hit_way[2] ? data_rdata_way[2] :
+                          data_hit_way[3] ? data_rdata_way[3] :
+                          data_hit_way[4] ? data_rdata_way[4] :
+                          data_hit_way[5] ? data_rdata_way[5] :
+                          data_hit_way[6] ? data_rdata_way[6] :
+                          data_hit_way[7] ? data_rdata_way[7] :
+                                     {CACHE_LINE_WIDTH{1\'d1}} ;  // all 1\'s for debug
+                           
+end
+endgenerate
+
+
+// ======================================
+// Function to select the way to use
+// for fills
+// ======================================
+generate
+if ( WAYS == 2 ) begin : pick_way_2ways
+
+    assign next_way = pick_way ( valid_bits_r, random_num );
+
+    function [WAYS-1:0] pick_way;
+    input [WAYS-1:0] valid_bits;
+    input [3:0]      random_num;
+    begin
+        if (      valid_bits[0] == 1\'d0 )
+            // way 0 not occupied so use it
+            pick_way     = 2\'b01;
+        else if ( valid_bits[1] == 1\'d0 )
+            // way 1 not occupied so use it
+            pick_way     = 2\'b10;
+        else
+            begin
+            // All ways occupied so pick one randomly
+            case (random_num[3:1])
+                3\'d0, 3\'d3,
+                3\'d5, 3\'d6: pick_way = 2\'b10;
+                default:    pick_way = 2\'b01;
+            endcase
+            end
+    end
+    endfunction
+                                                      
+end
+else if ( WAYS == 3 ) begin : pick_way_3ways
+
+    assign next_way = pick_way ( valid_bits_r, random_num );
+
+    function [WAYS-1:0] pick_way;
+    input [WAYS-1:0] valid_bits;
+    input [3:0]      random_num;
+    begin
+        if (      valid_bits[0] == 1\'d0 )
+            // way 0 not occupied so use it
+            pick_way     = 3\'b001;
+        else if ( valid_bits[1] == 1\'d0 )
+            // way 1 not occupied so use it
+            pick_way     = 3\'b010;
+        else if ( valid_bits[2] == 1\'d0 )
+            // way 2 not occupied so use it
+            pick_way     = 3\'b100;
+        else
+            begin
+            // All ways occupied so pick one randomly
+            case (random_num[3:1])
+                3\'d0, 3\'d1, 3\'d2: pick_way = 3\'b010;
+                3\'d2, 3\'d3, 3\'d4: pick_way = 3\'b100;
+                default:          pick_way = 3\'b001;
+            endcase
+            end
+    end
+    endfunction
+                           
+end
+else if ( WAYS == 4 ) begin : pick_way_4ways
+
+    assign next_way = pick_way ( valid_bits_r, random_num );
+
+    function [WAYS-1:0] pick_way;
+    input [WAYS-1:0] valid_bits;
+    input [3:0]      random_num;
+    begin
+        if (      valid_bits[0] == 1\'d0 )
+            // way 0 not occupied so use it
+            pick_way     = 4\'b0001;
+        else if ( valid_bits[1] == 1\'d0 )
+            // way 1 not occupied so use it
+            pick_way     = 4\'b0010;
+        else if ( valid_bits[2] == 1\'d0 )
+            // way 2 not occupied so use it
+            pick_way     = 4\'b0100;
+        else if ( valid_bits[3] == 1\'d0 )
+            // way 3 not occupied so use it
+            pick_way     = 4\'b1000;
+        else
+            begin
+            // All ways occupied so pick one randomly
+            case (random_num[3:1])
+                3\'d0, 3\'d1: pick_way = 4\'b0100;
+                3\'d2, 3\'d3: pick_way = 4\'b1000;
+                3\'d4, 3\'d5: pick_way = 4\'b0001;
+                default:    pick_way = 4\'b0010;
+            endcase
+            end
+    end
+    endfunction
+                           
+end
+else begin : pick_way_8ways
+
+    assign next_way = pick_way ( valid_bits_r, random_num );
+
+    function [WAYS-1:0] pick_way;
+    input [WAYS-1:0] valid_bits;
+    input [3:0]      random_num;
+    begin
+        if (      valid_bits[0] == 1\'d0 )
+            // way 0 not occupied so use it
+            pick_way     = 8\'b00000001;
+        else if ( valid_bits[1] == 1\'d0 )
+            // way 1 not occupied so use it
+            pick_way     = 8\'b00000010;
+        else if ( valid_bits[2] == 1\'d0 )
+            // way 2 not occupied so use it
+            pick_way     = 8\'b00000100;
+        else if ( valid_bits[3] == 1\'d0 )
+            // way 3 not occupied so use it
+            pick_way     = 8\'b00001000;
+        else if ( valid_bits[4] == 1\'d0 )
+            // way 3 not occupied so use it
+            pick_way     = 8\'b00010000;
+        else if ( valid_bits[5] == 1\'d0 )
+            // way 3 not occupied so use it
+            pick_way     = 8\'b00100000;
+        else if ( valid_bits[6] == 1\'d0 )
+            // way 3 not occupied so use it
+            pick_way     = 8\'b01000000;
+        else if ( valid_bits[7] == 1\'d0 )
+            // way 3 not occupied so use it
+            pick_way     = 8\'b10000000;
+        else
+            begin
+            // All ways occupied so pick one randomly
+            case (random_num[3:1])
+                3\'d0:       pick_way = 8\'b00010000;
+                3\'d1:       pick_way = 8\'b00100000;
+                3\'d2:       pick_way = 8\'b01000000;
+                3\'d3:       pick_way = 8\'b10000000;
+                3\'d4:       pick_way = 8\'b00000001;
+                3\'d5:       pick_way = 8\'b00000010;
+                3\'d6:       pick_way = 8\'b00000100;
+                default:    pick_way = 8\'b00001000;
+            endcase
+            end
+    end
+    endfunction
+                           
+end
+endgenerate
+
+
+// ========================================================
+// Debug WB bus - not synthesizable
+// ========================================================
+//synopsys translate_off
+wire    [(6*8)-1:0]     xSOURCE_SEL;
+wire    [(20*8)-1:0]    xC_STATE;
+
+assign xSOURCE_SEL = source_sel[C_CORE]            ? ""C_CORE""           :
+                     source_sel[C_INIT]            ? ""C_INIT""           :
+                     source_sel[C_FILL]            ? ""C_FILL""           :
+                     source_sel[C_INVA]            ? ""C_INVA""           :
+                                                     ""UNKNON""           ;
+ 
+assign xC_STATE    = c_state == CS_INIT            ? ""CS_INIT""          :
+                     c_state == CS_IDLE            ? ""CS_IDLE""          :
+                     c_state == CS_FILL1           ? ""CS_FILL1""         :
+                     c_state == CS_FILL2           ? ""CS_FILL2""         :
+                     c_state == CS_FILL3           ? ""CS_FILL3""         :
+                     c_state == CS_FILL4           ? ""CS_FILL4""         :
+                     c_state == CS_FILL_COMPLETE   ? ""CS_FILL_COMPLETE"" :
+                     c_state == CS_EX_DELETE       ? ""CS_EX_DELETE""     :
+                     c_state == CS_TURN_AROUND     ? ""CS_TURN_AROUND""   :
+                     c_state == CS_WRITE_HIT1      ? ""CS_WRITE_HIT1""    :
+                                                     ""UNKNOWN""          ;
+
+
+generate
+if ( WAYS == 2 ) begin : check_hit_2ways
+
+    always @( posedge i_clk )
+        if ( (data_hit_way[0] + data_hit_way[1] ) > 4\'d1 )
+            begin
+            `TB_ERROR_MESSAGE
+            $display(""Hit in more than one cache ways!"");                                                  
+            end
+                                                      
+end
+else if ( WAYS == 3 ) begin : check_hit_3ways
+
+    always @( posedge i_clk )
+        if ( (data_hit_way[0] + data_hit_way[1] + data_hit_way[2] ) > 4\'d1 )
+            begin
+            `TB_ERROR_MESSAGE
+            $display(""Hit in more than one cache ways!"");                                                  
+            end
+                           
+end
+else if ( WAYS == 4 ) begin : check_hit_4ways
+
+    always @( posedge i_clk )
+        if ( (data_hit_way[0] + data_hit_way[1] + 
+              data_hit_way[2] + data_hit_way[3] ) > 4\'d1 )
+            begin
+            `TB_ERROR_MESSAGE
+            $display(""Hit in more than one cache ways!"");                                                  
+            end
+                           
+end
+else if ( WAYS == 8 )  begin : check_hit_8ways
+
+    always @( posedge i_clk )
+        if ( (data_hit_way[0] + data_hit_way[1] + 
+              data_hit_way[2] + data_hit_way[3] +
+              data_hit_way[4] + data_hit_way[5] +
+              data_hit_way[6] + data_hit_way[7] ) > 4\'d1 )
+            begin
+            `TB_ERROR_MESSAGE
+            $display(""Hit in more than one cache ways!"");                                                  
+            end
+                           
+end
+else begin : check_hit_nways
+
+    initial
+        begin
+        `TB_ERROR_MESSAGE
+        $display(""Unsupported number of ways %0d"", WAYS);
+        $display(""Set A23_CACHE_WAYS in a23_config_defines.v to either 2,3,4 or 8"");
+        end
+
+end
+endgenerate
+    
+//synopsys translate_on
+    
+endmodule
+
+"
+"module LX9CoProARM2 (
+
+        input fastclk,
+        
+        // GOP Signals
+        inout [8:1] test,
+        input [3:0] sw,
+        
+        // Tube signals
+        input h_phi2,
+        input [2:0] h_addr,
+        inout [7:0] h_data,
+        input h_rdnw,
+        input h_cs_b,
+        input h_rst_b,
+        output h_irq_b,
+
+        // Ram Signals
+        output ram_ub_b,
+        output ram_lb_b,
+        output ram_cs,
+        output ram_oe,
+        output ram_wr,
+        output [18:0] ram_addr,
+        inout  [31:0] ram_data
+);
+
+  // Registers and nets
+  wire        clk;
+  wire [31:0] dat_o;
+  wire [31:0] dat_i;
+  wire [31:0] adr;
+  wire        we;
+  wire [ 3:0] sel;
+  wire        stb;
+  wire        cyc;
+  wire        ack;
+
+  // wires to BIOS ROM
+  wire [31:0] rom_dat_o;
+  wire [31:0] rom_dat_i;
+  wire [31:0] rom_adr_i;
+  wire [ 3:0] rom_sel_i;
+  wire        rom_we_i;
+  wire        rom_cyc_i;
+  wire        rom_stb_i;
+  wire        rom_ack_o;
+  
+  // wires to RAM
+  wire [31:0] ram_dat_o;
+  wire [31:0] ram_dat_i;
+  wire [31:0] ram_adr_i;
+  wire [ 3:0] ram_sel_i;
+  wire        ram_we_i;
+  wire        ram_cyc_i;
+  wire        ram_stb_i;
+  wire        ram_ack_o;
+
+  // wires to Tube
+  wire [31:0] tube_dat_o;
+  wire [31:0] tube_dat_i;
+  wire [31:0] tube_adr_i;
+  wire [ 3:0] tube_sel_i;
+  wire        tube_we_i;
+  wire        tube_cyc_i;
+  wire        tube_stb_i;
+  wire        tube_ack_o;
+
+  // wires to default slave
+  wire        def_cyc_i;
+  wire        def_stb_i;
+  
+  wire [2:0]  p_addr;
+  wire        p_cs_b; 
+  wire [7:0]  p_data; 
+  wire        p_rd_b; 
+  wire        p_wr_b;
+  wire        p_rst_b;
+  wire        p_nmi_b;
+  wire        p_irq_b;
+
+  reg         irq;
+  reg         nmi;
+  
+  reg         gsr0;
+  reg         gsr1;
+  reg         gsr2;
+  
+  reg [8:0]   reset_counter = 0;
+  reg [8:0]   gsr_counter = 0;
+
+  wire [3:0]  sw_out;
+   
+  ICAP_config inst_ICAP_config (
+    .fastclk(fastclk),
+    .sw_in  (sw),
+    .sw_out (sw_out),
+    .h_addr (h_addr),
+    .h_cs_b (h_cs_b),
+    .h_data (h_data),
+    .h_phi2 (h_phi2),
+    .h_rdnw (h_rdnw),
+    .h_rst_b(h_rst_b)
+  );
+   
+  assign clk = fastclk;
+
+  always @(posedge clk)
+    begin
+      // Trigger a global reset when the parasite is reset (e.g. break is pressed)
+      // Delay this to allow any pending reconfiguration to happen
+      if (gsr_counter != 0)
+        gsr_counter <= gsr_counter + 1;
+      else if (!p_rst_b)
+        gsr_counter <= 1;
+      gsr0 <= gsr_counter[8];
+      gsr1 <= gsr0;
+      gsr2 <= !gsr1 && gsr0; // rising edge
+      // Ensure reset is held active for 256 clock cycles on power up
+      // Needed as Beeb's reset is missed when using multiboot loader as initialization takes too long
+      if (reset_counter[8] == 0)
+        reset_counter <= reset_counter + 1;
+  end
+    
+  wire rst = !reset_counter[8];
+
+  STARTUP_SPARTAN6 startup_inst (
+    .CFGCLK(),
+    .CFGMCLK(),                                 
+    .EOS(),
+    .CLK(),
+    .GSR(gsr2),
+    .GTS(),
+    .KEYCLEARB()
+  );
+
+  bootrom bootrom (
+    .clk (clk),            // Wishbone slave interface
+    .rst (rst),
+    .wb_dat_i (rom_dat_i),
+    .wb_dat_o (rom_dat_o),
+    .wb_adr_i (rom_adr_i),
+    .wb_we_i  (rom_we_i ),
+    .wb_stb_i (rom_stb_i),
+    .wb_cyc_i (rom_cyc_i),
+    .wb_sel_i (rom_sel_i),
+    .wb_ack_o (rom_ack_o)
+  );
+  
+wb_sram32 wb_sram32 (
+    .clk(clk), 
+    .reset(rst), 
+    .wb_dat_i(ram_dat_i), 
+    .wb_dat_o(ram_dat_o), 
+    .wb_adr_i(ram_adr_i), 
+    .wb_we_i(ram_we_i),
+    .wb_stb_i(ram_stb_i), 
+    .wb_cyc_i(ram_cyc_i), 
+    .wb_sel_i(ram_sel_i), 
+    .wb_ack_o(ram_ack_o),
+    
+    .sram_adr(ram_addr), 
+    .sram_dat(ram_data), 
+    .sram_be_n({ram_ub_b, ram_lb_b}), 
+    .sram_ce_n(ram_cs), 
+    .sram_oe_n(ram_oe), 
+    .sram_we_n(ram_wr)
+    );
+
+wb_tube wb_tube_inst(
+    .clk(clk), 
+    .reset(rst), 
+    .wb_stb_i(tube_stb_i), 
+    .wb_cyc_i(tube_cyc_i), 
+    .wb_ack_o(tube_ack_o), 
+    .wb_we_i(tube_we_i),
+    .wb_adr_i(tube_adr_i[4:2]), 
+    .wb_sel_i(tube_sel_i), 
+    .wb_dat_i(tube_dat_i), 
+    .wb_dat_o(tube_dat_o), 
+    .tube_adr(p_addr), 
+    .tube_dat(p_data), 
+    .tube_cs_n(p_cs_b), 
+    .tube_rd_n(p_rd_b), 
+    .tube_wr_n(p_wr_b)
+    );
+    
+tube tube_inst(
+    .h_addr(h_addr), 
+    .h_cs_b(h_cs_b), 
+    .h_data(h_data), 
+    .h_phi2(h_phi2), 
+    .h_rdnw(h_rdnw), 
+    .h_rst_b(h_rst_b), 
+    .h_irq_b(), 
+    .p_addr(p_addr), 
+    .p_cs_b(p_cs_b), 
+    .p_data(p_data),
+    .p_rdnw(p_wr_b), 
+    .p_phi2(clk), 
+    .p_rst_b(p_rst_b), 
+    .p_nmi_b(p_nmi_b), 
+    .p_irq_b(p_irq_b)
+    );
+
+// Instantiate the module
+a23_core amber (
+    .i_clk(clk), 
+    .i_irq(irq), 
+    .i_firq(nmi), 
+    .i_system_rdy(1'b1), 
+    .o_wb_adr(adr), 
+    .o_wb_sel(sel), 
+    .o_wb_we(we), 
+    .i_wb_dat(dat_i), 
+    .o_wb_dat(dat_o), 
+    .o_wb_cyc(cyc), 
+    .o_wb_stb(stb), 
+    .i_wb_ack(ack), 
+    .i_wb_err(1'b0) 
+    );
+    
+  wb_switch #(
+    .s0_addr_1 (32'b0000_0000_0000_0000_0000_0000_0000_0000), // ROM  at 0x00000000-0x00000003
+    .s0_mask_1 (32'b0000_0011_1111_1111_1111_1111_1111_1100),
+
+    .s0_addr_2 (32'b0000_0011_0000_0000_0000_0000_0000_0000), // ROM  at 0x03000000-0x03ffffff
+    .s0_mask_2 (32'b0000_0011_0000_0000_0000_0000_0000_0000),
+
+    .s1_addr_1 (32'b0000_0001_0000_0000_0000_0000_0000_0000), // Tube at 0x01000000-0x01ffffff
+    .s1_mask_1 (32'b0000_0011_0000_0000_0000_0000_0000_0000),
+
+    .s2_addr_1 (32'b0000_0000_0000_0000_0000_0000_0000_0000), // RAM  at 0x00000000-0x001fffff
+    .s2_mask_1 (32'b0000_0011_1110_0000_0000_0000_0000_0000)
+
+    ) wbs (
+
+    // Master interface
+    .m_dat_i (dat_o),
+    .m_dat_o (dat_i),
+    .m_adr_i (adr),
+    .m_sel_i (sel),
+    .m_we_i  (we),
+    .m_cyc_i (cyc),
+    .m_stb_i (stb),
+    .m_ack_o (ack),
+
+    // Slave 0 interface - ROM
+    .s0_dat_i (rom_dat_o),
+    .s0_dat_o (rom_dat_i),
+    .s0_adr_o (rom_adr_i),
+    .s0_sel_o (rom_sel_i),
+    .s0_we_o  (rom_we_i),
+    .s0_cyc_o (rom_cyc_i),
+    .s0_stb_o (rom_stb_i),
+    .s0_ack_i (rom_ack_o),
+
+    // Slave 1 interface - Tube
+    .s1_dat_i (tube_dat_o),
+    .s1_dat_o (tube_dat_i),
+    .s1_adr_o (tube_adr_i),
+    .s1_sel_o (tube_sel_i),
+    .s1_we_o  (tube_we_i),
+    .s1_cyc_o (tube_cyc_i),
+    .s1_stb_o (tube_stb_i),
+    .s1_ack_i (tube_ack_o),
+
+     // Slave 2 interface - RAM
+    .s2_dat_i (ram_dat_o),
+    .s2_dat_o (ram_dat_i),
+    .s2_adr_o (ram_adr_i),
+    .s2_sel_o (ram_sel_i),
+    .s2_we_o  (ram_we_i),
+    .s2_cyc_o (ram_cyc_i),
+    .s2_stb_o (ram_stb_i),
+    .s2_ack_i (ram_ack_o),
+
+    .s3_dat_i (32'haaaaaaaa),
+    .s3_dat_o (),
+    .s3_adr_o (),
+    .s3_sel_o (),
+    .s3_we_o  (),
+    .s3_cyc_o (def_cyc_i),
+    .s3_stb_o (def_stb_i),
+    .s3_ack_i (def_cyc_i & def_stb_i)
+  );
+
+  always @(posedge clk) begin
+    irq <= ~p_irq_b;
+    nmi <= ~p_nmi_b;
+  end
+
+  assign h_irq_b  = 1;
+
+  // default to hi-impedence, to avoid conflicts with
+  // a Raspberry Pi connected to the test connector
+  assign test = 8'bZ;
+
+endmodule
+"
+"/*
+ *  Microcode ROM for Zet
+ *  Copyright (C) 2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+`include ""defines.v""
+
+// altera message_off 10030
+//  get rid of the warning about
+//  not initializing the ROM
+
+module zet_micro_rom (
+    input [`MICRO_ADDR_WIDTH-1:0] addr,
+    output [`MICRO_DATA_WIDTH-1:0] q
+  );
+
+  // Registers, nets and parameters
+  reg [`MICRO_DATA_WIDTH-1:0] rom[0:2**`MICRO_ADDR_WIDTH-1];
+
+  // Assignments
+  assign q = rom[addr];
+
+  // Behaviour
+  initial $readmemb(""micro_rom.dat"", rom);
+endmodule
+"
+"/*
+ *  Bitwise logical operations for Zet
+ *  Copyright (C) 2008-2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+module zet_bitlog (
+    input  [15:0] x,
+    output [15:0] o,
+    output        cfo,
+    output        ofo
+  );
+
+  // Assignments
+  assign o = ~x;  // Now we only do NEG
+
+  assign cfo = 1'b0;
+  assign ofo = 1'b0;
+
+endmodule
+"
+"/*
+ *  Integer conversion module for Zet
+ *  Copyright (C) 2008-2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+module zet_conv (
+    input  [15:0] x,
+    input  [ 2:0] func,
+    output [31:0] out,
+    input  [ 1:0] iflags, // afi, cfi
+    output [ 2:0] oflags  // afo, ofo, cfo
+  );
+
+  // Net declarations
+  wire        afi, cfi;
+  wire        ofo, afo, cfo;
+  wire [15:0] aaa, aas;
+  wire [ 7:0] daa, tmpdaa, das, tmpdas;
+  wire [15:0] cbw, cwd;
+
+  wire        acond, dcond;
+  wire        tmpcf;
+
+  // Module instances
+  zet_mux8_16 mux8_16 (func, cbw, aaa, aas, 16'd0,
+                       cwd, {x[15:8], daa}, {x[15:8], das}, 16'd0, out[15:0]);
+
+  // Assignments
+  assign aaa = (acond ? (x + 16'h0106) : x) & 16'hff0f;
+  assign aas = (acond ? (x - 16'h0106) : x) & 16'hff0f;
+
+  assign tmpdaa = acond ? (x[7:0] + 8'h06) : x[7:0];
+  assign daa    = dcond ? (tmpdaa + 8'h60) : tmpdaa;
+  assign tmpdas = acond ? (x[7:0] - 8'h06) : x[7:0];
+  assign das    = dcond ? (tmpdas - 8'h60) : tmpdas;
+
+  assign               cbw   = { { 8{x[ 7]}}, x[7:0] };
+  assign { out[31:16], cwd } = { {16{x[15]}}, x      };
+
+  assign acond = ((x[7:0] & 8'h0f) > 8'h09) | afi;
+  assign dcond = (x[7:0] > 8'h99) | cfi;
+
+  assign afi = iflags[1];
+  assign cfi = iflags[0];
+
+  assign afo = acond;
+  assign ofo = 1'b0;
+  assign tmpcf = (x[7:0] < 8'h06) | cfi;
+  assign cfo = func[2] ? (dcond ? 1'b1 : (acond & tmpcf))
+             : acond;
+
+  assign oflags = { afo, ofo, cfo };
+endmodule
+"
+"//////////////////////////////////////////////////////////////////
+//                                                              //
+//  Execute stage of Amber 2 Core                               //
+//                                                              //
+//  This file is part of the Amber project                      //
+//  http://www.opencores.org/project,amber                      //
+//                                                              //
+//  Description                                                 //
+//  Executes instructions. Instantiates the register file, ALU  //
+//  multiplication unit and barrel shifter. This stage is       //
+//  relitively simple. All the complex stuff is done in the     //
+//  decode stage.                                               //
+//                                                              //
+//  Author(s):                                                  //
+//      - Conor Santifort, csantifort.amber@gmail.com           //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+//                                                              //
+// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
+//                                                              //
+// This source file may be used and distributed without         //
+// restriction provided that this copyright statement is not    //
+// removed from the file and that any derivative work contains  //
+// the original copyright notice and the associated disclaimer. //
+//                                                              //
+// This source file is free software; you can redistribute it   //
+// and/or modify it under the terms of the GNU Lesser General   //
+// Public License as published by the Free Software Foundation; //
+// either version 2.1 of the License, or (at your option) any   //
+// later version.                                               //
+//                                                              //
+// This source is distributed in the hope that it will be       //
+// useful, but WITHOUT ANY WARRANTY; without even the implied   //
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
+// PURPOSE.  See the GNU Lesser General Public License for more //
+// details.                                                     //
+//                                                              //
+// You should have received a copy of the GNU Lesser General    //
+// Public License along with this source; if not, download it   //
+// from http://www.opencores.org/lgpl.shtml                     //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+
+`include ""a23_config_defines.vh""
+
+module a23_execute (
+
+input                       i_clk,
+input       [31:0]          i_read_data,
+input       [4:0]           i_read_data_alignment,  // 2 LSBs of address in [4:3], appended 
+                                                    // with 3 zeros
+input       [31:0]          i_copro_read_data,      // From Co-Processor, to either Register 
+                                                    // or Memory
+input                       i_data_access_exec,     // from Instruction Decode stage
+                                                    // high means the memory access is a read 
+                                                    // read or write, low for instruction
+
+output reg  [31:0]          o_copro_write_data = \'d0,
+output reg  [31:0]          o_write_data = \'d0,
+output wire [31:0]          o_address,
+output reg                  o_adex = \'d0,           // Address Exception
+output reg                  o_address_valid = \'d0,  // Prevents the reset address value being a 
+                                                    // wishbone access
+output      [31:0]          o_address_nxt,          // un-registered version of address to the 
+                                                    // cache rams address ports
+output reg                  o_priviledged = \'d0,    // Priviledged access
+output reg                  o_exclusive = \'d0,      // swap access
+output reg                  o_write_enable = \'d0,
+output reg  [3:0]           o_byte_enable = \'d0,
+output reg                  o_data_access = \'d0,    // To Fetch stage. high = data fetch, 
+                                                    // low = instruction fetch
+output      [31:0]          o_status_bits,          // Full PC will all status bits, but PC part zero\'ed out
+output                      o_multiply_done,
+
+
+// --------------------------------------------------
+// Control signals from Instruction Decode stage
+// --------------------------------------------------
+input                       i_fetch_stall,          // stall all stages of the cpu at the same time
+input      [1:0]            i_status_bits_mode,
+input                       i_status_bits_irq_mask,
+input                       i_status_bits_firq_mask,
+input      [31:0]           i_imm32,
+input      [4:0]            i_imm_shift_amount,
+input                       i_shift_imm_zero,
+input      [3:0]            i_condition,
+input                       i_exclusive_exec,       // swap access
+input                       i_use_carry_in,         // e.g. add with carry instruction
+
+input      [3:0]            i_rm_sel,
+input      [3:0]            i_rds_sel,
+input      [3:0]            i_rn_sel,
+input      [3:0]            i_rm_sel_nxt,
+input      [3:0]            i_rds_sel_nxt,
+input      [3:0]            i_rn_sel_nxt,
+input      [1:0]            i_barrel_shift_amount_sel,
+input      [1:0]            i_barrel_shift_data_sel,
+input      [1:0]            i_barrel_shift_function,
+input      [8:0]            i_alu_function,
+input      [1:0]            i_multiply_function,
+input      [2:0]            i_interrupt_vector_sel,
+input      [3:0]            i_address_sel,
+input      [1:0]            i_pc_sel,
+input      [1:0]            i_byte_enable_sel,
+input      [2:0]            i_status_bits_sel,
+input      [2:0]            i_reg_write_sel,
+input                       i_user_mode_regs_load,
+input                       i_user_mode_regs_store_nxt,
+input                       i_firq_not_user_mode,
+
+input                       i_write_data_wen,
+input                       i_base_address_wen,     // save LDM base address register, 
+                                                    // in case of data abort
+input                       i_pc_wen,
+input      [14:0]           i_reg_bank_wen,
+input      [3:0]            i_reg_bank_wsel,
+input                       i_status_bits_flags_wen,
+input                       i_status_bits_mode_wen,
+input                       i_status_bits_irq_mask_wen,
+input                       i_status_bits_firq_mask_wen,
+input                       i_copro_write_data_wen
+
+);
+
+`include ""a23_localparams.vh""
+`include ""a23_functions.vh""
+
+// ========================================================
+// Internal signals
+// ========================================================
+wire [31:0]         write_data_nxt;
+wire [3:0]          byte_enable_nxt;
+wire [31:0]         pc_plus4;
+wire [31:0]         pc_minus4;
+wire [31:0]         address_plus4;
+wire [31:0]         alu_plus4;
+wire [31:0]         rn_plus4;
+wire [31:0]         alu_out;
+wire [3:0]          alu_flags;
+wire [31:0]         rm;
+wire [31:0]         rs;
+wire [31:0]         rd;
+wire [31:0]         rn;
+wire [31:0]         pc;
+wire [31:0]         pc_nxt;
+wire                write_enable_nxt;
+wire [31:0]         interrupt_vector;
+wire [7:0]          shift_amount;
+wire [31:0]         barrel_shift_in;
+wire [31:0]         barrel_shift_out;
+wire                barrel_shift_carry;
+wire                barrel_shift_carry_alu;
+
+wire [3:0]          status_bits_flags_nxt;
+reg  [3:0]          status_bits_flags = \'d0;
+wire [1:0]          status_bits_mode_nxt;
+wire [1:0]          status_bits_mode_nr;
+reg  [1:0]          status_bits_mode = SVC;
+                    // raw rs select
+wire [1:0]          status_bits_mode_rds_nxt;
+wire [1:0]          status_bits_mode_rds_nr;
+reg  [1:0]          status_bits_mode_rds;
+                    // one-hot encoded rs select
+wire [3:0]          status_bits_mode_rds_oh_nxt;
+reg  [3:0]          status_bits_mode_rds_oh = 1\'d1 << OH_SVC;
+wire                status_bits_mode_rds_oh_update;
+wire                status_bits_irq_mask_nxt;
+reg                 status_bits_irq_mask = 1\'d1;
+wire                status_bits_firq_mask_nxt;
+reg                 status_bits_firq_mask = 1\'d1;
+
+wire                execute;           // high when condition execution is true
+wire [31:0]         reg_write_nxt;
+wire                pc_wen;
+wire [14:0]         reg_bank_wen;
+wire [3:0]          reg_bank_wsel;
+wire [31:0]         multiply_out;
+wire [1:0]          multiply_flags;
+reg  [31:0]         base_address = \'d0;    // Saves base address during LDM instruction in 
+                                           // case of data abort
+
+wire                priviledged_nxt;      
+wire                priviledged_update;
+wire                address_update;
+wire                base_address_update;
+wire                write_data_update;
+wire                copro_write_data_update;
+wire                byte_enable_update;
+wire                data_access_update;
+wire                write_enable_update;
+wire                exclusive_update;
+wire                status_bits_flags_update;
+wire                status_bits_mode_update;
+wire                status_bits_irq_mask_update;
+wire                status_bits_firq_mask_update;
+wire [1:0]          status_bits_out;
+
+wire [31:0]         alu_out_pc_filtered;
+wire                adex_nxt;
+
+wire                carry_in;
+
+reg  [31:0]         address_r = 32\'hdead_dead;
+
+
+// ========================================================
+// Status Bits in PC register
+// ========================================================
+assign status_bits_out = (i_status_bits_mode_wen && i_status_bits_sel == 3\'d1 && execute) ? 
+                            alu_out[1:0] : status_bits_mode ;
+
+
+assign o_status_bits = {   status_bits_flags,           // 31:28
+                           status_bits_irq_mask,        // 7
+                           status_bits_firq_mask,       // 6
+                           24\'d0,
+                           status_bits_out};          // 1:0 = mode
+
+// ========================================================
+// Status Bits Select
+// ========================================================
+assign status_bits_flags_nxt     = i_status_bits_sel == 3\'d0 ? alu_flags                           :
+                                   i_status_bits_sel == 3\'d1 ? alu_out          [31:28]            :
+                                   i_status_bits_sel == 3\'d3 ? i_copro_read_data[31:28]            :
+                                   //  update flags after a multiply operation
+                                   i_status_bits_sel == 3\'d4 ? { multiply_flags, status_bits_flags[1:0] } :
+                                   // regops that do not change the overflow flag
+                                   i_status_bits_sel == 3\'d5 ? { alu_flags[3:1], status_bits_flags[0] } :
+                                                               4\'b1111 ;
+
+assign status_bits_mode_nxt      = i_status_bits_sel == 3\'d0 ? i_status_bits_mode       :
+                                   i_status_bits_sel == 3\'d5 ? i_status_bits_mode       :
+                                   i_status_bits_sel == 3\'d1 ? alu_out            [1:0] :
+                                                               i_copro_read_data  [1:0] ;
+
+
+// Used for the Rds output of register_bank - this special version of
+// status_bits_mode speeds up the critical path from status_bits_mode through the
+// register_bank, barrel_shifter and alu. It moves a mux needed for the
+// i_user_mode_regs_store_nxt signal back into the previous stage -
+// so its really part of the decode stage even though the logic is right here
+// In addition the signal is one-hot encoded to further speed up the logic
+// Raw version is also kept for ram-based register bank implementation.
+
+assign status_bits_mode_rds_nxt  = i_user_mode_regs_store_nxt ? USR                  :
+                                   status_bits_mode_update    ? status_bits_mode_nxt :
+                                                                status_bits_mode     ;
+
+assign status_bits_mode_rds_oh_nxt    = oh_status_bits_mode(status_bits_mode_rds_nxt);
+
+
+assign status_bits_irq_mask_nxt  = i_status_bits_sel == 3\'d0 ? i_status_bits_irq_mask      :
+                                   i_status_bits_sel == 3\'d5 ? i_status_bits_irq_mask      :
+                                   i_status_bits_sel == 3\'d1 ? alu_out                [27] :
+                                                               i_copro_read_data      [27] ;
+                            
+assign status_bits_firq_mask_nxt = i_status_bits_sel == 3\'d0 ? i_status_bits_firq_mask     :
+                                   i_status_bits_sel == 3\'d5 ? i_status_bits_firq_mask     :
+                                   i_status_bits_sel == 3\'d1 ? alu_out                [26] :
+                                                               i_copro_read_data      [26] ;
+
+
+
+// ========================================================
+// Adders
+// ========================================================
+assign pc_plus4      = pc        + 32\'d4;
+assign pc_minus4     = pc        - 32\'d4;
+assign address_plus4 = address_r + 32\'d4;
+assign alu_plus4     = alu_out   + 32\'d4;
+assign rn_plus4      = rn        + 32\'d4;
+
+
+// ========================================================
+// Barrel Shift Amount Select
+// ========================================================
+// An immediate shift value of 0 is translated into 32
+assign shift_amount = i_barrel_shift_amount_sel == 2\'d0 ? 8\'d0                           :
+                      i_barrel_shift_amount_sel == 2\'d1 ? rs[7:0]                        :
+                      i_barrel_shift_amount_sel == 2\'d2 ? {3\'d0, i_imm_shift_amount    } :
+                                                          {3\'d0, i_read_data_alignment } ;
+
+// ========================================================
+// Barrel Shift Data Select
+// ========================================================
+assign barrel_shift_in = i_barrel_shift_data_sel == 2\'d0 ? i_imm32       :
+                         i_barrel_shift_data_sel == 2\'d1 ? i_read_data   :
+                                                           rm            ;
+                            
+// ========================================================
+// Interrupt vector Select
+// ========================================================
+
+assign interrupt_vector = // Reset vector
+                          (i_interrupt_vector_sel == 3\'d0) ? 32\'h00000000 :  
+                          // Data abort interrupt vector                 
+                          (i_interrupt_vector_sel == 3\'d1) ? 32\'h00000010 :
+                          // Fast interrupt vector  
+                          (i_interrupt_vector_sel == 3\'d2) ? 32\'h0000001c :
+                          // Regular interrupt vector
+                          (i_interrupt_vector_sel == 3\'d3) ? 32\'h00000018 :
+                          // Prefetch abort interrupt vector
+                          (i_interrupt_vector_sel == 3\'d5) ? 32\'h0000000c :
+                          // Undefined instruction interrupt vector
+                          (i_interrupt_vector_sel == 3\'d6) ? 32\'h00000004 :
+                          // Software (SWI) interrupt vector
+                          (i_interrupt_vector_sel == 3\'d7) ? 32\'h00000008 :
+                          // Default is the address exception interrupt
+                                                             32\'h00000014 ;
+
+
+// ========================================================
+// Address Select
+// ========================================================
+
+// If rd is the pc, then seperate the address bits from the status bits for
+// generating the next address to fetch
+assign alu_out_pc_filtered = pc_wen && i_pc_sel == 2\'d1 ? pcf(alu_out) : alu_out;
+
+// if current instruction does not execute because it does not meet the condition
+// then address advances to next instruction
+assign o_address_nxt = (!execute)              ? pc_plus4              : 
+                       (i_address_sel == 4\'d0) ? pc_plus4              :
+                       (i_address_sel == 4\'d1) ? alu_out_pc_filtered   :
+                       (i_address_sel == 4\'d2) ? interrupt_vector      :
+                       (i_address_sel == 4\'d3) ? pc                    :
+                       (i_address_sel == 4\'d4) ? rn                    :
+                       (i_address_sel == 4\'d5) ? address_plus4         :  // MTRANS address incrementer
+                       (i_address_sel == 4\'d6) ? alu_plus4             :  // MTRANS decrement after
+                                                 rn_plus4              ;  // MTRANS increment before
+
+// Data accesses use 32-bit address space, but instruction
+// accesses are restricted to 26 bit space
+assign adex_nxt      = |o_address_nxt[31:26] && !i_data_access_exec;
+
+// ========================================================
+// Program Counter Select
+// ========================================================
+// If current instruction does not execute because it does not meet the condition
+// then PC advances to next instruction
+assign pc_nxt = (!execute)       ? pc_plus4              :
+                i_pc_sel == 2\'d0 ? pc_plus4              :
+                i_pc_sel == 2\'d1 ? alu_out               :
+                                   interrupt_vector      ;
+
+
+// ========================================================
+// Register Write Select
+// ========================================================
+wire [31:0] save_int_pc;
+wire [31:0] save_int_pc_m4;
+
+assign save_int_pc    = { status_bits_flags, 
+                          status_bits_irq_mask, 
+                          status_bits_firq_mask, 
+                          pc[25:2], 
+                          status_bits_mode      };
+
+
+assign save_int_pc_m4 = { status_bits_flags, 
+                          status_bits_irq_mask, 
+                          status_bits_firq_mask, 
+                          pc_minus4[25:2], 
+                          status_bits_mode      };
+
+
+assign reg_write_nxt = i_reg_write_sel == 3\'d0 ? alu_out               :
+                       // save pc to lr on an interrupt                    
+                       i_reg_write_sel == 3\'d1 ? save_int_pc_m4        :
+                       // to update Rd at the end of Multiplication
+                       i_reg_write_sel == 3\'d2 ? multiply_out          :
+                       i_reg_write_sel == 3\'d3 ? o_status_bits         :
+                       i_reg_write_sel == 3\'d5 ? i_copro_read_data     :  // mrc
+                       i_reg_write_sel == 3\'d6 ? base_address          :
+                                                 save_int_pc           ;  
+
+
+// ========================================================
+// Byte Enable Select
+// ========================================================
+assign byte_enable_nxt = i_byte_enable_sel == 2\'d0  ? 4\'b1111 :  // word write
+                         i_byte_enable_sel == 2\'d2  ?            // halfword write
+                         ( o_address_nxt[1] == 1\'d0 ? 4\'b0011 : 
+                                                      4\'b1100  ) :
+                           
+                         o_address_nxt[1:0] == 2\'d0 ? 4\'b0001 :  // byte write
+                         o_address_nxt[1:0] == 2\'d1 ? 4\'b0010 :
+                         o_address_nxt[1:0] == 2\'d2 ? 4\'b0100 :
+                                                      4\'b1000 ;
+
+
+// ========================================================
+// Write Data Select
+// ========================================================
+assign write_data_nxt = i_byte_enable_sel == 2\'d0 ? rd            :
+                                                    {4{rd[ 7:0]}} ;
+
+
+// ========================================================
+// Conditional Execution
+// ========================================================
+assign execute = conditional_execute ( i_condition, status_bits_flags );
+            
+// allow the PC to increment to the next instruction when current
+// instruction does not execute
+assign pc_wen       = i_pc_wen || !execute;
+
+// only update register bank if current instruction executes
+assign reg_bank_wen = {{15{execute}} & i_reg_bank_wen};
+
+assign reg_bank_wsel = {{4{~execute}} | i_reg_bank_wsel};
+
+
+// ========================================================
+// Priviledged output flag
+// ========================================================
+// Need to look at status_bits_mode_nxt so switch to priviledged mode
+// at the same time as assert interrupt vector address
+assign priviledged_nxt  = ( i_status_bits_mode_wen ? status_bits_mode_nxt : status_bits_mode ) != USR ;
+
+
+// ========================================================
+// Write Enable
+// ========================================================
+// This must be de-asserted when execute is fault
+assign write_enable_nxt = execute && i_write_data_wen;
+
+
+// ========================================================
+// Register Update
+// ========================================================
+
+assign priviledged_update              = !i_fetch_stall;       
+assign data_access_update              = !i_fetch_stall && execute;
+assign write_enable_update             = !i_fetch_stall;
+assign write_data_update               = !i_fetch_stall && execute && i_write_data_wen;
+assign exclusive_update                = !i_fetch_stall && execute;
+assign address_update                  = !i_fetch_stall;
+assign byte_enable_update              = !i_fetch_stall && execute && i_write_data_wen;
+assign copro_write_data_update         = !i_fetch_stall && execute && i_copro_write_data_wen;
+
+assign base_address_update             = !i_fetch_stall && execute && i_base_address_wen; 
+assign status_bits_flags_update        = !i_fetch_stall && execute && i_status_bits_flags_wen;
+assign status_bits_mode_update         = !i_fetch_stall && execute && i_status_bits_mode_wen;
+assign status_bits_mode_rds_oh_update  = !i_fetch_stall;
+assign status_bits_irq_mask_update     = !i_fetch_stall && execute && i_status_bits_irq_mask_wen;
+assign status_bits_firq_mask_update    = !i_fetch_stall && execute && i_status_bits_firq_mask_wen;
+
+assign status_bits_mode_rds_nr         =  status_bits_mode_rds_oh_update ? status_bits_mode_rds_nxt :
+                                                                           status_bits_mode_rds     ;
+
+assign status_bits_mode_nr             =  status_bits_mode_update        ? status_bits_mode_nxt     :
+                                                                           status_bits_mode         ;
+
+always @( posedge i_clk )
+    begin                                                                                                             
+    o_priviledged           <= priviledged_update             ? priviledged_nxt              : o_priviledged;
+    o_exclusive             <= exclusive_update               ? i_exclusive_exec             : o_exclusive;
+    o_data_access           <= data_access_update             ? i_data_access_exec           : o_data_access;
+    o_write_enable          <= write_enable_update            ? write_enable_nxt             : o_write_enable;
+    o_write_data            <= write_data_update              ? write_data_nxt               : o_write_data; 
+    address_r               <= address_update                 ? o_address_nxt                : address_r;    
+    o_adex                  <= address_update                 ? adex_nxt                     : o_adex;    
+    o_address_valid         <= address_update                 ? 1\'d1                         : o_address_valid;
+    o_byte_enable           <= byte_enable_update             ? byte_enable_nxt              : o_byte_enable;
+    o_copro_write_data      <= copro_write_data_update        ? write_data_nxt               : o_copro_write_data; 
+
+    base_address            <= base_address_update            ? rn                           : base_address;    
+
+    status_bits_flags       <= status_bits_flags_update       ? status_bits_flags_nxt        : status_bits_flags;
+    status_bits_mode        <=  status_bits_mode_nr;
+    status_bits_mode_rds_oh <= status_bits_mode_rds_oh_update ? status_bits_mode_rds_oh_nxt  : status_bits_mode_rds_oh;
+    status_bits_mode_rds    <= status_bits_mode_rds_nr;
+    status_bits_irq_mask    <= status_bits_irq_mask_update    ? status_bits_irq_mask_nxt     : status_bits_irq_mask;
+    status_bits_firq_mask   <= status_bits_firq_mask_update   ? status_bits_firq_mask_nxt    : status_bits_firq_mask;
+    end
+
+assign o_address = address_r;
+
+
+// ========================================================
+// Instantiate Barrel Shift
+// ========================================================
+
+assign carry_in = i_use_carry_in ? status_bits_flags[1] : 1\'d0;
+
+`ifndef ALTERA_FPGA
+a23_barrel_shift u_barrel_shift  (
+`else
+a23_barrel_shift_fpga u_barrel_shift  (
+`endif
+    .i_in             ( barrel_shift_in           ),
+    .i_carry_in       ( carry_in                  ),
+    .i_shift_amount   ( shift_amount              ),
+    .i_shift_imm_zero ( i_shift_imm_zero          ),
+    .i_function       ( i_barrel_shift_function   ),
+
+    .o_out            ( barrel_shift_out          ),
+    .o_carry_out      ( barrel_shift_carry        ));
+
+
+
+// ========================================================
+// Instantiate ALU
+// ========================================================
+assign barrel_shift_carry_alu =  i_barrel_shift_data_sel == 2\'d0 ? 
+                                  (i_imm_shift_amount[4:1] == 0 ? status_bits_flags[1] : i_imm32[31]) : 
+                                   barrel_shift_carry;
+
+a23_alu u_alu (
+    .i_a_in                 ( rn                      ),
+    .i_b_in                 ( barrel_shift_out        ),
+    .i_barrel_shift_carry   ( barrel_shift_carry_alu  ),
+    .i_status_bits_carry    ( status_bits_flags[1]    ),
+    .i_function             ( i_alu_function          ),
+  
+    .o_out                  ( alu_out                 ),
+    .o_flags                ( alu_flags               ));
+
+
+
+// ========================================================
+// Instantiate Booth 64-bit Multiplier-Accumulator
+// ========================================================
+a23_multiply u_multiply (
+    .i_clk          ( i_clk                 ),
+    .i_fetch_stall  ( i_fetch_stall         ),
+    .i_a_in         ( rs                    ),
+    .i_b_in         ( rm                    ),
+    .i_function     ( i_multiply_function   ),
+    .i_execute      ( execute               ),
+    .o_out          ( multiply_out          ),
+    .o_flags        ( multiply_flags        ),  // [1] = N, [0] = Z
+    .o_done         ( o_multiply_done       )     
+);
+
+
+// ========================================================
+// Instantiate Register Bank
+// ========================================================
+`ifndef A23_RAM_REGISTER_BANK
+a23_register_bank u_register_bank(
+    .i_clk                   ( i_clk                     ),
+    .i_fetch_stall           ( i_fetch_stall             ),
+    .i_rm_sel                ( i_rm_sel                  ),
+    .i_rds_sel               ( i_rds_sel                 ),
+    .i_rn_sel                ( i_rn_sel                  ),
+    .i_pc_wen                ( pc_wen                    ),
+    .i_reg_bank_wen          ( reg_bank_wen              ),
+    .i_pc                    ( pc_nxt[25:2]              ),
+    .i_reg                   ( reg_write_nxt             ),
+    .i_mode_idec             ( i_status_bits_mode        ),
+    .i_mode_exec             ( status_bits_mode          ),
+
+    .i_status_bits_flags     ( status_bits_flags         ),
+    .i_status_bits_irq_mask  ( status_bits_irq_mask      ),
+    .i_status_bits_firq_mask ( status_bits_firq_mask     ),
+
+    // pre-encoded in decode stage to speed up long path
+    .i_firq_not_user_mode    ( i_firq_not_user_mode      ),
+    
+    // use one-hot version for speed, combine with i_user_mode_regs_store
+    .i_mode_rds_exec         ( status_bits_mode_rds_oh   ),  
+    
+    .i_user_mode_regs_load   ( i_user_mode_regs_load     ),
+    .o_rm                    ( rm                        ),
+    .o_rs                    ( rs                        ),
+    .o_rd                    ( rd                        ),
+    .o_rn                    ( rn                        ),
+    .o_pc                    ( pc                        )
+);
+`else
+a23_ram_register_bank u_register_bank(
+    .i_clk                   ( i_clk                     ),
+    .i_fetch_stall           ( i_fetch_stall             ),
+    .i_rm_sel                ( i_rm_sel_nxt              ),
+    .i_rds_sel               ( i_rds_sel_nxt             ),
+    .i_rn_sel                ( i_rn_sel_nxt              ),
+    .i_pc_wen                ( pc_wen                    ),
+    .i_reg_bank_wsel         ( reg_bank_wsel             ),
+    .i_pc                    ( pc_nxt[25:2]              ),
+    .i_reg                   ( reg_write_nxt             ),
+
+    .i_mode_exec_nxt         ( status_bits_mode_nr       ),
+    .i_mode_exec             ( status_bits_mode          ),
+    .i_mode_rds_exec         ( status_bits_mode_rds_nr   ),
+    .i_user_mode_regs_load   ( i_user_mode_regs_load     ),
+
+    .i_status_bits_flags     ( status_bits_flags         ),
+    .i_status_bits_irq_mask  ( status_bits_irq_mask      ),
+    .i_status_bits_firq_mask ( status_bits_firq_mask     ),
+
+    .o_rm                    ( rm                        ),
+    .o_rs                    ( rs                        ),
+    .o_rd                    ( rd                        ),
+    .o_rn                    ( rn                        ),
+    .o_pc                    ( pc                        )
+);
+`endif
+
+// ========================================================
+// Debug - non-synthesizable code
+// ========================================================
+//synopsys translate_off
+
+wire    [(2*8)-1:0]    xCONDITION;
+wire    [(4*8)-1:0]    xMODE;
+
+assign  xCONDITION           = i_condition == EQ ? ""EQ""  :
+                               i_condition == NE ? ""NE""  :
+                               i_condition == CS ? ""CS""  :
+                               i_condition == CC ? ""CC""  :
+                               i_condition == MI ? ""MI""  :
+                               i_condition == PL ? ""PL""  :
+                               i_condition == VS ? ""VS""  :
+                               i_condition == VC ? ""VC""  :
+                               i_condition == HI ? ""HI""  :
+                               i_condition == LS ? ""LS""  :
+                               i_condition == GE ? ""GE""  :
+                               i_condition == LT ? ""LT""  :
+                               i_condition == GT ? ""GT""  :
+                               i_condition == LE ? ""LE""  :
+                               i_condition == AL ? ""AL""  :
+                                                   ""NV "" ;
+
+assign  xMODE  =  status_bits_mode == SVC  ? ""SVC""  :
+                  status_bits_mode == IRQ  ? ""IRQ""  :
+                  status_bits_mode == FIRQ ? ""FIRQ"" :
+                  status_bits_mode == USR  ? ""USR""  :
+                                             ""XXX""  ;
+                                             
+
+//synopsys translate_on
+
+endmodule
+
+
+"
+"// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+// This file is part of the M32632 project\r
+// http://opencores.org/project,m32632\r
+//\r
+// Filename: DP_FPU.v\r
+// Version:  1.0\r
+// Date:     30 May 2015\r
+//\r
+// Copyright (C) 2015 Udo Moeller\r
+// \r
+// This source file may be used and distributed without \r
+// restriction provided that this copyright statement is not \r
+// removed from the file and that any derivative work contains \r
+// the original copyright notice and the associated disclaimer.\r
+// \r
+// This source file is free software; you can redistribute it \r
+// and/or modify it under the terms of the GNU Lesser General \r
+// Public License as published by the Free Software Foundation;\r
+// either version 2.1 of the License, or (at your option) any \r
+// later version. \r
+// \r
+// This source is distributed in the hope that it will be \r
+// useful, but WITHOUT ANY WARRANTY; without even the implied \r
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR \r
+// PURPOSE. See the GNU Lesser General Public License for more \r
+// details. \r
+// \r
+// You should have received a copy of the GNU Lesser General \r
+// Public License along with this source; if not, download it \r
+// from http://www.opencores.org/lgpl.shtml \r
+// \r
+// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\tModules contained in this file:\r
+//\t1. PREPDATA  \tPrepare data for the big multiplier\r
+//\t2. BCDADDER  \t4 bit BCD adder\r
+//\t3. DFPU_BCD\t\tBinary coded decimal (BCD) adder and subtractor\r
+//\t4. DFPU_ADDSUB\tDouble precision floating point adder and subtractor\r
+//\t5. DFPU_MISC\tDouble precision floating point miscellaneous operations \r
+//\t6. DFPU_MUL\t\tDouble precision floating point multiplier\r
+//\t7. DIVI_PREP\tPrepare data for the divider\r
+//\t8. DFPU_DIV\t\tThe divider for all divide opcodes : double, single and integer\r
+//\t9. DP_LOGIK\t\tControl logic and result path for different functions\r
+// 10. DP_FPU\t\tTop level of long operations datapath\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t1. PREPDATA  \tPrepare data for the big multiplier\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module PREPDATA ( START, MEI, DFLOAT, BWD, SRC1, SRC2,\r
+\t\t\t\t  MSD_1, MSD_2, LSD_1, LSD_2, LOAD_MSD, LOAD_LSD1, LOAD_LSD2 );\r
+\r
+\tinput\t [1:0]\tSTART;\r
+\tinput\t\t\tMEI,DFLOAT;\r
+\tinput\t [1:0]\tBWD;\r
+\tinput\t[31:0]\tSRC1,SRC2;\r
+\t\r
+\toutput [52:32]\tMSD_1,MSD_2;\r
+\toutput\t[31:0]\tLSD_1,LSD_2;\r
+\toutput\t\t\tLOAD_MSD,LOAD_LSD1,LOAD_LSD2;\r
+\r
+\treg\t\t[31:0]\tLSD_1,LSD_2;\r
+\t\r
+\tassign MSD_1 = MEI ? 21\'h0 : {1\'b1,SRC1[19:0]};\t  \r
+\tassign MSD_2 = MEI ? 21\'h0 : {1\'b1,SRC2[19:0]};\r
+\t\r
+\talways @(MEI or BWD or SRC1)\r
+\t\tcasex ({MEI,BWD})\r
+\t\t  3\'b100 : LSD_1 = {24\'h000000,SRC1[7:0]};\r
+\t\t  3\'b101 : LSD_1 = {16\'h0000,SRC1[15:0]};\r
+\t\t default : LSD_1 = SRC1;\r
+\t\tendcase\r
+\t\r
+\talways @(MEI or BWD or SRC2)\r
+\t\tcasex ({MEI,BWD})\r
+\t\t  3\'b100 : LSD_2 = {24\'h000000,SRC2[7:0]};\r
+\t\t  3\'b101 : LSD_2 = {16\'h0000,SRC2[15:0]};\r
+\t\t default : LSD_2 = SRC2;\r
+\t\tendcase\r
+\r
+\tassign LOAD_MSD  = (START[0] & MEI) | (START[0] & DFLOAT);\t// 1. step data load at DFLOAT\r
+\tassign LOAD_LSD1 = (START[0] & MEI) | (START[1] & DFLOAT);\t// 2. step execute at DFLOAT\r
+\tassign LOAD_LSD2 = (START[1] & MEI) | (START[1] & DFLOAT);\t// 2. step execute at DFLOAT\r
+\t\r
+endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t2. BCDADDER  \t4 bit BCD adder\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module BCDADDER ( A_IN, B_IN, CY_IN, SUBP, OUT, CY_OUT );\r
+\r
+\tinput\t [3:0]\tA_IN,B_IN;\r
+\tinput\t\t\tCY_IN;\r
+\tinput\t\t\tSUBP;\r
+\t\r
+\toutput\t [3:0]\tOUT;\r
+\toutput\t\t\tCY_OUT;\r
+\t\r
+\twire\t [4:0]\tresult;\r
+\twire\t\t\tover;\r
+\t\r
+\tassign result = SUBP ? ({1\'b0,A_IN} - {1\'b0,B_IN} - {4\'b0,CY_IN})\r
+\t\t\t\t\t\t : ({1\'b0,A_IN} + {1\'b0,B_IN} + {4\'b0,CY_IN});\r
+\r
+\tassign over = result[4] | (result[3] & (result[2] | result[1]));\r
+\t\r
+\t\t\t\t\t\t\t\t//\t\tif result<0 : -6\t\t\t\tif result>9 : -10\r
+\tassign OUT = result[3:0] - (SUBP ? {1\'b0,result[4],result[4],1\'b0} : {over,1\'b0,over,1\'b0});\r
+\tassign CY_OUT = SUBP ? result[4] : over;\r
+\t\r
+endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t3. DFPU_BCD\t\tBinary coded decimal (BCD) adder and subtractor\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module DFPU_BCD ( BCLK, BRESET, START, DO_BCD, BWD, SRC1, SRC2, CY_IN, SUBP, BCD_Q, CY_OUT, BCD_DONE );\r
+\r
+\t// Byte : 3 cycles in shortest case REG-REG, Word : 4 cycles and Double : 6 cycles\r
+\tinput\t\t\tBCLK;\r
+\tinput\t\t\tBRESET;\r
+\tinput\t\t\tSTART;\t// START[1]\r
+\tinput\t\t\tDO_BCD;\t// BCD Opcode is valid\r
+\tinput\t [1:0]\tBWD;\r
+\tinput\t[31:0]\tSRC1,SRC2;\t// Source , Destination, data is stable during operation\r
+\tinput\t\t\tCY_IN;\t// comes from PSR\r
+\tinput\t\t\tSUBP;\t// SUBP = 1 : SUBP , 0 : ADDP\r
+\t\r
+\toutput\treg\t[31:0]\tBCD_Q;\r
+\toutput\treg\t\tCY_OUT;\t// went to PSR if DONE is valid\r
+\toutput\t\t\tBCD_DONE;\r
+\t\r
+\treg\t\t\t\trun_bcd;\r
+\treg\t\t [1:0]\tbyte_cou;\r
+\treg\t\t[15:0]\tdatain;\r
+\t\r
+\twire\t [7:0]\tresult;\r
+\twire\t\t\tcarry,carry_lsd,carry_msd;\r
+\t\r
+\t// START :     _/---\\________________\r
+\t// byte_cou :  xxxxxx 0 x 1 x 2 x 3 x\r
+\t// BCD_DONE :  _____/---\\____________  if BWD = Byte\r
+\t\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) run_bcd <= 1\'b0;\r
+\t\t  else\r
+\t\t\trun_bcd <= (START & DO_BCD) | (run_bcd & (BWD != byte_cou));\r
+\t\r
+\talways @(posedge BCLK) byte_cou <= START ? 2\'d0 : byte_cou + {1\'b0,run_bcd};\r
+\t\r
+\talways @(*)\r
+\t\tcasex ({START,byte_cou})\r
+\t\t  3\'b1_xx : datain = {SRC1[7:0],  SRC2[7:0]};\r
+\t\t  3\'b0_00 : datain = {SRC1[15:8], SRC2[15:8]};\r
+\t\t  3\'b0_01 : datain = {SRC1[23:16],SRC2[23:16]};\r
+\t\t  3\'b0_1x : datain = {SRC1[31:24],SRC2[31:24]};\r
+\t\tendcase\r
+\t\t\r
+\tassign carry = START ? CY_IN : CY_OUT;\r
+\t\r
+\tBCDADDER\tlsd_inst ( .A_IN(datain[3:0]), .B_IN(datain[11:8]), .CY_IN(carry), .SUBP(SUBP),\r
+\t\t\t\t\t\t   .OUT(result[3:0]), .CY_OUT(carry_lsd) );\r
+\t\t\t\t\t\t   \r
+\tBCDADDER\tmsd_inst ( .A_IN(datain[7:4]), .B_IN(datain[15:12]), .CY_IN(carry_lsd), .SUBP(SUBP),\r
+\t\t\t\t\t\t   .OUT(result[7:4]), .CY_OUT(carry_msd) );\r
+\t\t\t\t\t\t   \r
+\talways @(posedge BCLK) CY_OUT <= carry_msd;\r
+\t\r
+\talways @(posedge BCLK) if (START)\t\t\t BCD_Q[7:0]   <= result;\r
+\talways @(posedge BCLK) if (byte_cou == 2\'d0) BCD_Q[15:8]  <= result;\r
+\talways @(posedge BCLK) if (byte_cou == 2\'d1) BCD_Q[23:16] <= result;\r
+\talways @(posedge BCLK) if (byte_cou[1])\t\t BCD_Q[31:24] <= result;\r
+\t\r
+\tassign BCD_DONE = run_bcd & (BWD == byte_cou);\r
+\r
+endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t4. DFPU_ADDSUB\tDouble precision floating point adder and subtractor\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//module DFPU_ADDSUB ( BCLK, START, SRC1, SRC2, MAN1, MAN2, SRCFLAGS, BWD, SELECT, OUT, IOUT, CMPRES );\r
+//\r
+//\tinput \t\t\tBCLK;\r
+//\tinput\t [1:0]\tSTART;\r
+//\tinput\t[31:0]\tSRC1,SRC2;\t// The input data\r
+//\tinput\t[20:0]\tMAN1,MAN2;\r
+//\tinput\t [5:0]\tSRCFLAGS;\t// NAN, ZERO and SIGN of operands\r
+//\tinput\t [1:0]\tBWD;\t\t// size of integer\r
+//\tinput\t [3:0]\tSELECT;\t\t// upper 2 bits : R.T.F. code\r
+//\t\r
+//\toutput\t[69:0]\tOUT;\r
+//\toutput\t[31:0]\tIOUT;\t\t// result of ROUNDLi/TRUNCLi/FLOORLi = R.T.F.\r
+//\toutput\t[1:0]\tCMPRES;\r
+//\r
+//\treg\t\t[69:0]\toutreg;\r
+//\treg\t\t[31:0]\tIOUT;\r
+//\r
+//\t// MOViL   : 2 cycles\r
+//\t// ROUNDLi : 3 cycles (+TRUNC & FLOOR)\r
+//\t// ADD/SUB : 4 cycles\r
+//\t// CMP     : 2 cycles\r
+//\t\t\t\r
+//\t// ++++++++++++++++++++++++++++++++++\r
+//\t// MOViL : 1. Pipeline stage : needs 3 cycles\r
+//\t\r
+//\treg  [31:8]\tmovdat;\r
+//\treg\t [31:0]\tmovif;\r
+//\treg\t\t\tsign_movif;\r
+//\r
+//\talways @(BWD or SRC1)\r
+//\t\tcasex({BWD,SRC1[15],SRC1[7]})\r
+//\t\t  4\'b00x0 : movdat =  24\'h0000_00;\t\t\t\t// Byte\r
+//\t\t  4\'b00x1 : movdat =  24\'hFFFF_FF;\r
+//\t\t  4\'b010x : movdat = {16\'h0000,SRC1[15:8]};\t\t// Word\r
+//\t\t  4\'b011x : movdat = {16\'hFFFF,SRC1[15:8]};\r
+//\t\tdefault   : movdat = SRC1[31:8];\t\t\t\t// Double\r
+//\t\tendcase\r
+//\t\r
+//\t// This  pipeline stage for better timing \r
+//\talways @(posedge BCLK) movif <= movdat[31] ? (32\'h0 - {movdat,SRC1[7:0]}) : {movdat,SRC1[7:0]};\t// -2^31 is kept !\r
+//\t\r
+//\talways @(posedge BCLK) sign_movif <= movdat[31];\r
+//\t\r
+//\t// ROUNDLi/TRUNCLi/FLOORLi : 1. pipeline stage : can Opcode-Decoder deliver direct the 64 bit operand ? From register ""yes""\r
+//\t\r
+//\treg\t\t\tovflag,ovflag2;\r
+//\treg\t\t\trovfl;\r
+//\treg\t\t\tminint;\r
+//\twire [11:0]\trexdiff,rexo;\r
+//\twire \t\tganzklein;\t// Flag for 0\r
+//\t\r
+//\tassign rexdiff = 12\'h41D - {1\'b0,SRC1[30:20]};\t// 4..0 is the right shift value : like Single FP same value space\r
+//\t\r
+//\t// ovflag2 at the end of rounding : Check for Overflow\r
+//\talways @(posedge BCLK) rovfl <= (ovflag | ovflag2) & (SELECT[1:0] == 2\'b11) & ~minint;\r
+//\t\r
+//\t// a large positiv difference is a very small number :\r
+//\tassign ganzklein = (~rexdiff[11] & (rexdiff[10:5] != 6\'b0));\t// 0 is implicit via SRC1[30:20]=0\r
+//\t\r
+//\t// Detection of Overflow\r
+//\tassign rexo = ({1\'b0,SRC1[30:20]} - {11\'h1FF,~BWD[1]});\t// subtract B/W = 3FF , D = 3FE\r
+//\t\r
+//\talways @(BWD or rexo)\t// 0 ist in implicitly\r
+//\t\tcasex (BWD)\r
+//\t\t  2\'b00 : ovflag = (~rexo[11] & (rexo[10:3] != 8\'h0));\t// Exponent 0..7 because -128.4 => -128\r
+//\t\t  2\'b01 : ovflag = (~rexo[11] & (rexo[10:4] != 7\'h0));\t// Exponent 0..15 look above\r
+//\t\tdefault : ovflag = (~rexo[11] & (rexo[10:5] != 6\'h0));\t// but Exponent only 0..30\r
+//\t\tendcase\r
+//\t\t\r
+//\talways @(posedge BCLK)\r
+//\t\tif (START[1]) minint <= (SRC1 == 32\'hC1E0_0000) & (SRC2 == 32\'h0) & BWD[1];\t// detection of -2^31\r
+//\t\r
+//\t// ++++++++++++++++++++++++++++++++++++\r
+//\t// ADD/SUB : 1. Pipeline Stage : which operand ist bigger ? Exchange if neccessary\r
+//\t// SUB/CMP : SRC2 - SRC1\r
+//\t\r
+//\treg\t\t\t\tex_null,ma_null,ex_msb,ma_msb;\r
+//\treg\t\t[10:0]\texpo1,expo2;\r
+//\twire\t[11:0]\texdiff,exdiff12;\r
+//\twire\t[20:0]\tmadiff;\r
+//\twire\t\t\tswitch,nan,sign,sign1,sign2;\r
+//\treg\t\t [5:0]\tshift1,shift2;\r
+//\r
+//\t\t// Pipeline register :\r
+//\treg\t\t[63:0]\tmuxsrc2;\r
+//\treg\t\t[55:3]\tpipe1;\t// Nummbers for right shifter\r
+//\treg  \t [5:0]\tshift;\r
+//\treg\t\t\t\tvorz,addflag;\r
+//\r
+//\twire\t[52:0]\tmuxsrc1;\r
+//\twire\t[32:0]\tlowdiff;\r
+//\t\r
+//\tassign nan = (SELECT[1:0] == 2\'b11) ? SRCFLAGS[1] : (~SELECT[1] & (SRCFLAGS[3] | SRCFLAGS[1]));\t// used at the end\r
+//\t\r
+//\tassign exdiff\t= {1\'b0,SRC2[30:20]} - {1\'b0,SRC1[30:20]};\t// Difference of Exponents\r
+//\tassign madiff\t= {1\'b0,SRC2[19:0]}  - {1\'b0,SRC1[19:0]};\t// Difference of Mantissa \r
+//\tassign exdiff12 = {1\'b0,SRC1[30:20]} - {1\'b0,SRC2[30:20]};\t// Diff. Exponents exchanged\r
+//\t\r
+//\talways @(posedge BCLK)\r
+//\t\tif (START[0])\r
+//\t\t  begin\r
+//\t\t\tex_null <= (exdiff[10:0] == 11\'h0);\r
+//\t\t\tma_null <= (madiff[19:0] == 20\'h0);\r
+//\t\t\tex_msb  <= exdiff[11];\r
+//\t\t\tma_msb  <= madiff[20];\r
+//\t\t\tshift1  <= (exdiff[10:6]   != 5\'h0) ? 6\'h3F : exdiff[5:0];\r
+//\t\t\tshift2  <= (exdiff12[10:6] != 5\'h0) ? 6\'h3F : exdiff12[5:0];\r
+//\t\t\texpo1\t<= SRC1[30:20];\r
+//\t\t\texpo2\t<= SRC2[30:20];\r
+//\t\t  end\r
+//\t\t\t\r
+//\tassign lowdiff = {1\'b0,SRC2} - {1\'b0,SRC1};\t// LSD compare\r
+//\t\r
+//\tassign switch = ex_msb | (ex_null & (ma_msb | (ma_null & lowdiff[32])));\t// exchange ?\r
+//\r
+//\tassign muxsrc1 = switch ? {MAN2,SRC2} : {MAN1,SRC1};\r
+//\r
+//\talways @(posedge BCLK)\t// Pipeline Reg\r
+//\t  begin\r
+//\t\tmuxsrc2 <= switch  ? {expo1,MAN1,SRC1}   : {expo2,MAN2,SRC2};\t// Incl. Exponent & ""1"" of mantissa\r
+//\t\tpipe1 <= SELECT[1] ? (ganzklein ? 53\'d0  : {1\'b1,SRC1[19:0],SRC2}) : muxsrc1;\t// Feeding of R.T.F.\r
+//\t\tshift <= SELECT[1] ? {1\'b0,rexdiff[4:0]} : (switch ? shift2 : shift1);\r
+//\t  end\r
+//\t\t\r
+//\t//\tSRC2   SRC1\t: switch = 0\t\tSRC2   SRC1 : switch = 1\r
+//\t//\t  5  +   3  : +(5 + 3) =  8\t\t  3  +   5  : +(5 + 3) =  8\t\tSELECT[0] = 0\r
+//\t//\t  5  + (-3) : +(5 - 3) =  2\t\t  3  + (-5) : -(5 - 3) = -2\r
+//\t//\t(-5) +   3  : -(5 - 3) = -2\t\t(-3) +   5  : +(5 - 3) =  2\r
+//\t//\t(-5) + (-3) : -(5 + 3) = -8\t\t(-3) + (-5) : -(5 + 3) = -8\r
+//\t//\t  5  -   3  : +(5 - 3) =  2\t\t  3  -   5  : -(5 - 3) = -2\t\tSELECT[0] = 1\r
+//\t//\t  5  - (-3) : +(5 + 3) =  8\t\t  3  - (-5) : +(5 + 3) =  8\r
+//\t//\t(-5) -   3  : -(5 + 3) = -8\t\t(-3) -   5  : -(5 + 3) = -8\r
+//\t//\t(-5) - (-3) : -(5 - 3) = -2\t\t(-3) - (-5) : +(5 - 3) =  2\r
+//\t\r
+//\tassign sign1 = SRCFLAGS[4];\r
+//\tassign sign2 = SRCFLAGS[5];\r
+//\t\r
+//\talways @(posedge BCLK)\t// Pipeline Reg\r
+//\t  begin\r
+//\t\tvorz \t<= switch ? (SELECT[0] ^ sign1) : sign2;\r
+//\t\taddflag <= ~(SELECT[0] ^ (sign1 ^ sign2));\r
+//\t  end\r
+//\t\r
+//\t// CMPF : 1. Pipeline Stage : first result : is stored one level higer in Reg\r
+//\t\r
+//\tassign CMPRES[1] = ~CMPRES[0] & (switch ? ~sign1 : sign2);\t// look table above\r
+//\tassign CMPRES[0] = (ex_null & ma_null & (sign1 == sign2) & (lowdiff == 33\'h0)) | (SRCFLAGS[2] & SRCFLAGS[0]);\r
+//\t\r
+//\t// ++++++++++++++++++++++++++++++++++\r
+//\t// ADD/SUB + ROUND/TRUNC : 2. Step : Barrelshifter to the right -->\r
+//\t\r
+//\twire [55:0] brshifta,brshiftb,brshiftc,brshiftd,brshifte,brshiftf;\r
+//\t\r
+//\t// 5..33322222222221111111111\tis this picture still correct ? Took over from Single FP\r
+//\t// 5..2109876543210987654321098765432-10\r
+//\t// 1..VVVVVVVVVVVVVVVVVVVVVVVV0000000-00\t// last 2 bit for rounding\r
+//\t\r
+//\tassign brshifta = shift[5] ? {32\'h0,   pipe1[55:33],   (pipe1[32:3] != 30\'h0)} : {pipe1,3\'h0};\r
+//\tassign brshiftb = shift[4] ? {16\'h0,brshifta[55:17],(brshifta[16:0] != 17\'h0)} : brshifta;\r
+//\tassign brshiftc = shift[3] ? { 8\'h0, brshiftb[55:9], (brshiftb[8:0] !=  9\'h0)} : brshiftb;\r
+//\tassign brshiftd = shift[2] ? { 4\'h0, brshiftc[55:5], (brshiftc[4:0] !=  5\'h0)} : brshiftc;\r
+//\tassign brshifte = shift[1] ? { 2\'h0, brshiftd[55:3], (brshiftd[2:0] !=  3\'h0)} : brshiftd;\r
+//\tassign brshiftf = shift[0] ? { 1\'b0, brshifte[55:2], (brshifte[1:0] !=  2\'h0)} : brshifte;\r
+//\t\r
+//\t// ++++++++++++++++++++++++++++++++++\r
+//\t// ROUNDLi/TRUNCLi/FLOORLi : 3. Step : round to Integer\r
+//\t\r
+//\treg\t\t\tcar_ry;\r
+//\twire  [1:0] inex;\r
+//\twire [30:0] compl;\r
+//\twire [31:0] iadder;\r
+//\twire\t\trestbits;\r
+//\t\r
+//\tassign restbits = (brshiftf[23:0] != 24\'h0);\r
+//\tassign inex     = {brshiftf[24],restbits};\t\t// Inexact-Flag-Data transfered to multiplexer at the end\r
+//\t\r
+//\talways @(SELECT or sign1 or brshiftf or restbits or inex or ganzklein)\r
+//\t\tcasex (SELECT[3:2])\r
+//\t\t    2\'b00 : car_ry = sign1 ^ (((brshiftf[25:24] == 2\'b11) & ~restbits) | (inex == 2\'b11));\t// ROUNDLi\r
+//\t\t    2\'b1x : car_ry = sign1 ? (~ganzklein & (inex == 2\'b00)) : 1\'b0;\t// +numbers like TRUNCLi, -numbers to ""-infinity"" round\r
+//\t\t  default : car_ry = sign1;\t// TRUNCLi , simple cut off\r
+//\t\tendcase\r
+//\r
+//\tassign compl  = sign1 ? ~brshiftf[55:25] : brshiftf[55:25];\r
+//\t\r
+//\tassign iadder = {sign1,compl} + {31\'h0,car_ry};\r
+//\t\r
+//\talways @(posedge BCLK) IOUT <= minint ? 32\'h8000_0000 : iadder;\r
+//\r
+//\talways @(iadder or BWD or sign1)\t// special overflow detection i.e. -129 to -255 at Byte\r
+//\t\tcasex (BWD)\t\t\t\t\t\t// or 127.9 -> 128 = error !\r
+//\t\t  2\'b00 : ovflag2 = (iadder[8]  != iadder[7]);\t// Byte\r
+//\t\t  2\'b01 : ovflag2 = (iadder[16] != iadder[15]);\t// Word\r
+//\t\tdefault : ovflag2 = 1\'b0;\r
+//\t\tendcase\r
+//\t\t\r
+//\t// ++++++++++++++++++++++++++++++++++\r
+//\t// ADD/SUB : 3. Step : Addition or Subtraction\r
+//\t\r
+//\twire\t[67:0]\tresult;\r
+//\twire\t[55:0]\tblshifti;\r
+//\twire\t[12:0]\tshiftl;\r
+//\twire\t\t\tshift_32;\r
+//\twire\t[65:0]\tadd_q;\r
+//\t\r
+//\t// The central adder : the subtraction needs 3 Guard-Bits after LSB for correct rounding\r
+//\tassign result = {1\'b0,muxsrc2,3\'b000} + (addflag ? {12\'h0,brshiftf} : {12\'hFFF,~brshiftf}) + {67\'d0,~addflag};\r
+//\t\t\t\t\t\t\r
+//\tassign blshifti = SELECT[1] ? {movif,24\'h0} : result[55:0];\t// Feeding of MOViL, comes from Register\r
+//\r
+//\tassign shiftl = SELECT[1] ? 13\'h041E : {1\'b0,result[67:56]};\t// MOViL\r
+//\t\t\r
+//\tassign shift_32 = (blshifti[55:24] == 32\'h0);\r
+//\t\r
+//\t// In case of ADD the result bypasses the barrelshifter : LSB of exponent has changed\r
+//\tassign add_q = (muxsrc2[53] != result[56]) ? {result[67:3],(result[2:0] != 3\'b000)}\r
+//\t\t\t\t\t\t\t\t\t\t\t   : {result[67:56],result[54:2],(result[1:0] != 2\'b00)} ;\r
+//\t\r
+//\t// ++++++++++++++++++++++++++++++++++\r
+//\t// ADD/SUB : 4. Step : Barrelshifter left for SUB and MOViF :\r
+//\t\r
+//\twire\t\tshift_16,shift_8,shift_4,shift_2,shift_1,zero;\r
+//\twire  [1:0] lsb_bl;\r
+//\twire [55:0]\tblshifta,blshiftb,blshiftc,blshiftd,blshifte,blshiftf;\r
+//\twire [12:0]\texpol;\r
+//\t\r
+//\tassign blshifta = shift_32 ? {blshifti[23:0],32\'h0} : blshifti;\r
+//\tassign shift_16 = (blshifta[55:40] == 16\'h0);\r
+//\tassign blshiftb = shift_16 ? {blshifta[39:0],16\'h0}\t: blshifta;\r
+//\tassign shift_8  = (blshiftb[55:48] == 8\'h00);\r
+//\tassign blshiftc = shift_8  ? {blshiftb[47:0],8\'h0} \t: blshiftb;\r
+//\tassign shift_4  = (blshiftc[55:52] == 4\'h0);\r
+//\tassign blshiftd = shift_4  ? {blshiftc[51:0],4\'h0} \t: blshiftc;\r
+//\tassign shift_2  = (blshiftd[55:54] == 2\'b00);\r
+//\tassign blshifte = shift_2  ? {blshiftd[53:0],2\'b0} \t: blshiftd;\r
+//\tassign shift_1  = ~blshifte[55];\r
+//\tassign blshiftf = shift_1  ? {blshifte[54:0],1\'b0} \t: blshifte;\r
+//\t\r
+//\t// Overflow at ROUNDLi/TRUNCLi/FLOORLi is shown in overflow of exponent , SELECT[1] is then 1\r
+//\tassign expol = shiftl - {7\'h00,shift_32,shift_16,shift_8,shift_4,shift_2,shift_1};\r
+//\t\t\r
+//\t// Inexact at ROUNDLi/TRUNCLi/FLOORLi : evaluation for all one level higher\r
+//\tassign lsb_bl = (SELECT == 2\'b11) ? inex : {blshiftf[2],(blshiftf[1:0] != 2\'b0)};\r
+//\t\r
+//\tassign zero =  (~SELECT[1] & SRCFLAGS[2] & SRCFLAGS[0])\r
+//\t\t\t\t | ((blshifti == 56\'h0) & ((~addflag & ~SELECT[1]) | (SELECT[1:0] == 2\'b10)));\r
+//\t\r
+//\tassign sign = SELECT[1] ? sign_movif : (vorz & ~zero);\t// sign for MOViL\r
+//\t\r
+//\t// 2. Pipeline register for ADD , SUB and MOViL \r
+//\talways @(posedge BCLK)\r
+//\t\toutreg <= (addflag & ~SELECT[1]) ? {nan,zero,sign,1\'b0,add_q}\r
+//\t\t\t\t\t\t\t\t\t\t : {nan,zero,sign,expol,blshiftf[54:3],lsb_bl};\r
+//\t\t\t\t\t\t\t\t\t\t\r
+//\t// ++++++++++++++++++++++++++++++++++\r
+//\t\r
+//\tassign OUT = {outreg[69:67],(rovfl ? 2\'b01 : outreg[66:65]),outreg[64:0]};\r
+//\t\t\r
+//endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t5. DFPU_MISC\tDouble precision floating point miscellaneous operations \r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//module DFPU_MISC ( BCLK, START, SRC1, SRC2, SRCFLAG, MIMUX, MODE, OUT );\r
+//\r
+//\tinput\t\t\tBCLK;\r
+//\tinput \t\t\tSTART;\r
+//\tinput\t[31:0]\tSRC1,SRC2;\r
+//\tinput\t\t\tSRCFLAG;\r
+//\tinput\t\t\tMIMUX;\r
+//\tinput\t [3:0]\tMODE;\r
+//\toutput\t[69:0]\tOUT;\r
+//\t\r
+//\treg\t\t[69:0]\tOUT;\r
+//\treg\t\t[63:0]\tdaten;\r
+//\t\r
+//\twire\t[10:0]\tscalb_l;\r
+//\twire\t\t\tnan,zero,sign;\r
+//\twire\t[12:0]\tlexpo,sexpo;\r
+//\twire\t[69:0]\tscalb_res,logb_res,fl_lf;\r
+//\t\r
+//\talways @(posedge BCLK) if (START) daten <= {(MIMUX ? {daten[31],scalb_l,daten[19:0]}: SRC1),SRC2};\r
+//\t\r
+//\tassign nan  = MODE[0] ? (daten[62:55] == 8\'hFF) : (daten[62:52] == 11\'h7FF);\r
+//\tassign zero = MODE[0] ? (daten[62:55] == 8\'h00) : (daten[62:52] == 11\'h000);\r
+//\tassign sign = daten[63] & ~zero;\r
+//\t\r
+//\tassign lexpo = {5\'b0,daten[62:55]} + 13\'h0380;\t// -7F + 3FF\r
+//\t\r
+//\tassign sexpo = (daten[62:52] > 11\'h47E) ? 13\'h0FFF \r
+//\t\t\t\t\t\t\t\t\t\t\t: ((daten[62:52] < 11\'h381) ? 13\'h0 : {2\'b0,{4{daten[62]}},daten[58:52]});\r
+//\r
+//\tassign fl_lf = MODE[0] ? {nan,zero,sign,lexpo,daten[54:32],31\'h0}\t\t\t\t\t\t\t\t\t\t// MOVFL\r
+//\t\t\t\t\t\t   : {nan,zero,sign,sexpo,daten[51:29],28\'h0,daten[29:28],(daten[27:0] != 28\'h0)};\t// MOVLF\r
+//\t\r
+//\t// +++++++++++++++++++++++++++  LOGBf  +++++++++++++++++++++++++++++++++++\r
+//\t\r
+//\twire\t\t\tlogb_null;\r
+//\twire\t [9:0]\tsel_data,unbiased,shift_l8,shift_l4,shift_l2;\r
+//\twire\t [8:0]\tshift_l;\r
+//\twire\t\t\tposi_8,posi_4,posi_2,posi_1;\r
+//\twire\t [4:0]\tcalc_exp;\r
+//\twire\t [6:0]\tlogb_exp;\r
+//\t\r
+//\tassign logb_null = MODE[1] ? (daten[62:55] == 8\'h7F) : (daten[62:52] == 11\'h3FF);\r
+//\t\r
+//\tassign sel_data  = MODE[1] ? {{3{~daten[62]}},daten[61:55]} : daten[61:52];\r
+//\tassign unbiased  = daten[62] ? (sel_data + 10\'h001) : ~sel_data;\r
+//\r
+//\t// detection of leading ""1""\r
+//\tassign posi_8\t= (unbiased[9:2] == 8\'h00);\r
+//\tassign shift_l8 = posi_8 ? {unbiased[1:0],8\'h00} : unbiased;\r
+//\tassign posi_4\t= (shift_l8[9:6] == 4\'h0);\r
+//\tassign shift_l4 = posi_4 ? {shift_l8[5:0],4\'h0}  : shift_l8;\r
+//\tassign posi_2\t= (shift_l4[9:8] == 2\'b00);\r
+//\tassign shift_l2 = posi_2 ? {shift_l4[7:0],2\'b0}  : shift_l4;\r
+//\tassign posi_1\t= ~shift_l2[9];\r
+//\tassign shift_l\t= posi_1 ? {shift_l2[7:0],1\'b0}  : shift_l2[8:0];\t// top bit is hidden ""1""\r
+//\t\r
+//\tassign calc_exp = 5\'h08 - {1\'b0,posi_8,posi_4,posi_2,posi_1};\t// Minimum is ""F"" = for exponent +/-1 <=> 2^0\r
+//\t\r
+//\t// exponent is set one level higher for F and L\r
+//\tassign logb_exp = MODE[1] ? {{4{~calc_exp[4]}},{3{calc_exp[4]}}} : {~calc_exp[4],{6{calc_exp[4]}}};\r
+//\t\r
+//\tassign logb_res = logb_null ? {70\'h10_0000_0000_0000_0000} : {2\'b00,~daten[62],2\'b00,logb_exp,calc_exp[3:0],shift_l,45\'h0};\r
+//\t\r
+//\t// ++++++++++++++++++++++++  SCALBf  ++++++++++++++++++++++++++++++++++\r
+//\t\r
+//\twire\t [7:0]\tscalb_f;\r
+//\t\r
+//\tassign scalb_f = SRCFLAG ?  8\'h00  : (daten[39:32] + daten[30:23]);\r
+//\tassign scalb_l = SRCFLAG ? 11\'h000 : (daten[42:32] + daten[30:20]);\r
+//\t\r
+//\tassign scalb_res = MODE[1] ?\t// no rounding of Single Data\r
+//\t\t\t\t\t   {2\'b00,daten[31],5\'b0,scalb_f,daten[22:0],daten[28:1],3\'b000}\t\r
+//\t\t\t\t\t : {2\'b00,daten[63],2\'b0,daten[62:0],2\'b00};\r
+//\t\t\t\t\t \r
+//\t// ++++++++++++++++++++++++  Output  ++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\t\r
+//\talways @(posedge BCLK) OUT <= MODE[3] ? (MODE[2] ? logb_res : scalb_res) : fl_lf ;\t// LOGB/SCALB : MOVLF/MOVFL\r
+//\t\t\t\t\t\r
+//endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t6. DFPU_MUL\t\tDouble precision floating point multiplier\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//module DFPU_MUL ( BCLK, SRC1, SRC2, START, MRESULT, SRCFLAGS, OUT );\r
+//\r
+//\tinput\t\t\tBCLK;\r
+//\tinput\t[31:0]\tSRC1,SRC2;\r
+//\tinput\t\t\tSTART;\t\t// that is START[0]\r
+//\tinput  [105:0] \tMRESULT;\r
+//\tinput\t [5:0] \tSRCFLAGS;\t// NAN and ZERO flags\r
+//\toutput  [69:0] \tOUT;\t\t// The result\r
+//\r
+//\treg\t\t[69:0]\tOUT;\r
+//\treg\t\t[12:0]\texponent;\r
+//\twire\t\t\torlow;\r
+//\twire\t[12:0]\texpoh,expol;\r
+//\twire\t [1:0]\trestlow,resthigh;\r
+//\twire\t\t\tzero,nan,sign;\r
+//\t\t\r
+//\tassign zero = \tSRCFLAGS[2] | SRCFLAGS[0];\t// one is NULL -> NULL is the result\r
+//\tassign nan = \tSRCFLAGS[3] | SRCFLAGS[1];\t// one is NAN -> error\r
+//\tassign sign = \t(SRCFLAGS[5] ^ SRCFLAGS[4]) & ~zero;\r
+//\t\r
+//\tassign orlow = (MRESULT[50:0] != 51\'b0);\r
+//\t\r
+//\tassign restlow  = {MRESULT[51],orlow};\r
+//\tassign resthigh = {MRESULT[52],(MRESULT[51] | orlow)};\r
+//\t\r
+//\talways @(posedge BCLK) if (START) exponent <= {2\'b00,SRC1[30:20]} + {2\'b00,SRC2[30:20]};\r
+//\t\t\r
+//\tassign expoh    = exponent - 13\'h03FE;\r
+//\tassign expol\t= exponent - 13\'h03FF;\t// for MSB if MRESULT=0\r
+//\t\r
+//\talways @(posedge BCLK)\r
+//\t\tOUT <= MRESULT[105] ? {nan,zero,sign,expoh,MRESULT[104:53],resthigh}\t// 52 Bit Mantissa\r
+//\t\t\t\t\t\t\t: {nan,zero,sign,expol,MRESULT[103:52],restlow};\r
+//\t\r
+//endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t7. DIVI_PREP\tPrepare data for the divider\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module DIVI_PREP (SRC, BWD, NOT_DEI, EXTDATA, DOUT, MSB, NULL, MINUS);\r
+\r
+\tinput\t[31:0]\tSRC;\r
+\tinput\t [1:0]\tBWD;\r
+\tinput\t\t\tNOT_DEI;\r
+\tinput\t\t\tEXTDATA;\r
+\t\r
+\toutput\t[31:0]\tDOUT;\r
+\toutput\t [4:0]\tMSB;\r
+\toutput\t\t\tNULL;\r
+\toutput\t\t\tMINUS;\r
+\r
+\treg\t\t[31:0]\tdouble;\r
+\t\r
+\twire\t[15:0]\ttest_16;\r
+\twire\t [7:0]\ttest_8;\r
+\twire\t [3:0]\ttest_4;\r
+\twire\t [1:0]\ttest_2;\r
+\twire\t\t\tbit_4,bit_3,bit_2,bit_1,bit_0;\r
+\twire\t [1:0]\tmodus;\r
+\t\r
+\tassign modus = (NOT_DEI | EXTDATA) ? BWD : {(BWD[1] | BWD[0]),1\'b1};\r
+\t\r
+\talways @(modus or SRC or NOT_DEI)\r
+\t\tcasex (modus)\r
+\t\t  2\'b00 : double = {{24{SRC[7]  & NOT_DEI}},SRC[7:0]};\r
+\t\t  2\'b01 : double = {{16{SRC[15] & NOT_DEI}},SRC[15:0]};\r
+\t\t  2\'b1x : double = SRC;\r
+\t\tendcase\r
+\t\t\r
+\tassign MINUS = double[31] & NOT_DEI;\r
+\t\r
+\tassign DOUT = ({32{MINUS}} ^ double) + {31\'h0,MINUS};\t//\tassign DOUT = MINUS ? (32\'d0 - double) : double;\r
+\t\r
+\t// now find most significant set bit : FFS\r
+\t\r
+\tassign bit_4   = (DOUT[31:16] != 16\'h0);\r
+\tassign test_16 = bit_4 ? DOUT[31:16]   : DOUT[15:0];\r
+\tassign bit_3   = (test_16[15:8] != 8\'h0);\r
+\tassign test_8  = bit_3 ? test_16[15:8] : test_16[7:0];\r
+\tassign bit_2   = (test_8[7:4] != 4\'h0);\r
+\tassign test_4  = bit_2 ? test_8[7:4]   : test_8[3:0];\r
+\tassign bit_1   = (test_4[3:2] != 2\'b0);\r
+\tassign test_2  = bit_1 ? test_4[3:2]   : test_4[1:0];\r
+\tassign bit_0   =  test_2[1];\r
+\tassign NULL    = (test_2 == 2\'b00);\r
+\t\r
+\tassign MSB = {bit_4,bit_3,bit_2,bit_1,bit_0};\r
+\t\r
+endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t8. DFPU_DIV\t\tThe divider for all divide opcodes : double, single and integer\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module DFPU_DIV ( BCLK, BRST, START, SRC1, SRC2, MAN1, MAN2, SRCFLAGS, FL, BWD, OPCODE, OUT, DONE, DIVI_OUT, DVZ_TRAP, DEI_OVF );\r
+\r
+\t// This version needs for Double 28+1 cycles if MAN1<MAN2 otherwise 28+2.\r
+\t// For Single it needs 13+1 cyckes or 13+2.\r
+\t\r
+\tinput\t\t\tBCLK,BRST;\r
+\tinput\t [3:0]\tSTART;\t\t// START & recognized Divider Operation\r
+\tinput\t[31:0]\tSRC1,SRC2;\t// input data\r
+\tinput\t[20:0]\tMAN1,MAN2;\r
+\tinput\t [5:0]\tSRCFLAGS;\t// NAN and ZERO\r
+\tinput\t\t\tFL;\r
+\tinput\t [1:0]\tBWD;\r
+\tinput\t [2:0]\tOPCODE;\t\t// for all DIVi variants\r
+\t\r
+\toutput\t[69:0]\tOUT;\t\t// the result\r
+\toutput\treg\t\tDONE;\t\t// Pipeline-Flag\r
+\toutput\t[63:0]\tDIVI_OUT;\t// for Integer Division\r
+\toutput\t\t\tDVZ_TRAP;\t// Divide by Zero Trap\r
+\toutput\t [1:0]\tDEI_OVF;\t// DEI Overflow\r
+\t\r
+\t// ++++++++++++++  for Integer Division  ++++++++++++++\r
+\treg\t\t\t\trun_divi;\r
+\treg\t\t\t\tdivi_pipe1,divi_pipe2,divi_pipe3,divi_pipe4;\r
+\treg\t\t\t\tneg_src1,neg_src2,nul_src2;\r
+\treg\t\t [4:0]\tmsb_src1;\r
+\treg\t\t [5:0]\tmsb_src2;\r
+\treg\t\t[31:0]\tivalue,src2_reg,pipe_reg;\r
+\treg\t\t [4:0]\tdivi_counter;\r
+\treg\t\t\t\tsub_case;\r
+\treg\t\t\t\tnegativ;\r
+\treg\t\t[32:0]\tdivi_result;\r
+\treg\t\t[63:0]\tDIVI_OUT;\r
+\treg\t\t\t\tDVZ_TRAP,dvz_pipe;\r
+\treg\t\t\t\tsel_in;\r
+\treg\t\t[62:0]\tdin_mux;\r
+\treg\t\t\t\tdei_pipe;\r
+\treg\t\t\t\textdata;\t// extended data : 2 data packets, only apply to DEI\r
+\treg\t\t [2:0]\taddoff;\r
+\treg\t\t\t\tnext_msb2;\r
+\treg\t\t[31:0]\tdei_result;\r
+\treg\t\t [1:0]\tDEI_OVF;\r
+\t\r
+\twire\t[31:0]\ti_in;\r
+\twire\t[37:0]\ti_out;\r
+\twire\t [6:0]\tdiff_msb;\r
+\twire\t [5:1]\tshift_r;\r
+\twire\t[62:0]\tshift_2;\r
+\twire\t[62:0]\tshift_4;\r
+\twire\t[62:0]\tshift_8;\r
+\twire\t[62:0]\tshift_16;\r
+\twire\t[64:0]\tshift_32;\r
+\twire\t\t\tstop_divi,neg_flag;\r
+\twire\t\t\trest_null,plus_1,ist_null;\r
+\twire\t\t\tnot_dei;\r
+\twire\t\t\tval'b'data;\t// Data <> 0 at DEI\r
+\t\r
+\t// ++++++++++++++  Floating Point & calculation path  ++++++++\r
+\treg\t\t[69:0]\tOUT;\r
+\treg\t\t[32:0]\tsave1;\r
+\treg\t\t\t\trunflag;\r
+\treg\t\t[55:0]\tdreimal;\r
+\treg\t\t[56:0]\tdivreg,divsr;\r
+\treg\t\t[31:0]\tdivreg_ext;\r
+\treg\t\t[12:0]\texponent;\r
+\t\r
+\twire\t\t\tload_src1,load_src2;\r
+\twire\t[56:0]\tsub1,sub2,sub3;\r
+\twire\t[32:0]\tsrc_1;\r
+\twire\t[20:0]\tman_1;\r
+\twire\t[12:0]\texpoh,expol,offset;\r
+\twire\t\t\trestlsb,restlow,resthigh;\r
+\twire\t\t\tzero,nan,sign,ende;\r
+\twire\t\t\torlow_s,orlow_d;\r
+\twire\t\t\tshort;\r
+\t\t\r
+\t// +++++++++++++++++++++++++++  Integer Division, DEI  +++++++++++++++++++++++++++\r
+\r
+\tassign not_dei = OPCODE[2];\t// 0 = DEI\r
+\talways @(posedge BCLK) if (START[3]) extdata <= ~START[1];\t// during START[0] for SRC1 not valid\r
+\t\r
+\talways @(posedge BCLK or negedge BRST)\r
+\t\tif (!BRST) run_divi <= 1\'b0;\r
+\t\t\telse\r
+\t\t\t\trun_divi <= (START[3] & ~ist_null) | (~divi_pipe4 & run_divi);\t// Abort at DVZ Trap\r
+\t\r
+\talways @(posedge BCLK) divi_pipe1 <= START[3] & ~ist_null;\t// no start if SRC1 = 0 : DVZ Trap\r
+\talways @(posedge BCLK) dei_pipe\t  <= divi_pipe1 & extdata;\r
+\talways @(posedge BCLK) divi_pipe2 <= extdata ? dei_pipe : divi_pipe1;\r
+\t\r
+\talways @(posedge BCLK) src2_reg <= SRC2;\r
+\t\r
+\talways @(posedge BCLK) sel_in <= START[3] | divi_pipe1;\t// two times data for DEI\r
+\tassign i_in = sel_in ? src2_reg : SRC1;\t\r
+\t\r
+\tDIVI_PREP prep_inst ( .SRC(i_in), .BWD(BWD), .NOT_DEI(not_dei), .EXTDATA(extdata | START[0]),\r
+\t\t\t\t\t\t  .DOUT(i_out[31:0]), .MSB(i_out[36:32]), .NULL(ist_null), .MINUS(i_out[37]) );\r
+\r
+\talways @(posedge BCLK) dvz_pipe <= START[3] & ist_null;\t// Pulse 1 cycle long\r
+\talways @(posedge BCLK) DVZ_TRAP <= dvz_pipe;\t// one cycle later if DEI with extdata\r
+\t\r
+\talways @(posedge BCLK)\r
+\t\tif (START[3])\r
+\t\t\tbegin\r
+\t\t\t\tneg_src1 <= i_out[37];\r
+\t\t\t\tmsb_src1 <= i_out[36:32];\r
+\t\t\tend\r
+\t\r
+\talways @(posedge BCLK)\r
+\t\tif (divi_pipe1)\r
+\t\t\tbegin\r
+\t\t\t\tnul_src2 <= ist_null;\r
+\t\t\t\tneg_src2 <= i_out[37];\r
+\t\t\tend\r
+\r
+\talways @(posedge BCLK) ivalue   <= i_out[31:0];\r
+\r
+\t// The following is only for DEI :\r
+\talways @(posedge BCLK) pipe_reg <= {32{extdata}} & ivalue;\t// Register must be 0 if not used\r
+\r
+\tassign valdata = extdata & ~ist_null;\r
+\talways @(BWD or valdata)\r
+\t\tcasex (BWD)\r
+\t\t  2\'b00   : addoff = {   1\'b0,   1\'b0,valdata};\r
+\t\t  2\'b01   : addoff = {   1\'b0,valdata,   1\'b0};\r
+\t\t  default : addoff = {valdata,   1\'b0,   1\'b0};\r
+\t\tendcase\r
+\t\t\r
+\talways @(posedge BCLK) next_msb2 <= extdata & ist_null & divi_pipe1;\t// Special case at DEI : MSD = 0\r
+\t\r
+\talways @(posedge BCLK)\r
+\t\tif (divi_pipe1) msb_src2 <= {addoff[2],(addoff[1:0] | i_out[36:35]),i_out[34:32]};\r
+\t\t  else\r
+\t\t\tif (next_msb2) msb_src2 <= {1\'b0,i_out[36:32]};\r
+\t\t\t\r
+\t// Shifter for Source2 \r
+\t\r
+\tassign diff_msb = {1\'b0,msb_src2} - {2\'b0,msb_src1};\r
+\t\r
+\t// negativ shift limited to 0 : Source2=0 calculated without special handling, result always 0\r
+\tassign shift_r = diff_msb[6] ? 5\'d0 : diff_msb[5:1];\t// LSB does not count\r
+\t\r
+\talways @(BWD or extdata or ivalue or pipe_reg)\r
+\t\tcasex ({BWD,extdata})\r
+\t\t\t3\'b0x0  : din_mux = {31\'b0,ivalue};\t// the normal case for all except DEI\r
+\t\t\t3\'b001  : din_mux = {23\'b0,pipe_reg,ivalue[7:0]};\r
+\t\t\t3\'b011  : din_mux = {15\'b0,pipe_reg,ivalue[15:0]};\r
+\t\t\tdefault : din_mux = {pipe_reg[30:0],ivalue};\t\t// 63 Bit wide\r
+\t\tendcase\r
+\r
+\tassign shift_2  = shift_r[1] ? din_mux : {din_mux[60:0], 2\'b0};\r
+\tassign shift_4  = shift_r[2] ? shift_2 : {shift_2[58:0], 4\'b0};\r
+\tassign shift_8  = shift_r[3] ? shift_4 : {shift_4[54:0], 8\'b0};\r
+\tassign shift_16 = shift_r[4] ? shift_8 : {shift_8[46:0],16\'b0};\t// Result is 63 Bit wide\r
+\t\r
+\t// 65 Bit result because of DEI \r
+\tassign shift_32 = shift_r[5] ? {1\'b0,pipe_reg,ivalue} : {shift_16,2\'b00};\t// special case DEI : 32 times shift\r
+\t\r
+\talways @(posedge BCLK or negedge BRST)\t// Flag for rounding, only if DEST <>0 \r
+\t\tif (!BRST) divi_pipe3 <= 1\'b0;\r
+\t\t  else\r
+\t\t    divi_pipe3 <= divi_pipe2 | (divi_pipe3 & ~stop_divi);\r
+\t\t    \r
+\talways @(posedge BCLK)\r
+\t\tif (divi_pipe2) divi_counter <= shift_r;\r
+\t\t  else divi_counter <= divi_counter - {4\'b000,~stop_divi};\t// should stop at 0 \r
+\t\t  \r
+\tassign stop_divi = (divi_counter == 5\'h0);\t// caclulation ready\r
+\t\r
+\talways @(posedge BCLK) divi_pipe4 <= divi_pipe3 & stop_divi;\r
+\t\r
+\tassign neg_flag  = neg_src1 ^ neg_src2;\r
+\tassign rest_null = (divreg[33:2] == 32\'h0);\r
+\t\r
+\talways @(posedge BCLK) sub_case <= neg_flag & ~nul_src2;\t// little help for MODi opcode\r
+\t\t\r
+\t// Result preparation :\r
+\t// DEST  SRC    QUO  REM /  DIV  MOD\r
+\t//  +33  +13 :   2    7  /   2    7\r
+\t//\t+33  -13 :  -2    7  /  -3   -6\r
+\t//\t-33  +13 :  -2   -7  /  -3    6\r
+\t//\t-33  -13 :   2   -7  /   2   -7\r
+\talways @(*)\r
+\t\tcase (OPCODE[1:0])\r
+\t\t  2\'b00 : divi_result = {neg_flag,divsr[31:0]};\t\t// QUO\r
+\t\t  2\'b01 : divi_result = {neg_src2,divreg[33:2]};\t// REM\r
+\t\t  2\'b10 : divi_result = {neg_src1,((sub_case & ~rest_null) ? (save1[31:0] - divreg[33:2]) : divreg[33:2])};\t// MOD\r
+\t\t  2\'b11 : divi_result = {neg_flag,divsr[31:0]};\t\t// DIV\r
+\t\tendcase\r
+\t\r
+\talways @(posedge BCLK) negativ <= divi_result[32];\r
+\t\r
+\tassign plus_1 = (OPCODE[1:0] == 2\'b11) ? (negativ & rest_null) : negativ;\t// Special case Rest=0 at DIV\r
+\t\r
+\talways @(posedge BCLK)\r
+\t\tif (divi_pipe4) DIVI_OUT[63:32] <= not_dei ? (({32{negativ}} ^ divi_result[31:0]) + {31\'d0,plus_1}) : dei_result;\r
+\t\r
+\talways @(posedge BCLK) if (divi_pipe4) DIVI_OUT[31:0] <= divreg[33:2];\r
+\t\r
+\talways @(extdata or BWD or divsr or divreg)\r
+\t\tcasex ({extdata,BWD})\r
+\t\t  3\'b000  : dei_result = {16\'hxxxx,divsr[7:0],divreg[9:2]};\r
+\t\t  3\'b001  : dei_result = {divsr[15:0],divreg[17:2]};\r
+\t\t  default : dei_result = divsr[31:0];\r
+\t\tendcase\r
+\t\t\r
+\t// +++++++++++++++++++++++++++  Calculation path for Division  ++++++++++++++++++++++++++++\r
+\t\r
+\talways @(posedge BCLK or negedge BRST)\r
+\t\tif (!BRST) runflag <= 1\'b0;\r
+\t\t\telse\r
+\t\t\t\trunflag <= START[2] | (~ende & runflag);\r
+\t\r
+\talways @(posedge BCLK) DONE <= (ende & runflag) | divi_pipe4;\r
+\t\r
+\tassign man_1 = (FL | run_divi) ? 21\'h0 : MAN1;\r
+\tassign src_1 = run_divi ? {1\'b0,ivalue} : ( FL ? {10\'h001,SRC1[22:0]} : {SRC1,1\'b0});\r
+\t\r
+\tassign load_src1 = START[2] | divi_pipe1;\r
+\t\r
+\t//\t\t\t\t\t\t\t\t\t\t\t\t\t\t*2 \t\t   +       *1\t\r
+\talways @(posedge BCLK) if (load_src1) dreimal <= {1\'b0,man_1,src_1,1\'b0} + {2\'b00,man_1,src_1};\t// 54 Bit Reg\r
+\t\r
+\talways @(posedge BCLK) if (load_src1) save1 <= src_1;\r
+\r
+\tassign sub1 = divreg - {3\'b000, man_1,save1     };\r
+\tassign sub2 = divreg - {2\'b00 ,man_1,save1,1\'b0};\r
+\tassign sub3 = divreg - {1\'b0, dreimal         };\r
+\r
+\tassign load_src2 = START[2] | divi_pipe2;\r
+\t\r
+\talways @(posedge BCLK)\r
+\t\tif (load_src2) divreg <= divi_pipe2 ? {23\'h0,shift_32[64:32]} : ( FL ? {34\'h0_0000_0001,SRC2[22:0]} : {3\'b0,MAN2,SRC2,1\'b0});\r
+\t\telse\r
+\t\t\tbegin\r
+\t\t\t  casex ({sub3[56],sub2[56],sub1[56]})\r
+\t\t\t\t3\'b0xx : divreg <=   {sub3[54:0],divreg_ext[31:30]};\r
+\t\t\t\t3\'b10x : divreg <=   {sub2[54:0],divreg_ext[31:30]};\r
+\t\t\t\t3\'b110 : divreg <=   {sub1[54:0],divreg_ext[31:30]};\r
+\t\t\t  default  : divreg <= {divreg[54:0],divreg_ext[31:30]};\r
+\t\t\t  endcase\r
+\t\t\tend\r
+\t\t\t\r
+\talways @(posedge BCLK)\t// Extension Register for Integer Division\r
+\t\tif (load_src2) divreg_ext <= divi_pipe2 ? shift_32[31:0] : 32\'d0;\r
+\t\t  else\r
+\t\t    divreg_ext <= {divreg_ext[29:0],2\'b0};\r
+\t\t    \r
+\talways @(posedge BCLK)\r
+\t\tif (load_src2) divsr <= 57\'h0;\r
+\t\telse\r
+\t\t\tbegin\r
+\t\t\t  casex ({sub3[56],sub2[56],sub1[56]})\r
+\t\t\t\t3\'b0xx : divsr <= {divsr[54:0],2\'b11};\r
+\t\t\t\t3\'b10x : divsr <= {divsr[54:0],2\'b10};\r
+\t\t\t\t3\'b110 : divsr <= {divsr[54:0],2\'b01};\r
+\t\t\t  default  : divsr <= {divsr[54:0],2\'b00};\r
+\t\t\t  endcase\r
+\t\t\tend\r
+\r
+\t// Overflow Detection for DEI : serial calculation\r
+\talways @(posedge BCLK)\r
+\t\tif (load_src2) DEI_OVF[0] <= 1\'b0;\r
+\t\t  else DEI_OVF[0] <= DEI_OVF[0] | (BWD[1] ? |divsr[33:32] : (BWD[0] ? |divsr[17:16] : |divsr[9:8]));\r
+\t\t  \r
+\talways @(posedge BCLK) DEI_OVF[1] <= divi_pipe4;\t// Timing pulse for OVF inclusiv for DIV and QUO\r
+\t\t  \r
+\tassign short = (SRCFLAGS[3:0] != 4\'h0) & runflag;\t\r
+\t\r
+\tassign ende = ((FL ? (divsr[26] | divsr[25]) : (divsr[56] | divsr[55])) & runflag) | short;\r
+\r
+\tassign sign = (SRCFLAGS[4] ^ SRCFLAGS[5]) & ~zero;\r
+\tassign zero =  SRCFLAGS[2] & ~SRCFLAGS[0];\t\t// SRC2 = NULL -> NULL as result\r
+\tassign nan  =  SRCFLAGS[3] | SRCFLAGS[1] | (SRCFLAGS[2] & SRCFLAGS[0]);\r
+\t\t\t// one of both NAN or both 0 -> invalid Operation \r
+\r
+\tassign orlow_d = (divreg[56:27] != 29\'b0) & ~zero & ~FL;\t// is there Rest ? [1:0] are always 0.\r
+\tassign orlow_s = (divreg[26:2]  != 25\'b0) & ~zero;\r
+\t\r
+\tassign restlsb  = divsr[0] | orlow_s;\r
+\tassign restlow  = (divsr[1:0] != 2\'b00) | orlow_s | orlow_d;\r
+\tassign resthigh = divsr[2] | restlow;\r
+\t\r
+\talways @(posedge BCLK) if (START[0]) exponent <= FL ? ({5\'b00,SRC2[30:23]} - {5\'b00,SRC1[30:23]})\r
+\t\t\t\t\t\t\t\t\t\t\t\t\t\t: ({2\'b00,SRC2[30:20]} - {2\'b00,SRC1[30:20]});\r
+\tassign offset   = FL ? 13\'h007E : 13\'h03FE;\r
+\tassign expoh    = exponent + {offset[12:1],1\'b1};\t// Double = 3FF/3FE\tSingle = 7F/7E\r
+\tassign expol\t= exponent + offset;\t\t\t\t// in case of normalizing\r
+\t\r
+\talways @(posedge BCLK)\r
+\t  if (ende && runflag)\r
+\t\tcasex ({FL,divsr[26],divsr[56]})\r
+\t\t  3\'b11x : OUT <= {nan,zero,sign,expoh[9:8],expoh[7],expoh[7],expoh[7],expoh[7:0],divsr[25:3],28\'b0,divsr[3:2],restlow};\r
+\t\t  3\'b10x : OUT <= {nan,zero,sign,expol[9:8],expol[7],expol[7],expol[7],expol[7:0],divsr[24:2],28\'b0,divsr[2:1],restlsb};\r
+\t\t  3\'b0x1 : OUT <= {nan,zero,sign,expoh,divsr[55:3],resthigh};\r
+\t\t  3\'b0x0 : OUT <= {nan,zero,sign,expol,divsr[54:2],restlow};\r
+\t\tendcase\r
+\t\t\r
+endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t9. DP_LOGIK\t\tControl logic and result path for different functions\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module DP_LOGIK ( BCLK, BRESET, OPCODE, SRC1, SRC2, FSR, START, MRESULT, BWD, FL, MAN1, MAN2, WR_REG, CY_IN,\r
+\t\t\t\t  COP_DONE, COP_OP, COP_IN,\r
+\t\t\t\t  DOUT, TT_DP, DP_CMP, OVF_BCD, MEI, DFLOAT, DONE, UP_DP, CLR_LSB, WREN_L, LD_OUT_L, DVZ_TRAP, COP_GO );\r
+\r
+// Definition of output word OUT of sub-moduls : the hidden-bit of the mantissa is already gone\r
+//\r
+//   N Z S   Exponent\t\t\tMantissa\t\t\t\t\t\t\t\t\t\t\t\t Round\r
+//   A E I  Double : 13 Bit\t\t52 Bit\t\t\t\t\t\t\t\t\t\t\t\t\t\t 2 Bit\r
+//   N R G  Single : 10 Bit     23 Bit\t\t\t\t\t\t\t\t\t\t\t\t\t\t 2 Bit\r
+//     O N\t\t\t\t   -mmmm.mmmm.mmmm.mmmm.mmmm.mmm-.--\t\t\t\t\t\t\t  -m.\r
+//  -F-F-F-E.EEEE.EEEE.EEEE-MMMM.MMMM.MMMM.MMMM.MMMM.MMMM.MMMM.MMMM.MMMM.MMMM.MMMM.MMMM.MMMM.RR\r
+//\r
+//   6 6 6 6 6666 6655 5555 5555 4444 4444 4433 3333 3333 2222 2222 2211 1111 1111 0000 0000 00\r
+//   9 8 7 6 5432 1098 7654 3210 9876 5432 1098 7654 3210 9876 5432 1098 7654 3210 9876 5432 10\r
+//\r
+// Single FP delivers the exponent in a way, that it is identical for rounding :\r
+//\r
+//  Exponent 61 - 54 => kept\r
+//  Bits 64 - 62 are filled with bit 61 , carry should come through\r
+//  Exponent 62 => Bit 65  , Overflow\r
+//  Exponent 63 => Bit 66  , Underflow\r
+\r
+\tinput\t\t\tBCLK,BRESET;\r
+\tinput\t [7:0]\tOPCODE;\t\r
+\tinput\t[31:0]\tSRC1,SRC2;\t// the input data\r
+\tinput\t[20:0]\tMAN1,MAN2;\t// the MSB of mantissa\r
+\tinput\t [8:3]\tFSR;\t\t// Floating Point Status Register\r
+\tinput\t [1:0]\tSTART;\r
+\tinput  [105:0]\tMRESULT;\t// Result of multiplier\r
+\tinput\t [1:0]\tBWD;\t\t// Size of integer\r
+\tinput\t\t\tFL;\r
+\tinput\t\t\tWR_REG;\t\t// from DECODER\r
+\tinput\t\t\tCY_IN;\r
+\tinput\t\t\tCOP_DONE;\t// Coprozessor Interface\r
+\tinput\t[23:0]\tCOP_OP;\r
+\tinput\t[63:0]\tCOP_IN;\r
+\r
+\toutput\t[63:0]\tDOUT;\r
+\toutput\t [4:0]\tTT_DP;\t\t// Trap-Info to FSR\r
+\toutput\t [2:0]\tDP_CMP;\t\t// CMPL result\r
+\toutput\t [3:0]\tOVF_BCD;\t// Integer Division Overflow + BCD Carry update\r
+\toutput\t\t\tMEI,DFLOAT;\r
+\toutput\t\t\tDONE,UP_DP;\r
+\toutput\t\t\tCLR_LSB,WREN_L,LD_OUT_L;\r
+\toutput\t\t\tDVZ_TRAP;\r
+\toutput\treg\t\tCOP_GO;\r
+\r
+\treg\t\t[63:0]\tDOUT;\r
+\treg\t\t\t\tCLR_LSB;\r
+\treg\t\t [2:0]\tDP_CMP;\r
+\treg\t\t [5:0]\tpreflags;\r
+\treg\t\t [5:0]\tsrcflags;\r
+//\treg\t\t[69:0]\tfpout;\r
+\twire\t[69:0]\tfpout;\r
+\treg\t\t [2:0]\ttt;\r
+\treg\t\t [6:0]\tselect;\r
+\treg\t\t [4:0]\twctrl;\r
+\treg\t\t [2:1]\tsequ;\r
+\treg\t\t\t\tmisc_op;\r
+\treg\t\t\t\tmisc_mux;\r
+\treg \t\t\tcar_ry;\r
+\treg\t\t\t\twr_part2;\r
+\treg\t\t\t\tup_flag;\r
+\treg\t\t\t\tovf_div;\r
+\t\r
+\twire\t\t\tzexp2,zman2,zexp1,zman1,znan1;\r
+\twire\t\t\tmake_i;\r
+\twire\t\t\tscalbl,go_misc;\r
+\twire\t\t\top_cmp;\r
+\twire\t[69:0]\tmulout,addout,divout,miscout;\r
+\twire\t\t\tgo_divf,go_divi,divi_ops,div_done;\r
+\twire\t\t\tbcd_ops,man_ops;\r
+\twire\t[31:0]\ti_out;\r
+\twire\t[63:0]\tdivi_out;\r
+\twire\t[66:2]\trund,cy_val;\t// Indexnumber like in xxxout\r
+\twire \t\t\tdiv_zero,overflow,underflow,inexact;\r
+\twire\t [1:0]\tcmpres;\r
+\twire\t[63:0]\tfp_out,fp_res;\r
+\twire\t\t\twr_part1;\r
+\twire\t\t\tdone_i;\r
+\twire\t[31:0]\tbcd_q;\r
+\twire\t\t\tbcd_done;\r
+\twire\t\t\tbcd_carry;\r
+\twire\t [1:0]\tdei_ovf;\r
+\twire\t\t\tquo_div;\r
+\twire\t\t\tcopop;\r
+\twire\t\t\tcopwr;\r
+\t\r
+\t// Control of datapath : together with START the Double Unit becomes activ \r
+\r
+\talways @(OPCODE or FL)\r
+\t\tcasex (OPCODE)\r
+\t\t  8\'b1001_000x : select = 7\'b00_01010;\t// 0 1 0 :\tMOViL\r
+\t\t  8\'b1001_010x : select = 7\'b10_11000;\t// MOVLF\r
+\t\t  8\'b1001_011x : select = 7\'b01_11000;\t// MOVFL\r
+\t\t  8\'b1001_100x : select = 7\'b10_01011;\t// 0 1 1 :\tROUNDLi\r
+\t\t  8\'b1001_101x : select = 7\'b10_01011;\t// 0 1 1 :  TRUNCLi\r
+\t\t  8\'b1001_111x : select = 7\'b10_01011;\t// 0 1 1 :\tFLOORLi\r
+\t\t  8\'b1011_0000 : select = 7\'bxx_01000;\t// 0 0 0 :\tADDL\r
+\t\t  8\'b1011_0010 : select = 7\'bxx_01001;\t// 0 0 1 :\tCMPL\r
+\t\t  8\'b1011_0100 : select = 7\'bxx_01001;\t// 0 0 1 :\tSUBL\r
+\t\t  8\'b1011_1000 : select = 7\'b11_01100;\t// 1 0 1 :  DIVf , Default Float for srcflags\r
+\t\t  8\'b1011_1100 : select = 7\'bxx_01100;\t// 1 0 0 :\tMULL\r
+\t\t  8\'b1011_0110 : select = 7\'b11_11000;\t// SCALBf , Default Float for srcflags\r
+\t\t  8\'b1011_0111 : select = {~FL,FL,5\'b11000};\t// LOGBf\r
+\t\t  default      : select = 7\'b0;\r
+\t\tendcase\r
+\r
+\tassign MEI      = (OPCODE == 8\'h79);\r
+\tassign divi_ops = (OPCODE[7:2] == 6\'b0111_11) | (OPCODE == 8\'h7B);\t// QUO/REM/MOD/DIV & DEI\r
+\tassign go_divf  = (OPCODE == 8\'hB8) & START[1];\t\t\t\t\t// because of runflag in DIV Unit\r
+\tassign go_divi  = divi_ops & (OPCODE[2] ? START[1] : START[0]);\t// DEI starts with START[0]\r
+\tassign bcd_ops  = (OPCODE == 8\'h6F) | (OPCODE == 8\'h6B);\t\t// ADDP , SUBP\r
+\t\r
+\tassign man_ops  = (OPCODE == 8\'hB1) | (OPCODE == 8\'hB5) | (OPCODE == 8\'hB9) | (OPCODE == 8\'hBD);\t// MOVf,NEGf,XXXf,ABSf\r
+\r
+\tassign DFLOAT   = (select[3] | copop) & ~FL;\t// all Double Floating Point Operations for PREPDATA\r
+\tassign make_i   = (select[2:0] == 3\'b011) | divi_ops | bcd_ops;\t// ROUND/TRUNC/FLOOR for output multiplexer\r
+\tassign op_cmp   = (OPCODE == 8\'hB2) & ~FL;\r
+\talways @(posedge BCLK) misc_op <= select[4];\t// for OUT-Multiplexer\r
+\t\r
+\tassign copop\t= (OPCODE == 8\'hDD);\r
+\tassign copwr\t= (COP_OP[18:17] == 2\'d0) & (COP_OP[13:11] == 3\'b111) & (COP_OP[7:5] == 3\'b001);\t// Custom Convert\r
+\t\r
+\t// very special solution for SCALBL\r
+\tassign scalbl\t= START[0] & ~FL & (OPCODE == 8\'hB6);\r
+\tassign go_misc\t= START[1] | scalbl;\r
+\talways @(posedge BCLK) misc_mux <= scalbl;\t// switches at START[1] the input multiplexer\r
+\t\r
+\t// SRCFLAGS : special handling for operands is done locally\r
+\t\r
+\tassign zexp2 = (SRC2[30:20] == 11\'d0);\r
+\tassign zman2 = (SRC2[19:0] == 20\'d0);\r
+\tassign zexp1 = (SRC1[30:20] == 11\'d0);\r
+\tassign zman1 = (SRC1[19:0] == 20\'d0);\r
+\tassign znan1 = (SRC1[30:20] == 11\'h7FF);\r
+\t\r
+\talways @(posedge BCLK)\r
+\t\tif (START[0])\r
+\t\t  begin\r
+\t\t\tsrcflags[5] <= SRC2[31];\r
+\t\t\tsrcflags[4] <= SRC1[31];\r
+\t\t\tpreflags    <= {(SRC2[30:20] == 11\'h7FF),zexp2,zman2,znan1,zexp1,zman1};\r
+\t\t   end\r
+\r
+\t// case Definition : 00 : 0\t\t, if START[i]=0 then there are always 2 long operands\r
+\t//\t\t\t\t\t 01 : 1 Float Operand SCR1\r
+\t//\t\t\t\t\t 10 : 1 Long Operand SRC1+SRC2\r
+\t//\t\t\t\t\t 11 : 2 Float Operands SRC1 , SRC2\r
+\t\r
+\talways @(posedge BCLK)\t// NaN \r
+\t\tif (START[1])\r
+\t\t\tcasex ({START[0],select[6:5]})\r
+\t\t\t   3\'b0xx : srcflags[3] <= preflags[5] | (preflags[4] & (~preflags[3] | SRC2[31] | ~zexp2 | ~zman2));\r
+\t\t\t   3\'b111 : srcflags[3] <= (SRC2[30:23] == 8\'hFF) | ((SRC2[30:23] == 8\'d0) & ((SRC2[22:20] != 3\'d0) | ~zman2));\t// F:SRC2 = NaN\r
+\t\t\t  default : srcflags[3] <= 1\'b0;\r
+\t\t\tendcase\r
+\t\t\t\r
+\talways @(posedge BCLK)\t// Zero : only exponent ! If denormalized => NaN !\r
+\t\tif (START[0])\r
+\t\t\tcasex ({START[1],select[6:5]})\r
+\t\t\t   3\'b0xx : srcflags[2] <= zexp2;\t// L:(SRC1,SRC2) = Zero , SRC1 = MSB\r
+\t\t\t   3\'b111 : srcflags[2] <= (SRC2[30:23] == 8\'d0);\t// F:SRC2 = Zero\r
+\t\t\t  default : srcflags[2] <= 1\'b0;\r
+\t\t\tendcase\r
+\t\t\t\r
+\talways @(posedge BCLK)\t// NaN \r
+\t\tif (START[1])\r
+\t\t\tcasex ({START[0],select[6:5]})\r
+\t\t\t   3\'b0xx : srcflags[1] <= preflags[2] | (preflags[1] & (~preflags[0] | SRC1[31] | ~zexp1 | ~zman1));\r
+\t\t\t   3\'b1x1 : srcflags[1] <= (SRC1[30:23] == 8\'hFF) | ((SRC1[30:23] == 8\'d0) & ((SRC1[22:20] != 3\'d0) | ~zman1));\t// F:SRC1 = NaN\r
+\t\t\t   3\'b110 : srcflags[1] <= znan1 | (zexp1 & (~zman1 | SRC2[31] | ~zexp2 | ~zman2));\t// L:(SRC1,SRC2) = NaN , SRC1 = MSB\r
+\t\t\t  default : srcflags[1] <= 1\'b0;\r
+\t\t\tendcase\r
+\t\t\t\r
+\talways @(posedge BCLK)\t// Zero : only exponent ! If denormalized => NaN !\r
+\t\tif (START[0])\r
+\t\t\tcasex ({START[1],select[6:5]})\r
+\t\t\t   3\'b0xx : srcflags[0] <= zexp1;\t// L:(SRC1,SRC2) = Zero , SRC1 = MSB\r
+\t\t\t   3\'b1x1 : srcflags[0] <= (SRC1[30:23] == 8\'d0);\t// F:SRC1 = Zero\r
+\t\t\t   3\'b110 : srcflags[0] <= zexp1;\t// L:(SRC1,SRC2) = Zero , SRC1 = MSB\r
+\t\t\t  default : srcflags[0] <= 1\'b0;\r
+\t\t\tendcase\r
+\r
+\t\t\t// The Sub-moduls : \r
+\t\r
+//\tDFPU_ADDSUB as_inst\t( .BCLK(BCLK), .START(START), .SRC1(SRC1), .SRC2(SRC2),\r
+//\t\t\t\t\t\t  .MAN1({~srcflags[0],MAN1[19:0]}), .MAN2({~srcflags[2],MAN2[19:0]}),\r
+//\t\t\t\t\t\t  .SRCFLAGS(srcflags), .BWD(BWD), .SELECT({OPCODE[2:1],select[1:0]}),\r
+//\t\t\t\t\t\t  .OUT(addout), .IOUT(i_out), .CMPRES(cmpres) );\r
+\r
+   assign addout = 70\'b0;\r
+   assign i_out  = 32\'b0;\r
+   assign cmpres = 2\'b0;\r
+\t\t\t\t\t\r
+//\tDFPU_MUL mul_inst\t( .BCLK(BCLK), .SRC1(SRC1), .SRC2(SRC2), .START(START[0]), .MRESULT(MRESULT),\r
+//\t\t\t\t\t\t  .OUT(mulout), .SRCFLAGS(srcflags) );\r
+\r
+   assign mulout = 70\'b0;\r
+\r
+\t\t\t\t\t\r
+\tDFPU_DIV div_inst\t( .BCLK(BCLK), .BRST(BRESET), .START({go_divi,go_divf,START}), .SRC1(SRC1), .SRC2(SRC2),\r
+\t\t\t\t\t\t  .MAN1(MAN1), .MAN2(MAN2), .SRCFLAGS(srcflags), .FL(FL), .OUT(divout), .DONE(div_done),\r
+\t\t\t\t\t\t  .BWD(BWD), .OPCODE(OPCODE[2:0]), .DIVI_OUT(divi_out), .DVZ_TRAP(DVZ_TRAP), .DEI_OVF(dei_ovf) ); \r
+\r
+//\tDFPU_MISC misc_inst\t( .BCLK(BCLK), .START(go_misc), .SRC1(SRC1), .SRC2(SRC2), .SRCFLAG(srcflags[2]),\r
+//\t\t\t\t\t\t  .MIMUX(misc_mux), .MODE({OPCODE[5],OPCODE[0],FL,OPCODE[1]}), .OUT(miscout) );\r
+\r
+   assign miscout = 70\'b0;\r
+\r
+\tDFPU_BCD bcd_inst\t( .BCLK(BCLK), .BRESET(BRESET), .START(START[1]), .DO_BCD(bcd_ops), .BWD(BWD), .SRC1(SRC1), .SRC2(SRC2),\r
+\t\t\t\t\t\t  .CY_IN(CY_IN), .SUBP(~OPCODE[2]), .BCD_Q(bcd_q), .CY_OUT(bcd_carry), .BCD_DONE(bcd_done) );\r
+\t\r
+\t// FP - path : selection of result and rounding :\r
+\r
+//\talways @(misc_op or OPCODE or mulout or addout or divout or miscout)\r
+//\t\tcasex ({misc_op,OPCODE[5],OPCODE[3:2]})\t//OPCODE[5] only for Flags i.e. NAN \r
+//\t\t  4\'b1xxx : fpout = miscout;\t\t// for MOVLF,MOVFL,SCALB & LOGB\r
+//\t\t  4\'b0110 : fpout = divout;\r
+//\t\t  4\'b0111 : fpout = mulout;\r
+//\t\t  default : fpout = addout;\r
+//\t\tendcase\r
+   assign fpout = 70\'d0;\r
+    \r
+\t\r
+\talways @(FSR or fpout)\t// Calculation of Carry according to rounding mode, fpout[67] = sign bit\r
+\t\tcasex (FSR[8:7])\r
+\t\t  2\'b00 : car_ry = ((fpout[1:0] == 2\'b10) & fpout[2]) | (fpout[1:0] == 2\'b11);\t// round to nearest\r
+\t\t  2\'b10 : car_ry = ~fpout[67] & (fpout[1:0] != 2\'b00);\t// round to positiv infinity\r
+\t\t  2\'b11 : car_ry =  fpout[67] & (fpout[1:0] != 2\'b00);\t// round to negativ infinity\r
+\t\tdefault : car_ry = 1\'b0;\t\t\t\t\t\t\t\t// round to zero\r
+\t\tendcase\r
+\r
+\tassign cy_val = {35\'h0,(FL & car_ry),28\'h0,(~FL & car_ry)};\r
+\t\r
+\tassign rund = {fpout[66:2]} + cy_val;\r
+\t\r
+\t// Detection of Div-by-0, Overflow, Underflow and Inexact : Epxonent from [66:54] = 13 Bits\r
+\tassign div_zero  = (srcflags[3:0] == 4\'h1) & (OPCODE == 8\'hB8);\t// true FPU Divide by Zero\r
+\tassign overflow  = ~rund[66] & (rund[65] | (rund[64:54] == 11\'h7FF));\r
+\tassign underflow = (rund[66] | (rund[65:54] == 12\'h0)) & ~fpout[68];\t// Zero-Flag\r
+\tassign inexact   = (fpout[1:0] != 2\'b00);\r
+\t\r
+\talways @(fpout or op_cmp or div_zero or overflow or underflow or inexact or FSR)\r
+\t\tcasex ({fpout[69],op_cmp,div_zero,overflow,FSR[3],underflow,FSR[5],inexact})\t// [69] = NAN\r
+\t\t\t8\'b1xxxxxxx : tt = 3\'b101;\t// Invalid operation\r
+\t\t\t8\'b001xxxxx : tt = 3\'b011;\t// Divide by Zero\r
+\t\t\t8\'b0001xxxx : tt = 3\'b010;\t// Overflow\r
+\t\t\t8\'b000011xx : tt = 3\'b001;\t// Underflow\r
+\t\t\t8\'b00000011 : tt = 3\'b110;\t// Inexact Result\r
+\t\t\tdefault\t\t: tt = 3\'b000;\t// no error\r
+\t\tendcase\r
+\t\t\r
+\tassign TT_DP = man_ops ? 5\'d0 : {(inexact & ~op_cmp),(underflow & ~op_cmp),tt};\t// at ABSf/NEGf no error : different to NS32381 !\r
+\r
+\tassign fp_res = FL ? {fpout[67],rund[61:31],rund[33:2]}\r
+\t\t\t\t\t   : {fpout[67],rund[64:2]};\t// lower 32 bits identical\r
+\r
+\t// Underflow special case and get ZERO\r
+\tassign fp_out = (underflow | fpout[68]) ? 64\'h0 : fp_res;\r
+\t\r
+\t// 63..32 goes to memory if Word or Byte ! Also in ODD Register , 31..0 goes in EVEN Register\r
+\t// DEI comes without WR_REG information\r
+\talways @(make_i or copop or MEI or BWD or WR_REG or MRESULT or COP_IN or i_out or fp_out or divi_ops or divi_out or bcd_ops or bcd_q)\r
+\t\tcasex ({make_i,copop,MEI,BWD})\r
+\t\t  5\'b00100 : DOUT = {MRESULT[31:8], (WR_REG ? MRESULT[15:8]  : MRESULT[7:0]), MRESULT[31:0]};\t// LSD always the same\r
+\t\t  5\'b00101 : DOUT = {MRESULT[31:16],(WR_REG ? MRESULT[31:16] : MRESULT[15:0]),MRESULT[31:0]};\r
+\t\t  5\'b0011x : DOUT =  MRESULT[63:0];\r
+\t\t  5\'b01xxx : DOUT =  COP_IN;\t// true alignment in Coprocessor\r
+\t\t  5\'b1xxxx : DOUT = divi_ops ? divi_out : {(bcd_ops ? bcd_q : i_out),fp_out[31:0]};\t// MSD is written first\r
+\t\t  default  : DOUT = fp_out;\r
+\t\tendcase\r
+\t\t\r
+\talways @(posedge BCLK) DP_CMP <= {(srcflags[3] | srcflags[1]),cmpres};\t// Only valid if not NaN\r
+\t\r
+\t// Pipeline Control + Registerfile write control\r
+\t\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) sequ <= 2\'b00;\r
+\t\t  else\r
+\t\t\tsequ <= {(sequ[1] & ~DONE),START[1]};\r
+\t\t  \r
+\talways @(FL or OPCODE or copwr)\r
+\t\tcasex ({FL,OPCODE})\t// WRITE Control : [2] = clr_lsb, [1] = wr_part2, [0] = wr_part1\r
+\t\t  9\'bx_1001_000x : wctrl = 5\'b01_111;\t// MOViL\r
+\t\t  9\'bx_1001_010x : wctrl = 5\'b00_010;\t// MOVLF\r
+\t\t  9\'bx_1001_011x : wctrl = 5\'b01_111;\t// MOVFL\r
+\t\t  9\'bx_1001_100x : wctrl = 5\'b00_010;\t// ROUNDLi\t- DONE is one cycle earlier for this opcodes\r
+\t\t  9\'bx_1001_101x : wctrl = 5\'b00_010;\t// TRUNCLi\t\r
+\t\t  9\'bx_1001_111x : wctrl = 5\'b00_010;\t// FLOORLi\r
+\t\t  9\'bx_1011_0000 : wctrl = 5\'b01_111;\t// ADDL\r
+\t\t  9\'bx_1011_0010 : wctrl = 5\'b00_000;\t// CMPL\t- via LD one cycle later in PSR\r
+\t\t  9\'bx_1011_0100 : wctrl = 5\'b01_111;\t// SUBL\r
+\t\t  9\'b1_1011_1000 : wctrl = 5\'b10_001;\t// DIVF - measured 18 cycles Reg-Reg\r
+\t\t  9\'b0_1011_1000 : wctrl = 5\'b10_111;\t// DIVL - measured 34 cycles Reg-Reg\r
+\t\t  9\'bx_1011_1100 : wctrl = 5\'b01_111;\t// MULL\r
+\t\t  9\'bx_0110_1x11 : wctrl = 5\'b10_001;\t// ADDP,SUBP\r
+\t\t  9\'bx_0111_1001 : wctrl = 5\'b00_111;\t// MEIi\r
+\t\t  9\'bx_0111_1011 : wctrl = 5\'b10_111;\t// DEIi\r
+\t\t  9\'bx_0111_11xx : wctrl = 5\'b10_001;\t// QUOi,REMi,MODi,DIVi\r
+\t\t  9\'b1_1011_011x : wctrl = 5\'b00_010;\t// SCALBF/LOGBF\r
+\t\t  9\'b0_1011_011x : wctrl = 5\'b01_111;\t// SCALBL/LOGBL\r
+\t\t  9\'bx_1101_1101 : wctrl = {4\'b10_00,copwr};\t// execute coprocessor opcode\r
+\t\t  default      \t : wctrl = 5\'b0;\r
+\t\tendcase\r
+\r
+\tassign done_i = wctrl[4] ? (div_done | bcd_done | COP_DONE) : ( (wctrl[3] | ~WR_REG) ? sequ[2] : sequ[1] );\r
+\tassign DONE = ~START[1] & done_i;\t// DONE is valid for all opcodes\r
+\r
+\tassign wr_part1 = DONE & WR_REG & wctrl[0];\r
+\t\r
+\talways @(posedge BCLK) CLR_LSB \t<= DONE & WR_REG & wctrl[2];\r
+\talways @(posedge BCLK) wr_part2 <= DONE & WR_REG & wctrl[1];\r
+\t\r
+\tassign WREN_L \t= wr_part1 | wr_part2;\r
+\tassign LD_OUT_L\t= DONE & ~WR_REG;\t\t// meaning is ""Load Out-Reg from Long-Path""\r
+\t\r
+\talways @(posedge BCLK) up_flag <= DONE & ~wctrl[0];\t\t// DONE one cycle later\r
+\tassign UP_DP    = (select[3] & (wctrl[0] ? DONE : up_flag)) | man_ops;\t// Update FSR Trap etc. : all FPU opcodes of DP_FPU\r
+\t\r
+\t// Overflow Trap for Division : DEI, QUO, DIV\r
+\tassign quo_div = (OPCODE == 8\'h7C) | (OPCODE == 8\'h7F);\r
+\talways @(*)\r
+\t\tcasex ({OPCODE[2],BWD})\r
+\t\t   3\'b100 : ovf_div = (divi_out[39] & SRC1[7]  & SRC2[7] ) & quo_div;\r
+\t\t   3\'b101 : ovf_div = (divi_out[47] & SRC1[15] & SRC2[15]) & quo_div;\r
+\t\t   3\'b11x : ovf_div = (divi_out[63] & SRC1[31] & SRC2[31]) & quo_div;\r
+\t\t  default : ovf_div = dei_ovf[0] & (OPCODE == 8\'h7B);\t// DEI\r
+\t\tendcase\r
+\t\t  \r
+\tassign OVF_BCD = {dei_ovf[1],ovf_div,bcd_done,bcd_carry};\t// to I_PFAD\r
+\t\r
+\talways @(posedge BCLK) COP_GO <= START[1] & copop;\r
+\r
+endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+// 10. DP_FPU\t\tTop level of long operations datapath\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module DP_FPU( BCLK, FL, BRESET, LD_LDQ, WR_REG, BWD, FSR, OPCODE, SRC1, SRC2, START, DONE, UP_DP, WREN_L,\r
+\t\t\t   CLR_LSB, LD_OUT_L, DVZ_TRAP, DP_CMP, DP_OUT, DP_Q, TT_DP, CY_IN, OVF_BCD, COP_GO, COP_OP,\r
+\t\t\t   COP_IN, COP_DONE, COP_OUT );\r
+\r
+input\t\t\tBCLK;\r
+input\t\t\tFL;\r
+input\t\t\tBRESET;\r
+input\t\t\tLD_LDQ;\r
+input\t\t\tWR_REG;\r
+input\t [1:0]\tBWD;\r
+input\t [8:3]\tFSR;\r
+input\t [7:0]\tOPCODE;\r
+input\t[31:0]\tSRC1;\r
+input\t[31:0]\tSRC2;\r
+input\t [1:0]\tSTART;\r
+input\t\t\tCY_IN;\r
+input\t\t\tCOP_DONE;\r
+input\t[23:0]\tCOP_OP;\r
+input\t[63:0]\tCOP_IN;\r
+\r
+output\t\t\tDONE;\r
+output\t\t\tUP_DP;\r
+output\t\t\tWREN_L;\r
+output\t\t\tCLR_LSB;\r
+output\t\t\tLD_OUT_L;\r
+output\t\t\tDVZ_TRAP;\r
+output\t [2:0]\tDP_CMP;\r
+output\t[31:0]\tDP_OUT;\r
+output\t[31:0]\tDP_Q;\r
+output\t [4:0]\tTT_DP;\r
+output\t [3:0]\tOVF_BCD;\r
+output\t\t\tCOP_GO;\r
+output [127:0]\tCOP_OUT;\r
+\r
+reg\t\t[52:0]\tMDA;\r
+reg\t\t[52:0]\tMDB;\r
+reg\t\t[31:0]\tDP_Q;\r
+reg\t   [31:20]\tRCOPA,RCOPB;\r
+\r
+wire\t[63:0]\tDOUT;\r
+wire   [105:0]\tMRESULT;\r
+wire\t\t\tMEI;\r
+wire\t\t\tDFLOAT;\r
+wire\t\t\tLOAD_MSD;\r
+wire\t\t\tLOAD_LSD1;\r
+wire\t\t\tLOAD_LSD2;\r
+wire\t[31:0]\tLSD_1;\r
+wire\t[31:0]\tLSD_2;\r
+wire   [52:32]\tMSD_1;\r
+wire   [52:32]\tMSD_2;\r
+\r
+\r
+DP_LOGIK\tDOUBLE_U(\r
+\t.FL(FL),\r
+\t.BRESET(BRESET),\r
+\t.BCLK(BCLK),\r
+\t.WR_REG(WR_REG),\r
+\t.BWD(BWD),\r
+\t.FSR(FSR),\r
+\t.MAN1(MDA[52:32]),\r
+\t.MAN2(MDB[52:32]),\r
+\t.MRESULT(MRESULT),\r
+\t.OPCODE(OPCODE),\r
+\t.SRC1(SRC1),\r
+\t.SRC2(SRC2),\r
+\t.START(START),\r
+\t.MEI(MEI),\r
+\t.DFLOAT(DFLOAT),\r
+\t.DONE(DONE),\r
+\t.UP_DP(UP_DP),\r
+\t.CLR_LSB(CLR_LSB),\r
+\t.WREN_L(WREN_L),\r
+\t.LD_OUT_L(LD_OUT_L),\r
+\t.DVZ_TRAP(DVZ_TRAP),\r
+\t.DOUT(DOUT),\r
+\t.DP_CMP(DP_CMP),\r
+\t.TT_DP(TT_DP),\r
+\t.CY_IN(CY_IN),\r
+\t.OVF_BCD(OVF_BCD),\r
+\t.COP_DONE(COP_DONE),\r
+\t.COP_OP(COP_OP),\r
+\t.COP_IN(COP_IN),\r
+\t.COP_GO(COP_GO));\r
+\r
+PREPDATA\tDP_PREP(\r
+\t.MEI(MEI),\r
+\t.DFLOAT(DFLOAT),\r
+\t.BWD(BWD),\r
+\t.SRC1(SRC1),\r
+\t.SRC2(SRC2),\r
+\t.START(START),\r
+\t.LOAD_LSD1(LOAD_LSD1),\r
+\t.LOAD_LSD2(LOAD_LSD2),\r
+\t.LOAD_MSD(LOAD_MSD),\r
+\t.LSD_1(LSD_1),\r
+\t.LSD_2(LSD_2),\r
+\t.MSD_1(MSD_1),\r
+\t.MSD_2(MSD_2));\r
+\r
+\tassign MRESULT =  {21\'d0,MDA[31:0]} * {21\'d0,MDB[31:0]};\t// unsigned multiplier 53 * 53 bits = 106 bits\r
+\t\r
+\tassign DP_OUT = CLR_LSB ? DP_Q : DOUT[63:32];\r
+\t\r
+\talways@(posedge BCLK) if (LD_OUT_L || LD_LDQ || WREN_L) DP_Q <= LD_LDQ ? SRC2 : DOUT[31:0];\r
+\r
+\talways@(posedge BCLK) if (LOAD_LSD1) MDA[31:0] <= LSD_1;\r
+\r
+\talways@(posedge BCLK) if (LOAD_LSD2) MDB[31:0] <= LSD_2;\r
+\r
+\talways@(posedge BCLK)\r
+\t\tif (LOAD_MSD)\r
+\t\t\tbegin\r
+\t\t\t\tMDA[52:32] <= MSD_1;\r
+\t\t\t\tMDB[52:32] <= MSD_2;\r
+\t\t\t\tRCOPA\t   <= SRC1[31:20];\r
+\t\t\t\tRCOPB\t   <= SRC2[31:20];\r
+\t\t\tend\r
+\t\t\t\r
+\tassign COP_OUT = {RCOPA,MDA[51:32],SRC1,RCOPB,MDB[51:32],SRC2};\r
+\r
+endmodule\r
+"
+"// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+// This file is part of the M32632 project\r
+// http://opencores.org/project,m32632\r
+//\r
+// Filename: DATENPFAD.v\r
+// Version:  1.1 bug fix\r
+// History:  1.0 first release of 30 Mai 2015\r
+// Date:     7 October 2015\r
+//\r
+// Copyright (C) 2015 Udo Moeller\r
+// \r
+// This source file may be used and distributed without \r
+// restriction provided that this copyright statement is not \r
+// removed from the file and that any derivative work contains \r
+// the original copyright notice and the associated disclaimer.\r
+// \r
+// This source file is free software; you can redistribute it \r
+// and/or modify it under the terms of the GNU Lesser General \r
+// Public License as published by the Free Software Foundation;\r
+// either version 2.1 of the License, or (at your option) any \r
+// later version. \r
+// \r
+// This source is distributed in the hope that it will be \r
+// useful, but WITHOUT ANY WARRANTY; without even the implied \r
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR \r
+// PURPOSE. See the GNU Lesser General Public License for more \r
+// details. \r
+// \r
+// You should have received a copy of the GNU Lesser General \r
+// Public License along with this source; if not, download it \r
+// from http://www.opencores.org/lgpl.shtml \r
+// \r
+// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\tModules contained in this file:\r
+//\tDATENPFAD\tthe data path of M32632\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+module DATENPFAD( BCLK, BRESET, WREN, IO_READY, LD_DIN, LD_IMME, WR_REG, IC_USER, ACC_FELD, ACC_STAT, DIN, DISP, IC_TEX,\r
+\t\t\t\t  IMME_Q, INFO_AU, LD_OUT, DETOIP, MMU_UPDATE, OPER, PC_ARCHI, PC_ICACHE, RDAA, RDAB, START, WMASKE, \r
+\t\t\t\t  WRADR, DONE, Y_INIT, WRITE_OUT, READ_OUT, ZTEST, RMW, QWATWO, ACC_DONE, REG_OUT, PTB_SEL, PTB_WR, ACB_ZERO, \r
+\t\t\t\t  ABORT, SAVE_PC, CFG, CINV, DP_Q, IVAR, MCR, PACKET, PC_NEW, PSR, SIZE, STRING, TRAPS, VADR, RWVFLAG, \r
+\t\t\t\t  DBG_HIT, DBG_IN, COP_GO, COP_OP, COP_IN, COP_DONE, COP_OUT);\r
+\r
+input\t\t\tBCLK;\r
+input\t\t\tBRESET;\r
+input\t\t\tWREN;\t\t// write enable of the register file\r
+input\t\t\tIO_READY;\r
+input\t\t\tLD_DIN;\r
+input\t\t\tLD_IMME;\r
+input\t\t\tWR_REG;\t\t// write signal for the DP_FPU\r
+input\t\t\tIC_USER;\r
+input\t\t\tRWVFLAG;\r
+input\t[14:0]\tACC_FELD;\r
+input\t [5:0] \tACC_STAT;\r
+input\t[31:0] \tDIN;\r
+input\t[31:0] \tDISP;\r
+input\t [2:0] \tIC_TEX;\r
+input\t[31:0] \tIMME_Q;\r
+input\t [6:0] \tINFO_AU;\r
+input\t [1:0] \tLD_OUT;\r
+input\t[12:0] \tDETOIP;\r
+input\t [1:0] \tMMU_UPDATE;\r
+input\t[10:0] \tOPER;\r
+input\t[31:0] \tPC_ARCHI;\r
+input\t[31:0] \tPC_ICACHE;\r
+input\t [7:0] \tRDAA;\r
+input\t [7:0] \tRDAB;\r
+input\t [1:0] \tSTART;\r
+input\t [1:0] \tWMASKE;\r
+input\t [5:0] \tWRADR;\r
+input\t\t\tDBG_HIT;\r
+input\t\t\tCOP_DONE;\r
+input\t[23:0]\tCOP_OP;\r
+input\t[63:0]\tCOP_IN;\r
+\r
+output\t\t\tDONE;\r
+output \t\t\tY_INIT;\r
+output\t\t\tWRITE_OUT;\r
+output\t\t\tREAD_OUT;\r
+output\t\t\tZTEST;\r
+output \t\t\tRMW;\r
+output\t\t\tQWATWO;\r
+output\t\t\tACC_DONE;\r
+output\t\t\tREG_OUT;\r
+output\t\t\tPTB_SEL;\r
+output\t\t\tPTB_WR;\r
+output reg\t\tACB_ZERO;\r
+output\t\t\tABORT;\r
+output \t\t\tSAVE_PC;\r
+output\t[12:0]\tCFG;\r
+output\t [3:0]\tCINV;\r
+output\t[63:0]\tDP_Q;\r
+output\t [1:0]\tIVAR;\r
+output\t [3:0]\tMCR;\r
+output\t [3:0]\tPACKET;\r
+output  [31:0]\tPC_NEW;\r
+output  [11:0]\tPSR;\r
+output\t [1:0]\tSIZE;\r
+output\t [4:0]\tSTRING;\r
+output\t [5:0]\tTRAPS;\r
+output\t[31:0]\tVADR;\r
+output\t[40:2]\tDBG_IN;\r
+output\t\t\tCOP_GO;\r
+output [127:0]\tCOP_OUT;\r
+\r
+reg  \t[31:0]\thigh_dq;\r
+reg\t\t[31:0]\tOUT_I;\r
+reg\t\t[31:0]\tBYDIN;\t\t// the bypass register\r
+\r
+wire\t [2:0]\tBITSEL;\r
+wire\t [1:0]\tBWD;\r
+wire\t\t\tCLR_LSB;\r
+wire\t[31:0]\tERGEBNIS;\t// the result bus\r
+wire\t\t\tFL;\r
+wire\t[31:0]\tFSR;\r
+wire\t[63:0]\tMRESULT;\r
+wire\t [7:0]\tOPCODE;\r
+wire\t\t\tSELI_A;\r
+wire\t\t\tSELI_B;\r
+wire\t [2:0]\tSP_CMP;\r
+wire\t[31:0]\tSRC1;\t\t// the bus for the Source 1 operand\r
+wire\t[31:0]\tSRC2;\t\t// the bus for the Source 2 operand\r
+wire\t [4:0]\tTT_DP;\r
+wire\t\t\tTWREN;\t\t// active if FPU Trap occurs\r
+wire\t\t\tUP_DP;\r
+wire\t\t\tWRADR_0;\r
+wire\t\t\tWREN_L,WREN_LX;\r
+wire\t\t\tLD_FSR;\r
+wire\t\t\tUP_SP;\r
+wire\t [4:0]\tTT_SP;\r
+wire\t[31:0]\taddr_i;\r
+wire\t [2:0]\tDP_CMP;\r
+wire\t[31:0]\tDP_OUT;\r
+wire\t[31:0]\tSFP_DAT;\r
+wire\t\t\tld_out_l;\r
+wire\t [6:0]\tBMCODE;\r
+wire\t[31:0]\tOUT_A,OUT_B;\r
+wire\t\t\tSP_MUX;\r
+wire\t[31:0]\tI_OUT;\r
+wire\t[31:0]\tFP_OUT;\r
+wire\t\t\tDOWR;\r
+wire\t[31:0]\tDEST1,DEST2;\r
+wire\t\t\tENWR;\r
+wire\t [3:0]\tOVF_BCD;\r
+wire\t [3:0]\tDSR;\r
+wire\t\t\tacb_zero_i;\r
+wire  \t[31:0] \tBMASKE;\r
+\r
+assign\tFL \t   = OPER[10];\r
+assign\tBWD\t   = OPER[9:8];\r
+assign\tOPCODE = OPER[7:0];\r
+\r
+assign\tERGEBNIS = SP_MUX ? FP_OUT : I_OUT;\r
+\r
+assign\tWRADR_0 = WRADR[0] ^ CLR_LSB;\r
+assign\tENWR = WREN_L | WREN;\r
+assign\tDOWR = ENWR & TWREN;\r
+\t\r
+assign\tWREN_L = WREN_LX & ~TRAPS[0];\r
+\r
+assign\tDP_Q[63:32] = high_dq;\r
+\r
+assign\tPC_NEW = SRC1;\r
+\r
+always @(posedge BCLK) if (LD_OUT[1] || WREN)\t ACB_ZERO <= acb_zero_i;\r
+\r
+always @(posedge BCLK) if (LD_OUT[1] || ld_out_l) high_dq <= ERGEBNIS;\r
+\r
+always @(posedge BCLK) if (LD_DIN) OUT_I <= LD_IMME ? IMME_Q : DIN;\r
+\r
+always @(posedge BCLK) if (RDAA[7]) BYDIN <= ERGEBNIS;\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+// Register Set 1 => SRC1\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+REGISTER\tREG_SET_A(\r
+\t.BCLK(BCLK),\r
+\t.ENWR(ENWR),\r
+\t.DOWR(DOWR),\r
+\t.DIN(ERGEBNIS),\r
+\t.BYDIN(BYDIN),\r
+\t.RADR(RDAA),\r
+\t.WADR({WRADR[5:1],WRADR_0}),\r
+\t.WMASKE(WMASKE),\r
+\t.SELI(SELI_A),\r
+\t.DOUT(OUT_A));\r
+\r
+assign SRC1 = SELI_A ? OUT_I : OUT_A;\r
+\t\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+// Register Set 2 => SRC2\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+REGISTER\tREG_SET_B(\r
+\t.BCLK(BCLK),\r
+\t.ENWR(ENWR),\r
+\t.DOWR(DOWR),\r
+\t.DIN(ERGEBNIS),\r
+\t.BYDIN(BYDIN),\r
+\t.RADR(RDAB),\r
+\t.WADR({WRADR[5:1],WRADR_0}),\r
+\t.WMASKE(WMASKE),\r
+\t.SELI(SELI_B),\r
+\t.DOUT(OUT_B));\r
+\r
+assign SRC2 = SELI_B ? OUT_I : OUT_B;\r
+\r
+MULFILTER\tM_FILTER(\r
+\t.FLOAT(OPCODE[2]),\r
+\t.BWD(BWD),\r
+\t.SRC1(SRC1),\r
+\t.SRC2(SRC2),\r
+\t.DEST1(DEST1),\r
+\t.DEST2(DEST2));\r
+\r
+SIGNMUL\t\tS_MULTI(\t\t// signed multiplier 32 * 32 bits = 64 bits\r
+\t.dataa(DEST1),\r
+\t.datab(DEST2),\r
+\t.result(MRESULT));\r
+\t\r
+BITMASK  BITM_U(\r
+\t.AA(BMCODE),\r
+\t.DOUT(BMASKE));\r
+\t\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+// The integer data path\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+I_PFAD\tGANZ_U(\r
+\t.FL(FL),\r
+\t.BRESET(BRESET),\r
+\t.BCLK(BCLK),\r
+\t.WREN(WREN),\r
+\t.LD_OUT(LD_OUT[1]),\r
+\t.ADDR(addr_i),\r
+\t.BITSEL(BITSEL),\r
+\t.BMASKE(BMASKE),\r
+\t.BWD(BWD),\r
+\t.DP_CMP(DP_CMP),\r
+\t.DP_OUT(DP_OUT),\r
+\t.FSR(FSR),\r
+\t.DETOIP(DETOIP[11:0]),\r
+\t.MRESULT(MRESULT),\r
+\t.OPCODE(OPCODE),\r
+\t.RDAA(RDAA),\r
+\t.SFP_DAT(SFP_DAT),\r
+\t.SP_CMP(SP_CMP),\r
+\t.SRC1(SRC1),\r
+\t.SRC2(SRC2),\r
+\t.WRADR(WRADR),\r
+\t.DSR(DSR),\t\r
+\t.OV_FLAG(TRAPS[2]),\r
+\t.ACB_ZERO(acb_zero_i),\r
+\t.BMCODE(BMCODE),\r
+\t.I_OUT(I_OUT),\r
+\t.PSR(PSR),\r
+\t.STRING(STRING),\r
+\t.OVF_BCD(OVF_BCD),\r
+\t.DISP(DISP[4:0]),\r
+\t.RWVFLAG(RWVFLAG));\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+// The address unit\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+ADDR_UNIT\tADDR_U(\r
+\t.BCLK(BCLK),\r
+\t.BRESET(BRESET),\r
+\t.IO_READY(IO_READY),\r
+\t.READ(ACC_FELD[11]),\r
+\t.WRITE(ACC_FELD[10]),\r
+\t.CLRMSW(ACC_FELD[2]),\r
+\t.FULLACC(ACC_FELD[8]),\r
+\t.POST(ACC_FELD[3]),\r
+\t.DISP_OK(INFO_AU[0]),\r
+\t.LDEA(ACC_FELD[9]),\r
+\t.NEWACC(ACC_FELD[14]),\r
+\t.FPU_TRAP(TRAPS[0]),\r
+\t.ADIVAR(INFO_AU[2]),\r
+\t.RWVAL_1(INFO_AU[3]),\r
+\t.ABO_STAT({INFO_AU[1],IC_USER}),\r
+\t.ACC_STAT(ACC_STAT),\r
+\t.ASIZE(ACC_FELD[13:12]),\r
+\t.BWD(BWD),\r
+\t.DISP(DISP),\r
+\t.IC_TEX(IC_TEX),\r
+\t.INDEX(ACC_FELD[7:4]),\r
+\t.MMU_UPDATE(MMU_UPDATE),\r
+\t.PC_ARCHI(PC_ARCHI),\r
+\t.PC_ICACHE(PC_ICACHE),\r
+\t.SRC1(SRC1),\r
+\t.SRC2(SRC2),\r
+\t.SRC2SEL(ACC_FELD[1:0]),\r
+\t.REG_OUT(REG_OUT),\r
+\t.ACC_DONE(ACC_DONE),\r
+\t.READ_OUT(READ_OUT),\r
+\t.WRITE_OUT(WRITE_OUT),\r
+\t.ABORT(ABORT),\r
+\t.ADDR(addr_i),\r
+\t.BITSEL(BITSEL),\r
+\t.PACKET(PACKET),\r
+\t.SIZE(SIZE),\r
+\t.VADR(VADR),\r
+\t.ZTEST(ZTEST),\r
+\t.RMW(RMW),\r
+\t.QWATWO(QWATWO),\r
+\t.OP_RMW(INFO_AU[4]),\r
+\t.PHASE_17(INFO_AU[5]),\r
+\t.NO_TRAP(INFO_AU[6]) );\r
+\t\r
+CONFIG_REGS\tCFG_DBG(\r
+\t.BCLK(BCLK),\r
+\t.BRESET(BRESET),\r
+\t.WREN(WREN),\r
+\t.LD_OUT(LD_OUT[1]),\r
+\t.OPCODE(OPCODE),\r
+\t.SRC1(SRC1),\r
+\t.WRADR(WRADR),\r
+\t.PTB_WR(PTB_WR),\r
+\t.PTB_SEL(PTB_SEL),\r
+\t.CFG(CFG),\r
+\t.CINV(CINV),\r
+\t.IVAR(IVAR),\r
+\t.Y_INIT(Y_INIT),\r
+\t.MCR(MCR),\r
+\t.DBG_TRAPS(TRAPS[5:3]),\r
+\t.PC_ARCHI(PC_ARCHI),\r
+\t.DSR(DSR),\r
+\t.USER(PSR[8]),\r
+\t.PCMATCH(DETOIP[12]),\r
+\t.DBG_IN(DBG_IN),\r
+\t.DBG_HIT(DBG_HIT),\r
+\t.READ(READ_OUT) );\r
+\t\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+// The long operation unit\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+DP_FPU\tDOUBLE_U(\r
+\t.BCLK(BCLK),\r
+\t.FL(FL),\r
+\t.BRESET(BRESET),\r
+\t.LD_LDQ(LD_OUT[0]),\r
+\t.WR_REG(WR_REG),\r
+\t.BWD(BWD),\r
+\t.FSR(FSR[8:3]),\r
+\t.OPCODE(OPCODE),\r
+\t.SRC1(SRC1),\r
+\t.SRC2(SRC2),\r
+\t.START(START),\r
+\t.DONE(DONE),\r
+\t.UP_DP(UP_DP),\r
+\t.WREN_L(WREN_LX),\r
+\t.CLR_LSB(CLR_LSB),\r
+\t.LD_OUT_L(ld_out_l),\r
+\t.DVZ_TRAP(TRAPS[1]),\r
+\t.DP_CMP(DP_CMP),\r
+\t.DP_OUT(DP_OUT),\r
+\t.DP_Q(DP_Q[31:0]),\r
+\t.TT_DP(TT_DP),\r
+\t.CY_IN(PSR[0]),\r
+\t.OVF_BCD(OVF_BCD),\r
+\t.COP_DONE(COP_DONE),\r
+\t.COP_OP(COP_OP),\r
+\t.COP_IN(COP_IN),\r
+\t.COP_GO(COP_GO),\r
+\t.COP_OUT(COP_OUT));\r
+\t\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+// The single precision floating point unit\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//SP_FPU\tSINGLE_U(\r
+//\t.FL(FL),\r
+//\t.BCLK(BCLK),\r
+//\t.BWD(BWD),\r
+//\t.FSR(FSR[8:3]),\r
+//\t.MRESULT(MRESULT[47:0]),\r
+//\t.OPCODE(OPCODE),\r
+//\t.SRC1(SRC1),\r
+//\t.SRC2(SRC2),\r
+//\t.LD_FSR(LD_FSR),\r
+//\t.SP_MUX(SP_MUX),\r
+//\t.UP_SP(UP_SP),\r
+//\t.FP_OUT(FP_OUT),\r
+//\t.I_OUT(SFP_DAT),\r
+//\t.SP_CMP(SP_CMP),\r
+//\t.TT_SP(TT_SP));\r
+\r
+   assign FP_OUT  = 32'b0;\r
+   assign SFP_DAT = 32'b0;\r
+   assign TT_SP   = 5'b0;\r
+   assign SP_CMP  = 3'b0;\r
+   assign SP_MUX  = 1'b0;\r
+   assign LD_FSR  = 1'b0;\r
+   assign UP_SP   = 1'b0;\r
+   \r
+FP_STAT_REG\tFPS_REG(\r
+\t.BCLK(BCLK),\r
+\t.BRESET(BRESET),\r
+\t.LFSR(LD_FSR),\r
+\t.WREN(ENWR),\r
+\t.WRADR(WRADR[5:4]),\r
+\t.UP_DP(UP_DP),\r
+\t.UP_SP(UP_SP & LD_OUT[1]),\r
+\t.DIN(SRC1[16:0]),\r
+\t.TT_DP(TT_DP),\r
+\t.TT_SP(TT_SP),\r
+\t.FPU_TRAP(TRAPS[0]),\r
+\t.TWREN(TWREN),\r
+\t.SAVE_PC(SAVE_PC),\r
+\t.FSR(FSR));\r
+\r
+endmodule\r
+"
+"//**************************************************************************
+//    hp_byte.v - single byte buffer for transfers in host to parasite direction
+//   
+//    COPYRIGHT 2010 Richard Evans, Ed Spittles
+// 
+//    This file is part of tube - an Acorn Tube ULA compatible system.
+//   
+//    tube is free software: you can redistribute it and/or modify
+//    it under the terms of the GNU Lesser General Public License as published by
+//    the Free Software Foundation, either version 3 of the License, or
+//    (at your option) any later version.
+//
+//    tube is distributed in the hope that it will be useful,
+//    but WITHOUT ANY WARRANTY; without even the implied warranty of
+//    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//    GNU Lesser General Public License for more details.
+//
+//    You should have received a copy of the GNU Lesser General Public License
+//    along with tube.  If not, see <http://www.gnu.org/licenses/>.
+//
+// **************************************************************************
+`timescale 1ns / 1ns
+
+module hp_byte (
+                  input h_rst_b,
+                  input h_we_b,
+                  input h_selectData,
+                  input h_phi2,
+                  input [7:0] h_data,
+                  
+                  input p_selectData,
+                  input p_phi2,
+                  input p_rdnw,                                
+                  output [7:0] p_data,
+                  output p_data_available,
+                  output h_full
+                  );
+
+   
+   reg [7:0] fifo_q_r ;
+   wire [7:0] fifo_d_w ;
+
+   // assign primary IOs
+   assign p_data = fifo_q_r;   
+   
+   // Compute D and resets for state bits
+   assign fifo_d_w = ( h_selectData & !h_we_b ) ? h_data : fifo_q_r;
+
+   // Instance the appropriate flag logic
+   hp_flag_m flag_0 (
+                       .rst_b(h_rst_b),
+                       .p1_rdnw( h_we_b),
+                       .p1_select(h_selectData),
+                       .p1_clk(h_phi2),
+                       .p2_select(p_selectData),
+                       .p2_rdnw(p_rdnw),
+                       .p2_clk(p_phi2 ),
+                       .p2_data_available(p_data_available),
+                       .p1_full(h_full)
+                       );
+
+   // All state inferences
+   always @ ( negedge h_phi2 or negedge h_rst_b )
+     begin
+        if ( ! h_rst_b)
+          fifo_q_r <= 8'b0;             
+        else
+          fifo_q_r <= fifo_d_w ;             
+     end
+   
+endmodule // hp_byte
+
+   "
+"/*
+ *  Zet SoC top level file for Altera DE1 board
+ *  Copyright (C) 2009, 2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+module LX9CoPro80186 (
+
+        input fastclk,
+        
+        // GOP Signals
+        inout [8:1] test,
+        input [3:0] sw,
+        
+        // Tube signals (use 16 out of 22 DIL pins)
+        input h_phi2,
+        input [2:0] h_addr,
+        inout [7:0] h_data,
+        input h_rdnw,
+        input h_cs_b,
+        input h_rst_b,
+        output h_irq_b,
+
+        // Ram Signals
+        output ram_ub_b,
+        output ram_lb_b,
+        output ram_cs,
+        output ram_oe,
+        output ram_wr,
+        output [18:0] ram_addr,
+        inout  [15:0] ram_data
+);
+
+  // Registers and nets
+  wire        clk;
+  wire        rst_lck;
+  wire [15:0] dat_o;
+  wire [15:0] dat_i;
+  wire [19:1] adr;
+  wire        we;
+  wire        tga;
+  wire [ 1:0] sel;
+  wire        stb;
+  wire        cyc;
+  wire        ack;
+  wire        lock;
+
+  // wires to BIOS ROM
+  wire [15:0] rom_dat_o;
+  wire [15:0] rom_dat_i;
+  wire        rom_tga_i;
+  wire [19:1] rom_adr_i;
+  wire [ 1:0] rom_sel_i;
+  wire        rom_we_i;
+  wire        rom_cyc_i;
+  wire        rom_stb_i;
+  wire        rom_ack_o;
+  
+    // wires to RAM
+  wire [15:0] ram_dat_o;
+  wire [15:0] ram_dat_i;
+  wire        ram_tga_i;
+  wire [19:1] ram_adr_i;
+  wire [ 1:0] ram_sel_i;
+  wire        ram_we_i;
+  wire        ram_cyc_i;
+  wire        ram_stb_i;
+  wire        ram_ack_o;
+
+  wire [18:0] ram_addr_int;
+
+  // wires to Tube
+  wire [15:0] tube_dat_o;
+  wire [15:0] tube_dat_i;
+  wire        tube_tga_i;
+  wire [19:1] tube_adr_i;
+  wire [ 1:0] tube_sel_i;
+  wire        tube_we_i;
+  wire        tube_cyc_i;
+  wire        tube_stb_i;
+  wire        tube_ack_o;
+
+
+  wire        drq;
+  wire        dack_b;
+  
+  wire [2:0]  p_addr;
+  wire        p_cs_b; 
+  wire [7:0]  p_data; 
+  wire        p_rd_b; 
+  wire        p_wr_b;
+  wire        p_rst_b;
+  wire        p_nmi_b;
+  wire        p_irq_b;
+
+
+  // unused slaves
+  wire        s3_cyc_i;
+  wire        s3_stb_i;
+  wire        s4_cyc_i;
+  wire        s4_stb_i;
+  wire        s5_cyc_i;
+  wire        s5_stb_i;
+  wire        s6_cyc_i;
+  wire        s6_stb_i;
+  wire        s7_cyc_i;
+  wire        s7_stb_i;
+  wire        s9_cyc_i;
+  wire        s9_stb_i;
+  wire        sa_cyc_i;
+  wire        sa_stb_i;
+  wire        def_cyc_i;
+  wire        def_stb_i;
+
+
+  // wires to default stb/ack
+  wire [15:0] sw_dat_o;
+
+  wire [ 7:0] intv;
+  wire [ 2:0] iid;
+  wire        intr;
+  wire        inta;
+
+  wire        nmi;
+  wire        nmia;
+  
+  reg tubeint0;
+  reg tubeint1;
+  reg tubeint2;
+  reg tubeint3;
+  reg tubenmi0;
+  reg tubenmi1;
+  reg tubenmi2;
+  reg tubenmi3;
+  
+  wire [19:0] pc;
+  wire trigger;
+  reg [8:0] reset_counter;
+
+  wire [3:0] sw_out;
+   
+  ICAP_config inst_ICAP_config (
+    .fastclk(fastclk),
+    .sw_in  (sw),
+    .sw_out (sw_out),
+    .h_addr (h_addr),
+    .h_cs_b (h_cs_b),
+    .h_data (h_data),
+    .h_phi2 (h_phi2),
+    .h_rdnw (h_rdnw),
+    .h_rst_b(h_rst_b)
+  );
+   
+  
+  dcm_32_12 inst_dcm (
+    .CLKIN_IN(fastclk), 
+    .CLK0_OUT(clk), 
+    .CLK0_OUT1(), 
+    .CLK2X_OUT()
+  );
+
+  // Ensure reset is held active for 256 clock cycles on power up
+  // Needed as Beeb's reset is missed when using multiboot loader as initialization takes too long
+  always @(posedge clk)
+  begin
+      if (reset_counter[8] == 0)
+          reset_counter <= reset_counter + 1;
+  end
+    
+  wire rst;
+  assign rst = !p_rst_b | !reset_counter[8];
+
+
+  bootrom bootrom (
+    .clk (clk),            // Wishbone slave interface
+    .rst (rst),
+    .wb_dat_i (rom_dat_i),
+    .wb_dat_o (rom_dat_o),
+    .wb_adr_i (rom_adr_i),
+    .wb_we_i  (rom_we_i ),
+    .wb_tga_i (rom_tga_i),
+    .wb_stb_i (rom_stb_i),
+    .wb_cyc_i (rom_cyc_i),
+    .wb_sel_i (rom_sel_i),
+    .wb_ack_o (rom_ack_o)
+  );
+  
+wb_sram16 wb_sram16 (
+    .clk(clk), 
+    .reset(rst), 
+    .wb_dat_i(ram_dat_i), 
+    .wb_dat_o(ram_dat_o), 
+    .wb_adr_i(ram_adr_i), 
+    .wb_we_i(ram_we_i),
+    .wb_tga_i(ram_tga_i),
+    .wb_stb_i(ram_stb_i), 
+    .wb_cyc_i(ram_cyc_i), 
+    .wb_sel_i(ram_sel_i), 
+    .wb_ack_o(ram_ack_o),
+    
+    .sram_adr(ram_addr_int), 
+    .sram_dat(ram_data), 
+    .sram_be_n({ram_ub_b, ram_lb_b}), 
+    .sram_ce_n(ram_cs), 
+    .sram_oe_n(ram_oe), 
+    .sram_we_n(ram_wr)
+    );
+
+wb_tube wb_tube_inst(
+    .clk(clk), 
+    .reset(rst), 
+    .wb_stb_i(tube_stb_i), 
+    .wb_cyc_i(tube_cyc_i), 
+    .wb_ack_o(tube_ack_o), 
+    .wb_we_i(tube_we_i),
+    .wb_tga_i(tube_tga_i),
+    .wb_adr_i(tube_adr_i[3:1]), 
+    .wb_sel_i(tube_sel_i), 
+    .wb_dat_i(tube_dat_i), 
+    .wb_dat_o(tube_dat_o), 
+    .tube_adr(p_addr), 
+    .tube_dat(p_data), 
+    .tube_cs_n(p_cs_b), 
+    .tube_rd_n(p_rd_b), 
+    .tube_wr_n(p_wr_b)
+    );
+    
+tube tube_inst(
+    .h_addr(h_addr), 
+    .h_cs_b(h_cs_b), 
+    .h_data(h_data), 
+    .h_phi2(h_phi2), 
+    .h_rdnw(h_rdnw), 
+    .h_rst_b(h_rst_b), 
+    .h_irq_b(), 
+    .p_addr(p_addr), 
+    .p_cs_b(p_cs_b), 
+    .p_data(p_data),
+    .p_rdnw(p_wr_b), 
+    .p_phi2(clk), 
+    .p_rst_b(p_rst_b), 
+    .p_nmi_b(p_nmi_b), 
+    .p_irq_b(p_irq_b)
+    );
+
+//  simple_pic pic0 (
+//    .clk  (clk),
+//    .rst  (rst),
+//    .intv (intv),
+//    .inta (inta),
+//    .intr (intr),
+//    .iid  (iid)
+//  );
+
+
+  zet zet (
+    .pc (pc),
+
+    // Wishbone master interface
+    .wb_clk_i (clk),
+    .wb_rst_i (rst),
+    .wb_dat_i (dat_i),
+    .wb_dat_o (dat_o),
+    .wb_adr_o (adr),
+    .wb_we_o  (we),
+    .wb_tga_o (tga),
+    .wb_sel_o (sel),
+    .wb_stb_o (stb),
+    .wb_cyc_o (cyc),
+    .wb_ack_i (ack),
+    .wb_tgc_i (intr),
+    .wb_tgc_o (inta),
+    .nmi      (nmi),
+    .nmia     (nmia)
+  );
+
+
+  // Interrupt Control Registers (0x20-0x3E)
+  // &0FF22 - EOI Register
+  // &0FF38 - INT0 Control Register                 
+
+  // Timer Control Registers (0x50-0x66)
+  // &0FF52                  
+  // &0FF56                  
+  // &0FF60                  
+  // &0FF62                  
+  // &0FF66
+
+  // Chip Select Control Registers (0xA0-0xA8)   
+  // &0FFA0                  
+  // &0FFA2                  
+  // &0FFA4                  
+  // &0FFA6                  
+  // &0FFA8                  
+
+  // DMA Channel 0 (0xC0 - 0xCA)
+  // &0FFC0                  
+  // &0FFC2                  
+  // &0FFC4                  
+  // &0FFC6                  
+  // &0FFCA
+  
+  wb_switch #(
+    .s0_addr_1 (20'b0_1111_0000_0000_0000_000), // bios boot mem 0xf0000 - 0xfffff
+    .s0_mask_1 (20'b1_1111_0000_0000_0000_000), // bios boot ROM Memory
+
+    .s1_addr_1 (20'b0_0000_0000_0000_0000_000), // mem 0x00000-0x7ffff
+    .s1_mask_1 (20'b1_1000_0000_0000_0000_000), // main memory
+
+    .s1_addr_2 (20'b0_1000_0000_0000_0000_000), // mem 0x80000-0xbffff
+    .s1_mask_2 (20'b1_1100_0000_0000_0000_000), // main memory
+
+    .s1_addr_3 (20'b0_1100_0000_0000_0000_000), // mem 0xC0000-0xDffff
+    .s1_mask_3 (20'b1_1110_0000_0000_0000_000), // main memory
+
+    .s1_addr_4 (20'b0_1110_0000_0000_0000_000), // mem 0xE0000-0xEffff
+    .s1_mask_4 (20'b1_1111_0000_0000_0000_000), // main memory
+
+    .s2_addr_1 (20'b1_0000_1111_1111_0010_000), // io 0xFF20 - 0xFF3E
+    .s2_mask_1 (20'b1_0000_1111_1111_1110_000), // Interrupt Control Registers
+
+    .s3_addr_1 (20'b1_0000_1111_1111_0101_000), // io 0xFF50 - 0xFF56
+    .s3_mask_1 (20'b1_0000_1111_1111_1111_100), // Timer Control 0 Registers
+
+    .s4_addr_1 (20'b1_0000_1111_1111_0101_100), // io 0xFF58 - 0xFF5E
+    .s4_mask_1 (20'b1_0000_1111_1111_1111_100), // Timer Control 1 Registers
+
+    .s5_addr_1 (20'b1_0000_1111_1111_0110_000), // io 0xFF60 - 0xFF66
+    .s5_mask_1 (20'b1_0000_1111_1111_1111_100), // Timer Control 2 Registers
+\t      
+    .s6_addr_1 (20'b1_0000_1111_1111_1010_000), // io 0xFFA0 - 0xFFAF
+    .s6_mask_1 (20'b1_0000_1111_1111_1111_000), // Chip Select Control Registers
+
+    .s7_addr_1 (20'b1_0000_1111_1111_1100_000), // io 0xFFC0 - 0xFFCf
+    .s7_mask_1 (20'b1_0000_1111_1111_1111_000), // DMA Channel 0
+
+    .s8_addr_1 (20'b1_0000_0000_0000_1000_000), // io 0x0080 - 0x008E
+    .s8_mask_1 (20'b1_0000_1111_1111_1111_000), // Tube ULA
+
+    .s9_addr_1 (20'b1_0000_0000_0000_0000_000), // Unused
+    .s9_mask_1 (20'b1_0000_1111_1111_1111_000), //
+
+    .sA_addr_1 (20'b1_0000_0000_0000_0000_000), // Unused
+    .sA_mask_1 (20'b1_0000_1111_1111_1111_000), //
+
+    .sA_addr_2 (20'b1_0000_0000_0000_0000_000), // Unused
+    .sA_mask_2 (20'b1_0000_1111_1111_1111_000)  //
+
+    ) wbs (
+
+    // Master interface
+    .m_dat_i (dat_o),
+    .m_dat_o (sw_dat_o),
+    .m_adr_i ({tga,adr}),
+    .m_sel_i (sel),
+    .m_we_i  (we),
+    .m_cyc_i (cyc),
+    .m_stb_i (stb),
+    .m_ack_o (ack),
+
+    // Slave 0 interface - bios rom
+    .s0_dat_i (rom_dat_o),
+    .s0_dat_o (rom_dat_i),
+    .s0_adr_o ({rom_tga_i,rom_adr_i}),
+    .s0_sel_o (rom_sel_i),
+    .s0_we_o  (rom_we_i),
+    .s0_cyc_o (rom_cyc_i),
+    .s0_stb_o (rom_stb_i),
+    .s0_ack_i (rom_ack_o),
+
+     // Slave 1 interface - main memory
+    .s1_dat_i (ram_dat_o),
+    .s1_dat_o (ram_dat_i),
+    .s1_adr_o ({ram_tga_i,ram_adr_i}),
+    .s1_sel_o (ram_sel_i),
+    .s1_we_o  (ram_we_i),
+    .s1_cyc_o (ram_cyc_i),
+    .s1_stb_o (ram_stb_i),
+    .s1_ack_i (ram_ack_o),
+
+    // Slave 2 interface - Interrupt Control
+    .s2_dat_i (16'h0000),
+    .s2_dat_o (),
+    .s2_adr_o (),
+    .s2_sel_o (),
+    .s2_we_o  (),
+    .s2_cyc_o (s2_cyc_i),
+    .s2_stb_o (s2_stb_i),
+    .s2_ack_i (s2_cyc_i && s2_stb_i),
+
+    // Slave 3 interface - Timer Control 0
+    .s3_dat_i (16'h0000),
+    .s3_dat_o (),
+    .s3_adr_o (),
+    .s3_sel_o (),
+    .s3_we_o  (),
+    .s3_cyc_o (s3_cyc_i),
+    .s3_stb_o (s3_stb_i),
+    .s3_ack_i (s3_cyc_i && s3_stb_i),
+
+    // Slave 4 interface - Timer Control 1
+    .s4_dat_i (16'h0000),
+    .s4_dat_o (),
+    .s4_adr_o (),
+    .s4_sel_o (),
+    .s4_we_o  (),
+    .s4_cyc_o (s4_cyc_i),
+    .s4_stb_o (s4_stb_i),
+    .s4_ack_i (s4_cyc_i && s4_stb_i),
+
+    // Slave 5 interface - Timer Control 2
+    .s5_dat_i (16'h0000),
+    .s5_dat_o (),
+    .s5_adr_o (),
+    .s5_sel_o (),
+    .s5_we_o  (),
+    .s5_cyc_o (s5_cyc_i),
+    .s5_stb_o (s5_stb_i),
+    .s5_ack_i (s5_cyc_i && s5_stb_i),
+
+    // Slave 6 interface - Chip Select Registers
+    .s6_dat_i (16'h0000),
+    .s6_dat_o (),
+    .s6_adr_o (),
+    .s6_sel_o (),
+    .s6_we_o  (),
+    .s6_cyc_o (s6_cyc_i),
+    .s6_stb_o (s6_stb_i),
+    .s6_ack_i (s6_cyc_i && s6_stb_i),
+
+    // Slave 7 interface - DMA Channel 0
+    .s7_dat_i (16'h0000),
+    .s7_dat_o (),
+    .s7_adr_o (),
+    .s7_sel_o (),
+    .s7_we_o  (),
+    .s7_cyc_o (s7_cyc_i),
+    .s7_stb_o (s7_stb_i),
+    .s7_ack_i (s7_cyc_i && s7_stb_i),
+
+    // Slave 8 interface - Tube
+    .s8_dat_i (tube_dat_o),
+    .s8_dat_o (tube_dat_i),
+    .s8_adr_o ({tube_tga_i,tube_adr_i}),
+    .s8_sel_o (tube_sel_i),
+    .s8_we_o  (tube_we_i),
+    .s8_cyc_o (tube_cyc_i),
+    .s8_stb_o (tube_stb_i),
+    .s8_ack_i (tube_ack_o),
+
+    // Slave 9 interface - not connected
+    .s9_dat_i (16'h0000),
+    .s9_dat_o (),
+    .s9_adr_o (),
+    .s9_sel_o (),
+    .s9_we_o  (),
+    .s9_cyc_o (s9_cyc_i),
+    .s9_stb_o (s9_stb_i),
+    .s9_ack_i (s9_cyc_i && s9_stb_i),
+
+    // Slave A interface - not connected
+    .sA_dat_i (16'h0000),
+    .sA_dat_o (),
+    .sA_adr_o (),
+    .sA_sel_o (),
+    .sA_we_o  (),
+    .sA_cyc_o (sa_cyc_i),
+    .sA_stb_o (sa_stb_i),
+    .sA_ack_i (sa_cyc_i && sa_stb_i),
+
+    // Slave B interface - default
+    .sB_dat_i (16'h0000),
+    .sB_dat_o (),
+    .sB_adr_o (),
+    .sB_sel_o (),
+    .sB_we_o  (),
+    .sB_cyc_o (def_cyc_i),
+    .sB_stb_o (def_stb_i),
+    .sB_ack_i (def_cyc_i & def_stb_i)
+  );
+
+  always @(posedge clk) begin
+     if (rst) begin
+         tubeint0 <= 0;
+         tubeint1 <= 0;
+         tubeint2 <= 0;
+         tubeint3 <= 0;
+         tubenmi0 <= 0;
+         tubenmi1 <= 0;
+         tubenmi2 <= 0;
+         tubenmi3 <= 0;
+     end else begin
+         tubeint0 <= ~p_irq_b;
+         tubeint1 <= tubeint0;
+         tubeint2 <= tubeint1;
+         if (inta) begin
+             tubeint3 <= 0;
+         end else if (tubeint1 & ~tubeint2) begin
+             tubeint3 <= 1;
+         end
+         tubenmi0 <= ~p_nmi_b;
+         tubenmi1 <= tubenmi0;
+         tubenmi2 <= tubenmi1;
+         if (nmia) begin
+             tubenmi3 <= 0;
+         end else if (tubenmi1 & ~tubenmi2) begin
+             tubenmi3 <= 1;
+         end
+     end     
+  end
+
+
+
+  assign nmi = tubenmi3;
+  assign intr = tubeint3;
+  
+//  assign intv[0] = tubeint3;
+//  assign intv[7:1] = 0;
+  
+  assign dat_i = nmia ? 16'h0002 :
+                (inta ? 16'h000c :
+                        sw_dat_o);
+                        
+  // 06bb:0a55                      
+  assign trigger = (pc[15:0] == 16'h7605) ? 1 : 0; 
+
+  // default to hi-impedence, to avoid conflicts with
+  // a Raspberry Pi connected to the test connector
+  assign test = 8'bZ;
+  
+  assign dack_b = 1;
+  
+  //assign ram_addr = {1'b0, ram_addr_int[18] ^ ram_addr_int[17], ram_addr_int[16:0]};
+  assign ram_addr = ram_addr_int;
+  
+  assign h_irq_b = 1;
+  
+
+
+
+endmodule
+"
+"`timescale 1ns / 1ns
+
+`define p1edge negedge
+`define p2edge posedge
+
+module hp_flag_m
+\t\t  
+`include ""gen_flag_v3.v""
+"
+"// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+// This file is part of the M32632 project\r
+// http://opencores.org/project,m32632\r
+//\r
+// Filename: STEUER_MISC.v\r
+// Version:  1.1 bug fix\r
+// History:  1.0 first release of 30 Mai 2015\r
+// Date:     21 January 2016\r
+//\r
+// Copyright (C) 2016 Udo Moeller\r
+// \r
+// This source file may be used and distributed without \r
+// restriction provided that this copyright statement is not \r
+// removed from the file and that any derivative work contains \r
+// the original copyright notice and the associated disclaimer.\r
+// \r
+// This source file is free software; you can redistribute it \r
+// and/or modify it under the terms of the GNU Lesser General \r
+// Public License as published by the Free Software Foundation;\r
+// either version 2.1 of the License, or (at your option) any \r
+// later version. \r
+// \r
+// This source is distributed in the hope that it will be \r
+// useful, but WITHOUT ANY WARRANTY; without even the implied \r
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR \r
+// PURPOSE. See the GNU Lesser General Public License for more \r
+// details. \r
+// \r
+// You should have received a copy of the GNU Lesser General \r
+// Public License along with this source; if not, download it \r
+// from http://www.opencores.org/lgpl.shtml \r
+// \r
+// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\tModules contained in this file:\r
+//\t1. OPDEC_REG \tCentral Instruction Register\r
+//\t2. PROG_COUNTER\tProgram Counters\r
+//\t3. REG_LIST\t\tRegister List Evaluation\r
+//\t4. ILL_UNDEF\tIllegal and Undefined Opcodes Detection\r
+//\t5. GRUPPE_2\t\tDecoder and State Machine for GRUPPE_2 Opcodes\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t1. OPDEC_REG \tCentral Instruction Register\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module OPDEC_REG ( BCLK, BRESET, NEW, ACC_STAT, PROT_ERROR, ALSB, USED, IC_DIN, IC_INIT, DC_INIT, Y_INIT, RESTART, STOP_IC,\r
+\t\t\t\t   OPREG, ANZ_VAL, IC_READ, NEW_PC, NEXT_ADR, DATA_HOLD, ABORT, IC_TEX, INIT_DONE);\r
+\r
+\tinput\t\t\tBCLK,BRESET;\r
+\tinput\t\t\tNEW;\t\t// a program jump took place\r
+\tinput\t [3:0]\tACC_STAT;\t// ICACHE signals data is available or Abort\r
+\tinput\t\t\tPROT_ERROR;\t// comes direct from ICACHE\r
+\tinput\t [1:0]\tALSB;\t\t// lower addressbits of access address to ICACHE\r
+\tinput\t [2:0]\tUSED;\t\t// Message from DECODER how many bytes were used\r
+\tinput\t[31:0]\tIC_DIN;\t\t// ICACHE Data\r
+\tinput\t\t\tIC_INIT,DC_INIT,Y_INIT;\t// Initialising or new setting is running\r
+\tinput\t\t\tRESTART;\t// ""Break"" of Instruction Pipeline - set up new i.e. after load of PSR\r
+\tinput\t\t\tSTOP_IC;\t// For LMR and CINV\r
+\t\r
+\toutput\t[55:0]\tOPREG;\t\t// this is the Central Opcode Decode Register, length = 7 bytes\r
+\toutput\t [2:0]\tANZ_VAL;\r
+\toutput\t\t\tIC_READ;\r
+\toutput\t\t\tNEW_PC;\r
+\toutput\t\t\tNEXT_ADR;\r
+\toutput\t\t\tDATA_HOLD;\r
+\toutput\t\t\tABORT;\r
+\toutput\t [2:0]\tIC_TEX;\r
+\toutput\t\t\tINIT_DONE;\r
+\t\r
+\treg\t\t[55:0]\tOPREG;\r
+\treg\t\t [2:0]\tANZ_VAL;\r
+\treg\t\t\t\tIC_READ;\r
+\treg\t\t\t\tABORT;\r
+\treg\t\t\t\tabort_flag;\r
+\treg\t\t [2:0]\tIC_TEX;\r
+\treg\t\t[55:0]\tdata_to_ri;\r
+\treg\t\t\t\told_init;\r
+\treg\t\t\t\tpre_new;\r
+\treg\t\t\t\tnew_reg;\r
+\treg\t\t\t\tnseq_flag;\r
+\treg\t\t\t\tstop_init;\r
+\t\r
+\twire\t [2:0]\tnew_anz;\r
+\twire\t\t\tnew_restart;\r
+\twire\t\t\tacc_err,acc_ok,acc_ende;\r
+\t\r
+\t// ++++++++++++++++++++  Evaluation of ACC_STAT from Instructioncache  ++++++++++++++++++++++++++++\r
+\t\r
+\t// ACC_STAT[3:0] : PROT_ERROR , ABO_LEVEL1 , ABORT , ACC_OK\r
+\t\r
+\tassign acc_err = ACC_STAT[3] | ACC_STAT[1] | PROT_ERROR;\r
+\tassign acc_ok  = ACC_STAT[0];\r
+\t\r
+\talways @(posedge BCLK or negedge BRESET)\t// is kept until DECODER really needs the data !\r
+\t\tif (!BRESET) ABORT <= 1\'b0;\r
+\t\t  else ABORT <=  (acc_err & ~(new_restart | pre_new)) | (ABORT & ~NEW_PC);\r
+\t\t  \r
+\talways @(posedge BCLK) if (acc_err) IC_TEX <= (ACC_STAT[3] | PROT_ERROR) ? {nseq_flag,2\'b11} : {nseq_flag,~ACC_STAT[2],ACC_STAT[2]};\r
+\t\r
+\talways @(posedge BCLK) nseq_flag <= NEW_PC | (nseq_flag & ~acc_ok);\t// for MMU Status Register\r
+\r
+\talways @(posedge BCLK) abort_flag <= acc_err;\r
+\tassign acc_ende = ~IC_READ | acc_ok | abort_flag;\t// abort_flag one cycle later is ok ! If no ICache access always end\r
+\t\r
+\tassign new_restart = NEW | RESTART;\t// They are pulses\r
+\t\r
+\t// Branch work out : NEW/RESTART notice if access still not ended\r
+\talways @(posedge BCLK) pre_new <= (new_restart & ~acc_ende) | (pre_new & ~acc_ende & BRESET);\r
+\t\r
+\tassign NEW_PC = (new_restart | pre_new) & acc_ende;\t// At the end of access geenerate new address !\r
+\t\r
+\t// There are 2 ""NEW/RESTART"" : ""new_restart"" combinatorical out of DECODER, ""pre_new"" out of Register\r
+\talways @(posedge BCLK) new_reg <= new_restart | pre_new | (new_reg & ~acc_ende & BRESET);\r
+\t\r
+\talways @(USED or OPREG)\t// Data first shift to the right\r
+\t\tcase (USED)\r
+\t\t  3\'b000 : data_to_ri = OPREG;\r
+\t\t  3\'b001 : data_to_ri =               { 8\'hxx, OPREG[55:8]};\r
+\t\t  3\'b010 : data_to_ri =             {16\'hxxxx,OPREG[55:16]};\r
+\t\t  3\'b011 : data_to_ri =          {24\'hxx_xxxx,OPREG[55:24]};\r
+\t\t  3\'b100 : data_to_ri =        {32\'hxxxx_xxxx,OPREG[55:32]};\r
+\t\t  3\'b101 : data_to_ri =     {40\'hxx_xxxx_xxxx,OPREG[55:40]};\r
+\t\t  3\'b110 : data_to_ri =   {48\'hxxxx_xxxx_xxxx,OPREG[55:48]};\r
+\t\t  3\'b111 : data_to_ri = 56\'hxx_xxxx_xxxx_xxxx;\r
+\t\tendcase\r
+\r
+\tassign new_anz = ANZ_VAL - USED;\r
+\r
+\talways @(posedge BCLK)\r
+\t\tcasex ({new_reg,acc_ok,ALSB,new_anz})\t\r
+\t\t  7\'b1_100_xxx : OPREG <=        {24\'hxx_xxxx,IC_DIN};\r
+\t\t  7\'b1_101_xxx : OPREG <=      {32\'hxxxx_xxxx,IC_DIN[31:8]};\r
+\t\t  7\'b1_110_xxx : OPREG <=   {40\'hxx_xxxx_xxxx,IC_DIN[31:16]};\r
+\t\t  7\'b1_111_xxx : OPREG <= {48\'hxxxx_xxxx_xxxx,IC_DIN[31:24]};\r
+\t\t  7\'b0_0xx_xxx : OPREG <= data_to_ri;\r
+\t\t  7\'b0_1xx_000 : OPREG <= {24\'hxx_xxxx,IC_DIN};\r
+\t\t  7\'b0_1xx_001 : OPREG <= {   16\'hxxxx,IC_DIN, data_to_ri[7:0]};\r
+\t\t  7\'b0_1xx_010 : OPREG <= {      8\'hxx,IC_DIN,data_to_ri[15:0]};\r
+\t\t  7\'b0_1xx_011 : OPREG <= {            IC_DIN,data_to_ri[23:0]};\r
+\t\t  7\'b0_1xx_1xx : OPREG <= data_to_ri;\r
+\t\tendcase\r
+\t\t\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) ANZ_VAL <= 3\'b000;\r
+\t\t  else\r
+\t\t\tcasex ({new_restart,new_reg,acc_ok,new_anz[2]})\r
+\t\t\t  4\'b1x_x_x : ANZ_VAL <= 3\'b000;\t// hard setting to 0\r
+\t\t\t  4\'b01_0_x : ANZ_VAL <= 3\'b000;\r
+\t\t\t  4\'b01_1_x : ANZ_VAL <= pre_new ? 3\'b000 : 3\'b100 - {1\'b0,ALSB};\r
+\t\t\t  4\'b00_0_x : ANZ_VAL <= new_anz;\r
+\t\t\t  4\'b00_1_0 : ANZ_VAL <= new_anz + 3\'b100;\r
+\t\t\t  4\'b00_1_1 : ANZ_VAL <= new_anz;\r
+\t\t\tendcase\r
+\t\t\r
+\tassign NEXT_ADR = new_reg ? (acc_ok & ~pre_new) : (acc_ok & ~new_anz[2]);\t// switches MUX at PC resp. ICACHE\r
+\r
+\t// Instruction CACHE Control : READ is coming after all INITs are done\r
+\t\r
+\talways @(posedge BCLK) old_init <= IC_INIT | DC_INIT | Y_INIT;\r
+\t\r
+\tassign INIT_DONE = old_init & ~IC_INIT & ~DC_INIT;\r
+\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) stop_init <= 1\'b0;\r
+\t\t\telse stop_init <= stop_init | IC_READ;\r
+\t\t\t\r
+\t// The INIT_DONE should come after Reset. But it comes too at LMR PTB therefore extra enable after Reset !\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) IC_READ <= 1\'b0;\r
+\t\t\telse IC_READ <= (IC_READ & ~acc_err & ~(STOP_IC & acc_ok)) | NEW_PC | (INIT_DONE & ~stop_init);\r
+\t\r
+\t// The Opcode-Register can not store the data : keep them in ICACHE at IO-access\r
+\tassign DATA_HOLD = ~new_restart & ~new_reg & acc_ok & new_anz[2];\r
+\t\r
+endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t2. PROG_COUNTER\tProgram Counters\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module PROG_COUNTER ( BCLK, BRESET, NEW, LOAD_PC, NEW_PC, NEXT_ADR, NEXT_PCA, DISP, PC_NEW, USED, USER, SAVE_PC, FPU_TRAP,\r
+\t\t\t\t\t  ADIVAR, PC_ARCHI, PC_ICACHE, PC_SAVE, ALSB, IC_USER);\r
+\r
+\tinput\t\t\tBCLK,BRESET;\r
+\tinput\t\t\tNEW;\r
+\tinput\t\t\tLOAD_PC;\r
+\tinput\t\t\tNEW_PC;\r
+\tinput\t\t\tNEXT_ADR;\r
+\tinput\t\t\tNEXT_PCA;\r
+\tinput\t[31:0]\tDISP;\r
+\tinput\t[31:0]\tPC_NEW;\r
+\tinput\t [2:0]\tUSED;\r
+\tinput\t\t\tUSER;\r
+\tinput\t\t\tSAVE_PC;\r
+\tinput\t\t\tFPU_TRAP;\r
+\tinput\t\t\tADIVAR;\r
+\t\r
+\toutput\t[31:0]\tPC_ARCHI;\t// goes to Datapath\r
+\toutput\t[31:0]\tPC_ICACHE;\r
+\toutput\t[31:0]\tPC_SAVE;\t// is the return address\r
+\toutput\t [1:0]\tALSB;\r
+\toutput\t\t\tIC_USER;\r
+\t\r
+\treg\t\t[31:0]\tPC_ARCHI;\r
+\treg\t\t[31:0]\tpc_adduse;\r
+\treg\t\t[31:0]\tpc_ic_reg;\r
+\treg\t\t[31:0]\tfpu_trap_pc;\r
+\treg\t\t\t\tIC_USER;\r
+\t\r
+\twire\t[31:0]\tbranch,pc_jump,next_pc,pc_icache_i;\r
+\t\r
+\tassign PC_SAVE = pc_adduse + {29\'h0,USED};\r
+\tassign branch  = PC_ARCHI + DISP;\r
+\t\r
+\tassign pc_jump = LOAD_PC ? PC_NEW : branch;\r
+\t\r
+\tassign next_pc = NEW ? pc_jump : PC_SAVE;\t// Only at NEW is the DISP correct !\r
+\t\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) pc_adduse <= 32\'h0;\r
+\t\t  else\r
+\t\t\tpc_adduse <= next_pc;\r
+\t\t\t\r
+\t// The Architectur - PC : Address mode ""Programm Memory""-relativ\r
+\t// no BRESET because NEXT_PCA is immediately valid\r
+\talways @(posedge BCLK)\r
+\t\tif (FPU_TRAP) PC_ARCHI <= fpu_trap_pc;\t// go back !\r
+\t\t  else\r
+\t\t\tif (NEXT_PCA) PC_ARCHI <= pc_adduse;\r
+\t\r
+\talways @(posedge BCLK) if (SAVE_PC) fpu_trap_pc <= PC_ARCHI;\t// Special storage for PC for FPU Trap\r
+\t\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) pc_ic_reg <= 32\'h0;\r
+\t\t  else\r
+\t\t\tpc_ic_reg <= pc_icache_i;\r
+\t\t\r
+\t// NEW is only one cycle long - but in pc_adduse is the PC stored when ACC_OK is not there and therefore NEW_PC\r
+\t// is used to initiate a new access in ICACHE\r
+\tassign pc_icache_i = NEW_PC ? (NEW ? pc_jump : pc_adduse) : (NEXT_ADR ? ({pc_ic_reg[31:2],2\'b00} + 32\'h0000_0004) : pc_ic_reg);\r
+\t\r
+\t// This MUX is extra for LMR IVAR,... and CINV build in\r
+\tassign PC_ICACHE = {(ADIVAR ? PC_NEW[31:4] : pc_icache_i[31:4]),pc_icache_i[3:0]};\r
+\t\r
+\tassign ALSB = pc_ic_reg[1:0];\t// for OPDEC_REG\r
+\t\r
+\t// The IC_USER flag is allowed to switch synchronously with one cycle delay to PC_ICACHE\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) IC_USER <= 1\'b0;\r
+\t\t  else\r
+\t\t\tif (NEW_PC) IC_USER <= USER;\r
+\t\r
+endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t3. REG_LIST\t\tRegister List Evaluation\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module REG_LIST ( DIN, IPOS, INIT, OPOS, VALID);\r
+\r
+\t// Detects set bits in register list for SAVE/RESTORE & ENTER/EXIT\r
+\r
+\tinput\t [7:0]\tDIN;\r
+\tinput\t [2:0]\tIPOS;\r
+\tinput\t\t\tINIT;\r
+\toutput\t [2:0]\tOPOS;\r
+\toutput\t\t\tVALID;\r
+\t\r
+\treg\t\t [7:1]\tfilter;\r
+\twire\t [7:0]\tmdat_0;\r
+\twire\t [3:0]\tmdat_1;\r
+\twire\t [1:0]\tmdat_2;\r
+\r
+\talways @(IPOS or DIN)\r
+\t\tcase (IPOS)\r
+\t\t  3\'d0 : filter =  DIN[7:1];\r
+\t\t  3\'d1 : filter = {DIN[7:2],1\'b0};\r
+\t\t  3\'d2 : filter = {DIN[7:3],2\'b0};\r
+\t\t  3\'d3 : filter = {DIN[7:4],3\'b0};\r
+\t\t  3\'d4 : filter = {DIN[7:5],4\'b0};\r
+\t\t  3\'d5 : filter = {DIN[7:6],5\'b0};\r
+\t\t  3\'d6 : filter = {DIN[7]  ,6\'b0};\r
+\t\t  3\'d7 : filter =           7\'b0;\r
+\t\tendcase\r
+\t\t\r
+\tassign mdat_0  = INIT ? DIN : {filter,1\'b0};\r
+\tassign OPOS[2] = (mdat_0[3:0] == 4\'h0);\r
+\tassign mdat_1  = OPOS[2] ? mdat_0[7:4] : mdat_0[3:0];\r
+\tassign OPOS[1] = (mdat_1[1:0] == 2\'b00);\r
+\tassign mdat_2  = OPOS[1] ? mdat_1[3:2] : mdat_1[1:0];\r
+\tassign OPOS[0] = ~mdat_2[0];\r
+\tassign VALID   = (mdat_2 != 2\'b00);\r
+\t\r
+endmodule\r
+\t\t  \r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t4. ILL_UNDEF\tIllegal and Undefined Opcodes Detection\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module ILL_UNDEF (OPREG, ANZ_VAL, USER, CFG, ILL, UNDEF );\r
+\r
+\tinput\t[23:0]\tOPREG;\r
+\tinput\t [2:0]\tANZ_VAL;\r
+\tinput\t [3:1]\tCFG;\t\t// 3=CUSTOM,2=MMU,1=FPU\r
+\tinput\t\t\tUSER;\r
+\t\r
+\toutput\treg\t\tILL;\r
+\toutput\t\t\tUNDEF;\r
+\r
+\treg\t\t\t\tundef_opc;\r
+\treg\t\t\t\tundef_am;\r
+\treg\t\t\t\tundef_im;\r
+\t\r
+\twire\t [2:0]\tvalid;\r
+\twire\t\t\tgen12,gen22,gen13,gen23;\r
+\twire\t\t\tigen12,igen22,igen13,igen23;\r
+\twire\t\t\tlsbes;\r
+\t\r
+\tparameter udef_amode = 5\'b10011;\t// Undefined Addressing Mode\r
+\tparameter imode\t\t = 5\'b10100;\t// Immediate Addressing Mode \r
+\t\r
+\t// [2]= minimum 3, [1]= minimum 2, [0]=minimum 1\r
+\tassign valid = {(ANZ_VAL[2] | (ANZ_VAL[1:0] == 2\'b11)),(ANZ_VAL[2:1] != 2\'b00),(ANZ_VAL != 3\'b000)};\r
+\tassign lsbes = (OPREG[1:0] == 2\'b10);\t// Tag of all 3 Byte opcodes\r
+\t\r
+\t// +++++++++++++++++++++++++  Detect illegale opcodes  +++++++++++++++++++\r
+\t\r
+\talways @(OPREG or lsbes or valid or USER)\r
+\t\tcasex ({valid[2:1],OPREG[13:2],lsbes})\r
+\t\t  15\'bx1_xx_x000_1x10_11_0 : ILL = USER;\t// SPRi/LPRi DCR\r
+\t\t  15\'bx1_xx_x001_xx10_11_0 : ILL = USER;\t// SPRi/LPRi BPC/DSR\r
+\t\t  15\'bx1_xx_xx10_xx10_11_0 : ILL = USER;\t// SPRi/LPRi CAR/CFG/PSR\r
+\t\t  15\'bx1_xx_x101_1x10_11_0 : ILL = USER;\t// SPRi/LPRi USP\r
+\t\t  15\'bx1_xx_x111_0x10_11_0 : ILL = USER;\t// SPRi/LPRi INTBASE\r
+\t\t  15\'bx1_xx_x0x1_0111_11_x : ILL = USER & OPREG[0];\t// BICPSRW,BISPSRW\r
+\t\t  15\'bx1_00_10xx_0000_11_1 : ILL = USER;\t// SETCFG - Achtung : is coded as 2 Byte Opcode \r
+\t\t  15\'b1x_00_xxxx_0001_11_1 : ILL = USER;\t// LMR/SMR/RDVAL/WRVAL\r
+\t\t  15\'b1x_10_01xx_0001_11_1 : ILL = USER;\t// CINV\r
+\t\t  default\t\t\t\t   : ILL = 1\'b0;\r
+\t\tendcase\r
+\r
+\t// ++++++++++++++++++++++++ Detect Undefined opcodes  +++++++++++++++\r
+\t\r
+\talways @(OPREG or lsbes or valid or CFG)\r
+\t\tcasex ({valid,OPREG[13:2],lsbes})\r
+\t\t  16\'bx1x_xx_xxxx_1111_110 : undef_opc = 1\'b1;\t\t// Format 3 : xxx1\r
+\t\t  16\'bx1x_xx_x100_0111_110 : undef_opc = 1\'b1;\t\t// Format 3 : 1000\r
+\t\t  16\'b1xx_1x_xxxx_0000_111 : undef_opc = 1\'b1;\t\t// Format 5 : 1xxx\r
+\t\t  16\'b1xx_01_xxxx_0000_111 : undef_opc = 1\'b1;\t\t// Format 5 : 01xx\r
+\t\t  16\'b1xx_01_00xx_0100_111 : undef_opc = 1\'b1;\t\t// Format 6 : 0100\r
+\t\t  16\'b1xx_10_10xx_x100_111 : undef_opc = 1\'b1;\t\t// Format 6/7 : 1010\r
+\t\t  16\'b1xx_xx_xxxx_x011_111 : undef_opc = ~CFG[1];\t// Format 9/11 : FPU Befehle wie MOVif etc. und ADDf etc.\r
+\t\t  16\'b1xx_xx_xxxx_1111_111 : undef_opc = ~CFG[1];\t// Format 12 : FPU Befehle wie POLYf etc.\r
+\t\t  16\'b1xx_x1_xxxx_0001_111 : undef_opc = 1\'b1;\t\t// Format 14 : x1xx \r
+\t\t  16\'b1xx_10_00xx_0001_111 : undef_opc = 1\'b1;\t\t// Format 14 : 1000\r
+\t\t  16\'b1xx_10_1xxx_0001_111 : undef_opc = 1\'b1;\t\t// Format 14 : 101x\r
+\t\t  16\'b1xx_00_1xxx_0001_111 : undef_opc = ~CFG[2] | ~OPREG[18];\t// Format 14 : LMR/SMR\r
+\t\t  16\'b1xx_xx_xxxx_x011_011 : undef_opc = ~CFG[3];\t// Format 15.1/15.5 : CUSTOM CCV0, CCAL0 etc.\r
+\t\t  16\'b1xx_xx_xxxx_0001_011 : undef_opc = 1\'b1;\t\t// Format 15.0 - not yet in, requires HW change\r
+\t\t  16\'b1xx_xx_xxxx_x1x1_011 : undef_opc = 1\'b1;\t\t// Format 15 : rest\r
+\t\t  16\'b1xx_xx_xxxx_1001_011 : undef_opc = 1\'b1;\t\t// Format 15.4\r
+\t\t// completely undefined :\r
+\t\t  16\'bxx1_xx_xxxx_0111_111 : undef_opc = 1\'b1;\t\t// Format 10\r
+\t\t  16\'bxx1_xx_xxxx_100x_111 : undef_opc = 1\'b1;\t\t// Format 13/18\r
+\t\t  16\'bxx1_xx_xxxx_x101_111 : undef_opc = 1\'b1;\t\t// Format 16/17\r
+\t\t  16\'bxx1_xx_xxxx_xxx0_011 : undef_opc = 1\'b1;\t\t// Format 19\r
+\t\t  default\t\t\t\t   : undef_opc = 1\'b0;\r
+\t\tendcase\r
+\r
+\t// 2. Undefined Addressing mode 5\'b10011\r
+\t\r
+\tassign gen12 = (OPREG[15:11] == udef_amode);\r
+\tassign gen22 = (OPREG[10:6]  == udef_amode);\r
+\tassign gen13 = (OPREG[23:19] == udef_amode);\r
+\tassign gen23 = (OPREG[18:14] == udef_amode);\r
+\t\r
+\talways @(OPREG or valid or gen12 or gen22 or gen13 or gen23)\r
+\t\tif (valid[2] && (OPREG[7:5] != 3\'b000) && (OPREG[3:0] == 4\'b1110)) undef_am = gen13 | gen23;\t// nearly all 3 Byte opcodes\r
+\t\t  else\r
+\t\t    undef_am = valid[1] & gen12 & (OPREG[1:0] != 2\'b10) & ((OPREG[3:2] != 2\'b11) & gen22);\t// all 2 Byte opcodes\r
+\t\t\r
+\t// 3. When is Immediate not allowed ?\r
+\t\r
+\tassign igen12 = (OPREG[15:11] == imode);\r
+\tassign igen22 = (OPREG[10:6]  == imode);\r
+\tassign igen13 = (OPREG[23:19] == imode);\r
+\tassign igen23 = (OPREG[18:14] == imode);\r
+\t\r
+\talways @(*)\r
+\t\tcasex ({valid[2:1],OPREG[13:2],lsbes})\r
+\t\t  15\'bx1_xxxxxx_x0xx11_0 : undef_im =  igen12 & (OPREG[5:4] != 2\'b01);\t// Format 2 : ADDQD,SPR,Scond\r
+\t\t  15\'bx1_xxxxxx_x10111_0 : undef_im =  igen12;\t\t// Format 2 : ACB,MOVQ\r
+\t\t  15\'bx1_xxxxx0_011111_0 : undef_im =  igen12;\t\t// Format 3 : CXPD,JUMP,JSR\r
+\t\t  15\'bx1_xxxxxx_xxxxx0_0 : undef_im =  igen22;\t\t// Format 4\r
+\t\t  15\'bx1_xxxxxx_xxxx01_0 : undef_im = (igen12 & (OPREG[5:4] == 2\'b10))\t// Format 4 : SRC1 - not ADDR\r
+\t\t\t\t\t\t\t\t\t\t\t |(igen22 & (OPREG[5:4] != 2\'b00)); // Format 4 : SRC2 - CMP\r
+\t\t  15\'b1x_xxxxxx_x10011_1 : undef_im =  igen23;\t\t// Format 6+7\r
+\t\t  15\'b1x_xxx0xx_0x1011_1 : undef_im =  igen13 | igen23;\t// Format 8 EXT,CVTP\r
+\t\t  15\'b1x_xxx0xx_101011_1 : undef_im =  igen23;\t\t// Format 8 : INS\r
+\t\t  15\'b1x_xxx0xx_111011_1 : undef_im =  igen13;\t\t// Format 8 : CHECK\r
+\t\t  15\'b1x_xxx1xx_101011_1 : undef_im =  igen13 | igen23;\t// Format 8 MOVUS,MOVSU\r
+\t\t  15\'b1x_xxx1xx_011011_1 : undef_im =  igen23;\t\t// Format 8 : FFS\r
+\t\t  15\'b1x_xxxxxx_001111_1 : undef_im =  igen23;\t\t// Format 9\r
+\t\t  15\'b1x_xxxxxx_101111_1 : undef_im =  igen23 & (OPREG[13:10] != 4\'h2);\t// Format 10 without CMPf\r
+\t\t  15\'b1x_010xxx_111111_1 : undef_im =  igen23;\t\t// Format 12 SCALB+LOGB\r
+\t\t  15\'b1x_000xxx_000111_1 : undef_im =  igen13;\t\t// Format 14 RDVAL+WRVAL\r
+\t\t  15\'b1x_0011xx_000111_1 : undef_im =  igen13;\t\t// Format 14 SMR\r
+\t\t  default\t\t\t\t : undef_im = 1\'b0;\r
+\t\tendcase\r
+\t\t\r
+\t// Final Message :\r
+\t\r
+\tassign UNDEF = undef_opc | undef_am | undef_im;\r
+\t\r
+endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t5. GRUPPE_2\t\tDecoder and State Machine for GRUPPE_2 Opcodes\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module GRUPPE_2 ( BCLK, PHASE_0, OPREG, PHASE, SRC_1, SRC_2, REGA1, REGA2, IRRW1, IRRW2, ADRD1, ADRD2, EXR12, EXR22,\r
+\t\t\t\t  PHRD1, PHRD2, NXRD1, NXRW2, ACCA, OPERA,\r
+\t\t\t\t  STATE_0, STATE_GROUP_50, STATE_GROUP_60 );\r
+\r
+\r
+\tinput\t\t\tBCLK,PHASE_0;\r
+\tinput\t[18:0]\tOPREG;\r
+\tinput\t [3:0]\tPHASE;\t// nur die 4 LSBs\r
+\t// Source 1 & 2 Inputs\r
+\tinput\t [6:0]\tSRC_1,SRC_2,REGA1,REGA2,IRRW1,IRRW2;\r
+\tinput\t[18:0]\tADRD1,ADRD2,EXR12,EXR22;\r
+\tinput\t [3:0]\tPHRD1,PHRD2;\r
+\tinput\t [3:0]\tNXRD1,NXRW2;\r
+\tinput\t [3:0]\tACCA;\t// ACCA = Access type :\t0x Register\r
+\t\t\t\t\t\t\t//\t[3:2] or [1:0]\t\t10 Memory\r
+\t\t\t\t\t\t\t//\t\t\t\t\t\t11 Memory + Index\r
+\tinput\t[10:0]\tOPERA;\r
+\r
+\toutput\t[66:0]\tSTATE_0;\r
+\toutput\t[66:0]\tSTATE_GROUP_50,STATE_GROUP_60;\r
+\t\r
+\treg\t\t[66:0]\tSTATE_GROUP_50,STATE_GROUP_60;\r
+\treg\t\t[66:0]\tSTATE_0,state_50,state_53,state_54,state_55,state_58,state_59,state_5A;\r
+\treg\t\t [4:0]\top_code,op_reg_reg;\r
+\treg\t\t [7:0]\tphsrc1,phsrc2;\r
+\treg\t\t [5:0]\tchkreg;\r
+\treg\t\t [1:0]\tbwdreg;\r
+\treg\t\t\t\ttbit_flag,size_dw;\r
+\treg\t\t\t\tinss_flag;\r
+\treg\t\t\t\text_tos;\r
+\t\r
+\twire\t[18:0]\texoffset,re_wr,rexwr;\r
+\twire\t[10:0]\top_kust,op_bwd;\r
+\twire\t [7:0]\tphchk;\r
+\twire\t [4:0]\top_reg;\r
+\twire\t [6:0]\tsrc_1l,src_2l;\r
+\twire\t [5:0]\tdest_2;\r
+\twire\t [3:0]\tget8b_s,get8b_d;\r
+\twire\t [6:0]\trd_reg;\r
+\twire\t[10:0]\top_zext;\r
+\twire\t [3:0]\timdi;\r
+\t\r
+\tparameter dont_care\t= 67\'hx_xxxx_xxxx_xxxx_xxxx;\r
+\t// Address-Field : Size:2 RD WR LDEA FULLACC INDEX:4 SPUPD disp_val:4 POST CLRMSW SRC2SEL:2\r
+\tparameter addr_nop\t= 19\'h0;\t// alle Parameter auf 0\r
+\tparameter disp2ea\t= 19\'bxx_0010_0000_0_0000_0010;\t// pass DISP\r
+\tparameter case_op\t= 19\'bxx_0010_1000_0_0000_0001;\t// SRC1 add to PC_ARCHI\r
+\tparameter read_byb\t= 19\'b00_1011_11xx_0_0000_0011;\t// read of SRC2 for Bit opcodes\r
+\tparameter exr11\t\t= {2\'b10  ,4\'b1011,4\'h0 ,9\'h080};\t// 2. access External with Mem.-Pointer + 4* Disp\r
+\tparameter adrcvtp\t= 19\'bxx_0010_0111_0_0000_0000;\t// for CVTP\r
+\tparameter addone\t= 19\'bxx_0010_0100_0_0000_0000;\t// for INDEX : SRC1 + SRC2 , simple Add without Flags\r
+\tparameter addind\t= 19\'bxx_0010_0100_0_0000_0011;\t// for INDEX : SRC1 + EA\r
+\tparameter src_x\t\t= 7\'hxx;\r
+\tparameter dest_x\t= 6\'hxx;\r
+\tparameter imme\t\t= {1\'b1,6\'hxx};\r
+\tparameter F0\t\t= 7\'h20;\r
+\tparameter F0_h\t\t= 7\'h21;\r
+\tparameter w_F0\t\t= 6\'h20;\r
+\tparameter w_F0_h\t= 6\'h21;\r
+\tparameter temp_l\t= 6\'h3C;\r
+\tparameter temp_h\t= 6\'h3D;\t// Second last place for 8B TEMP Register\r
+\tparameter temp_1\t= 6\'h3E;\r
+\tparameter rtmpl\t\t= 7\'h3C;\r
+\tparameter rtmph\t\t= 7\'h3D;\r
+\tparameter rtmp1\t\t= 7\'h3E;\r
+\tparameter op_mov\t= {3\'bx1x,8\'h45};\r
+\tparameter op_adr\t= {3\'bx1x,8\'h49};\r
+\tparameter op_addl\t= {3\'b01x,8\'hB0};\r
+\tparameter op_addf\t= {3\'b11x,8\'hB0};\r
+\tparameter op_mull\t= {3\'b01x,8\'hBC};\r
+\tparameter op_mulf\t= {3\'b11x,8\'hBC};\r
+\tparameter op_truf\t= {3\'b101,8\'h9A};\t// TRUNCFW for SCALBF\r
+\tparameter op_trul\t= {3\'b001,8\'h9A};\t// TRUNCLW for SCALBL\r
+\tparameter op_stpr\t= {3\'b11x,8\'h54};\t// Special-Op for String opcodes\r
+\tparameter op_lsh\t= {3\'b011,8\'h65};\t// EXT : shift to right : DOUBLE !\r
+\tparameter op_msk\t= {3\'b011,8\'h80};\t// reuse of EXT Opcode at INS !\r
+\tparameter op_mul\t= {3\'b011,8\'h78};\t// INDEX\r
+\tparameter op_rwv\t= {3\'bx1x,8\'hE0};\t// RDVAL+WRVAL\r
+\r
+\talways @(OPREG)\t// whether the Opcode is valid is decided in DECODER !\r
+\t  casex (OPREG[13:0])\r
+//\t\t14\'bxx_xxxx_1111_1110 : op_code = {2\'b01,OPREG[11:10],OPREG[8]};\t// DOT/POLY/SCALB\r
+\t\t14\'b00_0xxx_0000_1110 : op_code = 5\'b1_0000;\t// MOVS/CMPS\r
+\t\t14\'b00_11xx_0000_1110 : op_code = 5\'b1_0000;\t// SKPS\r
+\t\t14\'b00_0xxx_1100_1110 : op_code = 5\'b1_0001;\t// MOVM/CMPM\r
+\t\t14\'bxx_xx10_0111_11xx : op_code = 5\'b1_0010;\t// JUMP/JSR\r
+\t\t14\'bxx_x111_0111_11xx : op_code = 5\'b1_0011;\t// CASE\r
+\t\t14\'bxx_xxxx_xx11_010x : op_code = 5\'b1_0100;\t// TBIT\r
+\t\t14\'bxx_xxxx_xx11_0111 : op_code = 5\'b1_0100;\t// TBIT\r
+\t\t14\'b0x_1xxx_0100_1110 : op_code = 5\'b1_0100;\t// CBIT/SBIT\r
+\t\t14\'b11_10xx_0100_1110 : op_code = 5\'b1_0100;\t// IBIT\r
+\t\t14\'b00_11xx_1100_1110 : op_code = 5\'b1_0101;\t// EXTS\r
+\t\t14\'b10_x1xx_1100_1110 : op_code = 5\'b1_0111;\t// DEI/MEI\r
+\t\t14\'bxx_x0xx_1110_1110 : op_code = 5\'b1_1000;\t// CHECK\r
+\t\t14\'bxx_x0xx_0010_1110 : op_code = 5\'b1_1010;\t// EXT\r
+\t\t14\'bxx_x0xx_1010_1110 : op_code = 5\'b1_1011;\t// INS\r
+\t\t14\'b00_10xx_1100_1110 : op_code = 5\'b1_1011;\t// INSS, the same like INS !\r
+\t\t14\'bxx_x0xx_0110_1110 : op_code = 5\'b1_1100;\t// CVTP\r
+\t\t14\'bxx_x1xx_0010_1110 : op_code = 5\'b1_1101;\t// INDEX\r
+\t\t14\'bxx_x000_0111_11xx : op_code = 5\'b1_1110;\t// CXPD\r
+\t\t14\'b00_0xxx_0001_1110 : op_code = 5\'b1_1111;\t// RDVAL+WRVAL\r
+\t\tdefault\t\t\t\t  : op_code = 5\'b00_xxx;\r
+\t  endcase\r
+\t\r
+\talways @(posedge BCLK) if (PHASE_0) op_reg_reg <= op_code;\r
+\tassign op_reg = PHASE_0 ? op_code : op_reg_reg;\r
+\t\r
+\talways @(PHRD1)\t// recode of States\r
+\t  casex (PHRD1)\r
+\t\t 4\'h5 : phsrc1 = 8\'h51;\r
+\t\t 4\'h6 : phsrc1 = 8\'h52;\r
+\t\t 4\'hB : phsrc1 = 8\'h53;\t// ok, is in default ...\r
+\t  default : phsrc1 = 8\'h53;\r
+\t  endcase\r
+\t  \r
+\tassign get8b_s = (PHRD1 == 4\'hB) ? 4\'hC : 4\'h0;\t// Special case 8B Immeadiate, is used in State 53\r
+\t\r
+\talways @(PHRD2)\t// recode of States\r
+\t  casex (PHRD2)\r
+\t\t 4\'h5 : phsrc2 = 8\'h56;\r
+\t\t 4\'h6 : phsrc2 = 8\'h57;\r
+\t\t 4\'hB : phsrc2 = 8\'h58;\t// ok, is in default ...\r
+\t  default : phsrc2 = 8\'h58;\r
+\t  endcase\r
+\t  \r
+\tassign get8b_d = (PHRD2 == 4\'hB) ? 4\'hC : 4\'h0;\t// Special case 8B Immeadiate, is used in State 58\r
+\t\r
+\tassign src_1l = {SRC_1[6:1],1\'b0};\r
+\tassign src_2l = {SRC_2[6:1],~SRC_2[0]};\t// needed only for DEI/MEI\r
+\tassign dest_2 =  SRC_2[5:0];\r
+\t\r
+\tassign phchk = {7\'b0101_010,size_dw};\t// Phase 54 or 55\r
+\t\r
+\tassign op_kust = {1\'bx,OPERA[9:8],8\'h7A};\t// Special-Opcode for MOVM/CMPM\r
+\tassign op_bwd  = {1\'bx,OPERA[9:8],8\'h45};\t// for CASE and Bit opcodes\r
+\t\r
+\tassign re_wr   = {EXR22[18:17],4\'b0101,4\'h0, 9\'h003};\t// REUSE Address : Write of rmw , top 2 Bits contain size\r
+\r
+\talways @(posedge BCLK) if (PHASE_0) ext_tos <= (OPREG[18:14] == 5\'h17);\t// if TOS\r
+\tassign rexwr   = {EXR22[18:17],4\'b0101,4\'h0, ext_tos, 8\'h03};\t// REUSE Addresse : Write von rmw , only for EXT and EXTS !\r
+\t\r
+\talways @(posedge BCLK) tbit_flag <= ~OPERA[1];\t// due to Timing ...\r
+\talways @(posedge BCLK) size_dw\t <=  OPERA[9];\r
+\r
+\talways @(posedge BCLK) if (PHASE_0) chkreg <= {3\'b000,OPREG[13:11]};\t// for CHECK\r
+\tassign rd_reg = (PHASE_0) ? {4\'b0,OPREG[13:11]} : {1\'b0,chkreg};\t// for read operation at EXT/INS\r
+\t\r
+\talways @(posedge BCLK) if (PHASE_0) bwdreg <= OPREG[9:8];\t\t// only for INS/INSS !\r
+\tassign op_zext = {1\'bx,(PHASE_0 ? OPREG[9:8] : bwdreg),8\'h76};\r
+\t\r
+\talways @(posedge BCLK) if (PHASE_0) inss_flag <= OPREG[6];\t// Difference INSS to INS\r
+\tassign imdi = inss_flag ? 4\'h8 : 4\'hE;\t// read Immediate or Displacement\r
+\tassign exoffset = inss_flag ? 19\'b10_1011_0000_0_0000_0011 \t// Read of SRC2 at INSS\r
+\t\t\t\t\t\t\t\t: 19\'b10_1011_1100_0_0000_0011;\t// Read of SRC1+Offset at EXT, SRC2+Offset at INS \r
+\t\r
+\talways @(*)\r
+\t  casex (op_reg) \r
+\t\t5\'b1_0000 :\t// MOVS Phase 0 : Entry 1. Pointer ""in Page""-test prepare, 2. test for R0=0 , then jump to x\'C0\r
+\t\t\tbegin\r
+\t\t\t  STATE_0  = {\t addr_nop,8\'h67, 7\'h01, 7\'h02, 1\'b0,dest_x,op_stpr,\t2\'b00,2\'b00,4\'h0  };\t// String-Pointer prepare\r
+\t\t\t  state_50 = dont_care;\r
+\t\t\t  state_53 = dont_care;\r
+\t\t\t  state_54 = dont_care;\r
+\t\t\t  state_55 = dont_care;\r
+\t\t\t  state_58 = dont_care;\r
+\t\t\t  state_59 = dont_care;\r
+\t\t\t  state_5A = dont_care;\r
+\t\t\tend\r
+\t\t5\'b1_0001 :\t// MOVM Phase 0 : Entry with test for R0=0 , then jump to x\'C0\r
+\t\t\tbegin\r
+\t\t\t  STATE_0  = {   ADRD1,   phsrc1,src_x, REGA1, 1\'b0,dest_x,op_mov,  2\'b00,2\'b00,NXRD1 };\r
+\t\t\t  state_50 = {   ADRD1,   phsrc1,IRRW1, REGA1, 1\'b0,dest_x,op_mov,  2\'b00,2\'b00,NXRD1 };\r
+\t\t\t  state_53 = {   ADRD2,   phsrc2,IRRW2, REGA2, 1\'b1,temp_h,op_adr,  2\'b00,2\'b00,NXRW2 };\r
+\t\t\t  state_54 = dont_care;\r
+\t\t\t  state_55 = dont_care;\r
+\t\t\t  state_58 = {\t disp2ea, 8\'h65, src_x, src_x, 1\'b1,temp_1,op_adr,  2\'b00,2\'b00,4\'b1110 };\t// Read of DISP for count\r
+\t\t\t  state_59 = {\t addr_nop,8\'h67, rtmph, rtmp1, 1\'b0,dest_x,op_stpr,\t2\'b00,2\'b00,4\'h0  };\t// String-Pointer prepare\r
+\t\t\t  state_5A = dont_care;\r
+\t\t\tend\r
+\t\t5\'b1_0010 :\t// JUMP/JSR\r
+\t\t\tbegin\r
+\t\t\t  STATE_0  = {   ADRD1,   phsrc1,src_x, REGA1, 1\'b0,dest_x,op_mov,  2\'b00,2\'b00,NXRD1 };\r
+\t\t\t  state_50 = {   ADRD1,   phsrc1,IRRW1, REGA1, 1\'b0,dest_x,op_mov,  2\'b00,2\'b00,NXRD1 };\r
+\t\t\t  state_53 = {   addr_nop,8\'h66, src_x, src_x, 1\'b1,temp_h,op_adr,  2\'b00,2\'b00,4\'h0  };\r
+\t\t\t  state_54 = dont_care;\r
+\t\t\t  state_55 = dont_care;\r
+\t\t\t  state_58 = dont_care;\r
+\t\t\t  state_59 = dont_care;\r
+\t\t\t  state_5A = dont_care;\r
+\t\t\tend\r
+\t\t5\'b1_1110 :\t// CXPD\r
+\t\t\tbegin\r
+\t\t\t  STATE_0  = {   ADRD1,   phsrc1,src_x, REGA1, 1\'b0,dest_x,op_mov,  2\'b00,2\'b00,NXRD1 };\r
+\t\t\t  state_50 = {   ADRD1,   phsrc1,IRRW1, REGA1, 1\'b0,dest_x,op_mov,  2\'b00,2\'b00,NXRD1 };\r
+\t\t\t  state_53 = {   addr_nop,8\'h6B, imme,  src_x, 1\'b1,temp_h,op_mov,  2\'b00,2\'b00,4\'h0  };\r
+\t\t\t  state_54 = dont_care;\r
+\t\t\t  state_55 = dont_care;\r
+\t\t\t  state_58 = dont_care;\r
+\t\t\t  state_59 = dont_care;\r
+\t\t\t  state_5A = dont_care;\r
+\t\t\tend\r
+\t\t5\'b1_1111 :\t// RDVAL+WRVAL\r
+\t\t\tbegin\r
+\t\t\t  STATE_0  = {   ADRD1,   phsrc1,src_x, REGA1, 1\'b0,dest_x,op_mov,  2\'b00,2\'b00,NXRD1 };\r
+\t\t\t  state_50 = {   ADRD1,   phsrc1,IRRW1, REGA1, 1\'b0,dest_x,op_mov,  2\'b00,2\'b00,NXRD1 };\r
+\t\t\t  state_53 = {   addr_nop,8\'h00, src_x, src_x, 1\'b0,dest_x,op_rwv,  2\'b00,2\'b10,4\'h0  };\t// LD_OUT set because of ""F""\r
+\t\t\t  state_54 = dont_care;\r
+\t\t\t  state_55 = dont_care;\r
+\t\t\t  state_58 = dont_care;\r
+\t\t\t  state_59 = dont_care;\r
+\t\t\t  state_5A = dont_care;\r
+\t\t\tend\r
+\t\t5\'b1_0011 :\t// CASE\r
+\t\t\tbegin\r
+\t\t\t  STATE_0  = ACCA[3] ?\t\t// _M...\r
+\t\t\t\t\t\t {   ADRD1,   phsrc1,src_x, REGA1, 1\'b0,dest_x,op_mov,  2\'b00,2\'b00,NXRD1 }\r
+\t\t\t\t\t   : {\t case_op, 8\'h54, SRC_1, src_x, 1\'b0,dest_x,op_bwd,\t2\'b00,2\'b00,4\'h0  };\r
+\t\t\t  state_50 = {   ADRD1,   phsrc1,IRRW1, REGA1, 1\'b0,dest_x,op_mov,  2\'b00,2\'b00,NXRD1 };\t// only one operand in mem.\r
+\t\t\t  state_53 = {   case_op, 8\'h54, imme,  src_x, 1\'b0,dest_x,op_bwd,\t2\'b00,2\'b00,4\'h0  };\r
+\t\t\t  state_54 = {   addr_nop,8\'h66, src_x, src_x, 1\'b1,temp_h,op_adr,  2\'b00,2\'b00,4\'h0  };\r
+\t\t\t  state_55 = dont_care;\r
+\t\t\t  state_58 = dont_care;\r
+\t\t\t  state_59 = dont_care;\r
+\t\t\t  state_5A = dont_care;\r
+\t\t\tend\r
+\t\t5\'b1_0100 : // all Bit opcodes with Bit in memory. RMW Test in Phase x\'59 = Special case, otherwise x\'58\r
+\t\t\tbegin\r
+\t\t\t  STATE_0  = ACCA[3] ?\t\t// _M...\r
+\t\t\t\t\t\t {   ADRD1,   phsrc1,src_x, REGA1, 1\'b0,dest_x,op_mov,  2\'b00,2\'b00,NXRD1 }\r
+\t\t\t\t\t   : {\t addr_nop,8\'h54, SRC_1, src_x, 1\'b1,temp_h,op_mov,\t2\'b00,2\'b00,4\'h0  };\r
+\t\t\t  state_50 = ACCA[3] ?\t\t// _M...\r
+\t\t\t\t\t\t {   ADRD1,   phsrc1,IRRW1, REGA1, 1\'b0,dest_x,op_mov,  2\'b00,2\'b00,NXRD1 }\r
+\t\t\t\t\t   : {\t addr_nop,8\'h54, SRC_1, src_x, 1\'b1,temp_h,op_mov,\t2\'b00,2\'b00,4\'h0  };\r
+\t\t\t  state_53 = {   addr_nop,8\'h54, imme,  src_x, 1\'b1,temp_h,op_mov,\t2\'b00,2\'b00,4\'h0  };\r
+\t\t\t  state_54 = {\t ADRD2,   phsrc2,IRRW2, REGA2, 1\'b0,dest_x,op_mov,  2\'b00,2\'b00,NXRW2 };\t// here SRC1 => TEMP_H\r
+\t\t\t  state_55 = dont_care;\r
+\t\t\t  state_58 = {\t read_byb,8\'h59, rtmph, src_x, 1\'b0,dest_x,op_bwd,\t2\'b00,2\'b00,4\'h1  };\t// next read of Byte\r
+\t\t\t  state_59 = tbit_flag ?\r
+\t\t\t\t\t\t {\t addr_nop,8\'h00, src_x, imme,  1\'b0,dest_x,OPERA,\t2\'b00,2\'b10,4\'h0  }\t\t// TBIT end\r
+\t\t\t\t\t   : {\t re_wr,   8\'h27, src_x, imme,  1\'b0,dest_x,OPERA,\t2\'b00,2\'b10,4\'h1  };\t// CBIT/SBIT/IBIT end\r
+\t\t\t  state_5A = dont_care;\r
+\t\t\tend\r
+\t\t5\'b1_0101 : // EXTS : BASE Operand => TEMP, calculate address of Destination\r
+\t\t\tbegin\r
+\t\t\t  STATE_0  = ACCA[3] ?\t\t// _M...\r
+\t\t\t\t\t\t {   ADRD1,   phsrc1,src_x, REGA1, 1\'b0,dest_x,op_mov,  2\'b00,2\'b00,NXRD1 }\r
+\t\t\t\t\t   : {\t addr_nop,8\'h54, SRC_1, src_x, 1\'b1,temp_h,op_mov,\t2\'b00,2\'b00,4\'h0  };\r
+\t\t\t  state_50 = ACCA[3] ?\t\t// _M...\r
+\t\t\t\t\t\t {   ADRD1,   phsrc1,IRRW1, REGA1, 1\'b0,dest_x,op_mov,  2\'b00,2\'b00,NXRD1 }\r
+\t\t\t\t\t   : {\t addr_nop,8\'h54, SRC_1, src_x, 1\'b1,temp_h,op_mov,\t2\'b00,2\'b00,4\'h0  };\r
+\t\t\t  state_53 = {   addr_nop,8\'h54, imme,  src_x, 1\'b1,temp_h,op_mov,\t2\'b00,2\'b00,4\'h0  };\r
+\t\t\t  state_54 = ACCA[1] ?\r
+\t\t\t\t\t\t {\t ADRD2,   phsrc2,IRRW2, REGA2, 1\'b0,dest_x,op_mov,  2\'b00,2\'b00,NXRW2 }\t\t// here Adr(DEST) => EA\r
+\t\t\t\t\t   : {\t addr_nop,8\'h59, src_x, src_x, 1\'b0,dest_x,op_mov,\t2\'b00,2\'b00,4\'h8  };\t// 1 Byte Immediate read\r
+\t\t\t  state_55 = dont_care;\r
+\t\t\t  state_58 = {\t addr_nop,8\'h59, src_x, src_x, 1\'b0,dest_x,op_mov,\t2\'b00,2\'b00,4\'h8  };\t// 1 Byte Immediate read\r
+\t\t\t  state_59 = ACCA[1] ?\t\t// _..M.\r
+\t\t\t\t\t\t {\t rexwr,   8\'h27, imme,  rtmph, 1\'b0,dest_x,OPERA,\t2\'b00,2\'b10,4\'h1  }\t\t// result in memory\r
+\t\t\t\t\t   : {\t addr_nop,8\'h00, imme,  rtmph, 1\'b1,dest_2,OPERA,\t2\'b00,2\'b00,4\'h0  };\t// result in Register\r
+\t\t\t  state_5A = dont_care;\r
+\t\t\tend\r
+\t\t5\'b1_1010 : // EXT : BASE Operand => TEMP, calculate address of Destination\r
+\t\t\tbegin\r
+\t\t\t  STATE_0  = ACCA[3] ?\t\t// _M...\r
+\t\t\t\t\t\t {   ADRD1,   phsrc1,src_x, REGA1, 1\'b0,dest_x,op_mov,  2\'b00,2\'b00,NXRD1 }\r
+\t\t\t\t\t   : {\t addr_nop,8\'h54, SRC_1, src_x, 1\'b1,temp_h,op_mov,\t2\'b00,2\'b00,4\'h0  };\r
+\t\t\t  state_50 = ACCA[3] ?\t\t// _M...\r
+\t\t\t\t\t\t {   ADRD1,   phsrc1,IRRW1, REGA1, 1\'b0,dest_x,op_mov,  2\'b00,2\'b00,NXRD1 }\r
+\t\t\t\t\t   : {\t addr_nop,8\'h54, SRC_1, src_x, 1\'b1,temp_h,op_mov,\t2\'b00,2\'b00,4\'h0  };\r
+\t\t\t  state_53 = {   addr_nop,8\'h55, src_x, src_x, 1\'b0,dest_x,op_mov,\t2\'b00,2\'b00,4\'h0  };\t// Addr => EA Reg\r
+\t\t\t  state_54 = ACCA[1] ?\r
+\t\t\t\t\t\t  ( ACCA[3] ?\r
+\t\t\t\t\t\t    {addr_nop,8\'h5A, imme,  src_x, 1\'b1,temp_h,op_mov,\t2\'b00,2\'b00,4\'h0  }\r
+\t\t\t\t\t\t   :{ADRD2,   phsrc2,IRRW2, REGA2, 1\'b0,dest_x,op_mov,\t2\'b00,2\'b00,NXRW2 }\t)\t// here Adr(DEST) => EA\r
+\t\t\t\t\t   : {\t addr_nop,8\'h59, rd_reg,'b""(ACCA[3] ? imme : rtmph), \r
+\t\t\t\t\t\t\t\t\t\t\t\t\t\t   1'b1,temp_h,op_lsh,\t2'b00,2'b00,4'hE  };\t// Displacement read\r
+\t\t\t  state_55 = {   exoffset,8'h54, rd_reg,src_x, 1'b0,dest_x,op_mov,\t2'b00,2'b00,4'h1  };\t// Read Source, EA reuse\r
+\t\t\t  state_58 = {\t addr_nop,8'h59, rd_reg,rtmph, 1'b1,temp_h,op_lsh,\t2'b00,2'b00,4'hE  };\t// Displacement read\r
+\t\t\t  state_59 = ACCA[1] ?\t\t// _..M.\r
+\t\t\t\t\t\t {\t rexwr,   8'h27, src_x, rtmph, 1'b0,dest_x,OPERA,\t2'b00,2'b10,4'h1  }\t\t// result in memory\r
+\t\t\t\t\t   : {\t addr_nop,8'h00, src_x, rtmph, 1'b1,dest_2,OPERA,\t2'b00,2'b00,4'h0  };\t// result in Register\r
+\t\t\t  state_5A = {\t ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,\t2'b00,2'b00,NXRW2 };\t// special case Mem-Mem\r
+\t\t\tend\r
+\t\t5'b1_1011 : // INS/INSS : BASE Operand => TEMP, SRC2 read as Double ! RMW not tested (Phase x'6A) but uncritical\r
+\t\t\tbegin\r
+\t\t\t  STATE_0  = ACCA[3] ?\t\t// _M...\r
+\t\t\t\t\t\t {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }\r
+\t\t\t\t\t   : {\t addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0  };\r
+\t\t\t  state_50 = ACCA[3] ?\t\t// _M...\r
+\t\t\t\t\t\t {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }\r
+\t\t\t\t\t   : {\t addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0  };\r
+\t\t\t  state_53 = {   addr_nop,8'h54, imme,  src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0  };\t// zext(SRC1) => TEMP\r
+\t\t\t  state_54 = ACCA[1] ?\r
+\t\t\t\t\t\t {\t ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,\t2'b00,2'b00,NXRW2 }\t\t// here Adr(DEST) => EA\r
+\t\t\t\t\t   : {\t addr_nop,8'h5A, SRC_2, src_x, 1'b1,temp_l,op_mov,\t2'b00,2'b00,imdi  };\t// Imme./Disp. read\r
+\t\t\t  state_55 = {   exoffset,8'h6A, rd_reg,src_x, 1'b0,dest_x,op_mov,\t2'b00,2'b00,4'h1  };\t// Read Source, EA reuse\r
+\t\t\t  state_58 = {\t addr_nop,8'h55, src_x, src_x, 1'b0,dest_x,op_mov,\t2'b00,2'b00,4'h0  };\t// \r
+\t\t\t  state_59 = ACCA[1] ?\t\t// _..M.\r
+\t\t\t\t\t\t {\t re_wr,   8'h27, rtmph, rtmpl, 1'b0,dest_x,OPERA,\t2'b00,2'b10,4'h1  }\t\t// result in memory\r
+\t\t\t\t\t   : {\t addr_nop,8'h00, rtmph, rtmpl, 1'b1,dest_2,OPERA,\t2'b00,2'b00,4'h0  };\t// result in Register\r
+\t\t\t  state_5A = {\t addr_nop,8'h68, imme,  src_x, 1'b1,temp_1,op_msk,\t2'b00,2'b00,4'h0  };\t// Mask generate\r
+\t\t\tend\r
+\t\t5'b1_1101 : // INDEX : \r
+\t\t\tbegin\r
+\t\t\t  STATE_0  = ACCA[3] ?\t\t// _M...\r
+\t\t\t\t\t\t {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }\r
+\t\t\t\t\t   : {\t addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0  };\r
+\t\t\t  state_50 = ACCA[3] ?\t\t// _M...\r
+\t\t\t\t\t\t {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }\r
+\t\t\t\t\t   : {\t addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0  };\r
+\t\t\t  state_53 = {   addr_nop,8'h54, imme,  src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0  };\t// zext(SRC1) => TEMP_H\r
+\t\t\t  state_54 = ACCA[1] ?\r
+\t\t\t\t\t\t {\t ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,\t2'b00,2'b00,NXRW2 }\t\t// zext(SRC2) => TEMP_L\r
+\t\t\t\t\t   : {\t addr_nop,8'h55, SRC_2, src_x, 1'b1,temp_l,op_zext, 2'b00,2'b00,4'h0  };\r
+\t\t\t  state_55 = {   addr_nop,8'h5A, rd_reg,rtmph, 1'b1,temp_h,op_mul,\t2'b00,2'b00,4'h0  };\t// Multiplication\r
+\t\t\t  state_58 = {\t addr_nop,8'h55, imme,  src_x, 1'b1,temp_l,op_zext, 2'b00,2'b00,4'h0  };\t// \r
+\t\t\t  state_59 = {\t addind,  8'h60, rtmpl, src_x, 1'b0,dest_x,op_mov,\t2'b00,2'b00,4'h0  };\t// Add of Index in EA\r
+\t\t\t  state_5A = {\t addone,  8'h59, rd_reg,rtmph, 1'b0,dest_x,op_mov,\t2'b00,2'b00,4'h0  };\t// Add of EA (=+1)\r
+\t\t\tend\r
+\t\t5'b1_0111 :\t// DEI + MEI , both read 8B from DEST ! RMW critical !\r
+\t\t\tbegin\r
+\t\t\t  STATE_0  = ACCA[3] ?\t\t// _M...\r
+\t\t\t\t\t\t {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }\r
+\t\t\t\t\t   : {\t addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov,\t2'b00,2'b00,4'h0  };\r
+\t\t\t  state_50 = ACCA[3] ?\t\t// _M...\r
+\t\t\t\t\t\t {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }\r
+\t\t\t\t\t   : {\t addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov,\t2'b00,2'b00,4'h0  };\r
+\t\t\t  state_53 = {   addr_nop,8'h54, imme,  src_x, 1'b1,temp_h,op_mov,\t2'b00,2'b00,4'h0  };\r
+\t\t\t  state_54 = ACCA[1] ?\r
+\t\t\t\t\t\t {\t ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 }\t\t// here SRC1 => TEMP_H\r
+\t\t\t\t\t   : {\t addr_nop,8'h59, rtmph, SRC_2, 1'b0,dest_x,OPERA,\t2'b01,2'b00,4'h0  };\t// 1. part of Register\r
+\t\t\t  state_55 = dont_care;\r
+\t\t\t  state_58 = size_dw ?\r
+\t\t\t\t\t\t {\t addr_nop,8'h59, rtmph, imme,  1'b0,dest_x,OPERA,\t2'b01,2'b00,4'h0  }\t\t// D needs 2 accesses\r
+\t\t\t\t\t   : {\t addr_nop,8'h1F, rtmph, imme,  1'b0,dest_x,OPERA,\t2'b11,2'b00,4'h0  };\t// B+W start at once\r
+\t\t\t  state_59 = {\t addr_nop,8'h1F, src_x, (ACCA[1] ? imme : src_2l),\t\t\t\t\t\t\t// SRC2 = memory or Reg\r
+\t\t\t\t\t\t\t\t\t\t\t\t\t   ~ACCA[1],dest_2,OPERA,\t2'b10,2'b00,4'h0  };\r
+\t\t\t  state_5A = dont_care;\r
+\t\t\tend\r
+\t\t5'b1_1000 :\t// CHECK\r
+\t\t\tbegin\r
+\t\t\t  STATE_0  = {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 };\t// No Register !\r
+\t\t\t  state_50 = {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 };\r
+\t\t\t  state_53 = {   addr_nop,phchk, imme,  src_x, 1'b1,temp_h,op_mov,\t2'b00,2'b00,4'h0  };\t// No Immediate !\r
+\t\t\t  state_54 = ACCA[1] ?\r
+\t\t\t\t\t\t {\t ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 }\t\r
+\t\t\t\t\t   : (  size_dw ?\r
+\t\t\t\t\t\t\t{addr_nop,8'h5A, SRC_2, rtmpl, 1'b0,dest_x,OPERA,\t2'b00,2'b10,4'h0  }\t\t// Upper Bound - pointer\r
+\t\t\t\t\t\t  : {addr_nop,8'h00, rtmph, SRC_2, 1'b1,chkreg,OPERA,\t2'b00,2'b10,4'h0  } );\r
+\t\t\t  state_55 = {   addr_nop,8'h54, imme,  src_x, 1'b1,temp_l,op_mov,\t2'b00,2'b00,4'h0  };\r
+\t\t\t  state_58 = size_dw ?\r
+\t\t\t\t\t\t {\t addr_nop,8'h59, imme,  src_x, 1'b1,temp_1,op_mov,\t2'b00,2'b00,4'h0  }\t\t// here SRC2 => TEMP_1\r
+\t\t\t\t\t   : {\t addr_nop,8'h00, rtmph, imme,  1'b1,chkreg,OPERA,\t2'b00,2'b10,4'h0  };\r
+\t\t\t  state_59 = {\t addr_nop,8'h5A, rtmp1, rtmpl, 1'b0,dest_x,OPERA,\t2'b00,2'b10,4'h0  };\t// Upper Bound - pointer\r
+\t\t\t  state_5A = {\t addr_nop,8'h00, rtmph, (ACCA[1] ? rtmp1 : SRC_2),\r
+\t\t\t\t\t\t\t\t\t\t\t\t\t\t   1'b1,chkreg,OPERA,\t2'b00,2'b10,4'h0  };\t// pointer - Lower Bound\r
+\t\t\tend\r
+\t\t5'b1_1100 :\t// CVTP\r
+\t\t\tbegin\r
+\t\t\t  STATE_0  = {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 };\t// Address\r
+\t\t\t  state_50 = {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 };\r
+\t\t\t  state_53 = {   addr_nop,8'h54, src_x, src_x, 1'b1,temp_h,op_adr,\t2'b00,2'b00,4'h0  };\t\r
+\t\t\t  state_54 = {\t adrcvtp, 8'h73, rtmph, rd_reg,1'b0,dest_x,op_mov,  2'b00,2'b00,4'h0  };\t// 8*TEMP+Offset\r
+\t\t\t  state_55 = dont_care;\r
+\t\t\t  state_58 = dont_care;\r
+\t\t\t  state_59 = dont_care;\r
+\t\t\t  state_5A = dont_care;\r
+\t\t\tend\r
+//\t\t5'b01_000 :\t// SCALBL : RMW critical !\r
+//\t\t\tbegin\r
+//\t\t\t  STATE_0  = ACCA[3] ?\t\t// _M...\r
+//\t\t\t\t\t\t {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }\r
+//\t\t\t\t\t   : {\t addr_nop,8'h54, SRC_1, src_1l,1'b1,temp_h,op_trul, 2'b11,2'b00,4'h0  };\r
+//\t\t\t  state_50 = ACCA[3] ?\t\t// _M...\r
+//\t\t\t\t\t\t {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }\r
+//\t\t\t\t\t   : {\t addr_nop,8'h54, SRC_1, src_1l,1'b1,temp_h,op_trul, 2'b11,2'b00,4'h0  };\r
+//\t\t\t  state_53 = {   addr_nop,8'h55, imme,  src_x, 1'b1,temp_h,op_mov,\t2'b00,2'b00,get8b_s };\r
+//\t\t\t  state_54 = ACCA[1] ?\r
+//\t\t\t\t\t\t {\t ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_trul, 2'b00,2'b00,NXRW2 }\r
+//\t\t\t\t\t   : {\t addr_nop,8'h5A, src_x, src_x, 1'b0,temp_h,op_trul,\t2'b00,2'b00,4'h0  };\r
+//\t\t\t  state_55 = {\t addr_nop,8'h54, rtmph, imme,  1'b1,temp_h,op_trul, 2'b11,2'b00,4'h0  };\t// 2. half of external SRC1\r
+//\t\t\t  state_58 = {\t addr_nop,8'h59, rtmph, imme,  1'b0,dest_2,OPERA,\t2'b01,2'b00,4'h0  };\r
+//\t\t\t  state_59 = {\t addr_nop,8'h1F, src_x, (ACCA[1] ? imme : src_2l),\r
+//\t\t\t\t\t\t\t\t\t\t\t\t\t   ~ACCA[1],dest_2,OPERA,\t2'b10,2'b00,4'h0  };\r
+//\t\t\t  state_5A = {\t addr_nop,8'h59, rtmph, SRC_2, 1'b0,dest_2,OPERA,\t2'b01,2'b00,4'h0  };\t// empty cycle for TRUNC => TEMP !\r
+//\t\t\tend\r
+//\t\t5'b01_001 :\t// SCALBF : RMW critical !\r
+//\t\t\tbegin\r
+//\t\t\t  STATE_0  = ACCA[3] ?\t\t// _M...\r
+//\t\t\t\t\t\t {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }\r
+//\t\t\t\t\t   : {\t addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_truf, 2'b00,2'b00,4'h0  };\r
+//\t\t\t  state_50 = ACCA[3] ?\t\t// _M...\r
+//\t\t\t\t\t\t {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }\r
+//\t\t\t\t\t   : {\t addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_truf, 2'b00,2'b00,4'h0  };\r
+//\t\t\t  state_53 = {   addr_nop,8'h54, imme,  src_x, 1'b1,temp_h,op_truf, 2'b00,2'b00,4'h0  };\r
+//\t\t\t  state_54 = ACCA[1] ?\r
+//\t\t\t\t\t\t {\t ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 }\r
+//\t\t\t\t\t   : {\t addr_nop,8'h1F, rtmph, SRC_2, 1'b1,dest_2,OPERA,\t2'b11,2'b00,4'h0  };\r
+//\t\t\t  state_55 = dont_care;\r
+//\t\t\t  state_58 = {\t addr_nop,8'h1F, rtmph, imme,  1'b0,dest_x,OPERA,\t2'b11,2'b00,4'h0  };\r
+//\t\t\t  state_59 = dont_care;\r
+//\t\t\t  state_5A = dont_care;\r
+//\t\t\tend\r
+//\t\t5'b01_100 :\t// POLYL\r
+//\t\t\tbegin\r
+//\t\t\t  STATE_0  = ACCA[3] ?\t\t// _M...\r
+//\t\t\t\t\t\t {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }\r
+//\t\t\t\t\t   : {\t addr_nop,8'h54, SRC_1, F0_h,  1'b0,temp_h,op_mull, 2'b01,2'b00,4'h0  };\r
+//\t\t\t  state_50 = ACCA[3] ?\t\t// _M...\r
+//\t\t\t\t\t\t {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }\r
+//\t\t\t\t\t   : {\t addr_nop,8'h54, SRC_1, F0_h,  1'b0,temp_h,op_mull, 2'b01,2'b00,4'h0  };\r
+//\t\t\t  state_53 = {   addr_nop,8'h54, imme,  F0_h,  1'b0,temp_h,op_mull, 2'b01,2'b00,get8b_s };\r
+//\t\t\t  state_54 = {\t addr_nop,8'h64, (ACCA[3] ? imme : src_1l),\r
+//\t\t\t\t\t\t\t\t\t\t\t\t\tF0,    1'b1,temp_h,op_mull, 2'b10,2'b00,4'h0  };\r
+//\t\t\t  state_55 = dont_care;\r
+//\t\t\t  state_58 = {\t addr_nop,8'h59, imme,  rtmph, 1'b0,dest_x,op_addl, 2'b01,2'b00,get8b_d };\r
+//\t\t\t  state_59 = {\t addr_nop,8'h62, (ACCA[1] ? imme : src_2l),\r
+//\t\t\t\t\t\t\t\t\t\t\t\t\trtmpl, 1'b1,w_F0_h,op_addl, 2'b10,2'b00,4'h0  };\r
+//\t\t\t  state_5A = dont_care;\r
+//\t\t\tend\t\t\t  \r
+//\t\t5'b01_101 :\t// POLYF\r
+//\t\t\tbegin\r
+//\t\t\t  STATE_0  = ACCA[3] ?\t\t// _M...\r
+//\t\t\t\t\t\t {   ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }\r
+//\t\t\t\t\t   : {\t addr_nop,8'h54, SRC_1, F0,    1'b1,temp_h,op_mulf, 2'b00,2'b00,4'h0  };\r
+//\t\t\t  state_50 = ACCA[3] ?\t\t// _M...\r
+//\t\t\t\t\t\t {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }\r
+//\t\t\t\t\t   : {\t addr_nop,8'h54, SRC_1, F0,    1'b1,temp_h,op_mulf, 2'b00,2'b00,4'h0  };\r
+//\t\t\t  state_53 = {   addr_nop,8'h54, imme,  F0,    1'b1,temp_h,op_mulf, 2'b00,2'b00,4'h0  };\r
+//\t\t\t  state_54 = ACCA[1] ?\r
+//\t\t\t\t\t\t {\t ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 }\r
+//\t\t\t\t\t   : {\t addr_nop,8'h00, rtmph, SRC_2, 1'b1,w_F0  ,op_addf, 2'b00,2'b00,4'h0  };\r
+//\t\t\t  state_55 = dont_care;\r
+//\t\t\t  state_58 = {\t addr_nop,8'h00, rtmph, imme,  1'b1,w_F0  ,op_addf, 2'b00,2'b00,4'h0  };\r
+//\t\t\t  state_59 = dont_care;\r
+//\t\t\t  state_5A = dont_care;\r
+//\t\t\tend\t\t\t  \r
+//\t\t5'b01_110 :\t// DOTL\r
+//\t\t\tbegin\r
+//\t\t\t  STATE_0  = (~ACCA[3] & ~ACCA[1]) ?\t\t// _R.R.\r
+//\t\t\t\t\t\t {\t addr_nop,8'h59, SRC_1, SRC_2, 1'b0,dest_x,op_mull, 2'b01,2'b00,4'h0  }\r
+//\t\t\t\t\t   : (  ACCA[3] ?\t\t// _M...\r
+//\t\t\t\t\t\t    {ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }\r
+//\t\t\t\t\t\t  : {ADRD2,   phsrc2,src_x, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 } );\r
+//\t\t\t  state_50 = ACCA[3] ?\t\t// _M...\r
+//\t\t\t\t\t\t {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }\r
+//\t\t\t\t\t   : {   ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 };\r
+//\t\t\t  state_53 = ACCA[1] ?\t\t// _..M.\r
+//\t\t\t\t\t\t {   addr_nop,8'h54, imme,  src_x, 1'b1,temp_h,op_mov,  2'b00,2'b00,get8b_s }\r
+//\t\t\t\t\t   : {\t addr_nop,8'h59, imme,  SRC_2, 1'b0,dest_x,op_mull, 2'b01,2'b00,get8b_s };\r
+//\t\t\t  state_54 = {\t addr_nop,8'h55, imme,  src_x, 1'b1,temp_l,op_mov,  2'b00,2'b00,4'h0  };\r
+//\t\t\t  state_55 = {\t ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 };\r
+//\t\t\t  state_58 = {\t addr_nop,8'h59, (ACCA[3] ? rtmph : SRC_1),\t\t//_M...\r
+//\t\t\t\t\t\t\t\t\t\t\t\t\timme,  1'b0,dest_x,op_mull, 2'b01,2'b00,get8b_d };\r
+//\t\t\t  state_59 = {\t addr_nop,8'h5A, (ACCA[3] ? (ACCA[1] ? rtmpl : imme) : src_1l), (ACCA[1] ? imme : src_2l),\r
+//\t\t\t\t\t\t\t\t\t\t\t\t\t\t   1'b1,temp_h,op_mull, 2'b10,2'b00,4'h0  };\r
+//\t\t\t  state_5A = {\t addr_nop,8'h61, rtmph, F0_h,  1'b0,temp_h,op_mull, 2'b01,2'b00,4'h0  };\r
+//\t\t\tend\t\t\t  \r
+//\t\t5'b01_111 :\t// DOTF\r
+//\t\t\tbegin\r
+//\t\t\t  STATE_0  = (~ACCA[3] & ~ACCA[1]) ?\t\t// _R.R.\r
+//\t\t\t\t\t\t {\t addr_nop,8'h63, SRC_1 ,SRC_2 ,1'b1,temp_h,op_mulf, 2'b00,2'b00,4'h0  }\t\t// opera = MULF\r
+//\t\t\t\t\t   : (  ACCA[3] ?\t\t// _M...\r
+//\t\t\t\t\t\t    {ADRD1,   phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }\r
+//\t\t\t\t\t\t  : {ADRD2,   phsrc2,src_x, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 } );\r
+//\t\t\t  state_50 = ACCA[3] ?\t\t// _M...\r
+//\t\t\t\t\t\t {   ADRD1,   phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRD1 }\r
+//\t\t\t\t\t   : {   ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 };\r
+//\t\t\t  state_53 = ACCA[1] ?\t\t// _..M.\r
+//\t\t\t\t\t\t {   addr_nop,8'h55, imme,  src_x, 1'b1,temp_h,op_mov,  2'b00,2'b00,4'h0  }\r
+//\t\t\t\t\t   : {\t addr_nop,8'h63, imme,  SRC_2 ,1'b1,temp_h,op_mulf, 2'b00,2'b00,4'h0  };\r
+//\t\t\t  state_54 = dont_care;\r
+//\t\t\t  state_55 = {\t ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov,  2'b00,2'b00,NXRW2 };\r
+//\t\t\t  state_58 = {\t addr_nop,8'h63, (ACCA[3] ? rtmph : SRC_1),\t\t//_M...\r
+//\t\t\t\t\t\t\t\t\t\t\t\t\timme,  1'b1,temp_h,op_mulf, 2'b00,2'b00,4'h0  };\r
+//\t\t\t  state_59 = dont_care;\r
+//\t\t\t  state_5A = dont_care;\r
+//\t\t\tend\t\t\t  \r
+\t\tdefault\r
+\t\t\tbegin\r
+\t\t\t  STATE_0  = dont_care;\r
+\t\t\t  state_50 = dont_care;\r
+\t\t\t  state_53 = dont_care;\r
+\t\t\t  state_54 = dont_care;\r
+\t\t\t  state_55 = dont_care;\r
+\t\t\t  state_58 = dont_care;\r
+\t\t\t  state_59 = dont_care;\r
+\t\t\t  state_5A = dont_care;\r
+\t\t\tend\r
+\t\tendcase\r
+\t\t\r
+\talways @(*)\r
+\t  casex (PHASE)\r
+\t\t 4'h0 : STATE_GROUP_50 = state_50;\r
+\t\t// Phase 51 : wait for data and Disp2 for External Address mode : part 2 EA = (MOD+4)+4*DISP1\r
+\t\t 4'h1 : STATE_GROUP_50 = {exr11,   8'h52, src_x,imme , 1'b0,dest_x,\t\top_mov,\t2'b00,2'b00,\t4'b1111};\r
+\t\t// Phase 52 : Memory-Pointer for Memory Relative and last access External\r
+\t\t 4'h2 : STATE_GROUP_50 = {EXR12,   8'h53, IRRW1,imme , 1'b0,dest_x,\t\top_mov,\t2'b00,2'b00,\t4'b1111};  // atys[0] !\r
+\t\t 4'h3 : STATE_GROUP_50 = state_53;\r
+\t\t 4'h4 : STATE_GROUP_50 = state_54;\r
+\t\t 4'h5 : STATE_GROUP_50 = state_55;\r
+\t\t// Phase 56 : wait for data and Disp2 for External Address mode : part 2 EA = (MOD+4)+4*DISP1\r
+\t\t 4'h6 : STATE_GROUP_50 = {exr11,   8'h57, src_x,imme , 1'b0,dest_x,\t\top_mov,\t2'b00,2'b00,\t4'b1111};\r
+\t\t// Phase 57 : Memory-Pointer for Memory Relative and last access External\r
+\t\t 4'h7 : STATE_GROUP_50 = {EXR22,   8'h58, IRRW2,imme , 1'b0,dest_x,\t\top_mov,\t2'b00,2'b00,\t4'b1111};  // atyd[0] !\r
+\t\t 4'h8 : STATE_GROUP_50 = state_58;\r
+\t\t 4'h9 : STATE_GROUP_50 = state_59;\r
+\t\t 4'hA : STATE_GROUP_50 = state_5A;\r
+\t  default : STATE_GROUP_50 = dont_care;\r
+\t  endcase\r
+\t  \r
+\talways @(*)\r
+\t  casex (PHASE)\r
+\t\t 4'h0 : STATE_GROUP_60 = {\t addr_nop,8'h00, src_x, src_x, 1'b1,chkreg,op_adr,  2'b00,2'b00,4'h0  };\t// for INDEX\r
+\t\t 4'h1 : STATE_GROUP_60 = {\t addr_nop,8'h62, rtmpl, F0,    1'b1,w_F0_h,op_addl, 2'b10,2'b00,4'h0  };\t// for DOTL\r
+\t\t 4'h2 : STATE_GROUP_60 = {\t addr_nop,8'h00, src_x, src_x, 1'b0,w_F0_h,op_addl, 2'b00,2'b00,4'h0  };\t// for DOTL & POLYL !\r
+\t\t 4'h3 : STATE_GROUP_60 = {\t addr_nop,8'h00, rtmph, F0,    1'b1,w_F0,  op_addf, 2'b00,2'b00,4'h0  };\t// for DOTF\r
+\t\t 4'h4 : STATE_GROUP_60 = ACCA[1] ?\t// ..M.\r
+\t\t\t\t\t\t\t\t {\t ADRD2,   phsrc2,IRRW2, REGA2, 1'b0,temp_h,op_mull, 2'b00,2'b00,NXRW2 }\r
+\t\t\t\t\t\t\t   : {\t addr_nop,8'h59, SRC_2, rtmph, 1'b0,temp_h,op_addl, 2'b01,2'b00,4'h0  };\t// for POLYL\r
+\t\t 4'h5 : STATE_GROUP_60 = {\t addr_nop,8'h59, src_x, src_x, 1'b1,temp_l,op_kust, 2'b00,2'b00,4'h0  };\t// for MOVM/CMPM\r
+\t\t 4'h6 : STATE_GROUP_60 = {\t addr_nop,8'h01, rtmph, src_x, 1'b0,dest_x,op_mov,\t2'b00,2'b00,4'h0  };\t// for JUMP/JSR/CASE\r
+\t\t 4'h7 : STATE_GROUP_60 = {\t addr_nop,8'hC0, (op_reg_reg[0] ? rtmpl : 7'h00),\t\t\t\t\t\t\t// Jump to String execution\r
+\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tsrc_x, 1'b0,dest_x,OPERA,\t2'b00,2'b10,4'h0  };\t// LD_OUT set, CMPS F-Flag\r
+\t\t// for INS\t\t\t\t\t\t\t\t\t\t\t\t\t\t\r
+\t\t 4'h8 : STATE_GROUP_60 = {\t addr_nop,8'h69, rd_reg,rtmph, 1'b1,temp_h,op_lsh,\t2'b00,2'b00,4'h0  };\t// SRC1 shift\r
+\t\t 4'h9 : STATE_GROUP_60 = {\t addr_nop,8'h59, rd_reg,rtmp1, 1'b0,dest_x,op_lsh,\t2'b00,2'b00,4'h0  };\t// Mask shift\r
+\t\t 4'hA : STATE_GROUP_60 = {\t addr_nop,8'h5A, imme,  src_x, 1'b1,temp_l,op_mov,\t2'b00,2'b00,imdi  };\t// Imme./Disp. read\r
+\t\t// for CXPD, this State is decoded explicitly in DECODER\r
+\t\t 4'hB : STATE_GROUP_60 = {\t addr_nop,8'h39, imme,  src_x, 1'b1,temp_l,op_mov,\t2'b00,2'b00,4'h0  };\t// pass PC\r
+\t  default : STATE_GROUP_60 = dont_care;\r
+\t  endcase\r
+\t  \r
+endmodule\r
+"
+"// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+// This file is part of the M32632 project\r
+// http://opencores.org/project,m32632\r
+//\r
+// Filename: ADDR_UNIT.v\r
+// Version:  1.1 bug fix\r
+// History:  1.0 first release of 30 Mai 2015\r
+// Date:     7 October 2015\r
+//\r
+// Copyright (C) 2015 Udo Moeller\r
+// \r
+// This source file may be used and distributed without \r
+// restriction provided that this copyright statement is not \r
+// removed from the file and that any derivative work contains \r
+// the original copyright notice and the associated disclaimer.\r
+// \r
+// This source file is free software; you can redistribute it \r
+// and/or modify it under the terms of the GNU Lesser General \r
+// Public License as published by the Free Software Foundation;\r
+// either version 2.1 of the License, or (at your option) any \r
+// later version. \r
+// \r
+// This source is distributed in the hope that it will be \r
+// useful, but WITHOUT ANY WARRANTY; without even the implied \r
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR \r
+// PURPOSE. See the GNU Lesser General Public License for more \r
+// details. \r
+// \r
+// You should have received a copy of the GNU Lesser General \r
+// Public License along with this source; if not, download it \r
+// from http://www.opencores.org/lgpl.shtml \r
+// \r
+// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\tModules contained in this file:\r
+//\tADDR_UNIT\tgenerates data access addresses and controls data cache operation\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+module ADDR_UNIT ( BCLK, BRESET, READ, WRITE, LDEA, NEWACC, CLRMSW, POST, DISP_OK, FULLACC, SRC2SEL, INDEX, ASIZE, SRC1, SRC2, BWD,\r
+\t\t\t\t   DISP, PC_ARCHI, PC_ICACHE, IO_READY, ACC_STAT, MMU_UPDATE, IC_TEX, ABO_STAT, ADIVAR, RWVAL_1, OP_RMW, PHASE_17,\r
+\t\t\t\t   NO_TRAP, FPU_TRAP, READ_OUT, WRITE_OUT, ZTEST, RMW, VADR, ADDR, SIZE, PACKET, ACC_DONE, ABORT, REG_OUT, BITSEL,\r
+\t\t\t\t   QWATWO );\r
+\r
+\tinput\t\t\tBCLK,BRESET;\r
+\tinput\t\t\tREAD,WRITE,LDEA;\r
+\tinput\t\t\tNEWACC;\r
+\tinput\t\t\tCLRMSW,POST,FULLACC;\r
+\tinput\t [1:0]\tSRC2SEL;\r
+\tinput\t [3:0]\tINDEX;\r
+\tinput\t [1:0]\tASIZE;\r
+\tinput\t[31:0]\tSRC1,SRC2;\r
+\tinput\t [1:0]\tBWD;\r
+\tinput\t[31:0]\tDISP;\r
+\tinput\t[31:0]\tPC_ARCHI,PC_ICACHE;\r
+\tinput\t\t\tDISP_OK;\r
+\tinput\t\t\tIO_READY;\r
+\tinput\t [5:0]\tACC_STAT;\t// Feedback from data cache about the running access\r
+\tinput\t [1:0]\tMMU_UPDATE;\r
+\tinput\t [2:0]\tIC_TEX;\r
+\tinput\t [1:0]\tABO_STAT;\r
+\tinput\t\t\tADIVAR;\r
+\tinput\t\t\tRWVAL_1;\t// special access for RDVAL + WRVAL\r
+\tinput\t\t\tOP_RMW;\r
+\tinput\t\t\tPHASE_17;\r
+\tinput\t\t\tNO_TRAP;\r
+\tinput\t\t\tFPU_TRAP;\r
+\t\r
+\toutput\t\t\tREAD_OUT,WRITE_OUT,ZTEST,RMW;\r
+\toutput\t[31:0]\tVADR;\r
+\toutput\t[31:0]\tADDR;\r
+\toutput\t [1:0]\tSIZE;\r
+\toutput\t [3:0]\tPACKET;\r
+\toutput\t\t\tACC_DONE;\r
+\toutput\t\t\tABORT;\r
+\toutput\t\t\tREG_OUT;\r
+\toutput\t [2:0]\tBITSEL;\r
+\toutput\treg\t\tQWATWO;\r
+\t\r
+\treg\t\t[31:0]\tVADR;\r
+\treg\t\t\t\tREAD_OUT,write_reg,ZTEST,RMW;\r
+\treg\t\t [1:0]\tSIZE;\r
+\treg\t\t [3:0]\tPACKET;\r
+\treg\t\t [2:0]\tBITSEL;\r
+\treg\t\t[31:0]\tsource2;\r
+\treg\t\t[31:0]\tindex_val;\r
+\treg\t\t[31:0]\tvadr_reg;\r
+\treg\t\t[31:0]\tea_reg;\r
+\treg\t\t[31:0]\ttos_offset;\r
+\treg\t\t[31:0]\ticache_adr;\r
+\treg\t\t[31:0]\tsign_ext_src1;\r
+\treg\t   [31:12]\tpg_areg;\r
+\treg\t\t\t\treg_out_i,next_reg;\r
+\treg\t\t\t\tld_ea_reg;\r
+\treg\t\t\t\tacc_run,acc_ende,acc_step;\r
+\treg\t\t\t\tqwa_flag;\r
+\treg\t\t\t\tno_done;\r
+\treg\t\t\t\tfrueh_ok;\r
+\treg\t\t\t\tio_rdy;\r
+\treg\t\t\t\tABORT;\r
+\treg\t\t [1:0]\ttex_feld;\r
+\treg\t\t [2:0]\tu_ddt;\r
+\treg\t\t\t\tpg_op;\r
+\treg\t\t\t\tdo_wr;\r
+\t\r
+\twire\t\t\tacc_ok,acc_err,io_acc;\r
+\twire\t\t\tacc_pass;\r
+\twire\t\t\tca_hit;\r
+\twire\t[31:0]\treg_adder;\r
+\twire\t[31:0]\tnext_vadr;\r
+\twire\t[31:0]\tfinal_addr;\r
+\twire\t[31:0]\tpg_addr;\r
+\twire\t [1:0]\tinc_pack;\r
+\twire\t [3:0]\tindex_sel;\r
+\twire\t\t\tld_ea_i;\r
+\twire\t\t\tea_ok;\r
+\twire\t\t\tqw_align;\r
+\twire\t\t\tinit_acc;\r
+\twire\t\t\tin_page;\r
+\twire\t\t\tall_ok;\r
+\twire\t\t\tfa_out;\r
+\twire\t\t\tpg_test;\r
+\r
+\t// ++++++++++++++++++++  Decoding ACC_STAT from data cache  ++++++++++++++++++++++++++++\r
+\t\r
+\t// ACC_STAT[5:0] : CA_HIT, IO_ACC, PROT_ERROR , ABO_LEVEL1 , ABORT , ACC_OK\r
+\t\r
+\tassign ca_hit\t= ACC_STAT[5];\r
+\tassign io_acc   = ACC_STAT[4];\r
+\tassign acc_err  = ACC_STAT[3] | ACC_STAT[1];\t// Abort or Protection Error\r
+\tassign acc_ok   = ACC_STAT[0] & ~pg_op;\r
+\tassign acc_pass = ACC_STAT[0] & ZTEST;\r
+\t\r
+\talways @(posedge BCLK) ABORT <= acc_err;\t// Signal to Steuerung - only a pulse\r
+\t\r
+\talways @(posedge BCLK) if (acc_err) tex_feld <= ACC_STAT[3] ? 2'b11 : {~ACC_STAT[2],ACC_STAT[2]};\t// for MSR\r
+\talways @(posedge BCLK) if (acc_err) u_ddt \t <= {RMW,ABO_STAT[1],(WRITE_OUT | ZTEST)};\r
+\t\r
+\t// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\t\r
+\talways @(SRC2SEL or CLRMSW or SRC2 or PC_ARCHI or ea_reg)\r
+\t\tcase (SRC2SEL)\r
+\t\t  2'b00 : source2 = {(CLRMSW ? 16'h0000 : SRC2[31:16]),SRC2[15:0]};\t// base reg, External Addressing with MOD \r
+\t\t  2'b01 : source2 = PC_ARCHI;\t\t// PC relative\r
+\t\t  2'b10 : source2 = 32'h0;\t\t\t// Absolute Addressing\r
+\t\t  2'b11 : source2 = ea_reg;\t\t\t// REUSE : 2. TOS\r
+\t\tendcase\r
+\t\r
+\tassign index_sel = POST ? 4'h0 : INDEX;\t// Alternative application of Index for POST Adder : POP from Stack\r
+\t\r
+\talways @(BWD or SRC1)\r
+\t\tcasex (BWD)\r
+\t\t\t2'b00 : sign_ext_src1 = {{24{SRC1[7]}}, SRC1[7:0]};\t\t// Byte\r
+\t\t\t2'b01 : sign_ext_src1 = {{16{SRC1[15]}},SRC1[15:0]};\t// Word\r
+\t\t  default : sign_ext_src1 = SRC1;\r
+\t\tendcase\r
+\t\t\r
+\talways @(index_sel or sign_ext_src1 or SRC1)\r
+\t\tcasex (index_sel)\r
+\t\t  4'b1_0xx : index_val = sign_ext_src1;\t// f\xfcr CASE\r
+\t\t  4'b1_1xx : index_val = {{ 3{sign_ext_src1[31]}},sign_ext_src1[31:3]};\t// for Bit Opcodes\r
+\t\t  4'b0_100 : index_val = SRC1;\r
+\t\t  4'b0_101 : index_val = {SRC1[30:0],1'b0};\r
+\t\t  4'b0_110 : index_val = {SRC1[29:0],2'b00};\r
+\t\t  4'b0_111 : index_val = {SRC1[28:0],3'b000};\r
+\t\t  default  : index_val = 32'h0;\r
+\t\tendcase\r
+\t\t\r
+\tassign reg_adder = source2 + index_val;\t// SRC2 allows simple MOV with SRC1\r
+\t\r
+\tassign final_addr = reg_adder + DISP;\t// That's the final access address\r
+\t\r
+\talways @(posedge BCLK) if (LDEA && (index_sel[3:2] == 2'b11)) BITSEL <= SRC1[2:0];\t// for Bit Opcodes in I_PFAD\r
+\t\t\r
+\talways @(INDEX)\t// SP POP Operation & String Backward\r
+\t\tcase (INDEX[2:0])\r
+\t\t  3'b000 : tos_offset = 32'h0000_0001;\r
+\t\t  3'b001 : tos_offset = 32'h0000_0002;\r
+\t\t  3'b010 : tos_offset = 32'h0000_0004;\r
+\t\t  3'b011 : tos_offset = 32'h0000_0008;\r
+\t\t  3'b100 : tos_offset = 32'hFFFF_FFFF;\r
+\t\t  3'b101 : tos_offset = 32'hFFFF_FFFE;\r
+\t\t  3'b110 : tos_offset = 32'hFFFF_FFFC;\r
+\t\t  3'b111 : tos_offset = 32'hFFFF_FFF8;\r
+\t\tendcase\r
+\t\t\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) ld_ea_reg <= 1'b0;\r
+\t\t  else ld_ea_reg <= (LDEA | ld_ea_reg) & ~DISP_OK;\r
+\t\t\t\t\r
+\tassign ld_ea_i = (LDEA | ld_ea_reg) & DISP_OK;\r
+\t\t\r
+\tassign ea_ok = (READ | WRITE | LDEA | ld_ea_reg) & ~FULLACC & DISP_OK;\r
+\t\r
+\talways @(posedge BCLK) icache_adr <= PC_ICACHE;\r
+\t\r
+\t// Memory for the calculated address for reuse and Register for POST modified addresses : \r
+\talways @(posedge BCLK)\r
+\t\tif (ld_ea_i)\r
+\t\t  begin\r
+\t\t\tcasex ({MMU_UPDATE[1],INDEX[0],POST})\r
+\t\t\t  3'b10x : ea_reg <= MMU_UPDATE[0] ? vadr_reg : icache_adr;\t\t// TEAR\r
+\t\t\t  3'b11x : ea_reg <= MMU_UPDATE[0] ?\r
+\t\t\t\t\t\t\t\t  {24'h0000_00,3'b101,\t\tu_ddt,\t\t\t tex_feld}\t\t// MSR\r
+\t\t\t\t\t\t\t\t: {24'h0000_00,3'b100,IC_TEX[2],ABO_STAT[0],1'b0,IC_TEX[1:0]};\t// only READ from ICACHE\r
+\t\t\t  3'b0x1 : ea_reg <= source2 + tos_offset ;\r
+\t\t\t  3'b0x0 : ea_reg <= final_addr;\r
+\t\t\tendcase\r
+\t\t  end\r
+\t\r
+\tassign ADDR = ea_reg;\t// used for ADDR opcode and TOS Addressing\r
+\t\r
+\t// This pulse stores all parameters of access\r
+\tassign init_acc = ((FULLACC ? (NEWACC & acc_ende) : acc_ende) | ~acc_run) & DISP_OK & (READ | WRITE) & ~ABORT & NO_TRAP;\r
+\r
+\tassign fa_out = init_acc | ADIVAR;\t// special case for LMR IVAR,...\r
+\t\r
+\talways @(fa_out or acc_ok or final_addr or qw_align or pg_op or pg_areg or vadr_reg or next_vadr)\r
+\t\tcasex ({fa_out,acc_ok})\t\t\r
+\t\t  2'b1x : VADR = {final_addr[31:3],(final_addr[2] | qw_align),final_addr[1:0]};\r
+\t\t  2'b00 : VADR = pg_op ? {pg_areg,12'h0} : vadr_reg;\r
+\t\t  2'b01 : VADR = next_vadr;\r
+\t\tendcase\r
+\r
+\talways @(posedge BCLK)\r
+\t\tif (init_acc) vadr_reg <= {final_addr[31:3],(final_addr[2] | qw_align),final_addr[1:0]};\r
+\t\t  else\r
+\t\t\tif (pg_op && ZTEST && acc_err) vadr_reg <= {pg_areg,12'h0};\t// for TEAR !\r
+\t\t\t  else\r
+\t\t\t\tif (acc_ok) vadr_reg <= next_vadr;\r
+\t\t\t\r
+\tassign next_vadr = qwa_flag ? {vadr_reg[31:3],3'b000} : ({vadr_reg[31:2],2'b00} + 32'h0000_0004);\r
+\t\r
+\t// Logic for Page border WRITE Test\r
+\tassign pg_addr = final_addr + {29'h0,(ASIZE[1] & ASIZE[0]),ASIZE[1],(ASIZE[1] | ASIZE[0])};\r
+\talways @(posedge BCLK) if (init_acc) pg_areg <= pg_addr[31:12];\r
+\tassign pg_test = (final_addr[12] != pg_addr[12]) & ~OP_RMW;\t// At RMW no Test necessary\r
+\t\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) pg_op <= 1'b0;\r
+\t\t  else\r
+\t\t\tpg_op <= init_acc ? (WRITE & ~RWVAL_1 & pg_test) : (pg_op & ~acc_pass & ~acc_err);\r
+\t\t\t\r
+\talways @(posedge BCLK) do_wr <= pg_op & ZTEST & acc_pass;\t// All ok, Page exists => continue\r
+\t\t\t\t\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) READ_OUT <= 1'b0;\r
+\t\t  else\r
+\t\t\tREAD_OUT  <= init_acc ? (READ & ~RWVAL_1) : (READ_OUT  & ~acc_ende & ~acc_err);\t\r
+\t\t\t\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) write_reg <= 1'b0;\r
+\t\t  else\t\t\t\t\t\t\t\t\t\t\t\t\t\t \r
+\t\t\twrite_reg <= (init_acc ? (WRITE & ~RWVAL_1 & ~pg_test) : (write_reg & ~acc_ende & ~acc_err & ~FPU_TRAP)) | do_wr;\r
+\t\t\t\t\t\t \r
+\tassign WRITE_OUT = write_reg & ~FPU_TRAP;\r
+\r
+\t// Special case for RDVAL and WRVAL\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) ZTEST <= 1'b0;\r
+\t\t  else\r
+\t\t\tZTEST <= pg_op ? (~ZTEST | (~acc_pass & ~acc_err)) : (init_acc ? RWVAL_1  : (ZTEST  & ~acc_ende & ~acc_err));\r
+\t\t\t\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) RMW <= 1'b0;\r
+\t\t  else\r
+\t\t\tRMW <= init_acc ? (OP_RMW & PHASE_17) : (RMW  & ~acc_ende & ~acc_err);\r
+\t\t\t\r
+\t// Special case : first MSD access by aligned QWORD READ\r
+\tassign qw_align = (final_addr[2:0] == 3'b000) & READ & (ASIZE == 2'b11);\r
+\t\r
+\talways @(posedge BCLK) if (init_acc) qwa_flag <= qw_align;\r
+\t\r
+\talways @(posedge BCLK or negedge BRESET)\t// central flag that shows the ADDR_UNIT is busy\r
+\t\tif (!BRESET) acc_run <= 1'b0;\r
+\t\t  else\r
+\t\t\tacc_run <= init_acc | (acc_run & ~acc_ende & ~acc_err & ~FPU_TRAP);\r
+\t\r
+\talways @(posedge BCLK) if (init_acc) SIZE <= ASIZE;\r
+\r
+\tassign inc_pack = (PACKET[1:0] == 2'b00) ? 2'b10 : {(SIZE[1] ^ SIZE[0]),(SIZE[1] & SIZE[0])};\r
+\t\r
+\t// Counter for data packets 1 to 3 : special case aligned QWORD : only 2 packets. Additionally start address in bits 1 und 0.\r
+\t// special coding (00) -> [01] -> (10) , [01] optional by QWORD and (10) shows always the end\r
+\talways @(posedge BCLK)\r
+\t\tif (init_acc) PACKET <= {2'b00,final_addr[1:0]};\r
+\t\t  else\r
+\t\t\tif (acc_ok) PACKET <= PACKET + {inc_pack,2'b00};\r
+\t\r
+\t// This signal is the End signal for the ADDR_UNIT internally.\r
+\talways @(SIZE or PACKET or acc_ok)\r
+\t\tcasex ({SIZE,PACKET[3],PACKET[1:0]})\r
+\t\t  5'b00_x_xx : acc_ende = acc_ok;\t// Byte\r
+\t\t  5'b01_0_0x : acc_ende = acc_ok;\t// Word\t\t1 packet\r
+\t\t  5'b01_0_10 : acc_ende = acc_ok;\t//\t\t\t1 packet\r
+\t\t  5'b01_1_xx : acc_ende = acc_ok;\t//\t\t\t2 packets\r
+\t\t  5'b10_0_00 : acc_ende = acc_ok;\t// DWord\t1 packet\r
+\t\t  5'b10_1_xx : acc_ende = acc_ok;\t//\t\t\t2 packets\r
+\t\t  5'b11_1_xx : acc_ende = acc_ok;\t// QWord\tat least 2 packets\r
+\t\t  default    : acc_ende = 1'b0;\r
+\t\tendcase\r
+\t\t\r
+\tassign in_page = (vadr_reg[11:3] != 9'h1FF);\t// Access inside a page ? During WRITE address is increasing : 1. LSD 2. MSD\r
+\t\r
+\talways @(SIZE or vadr_reg or in_page or PACKET)\r
+\t\tcasex (SIZE)\r
+\t\t  2'b01 : frueh_ok = (vadr_reg[3:2] != 2'b11);\t//Word\r
+\t\t  2'b10 : frueh_ok = (vadr_reg[3:2] != 2'b11);\t//DWord\r
+\t\t  2'b11 : frueh_ok = (PACKET[1:0] == 2'b00) ? (~vadr_reg[3] | ~vadr_reg[2]) : ((PACKET[3:2] == 2'b01) & (vadr_reg[3:2] != 2'b11));\r
+\t\tdefault : frueh_ok = 1'b1;\t\t\t\t\t\t// Byte don't case\r
+\t\tendcase\r
+\t\t  \r
+\tassign all_ok = SIZE[1] ? (PACKET[1:0] == 2'b00) : (PACKET[1:0] != 2'b11);\t// for DWord : Word\r
+\t\r
+\talways @(SIZE or READ_OUT or frueh_ok or PACKET or all_ok or io_acc or acc_ok or qwa_flag or io_rdy or ca_hit)\r
+\t\tcasex ({SIZE,READ_OUT,frueh_ok,PACKET[3],io_acc,all_ok})\r
+\t\t  7'b00_xxxx_x : acc_step = acc_ok;\t// Byte, all ok\r
+\t\t//\r
+\t\t  7'b01_xxxx_1 : acc_step = acc_ok;\t// Word : \taligned access , only 1 packet\r
+\t\t  7'b01_1x1x_0 : acc_step = acc_ok;\t//\t\t\tREAD must wait for all data\r
+\t\t  7'b01_0x1x_0 : acc_step = acc_ok;\t//\t\t\tWRITE Adr. ist not perfect and waits for last packet\r
+\t\t  7'b01_0100_0 : acc_step = acc_ok;\t//\t\t\tWRITE Adr. perfect - acc_step after 1. packet\r
+\t\t//\r
+\t\t  7'b10_xxxx_1 : acc_step = acc_ok;\t// DWord : \taligned access , only 1 packet\r
+\t\t  7'b10_1x1x_0 : acc_step = acc_ok;\t//\t\t\tREAD must wait for all data\r
+\t\t  7'b10_0x1x_0 : acc_step = acc_ok;\t//\t\t\tWRITE Adr. ist not perfect and waits for last packet\r
+\t\t  7'b10_0100_0 : acc_step = acc_ok;\t//\t\t\tWRITE Adr. perfect - acc_step after 1. packet      \r
+\t\t// fast QWord READ : there would be a 2. acc_step if not ~PACK... \r
+\t\t  7'b11_1xxx_x : acc_step = acc_ok & ( (qwa_flag & ~io_rdy & ca_hit) ? ~PACKET[3] : PACKET[3] );\r
+\t\t  7'b11_0x1x_x : acc_step = acc_ok;\r
+\t\t  7'b11_0100_x : acc_step = acc_ok;\t//\t\t\tWRITE Adr. perfect - acc_step after 1. packet if not io_acc\r
+\t\t  default      : acc_step = 1'b0;\r
+\t\tendcase\r
+\t\r
+\t// There is a 2. acc_step if packet (10) - this must be suppressed\r
+\talways @(posedge BCLK or negedge BRESET)\r
+\t\tif (!BRESET) no_done <= 1'b0;\r
+\t\t  else no_done <= (~acc_ende & acc_step) | (no_done & ~(acc_run & acc_ende));\r
+\t\t  \r
+\t// The final DONE Multiplexer\r
+\tassign ACC_DONE = acc_run ? (acc_step & ~no_done) : ea_ok;\r
+\r
+\t// Bugfix of 7.October 2015\r
+\talways @(posedge BCLK) QWATWO <= acc_run & acc_ok & qwa_flag & ~io_rdy & ca_hit & ~PACKET[3] & (SIZE == 2'b11) & READ_OUT & ~no_done;\r
+\r
+\talways @(posedge BCLK) reg_out_i <= ~acc_step & BRESET & ((qwa_flag & (io_rdy | ~ca_hit) & acc_ok) | reg_out_i);\r
+\t\r
+\talways @(posedge BCLK) io_rdy  <= IO_READY & (WRITE_OUT | READ_OUT);\r
+\t\r
+\talways @(posedge BCLK) next_reg <= (acc_step & ~qwa_flag) & (SIZE == 2'b11);\r
+\tassign REG_OUT = reg_out_i | next_reg;\r
+\t\r
+endmodule\r
+"
+"/*
+ *  Fetch & Decode module for Zet
+ *  Copyright (C) 2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+`timescale 1ns/10ps
+
+`include ""defines.v""
+
+module zet_fetch (
+    input clk,
+    input rst,
+
+    // to decode
+    output     [7:0] opcode,
+    output     [7:0] modrm,
+    output           rep,
+    output           exec_st,
+    output           ld_base,
+    output reg [2:0] sop_l,
+
+    // from decode
+    input need_modrm,
+    input need_off,
+    input need_imm,
+    input off_size,
+    input imm_size,
+    input ext_int,
+    input end_seq,
+
+    // to microcode
+    output reg [15:0] off_l,
+    output reg [15:0] imm_l,
+
+    // from microcode
+    input [5:0] ftype,
+
+    // to exec
+    output [15:0] imm_f,
+
+    input [15:0] cs,
+    input [15:0] ip,
+    input of,
+    input zf,
+    input cx_zero,
+    input [15:0] data,
+    output [19:0] pc,
+    output bytefetch,
+    input  block,
+    input  div_exc,
+    input  tflm,
+    output wr_ip0,
+    input  intr,
+    input  iflm,
+    input  nmir,
+    input  iflss,
+    
+    output use_eintp
+  );
+
+  // Registers, nets and parameters
+  parameter opcod_st = 3\'h0;
+  parameter modrm_st = 3\'h1;
+  parameter offse_st = 3\'h2;
+  parameter immed_st = 3\'h3;
+  parameter execu_st = 3\'h4;
+
+  reg  [2:0] state;
+  wire [2:0] next_state;
+
+  wire prefix, repz_pr, sovr_pr, lock_pr;
+  wire next_in_opco, next_in_exec;
+
+  reg [7:0] opcode_l, modrm_l;
+  reg [1:0] pref_l;
+  reg       lock_l;
+
+  // Module instantiation
+  zet_next_or_not next_or_not(pref_l, opcode[7:1], cx_zero, zf, ext_int, next_in_opco,
+                  next_in_exec, use_eintp);
+  zet_nstate nstate (state, prefix, need_modrm, need_off, need_imm, end_seq,
+             ftype, of, next_in_opco, next_in_exec, block, div_exc,
+             tflm, intr, iflm, nmir, iflss, next_state);
+
+  // Assignments
+  assign pc = (cs << 4) + ip;
+
+  assign opcode = (state == opcod_st) ? data[7:0] : opcode_l;
+  assign modrm  = (state == modrm_st) ? data[7:0] : modrm_l;
+  assign bytefetch = (state == offse_st) ? ~off_size
+                   : ((state == immed_st) ? ~imm_size : 1\'b1);
+  assign exec_st = (state == execu_st);
+  assign imm_f = ((state == offse_st) & off_size
+                | (state == immed_st) & imm_size) ? 16\'d2
+               : 16\'d1;
+  assign wr_ip0 = (state == opcod_st) && !pref_l[1] && !sop_l[2] && !lock_l;
+
+  assign sovr_pr = (opcode[7:5]==3\'b001 && opcode[2:0]==3\'b110);
+  assign repz_pr = (opcode[7:1]==7\'b1111_001);
+  assign lock_pr = (opcode[7:0]==8\'b1111_0000);
+  assign prefix  = sovr_pr || repz_pr || lock_pr;
+  assign ld_base = (next_state == execu_st);
+  assign rep     = pref_l[1];
+
+  // Behaviour
+  always @(posedge clk)
+    if (rst)
+      begin
+        state <= execu_st;
+        opcode_l <= `OP_NOP;
+      end
+    else if (!block)
+      case (next_state)
+        default:  // opcode or prefix
+          begin
+            case (state)
+              opcod_st:
+                begin // There has been a prefix
+                  pref_l <= repz_pr ? { 1\'b1, opcode[0] }
+                          // clear prefixes on next instr
+                          : next_in_opco ? 2\'b0 : pref_l;
+                  sop_l  <= sovr_pr ? { 1\'b1, opcode[4:3] }
+                          // clear prefixes on next instr
+                          : next_in_opco ? 3\'b0 : sop_l;
+                  lock_l <= lock_pr ? 1\'b1
+                          // clear prefixes on next instr
+                          : next_in_opco ? 1\'b0 : lock_l;
+                end
+              default: begin pref_l <= 2\'b0; sop_l <= 3\'b0; lock_l <= 1\'b0; end
+            endcase
+            state <= opcod_st;
+            off_l <= 16\'d0;
+            modrm_l <= 8\'b0000_0110;
+          end
+
+        modrm_st:  // modrm
+          begin
+            opcode_l  <= data[7:0];
+            state <= modrm_st;
+          end
+
+        offse_st:  // offset
+          begin
+            case (state)
+              opcod_st: opcode_l <= data[7:0];
+              default: modrm_l <= data[7:0];
+            endcase
+            state <= offse_st;
+          end
+
+        immed_st:  // immediate
+          begin
+            case (state)
+              opcod_st: opcode_l <= data[7:0];
+              modrm_st: modrm_l <= data[7:0];
+              default: off_l <= data;
+            endcase
+            state <= immed_st;
+          end
+
+        execu_st:  // execute
+          begin
+            case (state)
+              opcod_st: opcode_l <= data[7:0];
+              modrm_st: modrm_l <= data[7:0];
+              offse_st: off_l <= data;
+              immed_st: imm_l <= data;
+            endcase
+            state <= execu_st;
+          end
+      endcase
+endmodule
+"
+"// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+// This file is part of the M32632 project\r
+// http://opencores.org/project,m32632\r
+//\r
+// Filename: SP_FPU.v\r
+// Version:  1.0\r
+// Date:     30 May 2015\r
+//\r
+// Copyright (C) 2015 Udo Moeller\r
+// \r
+// This source file may be used and distributed without \r
+// restriction provided that this copyright statement is not \r
+// removed from the file and that any derivative work contains \r
+// the original copyright notice and the associated disclaimer.\r
+// \r
+// This source file is free software; you can redistribute it \r
+// and/or modify it under the terms of the GNU Lesser General \r
+// Public License as published by the Free Software Foundation;\r
+// either version 2.1 of the License, or (at your option) any \r
+// later version. \r
+// \r
+// This source is distributed in the hope that it will be \r
+// useful, but WITHOUT ANY WARRANTY; without even the implied \r
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR \r
+// PURPOSE. See the GNU Lesser General Public License for more \r
+// details. \r
+// \r
+// You should have received a copy of the GNU Lesser General \r
+// Public License along with this source; if not, download it \r
+// from http://www.opencores.org/lgpl.shtml \r
+// \r
+// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\tModules contained in this file:\r
+//\t1. ADDSUB\t\tAdder and Subtractor for 36 bit\r
+//\t2. SFPU_ADDSUB\tSingle Precision Floating Point Adder/Subtractor and Converter\r
+//\t3. SFPU_MUL\t\tSingle Precision Floating Point Multiplier\r
+//\t4. SP_FPU\t\tTop Level of Single Precision Floating Point Unit\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t1. ADDSUB\t\tAdder and Subtractor for 36 bit\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module ADDSUB (dataa, datab, add_sub, result);\r
+\r
+\tinput\t[35:0]\tdataa,datab;\r
+\tinput\t\t\tadd_sub;\t// 1 = Addition , 0 = Subtraction\r
+\toutput\t[35:0]\tresult;\r
+\t\r
+\tassign result = dataa + (add_sub ? datab : ~datab) + {35\'d0,~add_sub};\r
+\t\r
+endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t2. SFPU_ADDSUB\tSingle Precision Floating Point Adder/Subtractor and Converter\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module SFPU_ADDSUB ( SRC1, SRC2, NZEXP, BWD, SELECT, OUT, IOUT, CMPRES );\r
+\r
+\tinput\t[31:0]\tSRC1,SRC2;\t// Input data\r
+\tinput\t [2:1]\tNZEXP;\r
+\tinput\t [1:0]\tBWD;\t\t// size of integer\r
+\tinput\t [3:0]\tSELECT;\r
+\r
+\toutput\t[36:0]\tOUT;\t\t// the result\r
+\toutput\t[31:0]\tIOUT;\t\t// result of ROUNDFi/TRUNCFi/FLOORFi\r
+\toutput\t [1:0]\tCMPRES;\r
+\r
+\t// ++++++++++++++++++++++++++++++++++\r
+\t// MOViF : 1. step\r
+\t\r
+\treg  [31:8]\tmovdat;\r
+\twire [31:0]\tmovif;\r
+\r
+\talways @(BWD or SRC1)\r
+\t\tcasex({BWD,SRC1[15],SRC1[7]})\r
+\t\t  4\'b00x0 : movdat =  24\'h0000_00;\t\t\t\t// Byte\r
+\t\t  4\'b00x1 : movdat =  24\'hFFFF_FF;\r
+\t\t  4\'b010x : movdat = {16\'h0000,SRC1[15:8]};\t\t// Word\r
+\t\t  4\'b011x : movdat = {16\'hFFFF,SRC1[15:8]};\r
+\t\tdefault   : movdat = SRC1[31:8];\t\t\t\t// Double\r
+\t\tendcase\r
+\t\t\r
+\tassign movif = movdat[31] ? (32\'h0 - {movdat,SRC1[7:0]}) : {movdat,SRC1[7:0]};\r
+\t\t\t\t\t\t\t\t// -2^31 is kept\r
+\t\r
+\t// ROUNDFi/TRUNCFi/FLOORFi : 1. step\r
+\t\r
+\treg\t\t\tovflag,ovflag2;\r
+\twire [8:0]\trexdiff,rexo;\r
+\twire\t\trovfl,minint;\r
+\twire \t\tganzklein;\t// Flag for 0\r
+\t\r
+\tassign rexdiff = 9\'h09D - {1\'b0,SRC1[30:23]};\t// 4..0 is the right shift value\r
+\tassign rovfl = (ovflag | ovflag2) & (SELECT[1:0] == 2\'b11) & ~minint;\r
+\tassign ganzklein = (~rexdiff[8]\t& (rexdiff[7:5] != 3\'b000));\t// 0 is implicit via SRC1[30:23]=0\r
+\t\r
+\t// Detection of Overflow\r
+\tassign rexo = ({1\'b0,SRC1[30:23]} - {8\'h3F,~BWD[1]});\t// subtract B/W = 7F , D = 7E\r
+\t\r
+\talways @(BWD or rexo)\r
+\t\tcasex (BWD)\r
+\t\t  2\'b00 : ovflag = (~rexo[8] & (rexo[7:3] != 5\'h0));\t// Exponent 0..7 because of -128.4 => -128\r
+\t\t  2\'b01 : ovflag = (~rexo[8] & (rexo[7:4] != 4\'h0));\t// Exponent 0..15 because of -128.4 => -128\r
+\t\tdefault : ovflag = (~rexo[8] & (rexo[7:5] != 3\'h0));\t// Exponent only 0..30 \r
+\t\tendcase\r
+\t\t\r
+\tassign minint = (SRC1 == 32\'hCF00_0000) & BWD[1];\t// detection of -2^31\r
+\t\r
+\t// ++++++++++++++++++++++++++++++++++\r
+\t// ADD/SUB : 1. step : which operand ist bigger ? if required exchange\r
+\t// SUB/CMP : SRC2 - SRC1\r
+\t\r
+\twire  [8:0]\texdiff;\r
+\twire [23:0]\tmadiff;\r
+\twire\t\tswitch,sign,sign1,sign2;\r
+\twire\t\tvariante;\r
+\twire\t\tvorz,addflag;\r
+\twire [35:0]\tresult_sw,result_nosw;\r
+\twire [24:0] value1,value2;\r
+\t\r
+\twire [35:0] result;\r
+\t\r
+\tassign exdiff = {1\'b0,SRC2[30:23]} - {1\'b0,SRC1[30:23]};\t// Difference of Exponents\r
+\tassign madiff = {1\'b0,SRC2[22:0]}  - {1\'b0,SRC1[22:0]};\t\t// Difference of Mantissas\r
+\t\r
+\t// if exdiff = 0 the shifter to the right is not needed ! \r
+\tassign variante = (exdiff[8:1] == 8\'h00) | (exdiff == 9\'h1FF) | SELECT[1];\t// MUX at the end, ROUND/TRUNC/MOViF uses case 1\r
+\t\r
+// ++++++++++++++++++++++++++  1. case works on MOViF  +++++++++++++++++++++++++++++++++++++++\r
+\r
+\tassign switch = exdiff[8] | ((exdiff[7:0] == 8\'h0) & madiff[23]);\t// exchange ?\r
+\r
+\tassign value1 = exdiff[0] ? {1\'b0,NZEXP[1],SRC1[22:0]} : {NZEXP[1],SRC1[22:0],1\'b0};\r
+\tassign value2 = exdiff[0] ? {1\'b0,NZEXP[2],SRC2[22:0]} : {NZEXP[2],SRC2[22:0],1\'b0};\r
+\t\r
+\t// The Subtraction needs 3 Guard-Bits after LSB for rounding ! 36 Bit wide\r
+\t//\t\t\t\t\t\t\t\t\t\t\t\t1\r
+\tADDSUB\taddsub_nosw\t(.dataa({1\'b0,SRC2[30:23],NZEXP[2],SRC2[22:0],3\'b000}),\t\r
+\t\t\t\t\t\t .datab({9\'h0,value1,2\'b0}), .add_sub(addflag), \r
+\t\t\t\t\t\t .result(result_nosw) );\r
+\r
+\tADDSUB\taddsub_sw\t(.dataa({1\'b0,SRC1[30:23],NZEXP[1],SRC1[22:0],3\'b000}),\t\r
+\t\t\t\t\t\t .datab({9\'h0,value2,2\'b0}), .add_sub(addflag), \r
+\t\t\t\t\t\t .result(result_sw) );\r
+\r
+\tassign result = switch ? result_sw : result_nosw;\r
+\t\r
+\t//\tSRC2   SRC1\t: switch = 0\t\tSRC2   SRC1 : switch = 1\r
+\t//\t  5  +   3  : +(5 + 3) =  8\t\t  3  +   5  : +(5 + 3) =  8\t\tSELECT[0] = 0\r
+\t//\t  5  + (-3) : +(5 - 3) =  2\t\t  3  + (-5) : -(5 - 3) = -2\r
+\t//\t(-5) +   3  : -(5 - 3) = -2\t\t(-3) +   5  : +(5 - 3) =  2\r
+\t//\t(-5) + (-3) : -(5 + 3) = -8\t\t(-3) + (-5) : -(5 + 3) = -8\r
+\t//\t  5  -   3  : +(5 - 3) =  2\t\t  3  -   5  : -(5 - 3) = -2\t\tSELECT[0] = 1\r
+\t//\t  5  - (-3) : +(5 + 3) =  8\t\t  3  - (-5) : +(5 + 3) =  8\r
+\t//\t(-5) -   3  : -(5 + 3) = -8\t\t(-3) -   5  : -(5 + 3) = -8\r
+\t//\t(-5) - (-3) : -(5 - 3) = -2\t\t(-3) - (-5) : +(5 - 3) =  2\r
+\t\r
+\tassign sign1 = SRC1[31];\r
+\tassign sign2 = SRC2[31];\r
+\t\r
+\tassign vorz    = switch ? (SELECT[0] ^ sign1) : sign2;\r
+\tassign addflag = ~(SELECT[0] ^ (sign1 ^ sign2));\r
+\r
+\t// CMPF : 1. step : what happend if Invalid Operand occurs - no Flag update !\r
+\t\r
+\tassign CMPRES[1] = ~CMPRES[0] & (switch ? ~sign1 : sign2);\t\t// see table above : N-Bit=1 if SRC1 > SRC2\r
+\tassign CMPRES[0] = (SRC1 == SRC2) | (~NZEXP[2] & ~NZEXP[1]);\t// Z-Bit : SRC1=SRC2, +0.0 = -0.0\r
+\t\r
+\t// ++++++++++++++++++++++++++++++++++\r
+\t// ADD/SUB : 3. step : prepare of Barrelshifter Left\r
+\t\r
+\twire [31:0] blshift;\r
+\twire  [9:0]\tshiftl;\r
+\twire\t\tshift_16;\r
+\twire [33:0] add_q;\r
+\twire [31:0]\tmuxsrc2;\r
+\twire  [1:0] inex;\r
+\t\r
+\tassign blshift = SELECT[1] ? movif : {result[26:0],5\'h00};\t// Feeding of MOViF\r
+\r
+\tassign shiftl = SELECT[1] ? 10\'h09E : {1\'b0,result[35:27]};\t// MOViF\r
+\r
+\tassign shift_16 = (blshift[31:16] == 16\'h0000);\r
+\r
+\t// In case of ADD the result bypasses the Barrelshifter left\r
+\tassign add_q = (muxsrc2[24] != result[27]) ? {result[35:3],(result[2:0] != 3\'b000)}\r
+\t\t\t\t\t\t\t\t\t\t\t   : {result[35:27],result[25:2],(result[1:0] != 2\'b00)} ;\r
+\t\r
+\t// ++++++++++++++++++++++++++++++++++\r
+\t// ADD/SUB : 4. step : Barrelshifter left for SUB and MOViF :\r
+\t\r
+\twire\t\tshift_8,shift_4,shift_2,shift_1,zero;\r
+\twire  [1:0] lsb_bl;\r
+\twire [31:0]\tblshifta,blshiftb,blshiftc,blshiftd,blshifte;\r
+\twire  [9:0]\texpol;\r
+\twire [36:0] out_v1;\r
+\t\r
+\tassign blshifta = shift_16 ? {blshift[15:0],16\'h0000}\t: blshift;\r
+\tassign shift_8 = (blshifta[31:24] == 8\'h00);\r
+\tassign blshiftb = shift_8  ? {blshifta[23:0],8\'h00} \t: blshifta;\r
+\tassign shift_4 = (blshiftb[31:28] == 4\'h0);\r
+\tassign blshiftc = shift_4  ? {blshiftb[27:0],4\'h0} \t\t: blshiftb;\r
+\tassign shift_2 = (blshiftc[31:30] == 2\'b00);\r
+\tassign blshiftd = shift_2  ? {blshiftc[29:0],2\'b00} \t: blshiftc;\r
+\tassign shift_1 = ~blshiftd[31];\r
+\tassign blshifte = shift_1  ? {blshiftd[30:0],1\'b0} \t\t: blshiftd;\r
+\t\r
+\t// Overflow at ROUNDFi/TRUNCFi/FLOORFi via overflow in exponent shown, SELECT[1] is then 1 !\r
+\tassign expol = (shiftl - {5\'h00,shift_16,shift_8,shift_4,shift_2,shift_1}) | {1\'b0,rovfl,8\'h00};\r
+\t\t\r
+\t// Inexact at ROUNDFi/TRUNCFi/FLOORFi : evaluation for all one level higher\r
+\tassign lsb_bl = (SELECT[1:0] == 2\'b11) ? inex : {blshifte[7],(blshifte[6:0] != 7\'h00)};\r
+\t\r
+\tassign zero =  (~SELECT[1] & ~NZEXP[2] & ~NZEXP[1])\t\r
+\t\t\t\t | ((blshift == 32\'h0) & ((~addflag & ~SELECT[1]) | (SELECT[1:0] == 2\'b10)));\r
+\t\r
+\tassign sign = SELECT[1] ? movdat[31] : vorz;\r
+\t\r
+\tassign out_v1 = (addflag & ~SELECT[1]) ? {zero,sign,1\'b0,add_q}\r
+\t\t\t\t\t\t\t\t\t\t   : {zero,sign,expol,blshifte[30:8],lsb_bl};\r
+\t\r
+// +++++++++++++++++++++++++  2. case works on ROUND/TRUNC/FLOOR  ++++++++++++++++++++++++++++++++++\r
+\r
+\twire\t\tvswitch;\r
+\twire  [4:0]\tshift1,shift2;\r
+\twire  [8:0]\texdiff12;\r
+\twire [23:0]\tmuxsrc1;\r
+\twire [32:9]\tpipe1;\t// numbering special for Right Shifter\r
+\twire  [4:0]\tshift;\r
+\t\r
+// the difference between SRC1 and SRC2 is bigger/equal 4:1 => no Barrelshifter after ADDSUB neccessary\r
+\r
+\tassign vswitch = exdiff[8];\t// exchange ?\r
+\t\t\r
+\tassign shift1 = (exdiff[7:5] != 3\'h0) ? 5\'h1F : exdiff[4:0];\r
+\tassign exdiff12 = {1\'b0,SRC1[30:23]} - {1\'b0,SRC2[30:23]};\t// caclulate already\r
+\tassign shift2 = (exdiff12[7:5] != 3\'h0) ? 5\'h1F : exdiff12[4:0];\r
+\t\r
+\tassign muxsrc2 = vswitch ? {SRC1[30:23],1\'b1,SRC1[22:0]} : {SRC2[30:23],1\'b1,SRC2[22:0]};\t// Including exponent\r
+\tassign muxsrc1 = vswitch ? {NZEXP[2],SRC2[22:0]} : {NZEXP[1],SRC1[22:0]};\r
+\r
+\tassign pipe1 = SELECT[1] ? (ganzklein ? 24\'h0 : {NZEXP[1],SRC1[22:0]}) : muxsrc1;\t// Feeding in R.T.F.\r
+\t\t\r
+\tassign shift = SELECT[1] ? rexdiff[4:0] : (vswitch ? shift2 : shift1);\r
+\t\t\r
+\t// ++++++++++++++++++++++++++++++++++\r
+\t// ADD/SUB + ROUND/TRUNC/FLOOR : 2. step : Barrelshifter to right -->\r
+\t\r
+\twire [32:0] brshifta,brshiftb,brshiftc,brshiftd;\r
+\twire [32:0] brshifte;\t// last stage\r
+\t\r
+\t// 33322222222221111111111\r
+\t// 2109876543210987654321098765432-10\r
+\t// 1VVVVVVVVVVVVVVVVVVVVVVV0000000-00\t// last 2 Bit for rounding\r
+\t\r
+\tassign brshifta = shift[4] ? {16\'h0,pipe1[32:17],  (pipe1[16:9]   != 8\'h00)}  : {pipe1,9\'h0};\r
+\tassign brshiftb = shift[3] ? { 8\'h0,brshifta[32:9],(brshifta[8:0] != 9\'h000)} : brshifta;\r
+\tassign brshiftc = shift[2] ? { 4\'h0,brshiftb[32:5],(brshiftb[4:0] != 5\'h00)}  : brshiftb;\r
+\tassign brshiftd = shift[1] ? { 2\'h0,brshiftc[32:3],(brshiftc[2:0] != 3\'h0)}   : brshiftc;\r
+\tassign brshifte = shift[0] ? { 1\'b0,brshiftd[32:2],(brshiftd[1:0] != 2\'h0)}   : brshiftd;\r
+\t\r
+\t// ++++++++++++++++++++++++++++++++++\r
+\t// ROUNDFi/TRUNCFi/FLOORFi : 3. step : round to integer\r
+\t\r
+\treg\t\t\tcar_ry;\r
+\twire [30:0] compl;\r
+\twire [31:0] iadder;\r
+\t\r
+\tassign inex = brshifte[1:0];\t\t// Inexact-Flag-Data via multiplexer at the end\r
+\t\r
+\talways @(SELECT or sign1 or brshifte or inex or ganzklein)\r
+\t\tcasex (SELECT[3:2])\r
+\t\t    2\'b00 : car_ry = sign1 ^ ((brshifte[2:0] == 3\'b110) | (inex == 2\'b11));\t// ROUNDLi\r
+\t\t    2\'b1x : car_ry = sign1 ? (~ganzklein & (inex == 2\'b00)) : 1\'b0;\t// +numbers like TRUNCLi, -numbers round to ""-infinity""\r
+\t\t  default : car_ry = sign1;\t// TRUNCLi , simple cut\r
+\t\tendcase\r
+\r
+\tassign compl  = sign1 ? ~brshifte[32:2] : brshifte[32:2];\r
+\t\r
+\tassign iadder = {sign1,compl} + {31\'h0,car_ry};\r
+\t\r
+\tassign IOUT = minint ? 32\'h8000_0000 : iadder;\r
+\r
+\talways @(iadder or BWD or sign1)\t// special overflow detection i.e. -129 bis -255 bei Byte\r
+\t\tcasex (BWD)\t\t\t\t\t\t// or 127.9 -> 128 = Fehler !\r
+\t\t  2\'b00 : ovflag2 = (iadder[8]  != iadder[7]);\t// Byte\r
+\t\t  2\'b01 : ovflag2 = (iadder[16] != iadder[15]);\t// Word\r
+\t\tdefault : ovflag2 = 1\'b0;\r
+\t\tendcase\r
+\t\t\r
+\t// ++++++++++++++++++++++++++++++++++\r
+\t// only ADD/SUB : 3. step : Add or Subtract\r
+\t// the modul ADDSUB integrates the carry from the mantissa : 35 Bit\r
+\t\r
+\twire\t\tlsb;\r
+\twire [35:0]\tvresult;\r
+\twire  [7:0]\teminus1;\r
+\twire [33:0] vadd_q,vsub_q;\r
+\twire\t\tvzero;\r
+\twire [36:0] out_v0;\r
+\t\r
+\tassign lsb = (brshifte[6:0] != 7\'h00);\r
+\r
+\t// Adder-Definition : ""0""(8 Bit Exponent)""1""(23 Bit Mantissa)""000""\r
+\r
+\tADDSUB\taddsub_v\t(.dataa({1\'b0,muxsrc2,3\'b000}),\r
+\t\t\t\t\t\t .datab({9\'h0,brshifte[32:7],lsb}), .add_sub(addflag), \r
+\t\t\t\t\t\t .result(vresult) );\r
+\t\t\t\t\t\t\r
+\tassign eminus1 = muxsrc2[31:24] - 8\'h01;\t// a greater Underflow can not exist, because minimal Exponent = 0..01\r
+\r
+\t// Case ADD : Bit 23 : LSB of exponent\r
+\tassign vadd_q = (muxsrc2[24] != vresult[27]) ? {vresult[35:3],(vresult[2:0] != 3\'b000)}\r
+\t\t\t\t\t\t\t\t\t\t\t\t : {vresult[35:27],vresult[25:2],(vresult[1:0] != 2\'b00)} ;\r
+\r
+\t// Case SUB : Bit 26 : ""hidden"" MSB of mantissa\r
+\tassign vsub_q = vresult[26] ? {vresult[35:27],     vresult[25:2],(vresult[1:0] != 2\'b00)}\t// like the vadd_q ""0"" case\r
+\t\t\t\t\t\t\t    : {vresult[35],eminus1,vresult[24:0]} ;\r
+\t\t\t\t\t\t\t   \r
+\t// SELECT[1] has here no meaning\r
+\tassign vzero = (vresult[26:0] == 27\'h0) & ~addflag;\t// only if ""-"" can be the result 0\r
+\r
+\tassign out_v0 = addflag ? {vzero,vorz,1\'b0,vadd_q}\r
+\t\t\t\t\t\t\t: {vzero,vorz,1\'b0,vsub_q} ;\r
+\t\r
+\tassign OUT = variante ? out_v1 : out_v0;\t// Last multiplexer\r
+\t\r
+endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t3. SFPU_MUL\t\tSingle Precision Floating Point Multiplier\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module SFPU_MUL ( SRC1, SRC2, MRESULT, NZEXP, OUT);\r
+\r
+\tinput\t[31:0]\tSRC1,SRC2;\t// only exponent of input data used\r
+\tinput\t[47:0]\tMRESULT;\r
+\tinput\t [2:1]\tNZEXP;\t\t// Flags of input data\r
+\t\r
+\toutput\t[36:0]\tOUT;\t\t// The result\r
+\r
+\twire  [9:0] exponent,expoh,expol;\r
+\twire  [1:0] restlow,resthigh;\r
+\twire \t\tzero,sign,orlow;\r
+\t\t\r
+\tassign zero = \t~NZEXP[2] | ~NZEXP[1];\t// one of both NULL -> NULL is the result\r
+\tassign sign = \t(SRC1[31] ^ SRC2[31]) & ~zero;\r
+\tassign orlow = \t(MRESULT[21:0] != 22\'b0);\r
+\t\r
+\tassign restlow  = {MRESULT[22],orlow};\r
+\tassign resthigh = {MRESULT[23],(MRESULT[22] | orlow)};\r
+\t\r
+\tassign exponent = {2\'b00,SRC1[30:23]} + {2\'b00,SRC2[30:23]};\r
+\tassign expoh    = exponent - 10\'h07E;\r
+\tassign expol\t= exponent - 10\'h07F;\t// for MSB if MRESULT=0\r
+\t\r
+\tassign OUT = MRESULT[47] ? {zero,sign,expoh,MRESULT[46:24],resthigh}\r
+\t\t\t\t\t\t\t : {zero,sign,expol,MRESULT[45:23],restlow};\r
+\t\r
+endmodule\r
+\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+//\r
+//\t4. SP_FPU\t\tTop Level of Single Precision Floating Point Unit\r
+//\r
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\r
+module SP_FPU (BCLK, OPCODE, SRC1, SRC2, FSR, MRESULT, BWD, FL, FP_OUT, I_OUT, TT_SP, SP_CMP, SP_MUX, LD_FSR, UP_SP);\r
+\r
+\tinput\t\t\tBCLK;\t\t// is not used !\r
+\tinput\t [7:0]\tOPCODE;\t\r
+\tinput\t[31:0]\tSRC1,SRC2;\t// Input data\r
+\tinput\t [8:3]\tFSR;\t\t// Floating Point Status Register\r
+\tinput\t[47:0]\tMRESULT;\t// Multiplier result\r
+\tinput\t [1:0]\tBWD;\t\t// Size of integer\r
+\tinput\t\t\tFL;\r
+\r
+\toutput\t[31:0]\tFP_OUT,I_OUT;\t// The results\r
+\toutput\t [4:0]\tTT_SP;\t\t// Trap-Type\r
+\toutput\t [2:0]\tSP_CMP;\t\t// CMPF result\r
+\toutput\t\t\tSP_MUX,LD_FSR,UP_SP;\r
+\r
+\treg\t\t [2:0]\ttt;\r
+\treg\t\t [3:0]\tselect;\r
+\treg\t\t\t\tcar_ry;\r
+\r
+\twire\t[36:0]\tmulout,addout,fpout;\r
+\twire\t [2:1]\tnzexp;\r
+\twire\t[34:2]\trund;\t\t// Indexnumbers like xxxout\r
+\twire\t\t\toverflow,underflow,inexact;\r
+\twire\t\t\top_cmp;\r
+\twire\t\t\tnan,nan_1,nan_2;\r
+\t\r
+\t// Control of datapath \r
+\r
+\talways @(OPCODE)\r
+\t\tcasex (OPCODE)\r
+\t\t  8\'b1011_0000 : select = 4\'b1000;\t// 0 0 0 :\tADDF\tShifter are reused\r
+\t\t  8\'b1011_0100 : select = 4\'b1001;\t// 0 0 1 :\tSUBF\r
+\t\t  8\'b1001_000x : select = 4\'b1010;\t// 0 1 0 :\tMOViF\r
+\t\t  8\'b1001_100x : select = 4\'b1011;\t// 0 1 1 :\tROUNDFi\r
+\t\t  8\'b1001_101x : select = 4\'b1011;\t// 0 1 1 :\tTRUNCFi\r
+\t\t  8\'b1001_111x : select = 4\'b1011;\t// 0 1 1 :\tFLOORFi\r
+\t\t  8\'b1011_0010 : select = 4\'b1001;\t// 0 0 1 :\tCMPF\r
+\t\t  8\'b1011_1100 : select = 4\'b1100;\t// 1 x x :\tMULF\r
+\t\t  default      : select = 4\'b0;\r
+\t\tendcase\r
+\r
+\tassign SP_MUX = select[3] & (select[1:0] != 2\'b11) & FL;\t// Output multiplexer\r
+\t\r
+\tassign LD_FSR = (OPCODE[7:4] == 4\'h9) & (OPCODE[3:1] == 3\'b001);\t// LFSR does only Double (according datasheet NS32016)\r
+\tassign UP_SP  = select[3] & FL;\t\t\t\t// All FPU opcodes of SP_FPU\r
+\tassign op_cmp = (OPCODE == 8\'hB2) & FL;\r
+\t\r
+\t// SRCFLAGS\r
+\t\r
+\tassign nzexp[2]\t= (SRC2[30:23] != 8\'d0);\t\t// only exponent 0 ,denormalized Number => NAN !\r
+\tassign nzexp[1] = (SRC1[30:23] != 8\'d0);\t\t// only exponent 0 ,denormalized Number => NAN !\r
+\tassign nan_2 \t= (SRC2[30:23] == 8\'hFF) | (~nzexp[2] & (SRC2[22:0] != 23\'d0));\t// NAN\r
+\tassign nan_1 \t= (SRC1[30:23] == 8\'hFF) | (~nzexp[1] & (SRC1[22:0] != 23\'d0));\t// NAN\r
+\r
+\tassign nan = (select[1:0] == 2\'b11) ? nan_1 : (~select[1] & (nan_2 | nan_1));\r
+\t\r
+\t// 001 : ADDF,... + 011 : CMPF\r
+\tSFPU_ADDSUB IADDSUB\t( .SRC1(SRC1), .SRC2(SRC2), .NZEXP(nzexp), .BWD(BWD),\r
+\t\t\t\t\t\t  .SELECT({OPCODE[2:1],select[1:0]}), .OUT(addout), .IOUT(I_OUT), .CMPRES(SP_CMP[1:0]) );\r
+\t\t\t\t\t\r
+\t// 100 : MULF\r
+\tSFPU_MUL IMUL ( .SRC1(SRC1), .SRC2(SRC2), .MRESULT(MRESULT), .OUT(mulout), .NZEXP(nzexp) );\r
+\t\t\t\t\t\r
+\t// FP - Pfad : selection of result and rounding :\r
+\r
+\tassign fpout = (OPCODE[5] & OPCODE[3]) ? mulout : addout;\r
+\t\r
+\talways @(FSR or fpout)\t// calculate Carry according rounding mode, fpout[35] = sign bit\r
+\t\tcasex (FSR[8:7])\r
+\t\t  2\'b00 : car_ry = ((fpout[1:0] == 2\'b10) & fpout[2]) | (fpout[1:0] == 2\'b11);\t// round to nearest\r
+\t\t  2\'b10 : car_ry = ~fpout[35] & (fpout[1:0] != 2\'b00);\t// round to positiv infinity\r
+\t\t  2\'b11 : car_ry =  fpout[35] & (fpout[1:0] != 2\'b00);\t// round to negativ infinity\r
+\t\tdefault : car_ry = 1\'b0;\t\t\t\t\t\t\t\t// round to zero\r
+\t\tendcase\r
+\r
+\tassign rund = {fpout[34:2]} + {32\'h0,car_ry};\r
+\t\r
+\t// Detection of Overflow, Underflow and Inexact : epxonent is [34:25] = 10 Bits\r
+\tassign overflow  = ~rund[34] & (rund[33] | (rund[32:25] == 8\'hFF));\r
+\tassign underflow = (rund[34] | (rund[33:25] == 9\'h0)) & ~fpout[36];\t// Zero-Flag\r
+\tassign inexact   = (fpout[1:0] != 2\'b00);\r
+\t\r
+\t// CMPF can have no other error except NAN \r
+\talways @(nan or op_cmp or overflow or underflow or inexact or FSR)\r
+\t\tcasex ({nan,op_cmp,overflow,FSR[3],underflow,FSR[5],inexact})\r
+\t\t\t7\'b1xxxxxx : tt = 3\'b101;\t// Invalid operation\r
+\t\t\t7\'b001xxxx : tt = 3\'b010;\t// Overflow\r
+\t\t\t7\'b00011xx : tt = 3\'b001;\t// Underflow\r
+\t\t\t7\'b0000011 : tt = 3\'b110;\t// Inexact Result\r
+\t\t\tdefault\t   : tt = 3\'b000;\t// no error\r
+\t\tendcase\r
+\r
+\tassign TT_SP = {(inexact & ~op_cmp),(underflow & ~op_cmp),tt};\r
+\tassign SP_CMP[2] = nan;\t\r
+\t\r
+\t// Underflow Special case and force ZERO \r
+\tassign FP_OUT = (underflow | fpout[36]) ? 32\'d0 : {fpout[35],rund[32:2]};\r
+\t\r
+endmodule\r
+"
+"/*
+ *  Wishbone master interface module for Zet
+ *  Copyright (C) 2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+module zet_wb_master (
+    input             cpu_byte_o,
+    input             cpu_memop,
+    input             cpu_m_io,
+    input      [19:0] cpu_adr_o,
+    output reg        cpu_block,
+    output reg [15:0] cpu_dat_i,
+    input      [15:0] cpu_dat_o,
+    input             cpu_we_o,
+
+    input             wb_clk_i,
+    input             wb_rst_i,
+    input      [15:0] wb_dat_i,
+    output reg [15:0] wb_dat_o,
+    output reg [19:1] wb_adr_o,
+    output            wb_we_o,
+    output            wb_tga_o,
+    output reg [ 1:0] wb_sel_o,
+    output reg        wb_stb_o,
+    output            wb_cyc_o,
+    input             wb_ack_i
+  );
+
+  // Register and nets declarations
+  reg  [ 1:0] cs; // current state
+  reg  [ 1:0] ns; // next state
+  reg  [19:1] adr1; // next address (for unaligned acc)
+
+  wire        op; // in an operation
+  wire        odd_word; // unaligned word
+  wire        a0;  // address 0 pin
+  wire [15:0] blw; // low byte (sign extended)
+  wire [15:0] bhw; // high byte (sign extended)
+  wire [ 1:0] sel_o; // bus byte select
+
+  // Declare the symbolic names for states
+  localparam [1:0]
+    IDLE    = 2'd0,
+    stb1_hi = 2'd1,
+    stb2_hi = 2'd2,
+    bloc_lo = 2'd3;
+
+  // Assignments
+  assign op        = (cpu_memop | cpu_m_io);
+  assign odd_word  = (cpu_adr_o[0] & !cpu_byte_o);
+  assign a0        = cpu_adr_o[0];
+  assign blw       = { {8{wb_dat_i[7]}}, wb_dat_i[7:0] };
+  assign bhw       = { {8{wb_dat_i[15]}}, wb_dat_i[15:8] };
+  assign wb_we_o   = cpu_we_o;
+  assign wb_tga_o  = cpu_m_io;
+  assign sel_o     = a0 ? 2'b10 : (cpu_byte_o ? 2'b01 : 2'b11);
+  assign wb_cyc_o  = wb_stb_o;
+
+  // Behaviour
+  // cpu_dat_i
+  always @(posedge wb_clk_i)
+    cpu_dat_i <= cpu_we_o ? cpu_dat_i : ((cs == stb1_hi) ?
+                   (wb_ack_i ?
+                     (a0 ? bhw : (cpu_byte_o ? blw : wb_dat_i))
+                   : cpu_dat_i)
+                 : ((cs == stb2_hi && wb_ack_i) ?
+                     { wb_dat_i[7:0], cpu_dat_i[7:0] }
+                   : cpu_dat_i));
+
+  // adr1
+  always @(posedge wb_clk_i)
+    adr1 <= cpu_adr_o[19:1] + 1'b1;
+
+  // wb_adr_o
+  always @(posedge wb_clk_i)
+    wb_adr_o <= (ns==stb2_hi) ? adr1 : cpu_adr_o[19:1];
+
+  // wb_sel_o
+  always @(posedge wb_clk_i)
+    wb_sel_o <= (ns==stb1_hi) ? sel_o : 2'b01;
+
+  // wb_stb_o
+  always @(posedge wb_clk_i)
+    wb_stb_o <= (ns==stb1_hi || ns==stb2_hi);
+
+  // wb_dat_o
+  always @(posedge wb_clk_i)
+    wb_dat_o <= a0 ? { cpu_dat_o[7:0], cpu_dat_o[15:8] }
+                       : cpu_dat_o;
+
+  // cpu_block
+  always @(*)
+    case (cs)
+      IDLE:    cpu_block <= op;
+      default: cpu_block <= 1'b1;
+      bloc_lo: cpu_block <= wb_ack_i;
+    endcase
+
+  // state machine
+  // cs - current state
+  always @(posedge wb_clk_i)
+    cs <= wb_rst_i ? IDLE : ns;
+
+  // ns - next state
+  always @(*)
+    case (cs)
+      default: ns <= wb_ack_i ? IDLE : (op ? stb1_hi : IDLE);
+      stb1_hi: ns <= wb_ack_i ? (odd_word ? stb2_hi : bloc_lo) : stb1_hi;
+      stb2_hi: ns <= wb_ack_i ? bloc_lo : stb2_hi;
+      bloc_lo: ns <= wb_ack_i ? bloc_lo : IDLE;
+    endcase
+
+endmodule
+"
+"/*
+ *  1-bit 8-way multiplexor
+ *  Copyright (C) 2008-2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+module zet_mux8_1(sel, in0, in1, in2, in3, in4, in5, in6, in7, out);
+  input  [2:0]  sel;
+  input  in0, in1, in2, in3, in4, in5, in6, in7;
+  output out;
+
+  reg    out;
+
+  always @(sel or in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7)
+    case(sel)
+     3'd0:  out = in0;
+     3'd1:  out = in1;
+     3'd2:  out = in2;
+     3'd3:  out = in3;
+     3'd4:  out = in4;
+     3'd5:  out = in5;
+     3'd6:  out = in6;
+     3'd7:  out = in7;
+    endcase
+endmodule
+"
+"/*
+ *  Super Simple Priority Interrupt Controller
+ *  Copyright (C) 2010  Zeus Gomez Marmolejo <zeus@aluzina.org>
+ *  Copyright (C) 2010  Donna Polehn <dpolehn@verizon.net>
+ *
+ *  This file is part of the Zet processor. This processor is free
+ *  hardware; you can redistribute it and/or modify it under the terms of
+ *  the GNU General Public License as published by the Free Software
+ *  Foundation; either version 3, or (at your option) any later version.
+ *
+ *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ *  License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Zet; see the file COPYING. If not, see
+ *  <http://www.gnu.org/licenses/>.
+ */
+
+module simple_pic (
+    input             clk,
+    input             rst,
+    input       [7:0] intv,
+    input             inta,
+    output            intr,
+    output reg  [2:0] iid
+  );
+
+  // Registers
+  reg [7:0] irr;
+  reg       inta_r;
+  reg       int3_r;
+  reg       int4_r;
+
+  // Continuous assignments, note that only IRQs 0,1,3 & 4 are driven atm
+  assign intr = irr[4] | irr[3] | irr[1] | irr[0];
+
+  // Behaviour of inta_r
+  always @(posedge clk) inta_r <= inta;
+
+  // irr
+  always @(posedge clk)
+    irr[0] <= rst ? 1'b0 : (intv[0] | irr[0] & !(iid == 3'b000 && inta_r && !inta));
+
+  always @(posedge clk)
+    irr[1] <= rst ? 1'b0 : (intv[1] | irr[1] & !(iid == 3'b001 && inta_r && !inta));
+
+  always @(posedge clk)
+    irr[3] <= rst ? 1'b0 : ((intv[3] && !int3_r) | irr[3] & !(iid == 3'b011 && inta_r && !inta));
+  always @(posedge clk) int3_r <= rst ? 1'b0 : intv[3];    // int3_r
+
+  always @(posedge clk)
+    irr[4] <= rst ? 1'b0 : ((intv[4] && !int4_r) | irr[4] & !(iid == 3'b100 && inta_r && !inta));
+  always @(posedge clk) int4_r <= rst ? 1'b0 : intv[4];    // int4_r
+
+  always @(posedge clk)                        // iid
+    iid <= rst ? 3'b0 : (inta ? iid :
+                        (irr[0] ? 3'b000 :
+                        (irr[1] ? 3'b001 :
+                        (irr[3] ? 3'b011 :
+                        (irr[4] ? 3'b100 : 
+                                  3'b000
+                        )))));
+
+endmodule
+"
+"//////////////////////////////////////////////////////////////////
+//                                                              //
+//  Multiplication Module for Amber 2 Core                      //
+//                                                              //
+//  This file is part of the Amber project                      //
+//  http://www.opencores.org/project,amber                      //
+//                                                              //
+//  Description                                                 //
+//  64-bit Booth signed or unsigned multiply and                //
+//  multiply-accumulate supported. It takes about 38 clock      //
+//  cycles to complete an operation.                            //
+//                                                              //
+//  Author(s):                                                  //
+//      - Conor Santifort, csantifort.amber@gmail.com           //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+//                                                              //
+// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
+//                                                              //
+// This source file may be used and distributed without         //
+// restriction provided that this copyright statement is not    //
+// removed from the file and that any derivative work contains  //
+// the original copyright notice and the associated disclaimer. //
+//                                                              //
+// This source file is free software; you can redistribute it   //
+// and/or modify it under the terms of the GNU Lesser General   //
+// Public License as published by the Free Software Foundation; //
+// either version 2.1 of the License, or (at your option) any   //
+// later version.                                               //
+//                                                              //
+// This source is distributed in the hope that it will be       //
+// useful, but WITHOUT ANY WARRANTY; without even the implied   //
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
+// PURPOSE.  See the GNU Lesser General Public License for more //
+// details.                                                     //
+//                                                              //
+// You should have received a copy of the GNU Lesser General    //
+// Public License along with this source; if not, download it   //
+// from http://www.opencores.org/lgpl.shtml                     //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+
+
+
+// bit 0 go, bit 1 accumulate
+// Command:
+//  4'b01 :  MUL   - 32 bit multiplication
+//  4'b11 :  MLA   - 32 bit multiply and accumulate
+//
+//  34-bit Booth adder
+//  The adder needs to be 34 bit to deal with signed and unsigned 32-bit
+//  multiplication inputs. This adds 1 extra bit. Then to deal with the
+//  case of two max negative numbers another bit is required.
+//
+
+module a23_multiply (
+input                       i_clk,
+input                       i_fetch_stall,
+
+input       [31:0]          i_a_in,         // Rds
+input       [31:0]          i_b_in,         // Rm
+input       [1:0]           i_function,
+input                       i_execute,
+
+output      [31:0]          o_out,
+output      [1:0]           o_flags,        // [1] = N, [0] = Z
+output reg                  o_done = 'd0    // goes high 2 cycles before completion                                          
+);
+
+
+wire        enable;
+wire        accumulate;
+wire [33:0] multiplier;
+wire [33:0] multiplier_bar;
+wire [33:0] sum;
+wire [33:0] sum34_b;
+
+reg  [5:0]  count = 'd0;
+reg  [5:0]  count_nxt;
+reg  [67:0] product = 'd0;
+reg  [67:0] product_nxt;
+reg  [1:0]  flags_nxt;
+wire [32:0] sum_acc1;           // the MSB is the carry out for the upper 32 bit addition
+
+
+assign enable         = i_function[0];
+assign accumulate     = i_function[1];
+ 
+assign multiplier     =  { 2'd0, i_a_in} ;
+assign multiplier_bar = ~{ 2'd0, i_a_in} + 34'd1 ;
+
+assign sum34_b        =  product[1:0] == 2'b01 ? multiplier     :
+                         product[1:0] == 2'b10 ? multiplier_bar :
+                                                 34'd0          ;
+
+
+// Use DSP modules from Xilinx Spartan6 FPGA devices
+`ifdef XILINX_FPGA
+    // -----------------------------------
+    // 34-bit adder - booth multiplication
+    // -----------------------------------
+    `ifdef XILINX_SPARTAN6_FPGA
+        xs6_addsub_n #(.WIDTH(34)) 
+    `endif
+    `ifdef XILINX_VIRTEX6_FPGA
+        xv6_addsub_n #(.WIDTH(34))  
+    `endif
+        
+        u_xx_addsub_34_sum (
+        .i_a    ( product[67:34]        ),
+        .i_b    ( sum34_b               ),
+        .i_cin  ( 1'd0                  ),
+        .i_sub  ( 1'd0                  ),
+        .o_sum  ( sum                   ),
+        .o_co   (                       )
+    );
+
+    // ------------------------------------
+    // 33-bit adder - accumulate operations
+    // ------------------------------------
+    `ifdef XILINX_SPARTAN6_FPGA
+        xs6_addsub_n #(.WIDTH(33)) 
+    `endif
+    `ifdef XILINX_VIRTEX6_FPGA
+        xv6_addsub_n #(.WIDTH(33)) 
+    `endif
+        u_xx_addsub_33_acc1 (
+        .i_a    ( {1'd0, product[32:1]} ),
+        .i_b    ( {1'd0, i_a_in}        ),
+        .i_cin  ( 1'd0                  ),
+        .i_sub  ( 1'd0                  ),
+        .o_sum  ( sum_acc1              ),
+        .o_co   (                       )
+    );
+
+`else
+ 
+    // -----------------------------------
+    // 34-bit adder - booth multiplication
+    // -----------------------------------
+    assign sum =  product[67:34] + sum34_b;
+     
+    // ------------------------------------
+    // 33-bit adder - accumulate operations
+    // ------------------------------------
+    assign sum_acc1 = {1'd0, product[32:1]} + {1'd0, i_a_in};
+     
+`endif
+
+
+always @*
+    begin
+    // Defaults
+    count_nxt           = count;
+    product_nxt         = product;
+    
+    // update Negative and Zero flags
+    // Use registered value of product so this adds an extra cycle
+    // but this avoids having the 64-bit zero comparator on the
+    // main adder path
+    flags_nxt   = { product[32], product[32:1] == 32'd0 }; 
+    
+
+    if ( count == 6'd0 )
+        product_nxt = {33'd0, 1'd0, i_b_in, 1'd0 } ;
+    else if ( count <= 6'd33 )
+        product_nxt = { sum[33], sum, product[33:1]} ;
+    else if ( count == 6'd34 && accumulate )
+        begin
+        // Note that bit 0 is not part of the product. It is used during the booth
+        // multiplication algorithm
+        product_nxt         = { product[64:33], sum_acc1[31:0], 1'd0}; // Accumulate
+        end
+        
+    // Multiplication state counter
+    if (count == 6'd0)  // start
+        count_nxt   = enable ? 6'd1 : 6'd0;
+    else if ((count == 6'd34 && !accumulate) ||  // MUL
+             (count == 6'd35 &&  accumulate)  )  // MLA
+        count_nxt   = 6'd0;
+    else
+        count_nxt   = count + 1'd1;
+    end
+
+
+always @ ( posedge i_clk )
+    if ( !i_fetch_stall )
+        begin
+        count           <= i_execute ? count_nxt          : count;           
+        product         <= i_execute ? product_nxt        : product;        
+        o_done          <= i_execute ? count == 6'd31     : o_done;          
+        end
+
+// Outputs
+assign o_out   = product[32:1]; 
+assign o_flags = flags_nxt;
+                     
+endmodule
+
+
+"
+"// **************************************************************************
+//    tube.v - top level module for the Beeb816 Acorn Tube Replacement
+//   
+//    COPYRIGHT 2010 Richard Evans, Ed Spittles
+// 
+//    This file is part of tube - an Acorn Tube ULA compatible system.
+//   
+//    tube is free software: you can redistribute it and/or modify
+//    it under the terms of the GNU Lesser General Public License as published by
+//    the Free Software Foundation, either version 3 of the License, or
+//    (at your option) any later version.
+//
+//    tube is distributed in the hope that it will be useful,
+//    but WITHOUT ANY WARRANTY; without even the implied warranty of
+//    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//    GNU Lesser General Public License for more details.
+//
+//    You should have received a copy of the GNU Lesser General Public License
+//    along with tube.  If not, see <http://www.gnu.org/licenses/>.
+//
+// **************************************************************************
+// Compile time Options
+// OMIT_DMA_PINS_D     - if set eliminates drq and dack_b pins, not required 
+//                       for 6502 and Z80 coprocessors
+// ENABLE_DMA_D        - set this to enable DMA operation. Since the 6502/Z80
+//                       don\'t require it we can\'t verify it on our board so
+//                       leave this disabled (and the logic slightly reduced)
+// DEBUG_NO_TUBE_D     - if set forces the LSB of register 0 (the status/
+//                       command word) to return \'0\' and so not be recognized
+//                       on boot by the host system
+// TWOSTATE_PARASITE_INTERRUPTS_D - if set then parasite interrupt pins are driven high and low
+//                                  if not set (default) then they are open collector
+// 
+// **************************************************************************
+`timescale 1ns /1ns
+
+// Interrupts can be open collector type outputs in non-trivial systems
+`ifdef TWOSTATE_HOST_INTERRUPTS_D
+ `define H_INTERRUPT_OFF_D 1\'b1
+`else
+ `define H_INTERRUPT_OFF_D 1\'bz
+`endif
+`ifdef TWOSTATE_PARASITE_INTERRUPTS_D
+ `define P_INTERRUPT_OFF_D 1\'b1
+`else
+ `define P_INTERRUPT_OFF_D 1\'bz
+`endif
+
+// Define bit positions of all flags
+`define S_IDX 7
+`define T_IDX 6
+`define P_IDX 5   
+`define V_IDX 4
+`define M_IDX 3
+`define J_IDX 2
+`define I_IDX 1
+`define Q_IDX 0   
+
+module tube (
+             input [2:0] h_addr,
+             input       h_cs_b,
+`ifdef SEPARATE_HOST_DATABUSSES_D
+             input [7:0]  h_data_in,
+             output [7:0] h_data_out,
+`else 
+             inout [7:0] h_data,
+`endif 
+             input       h_phi2,
+             input       h_rdnw,
+             input       h_rst_b,
+             output      h_irq_b,
+`ifndef OMIT_DMA_PINS_D            
+             output      drq,
+             input       dack_b,
+`endif
+             
+             input [2:0] p_addr,
+             input       p_cs_b,
+`ifdef SEPARATE_PARASITE_DATABUSSES_D
+             input [7:0]  p_data_in,
+             output [7:0] p_data_out,
+`else 
+             inout [7:0] p_data,
+`endif 
+             
+             input       p_rdnw,
+             input       p_phi2,
+             output      p_rst_b,
+             output      p_nmi_b,
+             output      p_irq_b
+             );
+   
+`ifdef OMIT_DMA_PINS_D   
+   wire       dack_b_w = 1\'b1;
+`else
+ `ifdef ENABLE_DMA_D
+   wire       dack_b_w = dack_b;
+ `else   
+   wire       dack_b_w = 1\'b1;
+ `endif   
+`endif
+
+   wire       p_r3_two_bytes_available_w;
+   
+   wire [3:0] h_select_fifo_d_w;
+   wire       h_select_reg0_d_w;      
+   reg        h_select_reg0_q_r;   
+   reg [3:0]  h_select_fifo_q_r;
+   reg [3:0]  p_select_fifo_r;
+   reg        h_rdnw_q_r;
+   reg        n_flag;
+   
+
+   
+   reg [7:0]    h_data_r;
+   reg [7:0]    p_data_r;
+   reg          p_nmi_b_r;
+          
+   reg [6:0]    h_reg0_q_r;
+   reg [5:0]    p_reg0_q_r;   
+   
+   wire [7:0]   p_data_w;
+   wire [7:0]   h_data_w;
+
+   wire [3:0]   p_data_available_w;
+   wire [3:0]   p_full_w;
+   wire [3:0]   h_data_available_w;
+   wire [3:0]   h_full_w;
+   
+   wire [6:0]   h_reg0_d_w;
+   wire         local_rst_b_w;
+   wire         ph_zero_r3_bytes_avail_w   ;
+
+   
+   // Assign to primary IOs
+`ifndef OMIT_DMA_PINS_D
+   // ""DMA Operation
+   //  The DRQ pin (active state = 1) may be used to request a DMA transfer - when M = 1 DRQ will have the
+   //  opposite value to PNMI, and depends on V in exactly the same way (see description of interrupt operation).""
+   assign drq = h_reg0_q_r[ `M_IDX] & !p_nmi_b_r  ;
+`endif   
+
+
+   // host interrupt active only if enabled and data ready in register 4 
+   assign h_irq_b = ( h_reg0_q_r[`Q_IDX] & h_data_available_w[3] ) ? 1\'b0 : `H_INTERRUPT_OFF_D ;
+   assign p_nmi_b = (p_nmi_b_r) ?  `P_INTERRUPT_OFF_D : 1\'b0 ;
+   // parasite IRQ active
+   assign p_irq_b = ( (h_reg0_q_r[`I_IDX] & p_data_available_w[0]) | (h_reg0_q_r[`J_IDX] & p_data_available_w[3]) ) ? 1\'b0 : `P_INTERRUPT_OFF_D  ;
+
+   // Active p_rst_b when \'1\' in P flag or host reset is applied
+   assign p_rst_b = (!h_reg0_q_r[`P_IDX] & h_rst_b) ;   
+
+`ifdef SEPARATE_HOST_DATABUSSES_D
+   wire [7:0] \th_data;
+   assign h_data = h_data_in;
+   assign h_data_out = h_data_r;
+`else // SEPARATE_HOST_DATABUSSES_D
+   assign h_data = ( h_rdnw && !h_cs_b && h_phi2 ) ? h_data_r : 8\'bzzzzzzzz;
+`endif // SEPARATE_HOST_DATABUSSES_D
+
+`ifdef SEPARATE_PARASITE_DATABUSSES_D
+   wire [7:0] \tp_data;
+   assign p_data = p_data_in;
+   assign p_data_out = p_data_r;
+`else // SEPARATE_PARASITE_DATABUSSES_D
+   assign p_data = ( p_rdnw && !p_cs_b ) ? p_data_r : 8\'bzzzzzzzz;   
+`endif // SEPARATE_PARASITE_DATABUSSES_D
+   
+   // Compute register selects for host side
+   assign h_select_reg0_d_w    = !h_cs_b && ( h_addr == 3\'b0);          
+   assign h_select_fifo_d_w[0] = !h_cs_b & ( h_addr == 3\'h1);
+   assign h_select_fifo_d_w[1] = !h_cs_b & ( h_addr == 3\'h3);
+   assign h_select_fifo_d_w[2] = !h_cs_b & ( h_addr == 3\'h5);
+   assign h_select_fifo_d_w[3] = !h_cs_b & ( h_addr == 3\'h7);        
+
+   // Flag definitions from the Tube Application Note
+   //
+   //  Q= 1 enable HIRQ from register 4
+   //  I= 1 enable PIRQ from register 1
+   //  J= 1 enable PIRQ from register 4
+   //  M= 1 enable PNMI from register 3
+   //  V =1 two byte operation of register 3 
+   //  P =1 activate PRST
+   //  T =1 clear all Tube registers  (soft reset)
+   //  S= 1 set control flag(s) indicated by mask
+   //     
+   //
+   // These flags are set or cleared according to the value of S, eg writing 92 (hex) 
+   // to address 0 will set V and I to 1 but not affect the other flags, whereas 12 (hex) 
+   // would clear V and I without changing the other flags. All flags except T are read 
+   // out directly as the least significant 6 bits from address 0.
+
+`ifdef DEBUG_NO_TUBE_D
+   // Don\'t allow host interrupts to be enabled and prevent tube from being recognized
+   assign h_reg0_d_w[`Q_IDX] = 1;
+`else   
+   assign h_reg0_d_w[`Q_IDX] = (  !h_rdnw && h_select_reg0_q_r) ? ( h_data[ `Q_IDX] ? h_data[`S_IDX] : h_reg0_q_r[ `Q_IDX] ): h_reg0_q_r [ `Q_IDX];
+`endif
+   assign h_reg0_d_w[`I_IDX] = (  !h_rdnw && h_select_reg0_q_r) ? ( h_data[ `I_IDX] ? h_data[`S_IDX] : h_reg0_q_r[ `I_IDX] ): h_reg0_q_r [ `I_IDX];
+   assign h_reg0_d_w[`J_IDX] = (  !h_rdnw && h_select_reg0_q_r) ? ( h_data[ `J_IDX] ? h_data[`S_IDX] : h_reg0_q_r[ `J_IDX] ): h_reg0_q_r [ `J_IDX];
+   assign h_reg0_d_w[`V_IDX] = (  !h_rdnw && h_select_reg0_q_r) ? ( h_data[ `V_IDX] ? h_data[`S_IDX] : h_reg0_q_r[ `V_IDX] ): h_reg0_q_r [ `V_IDX];
+   assign h_reg0_d_w[`M_IDX] = (  !h_rdnw && h_select_reg0_q_r) ? ( h_data[ `M_IDX] ? h_data[`S_IDX] : h_reg0_q_r[ `M_IDX] ): h_reg0_q_r [ `M_IDX];
+   assign h_reg0_d_w[`P_IDX] = (  !h_rdnw && h_select_reg0_q_r) ? ( h_data[ `P_IDX] ? h_data[`S_IDX] : h_reg0_q_r[ `P_IDX] ): h_reg0_q_r [ `P_IDX];
+   assign h_reg0_d_w[`T_IDX] = (  !h_rdnw && h_select_reg0_q_r) ? ( h_data[ `T_IDX] ? h_data[`S_IDX] : h_reg0_q_r[ `T_IDX] ): h_reg0_q_r [ `T_IDX];      
+
+   // Combine hard and soft resets
+   assign local_rst_b_w = ! ( !h_rst_b | h_reg0_q_r[`T_IDX] );   
+   
+
+//   PNMI  either: 
+//   M = 1 V = 0   1 or 2 bytes in host to parasite register 3 FIFO or 
+//                 0 bytes in parasite to host register 3 FIFO (this allows 
+//                 single byte transfers across register 3) 
+//   or:
+// \t
+//   M = 1 V = 1   2 bytes in host to parasite register 3 FIFO or 0 bytes 
+//                 in parasite to host register 3 FIFO. (this allows two 
+//                 byte transfers across register 3)
+//   
+   always @ ( h_reg0_q_r or
+              p_data_available_w or
+              ph_zero_r3_bytes_avail_w  or
+              p_r3_two_bytes_available_w or
+              p_full_w
+              )
+     begin
+       if ( h_reg0_q_r[`V_IDX] == 1\'b0 )
+         n_flag = ( p_data_available_w[2] | ph_zero_r3_bytes_avail_w  ) ;
+       else
+         n_flag = ( p_r3_two_bytes_available_w |  ph_zero_r3_bytes_avail_w  ) ;
+        if ( h_reg0_q_r[`M_IDX] == 1\'b1 )
+          if ( h_reg0_q_r[`V_IDX] == 1\'b0 )
+            p_nmi_b_r = ! ( p_data_available_w[2] | ph_zero_r3_bytes_avail_w  ) ;
+          else
+            p_nmi_b_r = ! ( p_r3_two_bytes_available_w |  ph_zero_r3_bytes_avail_w  ) ;            
+        else
+          p_nmi_b_r = 1\'b1;        
+     end     
+ 
+
+   // Multiplexing of different FIFO IOs
+   //
+   // NB. App note says that all \'x\' bits will read out as \'1\'
+   always @ ( p_data_w or 
+              p_addr or  
+              p_reg0_q_r or            
+              p_data_available_w or
+              n_flag or
+              p_full_w )
+     begin
+        case ( p_addr )
+          3\'h0: p_data_r = { p_data_available_w[0], !p_full_w[0], p_reg0_q_r[5:0]};
+          3\'h1: p_data_r = p_data_w;          
+          3\'h2: p_data_r = { p_data_available_w[1], !p_full_w[1], 6\'b111111};
+          3\'h3: p_data_r = p_data_w;
+          3\'h4: p_data_r = { n_flag, !p_full_w[2], 6\'b111111};
+          3\'h5: p_data_r = p_data_w;          
+          3\'h6: p_data_r = { p_data_available_w[3], !p_full_w[3], 6\'b111111};
+          3\'h7: p_data_r = p_data_w;          
+          // default: p_data_r = p_data_w;
+        endcase // case ( p_addr )        
+     end     
+
+   always @ ( h_data_w or 
+              h_addr or
+              h_reg0_q_r or
+              h_data_available_w or
+              h_full_w )
+     begin
+        case ( h_addr )
+          3\'h0: h_data_r = { h_data_available_w[0], !h_full_w[0], h_reg0_q_r[5:0]};
+          3\'h1: h_data_r = h_data_w;          
+          3\'h2: h_data_r = { h_data_available_w[1], !h_full_w[1], 6\'b111111};
+          3\'h3: h_data_r = h_data_w;
+          3\'h4: h_data_r = { h_data_available_w[2], !h_full_w[2], 6\'b111111};
+          3\'h5: h_data_r = h_data_w;          
+          3\'h6: h_data_r = { h_data_available_w[3], !h_full_w[3], 6\'b111111};
+          3\'h7: h_data_r = h_data_w;
+          // default: h_data_r = h_data_w;
+        endcase // case ( h_addr )        
+     end     
+
+
+   // Instance all the individual host-parasite direction FIFOs
+   hp_bytequad  hp_fifo (
+                         .h_rst_b( local_rst_b_w ) ,
+                         .h_we_b ( h_rdnw ),
+                         .h_selectData( h_select_fifo_q_r ),
+                         .h_phi2( h_phi2),
+                         .h_data( h_data),
+                         .p_selectData( p_select_fifo_r ),
+                         .p_phi2(p_phi2),
+                         .p_rdnw(p_rdnw),                         
+                         .p_data( p_data_w),
+                         .one_byte_mode( ! h_reg0_q_r[`V_IDX]),
+                         .p_data_available(p_data_available_w),
+                         .p_r3_two_bytes_available(p_r3_two_bytes_available_w),
+                         .h_full(h_full_w)
+                         );
+
+   // Instances of parasite->host modules
+   //
+   // ""DMA Operation ... DACK then selects register 3 independently of PA0-2 and PCS, and forces a 
+   //  read cycle if PNWDS is active or a write cycle if PNRDS is active (note inverse sense of 
+   //  PNWDS and PNRDS so that the DMA system can read the data from memory an write it into the 
+   //  Tube in one cycle).""
+   //
+   //  Tube App note, p12.   
+   always @ ( p_addr or p_cs_b or dack_b_w)
+     begin
+        p_select_fifo_r[0] = !p_cs_b & (( p_addr == 3\'h1) & dack_b_w);  // REG 1
+        p_select_fifo_r[1] = !p_cs_b & (( p_addr == 3\'h3) & dack_b_w);  // REG 2
+        p_select_fifo_r[2] = !p_cs_b & (( p_addr == 3\'h5) | !dack_b_w); // REG 3
+        p_select_fifo_r[3] = !p_cs_b & (( p_addr == 3\'h7) & dack_b_w);  // REG 4       
+     end
+
+   ph_bytequad  ph_fifo (
+                         .h_rst_b(local_rst_b_w),
+                         .h_rd( h_rdnw_q_r ),// Use latched version of rdnw
+                         .h_selectData(  h_select_fifo_q_r),
+                         .h_phi2(h_phi2 ),
+                         .p_data(p_data),                  
+                         .p_selectData(p_select_fifo_r ),
+                         .p_phi2(p_phi2),
+                         .p_rdnw( (!dack_b_w) ^ p_rdnw),
+                         .h_data (h_data_w),                
+                         .one_byte_mode( ! h_reg0_q_r[`V_IDX]),  
+                         .h_data_available( h_data_available_w),
+                         .ph_zero_r3_bytes_avail( ph_zero_r3_bytes_avail_w ),
+                         .p_full(p_full_w)
+                         );
+   
+   // Remaining state for host side reg 0, note that FIFO is unaffected by soft reset
+   always @ ( negedge h_phi2 or negedge h_rst_b )
+     if ( ! h_rst_b )
+       h_reg0_q_r <= 7\'b0;
+     else
+       h_reg0_q_r <= h_reg0_d_w;
+
+   // Latch host side register select signals on phi2 - found that the L1B CPLD was
+   // more robust when this was done avoiding bus hold issues ?
+   always @ (posedge h_phi2 or negedge h_rst_b)
+     begin
+        if ( ! h_rst_b )
+          begin
+             h_select_fifo_q_r <= 4\'h0;
+             h_select_reg0_q_r <= 1\'b0;
+             h_rdnw_q_r <= 1\'b0;             
+          end
+        else
+          begin
+             h_rdnw_q_r <= h_rdnw;                          
+             h_select_reg0_q_r    <= h_select_reg0_d_w;          
+             h_select_fifo_q_r[0] <= h_select_fifo_d_w[0];
+             h_select_fifo_q_r[1] <= h_select_fifo_d_w[1];
+             h_select_fifo_q_r[2] <= h_select_fifo_d_w[2];
+             h_select_fifo_q_r[3] <= h_select_fifo_d_w[3];      
+          end  
+     end // always @ ( posedge h_phi2 or negedge h_rst_b )
+
+
+   // Provide option for retiming read of status/command reg from host to parasite
+   always @ ( posedge p_phi2 or negedge h_rst_b )   
+     if ( !h_rst_b )
+       p_reg0_q_r <= 6\'b000000;
+     else
+       p_reg0_q_r <= h_reg0_q_r[5:0];
+   
+endmodule
+"
+"always @(negedge reset or posedge clk) begin
+  if (reset == 0) begin
+    d_out <= 16'h0000;
+    d_out_mem[resetcount] <= d_out;
+    laststoredvalue <= d_out;
+  end else begin
+    d_out <= d_out + 1'b1; 
+  end
+end
+
+always @(bufreadaddr)
+  bufreadval = d_out_mem[bufreadaddr];"
+"module counter_test;
+    parameter WIDTH = 8;
+
+    reg rst = 0;
+    
+    initial
+    begin
+        # 17 rst = 1;
+        # 11 rst = 0;
+        # 29 rst = 1;
+        # 11 rst = 0;
+        # 100 $stop;
+    end
+
+    reg clk = 0;
+    always #5 clk = !clk;
+
+    wire [WIDTH - 1 : 0] value;
+    counter c1 (value, clk, rst);
+
+    initial
+    begin
+       $monitor(""At time %t, value = %h (%0d)"", $time, value, value);
+    end
+
+endmodule"
+"// Stupid first CPU.
+module SimpleCPU(clk, rst, cur_ins);
+    // Definitions.
+    parameter REG_SET_SIZE = 16;
+    parameter WORD_SIZE = 32;
+    
+    // Instruction opcodes.
+    parameter OP_NOP = 32\'b00000000000000000000000000000000;
+    parameter OP_INC = 32\'b00000000000000000000000000000001;
+    parameter OP_DEC = 32\'b00000000000000000000000000000010;
+    
+    // Input ports.
+    input clk;
+    input rst;
+    input [WORD_SIZE-1:0] cur_ins;
+        
+    // Define the set of registers.
+    reg [WORD_SIZE-1:0] regs [0:REG_SET_SIZE];
+    reg [WORD_SIZE-1:0] CPSR;
+    
+    // Define aliases for the CPU registers.
+    `define REG_SP regs[13] // Stack pointer.
+    `define REG_LR regs[14] // Link register.
+    `define REG_PC regs[15] // Program counter.
+    
+    // Define aliases for the CPU flags. 
+    `define CPSR_V CPSR[28] // Overflow flag.
+    `define CPSR_C CPSR[29] // Carry flag.
+    `define CPSR_Z CPSR[30] // Zero flag.
+    `define CPSR_N CPSR[31] // Negative/less than flag.
+    
+    // Local variables.
+    integer i;
+    
+    // Advance on each \'clk\' tick and reset on each \'rst\' tick.
+    always @(posedge clk or posedge rst) begin 
+        if (rst) begin
+            $display(""Resetting the CPU."");
+            
+            // Reset the flags register.
+            CPSR = 0;
+            
+            // Reset the general purpose registers.
+            for (i = 0; i < REG_SET_SIZE; i = i + 1)
+            begin
+                regs[i] = 0;
+            end
+        end
+        
+        // Increment the program counter.
+        `REG_PC = `REG_PC + 1;
+        
+        // Debug: dump the state.
+        $display(""Current state:"");
+        $display(""  r0:%8x r1:%8x  r2:%8x  r3:%8x  r4:%8x r5:%8x r6:%8x r7:%8x"", regs[0], regs[1], regs[2], regs[3], regs[4], regs[5], regs[6], regs[7]);
+        $display(""  r8:%8x r9:%8x r10:%8x r11:%8x r12:%8x SP:%8x LR:%8x PC:%8x"", regs[8], regs[9], regs[10], regs[11], regs[12], regs[13], regs[14], regs[15]);
+        $display(""  cur_ins:%8x"", cur_ins);
+        
+        // Main instruction dispatcher.
+        case (cur_ins)
+
+            // No operation.
+            OP_NOP:
+            begin
+                $display(""OP_NOP"");
+            end
+            
+            // Increment r0.
+            OP_INC:
+            begin
+                $display(""OP_INC"");
+                regs[0] = regs[0] + 1; 
+            end
+            
+            // Decrement r0.
+            OP_DEC:
+            begin
+                $display(""OP_DEC"");
+                regs[0] = regs[0] - 1;
+            end
+            
+            // Handle unknown opcodes.
+            default:
+            begin
+                $display(""Unknown opcode %8x"", cur_ins);
+            end
+            
+        endcase
+    end
+endmodule
+"
+"module counter (out, clk, rst);
+    // Like a macro.
+    parameter WIDTH = 8;
+    
+    // Define if the arguments are inputs or outputs.
+    output [WIDTH - 1 : 0] out;
+    input clk;
+    input rst;
+
+    // Set the kind of variable, register or wire depending on what we need.
+    reg [WIDTH - 1 : 0] out;
+    wire clk;
+    wire rst;
+
+    // Execute whenever there is a positive transition on 'clk'.
+    always @(posedge clk)
+    begin
+        // Why don't we use assign here?.
+        out <= out + 1;
+    end
+    
+    always @(rst)
+    begin
+        if (rst)
+            assign out = 0;
+        else
+            deassign out;
+    end
+
+endmodule"
+"// Flip flop that sets the output 'q' to 't' when there is a possitive
+// clock tick.
+module ToggleFlipFlop (clk, rst, q);
+    input clk, rst, t;
+    output q;
+    reg q;
+
+    always @(negedge clk or posedge rst)
+    begin
+        if(rst) begin
+            q <= 0;
+        end else begin
+            q <= ~q;
+        end
+    end
+
+endmodule // ToggleFlipFlop
+
+module RippleCarryCounter (clk, rst, q);
+    input clk, rst;
+    output [3:0] q;
+
+    // Instanciate the toggle flip flop.
+    ToggleFlipFlop tff1(clk , rst, q[0]);
+    ToggleFlipFlop tff2(q[0], rst, q[1]);
+    ToggleFlipFlop tff3(q[1], rst, q[2]);
+    ToggleFlipFlop tff4(q[2], rst, q[3]);
+
+endmodule // RippleCarryCounter
+"
+"// Test the implemenation of SimpleCPU.
+// iverilog -o SimpleCPU SimpleCPU.v SimpleCPU_test.v
+// 
+module SimpleCPU_test ();
+    reg clk, rst;
+    reg [31:0] cur_ins;
+    
+    // Instanciate our CPU and connect the input ports.
+    SimpleCPU cpu(clk, rst, cur_ins);
+    
+    // Setup the simulation environment.
+    initial
+    begin
+        clk = 0;    // Set the clock to low.
+        rst = 1;    // Reset the counter.
+        cur_ins = 1;
+        
+        // After 5 time units change the reset flag.
+        #5 rst = 0;
+
+        // End the simulation after 50 time units.
+        #50;
+        $finish;
+    end
+
+    // Every 5 time units change the clock.
+    always 
+    begin 
+        #5 clk = ~clk;
+    end
+    
+endmodule"
+"module RippleCarryCounter_test ();
+    reg clk, rst;
+    wire [3:0] q;
+
+    // Create the carry counter.
+    RippleCarryCounter rcc (clk, rst, q);
+
+    // Setup the simulation environment.
+    initial
+    begin
+        clk = 0;    // Set the clock to low.
+        rst = 1;    // Reset the counter.
+
+        // Play with the time and reset.
+        #30 rst = 0;
+        #30 rst = 1;
+        #30 rst = 0;
+        #30 rst = 1;
+        #30 rst = 0;
+        #30 rst = 1;
+        #30 rst = 0;
+        #30 rst = 1;
+        #30 rst = 0;
+
+        // End the simulation after 50 time units.
+        #50;
+        $finish;
+    end
+
+    // Every 5 time units change the clock.
+    always 
+    begin 
+        #5 clk = ~clk;
+    end
+
+    initial
+    begin
+       $monitor(""At time %t, q=%2d, rst=%d"", $time, q, rst);
+    end
+
+
+
+endmodule"
+"// DESCRIPTION: Example top verilog file for vpassert program
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2000-2012 by Wilson Snyder.
+
+`timescale 1ns/1ns
+
+module example;
+
+   pli pli ();\t// Put on highest level of your design
+
+   integer i;
+
+`define ten 10
+
+   reg \\escaped[10] ;
+
+   initial begin
+      $uinfo (0, ""Welcome to a VPASSERTed file\
+"");
+      //
+      $uinfo (1, ""Printed only at debug level %0d\
+"",1);
+      $uinfo (9, ""Printed only at debug level %0d\
+"",9);
+      //
+      \\escaped[10] = 1\'b1;
+      $uassert (\\escaped[10] , ""Escaped not 1\
+"");
+      $uassert_info (\\escaped[10] , ""Escaped not 1\
+"");
+      //
+      i=0;
+      $uassert (1==1, ""Why doesn\'t 1==1??\
+"");
+      $uassert (10==`ten, ""Why doesn\'t 10==10??\
+"");
+      $uassert (/*comm
+\t\tent*/1==1,
+\t       //comment
+\t       /*com
+\t\tent*/""Why doesn\'t 1==1??\
+""/*com
+\t       ent*/
+\t       );
+      //
+      i=3\'b100;  $uassert_amone(\\i [2:0], ""amone ok\
+"");
+      i=3\'b010;  $uassert_amone(i[2:0], ""amone ok\
+"");
+      i=3\'b001;  $uassert_amone(i[2:0], ""amone ok\
+"");
+      i=3\'b000;  $uassert_amone(i[2:0], ""amone ok\
+"");
+      //i=3\'b011;  $uassert_amone(i[2:0], ""amone error expected\
+"");
+      //i=3\'b110;  $uassert_amone(i[2:0], ""amone error expected\
+"");
+      //
+      i=2\'b10;  $uassert_onehot(i[1:0], ""onehot ok\
+"");
+      i=2\'b01;  $uassert_onehot(i[1:0], ""onehot ok\
+"");
+      i=2\'b10;  $uassert_onehot(i[1],i[0], ""onehot ok\
+"");
+      i=2\'b10;  $uassert_onehot({i[1],i[0]}, ""onehot ok\
+"");
+      //i=2\'b11;  $uassert_onehot(i[2:0], ""onehot error expected\
+"");
+      //i=2\'b00;  $uassert_onehot(i[2:0], ""onehot error expected\
+"");
+   end
+
+   // Test assertions within case statements
+   initial begin
+      i=3\'b100;
+      casez (i)
+\t3\'b100: ;
+\t3\'b000: $stop;
+\t3\'b010: $uerror(""Why?\
+"");
+\tdefault: $stop;
+      endcase
+      if ($time > 1000) $stop;
+   end
+
+   // Example of request/grant handshake
+   reg\t      clk;
+   reg\t      bus_req;\t\t// Request a transaction, single cycle pulse
+   reg\t      bus_ack;\t\t// Acknowledged transaction, single cycle pulse
+   reg [31:0] bus_data;
+
+   initial begin
+      // Reset signals
+      bus_req  = 1\'b0;
+      bus_ack  = 1\'b0;
+      bus_data = 1\'b0;
+      // Assert a request
+      @ (posedge clk) ;
+      bus_req  = 1\'b1;
+      bus_data = 32\'hfeed;
+      // Wait for ack
+      @ (posedge clk) ;
+      bus_req  = 1\'b0;
+      // Send ack
+      @ (posedge clk) ;
+      bus_ack  = 1\'b1;
+      // Next request could be here
+      @ (posedge clk) ;
+      bus_ack  = 1\'b0;
+   end
+   always @ (posedge clk) begin
+      $uassert_req_ack (bus_req,
+\t\t\tbus_ack /*COMMENT*/,
+\t\t\tbus_data);
+   end
+
+   // Overall control loop
+   initial clk = 1\'b0;
+   initial forever begin
+      #1;
+      i = i + 1;
+      clk = !clk;
+      if (i==20) $uwarn  (0, ""Don\'t know what to do next!\
+"");
+      if (i==22) $uerror (0, ""Guess I\'ll error out!\
+"");
+   end
+
+   // Moved clock asserts
+   always @* begin
+      if (i==19) $uwarn_clk  (clk,""Called at next edge (1 of 2)\
+"");
+      if (i==18) $ucover_clk (clk,""example_cover_label"");
+      $ucover_foreach_clk(clk, ""foreach_label"", ""27:3,1,0"", (i[$ui]));
+   end
+
+   // Meta coverage disables
+   initial begin
+      // vp_coverage_off
+      if (0) begin end // cover off\'ed
+      // vp_coverage_on
+   end
+
+   // Ifdef based disables
+   initial begin
+`ifndef NEVER
+ `ifdef SYNTHESIS
+      if (1) begin end  // cover on
+ `elsif SYNTHESIS
+      if (1) begin end  // cover on
+ `else
+      if (1) begin end  // cover off\'ed
+ `endif
+ `ifndef SYNTHESIS
+      if (1) begin end  // cover off\'ed
+ `else
+      if (1) begin end  // cover on
+ `endif
+`endif
+    end
+
+endmodule
+"
+"// DESCRIPTION: Verilog-Perl: Example Verilog for testing package
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2009-2012 by Wilson Snyder.
+
+`include ""v_sv_pkg""
+
+interface sv_if_ported (input clk);
+endinterface
+
+module v_sv_mod (v_sv_intf intf, input clk);
+
+   // Import types
+   import v_sv_pkg::*;
+
+   // Internal interface (unconnected)
+   sv_if_ported if_ported(.clk(clk));
+
+   // Grab a program
+   v_sv_pgm pgm();
+
+endmodule
+
+"
+"// DESCRIPTION: Verilog-Perl: Example Verilog for testing package
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2000-2012 by Wilson Snyder.
+
+module v_hier_sub (/*AUTOARG*/
+   input clk,
+   input [3:0] avec,\t// Comment for v_hier_sub, avec
+   output [3:0] qvec\t/* Comment for v_hier_sub, qvec */
+   );
+
+   parameter FROM_DEFPARAM = 1;
+
+   supply1 \ta1;
+
+   v_hier_subsub #(
+\t\t   .IGNORED('sh20)
+\t\t   )
+     \\subsub0 (
+\t      // Outputs
+\t      .q\t\t(qvec[0]),
+\t      // Inputs
+\t      .a\t\t(a1));  // Comment for subsub cell
+
+
+   generate
+      genvar \tK, K_UNUSED;
+      for (K=0; K<1; K=K+1) begin : genloop
+\t // By pin position, inside generate
+\t v_hier_subsub subsub2 (qvec[2], 1'b0);
+      end
+   endgenerate
+
+   function foo;
+      (* attribute *)
+      /* synopsys metacommenttest */
+      input not_part_of_pinlist;
+      foo = not_part_of_pinlist;
+   endfunction
+
+endmodule
+"
+"// DESCRIPTION: Verilog::Preproc: Example source code
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012-2012 by Wilson Snyder.
+//
+// Test -F option in vppreproc.
+
+module bar(output wire y, input wire x);
+   assign y = x;
+endmodule // bar
+"
+"// The lack of a newline on the next line is intentional
+blah-no-newline-here>"
+"// DESCRIPTION: Verilog::Preproc: Example source code
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2007-2012 by Wilson Snyder.
+
+text.
+
+`include ""notfound""
+"
+"// DESCRIPTION: Verilog::Preproc: Example source code
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2000-2012 by Wilson Snyder.
+
+module t_86_vhier_tick_sub;
+endmodule
+"
+"// DESCRIPTION: Verilog-Perl: Example Verilog for testing package
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2006-2012 by Wilson Snyder.
+
+module v_v2k
+  #(parameter WIDTH = 16) (
+    input clk,
+    input rst,
+    input [WIDTH:0] \t sig1,
+    output reg [WIDTH:0] sig2
+   );
+
+   always @(clk) begin
+      if (rst) begin
+\t sig2 <= #1 0;
+      end
+      else begin
+\t sig2 <= #1 sig1;
+      end
+   end
+
+   // Multidim, bug1206
+   wire [1:2] [3:4]   netmd;
+   v_v2k_sub sub (.net1 (netmd[1]));
+
+endmodule
+
+module v_v2k_sub
+  (
+   input [3:4] net1
+   );
+endmodule
+"
+"// DESCRIPTION: Verilog::Preproc: Example source code
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2000-2012 by Wilson Snyder.
+
+module t_86_vhier_tick;
+
+   `define t_86_vhier_tick_sub FOOBAR_NOT_FOUND
+   t_86_vhier_tick_sub sub ();
+
+endmodule
+"
+"// DESCRIPTION: Verilog-Perl: Example Verilog for testing package
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2000-2012 by Wilson Snyder.
+
+module v_hier_top2 (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   v_hier_noport noport ();
+
+   inout [2:0] iosig/* synthesis useioff = 1 //*synthesis fpga_attr = ""BLAH=ON""//* synthesis fpga_pin = ""A22""*/;/* synthesis aftersemi*/ // NetListName=F12_IO
+
+endmodule
+"
+"// DESCRIPTION: Verilog-Perl: Example Verilog for testing package
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2009-2012 by Wilson Snyder.
+
+program v_sv_pgm;
+   int in_pgm;
+endprogram
+"
+"// DESCRIPTION: Verilog-Perl: Example Verilog for testing package
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2000-2012 by Wilson Snyder.
+
+// ENCRYPT_ME
+
+module example (/*AUTOARG*/
+   // Outputs
+   z,
+   // Inputs
+   a, b
+   );
+
+   // See http://www.veripool.org
+   // for what AUTOARG and friends can do for you!
+
+   /*Comment // test*/
+   //
+
+   input a;
+   input b;
+
+   output z;
+
+   wire result = a|b;
+
+   wire z = result;
+
+endmodule
+"
+"// Not legal:
+// end : ADDRESS_TEST_BLOCK             // See 9.8.1
+// `define at EOF with no newline
+
+module bug26141 ();
+   wire [0:3] b;
+   wire a = b[2];
+endmodule
+
+module bug26940 ();
+   (* attribute *)
+   assign q = {1\'b0,a} +{1\'b0,b};
+
+   adder u_add (.q(q),.a(d),.b(d));
+   initial begin
+      # 1;
+      q=0;
+      if (q!=0) $stop;
+   end
+endmodule
+
+module bug26968 ();
+   reg [4:0]  vect = 5\'b10100;
+   wire [4:0] tmp = { vect[0], vect[1], vect[2], vect[3], vect[4] };
+   initial begin
+      #1 $display(""vect=%b, tmp=%b"", vect, tmp);
+   end
+endmodule
+
+module bug26969 (input [31:0] ad, output [15:0] regff, input [31:0] read);
+   bufif0 ad_drv [31:0] (ad, {16\'b0, regff}, read);
+endmodule
+
+module bug26970;
+   parameter A = 2\'b1, B = 3\'b0;
+   parameter x = {B,B,B,A,A,B};
+endmodule
+
+module bug26997;
+   MUX_REG_8x8 PAGE_REG_B3 (
+\t\t\t    .CLK\t(CLK),
+\t\t\t    /*
+\t\t\t     .IN\t(DATA_RES[31:24]),
+\t\t\t     .OUT\t(PAGE[31:24]),
+\t\t\t     .EN_IN\t(EN_B3),
+\t\t\t     .EN_OUT\t(PAGE_SEL),
+\t\t\t     */
+\t\t\t    .TC\t(),
+\t\t\t    .TD\t(),
+\t\t\t    .TQ\t());
+endmodule
+
+module bug27013;
+   submod u1(0);
+   submod u2(1);
+endmodule
+
+module bug27036;
+   reg [2:0]  a_fifo_cam_indices[3:0], lt_fifo_cam_indices[5:0];
+   wire [2:0] db0_a_fifo_cam_indices = a_fifo_cam_indices[0];
+endmodule
+
+module bug27037;
+   reg mem[12:2];
+   reg [7:0] i;
+endmodule
+
+module bug27039;
+   integer i;
+endmodule
+
+module bug27045(
+    input clk, input reset,
+    input [7:0] d,
+    output reg [7:0] q );
+   parameter \t     REG_DELAY = 0;
+   always @(posedge clk or posedge reset)
+     q <= #(REG_DELAY*2) d;
+endmodule
+
+module bug27062 (input D, output Q);
+   p(Q, D);
+endmodule
+
+`timescale 1ns/1ns
+
+module bug27066;
+   integer i;
+   time    t;
+   realtime rt;
+   function integer toint;
+      input integer y;
+      input [15:0] x;
+      toint = x|y;
+   endfunction
+endmodule
+
+module bug27067;
+    initial $monitor( ""%T %b %b %b"", $time, clk1, clko1, clko2 );
+    initial forever @( negedge clk1 ) dclk1ff <= #50 ~ dclk1ff;
+endmodule
+
+module bug27072(
+    output reg sum,
+    input wire ci);
+endmodule
+
+`resetall
+module spec;
+   specify
+      specparam
+\tTac = 0.1,
+\tTcs = 0.2;
+      if ( !B & !M )
+\t( posedge CLK => (  Q[0] : 1\'bx )) = ( Tac, Tcs );
+      $width (negedge CLK &&& EN, Tac, 0, notif_clk);
+      ( in1 => q ) = (3, 4);
+      ( in1 +=> q ) = Tac;
+      ( a, b, c *> q1, q2) = 10;
+      ( s +*> q ) = Tcs;
+   endspecify
+endmodule
+
+module bugevent;
+   event e;
+   initial ->e;
+   always @ (e && e) $write(""Legal\
+"");
+endmodule
+
+module bugio (input [31:0] a, a2, output [15:0] o, o2, input ibit);
+endmodule
+
+module buglocal;
+   always #(cyclehalf) begin
+      clk <= ~clk;
+   end
+   always @(*) begin end
+   initial force flag = 0;
+   initial #(delta+0.5) CLRN <= 1;
+   assign (weak0,weak1) VDD=1\'b0;
+   assign (weak0,weak1) VSS=1\'b1;
+   wire [71:0] #1 xxout = xxin;
+   initial #1000_000 $finish;
+   initial $display($time,,""Double commas are stupid"");
+   initial for (counter[3:0] = 4\'h0; counter[3:0] < limit[3:0];
+\t\tcounter[3:0] = counter[3:0] + 4\'h1) $write();
+   always @(posedge(clk && !xclk) or negedge(clk && xclk) or reset) $write();
+
+   nmos   # (PullTime, PullTime, 0) (PT,PU,1\'b1);
+   pulldown (strong0) pullinst (r);
+
+   defparam x.y.z.PAR = 1;
+
+   cdrv #5.0 clk(clk);
+
+   initial PI = 3.1415926535_8979323846;
+
+   always val = @ eventid 1\'h1;
+
+   always dly = # (2:3:4) 5\'h6 ;
+
+   wire     \\33escapeneeded = 1\'b1;
+   wire     \\33escapenewlineend
+\t    = 1\'b1;
+   wire     \
+oescapenewlineend
+\t    = 1\'b1;
+   wire     \
+oescapespaceend = 1\'b1;
+
+endmodule
+
+module v2kparam
+  #(parameter WIDTH = 1,
+    parameter LENGTH = 1, LENGTH2 = 1)
+   (output [WIDTH-1:0] myout,
+    input  [LENGTH-1:0] myin, myinb
+    );
+   assign myout = myin ^ myinb ^ $callemptyparens();
+endmodule
+
+module foreqn (in);
+   input [1:0] in;
+   reg        a,b;
+   reg [1:0]  c;
+   always for ({a,c[0]} = in; a < 1\'b1; {b,c[1]} = in) begin
+   end
+   always for ({a,c[in]} = 0; a < 1\'b1; {b,c[in]} = 2\'b10) begin
+   end
+endmodule
+
+module colonslash;
+   always @*
+     case (cond&4\'b1110)
+       \'h0://Error
+\t t = 7;
+       \'h2:/*Another comment*/
+\t     t = 6;
+       \'h4: t = 5;
+     endcase
+endmodule
+
+module enums;
+   enum {red, yellow, green} light;
+   enum integer {IDLE, XX=\'x, S1=\'b01, S2=\'b10} state, next;
+   enum {bronze=3, silver, gold} medal;
+   enum { add=10, sub[5], jmp[6:8] } E1;
+   typedef enum {NOPE, YUP} boolean;
+   enum  logic [1:0] {IDLE, DIR} STATE, NSTATE;
+endmodule
+
+module invec (
+    output logic novec,
+    output logic [7:0] range,
+    output logic [1:0] [7:0] arrayAndRange,
+    output logic [2:0] [1:0] [7:0] arrayAndArrayAndRange,
+    output reg signed novec2
+\t      );
+endmodule
+
+module bug34575;
+   wire a,b,c,d;
+   assign #(0,0)         a = 1;
+   assign #(0:1:2)       b = 1;
+   assign #(0:1:2,0:1:2) c = 1;
+   assign #(0:1:2,0)     d = 1;
+endmodule
+
+module bug34649 (name);
+       output reg name = 0;
+endmodule
+module bug34649b (
+       output reg name = 0
+\t\t );
+endmodule
+module bug10;
+   initial begin
+      x += 1;
+      x -= 1;
+      x /= 1;
+      x *= 1;
+      x |= 1;
+      x ^= 1;
+      x <<= 1;
+      x >>= 1;
+      x <<<= 1;
+      x >>>= 1;
+      y = x++;  // Part of expression
+      y = ++x;
+      y = x--;
+      y = --x;
+      x++; // Statement
+      ++x;
+      x--;
+      --x;
+   end
+endmodule
+
+module bug33;
+   integer i;
+   initial begin
+      unique case (i)
+      endcase
+      priority case (i)
+      endcase
+      if (i) begin end else begin end
+   end
+endmodule
+
+module bug16;
+   timeunit 0.1ns;
+   timeprecision 1ns;
+endmodule
+
+parameter bug39 = 0;
+
+`default_nettype none
+`pragma foo = bar
+`default_nettype wire
+
+module bug64;
+   parameter integer  a=1,b=2;
+   parameter real     c=3.0;
+   parameter realtime d=4.0;
+   parameter time     e=5.0;
+endmodule
+
+module bug166;
+   assign {{o1,o2},o3,o4,{o5,o6}} = {{i1,i2},i3,i4,{i5,i6}};
+endmodule
+
+module coverage20090318;
+   task atask;
+      begin end
+   endtask
+endmodule
+
+module svsig;
+   function int count (input logic [3:0] d);
+      automatic int count = d[0]+d[1]+d[2]+d[3];
+      for (int i=0; i<4; i++) begin
+\t if (d[i]) count++;
+      end
+      return (count);
+   endfunction
+   task automatic autoconst;
+      const int CONS = 8;
+      $display(""CONS=%x\
+"", CONS);
+      $display(""Another stmt\
+"");
+   endtask
+endmodule
+
+module bug_empty_func_param;
+   //function int intfunc(int a=0, b=1);
+   //   return a+b;
+   //endfunction
+   always_comb begin
+      foo = funccall();
+      foo = intfunc(a, b);
+      foo = intfunc(a, .b(b));
+      foo = intfunc(.b(b), .a(a));
+   end
+endmodule
+
+module dotted_funcs;
+   initial ram.dotTask(addr[31:0],ramdata);  // Call task
+   initial zz = ram.a.dotFunc(foo);  // Call function
+endmodule
+
+module var_only_in_block;
+   initial begin : named
+      integer only_a_var_in_blk;
+   end
+endmodule
+
+module v2k_vec_no_vec
+  ( input [2:0] VEC,
+    VEC2,  \t\t// No direction, no port, no data type; inherits
+    input NOVEC,\t// No direction, no data type; use `default_nettype
+    input ARY [1:0],
+    NOARY2,\t\t// Array doesn\'t inherit
+    logic STILL_IN,\t// No direction, data type; inherits direction
+    input logic TYPED\t// Logic type
+    );
+   task t (input [2:0] FVEC, FVEC2,
+\t   input NOVEC);
+      begin end
+   endtask
+endmodule
+
+module bugfor;
+   initial for (a=0;a;) begin end
+endmodule
+
+module bug85 #(parameter type T_DATA = byte)
+   (data);
+   input T_DATA data;
+   sub #(.T_DATA( T_DATA ))
+   sub (.data(data));
+endmodule
+
+module bugmodportcomma (,a,);
+   input a;
+endmodule
+
+module bug168;
+   initial $display(""\
+Warning!  This is a\\
+              string with a line\\
+              continuation\\
+              at time %0d PS"", $time);
+endmodule
+
+module bug183
+  #(parameter NUM = 9
+    , WIDTH = 8
+    ) (  input logic  [NUM-1:0][WIDTH-1:0] a
+\t , output logic  [WIDTH-1:0]        sum
+\t );
+   localparam NLOG =
+                    (NUM <=     2) ?  1
+                    : (NUM <=  1024) ? 10
+                    : 0;
+   typedef logic [WIDTH-1:0] val_t;
+   val_t [NLOG:0][NUM-1:0] tree;
+endmodule
+
+module bug192;
+   covergroup cg192 @(posedge cclk);
+      count_tag_busy: coverpoint countones_tag_busy {
+\t bins count[] = {[0:DEPTH]};
+      }
+   endgroup: cg192
+   cg192 cover_ts = new();   // also bug361
+endmodule
+
+function bit func_implied_in (bit i); g_bit = ~i; endfunction
+
+module sparam;
+   specparam delay = 10;
+endmodule
+
+// bug221
+sequence stable_before_s(sig, clks_before, clk, rst=1\'b0);
+    @(clk) !rst throughout(##1 $stable(sig)[*clks_before-1]);
+endsequence : stable_before_s
+
+property stable_window(sample, sig, clks_before, clks_after, clk=$default_clk ,rst=1\'b0);
+    @(clk) disable iff(rst)  ## clks_before  sample
+            |-> stable_before_s(sig, clks_before, clk, rst).ended ##1
+                    ($stable(sig)[*clks_after]);
+endproperty : stable_window
+
+property never(prop, clk=$default_clk , rst=1\'b0);
+    @(clk) disable iff(rst) not(prop);
+endproperty : never
+
+property recur_triggers(trig, n, cond, clk=$default_clk , rst=1\'b0);
+    @(clk) disable iff (rst)
+     not ( !cond throughout (trig ##1 trig[->(n-1)]) );
+endproperty : recur_triggers
+
+property data_transfer(
+         start_ev, start_data, end_ev, end_data, clk=$default_clk ,rst=1\'b0);
+     logic [$bits(start_data)-1:0] local_data;
+     @(clk) disable iff (rst)
+     (start_ev, local_data = start_data) ##0
+       (end_ev or (!end_ev ##1 (!start_ev throughout end_ev[->1])))
+              |-> (local_data == end_data);
+endproperty : data_transfer
+
+module bug228;
+   wire net1, net2, net3;
+   nmos #(0:1:10, 0:1:10, 0:1:10) u (net1, net2, net3);
+endmodule
+
+module bug262 ( Y, {A1, A2} , B );
+   output  Y;
+   input   A1, A2, B;
+endmodule
+
+wire \\wire = bug282_must_keep_escape;
+
+module bug403_bug404;
+   // Simulators vary as to if ""(* /* */ )"" is legal or not
+   (* attr *) wire foo;
+   always @ (*) begin end
+   always @ (*
+\t     ) begin end
+endmodule
+
+/* multi
+ line
+ bug459*/
+
+module bug422;
+   generate
+   endgenerate
+endmodule
+
+module bug461;
+   generate
+      genvar  g;  // bug461
+      begin : topgen
+\t genvar  g2;
+\t genvar  g1;
+\t for (g=0; g<100; g++) begin end
+\t for (g=0; g<100; g++) begin end
+      end
+      for (g=0; g<100; g++) begin end
+   endgenerate
+endmodule
+
+module bug507;
+   integer x = 32\'d
+\t   6;
+endmodule
+
+// bug_msg_887;
+bind path.to.example_mod example_mod_fcov uexample_mod_fcov (.*);
+
+package bug586_pkg;
+   parameter B = 10;
+endpackage
+module non_bug586;  // Verilator only
+   input logic [bug586_pkg::B : 0] bvar;
+endmodule
+
+// bug_641
+import ""DPI-C"" function bit mydpi_bug641(input a_dpi_input);
+
+// .f() in function call
+module fbug;
+   initial a = f(, 1);
+   initial a = f(.s(1), .j(2));
+   initial a = f(.s(), .j());
+   initial a = f(2);
+   initial a = f();
+endmodule
+
+parameter bug671 = 5 : 10 : 20 ;
+
+module bug256;
+   always @(posedge clk) begin
+      myreg1 <= # 100 7\'d0;
+      myreg1 <= # 100 \'b0;
+      myreg1 <= # 100\'b0; // [#] [100] [\'b0]
+      myreg1 <= 100\'b0;
+   end
+endmodule
+
+module msg1491(A,B);
+   output A;
+   trireg (small) A;
+   output trireg B;
+endmodule
+"
+"module buffer (
+    output Z,
+    input  A);
+   buf u_buf(Z, A);
+endmodule
+
+module gate (
+    output Z,
+    input  A);
+   buffer u_buf(Z, A);
+endmodule
+"
+"// DESCRIPTION: Verilog-Perl: Example Verilog for testing package
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2000-2012 by Wilson Snyder.
+
+module v_hier_noport;
+   reg internal;
+endmodule
+"
+"// DESCRIPTION: Verilog-Perl: Example Verilog for testing package
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2009-2012 by Wilson Snyder.
+
+`ifndef _V_SV_PKG_
+ `define _V_SV_PKG_
+
+package v_sv_pkg;
+   typedef logic [7:0]  byte_t;
+endpackage
+
+`endif // guard
+"
+"// DESCRIPTION: Verilog::Preproc: Example source code
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012-2012 by Wilson Snyder.
+//
+// Test -F option in vppreproc.
+// This is the top level module.
+
+module foo(output wire y, input wire x);
+   bar i_bar(y, x);
+endmodule // foo
+"
+"// DESCRIPTION: Verilog-Perl: Example Verilog for testing package
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2003 by Wilson Snyder.
+
+module pinorder4();
+   wire b_i;
+   wire d_o;
+   wire [7:0] a_i;
+   wire [31:0] IPCD_const = 32'h1;
+
+   assign      a_i = 0;
+   assign      b_i = 0;
+
+   foo foo1( .y(b_i), .x(a_i), .abcconst(3'h0), .noconnect(),
+\t     .def(IPCD_const));
+   foo foo3( b_i, a_i, 3'h0, , IPCD_const);
+   foo2 foo2( b_i, a_i[0], d_o);
+
+endmodule
+
+module foo2(/*AUTOARG*/
+   // Outputs
+   x,
+   // Inputs
+   z, y
+   );
+   input z;
+   input y;
+   output x;
+   reg x;
+   always @(z or y) x = z & y;
+endmodule
+
+module foo (/*AUTOARG*/
+   // Inputs
+   y, x, abcconst, noconnect, def
+   );
+   input y;
+   input x;
+   input [2:0] abcconst;
+   input signed [3:0] noconnect;
+   input [31:0] def;
+endmodule
+
+module bug278
+  (
+   output wire ow,
+   inout wire iow,
+   input wire iw);
+endmodule
+"
+"`define ThirtyTwo 32
+
+module v_comments ( a,                // Pragma for a
+\t\t    b,                // pragma for b
+\t\t    c,
+\t\t    d, d1, d2, d3 );
+   input a;                     // comment for a
+   inout [10:0] b;
+   output [0:10] c;             // comment for c
+   output [ ((2*`ThirtyTwo) - 1) : 0 ] d;
+   output [ `ThirtyTwo : 0 ] d1;
+   output [ ( MATH - 1 ): 0 ] d2;
+   output [ `ThirtyTwo - 1: 0 ] d3;
+
+   reg           d;
+   reg [11:0]    e;             // Comment for e
+
+endmodule
+
+// 'Third' below must attach to 'b' becase there's no ) or , after b.
+module v_bug917  // modcmt
+  (input wire  a, // a-First
+   output wire m // m-Second
+   ,
+   output wire b // b-Third
+   );
+   // Third
+endmodule
+
+module v_bug917p
+  (input wire  a, // a-First
+   output wire b); // b-Secondparen
+   // Third
+endmodule
+"
+"// 1800-2009 mantis1769
+module mantis1769 #(N=1);
+   if (N < 1) $error(""Bad N value %d"", N);
+endmodule
+// 1800-2009 mantis1134
+module mantis1134_decoder
+  #(BITS = 3, localparam OUT_BITS = 1 << BITS)
+   (input [BITS-1:0] A, output reg [OUT_BITS-1:0] Y);
+   assign Y = 1 << A;
+endmodule
+// 1800-2009 mantis907
+module mantis907_default_parameter
+  #(REQUIRED);
+endmodule
+module mantis1619_default_input (input integer deflt = 10);
+endmodule
+module global_anal;  // Don\'t be anal about ""global"" in old code
+   integer global = 1;
+   global clocking z @(posedge clk);  // But still get it right
+   endclocking
+endmodule
+module bug400;
+   assert property
+   ( @(posedge clk)
+     disable iff (rst || $past (rst,1,,@(posedge clk)) || $isunknown(rst))
+     ""assert 0"");
+endmodule
+
+// dobbie
+package pkga;
+endpackage
+package pkgb;
+endpackage
+module impbegin
+  import pkga::*;
+   import pkgb::*;
+   (input foobar);
+endmodule
+"
+"/* This file contains some instantiations of an unknown module that use bit vectors. */
+
+module top(i,o);
+   input  [31:0] i;
+   output [31:0] o;
+
+   wire [3:0] \t somebus, someotherbus;
+   wire \t somenet_1,somenet_2,somenet_3;
+   wire [29:0] somewidebus;
+
+   parameter SOMEPARAM = 10;
+
+   assign somewidebus=i[31:2];
+   assign o[1]=somenet_1;
+   assign o[2]=somenet_2;
+   assign o[0]=1'b0;
+   assign o[3]=someotherbus[2];
+   assign o[28:4]=25'b0;
+   assign o[31]=~somenet_1;
+
+   mod instmod_1 (
+        .a(somebus),
+        .y(somenet_1)
+   );
+
+   mod instmod_2 (
+        .a(somebus),
+        .y(someotherbus[2])
+   );
+
+   mod instmod_3 (
+        .a(somewidebus[24:21]),
+        .y(somenet_2)
+   );
+
+   mod instmod_4 (
+        .a(i[31:27]),
+        .y(o[29])
+   );
+
+   mod instmod_5 (
+        .a({somenet_1,3'b101,someotherbus[2],somewidebus[2:1]}),
+        .y(o[30])
+   );
+
+   mod instmod_6 (
+        .a({somenet_1,3'b101,{someotherbus[2],someotherbus[2]},somewidebus[2:1]}),
+        .y(o[30])
+   );
+
+   mod instmod_7 (
+        .a(somebus[{SOMEPARAM_3[1],SOMEPARAM_3[0]}]),
+        .y(someotherbus[2])
+   );
+
+endmodule
+"
+"// DESCRIPTION: Verilog::Preproc: Example source code
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2000-2012 by Wilson Snyder.
+
+`define EMPTY_TRUE
+`ifndef EMPTY_TRUE
+  `error ""Empty is still true""
+`endif
+
+`define A
+`ifdef A
+  $display(""1A"");
+ `ifdef C
+  $display(""%Error: 2C"");
+ `elsif A
+  $display(""2A"");
+  `ifdef C
+  $display(""%Error: 3C"");
+  `elsif B
+  $display(""%Error: 3B"");
+  `else
+  $display(""3AELSE"");
+  `endif
+ `else
+  $display(""%Error: 2ELSE"");
+ `endif
+`elsif B
+  $display(""%Error: 1B"");
+  `ifdef A
+  $display(""%Error: noC"");
+  `elsif A
+  $display(""%Error: noB"");
+  `else
+  $display(""%Error: noELSE"");
+  `endif
+`elsif C
+  $display(""%Error: 1C"");
+`else
+  $display(""%Error: 1ELSE"");
+`endif
+"
+"// DESCRIPTION: Verilog-Perl: Example Verilog for testing package
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2000-2012 by Wilson Snyder.
+
+// surefire lint_off UDPUNS
+
+primitive v_hier_prim (/*AUTOARG*/
+   // Outputs
+   q,
+   // Inputs
+   a
+   );
+   output q;
+   input a;
+
+   table
+      0 : 1;
+      1 : 0;
+   endtable
+
+endprimitive
+
+`celldefine
+module bug27070();
+  `define W 4
+  parameter TAP = `W'b1001;
+endmodule
+`endcelldefine
+
+`celldefine
+module bug893();
+   reg r;
+   initial r <=#1 '0;
+endmodule
+`endcelldefine
+"
+"// DESCRIPTION: Verilog::Preproc: Example source code
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2000-2012 by Wilson Snyder.
+   text.
+
+//===========================================================================
+// Includes
+
+//===========================================================================
+// Defines
+
+`define DEF_A3
+`define DEF_A1
+// DEF_A0 set by command line
+   wire [3:0] q = {
+\t\t   `ifdef DEF_A3 1\'b1 `else 1\'b0 `endif ,
+\t\t   `ifdef DEF_A2 1\'b1 `else 1\'b0 `endif ,
+\t\t   `ifdef DEF_A1 1\'b1 `else 1\'b0 `endif ,
+\t\t   `ifdef DEF_A0 1\'b1 `else 1\'b0 `endif
+\t\t   };
+
+text.
+
+`define FOOBAR  foo /*this */ bar   /* this too */
+`define FOOBAR2  foobar2 // but not
+`FOOBAR
+`FOOBAR2
+
+`define MULTILINE first part \\
+  \t\tsecond part \\
+  \t\tthird part
+
+`define MOREMULTILINE {\\
+\t\t       a,\\
+\t\t       b,\\
+\t\t       c}
+
+/*******COMMENT*****/
+`MULTILINE
+`MOREMULTILINE
+Line_Preproc_Check `__LINE__
+
+//===========================================================================
+
+`define syn_negedge_reset_l or negedge reset_l
+
+`define DEEP deep
+`define DEEPER `DEEP `DEEP
+`DEEPER
+
+`define nosubst NOT_SUBSTITUTED
+`define WITHTICK ""`nosubst""
+""Inside: `nosubst""
+`WITHTICK
+
+`define withparam(a, b) a b LLZZ a b
+`withparam(x,y)
+`withparam(`withparam(p,q),`withparam ( r , s ))
+
+`withparam(firstline
+\t,
+\tcomma"",""line)
+
+`define withquote(a, bar) a bar LLZZ ""a"" bar
+`withquote( x , y)  // Simulators disagree here; some substitute ""a"" others do not
+
+`define noparam (a,b)
+`noparam(a,b)
+
+`define msg(x,y) `""x: `\\`""y`\\`""`""
+$display(`msg(left side, right side))
+
+`define foo(f) f``_suffix
+`foo(bar)  more
+
+`define zap(which)   \\
+\t$c(""Zap(\\"""",which,""\\"");"");
+`zap(bug1);
+`zap(""bug2"");
+
+/* Define inside comment: `DEEPER and `WITHTICK */
+// More commentary: `zap(bug1); `zap(""bug2"");
+
+//======================================================================
+// display passthru
+
+`define ls left_side
+`define rs right_side
+`define noarg  na
+`define thru(x) x
+`define thruthru `ls `rs\t// Doesn\'t expand
+`define msg(x,y) `""x: `\\`""y`\\`""`""
+   initial begin
+      //$display(`msg( \\`, \\`));  // Illegal
+      $display(`msg(pre `thru(thrupre `thru(thrumid) thrupost) post,right side));
+      $display(`msg(left side,right side));
+      $display(`msg( left side , right side ));
+      $display(`msg( `ls , `rs ));
+      $display(`msg( `noarg , `rs ));
+      $display(`msg( prep ( midp1 `ls midp2 ( outp ) ) , `rs ));
+      $display(`msg(`noarg,`noarg`noarg));
+      $display(`msg( `thruthru , `thruthru ));   // Results vary between simulators
+      $display(`msg(`thru(),));  // Empty
+      $display(`msg(`thru(left side),`thru(right side)));
+      $display(`msg( `thru( left side ) , `thru( right side ) ));
+      $display(`""standalone`"");
+
+      // Unspecified when the stringification has multiple lines
+`define twoline first \\
+      second
+      $display(`msg(twoline, `twoline));
+      //$display(`msg(left side, \\ right side \\ ));  // Not sure \\{space} is legal.
+      $write(""*-* All Finished *-*\
+"");
+      $finish;
+   end
+endmodule
+
+//======================================================================
+// rt.cpan.org bug34429
+
+`define ADD_UP(a,c)          \\
+wire  tmp_``a = a; \\
+wire  tmp_``c = tmp_``a + 1; \\
+assign c = tmp_``c ;
+
+module add1 ( input wire d1, output wire o1);
+ `ADD_UP(d1,o1)   // expansion is OK
+endmodule
+module add2 ( input wire d2, output wire o2);
+ `ADD_UP( d2 , o2 )  // expansion is bad
+endmodule
+
+ `define check(mod, width, flopname, gate, path) \\
+   generate for (i=0; i<(width); i=i+1) begin \\
+      psl cover {  path.d[i] & ~path.q[i] & !path.cond & (gate)} report `""fondNoRise: mod.flopname`""; \\
+      psl cover { ~path.d[i] &  path.q[i] & !path.cond & (gate)} report `""fondNoFall: mod.flopname`""; \\
+   end endgenerate
+
+// parameterized macro with arguments that are macros
+ `define MK\t\tm5k.f
+ `define MF\t\t`MK .ctl
+ `define CK_fr\t(`MF.alive & `MF.alive_m1)
+
+   `check(m5kc_fcl, 3, _ctl_mvldx_m1, `CK_fr,\t`MF._ctl_mvldx_m1)\t// ignorecmt
+
+//======================================================================
+// Quotes are legal in protected blocks.  Grr.
+module prot();
+`protected
+    I!#r#e6<_Q{{E2+]I3<[3s)1@D|\'E\'\'i!O?]jD>Jo_![Cl)
+    #nj1]p,3^1~,=""E@QZB\\T)eU\\pC#C|7=\\$J$##A[@-@{Qk]
+`endprotected
+endmodule
+
+module prot2();
+`pragma protect begin_protected
+`pragma protect encrypt_agent = ""Whatever agent""
+`pragma protect encrypt_agent_info = ""1.2.3""
+`pragma protect data_method = ""aes128-cbc""
+`pragma protect key_keyowner = ""Someone""
+`pragma protect key_keyname = ""somekey"", key_method = ""rsa""
+`pragma protect key_block encoding = (enctype = ""base64"")
+   wefjosdfjklajklasjkl
+`pragma protect data_block encoding = (enctype = ""base64"", bytes = 1059)
+    I!#r#e6<_Q{{E2+]I3<[3s)1@D|\'E\'\'i!O?]jD>Jo_![Cl)
+    #nj1]p,3^1~,=""E@QZB\\T)eU\\pC#C|7=\\$J$##A[@-@{Qk]
+`pragma protect end_protected
+`pragma reset protect
+endmodule
+
+//======================================================================
+// macro call with define that has comma
+`define REG_H   6
+`define REG_L   7
+`define _H      regs[`REG_H]
+`define _L      regs[`REG_L]
+`define _HL     {`_H, `_L}
+`define EX_WRITE(ad, da)      begin addr <= (ad); wdata <= (da); wr <= 1; end
+`define EX_READ(ad)           begin addr <= (ad); rd <= 1; end
+
+`EX_READ((`_HL + 1)) and `EX_WRITE((`_HL), rdata)
+`EX_READ(`_HL + 1)
+`EX_WRITE(`_HL, rdata)  more
+
+//======================================================================
+// include of parameterized file
+`define INCNAME ""t_preproc_inc4.vh""
+`include `INCNAME
+`ifndef T_PREPROC_INC4
+ `error ""No Inc4""
+`endif
+`undef T_PREPROC_INC4
+
+`ifdef NOT_DEFINED_INC
+ `include NOT_DEFINED_INC
+`endif
+
+//======================================================================
+// macro call with , in {}
+
+`define xxerror(logfile, msg) $blah(logfile,msg)
+`xxerror(""ab,cd"",""e,f"");
+`xxerror(this.logfile, vec);
+`xxerror(this.logfile, vec[1,2,3]);
+`xxerror(this.logfile, {blah.name(), "" is not foo""});
+
+//======================================================================
+// pragma/default net type
+
+`pragma foo = 1
+`default_nettype none
+`default_nettype uwire
+
+//======================================================================
+// Ifdef
+
+`define EMPTY_TRUE
+`ifndef EMPTY_TRUE
+  `error ""Empty is still true""
+`endif
+Line_Preproc_Check `__LINE__
+
+//======================================================================
+// bug84
+
+`define ARGPAR(a,  // Hello, comments MIGHT not be legal
+  /*more,,)cmts*/ b  // But newlines ARE legal... who speced THAT?
+  ) (a,b)
+`ARGPAR(p,q)
+`ARGPAR( //Here
+\t      x,
+  y   //Too
+  )
+Line_Preproc_Check `__LINE__
+
+//======================================================================
+// defines split arguments
+
+`define BEGIN begin
+`define END end
+`define BEGINEND `BEGIN`END
+`define quoteit(x) `""x`""
+`BEGIN`END   // 2001 spec doesn\'t require two tokens, so ""beginend"" ok
+`BEGINEND    // 2001 spec doesn\'t require two tokens, so ""beginend"" ok
+`quoteit(`BEGIN`END)  // No space ""beginend""
+
+//======================================================================
+// bug106
+`define \\esc`def got_escaped
+`ifdef \\esc`def
+  `\\esc`def
+`endif
+Not a \\`define
+
+//======================================================================
+// misparsed comma in submacro
+`define sb bee
+`define appease_emacs_paren_matcher (
+`define sa(l) x,y)
+`define sfoo(q,r) q--r
+`sfoo(`sa(el),`sb)  submacro has comma paren
+
+//======================================================================
+// bug191
+`define bug191(bits) $display(""bits %d %d"", $bits(foo), bits);
+`bug191(10)
+
+//======================================================================
+// 1800-2009
+`define UDALL
+`ifndef PREDEF_COMMAND_LINE `error ""Test setup error, PREDEF_COMMAND_LINE pre-missing"" `endif
+`undefineall
+`ifdef UDALL `error ""undefineall failed"" `endif
+`ifndef PREDEF_COMMAND_LINE `error ""Deleted too much, no PREDEF_COMMAND_LINE"" `endif
+
+//======================================================================
+// bug202
+`define FC_INV3(out, in)\t\t\t\t\t\\
+  `ifdef DC\t\t\t\t\t\t\t\\
+     cell \\inv_``out <$typeof(out)> (.a(<in>), .o(<out>));\t\\
+      /* multi-line comment\t\t\t\t\t\\
+\t multi-line comment */\t\t\t\t\t\\
+  `else\t\t\t\t\t\t\t\t\\
+    `ifdef MACRO_ATTRIBUTE\t\t\t\t\t\\
+      (* macro_attribute = `""INV (out``,in``)`"" *)\t\t\\
+    `endif\t\t\t\t\t\t\t\\
+     assign out = ~in ;\t\t\t\t\t\t\\
+  `endif
+
+`FC_INV3(a3,b3)
+
+`define /* multi\t\\
+\t line1*/\t\\
+ bug202( i /*multi\t\\
+\t   line2*/\t\\
+     )\t\t\t\\
+   /* multi\t\t\\
+      line 3*/\t\t\\
+   def i\t\t\\
+
+`bug202(foo)
+
+//======================================================================
+
+`define CMT1 // verilator NOT IN DEFINE
+`define CMT2 /* verilator PART OF DEFINE */
+`define CMT3 /* verilator NOT PART
+\t        OF DEFINE */
+`define CMT4 /* verilator PART \\
+\t        OF DEFINE */
+`define CMT5 // CMT NOT \\
+  also in  // BUT TEXT IS \\
+  also3  // CMT NOT
+
+1 `CMT1 (nodef)
+2 `CMT2 (hasdef)
+3 `CMT3 (nodef)
+4 `CMT4 (nodef)
+5 `CMT5 (nodef)
+`define NL HAS a NEW \\
+LINE
+`NL
+
+//======================================================================
+
+`define msg_fatal(log, msg)  \\
+   do \\
+      /* synopsys translate_off */ \\
+`ifdef NEVER \\
+  `error ""WTF"" \\
+`else \\
+      if (start(`__FILE__, `__LINE__)) begin \\
+`endif \\
+\t message(msg); \\
+      end \\
+      /* synopsys translate_on */ \\
+   while(0)
+
+`define msg_scen_(cl)   cl``_scen
+`define MSG_MACRO_TO_STRING(x) `""x`""
+
+EXP: clxx_scen
+`msg_scen_(clxx)
+EXP: clxx_scen
+`MSG_MACRO_TO_STRING(`msg_scen_(clxx))
+`define mf(clx) `msg_fatal(this.log, {""Blah-"", `MSG_MACRO_TO_STRING(`msg_scen_(clx)), "" end""});
+EXP: do if (start(""verilog/inc1.v"", 25)) begin  message({""Blah-"", ""clx_scen"", "" end""}); end  while(0);
+`mf(clx)
+
+//======================================================================
+
+`define makedefine(name) \\
+   `define def_``name   This is name \\
+   `define def_``name``_2 This is name``_2 \\
+
+`makedefine(fooed)
+`ifndef def_fooed  `error ""No def_fooed"" `endif
+//`ifndef def_fooed_2  `error ""No def_fooed_2"" `endif
+EXP: This is fooed
+`def_fooed
+EXP: This is fooed_2
+`def_fooed_2
+
+//======================================================================
+`define NOPARAM() np
+`NOPARAM()
+`NOPARAM( )
+//======================================================================
+// It\'s unclear if the spec allows this; is text_macro_idenitfier before or after substitution?
+`define NODS_DEFINED
+`define NODS_INDIRECT(x) x
+`ifndef `NODS_INDIRECT(NODS_DEFINED)
+   `error ""Indirect failed""
+`endif
+`ifdef `NODS_INDIRECT(NODS_UNDEFINED)
+   `error ""Indirect2 failed""
+`endif
+//======================================================================
+// Metaprogramming
+`define REPEAT_0(d)
+`define REPEAT_1(d) d
+`define REPEAT_2(d) `REPEAT_1(d)d
+`define REPEAT_3(d) `REPEAT_2(d)d
+`define REPEAT_4(d) `REPEAT_3(d)d
+
+`define CONCAT(a, b) a``b
+`define REPEATC(n, d) `CONCAT(`REPEAT_, n)(d)
+`define REPEATT(n, d) `REPEAT_``n(d)
+
+`REPEATC(3, hello3 )
+`REPEATT(4, hello4 )
+//======================================================================
+// Include from stringification
+`undef T_PREPROC_INC4
+`define NODS_CONC_VH(m) `""m.vh`""
+`include `NODS_CONC_VH(t_preproc_inc4)
+`ifndef T_PREPROC_INC4 `error_here `endif
+//======================================================================
+// Defines doing defines
+// Note the newline on the end - required to form the end of a define
+`define DEFINEIT(d) d \\
+
+`define _DEFIF_Z_0 1
+`define DEFIF_NZ(d,n) `undef d `ifndef _DEFIF_Z_``n `DEFINEIT(`define d 1) `endif
+`DEFIF_NZ(TEMP,1)
+`ifndef TEMP  `error ""bad1"" `endif
+`DEFIF_NZ(TEMP,0)
+`ifdef TEMP  `error ""bad0"" `endif
+Line_Preproc_Check `__LINE__
+//======================================================================
+// Quoted multiline - track line numbers, and insure \\\
+ gets propagated
+`define MULQUOTE ""FOO \\
+  BAR ""
+`define MULQUOTE2(mq) `MULQUOTE mq `MULQUOTE
+Line_Preproc_Check `__LINE__
+`MULQUOTE2(""arg_line1 \\
+  arg_line2"")
+Line_Preproc_Check `__LINE__
+//======================================================================
+// bug283
+
+`define A a
+`define B b
+`define C c
+// EXP: abc
+`define C5 `A``b```C
+`C5
+`undef A
+`undef B
+`undef C
+
+`define XTYPE sonet
+`define XJOIN(__arg1, __arg2) __arg1``__arg2
+`define XACTION `XJOIN(`XTYPE, _frame)
+EXP: sonet_frame
+`XACTION
+//
+`define XFRAME frame
+`define XACTION2 `XJOIN(sonet_, `XFRAME)
+EXP: sonet_frame
+`XACTION2
+// This result varies between simulators
+`define sonet_frame other_frame
+`define XACTION3 `XTYPE``_frame
+EXP: sonet_frame
+`XACTION3
+
+// The existance of non-existance of a base define can make a difference
+`define QA_b zzz
+`define Q1 `QA``_b
+EXP: module zzz ; endmodule
+module `Q1 ; endmodule
+module `Q1 ; endmodule
+
+`define QA a
+EXP: module a_b ; endmodule
+module `Q1 ; endmodule
+module `Q1 ; endmodule
+
+//======================================================================
+// bug311
+integer/*NEED_SPACE*/foo;
+//======================================================================
+synth_test:
+// synopsys translate_off
+synthesis_turned_off
+// synthesis translate_on
+EXP: on
+//======================================================================
+// bug441
+module t;
+   //-----
+   // case provided
+   // note this does NOT escape as suggested in the mail
+`define LEX_CAT(lexem1, lexem2) lexem1``lexem2
+`define LEX_ESC(name) \
+ame  \\
+
+   initial begin : `LEX_ESC( `LEX_CAT(a[0],_assignment) )   $write(""GOT%%m=\'%m\' EXP=\'%s\'\
+"", ""t.\\\\`LEX_CAT(a[0],_assignment) "");   end
+   //-----
+   // SHOULD(simulator-dependant): Backslash doesn\'t prevent arguments from
+   // substituting and the \\ staying in the expansion
+   // Note space after name is important so when substitute it has ending whitespace
+`define ESC_CAT(name,name2) \
+ame``_assignment_``name2 \\
+
+   initial begin : `ESC_CAT( a[0],a[1] )   $write(""GOT%%m=\'%m\' EXP=\'%s\'\
+"", ""t.\\\\a[0]_assignment_a[1] "");   end
+`undef ESC_CAT
+   //-----
+`define CAT(a,b) a``b
+`define ESC(name) \\`CAT(name,suffix)
+   // RULE: Ignoring backslash does NOT allow an additional expansion level
+   // (Because ESC gets expanded then the \\ has it\'s normal escape meaning)
+   initial begin : `ESC(pp)   $write(""GOT%%m=\'%m\' EXP=\'%s\'\
+"", ""t.\\\\`CAT(pp,suffix) "");   end
+`undef CAT `undef ESC
+   //-----
+`define CAT(a,b) a``b
+`define ESC(name) \
+ame \\
+
+   // Similar to above; \\ does not allow expansion after substitution
+   initial begin : `ESC( `CAT(ff,bb) )   $write(""GOT%%m=\'%m\' EXP=\'%s\'\
+"", ""t.\\\\`CAT(ff,bb) "");   end
+`undef CAT `undef ESC
+   //-----
+`define ESC(name) \
+ame \\
+
+   // MUST: Unknown macro with backslash escape stays as escaped symbol name
+   initial begin : `ESC( `zzz )   $write(""GOT%%m=\'%m\' EXP=\'%s\'\
+"", ""t.\\\\`zzz "");   end
+`undef ESC
+   //-----
+`define FOO bar
+`define ESC(name) \
+ame \\
+
+   // SHOULD(simulator-dependant): Known macro with backslash escape expands
+   initial begin : `ESC( `FOO )    $write(""GOT%%m=\'%m\' OTHER_EXP=\'%s\'\
+ OUR_EXP=\'%s\'"", ""t.bar "",""t.\\\\`FOO "");  end
+   // SHOULD(simulator-dependant): Prefix breaks the above
+   initial begin : `ESC( xx`FOO )   $write(""GOT%%m=\'%m\' EXP=\'%s\'\
+"", ""t.\\\\xx`FOO "");  end
+`undef FOO `undef ESC
+   //-----
+   // MUST: Unknown macro not under call with backslash escape doesn\'t expand
+`undef UNKNOWN
+   initial begin : \\`UNKNOWN   $write(""GOT%%m=\'%m\' EXP=\'%s\'\
+"", ""t.\\\\`UNKNOWN "");   end
+   //-----
+   // MUST: Unknown macro not under call doesn\'t expand
+`define DEF_NO_EXPAND  error_dont_expand
+   initial begin : \\`DEF_NO_EXPAND   $write(""GOT%%m=\'%m\' EXP=\'%s\'\
+"", ""t.\\\\`DEF_NO_EXPAND "");   end
+`undef DEF_NO_EXPAND
+   //-----
+   // bug441 derivative
+   // SHOULD(simulator-dependant): Quotes doesn\'t prevent arguments from expanding (like backslashes above)
+`define STR(name) ""foo name baz""
+   initial $write(""GOT=\'%s\' EXP=\'%s\'\
+"", `STR(bar), ""foo bar baz"");
+`undef STR
+   //-----
+   // RULE: Because there are quotes after substituting STR, the `A does NOT expand
+`define STR(name) ""foo name baz""
+`define A(name) boo name hiss
+   initial $write(""GOT=\'%s\' EXP=\'%s\'\
+"", `STR(`A(bar)), ""foo `A(bar) baz"");
+`undef A  `undef STR
+   //----
+   // bug845
+`define SLASHED ""1//2.3""
+   initial $write(""Slashed=`%s\'\
+"", `SLASHED);
+   //----
+   // bug915
+`define BUG915(a,b,c) \\
+       $display(""%s%s"",a,`""b``c``\
+`"")
+   initial `BUG915(""a1"",b2,c3);
+endmodule
+//======================================================================
+// IEEE mandated predefines
+`undefineall  // undefineall should have no effect on these
+predef `SV_COV_START 0
+predef `SV_COV_STOP 1
+predef `SV_COV_RESET 2
+predef `SV_COV_CHECK 3
+predef `SV_COV_MODULE 10
+predef `SV_COV_HIER 11
+predef `SV_COV_ASSERTION 20
+predef `SV_COV_FSM_STATE 21
+predef `SV_COV_STATEMENT 22
+predef `SV_COV_TOGGLE 23
+predef `SV_COV_OVERFLOW -2
+predef `SV_COV_ERROR -1
+predef `SV_COV_NOCOV 0
+predef `SV_COV_OK 1
+predef `SV_COV_PARTIAL 2
+"
+"module v_recursive ();
+   parameter DEPTH = 1;
+   generate
+      if (DEPTH > 1) begin : rec
+\tv_recursive #(.DEPTH(DEPTH-1)) recurse ();
+      end
+   endgenerate
+endmodule
+"
+"// DESCRIPTION: Verilog-Perl: Example Verilog for testing package
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2009-2012 by Wilson Snyder.
+
+`include ""v_sv_pkg.v""
+
+interface v_sv_intf;
+   v_sv_pkg::byte_t byte_port;
+   v_sv_intf2 subintf(.*);
+endinterface
+
+interface v_sv_intf2;
+   v_sv_pkg::byte_t byte_port;
+   modport Master(input data, output addr);
+endinterface
+"
+"// DESCRIPTION: Example pli file for vpassert program
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2000-2012 by Wilson Snyder.
+
+`timescale 1ns/1ns
+
+module pli;
+   // A module called PLI is required, to contain the error counts
+   // This is required with the vpassert --nostop option, which this example uses
+   // By default (--stop), this file isn\'t needed at all
+
+   integer errors; initial errors = 0;
+   integer warnings; initial warnings = 0;
+
+   // Normally this would be 0 at startup, then become 1 after reset deasserts
+   // This prevents false assertion checks during reset
+   integer message_on; initial message_on = 1;
+
+   always @ (errors or warnings) begin
+`ifdef OPTIONAL_EXIT_ON_WARNING
+      if (errors!=0 || warnings!=0) begin
+\t $uinfo (0, ""Errors/warnings found, exiting!\
+"");
+\t $finish;
+      end
+`else
+      if (errors!=0) begin
+\t $uinfo (0, ""Errors found, exiting!\
+"");
+\t $finish;
+      end
+      else if (warnings!=0) begin
+\t $uinfo (0, {""Warnings found, "",""consider stopping!\
+""});
+      end
+`endif
+   end
+
+endmodule
+"
+"// DESCRIPTION: Verilog::Preproc: Example source code
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2000-2012 by Wilson Snyder.
+At file `__FILE__  line `__LINE__
+`include <t_preproc_inc3.vh>
+  "
+"// DESCRIPTION: Verilog-Perl: Example Verilog for testing package
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2000-2012 by Wilson Snyder.
+
+module v_hier_subsub (/*AUTOARG*/
+   // Outputs
+   q,
+   // Inputs
+   a
+   );
+   parameter IGNORED = 0;
+   input  signed a;
+   output q;
+   wire   q = a;
+
+   // Test protected
+`pragma protect begin_protected
+`pragma protect encrypt_agent = ""Whatever agent""
+`pragma protect encrypt_agent_info = ""1.2.3""
+`pragma protect data_method = ""aes128-cbc""
+`pragma protect key_keyowner = ""Someone""
+`pragma protect key_keyname = ""somekey"", key_method = ""rsa""
+`pragma protect key_block encoding = (enctype = ""base64"")
+   wefjosdfjklajklasjkl
+`pragma protect data_block encoding = (enctype = ""base64"", bytes = 1059)
+    I!#r#e6<_Q{{E2+]I3<[3s)1@D|\'E\'\'i!O?]jD>Jo_![Cl)
+    #nj1]p,3^1~,=""E@QZB\\T)eU\\pC#C|7=\\$J$##A[@-@{Qk]
+`pragma protect end_protected
+`pragma reset protect
+//""
+
+endmodule
+"
+"// DESCRIPTION: Verilog-Perl: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2009 by Wilson Snyder.
+
+`undefineall
+
+// Definitions as speced
+// Note there are trailing spaces, which spec doesn\'t show properly
+`define D(x,y) initial $display(""start"", x , y, ""end"");
+\'`D( ""msg1"" , ""msg2"" )\'
+\'initial $display(""start"", ""msg1""  , ""msg2"" , ""end"");\'
+\'`D( "" msg1"", )\'
+\'initial $display(""start"", "" msg1"" , , ""end"");\'
+\'`D(, ""msg2 "")\'
+\'initial $display(""start"",  , ""msg2 "", ""end"");\'
+\'`D(,)\'
+\'initial $display(""start"",  , , ""end"");\'
+\'`D(  ,  )\'
+\'initial $display(""start"",  , , ""end"");\'
+//`D(""msg1"") // ILLEGAL: only one argument
+//`D()       // ILLEGAL: only one empty argument
+//`D(,,)     // ILLEGAL: more actual than formal arguments
+
+// Defaults:
+`define MACRO1(a=5,b=""B"",c) $display(a,,b,,c);
+\'`MACRO1 ( , 2, 3 )\'
+\'$display(5,,2,,3);\'
+\'`MACRO1 ( 1 , , 3 )\'
+\'$display(1 ,,""B"",,3 );\'
+\'`MACRO1 ( , 2, )\'
+\'$display(5,,2,,);\'
+//`MACRO1 ( 1 )  // ILLEGAL: b and c omitted, no default for c
+
+`define MACRO2(a=5, b, c=""C"") $display(a,,b,,c);
+\'`MACRO2 (1, , 3)\'
+\'$display(5,,,,""C"");\'
+\'`MACRO2 (, 2, )\'
+\'$display(5,,2,,""C"");\'
+\'`MACRO2 (, 2)\'
+\'$display(5,,2,,""C"");\'
+
+`define MACRO3(a=5, b=0, c=""C"") $display(a,,b,,c);
+\'`MACRO3 ( 1 )\'
+\'$display(1 ,,0,,""C"");\'
+\'`MACRO3 ( )\'
+\'$display(5,,0,,""C"");\'
+//`MACRO3    // ILLEGAL: parentheses required
+
+`define DTOP(a,b) a + b
+\'`DTOP( `DTOP(b,1), `DTOP(42,a) )\'
+\'b + 1 + 42 + a\'
+
+// Local tests
+`define MACROQUOTE(a=""==)"",b=""(((("",c=() ) \'a b c\'
+`MACROQUOTE();
+\'""==)"" ""(((("" () \';
+
+// Also check our line counting doesn\'t go bad
+`define MACROPAREN(a=(6),
+\t\t   b=(eq=al),
+\t\t   c) \'a b c\'
+`MACROPAREN(
+
+
+
+\t    ,,
+
+
+\t    ZOT)
+HERE-`__LINE__ - Line71
+
+//======================================================================
+"
+"// DESCRIPTION: Verilog-Perl: Example Verilog for testing package
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2000-2012 by Wilson Snyder.
+
+`define hsub v_hier_sub
+
+module v_hier_top (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;\t/* pragma jsc_clk */
+
+   defparam sub.FROM_DEFPARAM = 2;
+   `hsub sub (/*AUTOINST*/
+\t      // Outputs
+\t      .qvec\t\t\t(qvec[3:0]),
+\t      // Inputs
+\t      .avec\t\t\t({avec[3],avec[2:0]}),
+\t      .clk\t\t\t(1'b0));
+
+   missing missing ();
+
+   v_recursive #(.DEPTH(3)) recursive ();
+
+   // Width checks, bug65
+   wire  \tWC_w1;
+   wire [0:0]   WC_w1b;
+   wire [2:0]   WC_w3;
+   wire [-1:2]  WC_w4;
+   localparam         WC_p32=0;
+   localparam [0:0]   WC_p1=0;
+   localparam [2:0]   WC_p3=0;
+   localparam [-1:2]  WC_p4=0;
+   localparam integer WC_pint=0;
+
+   // Assignments
+   wire  asn_clk;
+   assign asn_clk = clk;
+
+endmodule
+
+localparam  GLOBAL_PARAM = 1;
+
+// Local Variables:
+// eval:(verilog-read-defines)
+// End:
+"
+"package mypackage;
+   bit [7:0] pkg_addr;
+   bit [7:0] pkg_data;
+endpackage
+
+module times ();
+   time x;
+   initial x = 33ns;\t// Note no space
+endmodule : times
+
+interface itf #(parameter num_of_cli = 0);
+   logic blabla;
+   logic [7:0] addr, data[9];
+   modport Master(input data, date_delayed, output addr);
+endinterface : itf
+
+module test (
+   itf whole_int,
+   itf.test modported_int,
+   input logic clk, rst,
+   input logic d_in,
+   output logic d_out
+   );
+
+   import mypackage::*;
+
+   logic \td_int;
+   logic [7:0] \tdata_, bork[2];
+   assign      d_int = d_in + pkg_data;
+
+   assign  modported_int.data = data_;
+
+   always_ff @(posedge clk or negedge rst) begin
+      if (~rst) d_out <= \'0;
+      else     d_out <= d_int;
+   end
+
+   property p1;
+      @(posedge clk)
+\tdisable iff(!rst)
+\t  $rose(d_int) |-> ##1 d_int;
+   endproperty
+
+   //a1:   assert property(p1) else $warning(""\
+Property violated\
+"");
+   c1:     cover  property(p1)  $display(""\
+p1_cover\
+"");
+endmodule : test
+
+// Different ways of declaring pins/vars
+module line49_diff_pins1 (
+    input in_nw,\t\t// Input, no type
+    input [1:0] in_vec[2:0],\t// Input, implicit
+    input in_nvec,\t\t// Isn\'t vectorized
+    output logic out_logic,\t// Output and var
+    output out_also_logic\t// ""logic"" sticks
+ );
+endmodule
+module line49_diff_pins2 (in2_nw, in2_vec, out2reg);
+
+   input       in2_nw;
+   input [1:0] in2_vec [2:0];
+   output reg  out2_reg;
+   input signed in2_signed;
+
+   var \t\tvar1_imp;
+   var [1:0]\tvar1_imp_vec [2:0];
+   var reg\tvar1_imp_reg;
+   var logic\tvar1_imp_logic;
+endmodule
+
+program automatic first_prog;
+   int i;
+endprogram
+
+// Importing
+package imp_test_pkg;
+   typedef logic [7:0] byte_t;
+   typedef logic [15:0] word_t;
+   function afunc(integer w); afunc=0; endfunction
+endpackage
+module imp_test_mod;
+   import imp_test_pkg::byte_t;
+   byte_t some_byte;
+endmodule
+module imp_test_mod2;
+   import imp_test_pkg::*;
+   word_t some_word;
+endmodule
+module imp_test_mod3
+  ( input imp_test_pkg::word_t wordin );
+   localparam FROM_FUNC = imp_test_pkg::afunc(1);
+endmodule
+
+module var_unnamed_block;
+   initial begin
+      integer var_in_unnamed;
+   end
+endmodule
+
+module cell_with_typeparam;
+   addr #(.PARAMTYPE(integer)) acell ();
+endmodule
+
+module arrayed_wire;
+   wire [3:0][7:0] n2;
+endmodule
+
+task empty_task;  // sv design book
+endtask
+task empty_task2;  // sv design book
+   integer i;
+endtask
+
+task check_casts;
+   typedef integer integer_t;
+   sum = a + integer \'(3);
+   sum = a + integer_t \'(3);
+   sum = a + 10\'(3);
+endtask
+
+module comma_assign;
+   int n[1:2][1:3] = \'{\'{0,1,2}, \'{3{4}}};
+endmodule
+
+task typed_pattern;
+   typedef int triple [1:3];
+   $mydisplay(triple\'{0,1,2});
+endtask
+
+virtual class VclassWCopy;
+   extern function new();
+   virtual function VclassWCopy copy(input VclassWCopy src=null);
+   endfunction
+endclass : VclassWCopy
+function VclassWCopy::new();
+endfunction : new
+
+typedef class FwdClass;
+function bit [3:0] FwdClass::ffunc (bit [3:0] in);
+   ffunc = in;
+endfunction : ffunc
+
+function VclassWCopy VclassWCopy::copy
+  (input VclassWCopy to);
+   dst = new();
+endfunction : copy
+
+task foreach_memref;
+   bit [0:52] [7:0] mem;
+   // It\'s *not* legal according to the grammar to have dotted/package ids here
+   foreach (mem[i]) $write(""i=%x "", mem[i]); $display;
+endtask
+
+typedef class PreTypedefedClass;
+class PreTypedefedClass;
+   extern function new();
+endclass
+typedef class PreTypedefedClass;
+
+class NewInNew;
+  function new;
+     s_self = new;
+  endfunction : new
+endclass
+
+// std package
+class TryStd;
+   semaphore s1;
+   std::semaphore s2;
+   mailbox #(integer) m1;
+   std::mailbox m2;
+   process p1;
+   std::process p2;
+endclass
+
+module cg_test1;
+   covergroup counter1 @ (posedge cyc);
+      cyc_bined : coverpoint cyc {
+\t bins zero    = {0};
+\t bins low    = {1,5};
+\t bins mid   = {[5:$]};
+      }
+      value_and_toggle:
+\tcross cyc_value, toggle;
+   endgroup
+endmodule
+
+task randomize_dotted();
+   int\t    vbl;
+   assert(vbl.randomize());
+endtask
+
+module prop_parens;
+   LABEL: cover property (@(posedge clk) ((foo[3:0] == 4\'h0) & bar));
+endmodule
+
+class this_dot_tests;
+   task ass;
+      this.super.foo = this.bar;
+   endtask
+endclass
+
+module sized_out
+  #( parameter SZ = 4 )
+   ( output logic [SZ-1:0] o_sized );
+endmodule
+
+class solve_size;
+   rand byte arrayed[];
+   rand bit b;
+   // The dot below doesn\'t seem legal according to grammar, but
+   // the intent makes sense, and it appears in the VMM
+   constraint solve_a_b { solve arrayed.size before b; }
+endclass
+
+class vmm_stuff;
+   task examples;
+      void\'(this.a.funccall(x));
+      this.a.taskcall();
+      super.new(name2);
+   endtask
+   extern static local function bit foo1();
+   extern virtual protected function void foo2();
+   protected static string foo3;
+   extern function bit foo4();
+   static local bit foo5[string];
+endclass
+
+class vmm_cl_func_colon;
+   typedef enum int unsigned {FIRM} restart_e;
+   function void do_all(vmm_cl_func_colon::restart_e kind = vmm_cl_func_colon::FIRM);
+   endfunction
+   extern function int uses_class_type();
+endclass
+
+class vmm_cl_subenv;
+   extern protected virtual task do_reset(vmm_cl_func_colon::restart_e kind = vmm_cl_func_colon::FIRM);
+endclass
+
+task empty_comma;
+   extracomma1(,);
+   extracomma2(""a"",);
+   extracomma3(""a"",,""c"");
+   extracomma4(,""b"");
+endtask
+
+task vmm_more;
+   file_is_a_string(`__FILE__,`__LINE__);
+   foreach(this.text[i]) begin $display(""%s\
+"", this.text[i]); end
+   // Not part of 1800-2005 grammar, but likely in 1800-2009
+   queue = \'{};
+   -> this.item_taken;
+endtask
+
+// Extern Functions/tasks when defined must scope to the class they\'re in to get appropriate types
+function int vmm_cl_func_colon::uses_class_type(restart_e note_uses_class_type);
+   var restart_e also_uses_class_type;
+endfunction
+
+module hidden_checks;
+   typedef int T;
+   sub (.T(123));  // Different T
+   task hidden;
+      typedef bit T;  // Different T
+   endtask
+endmodule
+
+typedef struct packed signed {
+      rand int m_a;
+      bit [7:0] m_b;
+   } t_bug91;
+t_bug91 v_bug91;
+
+module bug98(interfacex x_if);
+   h inst_h(.push(x_if.pop));
+endmodule
+
+module bugas;
+   initial begin
+      ASSERT_CHK: assert (0) else $error(""%m -- not allowed %d"", 0);
+   end
+endmodule
+
+typedef enum [2:0] { ENUM_RANGED_VALUE } enum_ranged_t;
+
+typedef struct packed { logic val; } t_bug202_struct;
+typedef union packed { logic val; } t_bug202_union;
+
+class ln288;
+   extern virtual function string extvirtstr;
+   extern virtual task extvirttask;
+endclass
+
+class cl_to_init;
+  extern function new();
+  extern static function cl_to_init init();
+endclass
+function cl_to_init cl_to_init::init();
+endfunction
+function cl_to_init::new();
+endfunction
+cl_to_init cl_inited = cl_to_init::init();
+
+// pure virtual functions have no endfunction.
+virtual class pure_virt_func_class;
+   pure virtual function string pure_virt_func();
+   pure virtual task pure_virt_task();
+endclass
+
+class extend_base;
+   typedef enum { EN_A, EN_B } base_enum;
+   virtual function extend_base create(); return null; endfunction
+endclass
+class extended extends extend_base;
+   typedef base_enum be_t;  // type must come from base class
+   virtual function int create ();  // Must override base\'s create
+      be_t mye;
+   endfunction
+endclass
+
+task rand_with_ln320();
+   if (!randomize(v) with { v > 0 && v < maxval; }) begin end
+   if (randomize(null)) begin end
+endtask
+task apply_request(data_req, input bit randomize = 1);
+   if (randomize == 1) begin
+      data_req.randomize();  // Generic method, not std::randomize
+   end
+endtask
+
+task foreach_class_scope_ln330;
+   foreach (extended::some_array[i,j]) begin end
+endtask
+
+module clkif_334;
+   always @(posedge top.clk iff !top.clken_l) begin end
+endmodule
+
+module gen_ln338;
+   generate
+      case (P)
+\t32\'b0:    initial begin end
+\tdefault:  initial begin end
+      endcase
+   endgenerate
+endmodule
+
+module par_packed;
+   parameter logic [31:0] P1 [3:0] = \'{ 1, 2, 3, 4 } ; // unpacked array
+   wire struct packed { logic ecc; logic [7:0] data; } memsig;
+endmodule
+
+module not_a_bug315;
+   typedef int supply_net_t;
+   input int i;
+   input imp_test_pkg::byte_t i;
+   input supply_net_t bug316;
+endmodule
+
+module bins_bracket;
+   parameter N = 2;
+   covergroup cg_debitor @(posedge eclk);
+      count: coverpoint count iff (erst_n) {
+         // \'std\' overrides std:: package, which confuses VP
+\t //bins  std[] = { [0:N] };
+      }
+   endgroup
+endmodule
+
+virtual class ovm_void;
+endclass
+virtual class ovm_port_base #(type IF=ovm_void) extends ovm_void;
+endclass
+virtual class uvm_build_phase #(type BASE=ovm_void) extends BASE;
+   static const string type_name = ""uvm_build_phase"";
+endclass
+
+class bug627sub;
+endclass
+class bug627 #(type TYPE=bug627sub);
+  typedef TYPE types_t[$];
+  static function types_t f();
+      $display(""%s"", { TYPE::type_name });
+      return types;
+  endfunction
+endclass
+
+interface if_bug777;
+    wire a;
+    modport master (input a);
+    modport slave (output a);
+endinterface
+module bug777 (clk, ifport);
+   input clk;
+   if_bug777 ifport ();
+   if_bug777.mp ifportmp;
+   //if_bug777.mp ifportmp ();  // Not legal
+   // Currently unsupported, parens required so VP knows is instance
+   //if_bug777 ifport;
+endmodule
+module bug778 ();
+   virtual if_bug777.master bar;
+endmodule
+class cls778;
+   virtual if_bug777.master bar;
+endclass : cls778;
+
+module bug810 #(
+\t\t/*parameter*/ int unsigned DW = 32);
+endmodule
+interface test_if (input clk);
+endinterface
+
+module bug815 (
+\t       test_if bad[2]);
+endmodule
+
+module bug868 (ifmp);
+   if_bug777.master ifmp;
+endmodule
+"
+"// DESCRIPTION: Verilog-Perl: Example Verilog for testing package
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2010-2012 by Wilson Snyder.
+
+module 51_vrename_kwd;
+   wire do = foo;
+   wire \\esc[ape]d = foo;
+   wire \\do = foo;
+   initial $display(""foo"");
+   initial $display(""foo.foo"");
+   initial $display(""baz_foo"");
+   initial $display(""foo_baz"");
+endmodule
+"
+"// DESCRIPTION: Verilog::Preproc: Example source code
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2007-2012 by Wilson Snyder.
+
+a_front_matter;
+
+module a;
+   wire inside_module_a;  /* // double cmt */
+endmodule
+
+b_front_matter;
+
+`ifdef B_HAS_X
+module b;
+`elsif
+module b (input x);
+`endif
+   wire inside_module_b;
+   // synopsys translate_off
+   wire in_translate_off;
+   // synopsys translate_on
+endmodule
+"
+"Set Printing Existential Instances.
+Set Printing All.
+Goal let y:=0 in exists x:y=y, x = x.
+intros.
+eexists.
+rename y into z.
+unfold z at 1 2.
+(* should fail because the evar type depends on z *)
+Fail clear z.
+Abort.
+"
+"(* Checks that f_equal does not reduce the term uselessly *)
+(* Expected time < 1.00s *)
+
+Fixpoint stupid (n : nat) : unit :=
+match n with
+| 0 => tt
+| S n =>
+  let () := stupid n in
+  let () := stupid n in
+  tt
+end.
+
+Goal stupid 23 = stupid 23.
+Timeout 5 Time f_equal.
+Abort.
+"
+"(* Test the behaviour of hnf and simpl introduced in revision *)
+
+Parameter n:nat.
+Definition a:=0.
+
+Eval simpl in (fix plus (n m : nat) {struct n} : nat :=
+  match n with
+  | 0 => m
+  | S p => S (p + m)
+  end) a a.
+
+Eval hnf in match (plus (S n) O) with S n => n | _ => O end.
+
+"
+"Set Implicit Arguments.
+Unset Strict Implicit.
+
+Module M.
+  Definition a (s : Set) := s.
+  Print a.
+End M.
+
+Print M.a.
+
+Module K.
+  Definition app (A B : Set) (f : A -> B) (x : A) := f x.
+  Module N.
+    Definition apap (A B : Set) := app (app (A:=A) (B:=B)).
+    Print app.
+    Print apap.
+  End N.
+  Print N.apap.
+End K.
+
+Print K.app.
+Print K.N.apap.
+
+Module W := K.N.
+
+Print W.apap.
+"
+"(* Last line should not loop, even in the presence of eta-expansion in the *)
+(* printing mechanism *)
+(* Expected time < 1.00s *)
+
+Notation ""\'bind\' x <- y ; z"" :=(y (fun x => z)) (at level 99, x at
+  level 0, y at level 0,format ""\'[hv\' \'bind\'  x  <-  y ;  \'/\' z \']\'"").
+
+Definition f (g : (nat -> nat) -> nat) := g (fun x => 0).
+
+Time Check (fun g => f g).
+"
+"Module Type S. End S.
+Module Type T. Declare Module M:S. End T.
+Module N:S. End N.
+
+Module NN:T. Module M:=N. End NN.
+Module Type U := T with Module M:=NN.
+"
+"
+(* test the strength of pretyping unification *)
+
+Require Import List.
+Definition listn A n := {l : list A | length l = n}.
+Definition make_ln A n (l : list A) (h : (fun l => length l = n) l) :=
+  exist _ l h.
+"
+"Module Type TA.
+Parameter t : Set.
+End TA.
+
+Module Type TB.
+Declare Module A: TA.
+End TB.
+
+Module Type TC.
+Declare Module B : TB.
+End TC.
+
+Module Type TD.
+
+Declare Module B: TB .
+Declare Module C: TC
+   with Module B := B  .
+End TD.
+
+Module Type TE.
+Declare Module D : TD.
+End TE.
+
+Module Type TF.
+Declare Module E:  TE.
+End TF.
+
+Module G (D: TD).
+Module B' := D.C.B.
+End G.
+
+Module H  (F: TF).
+Module I := G(F.E.D).
+End H.
+
+Declare Module F:  TF.
+Module K := H(F).
+"
+"(* This example checks if printing nested let-in's stays in linear time *)
+(* Expected time < 1.00s *)
+
+Definition f (x : nat * nat) :=
+  let (a,b) := x in
+  let (a,b) := x in
+  let (a,b) := x in
+  let (a,b) := x in
+  let (a,b) := x in
+  let (a,b) := x in
+  let (a,b) := x in
+  let (a,b) := x in
+  let (a,b) := x in
+  let (a,b) := x in
+  let (a,b) := x in
+  let (a,b) := x in
+  let (a,b) := x in
+  let (a,b) := x in
+  let (a,b) := x in
+  let (a,b) := x in
+  let (a,b) := x in
+  let (a,b) := x in
+  let (a,b) := x in
+  let (a,b) := x in
+  let (a,b) := x in
+  let (a,b) := x in
+  0.
+
+Timeout 5 Time Print f.
+"
+"Module N.
+Definition f := plus.
+(* <Warning> : Syntax is discontinued *)
+Check (f 0 0).
+End N.
+Check (N.f 0 0).
+Import N.
+Check (f 0 0).
+Check (f 0 0).
+Module M := N.
+Check (f 0 0).
+Check (f 0 0).
+Import M.
+Check (f 0 0).
+Check (N.f 0 0).
+"
+"Goal Type = Type.
+  Fail match goal with |- ?x = ?x => idtac end.
+Abort.
+
+Goal Prop.
+  Fail match goal with |- Type => idtac end.
+Abort.
+
+Goal Prop = Set.
+  (* This should fail *)
+ Fail match goal with |- ?x = ?x => idtac x end.
+Abort.
+
+Goal Type = Prop.
+  (* This should fail *)
+  Fail match goal with |- ?x = ?x => idtac end.
+Abort.
+
+Goal Type = Set.
+  (* This should fail *)
+  Fail match goal with |- ?x = ?x => idtac end.
+Abort.
+"
+"(* The synthesis of the elimination predicate may fail if algebraic *)
+(* universes are not cautiously treated *)
+
+Check (fun b : bool => if b then Type else nat).
+
+(* Check correct use of if-then-else predicate annotation (cf BZ#690) *)
+
+Check fun b : bool =>
+ if b as b0 return (if b0 then b0 = true else b0 = false)
+ then refl_equal true
+ else refl_equal false.
+
+"
+"Set Universe Polymorphism.
+
+Record Type_Over (X : Type)
+:= { Domain :> Type;
+     proj : Domain -> X }.
+
+Definition Self_Over (X : Type)
+  := {| Domain := X; proj := (fun x => x) |}.
+
+Canonical Structure Self_Over. (* fails with Anomaly: Mismatched instance and context when building universe substitution. Please report. for polymorphic structures *)
+(* if monomorphic, Warning: No global reference exists for projection
+ valuefun x : _UNBOUND_REL_1 => x in instance Self_Over of proj, ignoring it. *)
+"
+"(* Syntax test - all possible kinds of module parameters *)
+
+Module Type SIG.
+End SIG.
+
+Module Type FSIG (X: SIG).
+End FSIG.
+
+Module F (X: SIG).
+End F.
+
+Module Q.
+End Q.
+
+(*
+#trace Nametab.push;;
+#trace Nametab.push_short_name;;
+#trace Nametab.freeze;;
+#trace Nametab.unfreeze;;
+#trace Nametab.exists_cci;;
+*)
+
+Module M01. End M01.
+Module M02 (X: SIG). End M02.
+Module M03 (X Y: SIG). End M03.
+Module M04 (X: SIG) (Y: SIG). End M04.
+Module M05 (X Y: SIG) (Z1 Z: SIG). End M05.
+Module M06 (X: SIG) (Y: SIG). End M06.
+Module M07 (X Y: SIG) (Z1 Z: SIG). End M07.
+Module M08 : SIG. End M08.
+Module M09 (X: SIG) : SIG. End M09.
+Module M10 (X Y: SIG) : SIG. End M10.
+Module M11 (X: SIG) (Y: SIG) : SIG. End M11.
+Module M12 (X Y: SIG) (Z1 Z: SIG) : SIG. End M12.
+Module M13 (X: SIG) (Y: SIG) : SIG. End M13.
+Module M14 (X Y: SIG) (Z1 Z: SIG) : SIG. End M14.
+Module M15 := F Q.
+Module M16 (X: FSIG) := X Q.
+Module M17 (X Y: FSIG) := X Q.
+Module M18 (X: FSIG) (Y: SIG) := X Y.
+Module M19 (X Y: FSIG) (Z1 Z: SIG) := X Z.
+Module M20 (X: FSIG) (Y: SIG) := X Y.
+Module M21 (X Y: FSIG) (Z1 Z: SIG) := X Z.
+Module M22 : SIG := F Q.
+Module M23 (X: FSIG) : SIG := X Q.
+Module M24 (X Y: FSIG) : SIG := X Q.
+Module M25 (X: FSIG) (Y: SIG) : SIG := X Y.
+Module M26 (X Y: FSIG) (Z1 Z: SIG) : SIG := X Z.
+Module M27 (X: FSIG) (Y: SIG) : SIG := X Y.
+Module M28 (X Y: FSIG) (Z1 Z: SIG) : SIG := X Z.
+"
+"Arguments eq [A].
+
+Fail Check (bool = true).
+"
+"(* Check that Match arguments are forbidden *)
+Ltac E x := apply x.
+Goal True -> True.
+Fail E ltac:(match goal with
+        |  |- _ => intro H
+        end).
+Abort.
+"
+"Module Type SET.
+  Axiom T : Set.
+  Axiom x : T.
+End SET.
+
+Set Implicit Arguments.
+Unset Strict Implicit.
+
+Module M (X: SET).
+  Definition T := nat.
+  Definition x := 0.
+  Definition f (A : Set) (x : A) := X.x.
+End M.
+
+Module N := M.
+
+Module Nat.
+  Definition T := nat.
+  Definition x := 0.
+End Nat.
+
+Module Z := N Nat.
+
+Check (Z.f 0).
+
+Module P (Y: SET) := N.
+
+Module Y := P Z Nat.
+
+Check (Y.f 0).
+
+
+
+"
+"
+"
+"(* example from bug 5345 *)
+Ltac break_tuple :=
+  match goal with
+  | [ H: context[let '(n, m) := ?a in _] |- _ ] =>
+    let n := fresh n in
+    let m := fresh m in
+    destruct a as [n m]
+  end.
+
+(* desugared version of break_tuple *)
+Ltac break_tuple' :=
+  match goal with
+  | [ H: context[match ?a with | pair n m => _ end] |- _ ] =>
+    let n := fresh n in
+    let m := fresh m in
+    idtac
+  end.
+
+Ltac multiple_branches :=
+  match goal with
+  | [ H: match _ with
+         | left P => _
+         | right Q => _
+         end |- _ ] =>
+    let P := fresh P in
+    let Q := fresh Q in
+    idtac
+  end.
+"
+"(* Used in Import.v to test the locality flag *)
+
+Definition f (A:Type) (a:A) := a.
+
+Local Arguments f [A]%type_scope _%type_scope.
+
+(* Used in ImportedCoercion.v to test the locality flag *)
+
+Local Coercion g (b:bool) := if b then 0 else 1.
+"
+"(* Check all variables are different in a Context *)
+Ltac X := match goal with
+          | x:_,x:_ |- _ => apply x
+          end.
+Goal True -> True -> True.
+intros.
+Fail X.
+Abort.
+"
+"(* ClearBody must check that removing the body of definition does not
+   invalidate the well-typabilility of the visible goal *)
+
+Goal True.
+set (n := 0) in *.
+set (I := refl_equal 0) in *.
+change (n = 0) in (type of I).
+Fail clearbody n.
+Abort.
+"
+"Set Primitive Projections.
+Set Implicit Arguments.
+Set Universe Polymorphism.
+
+Record category (A : Type) :=
+  { ob :> Type;
+    hom : ob -> ob -> Type
+  }.
+
+Record foo { A: Type } := { C : category A; x : ob C; y :> hom _ x x }.
+Definition comp A (C : category A) (x : C) (f : hom _ x x) := f.
+
+Definition bar A (f : @foo A) := @comp _ _ _ f.
+
+(* Toplevel input, characters 0-42:
+Error: Cannot find the target class. *)
+"
+"Fail Type (fun x : nat => match x return nat with
+                     | S x as b => S b
+                     end).
+"
+"Require Import ZArith.
+Check 32%Z.
+Check (eq_refl : 0x2a%Z = 42%Z).
+Check (fun f : nat -> Z => (f 0%nat + 0)%Z).
+Check (fun x : positive => Zpos (xO x)).
+Check (fun x : positive => (Zpos x + 1)%Z).
+Check (fun x : positive => Zpos x).
+Check (fun x : positive => Zneg (xO x)).
+Check (fun x : positive => (Zpos (xO x) + 0)%Z).
+Check (fun x : positive => (- Zpos (xO x))%Z).
+Check (fun x : positive => (- Zpos (xO x) + 0)%Z).
+Check (Z.of_nat 0 + 1)%Z.
+Check (0 + Z.of_nat (0 + 0))%Z.
+Check (Z.of_nat 0 = 0%Z).
+Check 0x0%Z : Z.
+Check 0x00%Z : Z.
+Check 0x01%Z : Z.
+Check 0x02%Z : Z.
+Check 0xff%Z : Z.
+Check 0xFF%Z : Z.
+Check (-0x0)%Z : Z.
+Check (-0x00)%Z : Z.
+Check (-0x01)%Z : Z.
+Check (-0x02)%Z : Z.
+Check (-0xff)%Z : Z.
+Check (-0xFF)%Z : Z.
+Check 0x0%xZ : Z.
+Check 0x00%xZ : Z.
+Check 0x01%xZ : Z.
+Check 0x02%xZ : Z.
+Check 0xff%xZ : Z.
+Check 0xFF%xZ : Z.
+Check (-0x0)%xZ%Z : Z.
+Check (-0x00)%xZ%Z : Z.
+Check (-0x01)%xZ : Z.
+Check (-0x02)%xZ : Z.
+Check (-0xff)%xZ : Z.
+Check (-0xFF)%xZ : Z.
+
+(* Check hexadecimal printing *)
+Open Scope hex_Z_scope.
+Check 42%Z.
+Check (-42)%Z.
+Check 0%Z.
+Check 42%xZ.
+Check (-42)%xZ.
+Check 0%xZ.
+Check 0x0%Z : Z.
+Check 0x00%Z : Z.
+Check 0x01%Z : Z.
+Check 0x02%Z : Z.
+Check 0xff%Z : Z.
+Check 0xFF%Z : Z.
+Check (-0x0)%Z : Z.
+Check (-0x00)%Z : Z.
+Check (-0x01)%Z : Z.
+Check (-0x02)%Z : Z.
+Check (-0xff)%Z : Z.
+Check (-0xFF)%Z : Z.
+Check 0x0 : Z.
+Check 0x00 : Z.
+Check 0x01 : Z.
+Check 0x02 : Z.
+Check 0xff : Z.
+Check 0xFF : Z.
+Check 0x0%xZ : Z.
+Check 0x00%xZ : Z.
+Check 0x01%xZ : Z.
+Check 0x02%xZ : Z.
+Check 0xff%xZ : Z.
+Check 0xFF%xZ : Z.
+Check (-0x0)%xZ%Z : Z.
+Check (-0x00)%xZ%Z : Z.
+Check (-0x01)%xZ : Z.
+Check (-0x02)%xZ : Z.
+Check (-0xff)%xZ : Z.
+Check (-0xFF)%xZ : Z.
+Close Scope hex_Z_scope.
+
+(* Submitted by Pierre Casteran *)
+Require Import Arith.
+Check (0 + Z.of_nat 11)%Z.
+"
+"Definition b := true.
+"
+"Module A.
+
+Record Foo := { foo : unit; bar : unit }.
+
+Definition foo_ := {|
+  foo := tt;
+  bar := tt
+|}.
+
+Definition foo0 (p : Foo) := match p with {| |} => tt end.
+Definition foo1 (p : Foo) := match p with {| foo := f |} => f end.
+Definition foo2 (p : Foo) := match p with {| foo := f; |} => f end.
+Definition foo3 (p : Foo) := match p with {| foo := f; bar := g |} => (f, g) end.
+Definition foo4 (p : Foo) := match p with {| foo := f; bar := g; |} => (f, g) end.
+
+End A.
+
+Module B.
+
+Record Foo := { }.
+
+End B.
+
+Module C.
+
+Record Foo := { foo : unit; bar : unit; }.
+
+Definition foo_ := {|
+  foo := tt;
+  bar := tt;
+|}.
+
+End C.
+
+Module D.
+
+Record Foo := { foo : unit }.
+Definition foo_ := {| foo := tt |}.
+
+End D.
+
+Module E.
+
+Record Foo := { foo : unit; }.
+Definition foo_ := {| foo := tt; |}.
+
+End E.
+
+Module F.
+
+Record Foo := { foo : nat * nat -> nat -> nat }.
+
+Definition foo_ := {| foo '(x,y) n := x+y+n |}.
+
+End F.
+"
+"(* Examples to check that the guard condition does not evaluate
+   irrelevant subterms *)
+(* Expected time < 1.00s *)
+Require Import Bool.
+
+Fixpoint slow n :=
+ match n with
+ | 0 => true
+ | S k => andb (slow k) (slow k)
+ end.
+
+Timeout 5 Time Fixpoint F n :=
+  match n with
+  | 0 => 0
+  | S k =>
+    if slow 100 then F k else 0
+  end.
+
+Fixpoint slow2 n :=
+ match n with
+ | 0 => 0
+ | S k => slow2 k + slow2 k
+ end.
+
+Timeout 5 Time Fixpoint F' n :=
+  match n with
+  | 0 => 0
+  | S k =>
+    if slow2 100 then F' k else 0
+  end.
+"
+"Search and.
+(* Anomaly: Mismatched instance and context when building universe substitution.
+Please report. *)
+"
+"Fail Check (nat : Type) : Set.
+(* Error:
+The term ""nat:Type"" has type ""Type"" while it is expected to have type
+""Set"" (Universe inconsistency). *)
+"
+"Structure type : Type := Pack { ob : Type }.
+Polymorphic Record category := { foo : Type }.
+Definition FuncComp := Pack category.
+Axiom C : category.
+
+Check (C : ob FuncComp). (* OK *)
+
+Canonical Structure FuncComp.
+
+Check (C : ob FuncComp).
+(* Toplevel input, characters 15-39:
+Error:
+The term ""C"" has type ""category"" while it is expected to have type
+ ""ob FuncComp"". *)
+"
+"
+(* To test PP of fixpoints *)
+Require Import Arith.
+Check fix a(n: nat): n<5 -> nat :=
+  match n return n<5 -> nat with
+    | 0 => fun _ => 0
+    | S n => fun h => S (a n (lt_S_n _ _ (lt_S _ _ h)))
+  end.
+
+"
+"(**********************************************************************)
+(* Test dependencies in constructors                                  *)
+(**********************************************************************)
+
+Check
+  (fun x : {b : bool | if b then True else False} =>
+   match x return (let (b, _) := x in if b then True else False) with
+   | exist _ true y => y
+   | exist _ false z => z
+   end).
+"
+"(* Non exhaustive pattern-matching *)
+
+Fail Check
+  (fun x =>
+   match x, x with
+   | O, S (S y) => true
+   | O, S x => false
+   | S y, O => true
+   end).
+"
+"Module M.
+  Module Type SIG.
+    Parameter T : Set.
+    Parameter x : T.
+  End SIG.
+  Module N : SIG.
+    Definition T := nat.
+    Definition x := 0.
+  End N.
+End M.
+
+Module N := M.
+
+Module Type SPRYT.
+  Module N.
+    Definition T := M.N.T.
+    Parameter x : T.
+  End N.
+End SPRYT.
+
+Module K : SPRYT := N.
+Module K' : SPRYT := M.
+
+Module Type SIG.
+  Definition T : Set := M.N.T.
+  Parameter x : T.
+End SIG.
+
+Module J : SIG := M.N.
+"
+"Tactic Notation ""complete"" tactic(tac) := tac; fail.
+
+Ltac f0 := complete (intuition idtac).
+(** FIXME: This is badly printed because of bug #3079.
+    At least we check that it does not fail anomalously. *)
+Print Ltac f0.
+
+Ltac f1 := complete f1.
+Print Ltac f1.
+
+Ltac f2 := complete intuition.
+Print Ltac f2.
+"
+"Definition a := 1.
+"
+"Set Printing Universes.
+
+Fixpoint CardinalityRepresentative (n : nat) : Set :=
+  match n with
+    | O => Empty_set
+    | S n\' => sum (CardinalityRepresentative n\') unit
+  end.
+(* Toplevel input, characters 104-143:
+Error:
+In environment
+CardinalityRepresentative : nat -> Set
+n : nat
+n\' : nat
+The term ""(CardinalityRepresentative n\' + unit)%type"" has type
+ ""Type (* max(Top.73, Top.74) *)"" while it is expected to have type
+""Set"". *)
+"
+"Record Foo : Set :=
+  {
+    A' : nat;
+    A : Prop := (A' = 0)
+  }. (* Anomaly: Uncaught exception Reduction.NotConvertible. Please report. *)
+"
+"(* subtyping verification in presence of  pseudo-circularity*)
+Module Type S. End S.
+Module Type T. Declare Module M:S. End T.
+Module N:S. End N.
+Module NN <: T. Module M:=N. End NN.
+
+Fail Module P <: T with Module M:=NN := NN.
+
+Module F (X:S) (Y:T with Module M:=X). End F.
+Fail Module G := F N N.
+"
+"Print Tables.
+Print ML Path.
+Print ML Modules.
+Print LoadPath.
+Print Graph.
+Print Coercions.
+Print Classes.
+Print nat.
+Print Term O.
+Print All.
+Print Grammar constr.
+Inspect 10.
+
+Section A.
+Coercion f (x : nat) : Prop := True.
+Print Coercion Paths nat Sortclass.
+
+Print Section A.
+
+End A.
+"
+"Set Implicit Arguments.
+Set Universe Polymorphism.
+
+Module success.
+  Unset Primitive Projections.
+
+  Record group :=
+    { carrier : Type;
+      id : carrier }.
+
+  Notation ""1"" := (id _) : g_scope.
+
+  Delimit Scope g_scope with g.
+  Bind Scope g_scope with carrier.
+
+  Section foo.
+    Variable g : group.
+    Variable comp : carrier g -> carrier g -> carrier g.
+
+    Check comp 1 1.
+  End foo.
+End success.
+
+Module failure.
+  Set Primitive Projections.
+
+  Record group :=
+    { carrier : Type;
+      id : carrier }.
+
+  Notation ""1"" := (id _) : g_scope.
+
+  Delimit Scope g_scope with g.
+  Bind Scope g_scope with carrier.
+
+  Section foo.
+    Variable g : group.
+    Variable comp : carrier g -> carrier g -> carrier g.
+
+    Check comp 1 1.
+    (* Toplevel input, characters 11-12:
+Error:
+In environment
+g : group
+comp : carrier g -> carrier g -> carrier g
+The term ""1"" has type ""nat"" while it is expected to have type ""carrier g"".
+    *)
+  End foo.
+End failure.
+"
+"(* Test bug 2168: ending section of some name was removing objects of the
+   same name *)
+
+Require Import make_notation.
+
+Check add2 3.
+"
+"Set Implicit Arguments.
+
+Require Import Logic.
+
+Global Set Universe Polymorphism.
+Global Set Asymmetric Patterns.
+Local Set Nonrecursive Elimination Schemes.
+Local Set Primitive Projections.
+
+Record prod (A B : Type) : Type :=
+  pair { fst : A; snd : B }.
+
+Check fun x : prod Set Set => eq_refl : x = pair (fst x) (snd x).
+"
+"Module A.
+Section\tB.
+Fail End A.
+(*End A.*)
+End B.
+End A.
+"
+"Check (nat + nat + {True}).
+Check ({True} + {True} + {True}).
+Check (nat + {True} + {True}).
+"
+"Set Primitive Projections.
+Set Nonrecursive Elimination Schemes.
+Record Foo (A : Type) := { bar : A -> A; baz : A }.
+
+Definition test (A : Type) (f : Foo A) := 
+  let (x, y) := f in x.
+
+Scheme foo_case := Case for Foo Sort Type.
+
+Definition test' (A : Type) (f : Foo A) :=
+  let 'Build_Foo _ x y := f in x.
+"
+"(* Check that the syntax for options works *)
+Set Implicit Arguments.
+Unset Strict Implicit.
+Set Strict Implicit.
+Unset Implicit Arguments.
+Test Implicit Arguments.
+
+Set Printing Coercions.
+Unset Printing Coercions.
+Test Printing Coercions.
+
+Set Silent.
+Unset Silent.
+Test Silent.
+
+Set Printing Depth 100.
+Test Printing Depth.
+
+Parameter i : bool -> nat.
+Coercion i : bool >-> nat.
+Add Printing Coercion i.
+Remove Printing Coercion i.
+Test Printing Coercion for i.
+
+Test Printing Let.
+Test Printing If.
+Remove Printing Let sig.
+Remove Printing If bool.
+
+Unset Printing Synth.
+Set Printing Synth.
+Test Printing Synth.
+
+Unset Printing Wildcard.
+Set Printing Wildcard.
+Test Printing Wildcard.
+"
+"(* Check that non logical object loading is done after registration of
+   the logical objects in the environment
+*)
+
+(* BZ#1118 (simplified version), submitted by Evelyne Contejean
+  (used to failed in pre-V8.1 trunk because of a call to lookup_mind
+   for structure objects)
+*)
+
+Module Type S. Record t : Set := { a : nat; b : nat }. End S.
+Module Make (X:S). Module Y:=X. End Make.
+"
+"Set Implicit Arguments.
+Set Universe Polymorphism.
+
+Record category :=
+  { ob : Type }.
+
+Existing Class category. (*
+Toplevel input, characters 0-24:
+Anomaly: Mismatched instance and context when building universe substitution.
+Please report. *)
+
+Record category' :=
+  { ob' : Type;
+    hom' : ob' -> ob' -> Type }.
+
+Existing Class category'. (*
+Toplevel input, characters 0-24:
+Anomaly: Mismatched instance and context when building universe substitution.
+Please report. *)
+"
+"Fail Type (fun x : nat => match x return nat with
+                     | S x as b => S b x
+                     end).
+"
+"Require Reals.
+Print Sorted Universes.
+"
+"Section A.
+Notation ""*"" := O (at level 8).
+Notation ""**"" := O (at level 99).
+Notation ""***"" := O (at level 9).
+End A.
+Notation ""*"" := O (at level 8).
+Notation ""**"" := O (at level 99).
+Notation ""***"" := O (at level 9).
+"
+"Set Ltac Backtrace.
+
+Ltac foo x := idtac x.
+Ltac bar x := fun y _ => idtac x y.
+Ltac baz := foo.
+Ltac qux := bar.
+Ltac mydo tac := tac ().
+Ltac rec x := rec.
+
+Goal True.
+  Fail foo.
+  Fail bar.
+  Fail bar True.
+  Fail baz.
+  Fail qux.
+  Fail mydo ltac:(fun _ _ => idtac).
+  Fail let tac := (fun _ => idtac) in tac.
+  Fail (fun _ => idtac).
+  Fail rec True.
+  Fail let rec tac x := tac in tac True.
+Abort.
+"
+"Require all_stdlib.
+Print Sorted Universes ""universes.txt"".
+"
+"Notation ""x ++ y"" := (plus x y) (only printing).
+
+Fail Check 0 ++ 0.
+
+Notation ""x + y"" := (max x y) (only printing).
+
+Check (eq_refl : 42 + 18 = 60).
+"
+"(* Test of inference of elimination predicate for ""if"" *)
+(* submitted by Robert R Schneck *)
+
+Axiom bad : false = true.
+
+Definition try1 : False :=
+  match bad in (_ = b) return (if b then False else True) with
+  | refl_equal => I
+  end.
+
+Definition try2 : False :=
+  match bad in (_ = b) return ((if b then False else True):Prop) with
+  | refl_equal => I
+  end.
+
+Definition try3 : False :=
+  match
+    bad in (_ = b) return ((fun b\' : bool => if b\' then False else True) b)
+  with
+  | refl_equal => I
+  end.
+"
+"(* Soumis par Pierre *)
+Print sig2.
+Check (exists x : nat, x = x).
+Check (fun b : bool => if b then b else b).
+"
+"Fail Type match 0 with
+     | x => 0
+     | O => 1
+     end.
+"
+"Module Type T.
+  Module Type U.
+    Module Type V.
+      Variable b : nat.
+    End V.
+    Variable a : nat.
+  End U.
+  Declare Module u : U.
+  Declare Module v : u.V.
+End T.
+
+Module F (t:T).
+End F.
+
+Module M:T.
+  Module Type U.
+    Module Type V.
+      Variable b : nat.
+    End V.
+    Variable a : nat.
+  End U.
+  Declare Module u : U.
+  Declare Module v : u.V.
+End M.
+
+Module FM := F M.
+"
+"(* Used in Notation.v to test import of notations from files in sections *)
+
+Notation ""\'Z\'"" := O (at level 9).
+Notation plus := plus.
+Notation succ := S.
+Notation mult := mult (only parsing).
+Notation less := le (only parsing).
+
+(* Test bug 2168: ending section of some name was removing objects of the
+   same name *)
+
+Notation add2 n:=(S n).
+Section add2.
+End add2.
+
+"
+"Definition b := false.
+"
+"(* This example checks the efficiency of pattern-matching compilation on simple cases *)
+(* Expected time < 1.00s *)
+
+Time Definition a400 n := match n with
+  S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S(S x))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) => x
+| _ => 0
+end.
+
+"
+"Reserved Notation ""x :-) y"" (at level 50, only printing).
+
+Notation ""x :-) y"" := (plus x y).
+
+Check 0 + 0.
+"
+"(* Test visibility of imported objects *)
+
+Require Import make_local.
+
+(* Check local implicit arguments are not imported *)
+
+Check (f nat 0).
+
+(* Check local arguments scopes are not imported *)
+
+Check (f nat (0*0)).
+"
+"(** Some LtacProf tests *)
+
+Set Ltac Profiling.
+Ltac multi := (idtac + idtac).
+Goal True.
+  try (multi; fail). (* Used to result in: Anomaly: Uncaught exception Failure(""hd""). Please report. *)
+Admitted.
+Show Ltac Profile.
+
+(* backtracking across profiler manipulation *)
+Unset Ltac Profiling.
+Reset Ltac Profile.
+
+Fixpoint slow (n : nat) : unit
+  := match n with
+     | 0 => tt
+     | S n => fst (slow n, slow n)
+     end.
+
+Ltac slow := idtac; let v := eval cbv in (slow 16) in idtac.
+Ltac multi2 :=
+  try (((idtac; slow) + (start ltac profiling; slow) + (idtac; slow) + (slow; stop ltac profiling; slow) + slow + (start ltac profiling; (idtac + slow); ((stop ltac profiling + idtac); fail))); slow; fail); slow; show ltac profile.
+Goal True.
+  multi2.
+Admitted.
+"
+"(* Non exhaustive pattern-matching *)
+
+Fail Check
+  (fun x =>
+   match x, x with
+   | O, S (S y) => true
+   | O, S x => false
+   | S y, O => true
+   end).
+"
+"
+Fail Type
+  (fun x : nat =>
+   match x return nat with
+   | S x as b => match x with
+                 | x => x
+                 end
+   end).
+"
+"(* Placeholder file for directory / file test *)
+"
+"(* Simple let-patterns *)
+Variable A B : Type.
+
+Definition l1 (t : A * B * B) : A := let \'(x, y, z) := t in x.
+Print l1.
+Definition l2 (t : (A * B) * B) : A := let \'((x, y), z) := t in x.
+Definition l3 (t : A * (B * B)) : A := let \'(x, (y, z)) := t in x.
+Print l3.
+
+Record someT (A : Type) := mkT { a : nat; b: A }.
+
+Definition l4 A (t : someT A) : nat := let \'mkT _ x y := t in x.
+Print l4.
+Print sigT.
+
+Definition l5 A (B : A -> Type) (t : sigT B) : B (projT1 t) :=
+  let \'existT _ x y := t return B (projT1 t) in y.
+
+Definition l6 A (B : A -> Type) (t : sigT B) : B (projT1 t) :=
+  let \'existT _ x y as t\' := t return B (projT1 t\') in y.
+
+Definition l7 A (B : A -> Type) (t : sigT B) : B (projT1 t) :=
+  let \'existT _ x y as t\' in sigT _ := t return B (projT1 t\') in y.
+
+Definition l8 A (B : A -> Type) (t : sigT B) : B (projT1 t) :=
+  match t with
+    existT _ x y => y
+  end.
+
+(** An example from algebra, using let\' and inference of return clauses
+   to deconstruct contexts. *)
+
+Record a_category (A : Type) (hom : A -> A -> Type) := {  }.
+
+Definition category := { A : Type & { hom : A -> A -> Type & a_category A hom } }.
+
+Record a_functor (A : Type) (hom : A -> A -> Type) (C : a_category A hom) := {  }.
+
+Notation "" x :& y "" := (@existT _ _ x y) (right associativity, at level 55) : core_scope.
+
+Definition functor (c d : category) :=
+  let \' A :& homA :& CA := c in
+  let \' B :& homB :& CB := d in
+    A -> B.
+
+Definition identity_functor (c : category) : functor c c :=
+  let \'A :& homA :& CA := c in
+    fun x => x.
+
+Definition functor_composition (a b c : category) : functor a b -> functor b c -> functor a c :=
+  let \'A :& homA :& CA := a in
+  let \'B :& homB :& CB := b in
+  let \'C :& homB :& CB := c in
+    fun f g =>
+      fun x => g (f x).
+"
+"(* L'algo d'inf\xc3\xa9rence du pr\xc3\xa9dicat doit g\xc3\xa9rer le K-r\xc3\xa9dex dans le type de b *)
+(* Probl\xc3\xa8me rapport\xc3\xa9 par Solange Coupet *)
+
+Section A.
+
+Variables (Alpha : Set) (Beta : Set).
+
+Definition nodep_prod_of_dep (c : sigT (fun a : Alpha => Beta)) :
+  Alpha * Beta := match c with
+                  | existT _ a b => (a, b)
+                  end.
+
+End A.
+"
+"(* Check that no toplevel ""unresolved evar"" flees through Declare
+   Implicit Tactic support (bug #1229) *)
+
+Goal True.
+(* should raise an error, not an anomaly *)
+set (x := _).
+"
+"(* ============================================== *)
+(*     To test compilation of dependent case      *)
+(*  Nested patterns                               *)
+(* ============================================== *)
+
+Type
+  match 0 as n return (n = n) with
+  | O => refl_equal 0
+  | m => refl_equal m
+  end.
+
+
+"
+"(* Simple let-in's *)
+Definition l1 := let P := 0 in P.
+Definition l2 := let P := nat in P.
+Definition l3 := let P := True in P.
+Definition l4 := let P := Prop in P.
+Definition l5 := let P := Type in P.
+
+(* Check casting of let-in *)
+Definition l6 := let P := 0:nat in P.
+Definition l7 := let P := True:Prop in P.
+Definition l8 := let P := True:Type in P.
+"
+"Definition toto (x : Set) := x.
+
+(* <Warning> : Grammar is replaced by Notation *)
+"
+"Definition a := 0.
+"
+"Require Export plik.
+
+Definition tutu (X : Set) := toto X.
+"
+"Require Import A.
+Fail Require Import B.
+"
+"Record test := build { field : nat }.
+Record test_r := build_r { field_r : nat }.
+Record test_c := build_c { field_c : nat }.
+
+Add Printing Constructor test_c.
+Add Printing Record test_r.
+
+Set Printing Records.
+
+Check build 5.
+Check {| field := 5 |}.
+
+Check build_r 5.
+Check build_c 5.
+
+Unset Printing Records.
+
+Check build 5.
+Check {| field := 5 |}.
+Check build_r 5.
+Check build_c 5.
+
+Set Printing Records.
+
+Record N := C { T : Type; _ : True }.
+Check fun x:N => let \'C _ p := x in p.
+Check fun x:N => let \'C T _ := x in T.
+Check fun x:N => let \'C T p := x in (T,p).
+
+Record M := D { U : Type; a := 0; q : True }.
+Check fun x:M => let \'D T _ p := x in p.
+Check fun x:M => let \'D T _ p := x in T.
+Check fun x:M => let \'D T p := x in (T,p).
+Check fun x:M => let \'D T a p := x in (T,p,a).
+Check fun x:M => let \'{|U:=T;a:=a;q:=p|} := x in (T,p,a).
+
+Module FormattingIssue13142.
+
+Record T {A B} := {a:A;b:B}.
+
+Module LongModuleName.
+  Record test := { long_field_name0 : nat;
+                  long_field_name1 : nat;
+                  long_field_name2 : nat;
+                  long_field_name3 : nat }.
+End LongModuleName.
+
+Definition c :=
+      {| LongModuleName.long_field_name0 := 0;
+         LongModuleName.long_field_name1 := 1;
+         LongModuleName.long_field_name2 := 2;
+         LongModuleName.long_field_name3 := 3 |}.
+
+Definition d :=
+ fun \'{| LongModuleName.long_field_name0 := a;
+         LongModuleName.long_field_name1 := b;
+         LongModuleName.long_field_name2 := c;
+         LongModuleName.long_field_name3 := d |} => (a,b,c,d).
+
+Check {|a:=0;b:=0|}.
+Check fun \'{| LongModuleName.long_field_name0:=_ |} => 0.
+Eval compute in {|a:=c;b:=d|}.
+Import LongModuleName.
+Eval compute in {|a:=c;b:=d|}.
+
+End FormattingIssue13142.
+
+Module ProjectionPrinting.
+
+Notation ""a +++ b"" := (a * b) (at level 40, format ""\'[v\' a \'/\' +++ \'/\' b \']\'"").
+
+Record R := { field : nat -> nat }.
+Set Printing Projections.
+Check fun x => 0 +++ x.(field) 0.
+
+End ProjectionPrinting.
+
+Module RecordImplicitParameters.
+
+(* Check that implicit parameters are treated independently of extra
+   implicit arguments (at some time they did not and it was failing at
+   typing time) *)
+
+Record R A := { f : A -> A }.
+Fail Check fun x => x.(f).
+
+End RecordImplicitParameters.
+"
+"Module M.
+  Definition t := nat.
+  Definition x := 0.
+End M.
+
+Print M.t.
+
+
+Module Type SIG.
+  Parameter t : Set.
+  Parameter x : t.
+End SIG.
+
+
+Module F (X: SIG).
+  Definition t := X.t -> X.t.
+  Definition x : t.
+    intro.
+    exact X.x.
+  Defined.
+  Definition y := X.x.
+End F.
+
+
+Module N := F M.
+
+Print N.t.
+Eval compute in N.t.
+
+
+Module N' : SIG := N.
+
+Print N'.t.
+Eval compute in N'.t.
+
+
+Module N'' <: SIG := F N.
+
+Print N''.t.
+Eval compute in N''.t.
+
+Eval compute in N''.x.
+
+
+Module N''' : SIG with Definition t := nat -> nat := N.
+
+Print N'''.t.
+Eval compute in N'''.t.
+
+Print N'''.x.
+
+
+Import N'''.
+
+Print t.
+"
+"(* Check for redundant clauses *)
+
+Fail Check
+  (fun x =>
+   match x, x with
+   | O, S (S y) => true
+   | S _, S (S y) => true
+   | _, S (S x) => false
+   | S y, O => true
+   | _, _ => true
+   end).
+"
+"Monomorphic Definition U1 := Type.
+Monomorphic Definition U2 := Type.
+
+Set Printing Universes.
+Definition foo : True.
+let t1 := type of U1 in
+let t2 := type of U2 in
+idtac t1 t2;
+pose (t1 : t2). exact I. 
+Defined.
+"
+"Module monomorphic.
+  Class Inhabited (A : Type) : Prop := populate { _ : A }.
+  Arguments populate {_} _.
+
+  Instance prod_inhabited {A B : Type} (iA : Inhabited A)
+           (iB : Inhabited B) :   Inhabited (A * B) :=
+    match iA, iB with
+      | populate x, populate y => populate (x,y)
+    end.
+  (* Error: In environment
+A : Type
+B : Type
+iA : Inhabited A
+iB : Inhabited B
+The term ""(A * B)%type"" has type ""Type"" while it is expected to have type
+""Prop"". *)
+End monomorphic.
+
+Module polymorphic.
+  Set Universe Polymorphism.
+  Class Inhabited (A : Type) : Prop := populate { _ : A }.
+  Arguments populate {_} _.
+
+  Instance prod_inhabited {A B : Type} (iA : Inhabited A)
+           (iB : Inhabited B) :   Inhabited (A * B) :=
+    match iA, iB with
+      | populate x, populate y => populate (x,y)
+    end.
+End polymorphic.
+"
+"Record PreCategory :=  Build_PreCategory\' { object :> Type }.
+Class Foo (X : Type) := {}.
+Class Bar := {}.
+Definition functor_category `{Bar} (C D : PreCategory)  `{Foo (object D)} : PreCategory.
+Admitted.
+Fail Definition functor_object_of `{Bar} (C1 C2 D : PreCategory) `{Foo (object D)}
+: functor_category C1 (functor_category C2 D) -> True.
+(** Anomaly: File ""toplevel/himsg.ml"", line ..., characters ...: Assertion failed.
+Please report. *)
+"
+"Module Type SIG.
+  Axiom A : Set.
+  Axiom B : Set.
+End SIG.
+
+Module M : SIG.
+  Definition A := nat.
+  Definition B := nat.
+End M.
+
+Module N <: SIG := M.
+
+Module TranspId (X: SIG) <: SIG with Definition A := X.A := X.
+Module OpaqueId (X: SIG) : SIG with Definition A := X.A := X.
+
+Module TrM := TranspId M.
+Module OpM := OpaqueId M.
+
+Print TrM.A.
+Print OpM.A.
+Print TrM.B.
+Print OpM.B.
+"
+"Fail Type
+  (fun x : nat =>
+   match x return nat with
+   | S x as b => match x with
+                 | x => S b x
+                 end
+   end).
+"
+"Set Primitive Projections.
+Record foo (T : Type) := { bar : T}.
+"
+"(* Bug #2169 *)
+
+Module FOO.
+
+Module M.
+ Definition T := nat.
+End M.
+
+Module Type S.
+ Parameter T : Set.
+End S.
+
+Module N : S with Definition T := nat := M.
+
+Print Module N.
+
+Set Short Module Printing.
+Print Module N.
+Unset Short Module Printing.
+
+End FOO.
+
+Module BAR.
+
+Module K. End K.
+Module Type KS. End KS.
+
+Module M.
+ Module T := K.
+End M.
+
+Module Type S.
+ Declare Module T : KS.
+End S.
+
+Module N : S with Module T := K := M.
+
+Print Module N.
+
+Set Short Module Printing.
+Print Module N.
+Unset Short Module Printing.
+
+End BAR.
+
+(* Bug #4661 *)
+
+Module QUX.
+
+Module Type Test.
+  Parameter t : Type.
+End Test.
+
+Module Type Func (T:Test).
+  Parameter x : T.t.
+End Func.
+
+Module Shortest_path (T : Test).
+Print Func.
+End Shortest_path.
+
+End QUX.
+
+Module A.
+Variant I := C : nat -> I.
+Record R := { n : nat }.
+End A.
+
+Print Module A.
+"
+"Definition T := Type.
+Definition U := Type.
+
+Module Type MT.
+  Parameter t : T.
+End MT.
+
+Module Type MU.
+  Parameter t : U.
+End MU.
+
+Module F (E : MT).
+  Definition elt :T := E.t.
+End F.
+
+Module G (E : MU).
+  Include F E.
+Print Universes. (* U <= T *)
+End G.
+Print Universes. (* Check if constraint is lost *)
+
+Module Mt.
+  Definition t := T.
+End Mt.
+
+Fail Module P := G Mt. (* should yield Universe inconsistency *)
+(* ... otherwise the following command will show that T has type T! *)
+(* Eval cbv delta [P.elt Mt.t] in P.elt. *)
+
+
+"
+"Definition Type2 := Type.
+Definition Type1 : Type2 := Type.
+Fail Definition Inconsistency : Type1 := Type2.
+"
+"
+Fail Definition Berry (x y z : bool) :=
+  match x, y, z with
+  | true, false, _ => 0
+  | false, _, true => 1
+  | _, true, false => 2
+  end.
+"
+"(* It is forbidden to erase a variable (or a local def) that is used in
+   the current goal. *)
+Section S.
+Let a := 0.
+Definition b := a.
+Goal b = b.
+Fail clear a.
+Abort.
+End S.
+"
+"Goal 0 = 1.
+match goal with
+| |- context [?v] =>
+  idtac v ; fail
+| _ => idtac 2
+end.
+Abort.
+"
+"(* Check that reset remains synchronised with the compilation unit cache *)
+(* See BZ#1030 *)
+
+Section multiset_defs.
+  Require Import Plus.
+End multiset_defs.
+Unset Implicit Arguments.
+Back 1.
+"
+"Set Printing Universes.
+Local Close Scope nat_scope.
+Check (fun ab : Prop * Prop => (fst ab : Prop) * (snd ab : Prop)).
+(* fun ab : Prop * Prop =>
+(fst (* Top.5817 Top.5818 *) ab:Prop) * (snd (* Top.5817 Top.5818 *) ab:Prop)
+     : Prop * Prop -> Prop *)
+Check (fun ab : Prop * Prop => (fst ab : Prop) * (snd ab : Prop) : Prop).
+(* Toplevel input, characters 51-84:
+Error: In environment
+ab : Prop * Prop
+The term
+ ""(fst (* Top.5833 Top.5834 *) ab:Prop) *
+  (snd (* Top.5833 Top.5834 *) ab:Prop)"" has type
+ ""Type (* max(Top.5829, Top.5830) *)"" while it is expected to have type
+ ""Prop"". *)
+"
+"(* Test visibility of coercions *)
+
+Require Import make_local.
+
+(* Local coercion must not be used *)
+
+Fail Check (0 = true).
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+`timescale 1ns / 1ps
+
+`define P 20 // clock period
+
+`define M     593         // M is the degree of the irreducible polynomial
+`define WIDTH (2*`M-1)    // width for a GF(3^M) element
+`define WIDTH_D0 1187
+
+module test_ram;
+
+\t// Inputs
+\treg clk;
+\treg reset;
+\treg sel;
+\treg [5:0] addr;
+\treg w;
+\treg [`WIDTH_D0:0] data;
+
+\t// Outputs
+\twire [`WIDTH_D0:0] out;
+\twire done;
+
+\t// Instantiate the Unit Under Test (UUT)
+\ttiny uut (
+\t\t.clk(clk), 
+\t\t.reset(reset), 
+\t\t.sel(sel), 
+\t\t.addr(addr), 
+\t\t.w(w), 
+\t\t.data(data), 
+\t\t.out(out), 
+\t\t.done(done)
+\t);
+
+\tinitial begin
+\t\t// Initialize Inputs
+\t\tclk = 0;
+\t\treset = 0;
+\t\tsel = 0;
+\t\taddr = 0;
+\t\tw = 0;
+\t\tdata = 0;
+
+\t\t// Wait 100 ns for global reset to finish
+\t\t#100;
+        
+\t\t// Add stimulus here
+        @ (negedge clk);
+        
+        // write
+        sel = 1; w = 1;
+        data = 198\'h115a25886512165251569195908560596a6695612620504191;
+        addr = 0;
+        #(`P);
+        data = 198\'h1559546442405a181195655549614540592955a15a26984015;
+        addr = 3;
+        #(`P);
+        // not write
+        w = 0;
+        data = 198\'h12222222222222222222222222222222222222222222222222;
+        addr = 3;
+        #(`P);
+        
+        // read
+        sel = 1; w = 0;
+        addr = 0;
+        #(`P);
+        if (out !== 198\'h115a25886512165251569195908560596a6695612620504191) begin
+            $display(""E""); $finish;
+        end
+
+        addr = 3;
+        #(`P);
+        if (out !== 198\'h1559546442405a181195655549614540592955a15a26984015) begin
+            $display(""E""); $finish;
+        end
+
+        #(`P);
+        
+        $display(""Good"");
+        $finish;
+\tend
+    
+    initial #100 forever #(`P/2) clk = ~clk;
+endmodule
+
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+`define M     503         // M is the degree of the irreducible polynomial
+`define WIDTH (2*`M-1)    // width for a GF(3^M) element
+`define WIDTH_D0 (1008-1)
+
+module pairing(clk, reset, sel, addr, w, update, ready, i, o, done);
+   input clk;
+   input reset; // for the arithmethic core
+   input sel;
+   input [5:0] addr;
+   input w;
+   input update; // update reg_in & reg_out
+   input ready;  // shift reg_in & reg_out
+   input i;
+   output o;
+   output done;
+   
+   reg [`WIDTH_D0:0] reg_in, reg_out;
+   wire [`WIDTH_D0:0] out;
+   
+   assign o = reg_out[0];
+   
+   tiny
+      tiny0 (clk, reset, sel, addr, w, reg_in, out, done);
+   
+   always @ (posedge clk) // write LSB firstly
+      if (update) reg_in <= 0;
+      else if (ready) reg_in <= {i,reg_in[`WIDTH_D0:1]};
+   
+   always @ (posedge clk) // read LSB firstly
+      if (update) reg_out <= out;
+      else if (ready) reg_out <= reg_out>>1;
+endmodule
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+`timescale 1ns / 1ps
+`define P 20 // clock period 
+`define M     593         // M is the degree of the irreducible polynomial
+`define WIDTH (2*`M-1)    // width for a GF(3^M) element
+`define WIDTH_D0 1187
+
+module test_tiny;
+
+\t// Inputs
+\treg clk;
+\treg reset;
+\treg sel;
+\treg [5:0] addr;
+\treg w;
+\treg [`WIDTH_D0:0] data;
+
+\t// Outputs
+\twire [`WIDTH_D0:0] out;
+\twire done;
+
+\t// Instantiate the Unit Under Test (UUT)
+\ttiny uut (
+\t\t.clk(clk), 
+\t\t.reset(reset), 
+\t\t.sel(sel), 
+\t\t.addr(addr), 
+\t\t.w(w), 
+\t\t.data(data), 
+\t\t.out(out), 
+\t\t.done(done)
+\t);
+
+\tinitial begin
+\t\t// Initialize Inputs
+\t\tclk = 0;
+\t\treset = 0;
+\t\tsel = 0;
+\t\taddr = 0;
+\t\tw = 0;
+\t\tdata = 0;
+
+\t\t// Wait 100 ns for global reset to finish
+\t\t#100;
+        
+\t\t// Add stimulus here
+        reset = 1; // keep FSM silent
+            // init x, y
+            write(3, 1186\'h088a6aa4a8aa80a9aa922965a92a56510856606aa6400649a6004866466928a20090908210195560a8162a52442029a44a68004a8168496a0a8a8564962a0948118a5599a29450214995828245914a099051991602550105228289686988621a1a9126648644619a66111a026452641169158a4686884aa212199582406600921229a5948802528289a62454a2566a4122586a496);
+            write(5, 1186\'h05448582294062429a891a6509092496844141090214064988646241904502a0225046a54851a05454020044881088a2092411592909289861049124644a964a6188014aa25869a09890401a924048815a1008421459455411a4a65094410615a524458901026a9108a468650515a5aa50468005881a29055980995a145995146909841aa18890902264628884421894959956195);
+            write(6, 1186\'h088a6aa4a8aa80a9aa922965a92a56510856606aa6400649a6004866466928a20090908210195560a8162a52442029a44a68004a8168496a0a8a8564962a0948118a5599a29450214995828245914a099051991602550105228289686988621a1a9126648644619a66111a026452641169158a4686884aa212199582406600921229a5948802528289a62454a2566a4122586a496);
+            write(7, 1186\'h05448582294062429a891a6509092496844141090214064988646241904502a0225046a54851a05454020044881088a2092411592909289861049124644a964a6188014aa25869a09890401a924048815a1008421459455411a4a65094410615a524458901026a9108a468650515a5aa50468005881a29055980995a145995146909841aa18890902264628884421894959956195);
+            /* read back. uncomment me if error happens */
+            /* read(3);
+            $display(""xp = %h"", out);
+            read(5);
+            $display(""yp = %h"", out);
+            read(6);
+            $display(""xq = %h"", out);
+            read(7);
+            $display(""yq = %h"", out);*/
+        reset = 0;
+        sel = 0; w = 0;
+        @(posedge done);
+        @(negedge clk);
+            read(9);
+            check(1186\'h20115a6958895a08585a412698a58250900a651a859448a4848125164545598a426119a09885802424154a08855a0042a168516099228606222540582026aa0a6029a88805a1888628856a2a64504120aa290491925284508921140a24a0a8641548a521512698985a610861a401208644612a4a52625119000006004518844899810191a056aaa680889958996508954685a0920);
+            read(10);
+            check(1186\'h228a9556506501a0258028a8856851a5466a205a2544849a12a10a018a40aaa461959859a4408245094969a44565a160a98229805169491120568121008a04918050a9022854868440662591221116889a9668a82aa84182a59025424469164015a56698a95989555601618402286696055608a82508125aaa5882000aaa96114998660a684582889a5a5190058a0411426145250);
+            read(11);
+            check(1186\'h001224a468a9154205488585aaa9a0a9882056194952001a88424522191052a96a21102915181a845a5509844985196696160900a0515956a2a10a100a12566408a14450049a586951896442400a8620148582958a8a51869990a161412406860012a61a66214a4461a86895640a48284528201852615921952aaaaa40802586168a929582128a985929990826a9110186891489a);
+            read(12);
+            check(1186\'h019618a9624a522a280a06a0654418906998059625a892054996a0560a941a842589189984190884426125114000aa60a0a568285221026662226a626a8600605095054405486561a95059449282969a5a10819101a620902609052a1294182962a020512196945a2aa42598a41842096596551544969262a12a86685214a952494a956166a199682a649249a990088296422051a);
+            read(13);
+            check(1186\'h1a6999a0105054aaa2145298116480601695482119a0619155a4414a8a82840918a512a5680a8000889a4905016868480211289860a8a5699a250245161a042846096a9866025094a189860a9829465281646040866a26959a61a18621848689101a9a95685016a9581224968461a0a108958a91205a0220a18865105928298299a642a906900289a95095845649aa41591069866);
+            read(14);
+            check(1186\'h15a4208a19a0405005900212505098a881a49445242619a12a12491844110169529a422046a684668819599891a411954196961160591865590a699a04908a6196928965a1686a664210420908115a5816919169662656a855099464680902514586265602510840a566a94a506961a615420a908aa91959610a1a0899589600902a10962460a664104126056a82551462459169a);
+            $display(""Good"");
+        $finish;
+\tend
+
+    initial #100 forever #(`P/2) clk = ~clk;
+
+    task write;
+        input [6:0] adr;
+        input [`WIDTH_D0:0] dat;
+        begin
+            sel = 1; 
+            w = 1;
+            addr = adr;
+            data = dat;
+            #(`P);
+        end
+    endtask
+
+    task read;
+        input [6:0] adr;
+        begin
+            sel = 1; 
+            w = 0;
+            addr = adr;
+            #(`P);
+        end
+    endtask
+
+    task check;
+        input [`WIDTH_D0:0] wish;
+        begin
+            if (out !== wish) 
+                begin $display(""Error! %h %h"", out, wish); end
+        end
+    endtask    
+endmodule
+
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* FSM: finite state machine 
+ * halt if $ctrl == 0$
+ */
+module FSM(clk, reset, rom_addr, rom_q, ram_a_addr, ram_b_addr, ram_b_w, pe, done);
+    input clk;
+    input reset;
+    output reg [8:0] rom_addr; /* command id. extra bits? */
+    input [27:0] rom_q; /* command value */
+    output reg [5:0] ram_a_addr;
+    output reg [5:0] ram_b_addr;
+    output ram_b_w;
+    output reg [10:0] pe;
+    output reg done;
+    
+    reg [5:0] state;
+    parameter START=0, READ_SRC1=1, READ_SRC2=2, CALC=4, WAIT=8, WRITE=16, DON=32;
+\t
+    wire [5:0] dest, src1, src2; wire [7:0] times; wire [1:0] op;
+    assign {dest, src1, op, times, src2} = rom_q;
+
+    reg [7:0] count;
+\t
+    always @ (posedge clk)
+       if (reset) 
+          state<=START; 
+       else 
+          case (state)
+             START:
+                state<=READ_SRC1;
+             READ_SRC1:
+                state<=READ_SRC2;
+             READ_SRC2:
+                if (times==0) state<=DON; else state<=CALC;
+             CALC:
+                if (count==1) state<=WAIT;
+             WAIT:
+                state<=WRITE;
+             WRITE:
+                state<=READ_SRC1;
+          endcase
+
+    /* we support two loops */
+    parameter  LOOP1_START = 9\'d21,
+               LOOP1_END   = 9\'d116,
+               LOOP2_START = 9\'d290,
+               LOOP2_END   = 9\'d303;
+    reg [249:0] loop1, loop2;
+\t
+\talways @ (posedge clk)
+\t   if (reset) rom_addr<=0;
+\t   else if (state==WAIT)
+          begin
+             if(rom_addr == LOOP1_END && loop1[0])
+                rom_addr <= LOOP1_START;
+             else if(rom_addr == LOOP2_END && loop2[0])
+                rom_addr <= LOOP2_START;
+             else
+                rom_addr <= rom_addr + 1\'d1; 
+\t      end
+\t
+\talways @ (posedge clk)
+\t   if (reset) loop1 <= ~0;
+\t   else if(state==WAIT && rom_addr==LOOP1_END)
+          loop1 <= loop1 >> 1;
+\t
+\talways @ (posedge clk)
+\t   if (reset) loop2 <= ~0;
+\t   else if(state==WAIT && rom_addr==LOOP2_END)
+          loop2 <= loop2 >> 1;
+
+\talways @ (posedge clk)
+\t   if (reset)
+          count <= 0;
+\t   else if (state==READ_SRC1)
+          count <= times;
+\t   else if (state==CALC)
+          count <= count - 1\'d1;
+\t
+\talways @ (posedge clk)
+\t   if (reset) done<=0;
+\t   else if (state==DON) done<=1;
+\t   else done<=0;
+\t 
+    always @ (state, src1, src2)
+       case (state)
+       READ_SRC1: ram_a_addr=src1;
+       READ_SRC2: ram_a_addr=src2;
+       default: ram_a_addr=0;
+       endcase
+    
+    parameter CMD_ADD=6\'d4, CMD_SUB=6\'d8, CMD_CUBIC=6\'d16,
+              ADD=2\'d0, SUB=2\'d1, CUBIC=2\'d2, MULT=2\'d3;
+
+    always @ (posedge clk)
+       case (state)
+       READ_SRC1:
+          case (op)
+          ADD:   pe<=11\'b11001000000;
+          SUB:   pe<=11\'b11001000000;
+          CUBIC: pe<=11\'b11111000000;
+          MULT:  pe<=11\'b11110000000;
+          default: pe<=0;
+          endcase
+       READ_SRC2:
+          case (op)
+          ADD:   pe<=11\'b00110000000;
+          SUB:   pe<=11\'b00110000000;
+          CUBIC: pe<=0;
+          MULT:  pe<=11\'b00001000000;
+          default: pe<=0;
+          endcase
+       CALC:
+          case (op)
+          ADD:   pe<=11\'b00000010001;
+          SUB:   pe<=11\'b00000010001;
+          CUBIC: pe<=11\'b01010000001;
+          MULT:  pe<=11\'b00000111111;
+          default: pe<=0;
+          endcase
+       default: 
+          pe<=0;
+       endcase
+
+    always @ (state, op, src2, dest)
+       case (state)
+       READ_SRC1: 
+          case (op)
+          ADD: ram_b_addr=CMD_ADD;
+          SUB: ram_b_addr=CMD_SUB;
+          CUBIC: ram_b_addr=CMD_CUBIC;
+          default: ram_b_addr=0;
+          endcase
+       READ_SRC2: ram_b_addr=src2;
+       WRITE: ram_b_addr=dest;
+       default: ram_b_addr=0;
+       endcase
+
+    assign ram_b_w = (state==WRITE) ? 1\'b1 : 1\'b0;
+endmodule
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* v0(a)+v1(a)+v2(a)+v3(a) == a^3 in GF(3^m) */
+
+/* c == v0(a) */
+module v0(a, c);
+    input [1005:0] a;
+    output [1005:0] c;
+    assign c[1:0] = a[1:0];
+    assign c[3:2] = a[337:336];
+    assign c[5:4] = a[673:672];
+    assign c[7:6] = a[3:2];
+    assign c[9:8] = a[339:338];
+    assign c[11:10] = a[675:674];
+    assign c[13:12] = a[5:4];
+    assign c[15:14] = a[341:340];
+    assign c[17:16] = a[677:676];
+    assign c[19:18] = a[7:6];
+    assign c[21:20] = {a[608], a[609]};
+    assign c[23:22] = a[945:944];
+    assign c[25:24] = a[9:8];
+    assign c[27:26] = {a[610], a[611]};
+    assign c[29:28] = a[947:946];
+    assign c[31:30] = a[11:10];
+    assign c[33:32] = {a[612], a[613]};
+    assign c[35:34] = a[949:948];
+    assign c[37:36] = a[13:12];
+    assign c[39:38] = a[881:880];
+    assign c[41:40] = a[951:950];
+    assign c[43:42] = a[15:14];
+    assign c[45:44] = a[883:882];
+    assign c[47:46] = a[953:952];
+    assign c[49:48] = a[17:16];
+    assign c[51:50] = a[353:352];
+    assign c[53:52] = a[689:688];
+    assign c[55:54] = a[19:18];
+    assign c[57:56] = a[355:354];
+    assign c[59:58] = a[691:690];
+    assign c[61:60] = a[21:20];
+    assign c[63:62] = a[357:356];
+    assign c[65:64] = a[693:692];
+    assign c[67:66] = a[23:22];
+    assign c[69:68] = {a[624], a[625]};
+    assign c[71:70] = a[961:960];
+    assign c[73:72] = a[25:24];
+    assign c[75:74] = {a[626], a[627]};
+    assign c[77:76] = a[963:962];
+    assign c[79:78] = a[27:26];
+    assign c[81:80] = {a[628], a[629]};
+    assign c[83:82] = a[965:964];
+    assign c[85:84] = a[29:28];
+    assign c[87:86] = a[897:896];
+    assign c[89:88] = a[967:966];
+    assign c[91:90] = a[31:30];
+    assign c[93:92] = a[899:898];
+    assign c[95:94] = a[969:968];
+    assign c[97:96] = a[33:32];
+    assign c[99:98] = a[369:368];
+    assign c[101:100] = a[705:704];
+    assign c[103:102] = a[35:34];
+    assign c[105:104] = a[371:370];
+    assign c[107:106] = a[707:706];
+    assign c[109:108] = a[37:36];
+    assign c[111:110] = a[373:372];
+    assign c[113:112] = a[709:708];
+    assign c[115:114] = a[39:38];
+    assign c[117:116] = {a[640], a[641]};
+    assign c[119:118] = a[977:976];
+    assign c[121:120] = a[41:40];
+    assign c[123:122] = {a[642], a[643]};
+    assign c[125:124] = a[979:978];
+    assign c[127:126] = a[43:42];
+    assign c[129:128] = {a[644], a[645]};
+    assign c[131:130] = a[981:980];
+    assign c[133:132] = a[45:44];
+    assign c[135:134] = a[913:912];
+    assign c[137:136] = a[983:982];
+    assign c[139:138] = a[47:46];
+    assign c[141:140] = a[915:914];
+    assign c[143:142] = a[985:984];
+    assign c[145:144] = a[49:48];
+    assign c[147:146] = a[385:384];
+    assign c[149:148] = a[721:720];
+    assign c[151:150] = a[51:50];
+    assign c[153:152] = a[387:386];
+    assign c[155:154] = a[723:722];
+    assign c[157:156] = a[53:52];
+    assign c[159:158] = a[389:388];
+    assign c[161:160] = a[725:724];
+    assign c[163:162] = a[55:54];
+    assign c[165:164] = {a[656], a[657]};
+    assign c[167:166] = a[993:992];
+    assign c[169:168] = a[57:56];
+    assign c[171:170] = {a[658], a[659]};
+    assign c[173:172] = a[995:994];
+    assign c[175:174] = a[59:58];
+    assign c[177:176] = {a[660], a[661]};
+    assign c[179:178] = a[997:996];
+    assign c[181:180] = a[61:60];
+    assign c[183:182] = a[929:928];
+    assign c[185:184] = a[999:998];
+    assign c[187:186] = a[63:62];
+    assign c[189:188] = a[931:930];
+    assign c[191:190] = a[1001:1000];
+    assign c[193:192] = a[65:64];
+    assign c[195:194] = a[401:400];
+    assign c[197:196] = a[737:736];
+    assign c[199:198] = a[67:66];
+    assign c[201:200] = a[403:402];
+    assign c[203:202] = a[739:738];
+    assign c[205:204] = a[69:68];
+    assign c[207:206] = a[405:404];
+    assign c[209:208] = a[741:740];
+    assign c[211:210] = {a[336], a[337]};
+    assign c[213:212] = a[673:672];
+    assign c[215:214] = a[743:742];
+    assign c[217:216] = {a[338], a[339]};
+    assign c[219:218] = a[675:674];
+    assign c[221:220] = a[745:744];
+    assign c[223:222] = {a[340], a[341]};
+    assign c[225:224] = a[677:676];
+    assign c[227:226] = a[747:746];
+    assign c[229:228] = a[609:608];
+    assign c[231:230] = a[679:678];
+    assign c[233:232] = a[749:748];
+    assign c[235:234] = a[611:610];
+    assign c[237:236] = a[681:680];
+    assign c[239:238] = a[751:750];
+    assign c[241:240] = a[81:80];
+    assign c[243:242] = a[417:416];
+    assign c[245:244] = a[753:752];
+    assign c[247:246] = {a[880], a[881]};
+    assign c[249:248] = a[419:418];
+    assign c[251:250] = a[755:754];
+    assign c[253:252] = {a[882], a[883]};
+    assign c[255:254] = a[421:420];
+    assign c[257:256] = a[757:756];
+    assign c[259:258] = {a[352], a[353]};
+    assign c[261:260] = a[689:688];
+    assign c[263:262] = a[759:758];
+    assign c[265:264] = {a[354], a[355]};
+    assign c[267:266] = a[691:690];
+    assign c[269:268] = a[761:760];
+    assign c[271:270] = {a[356], a[357]};
+    assign c[273:272] = a[693:692];
+    assign c[275:274] = a[763:762];
+    assign c[277:276] = a[625:624];
+    assign c[279:278] = a[695:694];
+    assign c[281:280] = a[765:764];
+    assign c[283:282] = a[627:626];
+    assign c[285:284] = a[697:696];
+    assign c[287:286] = a[767:766];
+    assign c[289:288] = a[97:96];
+    assign c[291:290] = a[433:432];
+    assign c[293:292] = a[769:768];
+    assign c[295:294] = {a[896], a[897]};
+    assign c[297:296] = a[435:434];
+    assign c[299:298] = a[771:770];
+    assign c[301:300] = {a[898], a[899]};
+    assign c[303:302] = a[437:436];
+    assign c[305:304] = a[773:772];
+    assign c[307:306] = {a[368], a[369]};
+    assign c[309:308] = a[705:704];
+    assign c[311:310] = a[775:774];
+    assign c[313:312] = {a[370], a[371]};
+    assign c[315:314] = a[707:706];
+    assign c[317:316] = a[777:776];
+    assign c[319:318] = {a[372], a[373]};
+    assign c[321:320] = a[709:708];
+    assign c[323:322] = a[779:778];
+    assign c[325:324] = a[641:640];
+    assign c[327:326] = a[711:710];
+    assign c[329:328] = a[781:780];
+    assign c[331:330] = a[643:642];
+    assign c[333:332] = a[713:712];
+    assign c[335:334] = a[783:782];
+    assign c[337:336] = a[113:112];
+    assign c[339:338] = a[449:448];
+    assign c[341:340] = a[785:784];
+    assign c[343:342] = {a[912], a[913]};
+    assign c[345:344] = a[451:450];
+    assign c[347:346] = a[787:786];
+    assign c[349:348] = {a[914], a[915]};
+    assign c[351:350] = a[453:452];
+    assign c[353:352] = a[789:788];
+    assign c[355:354] = {a[384], a[385]};
+    assign c[357:356] = a[721:720];
+    assign c[359:358] = a[791:790];
+    assign c[361:360] = {a[386], a[387]};
+    assign c[363:362] = a[723:722];
+    assign c[365:364] = a[793:792];
+    assign c[367:366] = {a[388], a[389]};
+    assign c[369:368] = a[725:724];
+    assign c[371:370] = a[795:794];
+    assign c[373:372] = a[657:656];
+    assign c[375:374] = a[727:726];
+    assign c[377:376] = a[797:796];
+    assign c[379:378] = a[659:658];
+    assign c[381:380] = a[729:728];
+    assign c[383:382] = a[799:798];
+    assign c[385:384] = a[129:128];
+    assign c[387:386] = a[465:464];
+    assign c[389:388] = a[801:800];
+    assign c[391:390] = {a[928], a[929]};
+    assign c[393:392] = a[467:466];
+    assign c[395:394] = a[803:802];
+    assign c[397:396] = {a[930], a[931]};
+    assign c[399:398] = a[469:468];
+    assign c[401:400] = a[805:804];
+    assign c[403:402] = {a[400], a[401]};
+    assign c[405:404] = a[737:736];
+    assign c[407:406] = a[807:806];
+    assign c[409:408] = {a[402], a[403]};
+    assign c[411:410] = a[739:738];
+    assign c[413:412] = a[809:808];
+    assign c[415:414] = {a[404], a[405]};
+    assign c[417:416] = a[741:740];
+    assign c[419:418] = a[811:810];
+    assign c[421:420] = a[673:672];
+    assign c[423:422] = a[743:742];
+    assign c[425:424] = a[813:812];
+    assign c[427:426] = a[675:674];
+    assign c[429:428] = a[745:744];
+    assign c[431:430] = a[815:814];
+    assign c[433:432] = a[145:144];
+    assign c[435:434] = a[481:480];
+    assign c[437:436] = a[817:816];
+    assign c[439:438] = {a[944], a[945]};
+    assign c[441:440] = a[483:482];
+    assign c[443:442] = a[819:818];
+    assign c[445:444] = {a[946], a[947]};
+    assign c[447:446] = a[485:484];
+    assign c[449:448] = a[821:820];
+    assign c[451:450] = {a[416], a[417]};
+    assign c[453:452] = a[753:752];
+    assign c[455:454] = a[823:822];
+    assign c[457:456] = {a[418], a[419]};
+    assign c[459:458] = a[755:754];
+    assign c[461:460] = a[825:824];
+    assign c[463:462] = {a[420], a[421]};
+    assign c[465:464] = a[757:756];
+    assign c[467:466] = a[827:826];
+    assign c[469:468] = a[689:688];
+    assign c[471:470] = a[759:758];
+    assign c[473:472] = a[829:828];
+    assign c[475:474] = a[691:690];
+    assign c[477:476] = a[761:760];
+    assign c[479:478] = a[831:830];
+    assign c[481:480] = a[161:160];
+    assign c[483:482] = a[497:496];
+    assign c[485:484] = a[833:832];
+    assign c[487:486] = {a[960], a[961]};
+    assign c[489:488] = a[499:498];
+    assign c[491:490] = a[835:834];
+    assign c[493:492] = {a[962], a[963]};
+    assign c[495:494] = a[501:500];
+    assign c[497:496] = a[837:836];
+    assign c[499:498] = {a[432], a[433]};
+    assign c[501:500] = a[769:768];
+    assign c[503:502] = a[839:838];
+    assign c[505:504] = {a[434], a[435]};
+    assign c[507:506] = a[771:770];
+    assign c[509:508] = a[841:840];
+    assign c[511:510] = {a[436], a[437]};
+    assign c[513:512] = a[773:772];
+    assign c[515:514] = a[843:842];
+    assign c[517:516] = a[705:704];
+    assign c[519:518] = a[775:774];
+    assign c[521:520] = a[845:844];
+    assign c[523:522] = a[707:706];
+    assign c[525:524] = a[777:776];
+    assign c[527:526] = a[847:846];
+    assign c[529:528] = a[177:176];
+    assign c[531:530] = a[513:512];
+    assign c[533:532] = a[849:848];
+    assign c[535:534] = {a[976], a[977]};
+    assign c[537:536] = a[515:514];
+    assign c[539:538] = a[851:850];
+    assign c[541:540] = {a[978], a[979]};
+    assign c[543:542] = a[517:516];
+    assign c[545:544] = a[853:852];
+    assign c[547:546] = {a[448], a[449]};
+    assign c[549:548] = a[785:784];
+    assign c[551:550] = a[855:854];
+    assign c[553:552] = {a[450], a[451]};
+    assign c[555:554] = a[787:786];
+    assign c[557:556] = a[857:856];
+    assign c[559:558] = {a[452], a[453]};
+    assign c[561:560] = a[789:788];
+    assign c[563:562] = a[859:858];
+    assign c[565:564] = a[721:720];
+    assign c[567:566] = a[791:790];
+    assign c[569:568] = a[861:860];
+    assign c[571:570] = a[723:722];
+    assign c[573:572] = a[793:792];
+    assign c[575:574] = a[863:862];
+    assign c[577:576] = a[193:192];
+    assign c[579:578] = a[529:528];
+    assign c[581:580] = a[865:864];
+    assign c[583:582] = {a[992], a[993]};
+    assign c[585:584] = a[531:530];
+    assign c[587:586] = a[867:866];
+    assign c[589:588] = {a[994], a[995]};
+    assign c[591:590] = a[533:532];
+    assign c[593:592] = a[869:868];
+    assign c[595:594] = {a[464], a[465]};
+    assign c[597:596] = a[801:800];
+    assign c[599:598] = a[871:870];
+    assign c[601:600] = {a[466], a[467]};
+    assign c[603:602] = a[803:802];
+    assign c[605:604] = a[873:872];
+    assign c[607:606] = {a[468], a[469]};
+    assign c[609:608] = a[805:804];
+    assign c[611:610] = a[875:874];
+    assign c[613:612] = a[737:736];
+    assign c[615:614] = a[807:806];
+    assign c[617:616] = a[877:876];
+    assign c[619:618] = a[739:738];
+    assign c[621:620] = a[809:808];
+    assign c[623:622] = a[879:878];
+    assign c[625:624] = a[209:208];
+    assign c[627:626] = a[545:544];
+    assign c[629:628] = a[881:880];
+    assign c[631:630] = a[211:210];
+    assign c[633:632] = a[547:546];
+    assign c[635:634] = a[883:882];
+    assign c[637:636] = a[213:212];
+    assign c[639:638] = a[549:548];
+    assign c[641:640] = a[885:884];
+    assign c[643:642] = {a[480], a[481]};
+    assign c[645:644] = a[817:816];
+    assign c[647:646] = a[887:886];
+    assign c[649:648] = {a[482], a[483]};
+    assign c[651:650] = a[819:818];
+    assign c[653:652] = a[889:888];
+    assign c[655:654] = {a[484], a[485]};
+    assign c[657:656] = a[821:820];
+    assign c[659:658] = a[891:890];
+    assign c[661:660] = a[753:752];
+    assign c[663:662] = a[823:822];
+    assign c[665:664] = a[893:892];
+    assign c[667:666] = a[755:754];
+    assign c[669:668] = a[825:824];
+    assign c[671:670] = a[895:894];
+    assign c[673:672] = a[225:224];
+    assign c[675:674] = a[561:560];
+    assign c[677:676] = a[897:896];
+    assign c[679:678] = a[227:226];
+    assign c[681:680] = a[563:562];
+    assign c[683:682] = a[899:898];
+    assign c[685:684] = a[229:228];
+    assign c[687:686] = a[565:564];
+    assign c[689:688] = a[901:900];
+    assign c[691:690] = {a[496], a[497]};
+    assign c[693:692] = a[833:832];
+    assign c[695:694] = a[903:902];
+    assign c[697:696] = {a[498], a[499]};
+    assign c[699:698] = a[835:834];
+    assign c[701:700] = a[905:904];
+    assign c[703:702] = {a[500], a[501]};
+    assign c[705:704] = a[837:836];
+    assign c[707:706] = a[907:906];
+    assign c[709:708] = a[769:768];
+    assign c[711:710] = a[839:838];
+    assign c[713:712] = a[909:908];
+    assign c[715:714] = a[771:770];
+    assign c[717:716] = a[841:840];
+    assign c[719:718] = a[911:910];
+    assign c[721:720] = a[241:240];
+    assign c[723:722] = a[577:576];
+    assign c[725:724] = a[913:912];
+    assign c[727:726] = a[243:242];
+    assign c[729:728] = a[579:578];
+    assign c[731:730] = a[915:914];
+    assign c[733:732] = a[245:244];
+    assign c[735:734] = a[581:580];
+    assign c[737:736] = a[917:916];
+    assign c[739:738] = {a[512], a[513]};
+    assign c[741:740] = a[849:848];
+    assign c[743:742] = a[919:918];
+    assign c[745:744] = {a[514], a[515]};
+    assign c[747:746] = a[851:850];
+    assign c[749:748] = a[921:920];
+    assign c[751:750] = {a[516], a[517]};
+    assign c[753:752] = a[853:852];
+    assign c[755:754] = a[923:922];
+    assign c[757:756] = a[785:784];
+    assign c[759:758] = a[855:854];
+    assign c[761:760] = a[925:924];
+    assign c[763:762] = a[787:786];
+    assign c[765:764] = a[857:856];
+    assign c[767:766] = a[927:926];
+    assign c[769:768] = a[257:256];
+    assign c[771:770] = a[593:592];
+    assign c[773:772] = a[929:928];
+    assign c[775:774] = a[259:258];
+    assign c[777:776] = a[595:594];
+    assign c[779:778] = a[931:930];
+    assign c[781:780] = a[261:260];
+    assign c[783:782] = a[597:596];
+    assign c[785:784] = a[933:932];
+    assign c[787:786] = {a[528], a[529]};
+    assign c[789:788] = a[865:864];
+    assign c[791:790] = a[935:934];
+    assign c[793:792] = {a[530], a[531]};
+    assign c[795:794] = a[867:866];
+    assign c[797:796] = a[937:936];
+    assign c[799:798] = {a[532], a[533]};
+    assign c[801:800] = a[869:868];
+    assign c[803:802] = a[939:938];
+    assign c[805:804] = a[801:800];
+    assign c[807:806] = a[871:870];
+    assign c[809:808] = a[941:940];
+    assign c[811:810] = a[803:802];
+    assign c[813:812] = a[873:872];
+    assign c[815:814] = a[943:942];
+    assign c[817:816] = a[273:272];
+    assign c[819:818] = a[609:608];
+    assign c[821:820] = a[945:944];
+    assign c[823:822] = a[275:274];
+    assign c[825:824] = a[611:610];
+    assign c[827:826] = a[947:946];
+    assign c[829:828] = a[277:276];
+    assign c[831:830] = a[613:612];
+    assign c[833:832] = a[949:948];
+    assign c[835:834] = {a[544], a[545]};
+    assign c[837:836] = a[881:880];
+    assign c[839:838] = a[951:950];
+    assign c[841:840] = {a[546], a[547]};
+    assign c[843:842] = a[883:882];
+    assign c[845:844] = a[953:952];
+    assign c[847:846] = {a[548], a[549]};
+    assign c[849:848] = a[885:884];
+    assign c[851:850] = a[955:954];
+    assign c[853:852] = a[817:816];
+    assign c[855:854] = a[887:886];
+    assign c[857:856] = a[957:956];
+    assign c[859:858] = a[819:818];
+    assign c[861:860] = a[889:888];
+    assign c[863:862] = a[959:958];
+    assign c[865:864] = a[289:288];
+    assign c[867:866] = a[625:624];
+    assign c[869:868] = a[961:960];
+    assign c[871:870] = a[291:290];
+    assign c[873:872] = a[627:626];
+    assign c[875:874] = a[963:962];
+    assign c[877:876] = a[293:292];
+    assign c[879:878] = a[629:628];
+    assign c[881:880] = a[965:964];
+    assign c[883:882] = {a[560], a[561]};
+    assign c[885:884] = a[897:896];
+    assign c[887:886] = a[967:966];
+    assign c[889:888] = {a[562], a[563]};
+    assign c[891:890] = a[899:898];
+    assign c[893:892] = a[969:968];
+    assign c[895:894] = {a[564], a[565]};
+    assign c[897:896] = a[901:900];
+    assign c[899:898] = a[971:970];
+    assign c[901:900] = a[833:832];
+    assign c[903:902] = a[903:902];
+    assign c[905:904] = a[973:972];
+    assign c[907:906] = a[835:834];
+    assign c[909:908] = a[905:904];
+    assign c[911:910] = a[975:974];
+    assign c[913:912] = a[305:304];
+    assign c[915:914] = a[641:640];
+    assign c[917:916] = a[977:976];
+    assign c[919:918] = a[307:306];
+    assign c[921:920] = a[643:642];
+    assign c[923:922] = a[979:978];
+    assign c[925:924] = a[309:308];
+    assign c[927:926] = a[645:644];
+    assign c[929:928] = a[981:980];
+    assign c[931:930] = {a[576], a[577]};
+    assign c[933:932] = a[913:912];
+    assign c[935:934] = a[983:982];
+    assign c[937:936] = {a[578], a[579]};
+    assign c[939:938] = a[915:914];
+    assign c[941:940] = a[985:984];
+    assign c[943:942] = {a[580], a[581]};
+    assign c[945:944] = a[917:916];
+    assign c[947:946] = a[987:986];
+    assign c[949:948] = a[849:848];
+    assign c[951:950] = a[919:918];
+    assign c[953:952] = a[989:988];
+    assign c[955:954] = a[851:850];
+    assign c[957:956] = a[921:920];
+    assign c[959:958] = a[991:990];
+    assign c[961:960] = a[321:320];
+    assign c[963:962] = a[657:656];
+    assign c[965:964] = a[993:992];
+    assign c[967:966] = a[323:322];
+    assign c[969:968] = a[659:658];
+    assign c[971:970] = a[995:994];
+    assign c[973:972] = a[325:324];
+    assign c[975:974] = a[661:660];
+    assign c[977:976] = a[997:996];
+    assign c[979:978] = {a[592], a[593]};
+    assign c[981:980] = a[929:928];
+    assign c[983:982] = a[999:998];
+    assign c[985:984] = {a[594], a[595]};
+    assign c[987:986] = a[931:930];
+    assign c[989:988] = a[1001:1000];
+    assign c[991:990] = {a[596], a[597]};
+    assign c[993:992] = a[933:932];
+    assign c[995:994] = a[1003:1002];
+    assign c[997:996] = a[865:864];
+    assign c[999:998] = a[935:934];
+    assign c[1001:1000] = a[1005:1004];
+    assign c[1003:1002] = a[867:866];
+    assign c[1005:1004] = a[937:936];
+endmodule
+/* c == v1(a) */
+module v1(a, c);
+    input [1005:0] a;
+    output [1005:0] c;
+    assign c[1:0] = 0;
+    assign c[3:2] = a[869:868];
+    assign c[5:4] = a[939:938];
+    assign c[7:6] = 0;
+    assign c[9:8] = a[871:870];
+    assign c[11:10] = a[941:940];
+    assign c[13:12] = 0;
+    assign c[15:14] = a[873:872];
+    assign c[17:16] = a[943:942];
+    assign c[19:18] = 0;
+    assign c[21:20] = a[343:342];
+    assign c[23:22] = a[679:678];
+    assign c[25:24] = 0;
+    assign c[27:26] = a[345:344];
+    assign c[29:28] = a[681:680];
+    assign c[31:30] = 0;
+    assign c[33:32] = a[347:346];
+    assign c[35:34] = a[683:682];
+    assign c[37:36] = 0;
+    assign c[39:38] = {a[614], a[615]};
+    assign c[41:40] = a[685:684];
+    assign c[43:42] = 0;
+    assign c[45:44] = {a[616], a[617]};
+    assign c[47:46] = a[687:686];
+    assign c[49:48] = 0;
+    assign c[51:50] = a[885:884];
+    assign c[53:52] = a[955:954];
+    assign c[55:54] = 0;
+    assign c[57:56] = a[887:886];
+    assign c[59:58] = a[957:956];
+    assign c[61:60] = 0;
+    assign c[63:62] = a[889:888];
+    assign c[65:64] = a[959:958];
+    assign c[67:66] = 0;
+    assign c[69:68] = a[359:358];
+    assign c[71:70] = a[695:694];
+    assign c[73:72] = 0;
+    assign c[75:74] = a[361:360];
+    assign c[77:76] = a[697:696];
+    assign c[79:78] = 0;
+    assign c[81:80] = a[363:362];
+    assign c[83:82] = a[699:698];
+    assign c[85:84] = 0;
+    assign c[87:86] = {a[630], a[631]};
+    assign c[89:88] = a[701:700];
+    assign c[91:90] = 0;
+    assign c[93:92] = {a[632], a[633]};
+    assign c[95:94] = a[703:702];
+    assign c[97:96] = 0;
+    assign c[99:98] = a[901:900];
+    assign c[101:100] = a[971:970];
+    assign c[103:102] = 0;
+    assign c[105:104] = a[903:902];
+    assign c[107:106] = a[973:972];
+    assign c[109:108] = 0;
+    assign c[111:110] = a[905:904];
+    assign c[113:112] = a[975:974];
+    assign c[115:114] = 0;
+    assign c[117:116] = a[375:374];
+    assign c[119:118] = a[711:710];
+    assign c[121:120] = 0;
+    assign c[123:122] = a[377:376];
+    assign c[125:124] = a[713:712];
+    assign c[127:126] = 0;
+    assign c[129:128] = a[379:378];
+    assign c[131:130] = a[715:714];
+    assign c[133:132] = 0;
+    assign c[135:134] = {a[646], a[647]};
+    assign c[137:136] = a[717:716];
+    assign c[139:138] = 0;
+    assign c[141:140] = {a[648], a[649]};
+    assign c[143:142] = a[719:718];
+    assign c[145:144] = 0;
+    assign c[147:146] = a[917:916];
+    assign c[149:148] = a[987:986];
+    assign c[151:150] = 0;
+    assign c[153:152] = a[919:918];
+    assign c[155:154] = a[989:988];
+    assign c[157:156] = 0;
+    assign c[159:158] = a[921:920];
+    assign c[161:160] = a[991:990];
+    assign c[163:162] = 0;
+    assign c[165:164] = a[391:390];
+    assign c[167:166] = a[727:726];
+    assign c[169:168] = 0;
+    assign c[171:170] = a[393:392];
+    assign c[173:172] = a[729:728];
+    assign c[175:174] = 0;
+    assign c[177:176] = a[395:394];
+    assign c[179:178] = a[731:730];
+    assign c[181:180] = 0;
+    assign c[183:182] = {a[662], a[663]};
+    assign c[185:184] = a[733:732];
+    assign c[187:186] = 0;
+    assign c[189:188] = {a[664], a[665]};
+    assign c[191:190] = a[735:734];
+    assign c[193:192] = 0;
+    assign c[195:194] = a[933:932];
+    assign c[197:196] = a[1003:1002];
+    assign c[199:198] = 0;
+    assign c[201:200] = a[935:934];
+    assign c[203:202] = a[1005:1004];
+    assign c[205:204] = 0;
+    assign c[207:206] = a[937:936];
+    assign c[209:208] = 0;
+    assign c[211:210] = {a[868], a[869]};
+    assign c[213:212] = a[407:406];
+    assign c[215:214] = 0;
+    assign c[217:216] = {a[870], a[871]};
+    assign c[219:218] = a[409:408];
+    assign c[221:220] = 0;
+    assign c[223:222] = {a[872], a[873]};
+    assign c[225:224] = a[411:410];
+    assign c[227:226] = 0;
+    assign c[229:228] = {a[342], a[343]};
+    assign c[231:230] = a[413:412];
+    assign c[233:232] = 0;
+    assign c[235:234] = {a[344], a[345]};
+    assign c[237:236] = a[415:414];
+    assign c[239:238] = 0;
+    assign c[241:240] = a[613:612];
+    assign c[243:242] = a[683:682];
+    assign c[245:244] = 0;
+    assign c[247:246] = a[83:82];
+    assign c[249:248] = a[685:684];
+    assign c[251:250] = 0;
+    assign c[253:252] = a[85:84];
+    assign c[255:254] = a[687:686];
+    assign c[257:256] = 0;
+    assign c[259:258] = {a[884], a[885]};
+    assign c[261:260] = a[423:422];
+    assign c[263:262] = 0;
+    assign c[265:264] = {a[886], a[887]};
+    assign c[267:266] = a[425:424];
+    assign c[269:268] = 0;
+    assign c[271:270] = {a[888], a[889]};
+    assign c[273:272] = a[427:426];
+    assign c[275:274] = 0;
+    assign c[277:276] = {a[358], a[359]};
+    assign c[279:278] = a[429:428];
+    assign c[281:280] = 0;
+    assign c[283:282] = {a[360], a[361]};
+    assign c[285:284] = a[431:430];
+    assign c[287:286] = 0;
+    assign c[289:288] = a[629:628];
+    assign c[291:290] = a[699:698];
+    assign c[293:292] = 0;
+    assign c[295:294] = a[99:98];
+    assign c[297:296] = a[701:700];
+    assign c[299:298] = 0;
+    assign c[301:300] = a[101:100];
+    assign c[303:302] = a[703:702];
+    assign c[305:304] = 0;
+    assign c[307:306] = {a[900], a[901]};
+    assign c[309:308] = a[439:438];
+    assign c[311:310] = 0;
+    assign c[313:312] = {a[902], a[903]};
+    assign c[315:314] = a[441:440];
+    assign c[317:316] = 0;
+    assign c[319:318] = {a[904], a[905]};
+    assign c[321:320] = a[443:442];
+    assign c[323:322] = 0;
+    assign c[325:324] = {a[374], a[375]};
+    assign c[327:326] = a[445:444];
+    assign c[329:328] = 0;
+    assign c[331:330] = {a[376], a[377]};
+    assign c[333:332] = a[447:446];
+    assign c[335:334] = 0;
+    assign c[337:336] = a[645:644];
+    assign c[339:338] = a[715:714];
+    assign c[341:340] = 0;
+    assign c[343:342] = a[115:114];
+    assign c[345:344] = a[717:716];
+    assign c[347:346] = 0;
+    assign c[349:348] = a[117:116];
+    assign c[351:350] = a[719:718];
+    assign c[353:352] = 0;
+    assign c[355:354] = {a[916], a[917]};
+    assign c[357:356] = a[455:454];
+    assign c[359:358] = 0;
+    assign c[361:360] = {a[918], a[919]};
+    assign c[363:362] = a[457:456];
+    assign c[365:364] = 0;
+    assign c[367:366] = {a[920], a[921]};
+    assign c[369:368] = a[459:458];
+    assign c[371:370] = 0;
+    assign c[373:372] = {a[390], a[391]};
+    assign c[375:374] = a[461:460];
+    assign c[377:376] = 0;
+    assign c[379:378] = {a[392], a[393]};
+    assign c[381:380] = a[463:462];
+    assign c[383:382] = 0;
+    assign c[385:384] = a[661:660];
+    assign c[387:386] = a[731:730];
+    assign c[389:388] = 0;
+    assign c[391:390] = a[131:130];
+    assign c[393:392] = a[733:732];
+    assign c[395:394] = 0;
+    assign c[397:396] = a[133:132];
+    assign c[399:398] = a[735:734];
+    assign c[401:400] = 0;
+    assign c[403:402] = {a[932], a[933]};
+    assign c[405:404] = a[471:470];
+    assign c[407:406] = 0;
+    assign c[409:408] = {a[934], a[935]};
+    assign c[411:410] = a[473:472];
+    assign c[413:412] = 0;
+    assign c[415:414] = {a[936], a[937]};
+    assign c[417:416] = a[475:474];
+    assign c[419:418] = 0;
+    assign c[421:420] = {a[406], a[407]};
+    assign c[423:422] = a[477:476];
+    assign c[425:424] = 0;
+    assign c[427:426] = {a[408], a[409]};
+    assign c[429:428] = a[479:478];
+    assign c[431:430] = 0;
+    assign c[433:432] = a[677:676];
+    assign c[435:434] = a[747:746];
+    assign c[437:436] = 0;
+    assign c[439:438] = a[147:146];
+    assign c[441:440] = a[749:748];
+    assign c[443:442] = 0;
+    assign c[445:444] = a[149:148];
+    assign c[447:446] = a[751:750];
+    assign c[449:448] = 0;
+    assign c[451:450] = {a[948], a[949]};
+    assign c[453:452] = a[487:486];
+    assign c[455:454] = 0;
+    assign c[457:456] = {a[950], a[951]};
+    assign c[459:458] = a[489:488];
+    assign c[461:460] = 0;
+    assign c[463:462] = {a[952], a[953]};
+    assign c[465:464] = a[491:490];
+    assign c[467:466] = 0;
+    assign c[469:468] = {a[422], a[423]};
+    assign c[471:470] = a[493:492];
+    assign c[473:472] = 0;
+    assign c[475:474] = {a[424], a[425]};
+    assign c[477:476] = a[495:494];
+    assign c[479:478] = 0;
+    assign c[481:480] = a[693:692];
+    assign c[483:482] = a[763:762];
+    assign c[485:484] = 0;
+    assign c[487:486] = a[163:162];
+    assign c[489:488] = a[765:764];
+    assign c[491:490] = 0;
+    assign c[493:492] = a[165:164];
+    assign c[495:494] = a[767:766];
+    assign c[497:496] = 0;
+    assign c[499:498] = {a[964], a[965]};
+    assign c[501:500] = a[503:502];
+    assign c[503:502] = 0;
+    assign c[505:504] = {a[966], a[967]};
+    assign c[507:506] = a[505:504];
+    assign c[509:508] = 0;
+    assign c[511:510] = {a[968], a[969]};
+    assign c[513:512] = a[507:506];
+    assign c[515:514] = 0;
+    assign c[517:516] = {a[438], a[439]};
+    assign c[519:518] = a[509:508];
+    assign c[521:520] = 0;
+    assign c[523:522] = {a[440], a[441]};
+    assign c[525:524] = a[511:510];
+    assign c[527:526] = 0;
+    assign c[529:528] = a[709:708];
+    assign c[531:530] = a[779:778];
+    assign c[533:532] = 0;
+    assign c[535:534] = a[179:178];
+    assign c[537:536] = a[781:780];
+    assign c[539:538] = 0;
+    assign c[541:540] = a[181:180];
+    assign c[543:542] = a[783:782];
+    assign c[545:544] = 0;
+    assign c[547:546] = {a[980], a[981]};
+    assign c[549:548] = a[519:518];
+    assign c[551:550] = 0;
+    assign c[553:552] = {a[982], a[983]};
+    assign c[555:554] = a[521:520];
+    assign c[557:556] = 0;
+    assign c[559:558] = {a[984], a[985]};
+    assign c[561:560] = a[523:522];
+    assign c[563:562] = 0;
+    assign c[565:564] = {a[454], a[455]};
+    assign c[567:566] = a[525:524];
+    assign c[569:568] = 0;
+    assign c[571:570] = {a[456], a[457]};
+    assign c[573:572] = a[527:526];
+    assign c[575:574] = 0;
+    assign c[577:576] = a[725:724];
+    assign c[579:578] = a[795:794];
+    assign c[581:580] = 0;
+    assign c[583:582] = a[195:194];
+    assign c[585:584] = a[797:796];
+    assign c[587:586] = 0;
+    assign c[589:588] = a[197:196];
+    assign c[591:590] = a[799:798];
+    assign c[593:592] = 0;
+    assign c[595:594] = {a[996], a[997]};
+    assign c[597:596] = a[535:534];
+    assign c[599:598] = 0;
+    assign c[601:600] = {a[998], a[999]};
+    assign c[603:602] = a[537:536];
+    assign c[605:604] = 0;
+    assign c[607:606] = {a[1000], a[1001]};
+    assign c[609:608] = a[539:538];
+    assign c[611:610] = 0;
+    assign c[613:612] = {a[470], a[471]};
+    assign c[615:614] = a[541:540];
+    assign c[617:616] = 0;
+    assign c[619:618] = {a[472], a[473]};
+    assign c[621:620] = a[543:542];
+    assign c[623:622] = 0;
+    assign c[625:624] = a[741:740];
+    assign c[627:626] = a[811:810];
+    assign c[629:628] = 0;
+    assign c[631:630] = a[743:742];
+    assign c[633:632] = a[813:812];
+    assign c[635:634] = 0;
+    assign c[637:636] = a[745:744];
+    assign c[639:638] = a[815:814];
+    assign c[641:640] = 0;
+    assign c[643:642] = a[215:214];
+    assign c[645:644] = a[551:550];
+    assign c[647:646] = 0;
+    assign c[649:648] = a[217:216];
+    assign c[651:650] = a[553:552];
+    assign c[653:652] = 0;
+    assign c[655:654] = a[219:218];
+    assign c[657:656] = a[555:554];
+    assign c[659:658] = 0;
+    assign c[661:660] = {a[486], a[487]};
+    assign c[663:662] = a[557:556];
+    assign c[665:664] = 0;
+    assign c[667:666] = {a[488], a[489]};
+    assign c[669:668] = a[559:558];
+    assign c[671:670] = 0;
+    assign c[673:672] = a[757:756];
+    assign c[675:674] = a[827:826];
+    assign c[677:676] = 0;
+    assign c[679:678] = a[759:758];
+    assign c[681:680] = a[829:828];
+    assign c[683:682] = 0;
+    assign c[685:684] = a[761:760];
+    assign c[687:686] = a[831:830];
+    assign c[689:688] = 0;
+    assign c[691:690] = a[231:230];
+    assign c[693:692] = a[567:566];
+    assign c[695:694] = 0;
+    assign c[697:696] = a[233:232];
+    assign c[699:698] = a[569:568];
+    assign c[701:700] = 0;
+    assign c[703:702] = a[235:234];
+    assign c[705:704] = a[571:570];
+    assign c[707:706] = 0;
+    assign c[709:708] = {a[502], a[503]};
+    assign c[711:710] = a[573:572];
+    assign c[713:712] = 0;
+    assign c[715:714] = {a[504], a[505]};
+    assign c[717:716] = a[575:574];
+    assign c[719:718] = 0;
+    assign c[721:720] = a[773:772];
+    assign c[723:722] = a[843:842];
+    assign c[725:724] = 0;
+    assign c[727:726] = a[775:774];
+    assign c[729:728] = a[845:844];
+    assign c[731:730] = 0;
+    assign c[733:732] = a[777:776];
+    assign c[735:734] = a[847:846];
+    assign c[737:736] = 0;
+    assign c[739:738] = a[247:246];
+    assign c[741:740] = a[583:582];
+    assign c[743:742] = 0;
+    assign c[745:744] = a[249:248];
+    assign c[747:746] = a[585:584];
+    assign c[749:748] = 0;
+    assign c[751:750] = a[251:250];
+    assign c[753:752] = a[587:586];
+    assign c[755:754] = 0;
+    assign c[757:756] = {a[518], a[519]};
+    assign c[759:758] = a[589:588];
+    assign c[761:760] = 0;
+    assign c[763:762] = {a[520], a[521]};
+    assign c[765:764] = a[591:590];
+    assign c[767:766] = 0;
+    assign c[769:768] = a[789:788];
+    assign c[771:770] = a[859:858];
+    assign c[773:772] = 0;
+    assign c[775:774] = a[791:790];
+    assign c[777:776] = a[861:860];
+    assign c[779:778] = 0;
+    assign c[781:780] = a[793:792];
+    assign c[783:782] = a[863:862];
+    assign c[785:784] = 0;
+    assign c[787:786] = a[263:262];
+    assign c[789:788] = a[599:598];
+    assign c[791:790] = 0;
+    assign c[793:792] = a[265:264];
+    assign c[795:794] = a[601:600];
+    assign c[797:796] = 0;
+    assign c[799:798] = a[267:266];
+    assign c[801:800] = a[603:602];
+    assign c[803:802] = 0;
+    assign c[805:804] = {a[534], a[535]};
+    assign c[807:806] = a[605:604];
+    assign c[809:808] = 0;
+    assign c[811:810] = {a[536], a[537]};
+    assign c[813:812] = a[607:606];
+    assign c[815:814] = 0;
+    assign c[817:816] = a[805:804];
+    assign c[819:818] = a[875:874];
+    assign c[821:820] = 0;
+    assign c[823:822] = a[807:806];
+    assign c[825:824] = a[877:876];
+    assign c[827:826] = 0;
+    assign c[829:828] = a[809:808];
+    assign c[831:830] = a[879:878];
+    assign c[833:832] = 0;
+    assign c[835:834] = a[279:278];
+    assign c[837:836] = a[615:614];
+    assign c[839:838] = 0;
+    assign c[841:840] = a[281:280];
+    assign c[843:842] = a[617:616];
+    assign c[845:844] = 0;
+    assign c[847:846] = a[283:282];
+    assign c[849:848] = a[619:618];
+    assign c[851:850] = 0;
+    assign c[853:852] = {a[550], a[551]};
+    assign c[855:854] = a[621:620];
+    assign c[857:856] = 0;
+    assign c[859:858] = {a[552], a[553]};
+    assign c[861:860] = a[623:622];
+    assign c[863:862] = 0;
+    assign c[865:864] = a[821:820];
+    assign c[867:866] = a[891:890];
+    assign c[869:868] = 0;
+    assign c[871:870] = a[823:822];
+    assign c[873:872] = a[893:892];
+    assign c[875:874] = 0;
+    assign c[877:876] = a[825:824];
+    assign c[879:878] = a[895:894];
+    assign c[881:880] = 0;
+    assign c[883:882] = a[295:294];
+    assign c[885:884] = a[631:630];
+    assign c[887:886] = 0;
+    assign c[889:888] = a[297:296];
+    assign c[891:890] = a[633:632];
+    assign c[893:892] = 0;
+    assign c[895:894] = a[299:298];
+    assign c[897:896] = a[635:634];
+    assign c[899:898] = 0;
+    assign c[901:900] = {a[566], a[567]};
+    assign c[903:902] = a[637:636];
+    assign c[905:904] = 0;
+    assign c[907:906] = {a[568], a[569]};
+    assign c[909:908] = a[639:638];
+    assign c[911:910] = 0;
+    assign c[913:912] = a[837:836];
+    assign c[915:914] = a[907:906];
+    assign c[917:916] = 0;
+    assign c[919:918] = a[839:838];
+    assign c[921:920] = a[909:908];
+    assign c[923:922] = 0;
+    assign c[925:924] = a[841:840];
+    assign c[927:926] = a[911:910];
+    assign c[929:928] = 0;
+    assign c[931:930] = a[311:310];
+    assign c[933:932] = a[647:646];
+    assign c[935:934] = 0;
+    assign c[937:936] = a[313:312];
+    assign c[939:938] = a[649:648];
+    assign c[941:940] = 0;
+    assign c[943:942] = a[315:314];
+    assign c[945:944] = a[651:650];
+    assign c[947:946] = 0;
+    assign c[949:948] = {a[582], a[583]};
+    assign c[951:950] = a[653:652];
+    assign c[95'b'3:952] = 0;
+    assign c[955:954] = {a[584], a[585]};
+    assign c[957:956] = a[655:654];
+    assign c[959:958] = 0;
+    assign c[961:960] = a[853:852];
+    assign c[963:962] = a[923:922];
+    assign c[965:964] = 0;
+    assign c[967:966] = a[855:854];
+    assign c[969:968] = a[925:924];
+    assign c[971:970] = 0;
+    assign c[973:972] = a[857:856];
+    assign c[975:974] = a[927:926];
+    assign c[977:976] = 0;
+    assign c[979:978] = a[327:326];
+    assign c[981:980] = a[663:662];
+    assign c[983:982] = 0;
+    assign c[985:984] = a[329:328];
+    assign c[987:986] = a[665:664];
+    assign c[989:988] = 0;
+    assign c[991:990] = a[331:330];
+    assign c[993:992] = a[667:666];
+    assign c[995:994] = 0;
+    assign c[997:996] = {a[598], a[599]};
+    assign c[999:998] = a[669:668];
+    assign c[1001:1000] = 0;
+    assign c[1003:1002] = {a[600], a[601]};
+    assign c[1005:1004] = a[671:670];
+endmodule
+/* c == v2(a) */
+module v2(a, c);
+    input [1005:0] a;
+    output [1005:0] c;
+    assign c[1:0] = 0;
+    assign c[3:2] = {a[602], a[603]};
+    assign c[5:4] = 0;
+    assign c[7:6] = 0;
+    assign c[9:8] = {a[604], a[605]};
+    assign c[11:10] = 0;
+    assign c[13:12] = 0;
+    assign c[15:14] = {a[606], a[607]};
+    assign c[17:16] = 0;
+    assign c[19:18] = 0;
+    assign c[21:20] = a[875:874];
+    assign c[23:22] = 0;
+    assign c[25:24] = 0;
+    assign c[27:26] = a[877:876];
+    assign c[29:28] = 0;
+    assign c[31:30] = 0;
+    assign c[33:32] = a[879:878];
+    assign c[35:34] = 0;
+    assign c[37:36] = 0;
+    assign c[39:38] = a[349:348];
+    assign c[41:40] = 0;
+    assign c[43:42] = 0;
+    assign c[45:44] = a[351:350];
+    assign c[47:46] = 0;
+    assign c[49:48] = 0;
+    assign c[51:50] = {a[618], a[619]};
+    assign c[53:52] = 0;
+    assign c[55:54] = 0;
+    assign c[57:56] = {a[620], a[621]};
+    assign c[59:58] = 0;
+    assign c[61:60] = 0;
+    assign c[63:62] = {a[622], a[623]};
+    assign c[65:64] = 0;
+    assign c[67:66] = 0;
+    assign c[69:68] = a[891:890];
+    assign c[71:70] = 0;
+    assign c[73:72] = 0;
+    assign c[75:74] = a[893:892];
+    assign c[77:76] = 0;
+    assign c[79:78] = 0;
+    assign c[81:80] = a[895:894];
+    assign c[83:82] = 0;
+    assign c[85:84] = 0;
+    assign c[87:86] = a[365:364];
+    assign c[89:88] = 0;
+    assign c[91:90] = 0;
+    assign c[93:92] = a[367:366];
+    assign c[95:94] = 0;
+    assign c[97:96] = 0;
+    assign c[99:98] = {a[634], a[635]};
+    assign c[101:100] = 0;
+    assign c[103:102] = 0;
+    assign c[105:104] = {a[636], a[637]};
+    assign c[107:106] = 0;
+    assign c[109:108] = 0;
+    assign c[111:110] = {a[638], a[639]};
+    assign c[113:112] = 0;
+    assign c[115:114] = 0;
+    assign c[117:116] = a[907:906];
+    assign c[119:118] = 0;
+    assign c[121:120] = 0;
+    assign c[123:122] = a[909:908];
+    assign c[125:124] = 0;
+    assign c[127:126] = 0;
+    assign c[129:128] = a[911:910];
+    assign c[131:130] = 0;
+    assign c[133:132] = 0;
+    assign c[135:134] = a[381:380];
+    assign c[137:136] = 0;
+    assign c[139:138] = 0;
+    assign c[141:140] = a[383:382];
+    assign c[143:142] = 0;
+    assign c[145:144] = 0;
+    assign c[147:146] = {a[650], a[651]};
+    assign c[149:148] = 0;
+    assign c[151:150] = 0;
+    assign c[153:152] = {a[652], a[653]};
+    assign c[155:154] = 0;
+    assign c[157:156] = 0;
+    assign c[159:158] = {a[654], a[655]};
+    assign c[161:160] = 0;
+    assign c[163:162] = 0;
+    assign c[165:164] = a[923:922];
+    assign c[167:166] = 0;
+    assign c[169:168] = 0;
+    assign c[171:170] = a[925:924];
+    assign c[173:172] = 0;
+    assign c[175:174] = 0;
+    assign c[177:176] = a[927:926];
+    assign c[179:178] = 0;
+    assign c[181:180] = 0;
+    assign c[183:182] = a[397:396];
+    assign c[185:184] = 0;
+    assign c[187:186] = 0;
+    assign c[189:188] = a[399:398];
+    assign c[191:190] = 0;
+    assign c[193:192] = 0;
+    assign c[195:194] = {a[666], a[667]};
+    assign c[197:196] = 0;
+    assign c[199:198] = 0;
+    assign c[201:200] = {a[668], a[669]};
+    assign c[203:202] = 0;
+    assign c[205:204] = 0;
+    assign c[207:206] = {a[670], a[671]};
+    assign c[209:208] = 0;
+    assign c[211:210] = a[71:70];
+    assign c[213:212] = 0;
+    assign c[215:214] = 0;
+    assign c[217:216] = a[73:72];
+    assign c[219:218] = 0;
+    assign c[221:220] = 0;
+    assign c[223:222] = a[75:74];
+    assign c[225:224] = 0;
+    assign c[227:226] = 0;
+    assign c[229:228] = {a[874], a[875]};
+    assign c[231:230] = 0;
+    assign c[233:232] = 0;
+    assign c[235:234] = {a[876], a[877]};
+    assign c[237:236] = 0;
+    assign c[239:238] = 0;
+    assign c[241:240] = {a[346], a[347]};
+    assign c[243:242] = 0;
+    assign c[245:244] = 0;
+    assign c[247:246] = a[615:614];
+    assign c[249:248] = 0;
+    assign c[251:250] = 0;
+    assign c[253:252] = a[617:616];
+    assign c[255:254] = 0;
+    assign c[257:256] = 0;
+    assign c[259:258] = a[87:86];
+    assign c[261:260] = 0;
+    assign c[263:262] = 0;
+    assign c[265:264] = a[89:88];
+    assign c[267:266] = 0;
+    assign c[269:268] = 0;
+    assign c[271:270] = a[91:90];
+    assign c[273:272] = 0;
+    assign c[275:274] = 0;
+    assign c[277:276] = {a[890], a[891]};
+    assign c[279:278] = 0;
+    assign c[281:280] = 0;
+    assign c[283:282] = {a[892], a[893]};
+    assign c[285:284] = 0;
+    assign c[287:286] = 0;
+    assign c[289:288] = {a[362], a[363]};
+    assign c[291:290] = 0;
+    assign c[293:292] = 0;
+    assign c[295:294] = a[631:630];
+    assign c[297:296] = 0;
+    assign c[299:298] = 0;
+    assign c[301:300] = a[633:632];
+    assign c[303:302] = 0;
+    assign c[305:304] = 0;
+    assign c[307:306] = a[103:102];
+    assign c[309:308] = 0;
+    assign c[311:310] = 0;
+    assign c[313:312] = a[105:104];
+    assign c[315:314] = 0;
+    assign c[317:316] = 0;
+    assign c[319:318] = a[107:106];
+    assign c[321:320] = 0;
+    assign c[323:322] = 0;
+    assign c[325:324] = {a[906], a[907]};
+    assign c[327:326] = 0;
+    assign c[329:328] = 0;
+    assign c[331:330] = {a[908], a[909]};
+    assign c[333:332] = 0;
+    assign c[335:334] = 0;
+    assign c[337:336] = {a[378], a[379]};
+    assign c[339:338] = 0;
+    assign c[341:340] = 0;
+    assign c[343:342] = a[647:646];
+    assign c[345:344] = 0;
+    assign c[347:346] = 0;
+    assign c[349:348] = a[649:648];
+    assign c[351:350] = 0;
+    assign c[353:352] = 0;
+    assign c[355:354] = a[119:118];
+    assign c[357:356] = 0;
+    assign c[359:358] = 0;
+    assign c[361:360] = a[121:120];
+    assign c[363:362] = 0;
+    assign c[365:364] = 0;
+    assign c[367:366] = a[123:122];
+    assign c[369:368] = 0;
+    assign c[371:370] = 0;
+    assign c[373:372] = {a[922], a[923]};
+    assign c[375:374] = 0;
+    assign c[377:376] = 0;
+    assign c[379:378] = {a[924], a[925]};
+    assign c[381:380] = 0;
+    assign c[383:382] = 0;
+    assign c[385:384] = {a[394], a[395]};
+    assign c[387:386] = 0;
+    assign c[389:388] = 0;
+    assign c[391:390] = a[663:662];
+    assign c[393:392] = 0;
+    assign c[395:394] = 0;
+    assign c[397:396] = a[665:664];
+    assign c[399:398] = 0;
+    assign c[401:400] = 0;
+    assign c[403:402] = a[135:134];
+    assign c[405:404] = 0;
+    assign c[407:406] = 0;
+    assign c[409:408] = a[137:136];
+    assign c[411:410] = 0;
+    assign c[413:412] = 0;
+    assign c[415:414] = a[139:138];
+    assign c[417:416] = 0;
+    assign c[419:418] = 0;
+    assign c[421:420] = {a[938], a[939]};
+    assign c[423:422] = 0;
+    assign c[425:424] = 0;
+    assign c[427:426] = {a[940], a[941]};
+    assign c[429:428] = 0;
+    assign c[431:430] = 0;
+    assign c[433:432] = {a[410], a[411]};
+    assign c[435:434] = 0;
+    assign c[437:436] = 0;
+    assign c[439:438] = a[679:678];
+    assign c[441:440] = 0;
+    assign c[443:442] = 0;
+    assign c[445:444] = a[681:680];
+    assign c[447:446] = 0;
+    assign c[449:448] = 0;
+    assign c[451:450] = a[151:150];
+    assign c[453:452] = 0;
+    assign c[455:454] = 0;
+    assign c[457:456] = a[153:152];
+    assign c[459:458] = 0;
+    assign c[461:460] = 0;
+    assign c[463:462] = a[155:154];
+    assign c[465:464] = 0;
+    assign c[467:466] = 0;
+    assign c[469:468] = {a[954], a[955]};
+    assign c[471:470] = 0;
+    assign c[473:472] = 0;
+    assign c[475:474] = {a[956], a[957]};
+    assign c[477:476] = 0;
+    assign c[479:478] = 0;
+    assign c[481:480] = {a[426], a[427]};
+    assign c[483:482] = 0;
+    assign c[485:484] = 0;
+    assign c[487:486] = a[695:694];
+    assign c[489:488] = 0;
+    assign c[491:490] = 0;
+    assign c[493:492] = a[697:696];
+    assign c[495:494] = 0;
+    assign c[497:496] = 0;
+    assign c[499:498] = a[167:166];
+    assign c[501:500] = 0;
+    assign c[503:502] = 0;
+    assign c[505:504] = a[169:168];
+    assign c[507:506] = 0;
+    assign c[509:508] = 0;
+    assign c[511:510] = a[171:170];
+    assign c[513:512] = 0;
+    assign c[515:514] = 0;
+    assign c[517:516] = {a[970], a[971]};
+    assign c[519:518] = 0;
+    assign c[521:520] = 0;
+    assign c[523:522] = {a[972], a[973]};
+    assign c[525:524] = 0;
+    assign c[527:526] = 0;
+    assign c[529:528] = {a[442], a[443]};
+    assign c[531:530] = 0;
+    assign c[533:532] = 0;
+    assign c[535:534] = a[711:710];
+    assign c[537:536] = 0;
+    assign c[539:538] = 0;
+    assign c[541:540] = a[713:712];
+    assign c[543:542] = 0;
+    assign c[545:544] = 0;
+    assign c[547:546] = a[183:182];
+    assign c[549:548] = 0;
+    assign c[551:550] = 0;
+    assign c[553:552] = a[185:184];
+    assign c[555:554] = 0;
+    assign c[557:556] = 0;
+    assign c[559:558] = a[187:186];
+    assign c[561:560] = 0;
+    assign c[563:562] = 0;
+    assign c[565:564] = {a[986], a[987]};
+    assign c[567:566] = 0;
+    assign c[569:568] = 0;
+    assign c[571:570] = {a[988], a[989]};
+    assign c[573:572] = 0;
+    assign c[575:574] = 0;
+    assign c[577:576] = {a[458], a[459]};
+    assign c[579:578] = 0;
+    assign c[581:580] = 0;
+    assign c[583:582] = a[727:726];
+    assign c[585:584] = 0;
+    assign c[587:586] = 0;
+    assign c[589:588] = a[729:728];
+    assign c[591:590] = 0;
+    assign c[593:592] = 0;
+    assign c[595:594] = a[199:198];
+    assign c[597:596] = 0;
+    assign c[599:598] = 0;
+    assign c[601:600] = a[201:200];
+    assign c[603:602] = 0;
+    assign c[605:604] = 0;
+    assign c[607:606] = a[203:202];
+    assign c[609:608] = 0;
+    assign c[611:610] = 0;
+    assign c[613:612] = {a[1002], a[1003]};
+    assign c[615:614] = 0;
+    assign c[617:616] = 0;
+    assign c[619:618] = {a[1004], a[1005]};
+    assign c[621:620] = 0;
+    assign c[623:622] = 0;
+    assign c[625:624] = {a[474], a[475]};
+    assign c[627:626] = 0;
+    assign c[629:628] = 0;
+    assign c[631:630] = {a[476], a[477]};
+    assign c[633:632] = 0;
+    assign c[635:634] = 0;
+    assign c[637:636] = {a[478], a[479]};
+    assign c[639:638] = 0;
+    assign c[641:640] = 0;
+    assign c[643:642] = a[747:746];
+    assign c[645:644] = 0;
+    assign c[647:646] = 0;
+    assign c[649:648] = a[749:748];
+    assign c[651:650] = 0;
+    assign c[653:652] = 0;
+    assign c[655:654] = a[751:750];
+    assign c[657:656] = 0;
+    assign c[659:658] = 0;
+    assign c[661:660] = a[221:220];
+    assign c[663:662] = 0;
+    assign c[665:664] = 0;
+    assign c[667:666] = a[223:222];
+    assign c[669:668] = 0;
+    assign c[671:670] = 0;
+    assign c[673:672] = {a[490], a[491]};
+    assign c[675:674] = 0;
+    assign c[677:676] = 0;
+    assign c[679:678] = {a[492], a[493]};
+    assign c[681:680] = 0;
+    assign c[683:682] = 0;
+    assign c[685:684] = {a[494], a[495]};
+    assign c[687:686] = 0;
+    assign c[689:688] = 0;
+    assign c[691:690] = a[763:762];
+    assign c[693:692] = 0;
+    assign c[695:694] = 0;
+    assign c[697:696] = a[765:764];
+    assign c[699:698] = 0;
+    assign c[701:700] = 0;
+    assign c[703:702] = a[767:766];
+    assign c[705:704] = 0;
+    assign c[707:706] = 0;
+    assign c[709:708] = a[237:236];
+    assign c[711:710] = 0;
+    assign c[713:712] = 0;
+    assign c[715:714] = a[239:238];
+    assign c[717:716] = 0;
+    assign c[719:718] = 0;
+    assign c[721:720] = {a[506], a[507]};
+    assign c[723:722] = 0;
+    assign c[725:724] = 0;
+    assign c[727:726] = {a[508], a[509]};
+    assign c[729:728] = 0;
+    assign c[731:730] = 0;
+    assign c[733:732] = {a[510], a[511]};
+    assign c[735:734] = 0;
+    assign c[737:736] = 0;
+    assign c[739:738] = a[779:778];
+    assign c[741:740] = 0;
+    assign c[743:742] = 0;
+    assign c[745:744] = a[781:780];
+    assign c[747:746] = 0;
+    assign c[749:748] = 0;
+    assign c[751:750] = a[783:782];
+    assign c[753:752] = 0;
+    assign c[755:754] = 0;
+    assign c[757:756] = a[253:252];
+    assign c[759:758] = 0;
+    assign c[761:760] = 0;
+    assign c[763:762] = a[255:254];
+    assign c[765:764] = 0;
+    assign c[767:766] = 0;
+    assign c[769:768] = {a[522], a[523]};
+    assign c[771:770] = 0;
+    assign c[773:772] = 0;
+    assign c[775:774] = {a[524], a[525]};
+    assign c[777:776] = 0;
+    assign c[779:778] = 0;
+    assign c[781:780] = {a[526], a[527]};
+    assign c[783:782] = 0;
+    assign c[785:784] = 0;
+    assign c[787:786] = a[795:794];
+    assign c[789:788] = 0;
+    assign c[791:790] = 0;
+    assign c[793:792] = a[797:796];
+    assign c[795:794] = 0;
+    assign c[797:796] = 0;
+    assign c[799:798] = a[799:798];
+    assign c[801:800] = 0;
+    assign c[803:802] = 0;
+    assign c[805:804] = a[269:268];
+    assign c[807:806] = 0;
+    assign c[809:808] = 0;
+    assign c[811:810] = a[271:270];
+    assign c[813:812] = 0;
+    assign c[815:814] = 0;
+    assign c[817:816] = {a[538], a[539]};
+    assign c[819:818] = 0;
+    assign c[821:820] = 0;
+    assign c[823:822] = {a[540], a[541]};
+    assign c[825:824] = 0;
+    assign c[827:826] = 0;
+    assign c[829:828] = {a[542], a[543]};
+    assign c[831:830] = 0;
+    assign c[833:832] = 0;
+    assign c[835:834] = a[811:810];
+    assign c[837:836] = 0;
+    assign c[839:838] = 0;
+    assign c[841:840] = a[813:812];
+    assign c[843:842] = 0;
+    assign c[845:844] = 0;
+    assign c[847:846] = a[815:814];
+    assign c[849:848] = 0;
+    assign c[851:850] = 0;
+    assign c[853:852] = a[285:284];
+    assign c[855:854] = 0;
+    assign c[857:856] = 0;
+    assign c[859:858] = a[287:286];
+    assign c[861:860] = 0;
+    assign c[863:862] = 0;
+    assign c[865:864] = {a[554], a[555]};
+    assign c[867:866] = 0;
+    assign c[869:868] = 0;
+    assign c[871:870] = {a[556], a[557]};
+    assign c[873:872] = 0;
+    assign c[875:874] = 0;
+    assign c[877:876] = {a[558], a[559]};
+    assign c[879:878] = 0;
+    assign c[881:880] = 0;
+    assign c[883:882] = a[827:826];
+    assign c[885:884] = 0;
+    assign c[887:886] = 0;
+    assign c[889:888] = a[829:828];
+    assign c[891:890] = 0;
+    assign c[893:892] = 0;
+    assign c[895:894] = a[831:830];
+    assign c[897:896] = 0;
+    assign c[899:898] = 0;
+    assign c[901:900] = a[301:300];
+    assign c[903:902] = 0;
+    assign c[905:904] = 0;
+    assign c[907:906] = a[303:302];
+    assign c[909:908] = 0;
+    assign c[911:910] = 0;
+    assign c[913:912] = {a[570], a[571]};
+    assign c[915:914] = 0;
+    assign c[917:916] = 0;
+    assign c[919:918] = {a[572], a[573]};
+    assign c[921:920] = 0;
+    assign c[923:922] = 0;
+    assign c[925:924] = {a[574], a[575]};
+    assign c[927:926] = 0;
+    assign c[929:928] = 0;
+    assign c[931:930] = a[843:842];
+    assign c[933:932] = 0;
+    assign c[935:934] = 0;
+    assign c[937:936] = a[845:844];
+    assign c[939:938] = 0;
+    assign c[941:940] = 0;
+    assign c[943:942] = a[847:846];
+    assign c[945:944] = 0;
+    assign c[947:946] = 0;
+    assign c[949:948] = a[317:316];
+    assign c[951:950] = 0;
+    assign c[953:952] = 0;
+    assign c[955:954] = a[319:318];
+    assign c[957:956] = 0;
+    assign c[959:958] = 0;
+    assign c[961:960] = {a[586], a[587]};
+    assign c[963:962] = 0;
+    assign c[965:964] = 0;
+    assign c[967:966] = {a[588], a[589]};
+    assign c[969:968] = 0;
+    assign c[971:970] = 0;
+    assign c[973:972] = {a[590], a[591]};
+    assign c[975:974] = 0;
+    assign c[977:976] = 0;
+    assign c[979:978] = a[859:858];
+    assign c[981:980] = 0;
+    assign c[983:982] = 0;
+    assign c[985:984] = a[861:860];
+    assign c[987:986] = 0;
+    assign c[989:988] = 0;
+    assign c[991:990] = a[863:862];
+    assign c[993:992] = 0;
+    assign c[995:994] = 0;
+    assign c[997:996] = a[333:332];
+    assign c[999:998] = 0;
+    assign c[1001:1000] = 0;
+    assign c[1003:1002] = a[335:334];
+    assign c[1005:1004] = 0;
+endmodule
+/* c == v3(a) */
+module v3(a, c);
+    input [1005:0] a;
+    output [1005:0] c;
+    assign c[1:0] = 0;
+    assign c[3:2] = 0;
+    assign c[5:4] = 0;
+    assign c[7:6] = 0;
+    assign c[9:8] = 0;
+    assign c[11:10] = 0;
+    assign c[13:12] = 0;
+    assign c[15:14] = 0;
+    assign c[17:16] = 0;
+    assign c[19:18] = 0;
+    assign c[21:20] = 0;
+    assign c[23:22] = 0;
+    assign c[25:24] = 0;
+    assign c[27:26] = 0;
+    assign c[29:28] = 0;
+    assign c[31:30] = 0;
+    assign c[33:32] = 0;
+    assign c[35:34] = 0;
+    assign c[37:36] = 0;
+    assign c[39:38] = 0;
+    assign c[41:40] = 0;
+    assign c[43:42] = 0;
+    assign c[45:44] = 0;
+    assign c[47:46] = 0;
+    assign c[49:48] = 0;
+    assign c[51:50] = 0;
+    assign c[53:52] = 0;
+    assign c[55:54] = 0;
+    assign c[57:56] = 0;
+    assign c[59:58] = 0;
+    assign c[61:60] = 0;
+    assign c[63:62] = 0;
+    assign c[65:64] = 0;
+    assign c[67:66] = 0;
+    assign c[69:68] = 0;
+    assign c[71:70] = 0;
+    assign c[73:72] = 0;
+    assign c[75:74] = 0;
+    assign c[77:76] = 0;
+    assign c[79:78] = 0;
+    assign c[81:80] = 0;
+    assign c[83:82] = 0;
+    assign c[85:84] = 0;
+    assign c[87:86] = 0;
+    assign c[89:88] = 0;
+    assign c[91:90] = 0;
+    assign c[93:92] = 0;
+    assign c[95:94] = 0;
+    assign c[97:96] = 0;
+    assign c[99:98] = 0;
+    assign c[101:100] = 0;
+    assign c[103:102] = 0;
+    assign c[105:104] = 0;
+    assign c[107:106] = 0;
+    assign c[109:108] = 0;
+    assign c[111:110] = 0;
+    assign c[113:112] = 0;
+    assign c[115:114] = 0;
+    assign c[117:116] = 0;
+    assign c[119:118] = 0;
+    assign c[121:120] = 0;
+    assign c[123:122] = 0;
+    assign c[125:124] = 0;
+    assign c[127:126] = 0;
+    assign c[129:128] = 0;
+    assign c[131:130] = 0;
+    assign c[133:132] = 0;
+    assign c[135:134] = 0;
+    assign c[137:136] = 0;
+    assign c[139:138] = 0;
+    assign c[141:140] = 0;
+    assign c[143:142] = 0;
+    assign c[145:144] = 0;
+    assign c[147:146] = 0;
+    assign c[149:148] = 0;
+    assign c[151:150] = 0;
+    assign c[153:152] = 0;
+    assign c[155:154] = 0;
+    assign c[157:156] = 0;
+    assign c[159:158] = 0;
+    assign c[161:160] = 0;
+    assign c[163:162] = 0;
+    assign c[165:164] = 0;
+    assign c[167:166] = 0;
+    assign c[169:168] = 0;
+    assign c[171:170] = 0;
+    assign c[173:172] = 0;
+    assign c[175:174] = 0;
+    assign c[177:176] = 0;
+    assign c[179:178] = 0;
+    assign c[181:180] = 0;
+    assign c[183:182] = 0;
+    assign c[185:184] = 0;
+    assign c[187:186] = 0;
+    assign c[189:188] = 0;
+    assign c[191:190] = 0;
+    assign c[193:192] = 0;
+    assign c[195:194] = 0;
+    assign c[197:196] = 0;
+    assign c[199:198] = 0;
+    assign c[201:200] = 0;
+    assign c[203:202] = 0;
+    assign c[205:204] = 0;
+    assign c[207:206] = 0;
+    assign c[209:208] = 0;
+    assign c[211:210] = a[603:602];
+    assign c[213:212] = 0;
+    assign c[215:214] = 0;
+    assign c[217:216] = a[605:604];
+    assign c[219:218] = 0;
+    assign c[221:220] = 0;
+    assign c[223:222] = a[607:606];
+    assign c[225:224] = 0;
+    assign c[227:226] = 0;
+    assign c[229:228] = a[77:76];
+    assign c[231:230] = 0;
+    assign c[233:232] = 0;
+    assign c[235:234] = a[79:78];
+    assign c[237:236] = 0;
+    assign c[239:238] = 0;
+    assign c[241:240] = {a[878], a[879]};
+    assign c[243:242] = 0;
+    assign c[245:244] = 0;
+    assign c[247:246] = {a[348], a[349]};
+    assign c[249:248] = 0;
+    assign c[251:250] = 0;
+    assign c[253:252] = {a[350], a[351]};
+    assign c[255:254] = 0;
+    assign c[257:256] = 0;
+    assign c[259:258] = a[619:618];
+    assign c[261:260] = 0;
+    assign c[263:262] = 0;
+    assign c[265:264] = a[621:620];
+    assign c[267:266] = 0;
+    assign c[269:268] = 0;
+    assign c[271:270] = a[623:622];
+    assign c[273:272] = 0;
+    assign c[275:274] = 0;
+    assign c[277:276] = a[93:92];
+    assign c[279:278] = 0;
+    assign c[281:280] = 0;
+    assign c[283:282] = a[95:94];
+    assign c[285:284] = 0;
+    assign c[287:286] = 0;
+    assign c[289:288] = {a[894], a[895]};
+    assign c[291:290] = 0;
+    assign c[293:292] = 0;
+    assign c[295:294] = {a[364], a[365]};
+    assign c[297:296] = 0;
+    assign c[299:298] = 0;
+    assign c[301:300] = {a[366], a[367]};
+    assign c[303:302] = 0;
+    assign c[305:304] = 0;
+    assign c[307:306] = a[635:634];
+    assign c[309:308] = 0;
+    assign c[311:310] = 0;
+    assign c[313:312] = a[637:636];
+    assign c[315:314] = 0;
+    assign c[317:316] = 0;
+    assign c[319:318] = a[639:638];
+    assign c[321:320] = 0;
+    assign c[323:322] = 0;
+    assign c[325:324] = a[109:108];
+    assign c[327:326] = 0;
+    assign c[329:328] = 0;
+    assign c[331:330] = a[111:110];
+    assign c[333:332] = 0;
+    assign c[335:334] = 0;
+    assign c[337:336] = {a[910], a[911]};
+    assign c[339:338] = 0;
+    assign c[341:340] = 0;
+    assign c[343:342] = {a[380], a[381]};
+    assign c[345:344] = 0;
+    assign c[347:346] = 0;
+    assign c[349:348] = {a[382], a[383]};
+    assign c[351:350] = 0;
+    assign c[353:352] = 0;
+    assign c[355:354] = a[651:650];
+    assign c[357:356] = 0;
+    assign c[359:358] = 0;
+    assign c[361:360] = a[653:652];
+    assign c[363:362] = 0;
+    assign c[365:364] = 0;
+    assign c[367:366] = a[655:654];
+    assign c[369:368] = 0;
+    assign c[371:370] = 0;
+    assign c[373:372] = a[125:124];
+    assign c[375:374] = 0;
+    assign c[377:376] = 0;
+    assign c[379:378] = a[127:126];
+    assign c[381:380] = 0;
+    assign c[383:382] = 0;
+    assign c[385:384] = {a[926], a[927]};
+    assign c[387:386] = 0;
+    assign c[389:388] = 0;
+    assign c[391:390] = {a[396], a[397]};
+    assign c[393:392] = 0;
+    assign c[395:394] = 0;
+    assign c[397:396] = {a[398], a[399]};
+    assign c[399:398] = 0;
+    assign c[401:400] = 0;
+    assign c[403:402] = a[667:666];
+    assign c[405:404] = 0;
+    assign c[407:406] = 0;
+    assign c[409:408] = a[669:668];
+    assign c[411:410] = 0;
+    assign c[413:412] = 0;
+    assign c[415:414] = a[671:670];
+    assign c[417:416] = 0;
+    assign c[419:418] = 0;
+    assign c[421:420] = a[141:140];
+    assign c[423:422] = 0;
+    assign c[425:424] = 0;
+    assign c[427:426] = a[143:142];
+    assign c[429:428] = 0;
+    assign c[431:430] = 0;
+    assign c[433:432] = {a[942], a[943]};
+    assign c[435:434] = 0;
+    assign c[437:436] = 0;
+    assign c[439:438] = {a[412], a[413]};
+    assign c[441:440] = 0;
+    assign c[443:442] = 0;
+    assign c[445:444] = {a[414], a[415]};
+    assign c[447:446] = 0;
+    assign c[449:448] = 0;
+    assign c[451:450] = a[683:682];
+    assign c[453:452] = 0;
+    assign c[455:454] = 0;
+    assign c[457:456] = a[685:684];
+    assign c[459:458] = 0;
+    assign c[461:460] = 0;
+    assign c[463:462] = a[687:686];
+    assign c[465:464] = 0;
+    assign c[467:466] = 0;
+    assign c[469:468] = a[157:156];
+    assign c[471:470] = 0;
+    assign c[473:472] = 0;
+    assign c[475:474] = a[159:158];
+    assign c[477:476] = 0;
+    assign c[479:478] = 0;
+    assign c[481:480] = {a[958], a[959]};
+    assign c[483:482] = 0;
+    assign c[485:484] = 0;
+    assign c[487:486] = {a[428], a[429]};
+    assign c[489:488] = 0;
+    assign c[491:490] = 0;
+    assign c[493:492] = {a[430], a[431]};
+    assign c[495:494] = 0;
+    assign c[497:496] = 0;
+    assign c[499:498] = a[699:698];
+    assign c[501:500] = 0;
+    assign c[503:502] = 0;
+    assign c[505:504] = a[701:700];
+    assign c[507:506] = 0;
+    assign c[509:508] = 0;
+    assign c[511:510] = a[703:702];
+    assign c[513:512] = 0;
+    assign c[515:514] = 0;
+    assign c[517:516] = a[173:172];
+    assign c[519:518] = 0;
+    assign c[521:520] = 0;
+    assign c[523:522] = a[175:174];
+    assign c[525:524] = 0;
+    assign c[527:526] = 0;
+    assign c[529:528] = {a[974], a[975]};
+    assign c[531:530] = 0;
+    assign c[533:532] = 0;
+    assign c[535:534] = {a[444], a[445]};
+    assign c[537:536] = 0;
+    assign c[539:538] = 0;
+    assign c[541:540] = {a[446], a[447]};
+    assign c[543:542] = 0;
+    assign c[545:544] = 0;
+    assign c[547:546] = a[715:714];
+    assign c[549:548] = 0;
+    assign c[551:550] = 0;
+    assign c[553:552] = a[717:716];
+    assign c[555:554] = 0;
+    assign c[557:556] = 0;
+    assign c[559:558] = a[719:718];
+    assign c[561:560] = 0;
+    assign c[563:562] = 0;
+    assign c[565:564] = a[189:188];
+    assign c[567:566] = 0;
+    assign c[569:568] = 0;
+    assign c[571:570] = a[191:190];
+    assign c[573:572] = 0;
+    assign c[575:574] = 0;
+    assign c[577:576] = {a[990], a[991]};
+    assign c[579:578] = 0;
+    assign c[581:580] = 0;
+    assign c[583:582] = {a[460], a[461]};
+    assign c[585:584] = 0;
+    assign c[587:586] = 0;
+    assign c[589:588] = {a[462], a[463]};
+    assign c[591:590] = 0;
+    assign c[593:592] = 0;
+    assign c[595:594] = a[731:730];
+    assign c[597:596] = 0;
+    assign c[599:598] = 0;
+    assign c[601:600] = a[733:732];
+    assign c[603:602] = 0;
+    assign c[605:604] = 0;
+    assign c[607:606] = a[735:734];
+    assign c[609:608] = 0;
+    assign c[611:610] = 0;
+    assign c[613:612] = a[205:204];
+    assign c[615:614] = 0;
+    assign c[617:616] = 0;
+    assign c[619:618] = a[207:206];
+    assign c[621:620] = 0;
+    assign c[623:622] = 0;
+    assign c[625:624] = 0;
+    assign c[627:626] = 0;
+    assign c[629:628] = 0;
+    assign c[631:630] = 0;
+    assign c[633:632] = 0;
+    assign c[635:634] = 0;
+    assign c[637:636] = 0;
+    assign c[639:638] = 0;
+    assign c[641:640] = 0;
+    assign c[643:642] = 0;
+    assign c[645:644] = 0;
+    assign c[647:646] = 0;
+    assign c[649:648] = 0;
+    assign c[651:650] = 0;
+    assign c[653:652] = 0;
+    assign c[655:654] = 0;
+    assign c[657:656] = 0;
+    assign c[659:658] = 0;
+    assign c[661:660] = 0;
+    assign c[663:662] = 0;
+    assign c[665:664] = 0;
+    assign c[667:666] = 0;
+    assign c[669:668] = 0;
+    assign c[671:670] = 0;
+    assign c[673:672] = 0;
+    assign c[675:674] = 0;
+    assign c[677:676] = 0;
+    assign c[679:678] = 0;
+    assign c[681:680] = 0;
+    assign c[683:682] = 0;
+    assign c[685:684] = 0;
+    assign c[687:686] = 0;
+    assign c[689:688] = 0;
+    assign c[691:690] = 0;
+    assign c[693:692] = 0;
+    assign c[695:694] = 0;
+    assign c[697:696] = 0;
+    assign c[699:698] = 0;
+    assign c[701:700] = 0;
+    assign c[703:702] = 0;
+    assign c[705:704] = 0;
+    assign c[707:706] = 0;
+    assign c[709:708] = 0;
+    assign c[711:710] = 0;
+    assign c[713:712] = 0;
+    assign c[715:714] = 0;
+    assign c[717:716] = 0;
+    assign c[719:718] = 0;
+    assign c[721:720] = 0;
+    assign c[723:722] = 0;
+    assign c[725:724] = 0;
+    assign c[727:726] = 0;
+    assign c[729:728] = 0;
+    assign c[731:730] = 0;
+    assign c[733:732] = 0;
+    assign c[735:734] = 0;
+    assign c[737:736] = 0;
+    assign c[739:738] = 0;
+    assign c[741:740] = 0;
+    assign c[743:742] = 0;
+    assign c[745:744] = 0;
+    assign c[747:746] = 0;
+    assign c[749:748] = 0;
+    assign c[751:750] = 0;
+    assign c[753:752] = 0;
+    assign c[755:754] = 0;
+    assign c[757:756] = 0;
+    assign c[759:758] = 0;
+    assign c[761:760] = 0;
+    assign c[763:762] = 0;
+    assign c[765:764] = 0;
+    assign c[767:766] = 0;
+    assign c[769:768] = 0;
+    assign c[771:770] = 0;
+    assign c[773:772] = 0;
+    assign c[775:774] = 0;
+    assign c[777:776] = 0;
+    assign c[779:778] = 0;
+    assign c[781:780] = 0;
+    assign c[783:782] = 0;
+    assign c[785:784] = 0;
+    assign c[787:786] = 0;
+    assign c[789:788] = 0;
+    assign c[791:790] = 0;
+    assign c[793:792] = 0;
+    assign c[795:794] = 0;
+    assign c[797:796] = 0;
+    assign c[799:798] = 0;
+    assign c[801:800] = 0;
+    assign c[803:802] = 0;
+    assign c[805:804] = 0;
+    assign c[807:806] = 0;
+    assign c[809:808] = 0;
+    assign c[811:810] = 0;
+    assign c[813:812] = 0;
+    assign c[815:814] = 0;
+    assign c[817:816] = 0;
+    assign c[819:818] = 0;
+    assign c[821:820] = 0;
+    assign c[823:822] = 0;
+    assign c[825:824] = 0;
+    assign c[827:826] = 0;
+    assign c[829:828] = 0;
+    assign c[831:830] = 0;
+    assign c[833:832] = 0;
+    assign c[835:834] = 0;
+    assign c[837:836] = 0;
+    assign c[839:838] = 0;
+    assign c[841:840] = 0;
+    assign c[843:842] = 0;
+    assign c[845:844] = 0;
+    assign c[847:846] = 0;
+    assign c[849:848] = 0;
+    assign c[851:850] = 0;
+    assign c[853:852] = 0;
+    assign c[855:854] = 0;
+    assign c[857:856] = 0;
+    assign c[859:858] = 0;
+    assign c[861:860] = 0;
+    assign c[863:862] = 0;
+    assign c[865:864] = 0;
+    assign c[867:866] = 0;
+    assign c[869:868] = 0;
+    assign c[871:870] = 0;
+    assign c[873:872] = 0;
+    assign c[875:874] = 0;
+    assign c[877:876] = 0;
+    assign c[879:878] = 0;
+    assign c[881:880] = 0;
+    assign c[883:882] = 0;
+    assign c[885:884] = 0;
+    assign c[887:886] = 0;
+    assign c[889:888] = 0;
+    assign c[891:890] = 0;
+    assign c[893:892] = 0;
+    assign c[895:894] = 0;
+    assign c[897:896] = 0;
+    assign c[899:898] = 0;
+    assign c[901:900] = 0;
+    assign c[903:902] = 0;
+    assign c[905:904] = 0;
+    assign c[907:906] = 0;
+    assign c[909:908] = 0;
+    assign c[911:910] = 0;
+    assign c[913:912] = 0;
+    assign c[915:914] = 0;
+    assign c[917:916] = 0;
+    assign c[919:918] = 0;
+    assign c[921:920] = 0;
+    assign c[923:922] = 0;
+    assign c[925:924] = 0;
+    assign c[927:926] = 0;
+    assign c[929:928] = 0;
+    assign c[931:930] = 0;
+    assign c[933:932] = 0;
+    assign c[935:934] = 0;
+    assign c[937:936] = 0;
+    assign c[939:938] = 0;
+    assign c[941:940] = 0;
+    assign c[943:942] = 0;
+    assign c[945:944] = 0;
+    assign c[947:946] = 0;
+    assign c[949:948] = 0;
+    assign c[951:950] = 0;
+    assign c[953:952] = 0;
+    assign c[955:954] = 0;
+    assign c[957:956] = 0;
+    assign c[959:958] = 0;
+    assign c[961:960] = 0;
+    assign c[963:962] = 0;
+    assign c[965:964] = 0;
+    assign c[967:966] = 0;
+    assign c[969:968] = 0;
+    assign c[971:970] = 0;
+    assign c[973:972] = 0;
+    assign c[975:974] = 0;
+    assign c[977:976] = 0;
+    assign c[979:978] = 0;
+    assign c[981:980] = 0;
+    assign c[983:982] = 0;
+    assign c[985:984] = 0;
+    assign c[987:986] = 0;
+    assign c[989:988] = 0;
+    assign c[991:990] = 0;
+    assign c[993:992] = 0;
+    assign c[995:994] = 0;
+    assign c[997:996] = 0;
+    assign c[999:998] = 0;
+    assign c[1001:1000] = 0;
+    assign c[1003:1002] = 0;
+    assign c[1005:1004] = 0;
+endmodule
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+module ram #(
+    parameter DATA = 198,
+    parameter ADDR = 6
+) (
+    input                       clk,
+
+    // Port A
+    input   wire                a_wr,
+    input   wire    [ADDR-1:0]  a_addr,
+    input   wire    [DATA-1:0]  a_din,
+    output  reg     [DATA-1:0]  a_dout,
+    
+    // Port B
+    input   wire                b_wr,
+    input   wire    [ADDR-1:0]  b_addr,
+    input   wire    [DATA-1:0]  b_din,
+    output  reg     [DATA-1:0]  b_dout
+);
+
+    // Shared memory
+    reg [DATA-1:0] mem [(2**ADDR)-1:0];
+
+    initial begin : init
+        integer i;
+        for(i = 0; i < (2**ADDR); i = i + 1)
+            mem[i] = 0;
+    end
+
+    // Port A
+    always @(posedge clk) begin
+        a_dout      <= mem[a_addr];
+        if(a_wr) begin
+            a_dout      <= a_din;
+            mem[a_addr] <= a_din;
+        end
+    end
+
+    // Port B
+    always @(posedge clk) begin
+        b_dout      <= mem[b_addr];
+        if(b_wr) begin
+            b_dout      <= b_din;
+            mem[b_addr] <= b_din;
+        end
+    end
+
+endmodule
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+`define M     97          // M is the degree of the irreducible polynomial
+`define WIDTH (2*`M-1)    // width for a GF(3^M) element
+
+/* PE: processing element */
+module PE(clk, reset, ctrl, d0, d1, d2, out);
+    input clk;
+    input reset;
+    input [10:0] ctrl;
+    input [197:0] d0;
+    input [`WIDTH:0] d1, d2;
+    output [`WIDTH:0] out;
+    
+    reg [197:0] R0;
+    reg [`WIDTH:0] R1, R2, R3;
+    wire [1:0] e0, e1, e2; /* part of R0 */
+    wire [`WIDTH:0] ppg0, ppg1, ppg2, /* output of PPG */
+                    mx0, mx1, mx2, mx3, mx4, mx5, mx6, /* output of MUX */
+                    ad0, ad1, ad2, /* output of GF(3^m) adder */
+                    cu0, cu1, cu2, /* output of cubic */
+                    mo0, mo1, mo2, /* output of mod_p */
+                    t0, t1, t2;
+    wire c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10;
+    
+    assign {c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10} = ctrl;
+    assign mx0 = c0 ? d1 : ad2;
+    assign mx1 = c2 ? d2 : ad2;
+    always @ (posedge clk)
+        if(reset) R1 <= 0;
+        else if (c1) R1 <= mx0;
+    always @ (posedge clk)
+        if(reset) R2 <= 0;
+        else if (c3) R2 <= mx1;
+    always @ (posedge clk)
+        if(reset) R0 <= 0;
+        else if (c4) R0 <= d0;
+        else if (c5) R0 <= R0 << 6;
+    assign {e2,e1,e0} = R0[197:192];
+    PPG
+        ppg_0 (e0, R1, ppg0),
+        ppg_1 (e1, R2, ppg1),
+        ppg_2 (e2, R1, ppg2);
+    v0  v0_ (ppg0, cu0);
+    v1  v1_ (ppg1, cu1);
+    v2  v2_ (ppg2, cu2);
+    assign mx2 = c6 ? ppg0 : cu0;
+    assign mx3 = c6 ? ppg1 : cu1;
+    assign mx4 = c6 ? mo1 : cu2;
+    assign mx5 = c7 ? mo2 : R3;
+    mod_p
+        mod_p_0 (mx3, mo0),
+        mod_p_1 (ppg2, t0),
+        mod_p_2 (t0, mo1),
+        mod_p_3 (R3, t1),
+        mod_p_4 (t1, t2),
+        mod_p_5 (t2, mo2);
+    assign mx6 = c9 ? mo0 : mx3;
+    f3m_add
+        f3m_add_0 (mx2, mx6, ad0),
+        f3m_add_1 (mx4, c8 ? mx5 : 0, ad1),
+        f3m_add_2 (ad0, ad1, ad2);
+    always @ (posedge clk)
+        if (reset) R3 <= 0;
+        else if (c10) R3 <= ad2;
+        else R3 <= 0; /* change */
+    assign out = R3;
+endmodule
+
+// C = (x*B mod p(x))
+module mod_p(B, C);
+    input [`WIDTH:0] B;
+    output [`WIDTH:0] C;
+    wire [`WIDTH+2:0] A;
+    assign A = {B[`WIDTH:0], 2\'d0}; // A == B*x
+    wire [1:0] w0;
+    f3_mult m0 (A[195:194], 2\'d2, w0);
+    f3_add s0 (A[1:0], {w0[0], w0[1]}, C[1:0]); //f3_sub s0 (A[1:0], w0, C[1:0]);
+    assign C[23:2] = A[23:2];
+    wire [1:0] w12;
+    f3_mult m12 (A[195:194], 2\'d1, w12);
+    f3_add s12 (A[25:24], {w12[0], w12[1]}, C[25:24]); // f3_sub s12 (A[25:24], w12, C[25:24]);
+    assign C[193:26] = A[193:26];
+endmodule
+
+// PPG: partial product generator, C == A*d in GF(3^m)
+module PPG(d, A, C);
+    input [1:0] d;
+    input [`WIDTH:0] A;
+    output [`WIDTH:0] C;
+    genvar i;
+    generate
+        for (i=0; i < `M; i=i+1) 
+        begin: ppg0
+            f3_mult f3_mult_0 (d, A[2*i+1:2*i], C[2*i+1:2*i]);
+        end
+    endgenerate
+endmodule
+
+// f3m_add: C = A + B, in field F_{3^M}
+module f3m_add(A, B, C);
+    input [`WIDTH : 0] A, B;
+    output [`WIDTH : 0] C;
+    genvar i;
+    generate
+        for(i=0; i<`M; i=i+1) begin: aa
+            f3_add aa(A[(2*i+1) : 2*i], B[(2*i+1) : 2*i], C[(2*i+1) : 2*i]);
+        end
+    endgenerate
+endmodule
+
+// f3_add: C == A+B (mod 3)
+module f3_add(A, B, C);
+    input [1:0] A, B;
+    output [1:0] C;
+    wire a0, a1, b0, b1, c0, c1;
+    assign {a1, a0} = A;
+    assign {b1, b0} = B;
+    assign C = {c1, c0};
+    assign c0 = ( a0 & ~a1 & ~b0 & ~b1) |
+                (~a0 & ~a1 &  b0 & ~b1) |
+                (~a0 &  a1 & ~b0 &  b1) ;
+    assign c1 = (~a0 &  a1 & ~b0 & ~b1) |
+                ( a0 & ~a1 &  b0 & ~b1) |
+                (~a0 & ~a1 & ~b0 &  b1) ;
+endmodule
+
+// f3_mult: C = A*B (mod 3)
+module f3_mult(A, B, C); 
+    input [1:0] A;
+    input [1:0] B; 
+    output [1:0] C;
+    wire a0, a1, b0, b1;
+    assign {a1, a0} = A;
+    assign {b1, b0} = B;
+    assign C[0] = (~a1 & a0 & ~b1 & b0) | (a1 & ~a0 & b1 & ~b0);
+    assign C[1] = (~a1 & a0 & b1 & ~b0) | (a1 & ~a0 & ~b1 & b0);
+endmodule
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* v0(a)+v1(a)+v2(a) == a^3 in GF(3^m) */
+
+/* c == v0(a) */
+module v0(a, c);
+    input [193:0] a;
+    output [193:0] c;
+    assign c[1:0] = a[1:0];
+    assign c[3:2] = a[131:130];
+    assign c[5:4] = a[67:66];
+    assign c[7:6] = a[3:2];
+    assign c[9:8] = a[133:132];
+    assign c[11:10] = a[69:68];
+    assign c[13:12] = a[5:4];
+    assign c[15:14] = a[135:134];
+    assign c[17:16] = a[71:70];
+    assign c[19:18] = a[193:192];
+    assign c[21:20] = {a[128], a[129]};
+    assign c[23:22] = a[73:72];
+    assign c[25:24] = {a[178], a[179]};
+    assign c[27:26] = a[131:130];
+    assign c[29:28] = {a[66], a[67]};
+    assign c[31:30] = {a[180], a[181]};
+    assign c[33:32] = a[133:132];
+    assign c[35:34] = {a[68], a[69]};
+    assign c[37:36] = {a[182], a[183]};
+    assign c[39:38] = a[127:126];
+    assign c[41:40] = {a[70], a[71]};
+    assign c[43:42] = {a[184], a[185]};
+    assign c[45:44] = a[145:144];
+    assign c[47:46] = a[81:80];
+    assign c[49:48] = a[17:16];
+    assign c[51:50] = a[147:146];
+    assign c[53:52] = a[83:82];
+    assign c[55:54] = a[19:18];
+    assign c[57:56] = a[149:148];
+    assign c[59:58] = a[85:84];
+    assign c[61:60] = a[21:20];
+    assign c[63:62] = a[135:134];
+    assign c[65:64] = a[87:86];
+    assign c[67:66] = {a[192], a[193]};
+    assign c[69:68] = a[145:144];
+    assign c[71:70] = {a[80], a[81]};
+    assign c[73:72] = a[25:24];
+    assign c[75:74] = a[147:146];
+    assign c[77:76] = {a[82], a[83]};
+    assign c[79:78] = a[27:26];
+    assign c[81:80] = a[149:148];
+    assign c[83:82] = {a[84], a[85]};
+    assign c[85:84] = a[29:28];
+    assign c[87:86] = a[143:142];
+    assign c[89:88] = {a[86], a[87]};
+    assign c[91:90] = a[31:30];
+    assign c[93:92] = a[161:160];
+    assign c[95:94] = a[97:96];
+    assign c[97:96] = a[33:32];
+    assign c[99:98] = a[163:162];
+    assign c[101:100] = a[99:98];
+    assign c[103:102] = a[35:34];
+    assign c[105:104] = a[165:164];
+    assign c[107:106] = a[101:100];
+    assign c[109:108] = a[37:36];
+    assign c[111:110] = a[151:150];
+    assign c[113:112] = a[103:102];
+    assign c[115:114] = a[39:38];
+    assign c[117:116] = a[161:160];
+    assign c[119:118] = {a[96], a[97]};
+    assign c[121:120] = a[41:40];
+    assign c[123:122] = a[163:162];
+    assign c[125:124] = {a[98], a[99]};
+    assign c[127:126] = a[43:42];
+    assign c[129:128] = a[165:164];
+    assign c[131:130] = {a[100], a[101]};
+    assign c[133:132] = a[45:44];
+    assign c[135:134] = a[159:158];
+    assign c[137:136] = {a[102], a[103]};
+    assign c[139:138] = a[47:46];
+    assign c[141:140] = a[177:176];
+    assign c[143:142] = a[113:112];
+    assign c[145:144] = a[49:48];
+    assign c[147:146] = a[179:178];
+    assign c[149:148] = a[115:114];
+    assign c[151:150] = a[51:50];
+    assign c[153:152] = a[181:180];
+    assign c[155:154] = a[117:116];
+    assign c[157:156] = a[53:52];
+    assign c[159:158] = a[167:166];
+    assign c[161:160] = a[119:118];
+    assign c[163:162] = a[55:54];
+    assign c[165:164] = a[177:176];
+    assign c[167:166] = {a[112], a[113]};
+    assign c[169:168] = a[57:56];
+    assign c[171:170] = a[179:178];
+    assign c[173:172] = {a[114], a[115]};
+    assign c[175:174] = a[59:58];
+    assign c[177:176] = a[181:180];
+    assign c[179:178] = {a[116], a[117]};
+    assign c[181:180] = a[61:60];
+    assign c[183:182] = a[175:174];
+    assign c[185:184] = {a[118], a[119]};
+    assign c[187:186] = a[63:62];
+    assign c[189:188] = a[193:192];
+    assign c[191:190] = a[129:128];
+    assign c[193:192] = a[65:64];
+endmodule
+/* c == v1(a) */
+module v1(a, c);
+    input [193:0] a;
+    output [193:0] c;
+    assign c[1:0] = a[179:178];
+    assign c[3:2] = {a[122], a[123]};
+    assign c[5:4] = 0;
+    assign c[7:6] = a[181:180];
+    assign c[9:8] = {a[124], a[125]};
+    assign c[11:10] = 0;
+    assign c[13:12] = a[183:182];
+    assign c[15:14] = {a[126], a[127]};
+    assign c[17:16] = 0;
+    assign c[19:18] = a[7:6];
+    assign c[21:20] = a[137:136];
+    assign c[23:22] = 0;
+    assign c[25:24] = a[9:8];
+    assign c[27:26] = a[139:138];
+    assign c[29:28] = a[75:74];
+    assign c[31:30] = a[11:10];
+    assign c[33:32] = a[125:124];
+    assign c[35:34] = a[77:76];
+    assign c[37:36] = a[13:12];
+    assign c[39:38] = a[135:134];
+    assign c[41:40] = a[79:78];
+    assign c[43:42] = a[15:14];
+    assign c[45:44] = a[129:128];
+    assign c[47:46] = {a[72], a[73]};
+    assign c[49:48] = {a[186], a[187]};
+    assign c[51:50] = a[139:138];
+    assign c[53:52] = {a[74], a[75]};
+    assign c[55:54] = {a[188], a[189]};
+    assign c[57:56] = a[133:132];
+    assign c[59:58] = {a[76], a[77]};
+    assign c[61:60] = {a[190], a[191]};
+    assign c[63:62] = a[151:150];
+    assign c[65:64] = {a[78], a[79]};
+    assign c[67:66] = a[23:22];
+    assign c[69:68] = a[137:136];
+    assign c[71:70] = a[89:88];
+    assign c[73:72] = 0;
+    assign c[75:74] = a[155:154];
+    assign c[77:76] = a[91:90];
+    assign c[79:78] = 0;
+    assign c[81:80] = a[141:140];
+    assign c[83:82] = a[93:92];
+    assign c[85:84] = 0;
+    assign c[87:86] = a[151:150];
+    assign c[89:88] = a[95:94];
+    assign c[91:90] = 0;
+    assign c[93:92] = a[145:144];
+    assign c[95:94] = {a[88], a[89]};
+    assign c[97:96] = 0;
+    assign c[99:98] = a[155:154];
+    assign c[101:100] = {a[90], a[91]};
+    assign c[103:102] = 0;
+    assign c[105:104] = a[149:148];
+    assign c[107:106] = {a[92], a[93]};
+    assign c[109:108] = 0;
+    assign c[111:110] = a[167:166];
+    assign c[113:112] = {a[94], a[95]};
+    assign c[115:114] = 0;
+    assign c[117:116] = a[153:152];
+    assign c[119:118] = a[105:104];
+    assign c[121:120] = 0;
+    assign c[123:122] = a[171:170];
+    assign c[125:124] = a[107:106];
+    assign c[127:126] = 0;
+    assign c[129:128] = a[157:156];
+    assign c[131:130] = a[109:108];
+    assign c[133:132] = 0;
+    assign c[135:134] = a[167:166];
+    assign c[137:136] = a[111:110];
+    assign c[139:138] = 0;
+    assign c[141:140] = a[161:160];
+    assign c[143:142] = {a[104], a[105]};
+    assign c[145:144] = 0;
+    assign c[147:146] = a[171:170];
+    assign c[149:148] = {a[106], a[107]};
+    assign c[151:150] = 0;
+    assign c[153:152] = a[165:164];
+    assign c[155:154] = {a[108], a[109]};
+    assign c[157:156] = 0;
+    assign c[159:158] = a[183:182];
+    assign c[161:160] = {a[110], a[111]};
+    assign c[163:162] = 0;
+    assign c[165:164] = a[169:168];
+    assign c[167:166] = a[121:120];
+    assign c[169:168] = 0;
+    assign c[171:170] = a[187:186];
+    assign c[173:172] = a[123:122];
+    assign c[175:174] = 0;
+    assign c[177:176] = a[173:172];
+    assign c[179:178] = a[125:124];
+    assign c[181:180] = 0;
+    assign c[183:182] = a[183:182];
+    assign c[185:184] = a[127:126];
+    assign c[187:186] = 0;
+    assign c[189:188] = a[177:176];
+    assign c[191:190] = {a[120], a[121]};
+    assign c[193:192] = 0;
+endmodule
+/* c == v2(a) */
+module v2(a, c);
+    input [193:0] a;
+    output [193:0] c;
+    assign c[1:0] = a[187:186];
+    assign c[3:2] = 0;
+    assign c[5:4] = 0;
+    assign c[7:6] = a[189:188];
+    assign c[9:8] = 0;
+    assign c[11:10] = 0;
+    assign c[13:12] = a[191:190];
+    assign c[15:14] = 0;
+    assign c[17:16] = 0;
+    assign c[19:18] = a[185:184];
+    assign c[21:20] = 0;
+    assign c[23:22] = 0;
+    assign c[25:24] = 0;
+    assign c[27:26] = a[123:122];
+    assign c[29:28] = 0;
+    assign c[31:30] = 0;
+    assign c[33:32] = a[141:140];
+    assign c[35:34] = 0;
+    assign c[37:36] = 0;
+    assign c[39:38] = a[143:142];
+    assign c[41:40] = 0;
+    assign c[43:42] = 0;
+    assign c[45:44] = a[137:136];
+    assign c[47:46] = 0;
+    assign c[49:48] = 0;
+    assign c[51:50] = a[131:130];
+    assign c[53:52] = 0;
+    assign c[55:54] = 0;
+    assign c[57:56] = a[141:140];
+    assign c[59:58] = 0;
+    assign c[61:60] = 0;
+    assign c[63:62] = a[143:142];
+    assign c[65:64] = 0;
+    assign c[67:66] = 0;
+    assign c[69:68] = a[153:152];
+    assign c[71:70] = 0;
+    assign c[73:72] = 0;
+    assign c[75:74] = a[139:138];
+    assign c[77:76] = 0;
+    assign c[79:78] = 0;
+    assign c[81:80] = a[157:156];
+    assign c[83:82] = 0;
+    assign c[85:84] = 0;
+    assign c[87:86] = a[159:158];
+    assign c[89:88] = 0;
+    assign c[91:90] = 0;
+    assign c[93:92] = a[153:152];
+    assign c[95:94] = 0;
+    assign c[97:96] = 0;
+    assign c[99:98] = a[147:146];
+    assign c[101:100] = 0;
+    assign c[103:102] = 0;
+    assign c[105:104] = a[157:156];
+    assign c[107:106] = 0;
+    assign c[109:108] = 0;
+    assign c[111:110] = a[159:158];
+    assign c[113:112] = 0;
+    assign c[115:114] = 0;
+    assign c[117:116] = a[169:168];
+    assign c[119:118] = 0;
+    assign c[121:120] = 0;
+    assign c[123:122] = a[155:154];
+    assign c[125:124] = 0;
+    assign c[127:126] = 0;
+    assign c[129:128] = a[173:172];
+    assign c[131:130] = 0;
+    assign c[133:132] = 0;
+    assign c[135:134] = a[175:174];
+    assign c[137:136] = 0;
+    assign c[139:138] = 0;
+    assign c[141:140] = a[169:168];
+    assign c[143:142] = 0;
+    assign c[145:144] = 0;
+    assign c[147:146] = a[163:162];
+    assign c[149:148] = 0;
+    assign c[151:150] = 0;
+    assign c[153:152] = a[173:172];
+    assign c[155:154] = 0;
+    assign c[157:156] = 0;
+    assign c[159:158] = a[175:174];
+    assign c[161:160] = 0;
+    assign c[163:162] = 0;
+    assign c[165:164] = a[185:184];
+    assign c[167:166] = 0;
+    assign c[169:168] = 0;
+    assign c[171:170] = a[171:170];
+    assign c[173:172] = 0;
+    assign c[175:174] = 0;
+    assign c[177:176] = a[189:188];
+    assign c[179:178] = 0;
+    assign c[181:180] = 0;
+    assign c[183:182] = a[191:190];
+    assign c[185:184] = 0;
+    assign c[187:186] = 0;
+    assign c[189:188] = a[185:184];
+    assign c[191:190] = 0;
+    assign c[193:192] = 0;
+endmodule
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+`timescale 1ns / 1ps
+`define P 20 // clock period
+
+module test_const;
+
+\t// Inputs
+    reg clk;
+\treg [5:0] addr;
+
+\t// Outputs
+\twire [1187:0] out;
+\twire effective;
+    reg [1187:0] w_out;
+    reg w_effective;
+    
+\t// Instantiate the Unit Under Test (UUT)
+\tconst_ uut (
+        .clk(clk),
+\t\t.addr(addr), 
+\t\t.out(out), 
+\t\t.effective(effective)
+\t);
+
+\tinitial begin
+\t\t// Initialize Inputs
+\t\taddr = 0; clk = 0;
+
+\t\t// Wait 100 ns for global reset to finish
+\t\t#100;
+        
+\t\t// Add stimulus here
+        @ (negedge clk);
+        addr = 1; w_out = 0; w_effective = 1;
+        #(`P); check;
+        addr = 2; w_out = 1;
+        #(`P); check;
+        addr = 4; w_out = {6\'b000101, 1182\'d0};
+        #(`P); check;
+        addr = 8; w_out = {6\'b001001, 1182\'d0};
+        #(`P); check;
+        addr = 16; w_out = {6\'b010101, 1182\'d0};
+        #(`P); check;
+        addr = 0; w_out = 0; w_effective = 0;
+        #(`P); check;
+        $display(""Good"");
+        $finish;
+\tend
+
+    initial #100 forever #(`P/2) clk = ~clk;
+
+    task check;
+      begin
+        if (out !== w_out || effective !== w_effective)
+            $display(""E %d %h %h"", addr, out, w_out);
+      end
+    endtask
+endmodule
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+`timescale 1ns / 1ps
+`define P 20
+
+`define M     503         // M is the degree of the irreducible polynomial
+`define WIDTH (2*`M-1)    // width for a GF(3^M) element
+`define WIDTH_D0 (1008-1)
+
+module test_pe;
+
+\t// Inputs
+\treg clk;
+\treg reset;
+\treg [10:0] ctrl;
+\treg [`WIDTH_D0:0] d0;
+\treg [`WIDTH:0] d1;
+\treg [`WIDTH:0] d2;
+    reg [`WIDTH:0] wish;
+
+\t// Outputs
+\twire [`WIDTH:0] out;
+
+\t// Instantiate the Unit Under Test (UUT)
+\tPE uut (
+\t\t.clk(clk), 
+\t\t.reset(reset), 
+\t\t.ctrl(ctrl), 
+\t\t.d0(d0), 
+\t\t.d1(d1), 
+        .d2(d2),
+\t\t.out(out)
+\t);
+
+\tinitial begin
+\t\t// Initialize Inputs
+\t\tclk = 0;
+\t\treset = 0;
+\t\tctrl = 0;
+\t\td0 = 0;
+\t\td1 = 0;
+        d2 = 0;
+
+\t\t// Wait 100 ns for global reset to finish
+\t\t#100;
+        
+\t\t// Add stimulus here
+        // test mult
+        d0 = 1006\'h1119248464094a51549514585519508512555548915458194454a95a5a6550224816556284a5412965419544014a511556aa55955144aa5699655618601a19691a6691682455451456154a4585906a8615595595560656a15511545a9029959510158140619554a45a96a199aa69010216541569025125a4999591561495;
+        d1 = 1006\'h1a55960985561659551851556895049209954912568a591559455151a6a96614a415025691809658645a12a415a665241565a565896195925a558154045551590a9610255981a119295065a605955445a165985126506828941554156694564a29585611655965010115198aa64986559214641456656425290954464964;
+        d2 = d1;
+        wish = 1006\'h296690698528561902a89185a6682428590645221996249986180602212996548298118549a161545666651980291a9806a99a9911a2044444908214800aaa04402a2209496440aa11991aa5949a0152899416598196510996a5a50629996aa68a4a9150058552196045aa42209094906684805604282410248094120a61;
+        
+        @(negedge clk);
+        reset=1;#`P reset=0;
+        ctrl=11\'b11111_000000; #`P;
+        ctrl=11\'b00000_111111; #(168*`P);
+        check;
+        
+        // test cubic
+        d0 = {6\'b10101, 1002\'d0};
+        d1 = 1006\'h1119248464094a51549514585519508512555548915458194454a95a5a6550224816556284a5412965419544014a511556aa55955144aa5699655618601a19691a6691682455451456154a4585906a8615595595560656a15511545a9029959510158140619554a45a96a199aa69010216541569025125a4999591561495;
+        d2 = d1;
+        wish = 1006\'h25025a210a560a450298548062454110aa9458192245809a45964889a65a258440598a41411492199a15615080a4159911826049059a691598688804a991996924864959490519956855484104849a08904919aa59886a56859269504516a0aa604a49215a25a129458a6944aa5495981061589105441842001a50899565;
+        
+        @(negedge clk);
+        reset=1;#`P reset=0;
+        ctrl=11\'b11111_000000; #`P;
+        ctrl=1; #(`P);
+        check;
+        
+        // test add
+        d0 = {6\'b000101, 1002\'d0};
+        d1 = 1006\'h1119248464094a51549514585519508512555548915458194454a95a5a6550224816556284a5412965419544014a511556aa55955144aa5699655618601a19691a6691682455451456154a4585906a8615595595560656a15511545a9029959510158140619554a45a96a199aa69010216541569025125a4999591561495;
+        d2 = 1006\'h1a55960985561659551851556895049209954912568a591559455151a6a96614a415025691809658645a12a415a665241565a565896195925a558154045551590a9610255981a119295065a605955445a165985126506828941554156694564a29585611655965010115198aa64986559214641456656425290954464964;
+        wish = 1006\'h28628a81295051aaa9a165a181a25454182a925a2412a52291990aa80112860620285485556514459998a4281621860968100a0a1aa54025248a146064606a861509a151411626214065a0288a65820886822126495682992926a8600681281009611451962289a558a88a5451a68454a568494155865999869225995109;
+        
+        @(negedge clk);
+        reset=1;#`P reset=0;
+        ctrl=11\'b11111_000000; #`P;
+        ctrl=11\'b10001; #(`P);
+        check;
+
+        // test sub
+        d0 = {6\'b001001, 1002\'d0};
+        d1 = 1006\'h1119248464094a51549514585519508512555548915458194454a95a5a6550224816556284a5412965419544014a511556aa55955144aa5699655618601a19691a6691682455451456154a4585906a8615595595560656a15511545a9029959510158140619554a45a96a199aa69010216541569025125a4999591561495;
+        d2 = 1006\'h1a55960985561659551851556895049209954912568a591559455151a6a96614a415025691809658645a12a415a665241565a565896195925a558154045551590a9610255981a119295065a605955445a165985126506828941554156694564a29585611655965010115198aa64986559214641456656425290954464964;
+        wish = 1006\'h0684518aa2a664040289860629445826158018694a9902042a125809a488291a940156182625aa9101268690289428214145a060941615844210958468858810109081469a94940a69851592800a16416424894460a62a85810800456955425a26896a62084822a65981941204204aa94440a155a8288182a09849109a61;
+        
+        @(negedge clk);
+        reset=1;#`P reset=0;
+        ctrl=11\'b11111_000000; #`P;
+        ctrl=11\'b10001; #(`P);
+        check;
+
+        $display(""Good!"");
+        $finish;
+\tend
+
+    initial #100 forever #(`P/2) clk = ~clk;
+
+    task check;
+        begin
+          if (out !== wish)
+            begin $display(""E %h %h"", out, wish); $finish; end
+        end
+    endtask
+endmodule
+
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+`timescale 1ns / 1ps
+`define P 20 // clock period
+
+module test_const;
+
+\t// Inputs
+    reg clk;
+\treg [5:0] addr;
+
+\t// Outputs
+\twire [197:0] out;
+\twire effective;
+    reg [197:0] w_out;
+    reg w_effective;
+    
+\t// Instantiate the Unit Under Test (UUT)
+\tconst uut (
+        .clk(clk),
+\t\t.addr(addr), 
+\t\t.out(out), 
+\t\t.effective(effective)
+\t);
+
+\tinitial begin
+\t\t// Initialize Inputs
+\t\taddr = 0; clk = 0;
+
+\t\t// Wait 100 ns for global reset to finish
+\t\t#100;
+        
+\t\t// Add stimulus here
+        @ (negedge clk);
+        addr = 1; w_out = 0; w_effective = 1;
+        #(`P); check;
+        addr = 2; w_out = 1;
+        #(`P); check;
+        addr = 4; w_out = {6\'b000101, 192\'d0};
+        #(`P); check;
+        addr = 8; w_out = {6\'b001001, 192\'d0};
+        #(`P); check;
+        addr = 16; w_out = {6\'b010101, 192\'d0};
+        #(`P); check;
+        addr = 0; w_out = 0; w_effective = 0;
+        #(`P); check;
+        $display(""Good"");
+        $finish;
+\tend
+
+    initial #100 forever #(`P/2) clk = ~clk;
+
+    task check;
+      begin
+        if (out !== w_out || effective !== w_effective)
+            $display(""E %d %h %h"", addr, out, w_out);
+      end
+    endtask
+endmodule
+
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+module rom (clk, addr, out);
+   input clk;
+   input [8:0] addr;
+   output reg [28:0] out;
+   
+   always @(posedge clk)
+      case (addr)
+         0: out <= 29\'h1860042;
+         1: out <= 29\'h30d0041;
+         2: out <= 29\'h38f0041;
+         3: out <= 29\'h60046;
+         4: out <= 29\'hb01b180;
+         5: out <= 29\'hb810041;
+         6: out <= 29\'hb8bb197;
+         7: out <= 29\'hc0bb187;
+         8: out <= 29\'hcb1b187;
+         9: out <= 29\'h7ae8059;
+         10: out <= 29\'h79e8045;
+         11: out <= 29\'hbb1b185;
+         12: out <= 29\'hc2fb180;
+         13: out <= 29\'hb0fb196;
+         14: out <= 29\'h8b00056;
+         15: out <= 29\'h8a20051;
+         16: out <= 29\'h90a0045;
+         17: out <= 29\'h98fb180;
+         18: out <= 29\'h9ae8053;
+         19: out <= 29\'ha020041;
+         20: out <= 29\'ha8e0047;
+         21: out <= 29\'h1f0041;
+         22: out <= 29\'hb230041;
+         23: out <= 29\'hba50041;
+         24: out <= 29\'hc270041;
+         25: out <= 29\'hca90041;
+         26: out <= 29\'hd2b0041;
+         27: out <= 29\'h7800057;
+         28: out <= 29\'h79e0059;
+         29: out <= 29\'h8ac0058;
+         30: out <= 29\'h8a2005a;
+         31: out <= 29\'h8a20051;
+         32: out <= 29\'h92e8059;
+         33: out <= 29\'h9b48058;
+         34: out <= 29\'ha320041;
+         35: out <= 29\'hab4005a;
+         36: out <= 29\'h30d0081;
+         37: out <= 29\'h30c8042;
+         38: out <= 29\'h38f0081;
+         39: out <= 29\'h38e0047;
+         40: out <= 29\'h60046;
+         41: out <= 29\'hb000040;
+         42: out <= 29\'hb8bb187;
+         43: out <= 29\'h2db180;
+         44: out <= 29\'hc000056;
+         45: out <= 29\'hc808056;
+         46: out <= 29\'hd1e0054;
+         47: out <= 29\'hdb40052;
+         48: out <= 29\'he348052;
+         49: out <= 29\'he9e8054;
+         50: out <= 29\'hf3a8053;
+         51: out <= 29\'heba0053;
+         52: out <= 29\'hfa20055;
+         53: out <= 29\'h103e0053;
+         54: out <= 29\'h10be8053;
+         55: out <= 29\'h112e0056;
+         56: out <= 29\'hb2e8056;
+         57: out <= 29\'h11a28055;
+         58: out <= 29\'h12460052;
+         59: out <= 29\'h11c68052;
+         60: out <= 29\'h12b00057;
+         61: out <= 29\'h13360060;
+         62: out <= 29\'h13800062;
+         63: out <= 29\'h143c0064;
+         64: out <= 29\'h14b20057;
+         65: out <= 29\'h15380061;
+         66: out <= 29\'h15800056;
+         67: out <= 29\'h163a0063;
+         68: out <= 29\'hc31b19b;
+         69: out <= 29\'hdcbb1a6;
+         70: out <= 29\'h102fb1a0;
+         71: out <= 29\'hf01b19e;
+         72: out <= 29\'h12cfb1a8;
+         73: out <= 29\'h1145b1a4;
+         74: out <= 29\'hcb3b19c;
+         75: out <= 29\'he53b1aa;
+         76: out <= 29\'hbafb1a1;
+         77: out <= 29\'h1b19d;
+         78: out <= 29\'hed7b1ac;
+         79: out <= 29\'hb2db1a3;
+         80: out <= 29\'h10b00065;
+         81: out <= 29\'h11c0005d;
+         82: out <= 29\'h12408057;
+         83: out <= 29\'h13328058;
+         84: out <= 29\'hbae0060;
+         85: out <= 29\'hbc48057;
+         86: out <= 29\'hbae0056;
+         87: out <= 29\'hc320058;
+         88: out <= 29\'hc30805e;
+         89: out <= 29\'hc308040;
+         90: out <= 29\'hcc68061;
+         91: out <= 29\'hcb2805e;
+         92: out <= 29\'hb320056;
+         93: out <= 29\'hcc20063;
+         94: out <= 29\'hcb2805b;
+         95: out <= 29\'hcb20062;
+         96: out <= 29\'h320040;
+         97: out <= 29\'hcc80066;
+         98: out <= 29\'hf488066;
+         99: out <= 29\'hf3c005c;
+         100: out <= 29\'hf3c805b;
+         101: out <= 29\'h102e0058;
+         102: out <= 29\'hbae8058;
+         103: out <= 29\'hbae005c;
+         104: out <= 29\'hbae005b;
+         105: out <= 29\'hbae8065;
+         106: out <= 29\'hbae805d;
+         107: out <= 29\'h7ac8052;
+         108: out <= 29\'h8808053;
+         109: out <= 29\'h328052;
+         110: out <= 29\'h8054;
+         111: out <= 29\'hb3c8053;
+         112: out <= 29\'hb2c8055;
+         113: out <= 29\'ha40805a;
+         114: out <= 29\'haae805f;
+         115: out <= 29\'h9008041;
+         116: out <= 29\'h9ac8041;
+         117: out <= 29\'h49f0041;
+         118: out <= 29\'h1e0052;
+         119: out <= 29\'h54;
+         120: out <= 29\'hb1fb18f;
+         121: out <= 29\'hb9fb192;
+         122: out <= 29\'hc25b194;
+         123: out <= 29\'hca9b194;
+         124: out <= 29\'h1b180;
+         125: out <= 29\'hbae0058;
+         126: out <= 29\'hc2c8058;
+         127: out <= 29\'hcb28057;
+         128: out <= 29\'h57;
+         129: out <= 29\'h8056;
+         130: out <= 29\'hb220053;
+         131: out <= 29\'hb2c0055;
+         132: out <= 29\'hba3b191;
+         133: out <= 29\'hd23b193;
+         134: out <= 29\'hda7b195;
+         135: out <= 29\'he2bb195;
+         136: out <= 29\'hb2db196;
+         137: out <= 29\'hd34005b;
+         138: out <= 29\'hdae805b;
+         139: out <= 29\'he38805a;
+         140: out <= 29\'hb2c005a;
+         141: out <= 29\'hb2c8057;
+         142: out <= 29\'hb9e0052;
+         143: out <= 29\'hd1e0054;
+         144: out <= 29\'hea40054;
+         145: out <= 29\'hf220053;
+         146: out <= 29\'hfa20055;
+         147: out <= 29\'h10260055;
+         148: out <= 29\'h109fb191;
+         149: out <= 29\'h1125b193;
+         150: out <= 29\'h11a9b195;
+         151: out <= 29\'hbafb19e;
+         152: out <= 29\'hd35b19f;
+         153: out <= 29\'hebbb1a0;
+         154: out <= 29\'hf428062;
+         155: out <= 29\'hfbc8063;
+         156: out <= 29\'hfbe005d;
+         157: out <= 29\'hbae805e;
+         158: out <= 29\'hbae005d;
+         159: out <= 29\'hd34805e;
+         160: out <= 29\'heb0805b;
+         161: out <= 29\'hf32805c;
+         162: out <= 29\'h10008056;
+         163: out <= 29\'hc30005b;
+         164: out <= 29\'hcb2005c;
+         165: out <= 29\'h56;
+         166: out <= 29\'hb300059;
+         167: out <= 29\'hdb08040;
+         168: out <= 29\'he328058;
+         169: out <= 29\'h1080805c;
+         170: out <= 29\'h1131b198;
+         171: out <= 29\'h11b3b199;
+         172: out <= 29\'h1201b180;
+         173: out <= 29\'hcb1b199;
+         174: out <= 29\'hc31b180;
+         175: out <= 29\'h1b196;
+         176: out <= 29\'hb45b19b;
+         177: out <= 29\'hdc7b19c;
+         178: out <= 29\'he49b1a1;
+         179: out <= 29\'hb2c005b;
+         180: out <= 29\'hb2c005c;
+         181: out <= 29\'hdac0041;
+         182: out <= 29\'he370041;
+         183: out <= 29\'he37b19c;
+         184: out <= 29\'h10b90041;
+         185: out <= 29\'hdb7b1a1;
+         186: out <= 29\'h10b70081;
+         187: out <= 29\'he39b1a1;
+         188: out <= 29\'h10b900c1;
+         189: out <= 29\'hdb7b1a1;
+         190: out <= 29\'h10b70201;
+         191: out <= 29\'hdb7b1a1;
+         192: out <= 29\'h10b70141;
+         193: out <= 29\'he39b1a1;
+         194: out <= 29\'he390401;
+         195: out <= 29\'hdb7b19c;
+         196: out <= 29\'he370941;
+         197: out <= 29\'hdb7b19c;
+         198: out <= 29\'he371281;
+         199: out <= 29\'hdb7b19c;
+         200: out <= 29\'he372501;
+         201: out <= 29\'hdb7b19c;
+         202: out <= 29\'he374a01;
+         203: out <= 29\'hdb7b19c;
+         204: out <= 29\'hdb70041;
+         205: out <= 29\'hb37b196;
+         206: out <= 29\'hb37b196;
+         207: out <= 29\'hdc68064;
+         208: out <= 29\'he44805b;
+         209: out <= 29\'h388040;
+         210: out <= 29\'hcc88059;
+         211: out <= 29\'hc368058;
+         212: out <= 29\'h2db180;
+         213: out <= 29\'hcadb199;
+         214: out <= 29\'hb2db198;
+         215: out <= 29\'hc3a005e;
+         216: out <= 29\'hdba0060;
+         217: out <= 29\'he3c0060;
+         218: out <= 29\'h10800059;
+         219: out <= 29\'h11000056;
+         220: out <= 29\'h11b20056;
+         221: out <= 29\'hebbb180;
+         222: out <= 29\'hf3db199;
+         223: out <= 29\'h1041b196;
+         224: out <= 29\'hc31b1a1;
+         225: out <= 29\'hdb7b1a2;
+         226: out <= 29\'he39b1a3;
+         227: out <= 29\'heba805e;
+         228: out <= 29\'hf3a8060;
+         229: out <= 29\'hf3c005c;
+         230: out <= 29\'hc30805d;
+         231: out <= 29\'hc30005c;
+         232: out <= 29\'hdb6805d;
+         233: out <= 29\'he3e0057;
+         234: out <= 29\'hebe005a;
+         235: out <= 29\'h102e005a;
+         236: out <= 29\'h10800059;
+         237: out <= 29\'h11000056;
+         238: out <= 29\'h11b20056;
+         239: out <= 29\'h3fb180;
+         240: out <= 29\'hbafb199;
+         241: out <= 29\'hb35b196;
+         242: out <= 29\'hcb9b1a1;
+         243: out <= 29\'hd3bb1a2;
+         244: out <= 29\'he41b1a3;
+         245: out <= 29\'h8057;
+         246: out <= 29\'hb008056;
+         247: out <= 29\'hb2c005c;
+         248: out <= 29\'hbb28040;
+         249: out <= 29\'hbae005c;
+         250: out <= 29\'h348040;
+         251: out <= 29\'hcbc0056;
+         252: out <= 29\'hd300057;
+         253: out <= 29\'he368040;
+         254: out <= 29\'hebdb19b;
+         255: out <= 29\'hfadb180;
+         256: out <= 29\'hdb1b19b;
+         257: out <= 29\'h2fb180;
+         258: out <= 29\'h1033b19c;
+         259: out <= 29\'hb2db198;
+         260: out <= 29\'hbbdb197;
+         261: out <= 29\'hc33b19a;
+         262: out <= 29\'hcb5b19c;
+         263: out <= 29\'hd2c0057;
+         264: out <= 29\'hc348058;
+         265: out <= 29\'hd360040;
+         266: out <= 29\'hd34005a;
+         267: out <= 29\'h805b;
+         268: out <= 29\'hdbe805d;
+         269: out <= 29\'hdb60060;
+         270: out <= 29\'he04005d;
+         271: out <= 29\'he38005f;
+         272: out <= 29\'he38805a;
+         273: out <= 29\'hb2e8056;
+         274: out <= 29\'hb360056;
+         275: out <= 29\'hbb00041;
+         276: out <= 29\'heb20040;
+         277: out <= 29\'hdba005b;
+         278: out <= 29\'hc30005a;
+         279: out <= 29\'hc300058;
+         280: out <= 29\'h320040;
+         281: out <= 29\'h40;
+         282: out <= 29\'hcb90041;
+         283: out <= 29\'hd2d0041;
+         284: out <= 29\'heaf0041;
+         285: out <= 29\'hf370041;
+         286: out <= 29\'hfb10041;
+         287: out <= 29\'h10010041;
+         288: out <= 29\'hcb2005d;
+         289: out <= 29\'hcb2005f;
+         290: out <= 29\'hd34005a;
+         291: out <= 29\'hd34805e;
+         292: out <= 29\'hd348060;
+         293: out <= 29\'heba805f;
+         294: out <= 29\'hf40805e;
+         295: out <= 29\'h10400060;
+         296: out <= 29\'hcb30041;
+         297: out <= 29\'hd350041;
+         298: out <= 29\'hebb0041;
+         299: out <= 29\'hf3d0041;
+         300: out <= 29\'hfbf0041;
+         301: out <= 29\'h10410041;
+         302: out <= 29\'hcb2005d;
+         303: out <= 29\'hcb2005f;
+         304: out <= 29\'hd34005a;
+         305: out <= 29\'hd34805e;
+         306: out <= 29\'hd348060;
+         307: out <= 29\'heba805f;
+         308: out <= 29\'hf40805e;
+         309: out <= 29\'h10400060;
+         310: out <= 29\'h10b80056;
+         311: out <= 29\'h112e005b;
+         312: out <= 29\'h11b08040;
+         313: out <= 29\'h1239b198;
+         314: out <= 29\'h12adb180;
+         315: out <= 29\'hc2fb198;
+         316: out <= 29\'h37b180;
+         317: out <= 29\'h1343b1a3;
+         318: out <= 29\'hb2db197;
+         319: out <= 29\'hbb9b19b;
+         320: out <= 29\'hdc3b1a2;
+         321: out <= 29\'he45b1a3;
+         322: out <= 29\'h10ac0057;
+         323: out <= 29\'hdc2805b;
+         324: out <= 29\'h10b00040;
+         325: out <= 29\'h10c20061;
+         326: out <= 29\'h8058;
+         327: out <= 29\'hc4a8064;
+         328: out <= 29\'hc300066;
+         329: out <= 29\'h11040064;
+         330: out <= 29\'h11440065;
+         331: out <= 29\'h11448061;
+         332: out <= 29\'hb2e8056;
+         333: out <= 29\'hb300056;
+         334: out <= 29\'hbb60041;
+         335: out <= 29\'h11b80040;
+         336: out <= 29\'hc460058;
+         337: out <= 29\'hdb60061;
+         338: out <= 29\'hdb6005b;
+         339: out <= 29\'h380040;
+         340: out <= 29\'h40;
+         341: out <= 29\'he32005f;
+         342: out <= 29\'h10b8005d;
+         343: out <= 29\'he38805d;
+         344: out <= 29\'h11c4005b;
+         345: out <= 29\'h12460057;
+         346: out <= 29\'h11c68057;
+         347: out <= 29\'hcb2805f;
+         348: out <= 29\'h12b2805e;
+         349: out <= 29\'hcb2005e;
+         350: out <= 29\'h1144805b;
+         351: out <= 29\'h13448058;
+         352: out <= 29\'h11440058;
+         353: out <= 29\'h13b40060;
+         354: out <= 29\'h144e005e;
+         355: out <= 29\'hf4e805e;
+         356: out <= 29\'h13ac0040;
+         357: out <= 29\'h14ce0058;
+         358: out <= 29\'hc4e8058;
+         359: out <= 29\'hd348060;
+         360: out <= 29\'h13b4005d;
+         361: out <= 29\'hd34805d;
+         362: out <= 29\'hb2c8040;
+         363: out <= 29\'heac0057;
+         364: out <= 29\'hb2c8057;
+         365: out <= 29\'hbc20068;
+         366: out <= 29\'h15480069;
+         367: out <= 29\'h15ca0067;
+         368: out <= 29\'h164c005d;
+         369: out <= 29\'h16b8005e;
+         370: out <= 29\'h17460058;
+         371: out <= 29\'h17b2005a;
+         372: out <= 29\'h18440056;
+         373: out <= 29\'h18be0060;
+         374: out <= 29\'h19360040;
+         375: out <= 29\'h10c3b1a4;
+         376: out <= 29\'hbafb1aa;
+         377: out <= 29\'h1251b1a9;
+         378: out <= 29\'h12cbb1a6;
+         379: out <= 29\'h1357b1ac;
+         380: out <= 29\'hecfb19d;
+         381: out <= 29\'he39b1a3;
+         382: out <= 29\'h11dbb1ae;
+         383: out <= 29\'hc3db198;
+         384: out <= 29\'hcb3b1a2;
+         385: out <= 29\'hf5fb1b0;
+         386: out <= 29\'hb35b196;
+         387: out <= 29\'hd3fb19b;
+         388: out <= 29\'hde3b1b2;
+         389: out <= 29\'h41b180;
+         390: out <= 29\'hfc20066;
+         391: out <= 29\'hfbe005a;
+         392: out <= 29\'h1048005e;
+         393: out <= 29\'h10400040;
+         394: out <= 29\'hd38005a;
+         395: out <= 29\'h300040;
+         396: out <= 29\'h40;
+         397: out <= 29\'hc46005b;
+         398: out <= 29\'he000064;
+         399: out <= 29\'h11348061;
+         400: out <= 29\'h8064;
+         401: out <= 29\'h5d;
+         402: out <= 29\'h56;
+         403: out <= 29\'hd340061;
+         404: out <= 29\'hd348065;
+         405: out <= 29\'hd348059;
+         406: out <= 29\'h4c0805f;
+         407: out <= 29\'h4928065;
+         408: out <= 29\'h4920056;
+         409: out <= 29\'h53e0060;
+         410: out <= 29\'h5148057;
+         411: out <= 29\'h514005d;
+         412: out <= 29\'h5140059;
+         413: out <= 29\'h514805b;
+         414: out <= 29\'h5b80062;
+         415: out <= 29\'h6388062;
+         416: out <= 29\'h6180058;
+         417: out <= 29\'h6188057;
+         418: out <= 29\'h680005a;
+         419: out <= 29\'h700805a;
+         420: out <= 29\'h71c0058;
+         421: out <= 29\'h71c0057;
+         422: out <= 29\'h71c8066;
+         423: out <= 29\'h71c805e;
+         default: out <= 0;
+      endcase
+endmodule
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* FSM: finite state machine 
+ * halt if $ctrl == 0$
+ */
+module FSM(clk, reset, rom_addr, rom_q, ram_a_addr, ram_b_addr, ram_b_w, pe, done);
+    input clk;
+    input reset;
+    output reg [8:0] rom_addr; /* command id. extra bits? */
+    input [25:0] rom_q; /* command value */
+    output reg [5:0] ram_a_addr;
+    output reg [5:0] ram_b_addr;
+    output ram_b_w;
+    output reg [10:0] pe;
+    output reg done;
+    
+    reg [5:0] state;
+    parameter START=0, READ_SRC1=1, READ_SRC2=2, CALC=4, WAIT=8, WRITE=16, DON=32;
+\t
+    wire [5:0] dest, src1, src2, times; wire [1:0] op;
+    assign {dest, src1, op, times, src2} = rom_q;
+
+    reg [5:0] count;
+\t
+    always @ (posedge clk)
+       if (reset) 
+          state<=START; 
+       else 
+          case (state)
+             START:
+                state<=READ_SRC1;
+             READ_SRC1:
+                state<=READ_SRC2;
+             READ_SRC2:
+                if (times==0) state<=DON; else state<=CALC;
+             CALC:
+                if (count==1) state<=WAIT;
+             WAIT:
+                state<=WRITE;
+             WRITE:
+                state<=READ_SRC1;
+          endcase
+
+    /* we support two loops with 48 loop times */
+    parameter  LOOP1_START = 9\'d22,
+               LOOP1_END   = 9\'d117,
+               LOOP2_START = 9\'d280,
+               LOOP2_END   = 9\'d293;
+    reg [46:0] loop1, loop2;
+\t
+\talways @ (posedge clk)
+\t   if (reset) rom_addr<=0;
+\t   else if (state==WAIT)
+          begin
+             if(rom_addr == LOOP1_END && loop1[0])
+                rom_addr <= LOOP1_START;
+             else if(rom_addr == LOOP2_END && loop2[0])
+                rom_addr <= LOOP2_START;
+             else
+                rom_addr <= rom_addr + 1; 
+\t      end
+\t
+\talways @ (posedge clk)
+\t   if (reset) loop1 <= ~0;
+\t   else if(state==WAIT && rom_addr==LOOP1_END)
+          loop1 <= loop1 >> 1;
+\t
+\talways @ (posedge clk)
+\t   if (reset) loop2 <= ~0;
+\t   else if(state==WAIT && rom_addr==LOOP2_END)
+          loop2 <= loop2 >> 1;
+
+\talways @ (posedge clk)
+\t   if (reset)
+          count<=0;
+\t   else if (state==READ_SRC1)
+          count<=times;
+\t   else if (state==CALC)
+          count<=count-1;
+\t
+\talways @ (posedge clk)
+\t   if (reset) done<=0;
+\t   else if (state==DON) done<=1;
+\t   else done<=0;
+\t 
+    always @ (state, src1, src2)
+       case (state)
+       READ_SRC1: ram_a_addr=src1;
+       READ_SRC2: ram_a_addr=src2;
+       default: ram_a_addr=0;
+       endcase
+    
+    parameter CMD_ADD=6\'d4, CMD_SUB=6\'d8, CMD_CUBIC=6\'d16,
+              ADD=2\'d0, SUB=2\'d1, CUBIC=2\'d2, MULT=2\'d3;
+
+    always @ (posedge clk)
+       case (state)
+       READ_SRC1:
+          case (op)
+          ADD:   pe<=11\'b11001000000;
+          SUB:   pe<=11\'b11001000000;
+          CUBIC: pe<=11\'b11111000000;
+          MULT:  pe<=11\'b11110000000;
+          default: pe<=0;
+          endcase
+       READ_SRC2:
+          case (op)
+          ADD:   pe<=11\'b00110000000;
+          SUB:   pe<=11\'b00110000000;
+          CUBIC: pe<=0;
+          MULT:  pe<=11\'b00001000000;
+          default: pe<=0;
+          endcase
+       CALC:
+          case (op)
+          ADD:   pe<=11\'b00000010001;
+          SUB:   pe<=11\'b00000010001;
+          CUBIC: pe<=11\'b01010000001;
+          MULT:  pe<=11\'b00000111111;
+          default: pe<=0;
+          endcase
+       default: 
+          pe<=0;
+       endcase
+
+    always @ (state, op, src2, dest)
+       case (state)
+       READ_SRC1: 
+          case (op)
+          ADD: ram_b_addr=CMD_ADD;
+          SUB: ram_b_addr=CMD_SUB;
+          CUBIC: ram_b_addr=CMD_CUBIC;
+          default: ram_b_addr=0;
+          endcase
+       READ_SRC2: ram_b_addr=src2;
+       WRITE: ram_b_addr=dest;
+       default: ram_b_addr=0;
+       endcase
+
+    assign ram_b_w = (state==WRITE) ? 1\'b1 : 1\'b0;
+endmodule
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* FSM: finite state machine 
+ * halt if $ctrl == 0$
+ */
+module FSM(clk, reset, rom_addr, rom_q, ram_a_addr, ram_b_addr, ram_b_w, pe, done);
+    input clk;
+    input reset;
+    output reg [8:0] rom_addr; /* command id. extra bits? */
+    input [28:0] rom_q; /* command value */
+    output reg [5:0] ram_a_addr;
+    output reg [5:0] ram_b_addr;
+    output ram_b_w;
+    output reg [10:0] pe;
+    output reg done;
+    
+    reg [5:0] state;
+    parameter START=0, READ_SRC1=1, READ_SRC2=2, CALC=4, WAIT=8, WRITE=16, DON=32;
+\t
+    wire [5:0] dest, src1, src2; wire [8:0] times; wire [1:0] op;
+    assign {dest, src1, op, times, src2} = rom_q;
+
+    reg [8:0] count;
+\t
+    always @ (posedge clk)
+       if (reset) 
+          state<=START; 
+       else 
+          case (state)
+             START:
+                state<=READ_SRC1;
+             READ_SRC1:
+                state<=READ_SRC2;
+             READ_SRC2:
+                if (times==0) state<=DON; else state<=CALC;
+             CALC:
+                if (count==1) state<=WAIT;
+             WAIT:
+                state<=WRITE;
+             WRITE:
+                state<=READ_SRC1;
+          endcase
+
+    /* we support two loops */
+    parameter  LOOP1_START = 9\'d21,
+               LOOP1_END   = 9\'d116,
+               LOOP2_START = 9\'d288,
+               LOOP2_END   = 9\'d301;
+    reg [294:0] loop1, loop2;
+\t
+\talways @ (posedge clk)
+\t   if (reset) rom_addr<=0;
+\t   else if (state==WAIT)
+          begin
+             if(rom_addr == LOOP1_END && loop1[0])
+                rom_addr <= LOOP1_START;
+             else if(rom_addr == LOOP2_END && loop2[0])
+                rom_addr <= LOOP2_START;
+             else
+                rom_addr <= rom_addr + 1\'d1; 
+\t      end
+\t
+\talways @ (posedge clk)
+\t   if (reset) loop1 <= ~0;
+\t   else if(state==WAIT && rom_addr==LOOP1_END)
+          loop1 <= loop1 >> 1;
+\t
+\talways @ (posedge clk)
+\t   if (reset) loop2 <= ~0;
+\t   else if(state==WAIT && rom_addr==LOOP2_END)
+          loop2 <= loop2 >> 1;
+
+\talways @ (posedge clk)
+\t   if (reset)
+          count <= 0;
+\t   else if (state==READ_SRC1)
+          count <= times;
+\t   else if (state==CALC)
+          count <= count - 1\'d1;
+\t
+\talways @ (posedge clk)
+\t   if (reset) done<=0;
+\t   else if (state==DON) done<=1;
+\t   else done<=0;
+\t 
+    always @ (state, src1, src2)
+       case (state)
+       READ_SRC1: ram_a_addr=src1;
+       READ_SRC2: ram_a_addr=src2;
+       default: ram_a_addr=0;
+       endcase
+    
+    parameter CMD_ADD=6\'d4, CMD_SUB=6\'d8, CMD_CUBIC=6\'d16,
+              ADD=2\'d0, SUB=2\'d1, CUBIC=2\'d2, MULT=2\'d3;
+
+    always @ (posedge clk)
+       case (state)
+       READ_SRC1:
+          case (op)
+          ADD:   pe<=11\'b11001000000;
+          SUB:   pe<=11\'b11001000000;
+          CUBIC: pe<=11\'b11111000000;
+          MULT:  pe<=11\'b11110000000;
+          default: pe<=0;
+          endcase
+       READ_SRC2:
+          case (op)
+          ADD:   pe<=11\'b00110000000;
+          SUB:   pe<=11\'b00110000000;
+          CUBIC: pe<=0;
+          MULT:  pe<=11\'b00001000000;
+          default: pe<=0;
+          endcase
+       CALC:
+          case (op)
+          ADD:   pe<=11\'b00000010001;
+          SUB:   pe<=11\'b00000010001;
+          CUBIC: pe<=11\'b01010000001;
+          MULT:  pe<=11\'b00000111111;
+          default: pe<=0;
+          endcase
+       default: 
+          pe<=0;
+       endcase
+
+    always @ (state, op, src2, dest)
+       case (state)
+       READ_SRC1: 
+          case (op)
+          ADD: ram_b_addr=CMD_ADD;
+          SUB: ram_b_addr=CMD_SUB;
+          CUBIC: ram_b_addr=CMD_CUBIC;
+          default: ram_b_addr=0;
+          endcase
+       READ_SRC2: ram_b_addr=src2;
+       WRITE: ram_b_addr=dest;
+       default: ram_b_addr=0;
+       endcase
+
+    assign ram_b_w = (state==WRITE) ? 1\'b1 : 1\'b0;
+endmodule
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+`timescale 1ns / 1ps
+`define P 20 // clock period 
+
+module test_tiny;
+
+\t// Inputs
+\treg clk;
+\treg reset;
+\treg sel;
+\treg [5:0] addr;
+\treg w;
+\treg [197:0] data;
+
+\t// Outputs
+\twire [197:0] out;
+\twire done;
+
+\t// Instantiate the Unit Under Test (UUT)
+\ttiny uut (
+\t\t.clk(clk), 
+\t\t.reset(reset), 
+\t\t.sel(sel), 
+\t\t.addr(addr), 
+\t\t.w(w), 
+\t\t.data(data), 
+\t\t.out(out), 
+\t\t.done(done)
+\t);
+
+\tinitial begin
+\t\t// Initialize Inputs
+\t\tclk = 0;
+\t\treset = 0;
+\t\tsel = 0;
+\t\taddr = 0;
+\t\tw = 0;
+\t\tdata = 0;
+
+\t\t// Wait 100 ns for global reset to finish
+\t\t#100;
+        
+\t\t// Add stimulus here
+        reset = 1; // keep FSM silent
+            // init x, y
+            write(3, 194\'h21181940120548aa020568aa65a5989609251595a89a44598);
+            write(5, 194\'h0a905590506a8a845592a09644a2095291422910a968a5048);
+            write(6, 194\'h21181940120548aa020568aa65a5989609251595a89a44598);
+            write(7, 194\'h0a905590506a8a845592a09644a2095291422910a968a5048);
+            /* read back. uncomment me if error happens */
+            /* read(3);
+            $display(""xp = %h"", out);
+            read(5);
+            $display(""yp = %h"", out);
+            read(6);
+            $display(""xq = %h"", out);
+            read(7);
+            $display(""yq = %h"", out);*/
+        reset = 0;
+        sel = 0; w = 0;
+        @(posedge done);
+        @(negedge clk);
+            read(9);
+            check(194\'h09a49266428495042842965645266a2164a1268408a669866);
+            read(10);
+            check(194\'h204446152452400968480544296829199a169a2562a908520);
+            read(11);
+            check(194\'h1699142918666651a156954a80544689590a5094624610281);
+            read(12);
+            check(194\'h2461998924145511611291626a4a295888569280285884661);
+            read(13);
+            check(194\'h1040525045a404150a1881aa91a99156660a1658a090a1091);
+            read(14);
+            check(194\'h2400a94249694808254880924a06494816081900811198925);
+            $display(""Good"");
+        $finish;
+\tend
+
+    initial #100 forever #(`P/2) clk = ~clk;
+
+    task write;
+        input [6:0] adr;
+        input [197:0] dat;
+        begin
+            sel = 1; 
+            w = 1;
+            addr = adr;
+            data = dat;
+            #(`P);
+        end
+    endtask
+
+    task read;
+        input [6:0] adr;
+        begin
+            sel = 1; 
+            w = 0;
+            addr = adr;
+            #(`P);
+        end
+    endtask
+
+    task check;
+        input [197:0] wish;
+        begin
+            if (out !== wish) 
+                begin $display(""Error!""); $finish; end
+        end
+    endtask    
+endmodule
+
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+module pairing(clk, reset, sel, addr, w, update, ready, i, o, done);
+   input clk;
+   input reset; // for the arithmethic core
+   input sel;
+   input [5:0] addr;
+   input w;
+   input update; // update reg_in & reg_out
+   input ready;  // shift reg_in & reg_out
+   input i;
+   output o;
+   output done;
+   
+   reg [197:0] reg_in, reg_out;
+   wire [197:0] out;
+   
+   assign o = reg_out[0];
+   
+   tiny
+      tiny0 (clk, reset, sel, addr, w, reg_in, out, done);
+   
+   always @ (posedge clk) // write LSB firstly
+      if (update) reg_in <= 0;
+      else if (ready) reg_in <= {i,reg_in[197:1]};
+   
+   always @ (posedge clk) // read LSB firstly
+      if (update) reg_out <= out;
+      else if (ready) reg_out <= reg_out>>1;
+endmodule
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+`timescale 1ns / 1ps
+`define P 20 // clock period 
+
+module test_pairing;
+
+\t// Inputs
+\treg clk;
+\treg reset;
+\treg sel;
+\treg [5:0] addr;
+\treg w;
+    reg update;
+    reg ready;
+    reg i;
+
+\t// Outputs
+\twire done;
+    wire o;
+
+    // Buffers
+\treg [197:0] out;
+
+\t// Instantiate the Unit Under Test (UUT)
+\tpairing uut (
+        .clk(clk), 
+        .reset(reset), 
+        .sel(sel), 
+        .addr(addr), 
+        .w(w), 
+        .update(update),
+        .ready(ready),
+        .i(i),
+        .o(o),
+        .done(done)
+\t);
+
+\tinitial begin
+\t\t// Initialize Inputs
+\t\tclk = 0;
+\t\treset = 0;
+\t\tsel = 0;
+\t\taddr = 0;
+\t\tw = 0;
+        update = 0;
+        ready = 0;
+        i = 0;
+        out = 0;
+
+\t\t// Wait 100 ns for global reset to finish
+\t\t#100;
+        
+\t\t// Add stimulus here
+        /* keep FSM silent */
+        reset = 1;
+            /* init xp, yp, xq, yq */
+            write(3, 194\'h21181940120548aa020568aa65a5989609251595a89a44598);
+            write(5, 194\'h0a905590506a8a845592a09644a2095291422910a968a5048);
+            write(6, 194\'h21181940120548aa020568aa65a5989609251595a89a44598);
+            write(7, 194\'h0a905590506a8a845592a09644a2095291422910a968a5048);
+            /* read back. uncomment me if error happens */
+            /* read(3);
+            $display(""xp = %h"", out);
+            read(5);
+            $display(""yp = %h"", out);
+            read(6);
+            $display(""xq = %h"", out);
+            read(7);
+            $display(""yq = %h"", out);*/
+        reset = 0;
+        
+        sel = 0; w = 0;
+        @(posedge done);
+        @(negedge clk);
+            read(9);
+            check(194\'h09a49266428495042842965645266a2164a1268408a669866);
+            read(10);
+            check(194\'h204446152452400968480544296829199a169a2562a908520);
+            read(11);
+            check(194\'h1699142918666651a156954a80544689590a5094624610281);
+            read(12);
+            check(194\'h2461998924145511611291626a4a295888569280285884661);
+            read(13);
+            check(194\'h1040525045a404150a1881aa91a99156660a1658a090a1091);
+            read(14);
+            check(194\'h2400a94249694808254880924a06494816081900811198925);
+            $display(""Good"");
+        $finish;
+\tend
+
+    initial #100 forever #(`P/2) clk = ~clk;
+
+    task write;
+        input [5:0] adr;
+        input [197:0] dat;
+        integer j;
+        begin
+            sel = 1; 
+            w = 0;
+            addr = adr;
+            update = 1;
+            #`P;
+            update = 0;
+            ready = 1;
+            for(j=0;j<198;j=j+1)
+               begin
+               i = dat[j];
+               #`P;
+               end
+            ready = 0;
+            w = 1; #`P; w = 0;
+        end
+    endtask
+
+    task read;
+        input [5:0] adr;
+        integer j;
+        begin
+            sel = 1;
+            w = 0;
+            addr = adr;
+            #`P;
+            update = 1;
+            #`P;
+            update = 0;
+            out = 0;
+            ready = 1;
+            for(j=0;j<198;j=j+1)
+               begin
+               out = {o, out[197:1]};
+               #`P;
+               end
+        end
+    endtask
+    
+    task check;
+        input [197:0] wish;
+        begin
+            if (out !== wish) 
+                begin $display(""Error!""); $finish; end
+        end
+    endtask    
+endmodule
+
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+`define M     503         // M is the degree of the irreducible polynomial
+`define WIDTH (2*`M-1)    // width for a GF(3^M) element
+`define WIDTH_D0 (1008-1)
+
+module ram #(
+    parameter DATA = 1008,
+    parameter ADDR = 6
+) (
+    input                       clk,
+
+    // Port A
+    input   wire                a_wr,
+    input   wire    [ADDR-1:0]  a_addr,
+    input   wire    [DATA-1:0]  a_din,
+    output  reg     [DATA-1:0]  a_dout,
+    
+    // Port B
+    input   wire                b_wr,
+    input   wire    [ADDR-1:0]  b_addr,
+    input   wire    [DATA-1:0]  b_din,
+    output  reg     [DATA-1:0]  b_dout
+);
+
+    // Shared memory
+    reg [DATA-1:0] mem [(2**ADDR)-1:0];
+
+    initial begin : init
+        integer i;
+        for(i = 0; i < (2**ADDR); i = i + 1)
+            mem[i] = 0;
+    end
+
+    // Port A
+    always @(posedge clk) begin
+        a_dout      <= mem[a_addr];
+        if(a_wr) begin
+            a_dout      <= a_din;
+            mem[a_addr] <= a_din;
+        end
+    end
+
+    // Port B
+    always @(posedge clk) begin
+        b_dout      <= mem[b_addr];
+        if(b_wr) begin
+            b_dout      <= b_din;
+            mem[b_addr] <= b_din;
+        end
+    end
+
+endmodule
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+module rom (clk, addr, out);
+   input clk;
+   input [8:0] addr;
+   output reg [25:0] out;
+   
+   always @(posedge clk)
+      case (addr)
+         0: out <= 26\'h30c042;
+         1: out <= 26\'h514045;
+         2: out <= 26\'h61a041;
+         3: out <= 26\'h71e041;
+         4: out <= 26\'hc046;
+         5: out <= 26\'h1603840;
+         6: out <= 26\'h1702041;
+         7: out <= 26\'h1717857;
+         8: out <= 26\'h1817847;
+         9: out <= 26\'h1963847;
+         10: out <= 26\'hf5d059;
+         11: out <= 26\'hf3d045;
+         12: out <= 26\'h1763845;
+         13: out <= 26\'h185f840;
+         14: out <= 26\'h161f856;
+         15: out <= 26\'h1160056;
+         16: out <= 26\'h1144051;
+         17: out <= 26\'h1214045;
+         18: out <= 26\'h131f840;
+         19: out <= 26\'h135d053;
+         20: out <= 26\'h1404041;
+         21: out <= 26\'h151c047;
+         22: out <= 26\'h3e041;
+         23: out <= 26\'h1646041;
+         24: out <= 26\'h174a041;
+         25: out <= 26\'h184e041;
+         26: out <= 26\'h1952041;
+         27: out <= 26\'h1a56041;
+         28: out <= 26\'hf00057;
+         29: out <= 26\'hf3c059;
+         30: out <= 26\'h1158058;
+         31: out <= 26\'h114405a;
+         32: out <= 26\'h1144051;
+         33: out <= 26\'h125d059;
+         34: out <= 26\'h1369058;
+         35: out <= 26\'h1464041;
+         36: out <= 26\'h156805a;
+         37: out <= 26\'h61a081;
+         38: out <= 26\'h619042;
+         39: out <= 26\'h71e081;
+         40: out <= 26\'h71c047;
+         41: out <= 26\'hc046;
+         42: out <= 26\'h1600040;
+         43: out <= 26\'h1717847;
+         44: out <= 26\'h5b840;
+         45: out <= 26\'h1800056;
+         46: out <= 26\'h1901056;
+         47: out <= 26\'h1a3c054;
+         48: out <= 26\'h1b68052;
+         49: out <= 26\'h1c69052;
+         50: out <= 26\'h1d3d054;
+         51: out <= 26\'h1e75053;
+         52: out <= 26\'h1d74053;
+         53: out <= 26\'h1f44055;
+         54: out <= 26\'h207c053;
+         55: out <= 26\'h217d053;
+         56: out <= 26\'h225c056;
+         57: out <= 26\'h165d056;
+         58: out <= 26\'h2345055;
+         59: out <= 26\'h248c052;
+         60: out <= 26\'h238d052;
+         61: out <= 26\'h2560057;
+         62: out <= 26\'h266c060;
+         63: out <= 26\'h2700062;
+         64: out <= 26\'h2878064;
+         65: out <= 26\'h2964057;
+         66: out <= 26\'h2a70061;
+         67: out <= 26\'h2b00056;
+         68: out <= 26\'h2c74063;
+         69: out <= 26\'h186385b;
+         70: out <= 26\'h1b97866;
+         71: out <= 26\'h205f860;
+         72: out <= 26\'h1e0385e;
+         73: out <= 26\'h259f868;
+         74: out <= 26\'h228b864;
+         75: out <= 26\'h196785c;
+         76: out <= 26\'h1ca786a;
+         77: out <= 26\'h175f861;
+         78: out <= 26\'h385d;
+         79: out <= 26\'h1daf86c;
+         80: out <= 26\'h165b863;
+         81: out <= 26\'h2160065;
+         82: out <= 26\'h238005d;
+         83: out <= 26\'h2481057;
+         84: out <= 26\'h2665058;
+         85: out <= 26\'h175c060;
+         86: out <= 26\'h1789057;
+         87: out <= 26\'h175c056;
+         88: out <= 26\'h1864058;
+         89: out <= 26\'h186105e;
+         90: out <= 26\'h1861040;
+         91: out <= 26\'h198d061;
+         92: out <= 26\'h196505e;
+         93: out <= 26\'h1664056;
+         94: out <= 26\'h1984063;
+         95: out <= 26\'h196505b;
+         96: out <= 26\'h1964062;
+         97: out <= 26\'h64040;
+         98: out <= 26\'h1990066;
+         99: out <= 26\'h1e91066;
+         100: out <= 26\'h1e7805c;
+         101: out <= 26\'h1e7905b;
+         102: out <= 26\'h205c058;
+         103: out <= 26\'h175d058;
+         104: out <= 26\'h175c05c;
+         105: out <= 26\'h175c05b;
+         106: out <= 26\'h175d065;
+         107: out <= 26\'h175d05d;
+         108: out <= 26\'hf59052;
+         109: out <= 26\'h1101053;
+         110: out <= 26\'h65052;
+         111: out <= 26\'h1054;
+         112: out <= 26\'h1679053;
+         113: out <= 26\'h1659055;
+         114: out <= 26\'h148105a;
+         115: out <= 26\'h155d05f;
+         116: out <= 26\'h1201041;
+         117: out <= 26\'h1359041;
+         118: out <= 26\'h93e041;
+         119: out <= 26\'h3c052;
+         120: out <= 26\'h54;
+         121: out <= 26\'h163f84f;
+         122: out <= 26\'h173f852;
+         123: out <= 26\'h184b854;
+         124: out <= 26\'h1953854;
+         125: out <= 26\'h3840;
+         126: out <= 26\'h175c058;
+         127: out <= 26\'h1859058;
+         128: out <= 26\'h1965057;
+         129: out <= 26\'h57;
+         130: out <= 26\'h1056;
+         131: out <= 26\'h1644053;
+         132: out <= 26\'h1658055;
+         133: out <= 26\'h1747851;
+         134: out <= 26\'h1a47853;
+         135: out <= 26\'h1b4f855;
+         136: out <= 26\'h1c57855;
+         137: out <= 26\'h165b856;
+         138: out <= 26\'h1a6805b;
+         139: out <= 26\'h1b5d05b;
+         140: out <= 26\'h1c7105a;
+         141: out <= 26\'h165805a;
+         142: out <= 26\'h1659057;
+         143: out <= 26\'h173c052;
+         144: out <= 26\'h1a3c054;
+         145: out <= 26\'h1d48054;
+         146: out <= 26\'h1e44053;
+         147: out <= 26\'h1f44055;
+         148: out <= 26\'h204c055;
+         149: out <= 26\'h213f851;
+         150: out <= 26\'h224b853;
+         151: out <= 26\'h2353855;
+         152: out <= 26\'h175f85e;
+         153: out <= 26\'h1a6b85f;
+         154: out <= 26\'h1d77860;
+         155: out <= 26\'h1e85062;
+         156: out <= 26\'h1f79063;
+         157: out <= 26\'h1f7c05d;
+         158: out <= 26\'h175d05e;
+         159: out <= 26\'h175c05d;
+         160: out <= 26\'h1a6905e;
+         161: out <= 26\'h1d6105b;
+         162: out <= 26\'h1e6505c;
+         163: out <= 26\'h2001056;
+         164: out <= 26\'h186005b;
+         165: out <= 26\'h196405c;
+         166: out <= 26\'h56;
+         167: out <= 26\'h1660059;
+         168: out <= 26\'h1b61040;
+         169: out <= 26\'h1c65058;
+         170: out <= 26\'h210105c;
+         171: out <= 26\'h2263858;
+         172: out <= 26\'h2367859;
+         173: out <= 26\'h2403840;
+         174: out <= 26\'h1963859;
+         175: out <= 26\'h1863840;
+         176: out <= 26\'h3856;
+         177: out <= 26\'h168b85b;
+         178: out <= 26\'h1b8f85c;
+         179: out <= 26\'h1c93861;
+         180: out <= 26\'h165805b;
+         181: out <= 26\'h165805c;
+         182: out <= 26\'h1b58041;
+         183: out <= 26\'h1c6e041;
+         184: out <= 26\'h1b6f85c;
+         185: out <= 26\'h1c6e081;
+         186: out <= 26\'h1b6f85c;
+         187: out <= 26\'h1c6e101;
+         188: out <= 26\'h1b6f85c;
+         189: out <= 26\'h1c6e201;
+         190: out <= 26\'h1b6f85c;
+         191: out <= 26\'h1c6e401;
+         192: out <= 26\'h1b6f85c;
+         193: out <= 26\'h1c6e801;
+         194: out <= 26\'h1c6f85c;
+         195: out <= 26\'h1c72801;
+         196: out <= 26\'h1b6f85c;
+         197: out <= 26\'h1b6e041;
+         198: out <= 26\'h166f856;
+         199: out <= 26\'h166f856;
+         200: out <= 26\'h1b8d064;
+         201: out <= 26\'h1c8905b;
+         202: out <= 26\'h71040;
+         203: out <= 26\'h1991059;
+         204: out <= 26\'h186d058;
+         205: out <= 26\'h5b840;
+         206: out <= 26\'h195b859;
+         207: out <= 26\'h165b858;
+         208: out <= 26\'h187405e;
+         209: out <= 26\'h1b74060;
+         210: out <= 26\'h1c78060;
+         211: out <= 26\'h2100059;
+         212: out <= 26\'h2200056;
+         213: out <= 26\'h2364056;
+         214: out <= 26\'h1d77840;
+         215: out <= 26\'h1e7b859;
+         216: out <= 26\'h2083856;
+         217: out <= 26\'h1863861;
+         218: out <= 26\'h1b6f862;
+         219: out <= 26\'h1c73863;
+         220: out <= 26\'h1d7505e;
+         221: out <= 26\'h1e75060;
+         222: out <= 26\'h1e7805c;
+         223: out <= 26\'h186105d;
+         224: out <= 26\'h186005c;
+         225: out <= 26\'h1b6d05d;
+         226: out <= 26\'h1c7c057;
+         227: out <= 26\'h1d7c05a;
+         228: out <= 26\'h205c05a;
+         229: out <= 26\'h2100059;
+         230: out <= 26\'h2200056;
+         231: out <= 26\'h2364056;
+         232: out <= 26\'h7f840;
+         233: out <= 26\'h175f859;
+         234: out <= 26\'h166b856;
+         235: out <= 26\'h1973861;
+         236: out <= 26\'h1a77862;
+         237: out <= 26\'h1c83863;
+         238: out <= 26\'h1057;
+         239: out <= 26\'h1601056;
+         240: out <= 26\'h165805c;
+         241: out <= 26\'h1765040;
+         242: out <= 26\'h175c05c;
+         243: out <= 26\'h69040;
+         244: out <= 26\'h1978056;
+         245: out <= 26\'h1a60057;
+         246: out <= 26\'h1c6d040;
+         247: out <= 26\'h1d7b85b;
+         248: out <= 26\'h1f5b840;
+         249: out <= 26\'h1b6385b;
+         250: out <= 26\'h5f840;
+         251: out <= 26\'h206785c;
+         252: out <= 26\'h165b858;
+         253: out <= 26\'h177b857;
+         254: out <= 26\'h186785a;
+         255: out <= 26\'h196b85c;
+         256: out <= 26\'h1a58057;
+         257: out <= 26\'h1869058;
+         258: out <= 26\'h1a6c040;
+         259: out <= 26\'h1a6805a;
+         260: out <= 26\'h105b;
+         261: out <= 26\'h1b7d05d;
+         262: out <= 26\'h1b6c060;
+         263: out <= 26\'h1c0805d;
+         264: out <= 26\'h1c7005f;
+         265: out <= 26\'h1c7005a;
+         266: out <= 26\'h1659057;
+         267: out <= 26\'h165805b;
+         268: out <= 26\'h1769058;
+         269: out <= 26\'h1d64040;
+         270: out <= 26\'h1b7505b;
+         271: out <= 26\'h1860058;
+         272: out <= 26\'h186105a;
+         273: out <= 26\'h64040;
+         274: out <= 26\'h1972041;
+         275: out <= 26\'h1a5a041;
+         276: out <= 26\'h1d5e041;
+         277: out <= 26\'h1e6e041;
+         278: out <= 26\'h1f62041;
+         279: out <= 26\'h2002041;
+         280: out <= 26\'h196405d;
+         281: out <= 26\'h196405f;
+         282: out <= 26\'h1a6805a;
+         283: out <= 26\'h1a6905e;
+         284: out <= 26\'h1a69060;
+         285: out <= 26\'h1d7505f;
+         286: out <= 26\'h1e8105e;
+         287: out <= 26\'h2080060;
+         288: out <= 26\'h1966041;
+         289: out <= 26\'h1a6a041;
+         290: out <= 26\'h1d76041;
+         291: out <= 26\'h1e7a041;
+         292: out <= 26\'h1f7e041;
+         293: out <= 26\'h2082041;
+         294: out <= 26\'h196405d;
+         295: out <= 26\'h196405f;
+         296: out <= 26\'h1a6805a;
+         297: out <= 26\'h1a6905e;
+         298: out <= 26\'h1a69060;
+         299: out <= 26\'h1d7505f;
+         300: out <= 26\'h1e8105e;
+         301: out <= 26\'h2080060;
+         302: out <= 26\'h2170056;
+         303: out <= 26\'h225c05b;
+         304: out <= 26\'h2361040;
+         305: out <= 26\'h2473858;
+         306: out <= 26\'h255b840;
+         307: out <= 26\'h185f858;
+         308: out <= 26\'h6f840;
+         309: out <= 26\'h2687863;
+         310: out <= 26\'h165b857;
+         311: out <= 26\'h177385b;
+         312: out <= 26\'h1b87862;
+         313: out <= 26\'h1c8b863;
+         314: out <= 26\'h2158057;
+         315: out <= 26\'h1b8505b;
+         316: out <= 26\'h2160040;
+         317: out <= 26\'h2184061;
+         318: out <= 26\'h1058;
+         319: out <= 26\'h1895064;
+         320: out <= 26\'h1860066;
+         321: out <= 26\'h2208064;
+         322: out <= 26\'h2288065;
+         323: out <= 26\'h2288061;
+         324: out <= 26\'h1659057;
+         325: out <= 26\'h1658058;
+         326: out <= 26\'h178505b;
+         327: out <= 26\'h2370040;
+         328: out <= 26\'h188d058;
+         329: out <= 26\'h1b6c05b;
+         330: out <= 26\'h1b6d061;
+         331: out <= 26\'h70040;
+         332: out <= 26\'h1a6805a;
+         333: out <= 26\'h1c7805e;
+         334: out <= 26\'h1e80060;
+         335: out <= 26\'h206405f;
+         336: out <= 26\'h218005d;
+         337: out <= 26\'h208105d;
+         338: out <= 26\'h238805b;
+         339: out <= 26\'h248c057;
+         340: out <= 26\'h238d057;
+         341: out <= 26\'h196505f;
+         342: out <= 26\'h256505c;
+         343: out <= 26\'h196405c;
+         344: out <= 26\'h228905b;
+         345: out <= 26\'h2689058;
+         346: out <= 26\'h2288058;
+         347: out <= 26\'h276805e;
+         348: out <= 26\'h289c05c;
+         349: out <= 26\'h1c9d05c;
+         350: out <= 26\'h2758040;
+         351: out <= 26\'h299c058;
+         352: out <= 26\'h189d058;
+         353: out <= 26\'h1a6905e;
+         354: out <= 26\'h276805d;
+         355: out <= 26\'h1a6905d;
+         356: out <= 26\'h1659040;
+         357: out <= 26\'h1d58057;
+         358: out <= 26\'h1659057;
+         359: out <= 26\'h1784068;
+         360: out <= 26\'h2a90069;
+         361: out <= 26\'h2b94067;
+         362: out <= 26\'h2c9805d;
+         363: out <= 26\'h2d8005c;
+         364: out <= 26\'h2e8c058;
+         365: out <= 26\'h2f6405a;
+         366: out <= 26\'h3088056;
+         367: out <= 26\'h317c05e;
+         368: out <= 26\'h326c040;
+         369: out <= 26\'h2187864;
+         370: out <= 26\'h175f86a;
+         371: out <= 26\'h24a3869;
+         372: out <= 26\'h2597866;
+         373: out <= 26\'h26af86c;
+         374: out <= 26\'h1d9f85d;
+         375: out <= 26\'h2083863;
+         376: out <= 26\'h23b786e;
+         377: out <= 26\'h1873858;
+         378: out <= 26\'h1967862;
+         379: out <= 26\'h1cbf870;
+         380: out <= 26\'h166b856;
+         381: out <= 26\'h1a7f85b;
+         382: out <= 26\'h1bc7872;
+         383: out <= 26\'h7b840;
+         384: out <= 26\'h1e84066;
+         385: out <= 26\'h1e7805a;
+         386: out <= 26\'h1f9005c;
+         387: out <= 26\'h1f7c040;
+         388: out <= 26\'h1a8005a;
+         389: out <= 26\'h60040;
+         390: out <= 26\'h40;
+         391: out <= 26\'h188c05b;
+         392: out <= 26\'h2000064;
+         393: out <= 26\'h2269061;
+         394: out <= 26\'h1064;
+         395: out <= 26\'h5d;
+         396: out <= 26\'h56;
+         397: out <= 26\'h1a68061;
+         398: out <= 26\'h1a69065;
+         399: out <= 26\'h1a69059;
+         400: out <= 26\'h97d05e;
+         401: out <= 26\'h925065;
+         402: out <= 26\'h924056;
+         403: out <= 26\'ha7805f;
+         404: out <= 26\'ha29057;
+         405: out <= 26\'ha2805d;
+         406: out <= 26\'ha28059;
+         407: out <= 26\'ha2905b;
+         408: out <= 26\'hb80062;
+         409: out <= 26\'hc81062;
+         410: out <= 26\'hc30058;
+         411: out <= 26\'hc31057;
+         412: out <= 26\'hd0005a;
+         413: out <= 26\'he0105a;
+         414: out <= 26\'he38058;
+         415: out <= 26\'he38057;
+         416: out <= 26\'he39066;
+         417: out <= 26\'he3905c;
+         default: out <= 0;
+      endcase
+endmodule
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+`timescale 1ns / 1ps
+`define P 20
+
+`define M     593         // M is the degree of the irreducible polynomial
+`define WIDTH (2*`M-1)    // width for a GF(3^M) element
+`define WIDTH_D0 1187
+
+module test_pe;
+
+\t// Inputs
+\treg clk;
+\treg reset;
+\treg [10:0] ctrl;
+\treg [`WIDTH_D0:0] d0;
+\treg [`WIDTH:0] d1;
+\treg [`WIDTH:0] d2;
+    reg [`WIDTH:0] wish;
+
+\t// Outputs
+\twire [`WIDTH:0] out;
+
+\t// Instantiate the Unit Under Test (UUT)
+\tPE uut (
+\t\t.clk(clk), 
+\t\t.reset(reset), 
+\t\t.ctrl(ctrl), 
+\t\t.d0(d0), 
+\t\t.d1(d1), 
+        .d2(d2),
+\t\t.out(out)
+\t);
+
+\tinitial begin
+\t\t// Initialize Inputs
+\t\tclk = 0;
+\t\treset = 0;
+\t\tctrl = 0;
+\t\td0 = 0;
+\t\td1 = 0;
+        d2 = 0;
+
+\t\t// Wait 100 ns for global reset to finish
+\t\t#100;
+        
+\t\t// Add stimulus here
+        // test mult
+        d0 = 1186\'h245958540550916859984664a9559916599551944415826a8429555562950a5555a9661855015655694448585615852515916545158595955690a96a566591598660556a61880a410615585525454612010662a4a9116906410014611105015955161455804415166155815941116592650115564164556112804292528419450a45840158a926588250411118055565654556964;
+        d1 = 1186\'h212291922556595445146a555159a2414515699455212899424869242411a459a6a96954461552562556a11694912451a058440646451050819559181a546891566865542169546869551654262068564119555949915194580525869959a159444051555a01a11509919294620158600555158520569556a514684225201a255a586294585262195922250514115a05542946299;
+        d2 = d1;
+        wish = 1186\'h21a0004a5961412a2068488080020408114aa1aa6296a615418a9a22220948905a4a119849a541100016a14141625a21a906a05024001559086584205a1241804215518688468146052485a40581824a1146915164288a904150960222022aa49555608086151504905a68065906122568a2188a22aa09004451464946201a689926105411588591198551a1085145a6846196910;
+        
+        @(negedge clk);
+        reset=1;#`P reset=0;
+        ctrl=11\'b11111_000000; #`P;
+        ctrl=11\'b00000_111111; #(198*`P);
+        check;
+        
+        // test cubic
+        d0 = {6\'b10101, 1182\'d0};
+        d1 = 1186\'h198565655595622106a15596a98a5186101959554541466581244585515555665552584505511552650944484555052655692189595619806549462551a56051552069242a6555542014551599866559955466a604511499554654119144668125851211419566a645856592a55865458582952556a916189591194655519664218a5a9a64990415a516a5169865415a912605951;
+        d2 = d1;
+        wish = 1186\'h01a1425a929600890401891a44129844120112246215a566842954a605aaa8aa08588091659481a062a8519a868aa1548569a18a642222490a80aa8026a22501a8492a10555158491155025a84686680984852046a88a1008249008541a550556181952208252029264a0a4151045415450886854129a9658608684901089910281a22a46262a18108451120145a2625904921a96;
+        
+        @(negedge clk);
+        reset=1;#`P reset=0;
+        ctrl=11\'b11111_000000; #`P;
+        ctrl=1; #(`P);
+        check;
+        
+        // test add
+        d0 = {6\'b000101, 1182\'d0};
+        d1 = 1186\'h00a6540512a166a914956a65149495511551891946505601545514458a955815a5596918a2195a565906902549a4954419294a5045199954951561555804612a6655256899454941a51a590259466611545a628496596845046015584a4455a5aa69858911112a9666549561252a156559564966195415951a41226620598145a0441915951185246145aa55615556585564965a5;
+        d2 = 1186\'h219146612691209655566446a585291504580155555689915a555564404562896415518a65915062459564695665590a11465845a6659441a515a50a656a0a809016195545425645a509895161841616a665599585a0115416a8952185954555564146a56025559466a85a098a68584564969965441822018992901511a954664a90555414555114149641a811854525452a65612;
+        wish = 1186\'h21449a6605425640692892a88959826619a98a6298a61092a2aa69a90a1a8a9219628a9614aaaa8592980452901922422a609695284261954a2a1650816268aa06680281128490865a1416508a0a49240a808859580949991a18aa4900199a0a01aa08624106406a9900206aa05661aa812916985160049694108248010615a82a146269a966160845182801421a98419a5208884;
+        
+        @(negedge clk);
+        reset=1;#`P reset=0;
+        ctrl=11\'b11111_000000; #`P;
+        ctrl=11\'b10001; #(`P);
+        check;
+
+        // test sub
+        d0 = {6\'b001001, 1182\'d0};
+        d1 = 1186\'h00a6540512a166a914956a65149495511551891946505601545514458a955815a5596918a2195a565906902549a4954419294a5045199954951561555804612a6655256899454941a51a590259466611545a628496596845046015584a4455a5aa69858911112a9666549561252a156559564966195415951a41226620598145a0441915951185246145aa55615556585564965a5;
+        d2 = 1186\'h219146612691209655566446a585291504580155555689915a555564404562896415518a65915062459564695665590a11465845a6659441a515a50a656a0a809016195545425645a509895161841616a665599585a0115416a8952185954555564146a56025559466a85a098a68584564969965441822018992901511a954664a90555414555114149641a811854525452a65612;
+        wish = 1186\'h1215119428104616824206226212a8481105888421099960090082114a5029584144185149480a24146168882642484908a6221a92a405162000885a2699666a9642181654062608001190a12882500aa125152211a95a212184406a85a2105054284214a128950200a84a646a8289202580a0019548269451a2525112a0691265a484818188641059a269a950901166104961296;
+        
+        @(negedge clk);
+        reset=1;#`P reset=0;
+        ctrl=11\'b11111_000000; #`P;
+        ctrl=11\'b10001; #(`P);
+        check;
+
+        $display(""Good!"");
+        $finish;
+\tend
+
+    initial #100 forever #(`P/2) clk = ~clk;
+
+    task check;
+        begin
+          if (out !== wish)
+            begin $display(""E %h %h"", out, wish); $finish; end
+        end
+    endtask
+endmodule
+
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+`timescale 1ns / 1ps
+
+`define P 20 // clock period
+
+module test_ram;
+
+\t// Inputs
+\treg clk;
+\treg reset;
+\treg sel;
+\treg [5:0] addr;
+\treg w;
+\treg [197:0] data;
+
+\t// Outputs
+\twire [197:0] out;
+\twire done;
+
+\t// Instantiate the Unit Under Test (UUT)
+\ttiny uut (
+\t\t.clk(clk), 
+\t\t.reset(reset), 
+\t\t.sel(sel), 
+\t\t.addr(addr), 
+\t\t.w(w), 
+\t\t.data(data), 
+\t\t.out(out), 
+\t\t.done(done)
+\t);
+
+\tinitial begin
+\t\t// Initialize Inputs
+\t\tclk = 0;
+\t\treset = 0;
+\t\tsel = 0;
+\t\taddr = 0;
+\t\tw = 0;
+\t\tdata = 0;
+
+\t\t// Wait 100 ns for global reset to finish
+\t\t#100;
+        
+\t\t// Add stimulus here
+        @ (negedge clk);
+        
+        // write
+        sel = 1; w = 1;
+        data = 198\'h115a25886512165251569195908560596a6695612620504191;
+        addr = 0;
+        #(`P);
+        data = 198\'h1559546442405a181195655549614540592955a15a26984015;
+        addr = 3;
+        #(`P);
+        // not write
+        w = 0;
+        data = 198\'h12222222222222222222222222222222222222222222222222;
+        addr = 3;
+        #(`P);
+        
+        // read
+        sel = 1; w = 0;
+        addr = 0;
+        #(`P);
+        if (out !== 198\'h115a25886512165251569195908560596a6695612620504191)
+            $display(""E"");
+
+        addr = 3;
+        #(`P);
+        if (out !== 198\'h1559546442405a181195655549614540592955a15a26984015)
+            $display(""E"");
+
+        #(`P);
+        
+        $display(""Good"");
+        $finish;
+\tend
+    
+    initial #100 forever #(`P/2) clk = ~clk;
+endmodule
+
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+`define M     503         // M is the degree of the irreducible polynomial
+`define WIDTH (2*`M-1)    // width for a GF(3^M) element
+`define WIDTH_D0 (1008-1)
+
+/* PE: processing element */
+module PE(clk, reset, ctrl, d0, d1, d2, out);
+    input clk;
+    input reset;
+    input [10:0] ctrl;
+    input [`WIDTH_D0:0] d0;
+    input [`WIDTH:0] d1, d2;
+    output [`WIDTH:0] out;
+    
+    reg [`WIDTH_D0:0] R0;
+    reg [`WIDTH:0] R1, R2, R3;
+    wire [1:0] e0, e1, e2; /* part of R0 */
+    wire [`WIDTH:0] ppg0, ppg1, ppg2, /* output of PPG */
+                    mx0, mx1, mx2, mx3, mx4, mx5, mx6, mx7, /* output of MUX */
+                    ad0, ad1, ad2, /* output of GF(3^m) adder */
+                    cu0, cu1, cu2, cu3, /* output of cubic */
+                    mo0, mo1, mo2, /* output of mod_p */
+                    t0, t1, t2;
+    wire c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10;
+    
+    assign {c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10} = ctrl;
+    assign mx0 = c0 ? d1 : ad2;
+    assign mx1 = c2 ? d2 : ad2;                                                  
+    always @ (posedge clk)
+        if(reset) R1 <= 0;
+        else if (c1) R1 <= mx0;
+    always @ (posedge clk)
+        if(reset) R2 <= 0;
+        else if (c3) R2 <= mx1;
+    always @ (posedge clk)
+        if(reset) R0 <= 0;
+        else if (c4) R0 <= d0;
+        else if (c5) R0 <= R0 << 6;
+    assign {e2,e1,e0} = R0[`WIDTH_D0:(`WIDTH_D0-5)];
+    PPG
+        ppg_0 (e0, R1, ppg0),
+        ppg_1 (e1, R2, ppg1),
+        ppg_2 (e2, R1, ppg2);
+    v0  v0_ (ppg0, cu0);
+    v1  v1_ (ppg1, cu1);
+    v2  v2_ (ppg2, cu2);
+    v3  v3_ (R2,   cu3);
+    assign mx2 = c6 ? ppg0 : cu0;
+    assign mx3 = c6 ? ppg1 : cu1;
+    assign mx4 = c6 ? mo1 : cu2;
+    assign mx5 = c7 ? mo2 : R3;
+    mod_p
+        mod_p_0 (mx3, mo0),
+        mod_p_1 (ppg2, t0),
+        mod_p_2 (t0, mo1),
+        mod_p_3 (R3, t1),
+        mod_p_4 (t1, t2),
+        mod_p_5 (t2, mo2);
+    assign mx6 = c9 ? mo0 : mx3;
+    assign mx7 = c6 ? (c8 ? mx5 : 0) : cu3;
+    f3m_add
+        f3m_add_0 (mx2, mx6, ad0),
+        f3m_add_1 (mx4, mx7, ad1),
+        f3m_add_2 (ad0, ad1, ad2);
+    always @ (posedge clk)
+        if (reset) R3 <= 0;
+        else if (c10) R3 <= ad2;
+        else R3 <= 0; /* change */
+    assign out = R3;
+endmodule
+
+// C = (x*B mod p(x))
+module mod_p(B, C);
+    input [`WIDTH:0] B;
+    output [`WIDTH:0] C;
+    wire [`WIDTH+2:0] A;
+    assign A = {B[`WIDTH:0], 2\'d0}; // A == B*x
+    wire [1:0] w0;
+    f3_mult m0 (A[1007:1006], 2\'d2, w0);
+    f3_sub s0 (A[1:0], w0, C[1:0]);
+    assign C[207:2] = A[207:2];
+    wire [1:0] w104;
+    f3_mult m104 (A[1007:1006], 2\'d1, w104);
+    f3_sub s104 (A[209:208], w104, C[209:208]);
+    assign C[1005:210] = A[1005:210];
+endmodule
+
+// PPG: partial product generator, C == A*d in GF(3^m)
+module PPG(d, A, C);
+    input [1:0] d;
+    input [`WIDTH:0] A;
+    output [`WIDTH:0] C;
+    genvar i;
+    generate
+        for (i=0; i < `M; i=i+1) 
+        begin: ppg0
+            f3_mult f3_mult_0 (d, A[2*i+1:2*i], C[2*i+1:2*i]);
+        end
+    endgenerate
+endmodule
+
+// f3m_add: C = A + B, in field F_{3^M}
+module f3m_add(A, B, C);
+    input [`WIDTH : 0] A, B;
+    output [`WIDTH : 0] C;
+    genvar i;
+    generate
+        for(i=0; i<`M; i=i+1) begin: aa
+            f3_add aa(A[(2*i+1) : 2*i], B[(2*i+1) : 2*i], C[(2*i+1) : 2*i]);
+        end
+    endgenerate
+endmodule
+
+// f3_add: C == A+B (mod 3)
+module f3_add(A, B, C);
+    input [1:0] A, B;
+    output [1:0] C;
+    wire a0, a1, b0, b1, c0, c1;
+    assign {a1, a0} = A;
+    assign {b1, b0} = B;
+    assign C = {c1, c0};
+    assign c0 = ( a0 & ~a1 & ~b0 & ~b1) |
+                (~a0 & ~a1 &  b0 & ~b1) |
+                (~a0 &  a1 & ~b0 &  b1) ;
+    assign c1 = (~a0 &  a1 & ~b0 & ~b1) |
+                ( a0 & ~a1 &  b0 & ~b1) |
+                (~a0 & ~a1 & ~b0 &  b1) ;
+endmodule
+
+// f3_sub: C == A-B (mod 3)
+module f3_sub(A, B, C);
+    input [1:0] A, B;
+    output [1:0] C;
+    f3_add a0(A, {B[0],B[1]}, C);
+endmodule
+
+// f3_mult: C = A*B (mod 3)
+module f3_mult(A, B, C); 
+    input [1:0] A;
+    input [1:0] B; 
+    output [1:0] C;
+    wire a0, a1, b0, b1;
+    assign {a1, a0} = A;
+    assign {b1, b0} = B;
+    assign C[0] = (~a1 & a0 & ~b1 & b0) | (a1 & ~a0 & b1 & ~b0);
+    assign C[1] = (~a1 & a0 & b1 & ~b0) | (a1 & ~a0 & ~b1 & b0);
+endmodule
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+`define M     593         // M is the degree of the irreducible polynomial
+`define WIDTH (2*`M-1)    // width for a GF(3^M) element
+`define WIDTH_D0 1187
+
+module ram #(
+    parameter DATA = 1188,
+    parameter ADDR = 6
+) (
+    input                       clk,
+
+    // Port A
+    input   wire                a_wr,
+    input   wire    [ADDR-1:0]  a_addr,
+    input   wire    [DATA-1:0]  a_din,
+    output  reg     [DATA-1:0]  a_dout,
+    
+    // Port B
+    input   wire                b_wr,
+    input   wire    [ADDR-1:0]  b_addr,
+    input   wire    [DATA-1:0]  b_din,
+    output  reg     [DATA-1:0]  b_dout
+);
+
+    // Shared memory
+    reg [DATA-1:0] mem [(2**ADDR)-1:0];
+
+    initial begin : init
+        integer i;
+        for(i = 0; i < (2**ADDR); i = i + 1)
+            mem[i] = 0;
+    end
+
+    // Port A
+    always @(posedge clk) begin
+        a_dout      <= mem[a_addr];
+        if(a_wr) begin
+            a_dout      <= a_din;
+            mem[a_addr] <= a_din;
+        end
+    end
+
+    // Port B
+    always @(posedge clk) begin
+        b_dout      <= mem[b_addr];
+        if(b_wr) begin
+            b_dout      <= b_din;
+            mem[b_addr] <= b_din;
+        end
+    end
+
+endmodule
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* v0(a)+v1(a)+v2(a) == a^3 in GF(3^m) */
+
+/* c == v0(a) */
+module v0(a, c);
+    input [1185:0] a;
+    output [1185:0] c;
+    assign c[1:0] = a[1:0];
+    assign c[3:2] = a[1113:1112];
+    assign c[5:4] = a[793:792];
+    assign c[7:6] = a[3:2];
+    assign c[9:8] = a[1115:1114];
+    assign c[11:10] = a[1041:1040];
+    assign c[13:12] = {a[720], a[721]};
+    assign c[15:14] = a[401:400];
+    assign c[17:16] = a[1043:1042];
+    assign c[19:18] = {a[722], a[723]};
+    assign c[21:20] = a[403:402];
+    assign c[23:22] = a[1045:1044];
+    assign c[25:24] = {a[724], a[725]};
+    assign c[27:26] = a[1121:1120];
+    assign c[29:28] = a[801:800];
+    assign c[31:30] = {a[726], a[727]};
+    assign c[33:32] = a[1123:1122];
+    assign c[35:34] = a[803:802];
+    assign c[37:36] = {a[728], a[729]};
+    assign c[39:38] = a[1125:1124];
+    assign c[41:40] = a[805:804];
+    assign c[43:42] = {a[730], a[731]};
+    assign c[45:44] = a[1127:1126];
+    assign c[47:46] = a[807:806];
+    assign c[49:48] = a[17:16];
+    assign c[51:50] = a[1129:1128];
+    assign c[53:52] = a[809:808];
+    assign c[55:54] = a[19:18];
+    assign c[57:56] = a[1131:1130];
+    assign c[59:58] = a[1057:1056];
+    assign c[61:60] = {a[736], a[737]};
+    assign c[63:62] = a[417:416];
+    assign c[65:64] = a[1059:1058];
+    assign c[67:66] = {a[738], a[739]};
+    assign c[69:68] = a[419:418];
+    assign c[71:70] = a[1061:1060];
+    assign c[73:72] = {a[740], a[741]};
+    assign c[75:74] = a[1137:1136];
+    assign c[77:76] = a[817:816];
+    assign c[79:78] = {a[742], a[743]};
+    assign c[81:80] = a[1139:1138];
+    assign c[83:82] = a[819:818];
+    assign c[85:84] = {a[744], a[745]};
+    assign c[87:86] = a[1141:1140];
+    assign c[89:88] = a[821:820];
+    assign c[91:90] = {a[746], a[747]};
+    assign c[93:92] = a[1143:1142];
+    assign c[95:94] = a[823:822];
+    assign c[97:96] = a[33:32];
+    assign c[99:98] = a[1145:1144];
+    assign c[101:100] = a[825:824];
+    assign c[103:102] = a[35:34];
+    assign c[105:104] = a[1147:1146];
+    assign c[107:106] = a[1073:1072];
+    assign c[109:108] = {a[752], a[753]};
+    assign c[111:110] = a[433:432];
+    assign c[113:112] = a[1075:1074];
+    assign c[115:114] = {a[754], a[755]};
+    assign c[117:116] = a[435:434];
+    assign c[119:118] = a[1077:1076];
+    assign c[121:120] = {a[756], a[757]};
+    assign c[123:122] = a[1153:1152];
+    assign c[125:124] = a[833:832];
+    assign c[127:126] = {a[758], a[759]};
+    assign c[129:128] = a[1155:1154];
+    assign c[131:130] = a[835:834];
+    assign c[133:132] = {a[760], a[761]};
+    assign c[135:134] = a[1157:1156];
+    assign c[137:136] = a[837:836];
+    assign c[139:138] = {a[762], a[763]};
+    assign c[141:140] = a[1159:1158];
+    assign c[143:142] = a[839:838];
+    assign c[145:144] = a[49:48];
+    assign c[147:146] = a[1161:1160];
+    assign c[149:148] = a[841:840];
+    assign c[151:150] = a[51:50];
+    assign c[153:152] = a[1163:1162];
+    assign c[155:154] = a[1089:1088];
+    assign c[157:156] = {a[768], a[769]};
+    assign c[159:158] = a[449:448];
+    assign c[161:160] = a[1091:1090];
+    assign c[163:162] = {a[770], a[771]};
+    assign c[165:164] = a[451:450];
+    assign c[167:166] = a[1093:1092];
+    assign c[169:168] = {a[772], a[773]};
+    assign c[171:170] = a[1169:1168];
+    assign c[173:172] = a[849:848];
+    assign c[175:174] = {a[774], a[775]};
+    assign c[177:176] = a[1171:1170];
+    assign c[179:178] = a[851:850];
+    assign c[181:180] = {a[776], a[777]};
+    assign c[183:182] = a[1173:1172];
+    assign c[185:184] = a[853:852];
+    assign c[187:186] = {a[778], a[779]};
+    assign c[189:188] = a[1175:1174];
+    assign c[191:190] = a[855:854];
+    assign c[193:192] = a[65:64];
+    assign c[195:194] = a[1177:1176];
+    assign c[197:196] = a[857:856];
+    assign c[199:198] = a[67:66];
+    assign c[201:200] = a[1179:1178];
+    assign c[203:202] = a[1105:1104];
+    assign c[205:204] = {a[784], a[785]};
+    assign c[207:206] = a[465:464];
+    assign c[209:208] = a[1107:1106];
+    assign c[211:210] = {a[786], a[787]};
+    assign c[213:212] = a[467:466];
+    assign c[215:214] = a[1109:1108];
+    assign c[217:216] = {a[788], a[789]};
+    assign c[219:218] = a[1185:1184];
+    assign c[221:220] = a[865:864];
+    assign c[223:222] = {a[790], a[791]};
+    assign c[225:224] = a[471:470];
+    assign c[227:226] = a[867:866];
+    assign c[229:228] = a[793:792];
+    assign c[231:230] = a[473:472];
+    assign c[233:232] = a[869:868];
+    assign c[235:234] = {a[1040], a[1041]};
+    assign c[237:236] = a[721:720];
+    assign c[239:238] = {a[400], a[401]};
+    assign c[241:240] = a[81:80];
+    assign c[243:242] = a[723:722];
+    assign c[245:244] = {a[402], a[403]};
+    assign c[247:246] = a[83:82];
+    assign c[249:248] = a[725:724];
+    assign c[251:250] = {a[404], a[405]};
+    assign c[253:252] = a[801:800];
+    assign c[255:254] = a[481:480];
+    assign c[257:256] = {a[406], a[407]};
+    assign c[259:258] = a[803:802];
+    assign c[261:260] = a[483:482];
+    assign c[263:262] = {a[408], a[409]};
+    assign c[265:264] = a[805:804];
+    assign c[267:266] = a[485:484];
+    assign c[269:268] = a[881:880];
+    assign c[271:270] = a[807:806];
+    assign c[273:272] = a[487:486];
+    assign c[275:274] = a[883:882];
+    assign c[277:276] = a[809:808];
+    assign c[279:278] = a[489:488];
+    assign c[281:280] = a[885:884];
+    assign c[283:282] = {a[1056], a[1057]};
+    assign c[285:284] = a[737:736];
+    assign c[287:286] = {a[416], a[417]};
+    assign c[289:288] = a[97:96];
+    assign c[291:290] = a[739:738];
+    assign c[293:292] = {a[418], a[419]};
+    assign c[295:294] = a[99:98];
+    assign c[297:296] = a[741:740];
+    assign c[299:298] = {a[420], a[421]};
+    assign c[301:300] = a[817:816];
+    assign c[303:302] = a[497:496];
+    assign c[305:304] = {a[422], a[423]};
+    assign c[307:306] = a[819:818];
+    assign c[309:308] = a[499:498];
+    assign c[311:310] = {a[424], a[425]};
+    assign c[313:312] = a[821:820];
+    assign c[315:314] = a[501:500];
+    assign c[317:316] = a[897:896];
+    assign c[319:318] = a[823:822];
+    assign c[321:320] = a[503:502];
+    assign c[323:322] = a[899:898];
+    assign c[325:324] = a[825:824];
+    assign c[327:326] = a[505:504];
+    assign c[329:328] = a[901:900];
+    assign c[331:330] = {a[1072], a[1073]};
+    assign c[333:332] = a[753:752];
+    assign c[335:334] = {a[432], a[433]};
+    assign c[337:336] = a[113:112];
+    assign c[339:338] = a[755:754];
+    assign c[341:340] = {a[434], a[435]};
+    assign c[343:342] = a[115:114];
+    assign c[345:344] = a[757:756];
+    assign c[347:346] = {a[436], a[437]};
+    assign c[349:348] = a[833:832];
+    assign c[351:350] = a[513:512];
+    assign c[353:352] = {a[438], a[439]};
+    assign c[355:354] = a[835:834];
+    assign c[357:356] = a[515:514];
+    assign c[359:358] = {a[440], a[441]};
+    assign c[361:360] = a[837:836];
+    assign c[363:362] = a[517:516];
+    assign c[365:364] = a[913:912];
+    assign c[367:366] = a[839:838];
+    assign c[369:368] = a[519:518];
+    assign c[371:370] = a[915:914];
+    assign c[373:372] = a[841:840];
+    assign c[375:374] = a[521:520];
+    assign c[377:376] = a[917:916];
+    assign c[379:378] = {a[1088], a[1089]};
+    assign c[381:380] = a[769:768];
+    assign c[383:382] = {a[448], a[449]};
+    assign c[385:384] = a[129:128];
+    assign c[387:386] = a[771:770];
+    assign c[389:388] = {a[450], a[451]};
+    assign c[391:390] = a[131:130];
+    assign c[393:392] = a[773:772];
+    assign c[395:394] = {a[452], a[453]};
+    assign c[397:396] = a[849:848];
+    assign c[399:398] = a[529:528];
+    assign c[401:400] = {a[454], a[455]};
+    assign c[403:402] = a[851:850];
+    assign c[405:404] = a[531:530];
+    assign c[407:406] = {a[456], a[457]};
+    assign c[409:408] = a[853:852];
+    assign c[411:410] = a[533:532];
+    assign c[413:412] = a[929:928];
+    assign c[415:414] = a[855:854];
+    assign c[417:416] = a[535:534];
+    assign c[419:418] = a[931:930];
+    assign c[421:420] = a[857:856];
+    assign c[423:422] = a[537:536];
+    assign c[425:424] = a[933:932];
+    assign c[427:426] = {a[1104], a[1105]};
+    assign c[429:428] = a[785:784];
+    assign c[431:430] = {a[464], a[465]};
+    assign c[433:432] = a[145:144];
+    assign c[435:434] = a[787:786];
+    assign c[437:436] = {a[466], a[467]};
+    assign c[439:438] = a[147:146];
+    assign c[441:440] = a[789:788];
+    assign c[443:442] = {a[468], a[469]};
+    assign c[445:444] = a[865:864];
+    assign c[447:446] = a[545:544];
+    assign c[449:448] = {a[470], a[471]};
+    assign c[451:450] = a[867:866];
+    assign c[453:452] = a[547:546];
+    assign c[455:454] = {a[472], a[473]};
+    assign c[457:456] = a[869:868];
+    assign c[459:458] = a[549:548];
+    assign c[461:460] = a[945:944];
+    assign c[463:462] = a[871:870];
+    assign c[465:464] = a[551:550];
+    assign c[467:466] = a[947:946];
+    assign c[469:468] = a[873:872];
+    assign c[471:470] = a[553:552];
+    assign c[473:472] = a[949:948];
+    assign c[475:474] = {a[1120], a[1121]};
+    assign c[477:476] = a[801:800];
+    assign c[479:478] = {a[480], a[481]};
+    assign c[481:480] = a[161:160];
+    assign c[483:482] = a[803:802];
+    assign c[485:484] = {a[482], a[483]};
+    assign c[487:486] = a[163:162];
+    assign c[489:488] = a[805:804];
+    assign c[491:490] = {a[484], a[485]};
+    assign c[493:492] = a[881:880];
+    assign c[495:494] = a[561:560];
+    assign c[497:496] = {a[486], a[487]};
+    assign c[499:498] = a[883:882];
+    assign c[501:500] = a[563:562];
+    assign c[503:502] = {a[488], a[489]};
+    assign c[505:504] = a[885:884];
+    assign c[507:506] = a[565:564];
+    assign c[509:508] = a[961:960];
+    assign c[511:510] = a[887:886];
+    assign c[513:512] = a[567:566];
+    assign c[515:514] = a[963:962];
+    assign c[517:516] = a[889:888];
+    assign c[519:518] = a[569:568];
+    assign c[521:520] = a[965:964];
+    assign c[523:522] = {a[1136], a[1137]};
+    assign c[525:524] = a[817:816];
+    assign c[527:526] = {a[496], a[497]};
+    assign c[529:528] = a[177:176];
+    assign c[531:530] = a[819:818];
+    assign c[533:532] = {a[498], a[499]};
+    assign c[535:534] = a[179:178];
+    assign c[537:536] = a[821:820];
+    assign c[539:538] = {a[500], a[501]};
+    assign c[541:540] = a[897:896];
+    assign c[543:542] = a[577:576];
+    assign c[545:544] = {a[502], a[503]};
+    assign c[547:546] = a[899:898];
+    assign c[549:548] = a[579:578];
+    assign c[551:550] = {a[504], a[505]};
+    assign c[553:552] = a[901:900];
+    assign c[555:554] = a[581:580];
+    assign c[557:556] = a[977:976];
+    assign c[559:558] = a[903:902];
+    assign c[561:560] = a[583:582];
+    assign c[563:562] = a[979:978];
+    assign c[565:564] = a[905:904];
+    assign c[567:566] = a[585:584];
+    assign c[569:568] = a[981:980];
+    assign c[571:570] = {a[1152], a[1153]};
+    assign c[573:572] = a[833:832];
+    assign c[575:574] = {a[512], a[513]};
+    assign c[577:576] = a[193:192];
+    assign c[579:578] = a[835:834];
+    assign c[581:580] = {a[514], a[515]};
+    assign c[583:582] = a[195:194];
+    assign c[585:584] = a[837:836];
+    assign c[587:586] = {a[516], a[517]};
+    assign c[589:588] = a[913:912];
+    assign c[591:590] = a[593:592];
+    assign c[593:592] = {a[518], a[519]};
+    assign c[595:594] = a[915:914];
+    assign c[597:596] = a[595:594];
+    assign c[599:598] = {a[520], a[521]};
+    assign c[601:600] = a[917:916];
+    assign c[603:602] = a[597:596];
+    assign c[605:604] = a[993:992];
+    assign c[607:606] = a[919:918];
+    assign c[609:608] = a[599:598];
+    assign c[611:610] = a[995:994];
+    assign c[613:612] = a[921:920];
+    assign c[615:614] = a[601:600];
+    assign c[617:616] = a[997:996];
+    assign c[619:618] = {a[1168], a[1169]};
+    assign c[621:620] = a[849:848];
+    assign c[623:622] = {a[528], a[529]};
+    assign c[625:624] = a[209:208];
+    assign c[627:626] = a[851:850];
+    assign c[629:628] = {a[530], a[531]};
+    assign c[631:630] = a[211:210];
+    assign c[633:632] = a[853:852];
+    assign c[635:634] = {a[532], a[533]};
+    assign c[637:636] = a[929:928];
+    assign c[639:638] = a[609:608];
+    assign c[641:640] = {a[534], a[535]};
+    assign c[643:642] = a[931:930];
+    assign c[645:644] = a[611:610];
+    assign c[647:646] = {a[536], a[537]};
+    assign c[649:648] = a[933:932];
+    assign c[651:650] = a[613:612];
+    assign c[653:652] = a[1009:1008];
+    assign c[655:654] = a[935:934];
+    assign c[657:656] = a[615:614];
+    assign c[659:658] = a[1011:1010];
+    assign c[661:660] = a[937:936];
+    assign c[663:662] = a[617:616];
+    assign c[665:664] = a[1013:1012];
+    assign c[667:666] = {a[1184], a[1185]};
+    assign c[669:668] = a[865:864];
+    assign c[671:670] = {a[544], a[545]};
+    assign c[673:672] = a[225:224];
+    assign c[675:674] = a[867:866];
+    assign c[677:676] = {a[546], a[547]};
+    assign c[679:678] = a[227:226];
+    assign c[681:680] = a[869:868];
+    assign c[683:682] = {a[548], a[549]};
+    assign c[685:684] = a[945:944];
+    assign c[687:686] = a[625:624];
+    assign c[689:688] = {a[550], a[551]};
+    assign c[691:690] = a[947:946];
+    assign c[693:692] = a[627:626];
+    assign c[695:694] = {a[552], a[553]};
+    assign c[697:696] = a[949:948];
+    assign c[699:698] = a[629:628];
+    assign c[701:700] = a[1025:1024];
+    assign c[703:702] = a[951:950];
+    assign c[705:704] = a[631:630];
+    assign c[707:706] = a[1027:1026];
+    assign c[709:708] = a[953:952];
+    assign c[711:710] = a[633:632];
+    assign c[713:712] = a[1029:1028];
+    assign c[715:714] = a[955:954];
+    assign c[717:716] = a[881:880];
+    assign c[719:718] = {a[560], a[561]};
+    assign c[721:720] = a[241:240];
+    assign c[723:722] = a[883:882];
+    assign c[725:724] = {a[562], a[563]};
+    assign c[727:726] = a[243:242];
+    assign c[729:728] = a[885:884];
+    assign c[731:730] = {a[564], a[565]};
+    assign c[733:732] = a[961:960];
+    assign c[735:734] = a[641:640];
+    assign c[737:736] = {a[566], a[567]};
+    assign c[739:738] = a[963:962];
+    assign c[741:740] = a[643:642];
+    assign c[743:742] = {a[568], a[569]};
+    assign c[745:744] = a[965:964];
+    assign c[747:746] = a[645:644];
+    assign c[749:748] = a[1041:1040];
+    assign c[751:750] = a[967:966];
+    assign c[753:752] = a[647:646];
+    assign c[755:754] = a[1043:1042];
+    assign c[757:756] = a[969:968];
+    assign c[759:758] = a[649:648];
+    assign c[761:760] = a[1045:1044];
+    assign c[763:762] = a[971:970];
+    assign c[765:764] = a[897:896];
+    assign c[767:766] = {a[576], a[577]};
+    assign c[769:768] = a[257:256];
+    assign c[771:770] = a[899:898];
+    assign c[773:772] = {a[578], a[579]};
+    assign c[775:774] = a[259:258];
+    assign c[777:776] = a[901:900];
+    assign c[779:778] = {a[580], a[581]};
+    assign c[781:780] = a[977:976];
+    assign c[783:782] = a[657:656];
+    assign c[785:784] = {a[582], a[583]};
+    assign c[787:786] = a[979:978];
+    assign c[789:788] = a[659:658];
+    assign c[791:790] = {a[584], a[585]};
+    assign c[793:792] = a[981:980];
+    assign c[795:794] = a[661:660];
+    assign c[797:796] = a[1057:1056];
+    assign c[799:798] = a[983:982];
+    assign c[801:800] = a[663:662];
+    assign c[803:802] = a[1059:1058];
+    assign c[805:804] = a[985:984];
+    assign c[807:806] = a[665:664];
+    assign c[809:808] = a[1061:1060];
+    assign c[811:810] = a[987:986];
+    assign c[813:812] = a[913:912];
+    assign c[815:814] = {a[592], a[593]};
+    assign c[817:816] = a[273:272];
+    assign c[819:818] = a[915:914];
+    assign c[821:820] = {a[594], a[595]};
+    assign c[823:822] = a[275:274];
+    assign c[825:824] = a[917:916];
+    assign c[827:826] = {a[596], a[597]};
+    assign c[829:828] = a[993:992];
+    assign c[831:830] = a[673:672];
+    assign c[833:832] = {a[598], a[599]};
+    assign c[835:834] = a[995:994];
+    assign c[837:836] = a[675:674];
+    assign c[839:838] = {a[600], a[601]};
+    assign c[841:840] = a[997:996];
+    assign c[843:842] = a[677:676];
+    assign c[845:844] = a[1073:1072];
+    assign c[847:846] = a[999:998];
+    assign c[849:848] = a[679:678];
+    assign c[851:850] = a[1075:1074];
+    assign c[853:852] = a[1001:1000];
+    assign c[855:854] = a[681:680];
+    assign c[857:856] = a[1077:1076];
+    assign c[859:858] = a[1003:1002];
+    assign c[861:860] = a[929:928];
+    assign c[863:862] = {a[608], a[609]};
+    assign c[865:864] = a[289:288];
+    assign c[867:866] = a[931:930];
+    assign c[869:868] = {a[610], a[611]};
+    assign c[871:870] = a[291:290];
+    assign c[873:872] = a[933:932];
+    assign c[875:874] = {a[612], a[613]};
+    assign c[877:876] = a[1009:1008];
+    assign c[879:878] = a[689:688];
+    assign c[881:880] = {a[614], a[615]};
+    assign c[883:882] = a[1011:1010];
+    assign c[885:884] = a[691:690];
+    assign c[887:886] = {a[616], a[617]};
+    assign c[889:888] = a[1013:1012];
+    assign c[891:890] = a[693:692];
+    assign c[893:892] = a[1089:1088];
+    assign c[895:894] = a[1015:1014];
+    assign c[897:896] = a[695:694];
+    assign c[899:898] = a[1091:1090];
+    assign c[901:900] = a[1017:1016];
+    assign c[903:902] = a[697:696];
+    assign c[905:904] = a[1093:1092];
+    assign c[907:906] = a[1019:1018];
+    assign c[909:908] = a[945:944];
+    assign c[911:910] = {a[624], a[625]};
+    assign c[913:912] = a[305:304];
+    assign c[915:914] = a[947:946];
+    assign c[917:916] = {a[626], a[627]};
+    assign c[919:918] = a[307:306];
+    assign c[921:920] = a[949:948];
+    assign c[923:922] = {a[628], a[629]};
+    assign c[925:924] = a[1025:1024];
+    assign c[927:926] = a[705:704];
+    assign c[929:928] = {a[630], a[631]};
+    assign c[931:930] = a[1027:1026];
+    assign c[933:932] = a[707:706];
+    assign c[935:934] = {a[632], a[633]};
+    assign c[937:936] = a[1029:1028];
+    assign c[939:938] = a[709:708];
+    assign c[941:940] = a[1105:1104];
+    assign c[943:942] = a[1031:1030];
+    assign c[945:944] = a[711:710];
+    assign c[947:946] = a[1107:1106];
+    assign c[949:948] = a[1033:1032];
+    assign c[951:950] = a[713:712];
+    assign c[953:952] = a[1109:1108];
+    assign c[955:954] = a[1035:1034];
+    assign c[957:956] = a[961:960];
+    assign c[959:958] = {a[640], a[641]};
+    assign c[961:960] = a[321:320];
+    assign c[963:962] = a[963:962];
+    assign c[965:964] = {a[642], a[643]};
+    assign c[967:966] = a[323:322];
+    assign c[969:968] = a[965:964];
+    assign c[971:970] = {a[644], a[645]};
+    assign c[973:972] = a[1041:1040];
+    assign c[975:974] = a[721:720];
+    assign c[977:976] = {a[646], a[647]};
+    assign c[979:978] = a[1043:1042];
+    assign c[981:980] = a[723:722];
+    assign c[983:982] = {a[648], a[649]};
+    assign c[985:984] = a[1045:1044];
+    assign c[987:986] = a[725:724];
+    assign c[989:988] = a[1121:1120];
+    assign c[991:990] = a[1047:1046];
+    assign c[993:992] = a[727:726];
+    assign c[995:994] = a[1123:1122];
+    assign c[997:996] = a[1049:1048];
+    assign c[999:998] = a[729:728];
+    assign c[1001:1000] = a[1125:1124];
+    assign c[1003:1002] = a[1051:1050];
+    assign c[1005:1004] = a[977:976];
+    assign c[1007:1006] = {a[656], a[657]};
+    assign c[1009:1008] = a[337:336];
+    assign c[1011:1010] = a[979:978];
+    assign c[1013:1012] = {a[658], a[659]};
+    assign c[1015:1014] = a[339:338];
+    assign c[1017:1016] = a[981:980];
+    assign c[1019:1018] = {a[660], a[661]};
+    assign c[1021:1020] = a[1057:1056];
+    assign c[1023:1022] = a[737:736];
+    assign c[1025:1024] = {a[662], a[663]};
+    assign c[1027:1026] = a[1059:1058];
+    assign c[1029:1028] = a[739:738];
+    assign c[1031:1030] = {a[664], a[665]};
+    assign c[1033:1032] = a[1061:1060];
+    assign c[1035:1034] = a[741:740];
+    assign c[1037:1036] = a[1137:1136];
+    assign c[1039:1038] = a[1063:1062];
+    assign c[1041:1040] = a[743:742];
+    assign c[1043:1042] = a[1139:1138];
+    assign c[1045:1044] = a[1065:1064];
+    assign c[1047:1046] = a[745:744];
+    assign c[1049:1048] = a[1141:1140];
+    assign c[1051:1050] = a[1067:1066];
+    assign c[1053:1052] = a[993:992];
+    assign c[1055:1054] = {a[672], a[673]};
+    assign c[1057:1056] = a[353:352];
+    assign c[1059:1058] = a[995:994];
+    assign c[1061:1060] = {a[674], a[675]};
+    assign c[1063:1062] = a[355:354];
+    assign c[1065:1064] = a[997:996];
+    assign c[1067:1066] = {a[676], a[677]};
+    assign c[1069:1068] = a[1073:1072];
+    assign c[1071:1070] = a[753:752];
+    assign c[1073:1072] = {a[678], a[679]};
+    assign c[1075:1074] = a[1075:1074];
+    assign c[1077:1076] = a[755:754];
+    assign c[1079:1078] = {a[680], a[681]};
+    assign c[1081:1080] = a[1077:1076];
+    assign c[1083:1082] = a[757:756];
+    assign c[1085:1084] = a[1153:1152];
+    assign c[1087:1086] = a[1079:1078];
+    assign c[1089:1088] = a[759:758];
+    assign c[1091:1090] = a[1155:1154];
+    assign c[1093:1092] = a[1081:1080];
+    assign c[1095:1094] = a[761:760];
+    assign c[1097:1096] = a[1157:1156];
+    assign c[1099:1098] = a[1083:1082];
+    assign c[1101:1100] = a[1009:1008];
+    assign c[1103:1102] = {a[688], a[689]};
+    assign c[1105:1104] = a[369:368];
+    assign c[1107:1106] = a[1011:1010];
+    assign c[1109:1108] = {a[690], a[691]};
+    assign c[1111:1110] = a[371:370];
+    assign c[1113:1112] = a[1013:1012];
+    assign c[1115:1114] = {a[692], a[693]};
+    assign c[1117:1116] = a[1089:1088];
+    assign c[1119:1118] = a[769:768];
+    assign c[1121:1120] = {a[694], a[695]};
+    assign c[1123:1122] = a[1091:1090];
+    assign c[1125:1124] = a[771:770];
+    assign c[1127:1126] = {a[696], a[697]};
+    assign c[1129:1128] = a[1093:1092];
+    assign c[1131:1130] = a[773:772];
+    assign c[1133:1132] = a[1169:1168];
+    assign c[1135:1134] = a[1095:1094];
+    assign c[1137:1136] = a[775:774];
+    assign c[1139:1138] = a[1171:1170];
+    assign c[1141:1140] = a[1097:1096];
+    assign c[1143:1142] = a[777:776];
+    assign c[1145:1144] = a[1173:1172];
+    assign c[1147:1146] = a[1099:1098];
+    assign c[1149:1148] = a[1025:1024];
+    assign c[1151:1150] = {a[704], a[705]};
+    assign c[1153:1152] = a[385:384];
+    assign c[1155:1154] = a[1027:1026];
+    assign c[1157:1156] = {a[706], a[707]};
+    assign c[1159:1158] = a[387:386];
+    assign c[1161:1160] = a[1029:1028];
+    assign c[1163:1162] = {a[708], a[709]};
+    assign c[1165:1164] = a[1105:1104];
+    assign c[1167:1166] = a[785:784];
+    assign c[1169:1168] = {a[710], a[711]};
+    assign c[1171:1170] = a[1107:1106];
+    assign c[1173:1172] = a[787:786];
+    assign c[1175:1174] = {a[712], a[713]};
+    assign c[1177:1176] = a[1109:1108];
+    assign c[1179:1178] = a[789:788];
+    assign c[1181:1180] = a[1185:1184];
+    assign c[1183:1182] = a[1111:1110];
+    assign c[1185:1184] = a[791:790];
+endmodule
+/* c == v1(a) */
+module v1(a, c);
+    input [1185:0] a;
+    output [1185:0] c;
+    assign c[1:0] = {a[716], a[717]};
+    assign c[3:2] = a[397:396];
+    assign c[5:4] = a[1039:1038];
+    assign c[7:6] = {a[718], a[719]};
+    assign c[9:8] = a[399:398];
+    assign c[11:10] = a[795:794];
+    assign c[13:12] = a[5:4];
+    assign c[15:14] = a[1117:1116];
+    assign c[17:16] = a[797:796];
+    assign c[19:18] = a[7:6];
+    assign c[21:20] = a[1119:1118];
+    assign c[23:22] = a[799:798];
+    assign c[25:24] = a[9:8];
+    assign c[27:26] = a[405:404];
+    assign c[29:28] = a[1047:1046];
+    assign c[31:30] = a[11:10];
+    assign c[33:32] = a[407:406];
+    assign c[35:34] = a[1049:1048];
+    assign c[37:36] = a[13:12];
+    assign c[39:38] = a[409:408];
+    assign c[41:40] = a[1051:1050];
+    assign c[43:42] = a[15:14];
+    assign c[45:44] = a[411:410];
+    assign c[47:46] = a[1053:1052];
+    assign c[49:48] = {a[732], a[733]};
+    assign c[51:50] = a[413:412];
+    assign c[53:52] = a[1055:1054];
+    assign c[55:54] = {a[734], a[735]};
+    assign c[57:56] = a[415:414];
+    assign c[59:58] = a[811:810];
+    assign c[61:60] = a[21:20];
+    assign c[63:62] = a[1133:1132];
+    assign c[65:64] = a[813:812];
+    assign c[67:66] = a[23:22];
+    assign c[69:68] = a[1135:1134];
+    assign c[71:70] = a[815:814];
+    assign c[73:72] = a[25:24];
+    assign c[75:74] = a[421:420];
+    assign c[77:76] = a[1063:1062];
+    assign c[79:78] = a[27:26];
+    assign c[81:80] = a[423:422];
+    assign c[83:82] = a[1065:1064];
+    assign c[85:84] = a[29:28];
+    assign c[87:86] = a[425:424];
+    assign c[89:88] = a[1067:1066];
+    assign c[91:90] = a[31:30];
+    assign c[93:92] = a[427:426];
+    assign c[95:94] = a[1069:1068];
+    assign c[97:96] = {a[748], a[749]};
+    assign c[99:98] = a[429:428];
+    assign c[101:100] = a[1071:1070];
+    assign c[103:102] = {a[750], a[751]};
+    assign c[105:104] = a[431:430];
+    assign c[107:106] = a[827:826];
+    assign c[109:108] = a[37:36];
+    assign c[111:110] = a[1149:1148];
+    assign c[113:112] = a[829:828];
+    assign c[115:114] = a[39:38];
+    assign c[117:116] = a[1151:1150];
+    assign c[119:118] = a[831:830];
+    assign c[121:120] = a[41:40];
+    assign c[123:122] = a[437:436];
+    assign c[125:124] = a[1079:1078];
+    assign c[127:126] = a[43:42];
+    assign c[129:128] = a[439:438];
+    assign c[131:130] = a[1081:1080];
+    assign c[133:132] = a[45:44];
+    assign c[135:134] = a[441:440];
+    assign c[137:136] = a[1083:1082];
+    assign c[139:138] = a[47:46];
+    assign c[141:140] = a[443:442];
+    assign c[143:142] = a[1085:1084];
+    assign c[145:144] = {a[764], a[765]};
+    assign c[147:146] = a[445:444];
+    assign c[149:148] = a[1087:1086];
+    assign c[151:150] = {a[766], a[767]};
+    assign c[153:152] = a[447:446];
+    assign c[155:154] = a[843:842];
+    assign c[157:156] = a[53:52];
+    assign c[159:158] = a[1165:1164];
+    assign c[161:160] = a[845:844];
+    assign c[163:162] = a[55:54];
+    assign c[165:164] = a[1167:1166];
+    assign c[167:166] = a[847:846];
+    assign c[169:168] = a[57:56];
+    assign c[171:170] = a[453:452];
+    assign c[173:172] = a[1095:1094];
+    assign c[175:174] = a[59:58];
+    assign c[177:176] = a[455:454];
+    assign c[179:178] = a[1097:1096];
+    assign c[181:180] = a[61:60];
+    assign c[183:182] = a[457:456];
+    assign c[185:184] = a[1099:1098];
+    assign c[187:186] = a[63:62];
+    assign c[189:188] = a[459:458];
+    assign c[191:190] = a[1101:1100];
+    assign c[193:192] = {a[780], a[781]};
+    assign c[195:194] = a[461:460];
+    assign c[197:196] = a[1103:1102];
+    assign c[199:198] = {a[782], a[783]};
+    assign c[201:200] = a[463:462];
+    assign c[203:202] = a[859:858];
+    assign c[205:204] = a[69:68];
+    assign c[207:206] = a[1181:1180];
+    assign c[209:208] = a[861:860];
+    assign c[211:210] = a[71:70];
+    assign c[213:212] = a[1183:1182];
+    assign c[215:214] = a[863:862];
+    assign c[217:216] = a[73:72];
+    assign c[219:218] = a[469:468];
+    assign c[221:220] = a[1111:1110];
+    assign c[223:222] = a[75:74];
+    assign c[225:224] = a[717:716];
+    assign c[227:226] = {a[396], a[397]};
+    assign c[229:228] = a[77:76];
+    assign c[231:230] = a[719:718];
+    assign c[233:232] = {a[398], a[399]};
+    assign c[235:234] = a[795:794];
+    assign c[237:236] = a[475:474];
+    assign c[239:238] = a[871:870];
+    assign c[241:240] = {a[1042], a[1043]};
+    assign c[243:242] = a[477:476];
+    assign c[245:244] = a[873:872];
+    assign c[247:246] = {a[1044], a[1045]};
+    assign c[249:248] = a[479:478];
+    assign c[251:250] = a[875:874];
+    assign c[253:252] = a[85:84];
+    assign c[255:254] = a[727:726];
+    assign c[257:256] = a[877:876];
+    assign c[259:258] = a[87:86];
+    assign c[261:260] = a[729:728];
+    assign c[263:262] = a[879:878];
+    assign c[265:264] = a[89:88];
+    assign c[267:266] = a[731:730];
+    assign c[269:268] = {a[410], a[411]};
+    assign c[271:270] = a[91:90];
+    assign c[273:272] = a[733:732];
+    assign c[275:274] = {a[412], a[413]};
+    assign c[277:276] = a[93:92];
+    assign c[279:278] = a[735:734];
+    assign c[281:280] = {a[414], a[415]};
+    assign c[283:282] = a[811:810];
+    assign c[285:284] = a[491:490];
+    assign c[287:286] = a[887:886];
+    assign c[289:288] = {a[1058], a[1059]};
+    assign c[291:290] = a[493:492];
+    assign c[293:292] = a[889:888];
+    assign c[295:294] = {a[1060], a[1061]};
+    assign c[297:296] = a[495:494];
+    assign c[299:298] = a[891:890];
+    assign c[301:300] = a[101:100];
+    assign c[303:302] = a[743:742];
+    assign c[305:304] = a[893:892];
+    assign c[307:306] = a[103:102];
+    assign c[309:308] = a[745:744];
+    assign c[311:310] = a[895:894];
+    assign c[313:312] = a[105:104];
+    assign c[315:314] = a[747:746];
+    assign c[317:316] = {a[426], a[427]};
+    assign c[319:318] = a[107:106];
+    assign c[321:320] = a[749:748];
+    assign c[323:322] = {a[428], a[429]};
+    assign c[325:324] = a[109:108];
+    assign c[327:326] = a[751:750];
+    assign c[329:328] = {a[430], a[431]};
+    assign c[331:330] = a[827:826];
+    assign c[333:332] = a[507:506];
+    assign c[335:334] = a[903:902];
+    assign c[337:336] = {a[1074], a[1075]};
+    assign c[339:338] = a[509:508];
+    assign c[341:340] = a[905:904];
+    assign c[343:342] = {a[1076], a[1077]};
+    assign c[345:344] = a[511:510];
+    assign c[347:346] = a[907:906];
+    assign c[349:348] = a[117:116];
+    assign c[351:350] = a[759:758];
+    assign c[353:352] = a[909:908];
+    assign c[355:354] = a[119:118];
+    assign c[357:356] = a[761:760];
+    assign c[359:358] = a[911:910];
+    assign c[361:360] = a[121:120];
+    assign c[363:362] = a[763:762];
+    assign c[365:364] = {a[442], a[443]};
+    assign c[367:366] = a[123:122];
+    assign c[369:368] = a[765:764];
+    assign c[371:370] = {a[444], a[445]};
+    assign c[373:372] = a[125:124];
+    assign c[375:374] = a[767:766];
+    assign c[377:376] = {a[446], a[447]};
+    assign c[379:378] = a[843:842];
+    assign c[381:380] = a[523:522];
+    assign c[383:382] = a[919:918];
+    assign c[385:384] = {a[1090], a[1091]};
+    assign c[387:386] = a[525:524];
+    assign c[389:388] = a[921:920];
+    assign c[391:390] = {a[1092], a[1093]};
+    assign c[393:392] = a[527:526];
+    assign c[395:394] = a[923:922];
+    assign c[397:396] = a[133:132];
+    assign c[399:398] = a[775:774];
+    assign c[401:400] = a[925:924];
+    assign c[403:402] = a[135:134];
+    assign c[405:404] = a[777:776];
+    assign c[407:406] = a[927:926];
+    assign c[409:408] = a[137:136];
+    assign c[411:410] = a[779:778];
+    assign c[413:412] = {a[458], a[459]};
+    assign c[415:414] = a[139:138];
+    assign c[417:416] = a[781:780];
+    assign c[419:418] = {a[460], a[461]};
+    assign c[421:420] = a[141:140];
+    assign c[423:422] = a[783:782];
+    assign c[425:424] = {a[462], a[463]};
+    assign c[427:426] = a[859:858];
+    assign c[429:428] = a[539:538];
+    assign c[431:430] = a[935:934];
+    assign c[433:432] = {a[1106], a[1107]};
+    assign c[435:434] = a[541:540];
+    assign c[437:436] = a[937:936];
+    assign c[439:438] = {a[1108], a[1109]};
+    assign c[441:440] = a[543:542];
+    assign c[443:442] = a[939:938];
+    assign c[445:444] = a[149:148];
+    assign c[447:446] = a[791:790];
+    assign c[449:448] = a[941:940];
+    assign c[451:450] = a[151:150];
+    assign c[453:452] = a[793:792];
+    assign c[455:454] = a[943:942];
+    assign c[457:456] = a[153:152];
+    assign c[459:458] = a[795:794];
+    assign c[461:460] = {a[474], a[475]};
+    assign c[463:462] = a[155:154];
+    assign c[465:464] = a[797:796];
+    assign c[467:466] = {a[476], a[477]};
+    assign c[469:468] = a[157:156];
+    assign c[471:470] = a[799:798];
+    assign c[473:472] = {a[478], a[479]};
+    assign c[475:474] = a[875:874];
+    assign c[477:476] = a[555:554];
+    assign c[479:478] = a[951:950];
+    assign c[481:480] = {a[1122], a[1123]};
+    assign c[483:482] = a[557:556];
+    assign c[485:484] = a[953:952];
+    assign c[487:486] = {a[1124], a[1125]};
+    assign c[489:488] = a[559:558];
+    assign c[491:490] = a[955:954];
+    assign c[493:492] = a[165:164];
+    assign c[495:494] = a[807:806];
+    assign c[497:496] = a[957:956];
+    assign c[499:498] = a[167:166];
+    assign c[501:500] = a[809:808];
+    assign c[503:502] = a[959:958];
+    assign c[505:504] = a[169:168];
+    assign c[507:506] = a[811:810];
+    assign c[509:508] = {a[490], a[491]};
+    assign c[511:510] = a[171:170];
+    assign c[513:512] = a[813:812];
+    assign c[515:514] = {a[492], a[493]};
+    assign c[517:516] = a[173:172];
+    assign c[519:518] = a[815:814];
+    assign c[521:520] = {a[494], a[495]};
+    assign c[523:522] = a[891:890];
+    assign c[525:524] = a[571:570];
+    assign c[527:526] = a[967:966];
+    assign c[529:528] = {a[1138], a[1139]};
+    assign c[531:530] = a[573:572];
+    assign c[533:532] = a[969:968];
+    assign c[535:534] = {a[1140], a[1141]};
+    assign c[537:536] = a[575:574];
+    assign c[539:538] = a[971:970];
+    assign c[541:540] = a[181:180];
+    assign c[543:542] = a[823:822];
+    assign c[545:544] = a[973:972];
+    assign c[547:546] = a[183:182];
+    assign c[549:548] = a[825:824];
+    assign c[551:550] = a[975:974];
+    assign c[553:552] = a[185:184]'b';
+    assign c[555:554] = a[827:826];
+    assign c[557:556] = {a[506], a[507]};
+    assign c[559:558] = a[187:186];
+    assign c[561:560] = a[829:828];
+    assign c[563:562] = {a[508], a[509]};
+    assign c[565:564] = a[189:188];
+    assign c[567:566] = a[831:830];
+    assign c[569:568] = {a[510], a[511]};
+    assign c[571:570] = a[907:906];
+    assign c[573:572] = a[587:586];
+    assign c[575:574] = a[983:982];
+    assign c[577:576] = {a[1154], a[1155]};
+    assign c[579:578] = a[589:588];
+    assign c[581:580] = a[985:984];
+    assign c[583:582] = {a[1156], a[1157]};
+    assign c[585:584] = a[591:590];
+    assign c[587:586] = a[987:986];
+    assign c[589:588] = a[197:196];
+    assign c[591:590] = a[839:838];
+    assign c[593:592] = a[989:988];
+    assign c[595:594] = a[199:198];
+    assign c[597:596] = a[841:840];
+    assign c[599:598] = a[991:990];
+    assign c[601:600] = a[201:200];
+    assign c[603:602] = a[843:842];
+    assign c[605:604] = {a[522], a[523]};
+    assign c[607:606] = a[203:202];
+    assign c[609:608] = a[845:844];
+    assign c[611:610] = {a[524], a[525]};
+    assign c[613:612] = a[205:204];
+    assign c[615:614] = a[847:846];
+    assign c[617:616] = {a[526], a[527]};
+    assign c[619:618] = a[923:922];
+    assign c[621:620] = a[603:602];
+    assign c[623:622] = a[999:998];
+    assign c[625:624] = {a[1170], a[1171]};
+    assign c[627:626] = a[605:604];
+    assign c[629:628] = a[1001:1000];
+    assign c[631:630] = {a[1172], a[1173]};
+    assign c[633:632] = a[607:606];
+    assign c[635:634] = a[1003:1002];
+    assign c[637:636] = a[213:212];
+    assign c[639:638] = a[855:854];
+    assign c[641:640] = a[1005:1004];
+    assign c[643:642] = a[215:214];
+    assign c[645:644] = a[857:856];
+    assign c[647:646] = a[1007:1006];
+    assign c[649:648] = a[217:216];
+    assign c[651:650] = a[859:858];
+    assign c[653:652] = {a[538], a[539]};
+    assign c[655:654] = a[219:218];
+    assign c[657:656] = a[861:860];
+    assign c[659:658] = {a[540], a[541]};
+    assign c[661:660] = a[221:220];
+    assign c[663:662] = a[863:862];
+    assign c[665:664] = {a[542], a[543]};
+    assign c[667:666] = a[939:938];
+    assign c[669:668] = a[619:618];
+    assign c[671:670] = a[1015:1014];
+    assign c[673:672] = a[941:940];
+    assign c[675:674] = a[621:620];
+    assign c[677:676] = a[1017:1016];
+    assign c[679:678] = a[943:942];
+    assign c[681:680] = a[623:622];
+    assign c[683:682] = a[1019:1018];
+    assign c[685:684] = a[229:228];
+    assign c[687:686] = a[871:870];
+    assign c[689:688] = a[1021:1020];
+    assign c[691:690] = a[231:230];
+    assign c[693:692] = a[873:872];
+    assign c[695:694] = a[1023:1022];
+    assign c[697:696] = a[233:232];
+    assign c[699:698] = a[875:874];
+    assign c[701:700] = {a[554], a[555]};
+    assign c[703:702] = a[235:234];
+    assign c[705:704] = a[877:876];
+    assign c[707:706] = {a[556], a[557]};
+    assign c[709:708] = a[237:236];
+    assign c[711:710] = a[879:878];
+    assign c[713:712] = {a[558], a[559]};
+    assign c[715:714] = a[239:238];
+    assign c[717:716] = a[635:634];
+    assign c[719:718] = a[1031:1030];
+    assign c[721:720] = a[957:956];
+    assign c[723:722] = a[637:636];
+    assign c[725:724] = a[1033:1032];
+    assign c[727:726] = a[959:958];
+    assign c[729:728] = a[639:638];
+    assign c[731:730] = a[1035:1034];
+    assign c[733:732] = a[245:244];
+    assign c[735:734] = a[887:886];
+    assign c[737:736] = a[1037:1036];
+    assign c[739:738] = a[247:246];
+    assign c[741:740] = a[889:888];
+    assign c[743:742] = a[1039:1038];
+    assign c[745:744] = a[249:248];
+    assign c[747:746] = a[891:890];
+    assign c[749:748] = {a[570], a[571]};
+    assign c[751:750] = a[251:250];
+    assign c[753:752] = a[893:892];
+    assign c[755:754] = {a[572], a[573]};
+    assign c[757:756] = a[253:252];
+    assign c[759:758] = a[895:894];
+    assign c[761:760] = {a[574], a[575]};
+    assign c[763:762] = a[255:254];
+    assign c[765:764] = a[651:650];
+    assign c[767:766] = a[1047:1046];
+    assign c[769:768] = a[973:972];
+    assign c[771:770] = a[653:652];
+    assign c[773:772] = a[1049:1048];
+    assign c[775:774] = a[975:974];
+    assign c[777:776] = a[655:654];
+    assign c[779:778] = a[1051:1050];
+    assign c[781:780] = a[261:260];
+    assign c[783:782] = a[903:902];
+    assign c[785:784] = a[1053:1052];
+    assign c[787:786] = a[263:262];
+    assign c[789:788] = a[905:904];
+    assign c[791:790] = a[1055:1054];
+    assign c[793:792] = a[265:264];
+    assign c[795:794] = a[907:906];
+    assign c[797:796] = {a[586], a[587]};
+    assign c[799:798] = a[267:266];
+    assign c[801:800] = a[909:908];
+    assign c[803:802] = {a[588], a[589]};
+    assign c[805:804] = a[269:268];
+    assign c[807:806] = a[911:910];
+    assign c[809:808] = {a[590], a[591]};
+    assign c[811:810] = a[271:270];
+    assign c[813:812] = a[667:666];
+    assign c[815:814] = a[1063:1062];
+    assign c[817:816] = a[989:988];
+    assign c[819:818] = a[669:668];
+    assign c[821:820] = a[1065:1064];
+    assign c[823:822] = a[991:990];
+    assign c[825:824] = a[671:670];
+    assign c[827:826] = a[1067:1066];
+    assign c[829:828] = a[277:276];
+    assign c[831:830] = a[919:918];
+    assign c[833:832] = a[1069:1068];
+    assign c[835:834] = a[279:278];
+    assign c[837:836] = a[921:920];
+    assign c[839:838] = a[1071:1070];
+    assign c[841:840] = a[281:280];
+    assign c[843:842] = a[923:922];
+    assign c[845:844] = {a[602], a[603]};
+    assign c[847:846] = a[283:282];
+    assign c[849:848] = a[925:924];
+    assign c[851:850] = {a[604], a[605]};
+    assign c[853:852] = a[285:284];
+    assign c[855:854] = a[927:926];
+    assign c[857:856] = {a[606], a[607]};
+    assign c[859:858] = a[287:286];
+    assign c[861:860] = a[683:682];
+    assign c[863:862] = a[1079:1078];
+    assign c[865:864] = a[1005:1004];
+    assign c[867:866] = a[685:684];
+    assign c[869:868] = a[1081:1080];
+    assign c[871:870] = a[1007:1006];
+    assign c[873:872] = a[687:686];
+    assign c[875:874] = a[1083:1082];
+    assign c[877:876] = a[293:292];
+    assign c[879:878] = a[935:934];
+    assign c[881:880] = a[1085:1084];
+    assign c[883:882] = a[295:294];
+    assign c[885:884] = a[937:936];
+    assign c[887:886] = a[1087:1086];
+    assign c[889:888] = a[297:296];
+    assign c[891:890] = a[939:938];
+    assign c[893:892] = {a[618], a[619]};
+    assign c[895:894] = a[299:298];
+    assign c[897:896] = a[941:940];
+    assign c[899:898] = {a[620], a[621]};
+    assign c[901:900] = a[301:300];
+    assign c[903:902] = a[943:942];
+    assign c[905:904] = {a[622], a[623]};
+    assign c[907:906] = a[303:302];
+    assign c[909:908] = a[699:698];
+    assign c[911:910] = a[1095:1094];
+    assign c[913:912] = a[1021:1020];
+    assign c[915:914] = a[701:700];
+    assign c[917:916] = a[1097:1096];
+    assign c[919:918] = a[1023:1022];
+    assign c[921:920] = a[703:702];
+    assign c[923:922] = a[1099:1098];
+    assign c[925:924] = a[309:308];
+    assign c[927:926] = a[951:950];
+    assign c[929:928] = a[1101:1100];
+    assign c[931:930] = a[311:310];
+    assign c[933:932] = a[953:952];
+    assign c[935:934] = a[1103:1102];
+    assign c[937:936] = a[313:312];
+    assign c[939:938] = a[955:954];
+    assign c[941:940] = {a[634], a[635]};
+    assign c[943:942] = a[315:314];
+    assign c[945:944] = a[957:956];
+    assign c[947:946] = {a[636], a[637]};
+    assign c[949:948] = a[317:316];
+    assign c[951:950] = a[959:958];
+    assign c[953:952] = {a[638], a[639]};
+    assign c[955:954] = a[319:318];
+    assign c[957:956] = a[715:714];
+    assign c[959:958] = a[1111:1110];
+    assign c[961:960] = a[1037:1036];
+    assign c[963:962] = a[717:716];
+    assign c[965:964] = a[1113:1112];
+    assign c[967:966] = a[1039:1038];
+    assign c[969:968] = a[719:718];
+    assign c[971:970] = a[1115:1114];
+    assign c[973:972] = a[325:324];
+    assign c[975:974] = a[967:966];
+    assign c[977:976] = a[1117:1116];
+    assign c[979:978] = a[327:326];
+    assign c[981:980] = a[969:968];
+    assign c[983:982] = a[1119:1118];
+    assign c[985:984] = a[329:328];
+    assign c[987:986] = a[971:970];
+    assign c[989:988] = {a[650], a[651]};
+    assign c[991:990] = a[331:330];
+    assign c[993:992] = a[973:972];
+    assign c[995:994] = {a[652], a[653]};
+    assign c[997:996] = a[333:332];
+    assign c[999:998] = a[975:974];
+    assign c[1001:1000] = {a[654], a[655]};
+    assign c[1003:1002] = a[335:334];
+    assign c[1005:1004] = a[731:730];
+    assign c[1007:1006] = a[1127:1126];
+    assign c[1009:1008] = a[1053:1052];
+    assign c[1011:1010] = a[733:732];
+    assign c[1013:1012] = a[1129:1128];
+    assign c[1015:1014] = a[1055:1054];
+    assign c[1017:1016] = a[735:734];
+    assign c[1019:1018] = a[1131:1130];
+    assign c[1021:1020] = a[341:340];
+    assign c[1023:1022] = a[983:982];
+    assign c[1025:1024] = a[1133:1132];
+    assign c[1027:1026] = a[343:342];
+    assign c[1029:1028] = a[985:984];
+    assign c[1031:1030] = a[1135:1134];
+    assign c[1033:1032] = a[345:344];
+    assign c[1035:1034] = a[987:986];
+    assign c[1037:1036] = {a[666], a[667]};
+    assign c[1039:1038] = a[347:346];
+    assign c[1041:1040] = a[989:988];
+    assign c[1043:1042] = {a[668], a[669]};
+    assign c[1045:1044] = a[349:348];
+    assign c[1047:1046] = a[991:990];
+    assign c[1049:1048] = {a[670], a[671]};
+    assign c[1051:1050] = a[351:350];
+    assign c[1053:1052] = a[747:746];
+    assign c[1055:1054] = a[1143:1142];
+    assign c[1057:1056] = a[1069:1068];
+    assign c[1059:1058] = a[749:748];
+    assign c[1061:1060] = a[1145:1144];
+    assign c[1063:1062] = a[1071:1070];
+    assign c[1065:1064] = a[751:750];
+    assign c[1067:1066] = a[1147:1146];
+    assign c[1069:1068] = a[357:356];
+    assign c[1071:1070] = a[999:998];
+    assign c[1073:1072] = a[1149:1148];
+    assign c[1075:1074] = a[359:358];
+    assign c[1077:1076] = a[1001:1000];
+    assign c[1079:1078] = a[1151:1150];
+    assign c[1081:1080] = a[361:360];
+    assign c[1083:1082] = a[1003:1002];
+    assign c[1085:1084] = {a[682], a[683]};
+    assign c[1087:1086] = a[363:362];
+    assign c[1089:1088] = a[1005:1004];
+    assign c[1091:1090] = {a[684], a[685]};
+    assign c[1093:1092] = a[365:364];
+    assign c[1095:1094] = a[1007:1006];
+    assign c[1097:1096] = {a[686], a[687]};
+    assign c[1099:1098] = a[367:366];
+    assign c[1101:1100] = a[763:762];
+    assign c[1103:1102] = a[1159:1158];
+    assign c[1105:1104] = a[1085:1084];
+    assign c[1107:1106] = a[765:764];
+    assign c[1109:1108] = a[1161:1160];
+    assign c[1111:1110] = a[1087:1086];
+    assign c[1113:1112] = a[767:766];
+    assign c[1115:1114] = a[1163:1162];
+    assign c[1117:1116] = a[373:372];
+    assign c[1119:1118] = a[1015:1014];
+    assign c[1121:1120] = a[1165:1164];
+    assign c[1123:1122] = a[375:374];
+    assign c[1125:1124] = a[1017:1016];
+    assign c[1127:1126] = a[1167:1166];
+    assign c[1129:1128] = a[377:376];
+    assign c[1131:1130] = a[1019:1018];
+    assign c[1133:1132] = {a[698], a[699]};
+    assign c[1135:1134] = a[379:378];
+    assign c[1137:1136] = a[1021:1020];
+    assign c[1139:1138] = {a[700], a[701]};
+    assign c[1141:1140] = a[381:380];
+    assign c[1143:1142] = a[1023:1022];
+    assign c[1145:1144] = {a[702], a[703]};
+    assign c[1147:1146] = a[383:382];
+    assign c[1149:1148] = a[779:778];
+    assign c[1151:1150] = a[1175:1174];
+    assign c[1153:1152] = a[1101:1100];
+    assign c[1155:1154] = a[781:780];
+    assign c[1157:1156] = a[1177:1176];
+    assign c[1159:1158] = a[1103:1102];
+    assign c[1161:1160] = a[783:782];
+    assign c[1163:1162] = a[1179:1178];
+    assign c[1165:1164] = a[389:388];
+    assign c[1167:1166] = a[1031:1030];
+    assign c[1169:1168] = a[1181:1180];
+    assign c[1171:1170] = a[391:390];
+    assign c[1173:1172] = a[1033:1032];
+    assign c[1175:1174] = a[1183:1182];
+    assign c[1177:1176] = a[393:392];
+    assign c[1179:1178] = a[1035:1034];
+    assign c[1181:1180] = {a[714], a[715]};
+    assign c[1183:1182] = a[395:394];
+    assign c[1185:1184] = a[1037:1036];
+endmodule
+/* c == v2(a) */
+module v2(a, c);
+    input [1185:0] a;
+    output [1185:0] c;
+    assign c[1:0] = 0;
+    assign c[3:2] = 0;
+    assign c[5:4] = 0;
+    assign c[7:6] = 0;
+    assign c[9:8] = 0;
+    assign c[11:10] = 0;
+    assign c[13:12] = 0;
+    assign c[15:14] = 0;
+    assign c[17:16] = 0;
+    assign c[19:18] = 0;
+    assign c[21:20] = 0;
+    assign c[23:22] = 0;
+    assign c[25:24] = 0;
+    assign c[27:26] = 0;
+    assign c[29:28] = 0;
+    assign c[31:30] = 0;
+    assign c[33:32] = 0;
+    assign c[35:34] = 0;
+    assign c[37:36] = 0;
+    assign c[39:38] = 0;
+    assign c[41:40] = 0;
+    assign c[43:42] = 0;
+    assign c[45:44] = 0;
+    assign c[47:46] = 0;
+    assign c[49:48] = 0;
+    assign c[51:50] = 0;
+    assign c[53:52] = 0;
+    assign c[55:54] = 0;
+    assign c[57:56] = 0;
+    assign c[59:58] = 0;
+    assign c[61:60] = 0;
+    assign c[63:62] = 0;
+    assign c[65:64] = 0;
+    assign c[67:66] = 0;
+    assign c[69:68] = 0;
+    assign c[71:70] = 0;
+    assign c[73:72] = 0;
+    assign c[75:74] = 0;
+    assign c[77:76] = 0;
+    assign c[79:78] = 0;
+    assign c[81:80] = 0;
+    assign c[83:82] = 0;
+    assign c[85:84] = 0;
+    assign c[87:86] = 0;
+    assign c[89:88] = 0;
+    assign c[91:90] = 0;
+    assign c[93:92] = 0;
+    assign c[95:94] = 0;
+    assign c[97:96] = 0;
+    assign c[99:98] = 0;
+    assign c[101:100] = 0;
+    assign c[103:102] = 0;
+    assign c[105:104] = 0;
+    assign c[107:106] = 0;
+    assign c[109:108] = 0;
+    assign c[111:110] = 0;
+    assign c[113:112] = 0;
+    assign c[115:114] = 0;
+    assign c[117:116] = 0;
+    assign c[119:118] = 0;
+    assign c[121:120] = 0;
+    assign c[123:122] = 0;
+    assign c[125:124] = 0;
+    assign c[127:126] = 0;
+    assign c[129:128] = 0;
+    assign c[131:130] = 0;
+    assign c[133:132] = 0;
+    assign c[135:134] = 0;
+    assign c[137:136] = 0;
+    assign c[139:138] = 0;
+    assign c[141:140] = 0;
+    assign c[143:142] = 0;
+    assign c[145:144] = 0;
+    assign c[147:146] = 0;
+    assign c[149:148] = 0;
+    assign c[151:150] = 0;
+    assign c[153:152] = 0;
+    assign c[155:154] = 0;
+    assign c[157:156] = 0;
+    assign c[159:158] = 0;
+    assign c[161:160] = 0;
+    assign c[163:162] = 0;
+    assign c[165:164] = 0;
+    assign c[167:166] = 0;
+    assign c[169:168] = 0;
+    assign c[171:170] = 0;
+    assign c[173:172] = 0;
+    assign c[175:174] = 0;
+    assign c[177:176] = 0;
+    assign c[179:178] = 0;
+    assign c[181:180] = 0;
+    assign c[183:182] = 0;
+    assign c[185:184] = 0;
+    assign c[187:186] = 0;
+    assign c[189:188] = 0;
+    assign c[191:190] = 0;
+    assign c[193:192] = 0;
+    assign c[195:194] = 0;
+    assign c[197:196] = 0;
+    assign c[199:198] = 0;
+    assign c[201:200] = 0;
+    assign c[203:202] = 0;
+    assign c[205:204] = 0;
+    assign c[207:206] = 0;
+    assign c[209:208] = 0;
+    assign c[211:210] = 0;
+    assign c[213:212] = 0;
+    assign c[215:214] = 0;
+    assign c[217:216] = 0;
+    assign c[219:218] = 0;
+    assign c[221:220] = 0;
+    assign c[223:222] = 0;
+    assign c[225:224] = 0;
+    assign c[227:226] = 0;
+    assign c[229:228] = {a[1038], a[1039]};
+    assign c[231:230] = 0;
+    assign c[233:232] = 0;
+    assign c[235:234] = a[79:78];
+    assign c[237:236] = 0;
+    assign c[239:238] = 0;
+    assign c[241:240] = a[797:796];
+    assign c[243:242] = 0;
+    assign c[245:244] = 0;
+    assign c[247:246] = a[799:798];
+    assign c[249:248] = 0;
+    assign c[251:250] = 0;
+    assign c[253:252] = {a[1046], a[1047]};
+    assign c[255:254] = 0;
+    assign c[257:256] = 0;
+    assign c[259:258] = {a[1048], a[1049]};
+    assign c[261:260] = 0;
+    assign c[263:262] = 0;
+    assign c[265:264] = {a[1050], a[1051]};
+    assign c[267:266] = 0;
+    assign c[269:268] = 0;
+    assign c[271:270] = {a[1052], a[1053]};
+    assign c[273:272] = 0;
+    assign c[275:274] = 0;
+    assign c[277:276] = {a[1054], a[1055]};
+    assign c[279:278] = 0;
+    assign c[281:280] = 0;
+    assign c[283:282] = a[95:94];
+    assign c[285:284] = 0;
+    assign c[287:286] = 0;
+    assign c[289:288] = a[813:812];
+    assign c[291:290] = 0;
+    assign c[293:292] = 0;
+    assign c[295:294] = a[815:814];
+    assign c[297:296] = 0;
+    assign c[299:298] = 0;
+    assign c[301:300] = {a[1062], a[1063]};
+    assign c[303:302] = 0;
+    assign c[305:304] = 0;
+    assign c[307:306] = {a[1064], a[1065]};
+    assign c[309:308] = 0;
+    assign c[311:310] = 0;
+    assign c[313:312] = {a[1066], a[1067]};
+    assign c[315:314] = 0;
+    assign c[317:316] = 0;
+    assign c[319:318] = {a[1068], a[1069]};
+    assign c[321:320] = 0;
+    assign c[323:322] = 0;
+    assign c[325:324] = {a[1070], a[1071]};
+    assign c[327:326] = 0;
+    assign c[329:328] = 0;
+    assign c[331:330] = a[111:110];
+    assign c[333:332] = 0;
+    assign c[335:334] = 0;
+    assign c[337:336] = a[829:828];
+    assign c[339:338] = 0;
+    assign c[341:340] = 0;
+    assign c[343:342] = a[831:830];
+    assign c[345:344] = 0;
+    assign c[347:346] = 0;
+    assign c[349:348] = {a[1078], a[1079]};
+    assign c[351:350] = 0;
+    assign c[353:352] = 0;
+    assign c[355:354] = {a[1080], a[1081]};
+    assign c[357:356] = 0;
+    assign c[359:358] = 0;
+    assign c[361:360] = {a[1082], a[1083]};
+    assign c[363:362] = 0;
+    assign c[365:364] = 0;
+    assign c[367:366] = {a[1084], a[1085]};
+    assign c[369:368] = 0;
+    assign c[371:370] = 0;
+    assign c[373:372] = {a[1086], a[1087]};
+    assign c[375:374] = 0;
+    assign c[377:376] = 0;
+    assign c[379:378] = a[127:126];
+    assign c[381:380] = 0;
+    assign c[383:382] = 0;
+    assign c[385:384] = a[845:844];
+    assign c[387:386] = 0;
+    assign c[389:388] = 0;
+    assign c[391:390] = a[847:846];
+    assign c[393:392] = 0;
+    assign c[395:394] = 0;
+    assign c[397:396] = {a[1094], a[1095]};
+    assign c[399:398] = 0;
+    assign c[401:400] = 0;
+    assign c[403:402] = {a[1096], a[1097]};
+    assign c[405:404] = 0;
+    assign c[407:406] = 0;
+    assign c[409:408] = {a[1098], a[1099]};
+    assign c[411:410] = 0;
+    assign c[413:412] = 0;
+    assign c[415:414] = {a[1100], a[1101]};
+    assign c[417:416] = 0;
+    assign c[419:418] = 0;
+    assign c[421:420] = {a[1102], a[1103]};
+    assign c[423:422] = 0;
+    assign c[425:424] = 0;
+    assign c[427:426] = a[143:142];
+    assign c[429:428] = 0;
+    assign c[431:430] = 0;
+    assign c[433:432] = a[861:860];
+    assign c[435:434] = 0;
+    assign c[437:436] = 0;
+    assign c[439:438] = a[863:862];
+    assign c[441:440] = 0;
+    assign c[443:442] = 0;
+    assign c[445:444] = {a[1110], a[1111]};
+    assign c[447:446] = 0;
+    assign c[449:448] = 0;
+    assign c[451:450] = {a[1112], a[1113]};
+    assign c[453:452] = 0;
+    assign c[455:454] = 0;
+    assign c[457:456] = {a[1114], a[1115]};
+    assign c[459:458] = 0;
+    assign c[461:460] = 0;
+    assign c[463:462] = {a[1116], a[1117]};
+    assign c[465:464] = 0;
+    assign c[467:466] = 0;
+    assign c[469:468] = {a[1118], a[1119]};
+    assign c[471:470] = 0;
+    assign c[473:472] = 0;
+    assign c[475:474] = a[159:158];
+    assign c[477:476] = 0;
+    assign c[479:478] = 0;
+    assign c[481:480] = a[877:876];
+    assign c[483:482] = 0;
+    assign c[485:484] = 0;
+    assign c[487:486] = a[879:878];
+    assign c[489:488] = 0;
+    assign c[491:490] = 0;
+    assign c[493:492] = {a[1126], a[1127]};
+    assign c[495:494] = 0;
+    assign c[497:496] = 0;
+    assign c[499:498] = {a[1128], a[1129]};
+    assign c[501:500] = 0;
+    assign c[503:502] = 0;
+    assign c[505:504] = {a[1130], a[1131]};
+    assign c[507:506] = 0;
+    assign c[509:508] = 0;
+    assign c[511:510] = {a[1132], a[1133]};
+    assign c[513:512] = 0;
+    assign c[515:514] = 0;
+    assign c[517:516] = {a[1134], a[1135]};
+    assign c[519:518] = 0;
+    assign c[521:520] = 0;
+    assign c[523:522] = a[175:174];
+    assign c[525:524] = 0;
+    assign c[527:526] = 0;
+    assign c[529:528] = a[893:892];
+    assign c[531:530] = 0;
+    assign c[533:532] = 0;
+    assign c[535:534] = a[895:894];
+    assign c[537:536] = 0;
+    assign c[539:538] = 0;
+    assign c[541:540] = {a[1142], a[1143]};
+    assign c[543:542] = 0;
+    assign c[545:544] = 0;
+    assign c[547:546] = {a[1144], a[1145]};
+    assign c[549:548] = 0;
+    assign c[551:550] = 0;
+    assign c[553:552] = {a[1146], a[1147]};
+    assign c[555:554] = 0;
+    assign c[557:556] = 0;
+    assign c[559:558] = {a[1148], a[1149]};
+    assign c[561:560] = 0;
+    assign c[563:562] = 0;
+    assign c[565:564] = {a[1150], a[1151]};
+    assign c[567:566] = 0;
+    assign c[569:568] = 0;
+    assign c[571:570] = a[191:190];
+    assign c[573:572] = 0;
+    assign c[575:574] = 0;
+    assign c[577:576] = a[909:908];
+    assign c[579:578] = 0;
+    assign c[581:580] = 0;
+    assign c[583:582] = a[911:910];
+    assign c[585:584] = 0;
+    assign c[587:586] = 0;
+    assign c[589:588] = {a[1158], a[1159]};
+    assign c[591:590] = 0;
+    assign c[593:592] = 0;
+    assign c[595:594] = {a[1160], a[1161]};
+    assign c[597:596] = 0;
+    assign c[599:598] = 0;
+    assign c[601:600] = {a[1162], a[1163]};
+    assign c[603:602] = 0;
+    assign c[605:604] = 0;
+    assign c[607:606] = {a[1164], a[1165]};
+    assign c[609:608] = 0;
+    assign c[611:610] = 0;
+    assign c[613:612] = {a[1166], a[1167]};
+    assign c[615:614] = 0;
+    assign c[617:616] = 0;
+    assign c[619:618] = a[207:206];
+    assign c[621:620] = 0;
+    assign c[623:622] = 0;
+    assign c[625:624] = a[925:924];
+    assign c[627:626] = 0;
+    assign c[629:628] = 0;
+    assign c[631:630] = a[927:926];
+    assign c[633:632] = 0;
+    assign c[635:634] = 0;
+    assign c[637:636] = {a[1174], a[1175]};
+    assign c[639:638] = 0;
+    assign c[641:640] = 0;
+    assign c[643:642] = {a[1176], a[1177]};
+    assign c[645:644] = 0;
+    assign c[647:646] = 0;
+    assign c[649:648] = {a[1178], a[1179]};
+    assign c[651:650] = 0;
+    assign c[653:652] = 0;
+    assign c[655:654] = {a[1180], a[1181]};
+    assign c[657:656] = 0;
+    assign c[659:658] = 0;
+    assign c[661:660] = {a[1182], a[1183]};
+    assign c[663:662] = 0;
+    assign c[665:664] = 0;
+    assign c[667:666] = a[223:222];
+    assign c[669:668] = 0;
+    assign c[671:670] = 0;
+    assign c[673:672] = 0;
+    assign c[675:674] = 0;
+    assign c[677:676] = 0;
+    assign c[679:678] = 0;
+    assign c[681:680] = 0;
+    assign c[683:682] = 0;
+    assign c[685:684] = 0;
+    assign c[687:686] = 0;
+    assign c[689:688] = 0;
+    assign c[691:690] = 0;
+    assign c[693:692] = 0;
+    assign c[695:694] = 0;
+    assign c[697:696] = 0;
+    assign c[699:698] = 0;
+    assign c[701:700] = 0;
+    assign c[703:702] = 0;
+    assign c[705:704] = 0;
+    assign c[707:706] = 0;
+    assign c[709:708] = 0;
+    assign c[711:710] = 0;
+    assign c[713:712] = 0;
+    assign c[715:714] = 0;
+    assign c[717:716] = 0;
+    assign c[719:718] = 0;
+    assign c[721:720] = 0;
+    assign c[723:722] = 0;
+    assign c[725:724] = 0;
+    assign c[727:726] = 0;
+    assign c[729:728] = 0;
+    assign c[731:730] = 0;
+    assign c[733:732] = 0;
+    assign c[735:734] = 0;
+    assign c[737:736] = 0;
+    assign c[739:738] = 0;
+    assign c[741:740] = 0;
+    assign c[743:742] = 0;
+    assign c[745:744] = 0;
+    assign c[747:746] = 0;
+    assign c[749:748] = 0;
+    assign c[751:750] = 0;
+    assign c[753:752] = 0;
+    assign c[755:754] = 0;
+    assign c[757:756] = 0;
+    assign c[759:758] = 0;
+    assign c[761:760] = 0;
+    assign c[763:762] = 0;
+    assign c[765:764] = 0;
+    assign c[767:766] = 0;
+    assign c[769:768] = 0;
+    assign c[771:770] = 0;
+    assign c[773:772] = 0;
+    assign c[775:774] = 0;
+    assign c[777:776] = 0;
+    assign c[779:778] = 0;
+    assign c[781:780] = 0;
+    assign c[783:782] = 0;
+    assign c[785:784] = 0;
+    assign c[787:786] = 0;
+    assign c[789:788] = 0;
+    assign c[791:790] = 0;
+    assign c[793:792] = 0;
+    assign c[795:794] = 0;
+    assign c[797:796] = 0;
+    assign c[799:798] = 0;
+    assign c[801:800] = 0;
+    assign c[803:802] = 0;
+    assign c[805:804] = 0;
+    assign c[807:806] = 0;
+    assign c[809:808] = 0;
+    assign c[811:810] = 0;
+    assign c[813:812] = 0;
+    assign c[815:814] = 0;
+    assign c[817:816] = 0;
+    assign c[819:818] = 0;
+    assign c[821:820] = 0;
+    assign c[823:822] = 0;
+    assign c[825:824] = 0;
+    assign c[827:826] = 0;
+    assign c[829:828] = 0;
+    assign c[831:830] = 0;
+    assign c[833:832] = 0;
+    assign c[835:834] = 0;
+    assign c[837:836] = 0;
+    assign c[839:838] = 0;
+    assign c[841:840] = 0;
+    assign c[843:842] = 0;
+    assign c[845:844] = 0;
+    assign c[847:846] = 0;
+    assign c[849:848] = 0;
+    assign c[851:850] = 0;
+    assign c[853:852] = 0;
+    assign c[855:854] = 0;
+    assign c[857:856] = 0;
+    assign c[859:858] = 0;
+    assign c[861:860] = 0;
+    assign c[863:862] = 0;
+    assign c[865:864] = 0;
+    assign c[867:866] = 0;
+    assign c[869:868] = 0;
+    assign c[871:870] = 0;
+    assign c[873:872] = 0;
+    assign c[875:874] = 0;
+    assign c[877:876] = 0;
+    assign c[879:878] = 0;
+    assign c[881:880] = 0;
+    assign c[883:882] = 0;
+    assign c[885:884] = 0;
+    assign c[887:886] = 0;
+    assign c[889:888] = 0;
+    assign c[891:890] = 0;
+    assign c[893:892] = 0;
+    assign c[895:894] = 0;
+    assign c[897:896] = 0;
+    assign c[899:898] = 0;
+    assign c[901:900] = 0;
+    assign c[903:902] = 0;
+    assign c[905:904] = 0;
+    assign c[907:906] = 0;
+    assign c[909:908] = 0;
+    assign c[911:910] = 0;
+    assign c[913:912] = 0;
+    assign c[915:914] = 0;
+    assign c[917:916] = 0;
+    assign c[919:918] = 0;
+    assign c[921:920] = 0;
+    assign c[923:922] = 0;
+    assign c[925:924] = 0;
+    assign c[927:926] = 0;
+    assign c[929:928] = 0;
+    assign c[931:930] = 0;
+    assign c[933:932] = 0;
+    assign c[935:934] = 0;
+    assign c[937:936] = 0;
+    assign c[939:938] = 0;
+    assign c[941:940] = 0;
+    assign c[943:942] = 0;
+    assign c[945:944] = 0;
+    assign c[947:946] = 0;
+    assign c[949:948] = 0;
+    assign c[951:950] = 0;
+    assign c[953:952] = 0;
+    assign c[955:954] = 0;
+    assign c[957:956] = 0;
+    assign c[959:958] = 0;
+    assign c[961:960] = 0;
+    assign c[963:962] = 0;
+    assign c[965:964] = 0;
+    assign c[967:966] = 0;
+    assign c[969:968] = 0;
+    assign c[971:970] = 0;
+    assign c[973:972] = 0;
+    assign c[975:974] = 0;
+    assign c[977:976] = 0;
+    assign c[979:978] = 0;
+    assign c[981:980] = 0;
+    assign c[983:982] = 0;
+    assign c[985:984] = 0;
+    assign c[987:986] = 0;
+    assign c[989:988] = 0;
+    assign c[991:990] = 0;
+    assign c[993:992] = 0;
+    assign c[995:994] = 0;
+    assign c[997:996] = 0;
+    assign c[999:998] = 0;
+    assign c[1001:1000] = 0;
+    assign c[1003:1002] = 0;
+    assign c[1005:1004] = 0;
+    assign c[1007:1006] = 0;
+    assign c[1009:1008] = 0;
+    assign c[1011:1010] = 0;
+    assign c[1013:1012] = 0;
+    assign c[1015:1014] = 0;
+    assign c[1017:1016] = 0;
+    assign c[1019:1018] = 0;
+    assign c[1021:1020] = 0;
+    assign c[1023:1022] = 0;
+    assign c[1025:1024] = 0;
+    assign c[1027:1026] = 0;
+    assign c[1029:1028] = 0;
+    assign c[1031:1030] = 0;
+    assign c[1033:1032] = 0;
+    assign c[1035:1034] = 0;
+    assign c[1037:1036] = 0;
+    assign c[1039:1038] = 0;
+    assign c[1041:1040] = 0;
+    assign c[1043:1042] = 0;
+    assign c[1045:1044] = 0;
+    assign c[1047:1046] = 0;
+    assign c[1049:1048] = 0;
+    assign c[1051:1050] = 0;
+    assign c[1053:1052] = 0;
+    assign c[1055:1054] = 0;
+    assign c[1057:1056] = 0;
+    assign c[1059:1058] = 0;
+    assign c[1061:1060] = 0;
+    assign c[1063:1062] = 0;
+    assign c[1065:1064] = 0;
+    assign c[1067:1066] = 0;
+    assign c[1069:1068] = 0;
+    assign c[1071:1070] = 0;
+    assign c[1073:1072] = 0;
+    assign c[1075:1074] = 0;
+    assign c[1077:1076] = 0;
+    assign c[1079:1078] = 0;
+    assign c[1081:1080] = 0;
+    assign c[1083:1082] = 0;
+    assign c[1085:1084] = 0;
+    assign c[1087:1086] = 0;
+    assign c[1089:1088] = 0;
+    assign c[1091:1090] = 0;
+    assign c[1093:1092] = 0;
+    assign c[1095:1094] = 0;
+    assign c[1097:1096] = 0;
+    assign c[1099:1098] = 0;
+    assign c[1101:1100] = 0;
+    assign c[1103:1102] = 0;
+    assign c[1105:1104] = 0;
+    assign c[1107:1106] = 0;
+    assign c[1109:1108] = 0;
+    assign c[1111:1110] = 0;
+    assign c[1113:1112] = 0;
+    assign c[1115:1114] = 0;
+    assign c[1117:1116] = 0;
+    assign c[1119:1118] = 0;
+    assign c[1121:1120] = 0;
+    assign c[1123:1122] = 0;
+    assign c[1125:1124] = 0;
+    assign c[1127:1126] = 0;
+    assign c[1129:1128] = 0;
+    assign c[1131:1130] = 0;
+    assign c[1133:1132] = 0;
+    assign c[1135:1134] = 0;
+    assign c[1137:1136] = 0;
+    assign c[1139:1138] = 0;
+    assign c[1141:1140] = 0;
+    assign c[1143:1142] = 0;
+    assign c[1145:1144] = 0;
+    assign c[1147:1146] = 0;
+    assign c[1149:1148] = 0;
+    assign c[1151:1150] = 0;
+    assign c[1153:1152] = 0;
+    assign c[1155:1154] = 0;
+    assign c[1157:1156] = 0;
+    assign c[1159:1158] = 0;
+    assign c[1161:1160] = 0;
+    assign c[1163:1162] = 0;
+    assign c[1165:1164] = 0;
+    assign c[1167:1166] = 0;
+    assign c[1169:1168] = 0;
+    assign c[1171:1170] = 0;
+    assign c[1173:1172] = 0;
+    assign c[1175:1174] = 0;
+    assign c[1177:1176] = 0;
+    assign c[1179:1178] = 0;
+    assign c[1181:1180] = 0;
+    assign c[1183:1182] = 0;
+    assign c[1185:1184] = 0;
+endmodule
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+`define M     593         // M is the degree of the irreducible polynomial
+`define WIDTH (2*`M-1)    // width for a GF(3^M) element
+`define WIDTH_D0 1187
+
+module tiny(clk, reset, sel, addr, w, data, out, done);
+    input clk, reset;
+    input sel;
+    input [5:0] addr;
+    input w;
+    input [`WIDTH_D0:0] data;
+    output [`WIDTH_D0:0] out;
+    output done;
+
+    /* for FSM */
+    wire [5:0] fsm_addr;
+    /* for RAM */
+    wire [5:0] ram_a_addr, ram_b_addr;
+    wire [`WIDTH_D0:0] ram_b_data_in;
+    wire ram_a_w, ram_b_w;
+    wire [`WIDTH_D0:0] ram_a_data_out, ram_b_data_out;
+    /* for const */
+    wire [`WIDTH_D0:0] const0_out, const1_out;
+    wire const0_effective, const1_effective;
+    /* for muxer */
+    wire [`WIDTH_D0:0] muxer0_out, muxer1_out;
+    /* for ROM */
+    wire [8:0] rom_addr;
+    wire [28:0] rom_q;
+    /* for PE */
+    wire [10:0] pe_ctrl;
+    
+    assign out = ram_a_data_out;
+    
+    select 
+        select0 (sel, addr, fsm_addr, w, ram_a_addr, ram_a_w);
+    rom
+        rom0 (clk, rom_addr, rom_q);
+    FSM
+        fsm0 (clk, reset, rom_addr, rom_q, fsm_addr, ram_b_addr, ram_b_w, pe_ctrl, done);
+    const_
+        const0 (clk, ram_a_addr, const0_out, const0_effective),
+        const1 (clk, ram_b_addr, const1_out, const1_effective);
+    ram
+        ram0 (clk, ram_a_w, ram_a_addr, data, ram_a_data_out, ram_b_w, ram_b_addr[5:0], ram_b_data_in, ram_b_data_out);
+    muxer
+        muxer0 (ram_a_data_out, const0_out, const0_effective, muxer0_out),
+        muxer1 (ram_b_data_out, const1_out, const1_effective, muxer1_out);
+    PE
+        pe0 (clk, reset, pe_ctrl, muxer1_out, muxer0_out[`WIDTH:0], muxer0_out[`WIDTH:0], ram_b_data_in[`WIDTH:0]);
+    
+    assign ram_b_data_in[`WIDTH_D0:`WIDTH+1] = 0;
+endmodule
+
+module select(sel, addr_in, addr_fsm_in, w_in, addr_out, w_out);
+    input sel;
+    input [5:0] addr_in;
+    input [5:0] addr_fsm_in;
+    input w_in;
+    output [5:0] addr_out;
+    output w_out;
+    
+    assign addr_out = sel ? addr_in : addr_fsm_in;
+    assign w_out = sel & w_in;
+endmodule
+
+module muxer(from_ram, from_const, const_effective, out);
+    input [`WIDTH_D0:0] from_ram, from_const;
+    input const_effective;
+    output [`WIDTH_D0:0] out;
+    
+    assign out = const_effective ? from_const : from_ram;
+endmodule
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+`timescale 1ns / 1ps
+`define P 20 // clock period 
+`define M     503         // M is the degree of the irreducible polynomial
+`define WIDTH (2*`M-1)    // width for a GF(3^M) element
+`define WIDTH_D0 (1008-1)
+
+module test_pairing;
+
+\t// Inputs
+\treg clk;
+\treg reset;
+\treg sel;
+\treg [5:0] addr;
+\treg w;
+    reg update;
+    reg ready;
+    reg i;
+
+\t// Outputs
+\twire done;
+    wire o;
+
+    // Buffers
+\treg [`WIDTH_D0:0] out;
+
+\t// Instantiate the Unit Under Test (UUT)
+\tpairing uut (
+        .clk(clk), 
+        .reset(reset), 
+        .sel(sel), 
+        .addr(addr), 
+        .w(w), 
+        .update(update),
+        .ready(ready),
+        .i(i),
+        .o(o),
+        .done(done)
+\t);
+
+\tinitial begin
+\t\t// Initialize Inputs
+\t\tclk = 0;
+\t\treset = 0;
+\t\tsel = 0;
+\t\taddr = 0;
+\t\tw = 0;
+        update = 0;
+        ready = 0;
+        i = 0;
+        out = 0;
+
+\t\t// Wait 100 ns for global reset to finish
+\t\t#100;
+        
+\t\t// Add stimulus here
+        /* keep FSM silent */
+        reset = 1;
+            /* init xp, yp, xq, yq */
+            write(3, 1006\'h0412500224298894260864922a0084a98a0454681a18164a08268062495a596469659050406960a191646a024a0aa26688240682059585a258a89664946584924a9a8a1a8145400889899a6a2601184a2596419a04161969169128281805669a9509145852901691690a8506a9145224850109a150110629229564901a00);
+            write(5, 1006\'h161181618265a480158208a088a01aa89a424001019a90912969511008944a806119a1429520105654089861546a912295590518a90842962660a665899405681aa510844840524240145a0295855920091640a66a5a044568510469454a18a06218922914510004a25409a81a5800456055996128a965624116289904aa);
+            write(6, 1006\'h0412500224298894260864922a0084a98a0454681a18164a08268062495a596469659050406960a191646a024a0aa26688240682059585a258a89664946584924a9a8a1a8145400889899a6a2601184a2596419a04161969169128281805669a9509145852901691690a8506a9145224850109a150110629229564901a00);
+            write(7, 1006\'h161181618265a480158208a088a01aa89a424001019a90912969511008944a806119a1429520105654089861546a912295590518a90842962660a665899405681aa510844840524240145a0295855920091640a66a5a044568510469454a18a06218922914510004a25409a81a5800456055996128a965624116289904aa);
+            /* read back. uncomment me if error happens */
+            /* read(3);
+            $display(""xp = %h"", out);
+            read(5);
+            $display(""yp = %h"", out);
+            read(6);
+            $display(""xq = %h"", out);
+            read(7);
+            $display(""yq = %h"", out);*/
+        reset = 0;
+        
+        sel = 0; w = 0;
+        @(posedge done);
+        @(negedge clk);
+            read(9);
+            check(1006\'h2965a664a44a85426524a19821aa12a42605258540a056525248149a96061560451a6a95861496a8140985a8902955951552696a425948159a2141a0aaa5840442851218546a49a2a2496658644656a9a6162a5098a025645151aa668902aaa102a0805900488980545120462896204252584282868449488a00884995a9);
+            read(10);
+            check(1006\'h244151402864a58144a0509a26121148024224a299a4062a248944801589895a04a8a681a4245492a5aa5958901a142120515582941220529512012554699982594528256086220a55641a5a212511aa50a0a4a198200560a628994925551249659028459a8a24688191044a08529064119949a112564a52082068858890);
+            read(11);
+            check(1006\'h180645a168488aa651260a226a124a66080299922a8595404428610808262992a22682905a55625665824505a609882a88422a886296551a6221a29a16aa11141a12280942aa84094946860205964a26669684569054810a914124a086212a5a5821440119015a98844101854a9951141981221169224a1599a11914a504);
+            read(12);
+            check(1006\'h18a6911a415584242209a6a52629464160400a0a45554552866a9a20a8520a551856814024118140a144a151604449609aa24085a609a2a0851285445a96602a2461212641204a591a66a5604211004882191912920862a9860a861a88a005516611622a44880a48690412292244615156004952521664a84a5961510225);
+            read(13);
+            check(1006\'h250869062a008a1882940945a20441680111009595094282260a95488aaa4588262641912aa64a29a8526408451940619612014212441090209588888a004002462206a8294a158809258852650a15226a99808952201191614814166198a52a8151454968a288295994286919811691aa21048661a5288402182a558215);
+            read(14);
+            check(1006\'h016641111896469064656661124a160226a89485469954a6a5406aa28590655a018922965688045984585a61888165085289a61a051258a59459210842108082566966664250991442a2941521806608610a52182256042680a4881900605a8459260a9824295244629865a6a62a18958a66955152404814065588150894);
+            $display(""Good"");
+        $finish;
+\tend
+
+    initial #100 forever #(`P/2) clk = ~clk;
+
+    task write;
+        input [5:0] adr;
+        input [`WIDTH_D0:0] dat;
+        integer j;
+        begin
+            sel = 1; 
+            w = 0;
+            addr = adr;
+            update = 1;
+            #`P;
+            update = 0;
+            ready = 1;
+            for(j=0;j<`WIDTH_D0+1;j=j+1)
+               begin
+               i = dat[j];
+               #`P;
+               end
+            ready = 0;
+            w = 1; #`P; w = 0;
+        end
+    endtask
+
+    task read;
+        input [5:0] adr;
+        integer j;
+        begin
+            sel = 1;
+            w = 0;
+            addr = adr;
+            #`P;
+            update = 1;
+            #`P;
+            update = 0;
+            out = 0;
+            ready = 1;
+            for(j=0;j<`WIDTH_D0+1;j=j+1)
+               begin
+               out = {o, out[`WIDTH_D0:1]};
+               #`P;
+               end
+        end
+    endtask
+    
+    task check;
+        input [`WIDTH_D0:0] wish;
+        begin
+            if (out !== wish) 
+                begin $display(""Error!""); $finish; end
+        end
+    endtask    
+endmodule
+
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+`timescale 1ns / 1ps
+`define P 20 // clock period
+
+module test_const;
+
+\t// Inputs
+    reg clk;
+\treg [5:0] addr;
+
+\t// Outputs
+\twire [1007:0] out;
+\twire effective;
+    reg [1007:0] w_out;
+    reg w_effective;
+    
+\t// Instantiate the Unit Under Test (UUT)
+\tconst_ uut (
+        .clk(clk),
+\t\t.addr(addr), 
+\t\t.out(out), 
+\t\t.effective(effective)
+\t);
+
+\tinitial begin
+\t\t// Initialize Inputs
+\t\taddr = 0; clk = 0;
+
+\t\t// Wait 100 ns for global reset to finish
+\t\t#100;
+        
+\t\t// Add stimulus here
+        @ (negedge clk);
+        addr = 1; w_out = 0; w_effective = 1;
+        #(`P); check;
+        addr = 2; w_out = 1;
+        #(`P); check;
+        addr = 4; w_out = {6\'b000101, 1002\'d0};
+        #(`P); check;
+        addr = 8; w_out = {6\'b001001, 1002\'d0};
+        #(`P); check;
+        addr = 16; w_out = {6\'b010101, 1002\'d0};
+        #(`P); check;
+        addr = 0; w_out = 0; w_effective = 0;
+        #(`P); check;
+        $display(""Good"");
+        $finish;
+\tend
+
+    initial #100 forever #(`P/2) clk = ~clk;
+
+    task check;
+      begin
+        if (out !== w_out || effective !== w_effective)
+            $display(""E %d %h %h"", addr, out, w_out);
+      end
+    endtask
+endmodule
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+`define M     593         // M is the degree of the irreducible polynomial
+`define WIDTH (2*`M-1)    // width for a GF(3^M) element
+`define WIDTH_D0 1187
+
+/*
+ * the module of constants
+ *
+ * addr  out  effective
+ *    1   0     1
+ *    2   1     1
+ *    4   +     1
+ *    8   -     1
+ *   16 cubic   1
+ * other  0     0
+ */
+module const_ (clk, addr, out, effective);
+    input clk;
+    input [5:0] addr;
+    output reg [`WIDTH_D0:0] out;
+    output reg effective; // active high if out is effective
+    
+    always @ (posedge clk)
+      begin
+         effective <= 1;
+         case (addr)
+            1:  out <= 0;
+            2:  out <= 1;
+            4:  out <= {6\'b000101, 1182\'d0};
+            8:  out <= {6\'b001001, 1182\'d0};
+            16: out <= {6\'b010101, 1182\'d0};
+            default: 
+               begin out <= 0; effective <= 0; end
+         endcase
+      end
+endmodule
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+`define M     503         // M is the degree of the irreducible polynomial
+`define WIDTH (2*`M-1)    // width for a GF(3^M) element
+`define WIDTH_D0 (1008-1)
+
+/*
+ * the module of constants
+ *
+ * addr  out  effective
+ *    1   0     1
+ *    2   1     1
+ *    4   +     1
+ *    8   -     1
+ *   16 cubic   1
+ * other  0     0
+ */
+module const_ (clk, addr, out, effective);
+    input clk;
+    input [5:0] addr;
+    output reg [`WIDTH_D0:0] out;
+    output reg effective; // active high if out is effective
+    
+    always @ (posedge clk)
+      begin
+         effective <= 1;
+         case (addr)
+            1:  out <= 0;
+            2:  out <= 1;
+            4:  out <= {6\'b000101, 1002\'d0};
+            8:  out <= {6\'b001001, 1002\'d0};
+            16: out <= {6\'b010101, 1002\'d0};
+            default: 
+               begin out <= 0; effective <= 0; end
+         endcase
+      end
+endmodule
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+`timescale 1ns / 1ps
+`define P 20 // clock period
+
+module test_fsm;
+
+\t// Inputs
+\treg clk;
+\treg reset;
+\treg [25:0] rom_q;
+
+\t// Outputs
+\twire [8:0] rom_addr;
+\twire [5:0] ram_a_addr;
+\twire [5:0] ram_b_addr;
+\twire ram_b_w;
+\twire [10:0] pe;
+\twire done;
+
+\t// Instantiate the Unit Under Test (UUT)
+\tFSM uut (
+\t\t.clk(clk), 
+\t\t.reset(reset), 
+\t\t.rom_addr(rom_addr), 
+\t\t.rom_q(rom_q), 
+\t\t.ram_a_addr(ram_a_addr), 
+\t\t.ram_b_addr(ram_b_addr), 
+\t\t.ram_b_w(ram_b_w), 
+\t\t.pe(pe), 
+\t\t.done(done)
+\t);
+
+\tinitial begin
+\t\t// Initialize Inputs
+\t\tclk = 0;
+\t\treset = 0;
+
+\t\t// Wait 100 ns for global reset to finish
+\t\t#100;
+        
+\t\t// Add stimulus here
+        #(`P/2); reset = 1; #(`P); reset = 0;
+        
+        @(posedge done);
+        $finish;
+\tend
+    
+    initial #100 forever #(`P/2) clk = ~clk;
+    
+    /* rom code format 
+     * wire [5:0] dest, src1, src2, times; wire [1:0] op;
+     * assign {dest, src1, op, times, src2} = rom_q;
+     */
+    parameter ADD=2\'d0, SUB=2\'d1, CUBIC=2\'d2, MULT=2\'d3;
+
+    always @ (posedge clk)
+        case(rom_addr)
+        0: rom_q <= {6\'d10, 6\'d11, ADD, 6\'d1, 6\'d12};
+        1: rom_q <= {6\'d20, 6\'d21, SUB, 6\'d1, 6\'d22};
+        2: rom_q <= {6\'d30, 6\'d31, CUBIC, 6\'d5, 6\'d32};
+        3: rom_q <= {6\'d40, 6\'d41, MULT, 6\'d33, 6\'d42};
+        default: rom_q <= 0;
+        endcase
+endmodule
+
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+`define M     593         // M is the degree of the irreducible polynomial
+`define WIDTH (2*`M-1)    // width for a GF(3^M) element
+`define WIDTH_D0 1187
+
+/* PE: processing element */
+module PE(clk, reset, ctrl, d0, d1, d2, out);
+    input clk;
+    input reset;
+    input [10:0] ctrl;
+    input [`WIDTH_D0:0] d0;
+    input [`WIDTH:0] d1, d2;
+    output [`WIDTH:0] out;
+    
+    reg [`WIDTH_D0:0] R0;
+    reg [`WIDTH:0] R1, R2, R3;
+    wire [1:0] e0, e1, e2; /* part of R0 */
+    wire [`WIDTH:0] ppg0, ppg1, ppg2, /* output of PPG */
+                    mx0, mx1, mx2, mx3, mx4, mx5, mx6, /* output of MUX */
+                    ad0, ad1, ad2, /* output of GF(3^m) adder */
+                    cu0, cu1, cu2, /* output of cubic */
+                    mo0, mo1, mo2, /* output of mod_p */
+                    t0, t1, t2;
+    wire c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10;
+    
+    assign {c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10} = ctrl;
+    assign mx0 = c0 ? d1 : ad2;
+    assign mx1 = c2 ? d2 : ad2;
+    always @ (posedge clk)
+        if(reset) R1 <= 0;
+        else if (c1) R1 <= mx0;
+    always @ (posedge clk)
+        if(reset) R2 <= 0;
+        else if (c3) R2 <= mx1;
+    always @ (posedge clk)
+        if(reset) R0 <= 0;
+        else if (c4) R0 <= d0;
+        else if (c5) R0 <= R0 << 6;
+    assign {e2,e1,e0} = R0[`WIDTH_D0:(`WIDTH_D0-5)];
+    PPG
+        ppg_0 (e0, R1, ppg0),
+        ppg_1 (e1, R2, ppg1),
+        ppg_2 (e2, R1, ppg2);
+    v0  v0_ (ppg0, cu0);
+    v1  v1_ (ppg1, cu1);
+    v2  v2_ (ppg2, cu2);
+    assign mx2 = c6 ? ppg0 : cu0;
+    assign mx3 = c6 ? ppg1 : cu1;
+    assign mx4 = c6 ? mo1 : cu2;
+    assign mx5 = c7 ? mo2 : R3;
+    mod_p
+        mod_p_0 (mx3, mo0),
+        mod_p_1 (ppg2, t0),
+        mod_p_2 (t0, mo1),
+        mod_p_3 (R3, t1),
+        mod_p_4 (t1, t2),
+        mod_p_5 (t2, mo2);
+    assign mx6 = c9 ? mo0 : mx3;
+    f3m_add
+        f3m_add_0 (mx2, mx6, ad0),
+        f3m_add_1 (mx4, c8 ? mx5 : 0, ad1),
+        f3m_add_2 (ad0, ad1, ad2);
+    always @ (posedge clk)
+        if (reset) R3 <= 0;
+        else if (c10) R3 <= ad2;
+        else R3 <= 0; /* change */
+    assign out = R3;
+endmodule
+
+// C = (x*B mod p(x))
+module mod_p(B, C);
+    input [`WIDTH:0] B;
+    output [`WIDTH:0] C;
+    wire [`WIDTH+2:0] A;
+    assign A = {B[`WIDTH:0], 2\'d0}; // A == B*x
+    wire [1:0] w0;
+    f3_mult m0 (A[1187:1186], 2\'d2, w0);
+    f3_sub s0 (A[1:0], w0, C[1:0]);
+    assign C[223:2] = A[223:2];
+    wire [1:0] w112;
+    f3_mult m112 (A[1187:1186], 2\'d1, w112);
+    f3_sub s112 (A[225:224], w112, C[225:224]);
+    assign C[1185:226] = A[1185:226];
+endmodule
+
+// PPG: partial product generator, C == A*d in GF(3^m)
+module PPG(d, A, C);
+    input [1:0] d;
+    input [`WIDTH:0] A;
+    output [`WIDTH:0] C;
+    genvar i;
+    generate
+        for (i=0; i < `M; i=i+1) 
+        begin: ppg0
+            f3_mult f3_mult_0 (d, A[2*i+1:2*i], C[2*i+1:2*i]);
+        end
+    endgenerate
+endmodule
+
+// f3m_add: C = A + B, in field F_{3^M}
+module f3m_add(A, B, C);
+    input [`WIDTH : 0] A, B;
+    output [`WIDTH : 0] C;
+    genvar i;
+    generate
+        for(i=0; i<`M; i=i+1) begin: aa
+            f3_add aa(A[(2*i+1) : 2*i], B[(2*i+1) : 2*i], C[(2*i+1) : 2*i]);
+        end
+    endgenerate
+endmodule
+
+// f3_add: C == A+B (mod 3)
+module f3_add(A, B, C);
+    input [1:0] A, B;
+    output [1:0] C;
+    wire a0, a1, b0, b1, c0, c1;
+    assign {a1, a0} = A;
+    assign {b1, b0} = B;
+    assign C = {c1, c0};
+    assign c0 = ( a0 & ~a1 & ~b0 & ~b1) |
+                (~a0 & ~a1 &  b0 & ~b1) |
+                (~a0 &  a1 & ~b0 &  b1) ;
+    assign c1 = (~a0 &  a1 & ~b0 & ~b1) |
+                ( a0 & ~a1 &  b0 & ~b1) |
+                (~a0 & ~a1 & ~b0 &  b1) ;
+endmodule
+
+// f3_sub: C == A-B (mod 3)
+module f3_sub(A, B, C);
+    input [1:0] A, B;
+    output [1:0] C;
+    f3_add a0(A, {B[0],B[1]}, C);
+endmodule
+
+// f3_mult: C = A*B (mod 3)
+module f3_mult(A, B, C); 
+    input [1:0] A;
+    input [1:0] B; 
+    output [1:0] C;
+    wire a0, a1, b0, b1;
+    assign {a1, a0} = A;
+    assign {b1, b0} = B;
+    assign C[0] = (~a1 & a0 & ~b1 & b0) | (a1 & ~a0 & b1 & ~b0);
+    assign C[1] = (~a1 & a0 & b1 & ~b0) | (a1 & ~a0 & ~b1 & b0);
+endmodule
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+`timescale 1ns / 1ps
+`define P 20
+
+module test_pe;
+
+\t// Inputs
+\treg clk;
+\treg reset;
+\treg [10:0] ctrl;
+\treg [197:0] d0;
+\treg [193:0] d1;
+\treg [193:0] d2;
+    reg [193:0] wish;
+
+\t// Outputs
+\twire [193:0] out;
+
+\t// Instantiate the Unit Under Test (UUT)
+\tPE uut (
+\t\t.clk(clk), 
+\t\t.reset(reset), 
+\t\t.ctrl(ctrl), 
+\t\t.d0(d0), 
+\t\t.d1(d1), 
+        .d2(d2),
+\t\t.out(out)
+\t);
+
+\tinitial begin
+\t\t// Initialize Inputs
+\t\tclk = 0;
+\t\treset = 0;
+\t\tctrl = 0;
+\t\td0 = 0;
+\t\td1 = 0;
+        d2 = 0;
+
+\t\t// Wait 100 ns for global reset to finish
+\t\t#100;
+        
+\t\t// Add stimulus here
+        // test mult
+        d0 = 194\'h15a25886512165251569195908560596a6695612620504191;
+        d1 = 194\'h159546442405a181195655549614540592955a15a26984015;
+        d2 = d1;
+        wish = 194\'h21019120440545215a1462a194a24a6019441081402410969;
+        
+        @(negedge clk);
+        reset=1;#`P reset=0;
+        ctrl=11\'b11111_000000; #`P;
+        ctrl=11\'b00000_111111; #(33*`P);
+        check;
+        
+        // test cubic
+        d0 = {6\'b10101, 192\'d0};
+        d1 = 194\'h0894286a45940549565566512aa04a15558406850485454a4;
+        d2 = d1;
+        wish = 194\'h1049480a48a0855a494855810160a90956659914560616652;
+        
+        @(negedge clk);
+        reset=1;#`P reset=0;
+        ctrl=11\'b11111_000000; #`P;
+        ctrl=1; #(33*`P);
+        check;
+        
+        // test add
+        d0 = {6\'b000101, 192\'d0};
+        d1 = 194\'h0994544a41588446516618a14691a545542521a4158868428;
+        d2 = 194\'h1901269451681914415481656104980811a5a555155546949;
+        wish = 194\'h16954a129284915a928a9916a4954141659a96092a11a2165;
+        
+        @(negedge clk);
+        reset=1;#`P reset=0;
+        ctrl=11\'b11111_000000; #`P;
+        ctrl=11\'b10001; #(33*`P);
+        check;
+
+        // test sub
+        d0 = {6\'b001001, 192\'d0};
+        d1 = 194\'h0994544a41588446516618a14691a545542521a4158868428;
+        d2 = 194\'h1901269451681914415481656104980811a5a555155546949;
+        wish = 194\'h209661a62020aa6210125a481599194946404852006625aa2;
+        
+        @(negedge clk);
+        reset=1;#`P reset=0;
+        ctrl=11\'b11111_000000; #`P;
+        ctrl=11\'b10001; #(33*`P);
+        check;
+
+        $display(""Good!"");
+        $finish;
+\tend
+
+    initial #100 forever #(`P/2) clk = ~clk;
+
+    task check;
+        begin
+          if (out !== wish)
+            begin $display(""E %h %h"", out, wish); $finish; end
+        end
+    endtask
+endmodule
+
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+`define M     503         // M is the degree of the irreducible polynomial
+`define WIDTH (2*`M-1)    // width for a GF(3^M) element
+`define WIDTH_D0 (1008-1)
+
+module tiny(clk, reset, sel, addr, w, data, out, done);
+    input clk, reset;
+    input sel;
+    input [5:0] addr;
+    input w;
+    input [`WIDTH_D0:0] data;
+    output [`WIDTH_D0:0] out;
+    output done;
+
+    /* for FSM */
+    wire [5:0] fsm_addr;
+    /* for RAM */
+    wire [5:0] ram_a_addr, ram_b_addr;
+    wire [`WIDTH_D0:0] ram_b_data_in;
+    wire ram_a_w, ram_b_w;
+    wire [`WIDTH_D0:0] ram_a_data_out, ram_b_data_out;
+    /* for const */
+    wire [`WIDTH_D0:0] const0_out, const1_out;
+    wire const0_effective, const1_effective;
+    /* for muxer */
+    wire [`WIDTH_D0:0] muxer0_out, muxer1_out;
+    /* for ROM */
+    wire [8:0] rom_addr;
+    wire [27:0] rom_q;
+    /* for PE */
+    wire [10:0] pe_ctrl;
+    
+    assign out = ram_a_data_out;
+    
+    select 
+        select0 (sel, addr, fsm_addr, w, ram_a_addr, ram_a_w);
+    rom
+        rom0 (clk, rom_addr, rom_q);
+    FSM
+        fsm0 (clk, reset, rom_addr, rom_q, fsm_addr, ram_b_addr, ram_b_w, pe_ctrl, done);
+    const_
+        const0 (clk, ram_a_addr, const0_out, const0_effective),
+        const1 (clk, ram_b_addr, const1_out, const1_effective);
+    ram
+        ram0 (clk, ram_a_w, ram_a_addr, data, ram_a_data_out, ram_b_w, ram_b_addr[5:0], ram_b_data_in, ram_b_data_out);
+    muxer
+        muxer0 (ram_a_data_out, const0_out, const0_effective, muxer0_out),
+        muxer1 (ram_b_data_out, const1_out, const1_effective, muxer1_out);
+    PE
+        pe0 (clk, reset, pe_ctrl, muxer1_out, muxer0_out[`WIDTH:0], muxer0_out[`WIDTH:0], ram_b_data_in[`WIDTH:0]);
+    
+    assign ram_b_data_in[`WIDTH_D0:`WIDTH+1] = 0;
+endmodule
+
+module select(sel, addr_in, addr_fsm_in, w_in, addr_out, w_out);
+    input sel;
+    input [5:0] addr_in;
+    input [5:0] addr_fsm_in;
+    input w_in;
+    output [5:0] addr_out;
+    output w_out;
+    
+    assign addr_out = sel ? addr_in : addr_fsm_in;
+    assign w_out = sel & w_in;
+endmodule
+
+module muxer(from_ram, from_const, const_effective, out);
+    input [`WIDTH_D0:0] from_ram, from_const;
+    input const_effective;
+    output [`WIDTH_D0:0] out;
+    
+    assign out = const_effective ? from_const : from_ram;
+endmodule
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+module rom (clk, addr, out);
+   input clk;
+   input [8:0] addr;
+   output reg [27:0] out;
+   
+   always @(posedge clk)
+      case (addr)
+         0: out <= 28\'hc30042;
+         1: out <= 28\'h1450045;
+         2: out <= 28\'h1868041;
+         3: out <= 28\'h1c78041;
+         4: out <= 28\'h30046;
+         5: out <= 28\'h580ea00;
+         6: out <= 28\'h5c08041;
+         7: out <= 28\'h5c5ea17;
+         8: out <= 28\'h605ea07;
+         9: out <= 28\'h658ea07;
+         10: out <= 28\'h3d74059;
+         11: out <= 28\'h3c5404f;
+         12: out <= 28\'h5d8ea05;
+         13: out <= 28\'h617ea00;
+         14: out <= 28\'h587ea16;
+         15: out <= 28\'h4580056;
+         16: out <= 28\'h4850041;
+         17: out <= 28\'h4c7ea00;
+         18: out <= 28\'h4d34057;
+         19: out <= 28\'h5014041;
+         20: out <= 28\'h5474041;
+         21: out <= 28\'hf8041;
+         22: out <= 28\'h5918041;
+         23: out <= 28\'h5d28041;
+         24: out <= 28\'h6138041;
+         25: out <= 28\'h6548041;
+         26: out <= 28\'h6958041;
+         27: out <= 28\'h3c00057;
+         28: out <= 28\'h3cf0059;
+         29: out <= 28\'h4560058;
+         30: out <= 28\'h451005a;
+         31: out <= 28\'h4510051;
+         32: out <= 28\'h4974059;
+         33: out <= 28\'h4da4058;
+         34: out <= 28\'h5190041;
+         35: out <= 28\'h55a005a;
+         36: out <= 28\'h1868081;
+         37: out <= 28\'h1864042;
+         38: out <= 28\'h1c78081;
+         39: out <= 28\'h1c70047;
+         40: out <= 28\'h30046;
+         41: out <= 28\'h5800040;
+         42: out <= 28\'h5c5ea07;
+         43: out <= 28\'h16ea00;
+         44: out <= 28\'h6000056;
+         45: out <= 28\'h6404056;
+         46: out <= 28\'h68f0054;
+         47: out <= 28\'h6da0052;
+         48: out <= 28\'h71a4052;
+         49: out <= 28\'h74f4054;
+         50: out <= 28\'h79d4053;
+         51: out <= 28\'h75d0053;
+         52: out <= 28\'h7d10055;
+         53: out <= 28\'h81f0053;
+         54: out <= 28\'h85f4053;
+         55: out <= 28\'h8970056;
+         56: out <= 28\'h5974056;
+         57: out <= 28\'h8d14055;
+         58: out <= 28\'h9230052;
+         59: out <= 28\'h8e34052;
+         60: out <= 28\'h9580057;
+         61: out <= 28\'h99b0060;
+         62: out <= 28\'h9c00062;
+         63: out <= 28\'ha1e0064;
+         64: out <= 28\'ha590057;
+         65: out <= 28\'ha9c0061;
+         66: out <= 28\'hac00056;
+         67: out <= 28\'hb1d0063;
+         68: out <= 28\'h618ea1b;
+         69: out <= 28\'h6e5ea26;
+         70: out <= 28\'h817ea20;
+         71: out <= 28\'h780ea1e;
+         72: out <= 28\'h967ea28;
+         73: out <= 28\'h8a2ea24;
+         74: out <= 28\'h659ea1c;
+         75: out <= 28\'h729ea2a;
+         76: out <= 28\'h5d7ea21;
+         77: out <= 28\'hea1d;
+         78: out <= 28\'h76bea2c;
+         79: out <= 28\'h596ea23;
+         80: out <= 28\'h8580065;
+         81: out <= 28\'h8e0005d;
+         82: out <= 28\'h9204057;
+         83: out <= 28\'h9994058;
+         84: out <= 28\'h5d70060;
+         85: out <= 28\'h5e24057;
+         86: out <= 28\'h5d70056;
+         87: out <= 28\'h6190058;
+         88: out <= 28\'h618405e;
+         89: out <= 28\'h6184040;
+         90: out <= 28\'h6634061;
+         91: out <= 28\'h659405e;
+         92: out <= 28\'h5990056;
+         93: out <= 28\'h6610063;
+         94: out <= 28\'h659405b;
+         95: out <= 28\'h6590062;
+         96: out <= 28\'h190040;
+         97: out <= 28\'h6640066;
+         98: out <= 28\'h7a44066;
+         99: out <= 28\'h79e005c;
+         100: out <= 28\'h79e405b;
+         101: out <= 28\'h8170058;
+         102: out <= 28\'h5d74058;
+         103: out <= 28\'h5d7005c;
+         104: out <= 28\'h5d7005b;
+         105: out <= 28\'h5d74065;
+         106: out <= 28\'h5d7405d;
+         107: out <= 28\'h3d64052;
+         108: out <= 28\'h4404053;
+         109: out <= 28\'h194052;
+         110: out <= 28\'h4054;
+         111: out <= 28\'h59e4053;
+         112: out <= 28\'h5964055;
+         113: out <= 28\'h520405a;
+         114: out <= 28\'h557405f;
+         115: out <= 28\'h4804041;
+         116: out <= 28\'h4d64041;
+         117: out <= 28\'h24f8041;
+         118: out <= 28\'hf0052;
+         119: out <= 28\'h54;
+         120: out <= 28\'h58fea0f;
+         121: out <= 28\'h5cfea12;
+         122: out <= 28\'h612ea14;
+         123: out <= 28\'h654ea14;
+         124: out <= 28\'hea00;
+         125: out <= 28\'h5d70058;
+         126: out <= 28\'h6164058;
+         127: out <= 28\'h6594057;
+         128: out <= 28\'h57;
+         129: out <= 28\'h4056;
+         130: out <= 28\'h5910053;
+         131: out <= 28\'h5960055;
+         132: out <= 28\'h5d1ea11;
+         133: out <= 28\'h691ea13;
+         134: out <= 28\'h6d3ea15;
+         135: out <= 28\'h715ea15;
+         136: out <= 28\'h596ea16;
+         137: out <= 28\'h69a005b;
+         138: out <= 28\'h6d7405b;
+         139: out <= 28\'h71c405a;
+         140: out <= 28\'h596005a;
+         141: out <= 28\'h5964057;
+         142: out <= 28\'h5cf0052;
+         143: out <= 28\'h68f0054;
+         144: out <= 28\'h7520054;
+         145: out <= 28\'h7910053;
+         146: out <= 28\'h7d10055;
+         147: out <= 28\'h8130055;
+         148: out <= 28\'h84fea11;
+         149: out <= 28\'h892ea13;
+         150: out <= 28\'h8d4ea15;
+         151: out <= 28\'h5d7ea1e;
+         152: out <= 28\'h69aea1f;
+         153: out <= 28\'h75dea20;
+         154: out <= 28\'h7a14062;
+         155: out <= 28\'h7de4063;
+         156: out <= 28\'h7df005d;
+         157: out <= 28\'h5d7405e;
+         158: out <= 28\'h5d7005d;
+         159: out <= 28\'h69a405e;
+         160: out <= 28\'h758405b;
+         161: out <= 28\'h799405c;
+         162: out <= 28\'h8004056;
+         163: out <= 28\'h618005b;
+         164: out <= 28\'h659005c;
+         165: out <= 28\'h56;
+         166: out <= 28\'h5980059;
+         167: out <= 28\'h6d84040;
+         168: out <= 28\'h7194058;
+         169: out <= 28\'h840405c;
+         170: out <= 28\'h898ea18;
+         171: out <= 28\'h8d9ea19;
+         172: out <= 28\'h900ea00;
+         173: out <= 28\'h658ea19;
+         174: out <= 28\'h618ea00;
+         175: out <= 28\'hea16;
+         176: out <= 28\'h5a2ea1b;
+         177: out <= 28\'h6e3ea1c;
+         178: out <= 28\'h724ea21;
+         179: out <= 28\'h596005b;
+         180: out <= 28\'h596005c;
+         181: out <= 28\'h6d60041;
+         182: out <= 28\'h71b8041;
+         183: out <= 28\'h71bea1c;
+         184: out <= 28\'h71c8041;
+         185: out <= 28\'h71bea1c;
+         186: out <= 28\'h85c8041;
+         187: out <= 28\'h6dbea21;
+         188: out <= 28\'h85b80c1;
+         189: out <= 28\'h71cea21;
+         190: out <= 28\'h71c8101;
+         191: out <= 28\'h71bea1c;
+         192: out <= 28\'h85c8101;
+         193: out <= 28\'h6dbea21;
+         194: out <= 28\'h85b83c1;
+         195: out <= 28\'h6dbea21;
+         196: out <= 28\'h85b8781;
+         197: out <= 28\'h6dbea21;
+         198: out <= 28\'h85b8f01;
+         199: out <= 28\'h6dbea21;
+         200: out <= 28\'h85b82c1;
+         201: out <= 28\'h71cea21;
+         202: out <= 28\'h71c9e01;
+         203: out <= 28\'h6dbea1c;
+         204: out <= 28\'h71bbec1;
+         205: out <= 28\'h6dbea1c;
+         206: out <= 28\'h6db8041;
+         207: out <= 28\'h59bea16;
+         208: out <= 28\'h59bea16;
+         209: out <= 28\'h6e34064;
+         210: out <= 28\'h722405b;
+         211: out <= 28\'h1c4040;
+         212: out <= 28\'h6644059;
+         213: out <= 28\'h61b4058;
+         214: out <= 28\'h16ea00;
+         215: out <= 28\'h656ea19;
+         216: out <= 28\'h596ea18;
+         217: out <= 28\'h61d005e;
+         218: out <= 28\'h6dd0060;
+         219: out <= 28\'h71e0060;
+         220: out <= 28\'h8400059;
+         221: out <= 28\'h8800056;
+         222: out <= 28\'h8d90056;
+         223: out <= 28\'h75dea00;
+         224: out <= 28\'h79eea19;
+         225: out <= 28\'h820ea16;
+         226: out <= 28\'h618ea21;
+         227: out <= 28\'h6dbea22;
+         228: out <= 28\'h71cea23;
+         229: out <= 28\'h75d405e;
+         230: out <= 28\'h79d4060;
+         231: out <= 28\'h79e005c;
+         232: out <= 28\'h618405d;
+         233: out <= 28\'h618005c;
+         234: out <= 28\'h6db405d;
+         235: out <= 28\'h71f0057;
+         236: out <= 28\'h75f005a;
+         237: out <= 28\'h817005a;
+         238: out <= 28\'h8400059;
+         239: out <= 28\'h8800056;
+         240: out <= 28\'h8d90056;
+         241: out <= 28\'h1fea00;
+         242: out <= 28\'h5d7ea19;
+         243: out <= 28\'h59aea16;
+         244: out <= 28\'h65cea21;
+         245: out <= 28\'h69dea22;
+         246: out <= 28\'h720ea23;
+         247: out <= 28\'h4057;
+         248: out <= 28\'h5804056;
+         249: out <= 28\'h596005c;
+         250: out <= 28\'h5d94040;
+         251: out <= 28\'h5d7005c;
+         252: out <= 28\'h1a4040;
+         253: out <= 28\'h65e0056;
+         254: out <= 28\'h6980057;
+         255: out <= 28\'h71b4040;
+         256: out <= 28\'h75eea1b;
+         257: out <= 28\'h7d6ea00;
+         258: out <= 28\'h6d8ea1b;
+         259: out <= 28\'h17ea00;
+         260: out <= 28\'h819ea1c;
+         261: out <= 28\'h596ea18;
+         262: out <= 28\'h5deea17;
+         263: out <= 28\'h619ea1a;
+         264: out <= 28\'h65aea1c;
+         265: out <= 28\'h6960057;
+         266: out <= 28\'h61a4058;
+         267: out <= 28\'h69b0040;
+         268: out <= 28\'h69a005a;
+         269: out <= 28\'h405b;
+         270: out <= 28\'h6df405d;
+         271: out <= 28\'h6db0060;
+         272: out <= 28\'h702005d;
+         273: out <= 28\'h71c005f;
+         274: out <= 28\'h71c405a;
+         275: out <= 28\'h5974056;
+         276: out <= 28\'h59b0056;
+         277: out <= 28\'h5d80041;
+         278: out <= 28\'h7590040;
+         279: out <= 28\'h6dd005b;
+         280: out <= 28\'h618005a;
+         281: out <= 28\'h6180058;
+         282: out <= 28\'h190040;
+         283: out <= 28\'h40;
+         284: out <= 28\'h65c8041;
+         285: out <= 28\'h6968041;
+         286: out <= 28\'h7578041;
+         287: out <= 28\'h79b8041;
+         288: out <= 28\'h7d88041;
+         289: out <= 28\'h8008041;
+         290: out <= 28\'h659005d;
+         291: out <= 28\'h659005f;
+         292: out <= 28\'h69a005a;
+         293: out <= 28\'h69a405e;
+         294: out <= 28\'h69a4060;
+         295: out <= 28\'h75d405f;
+         296: out <= 28\'h7a0405e;
+         297: out <= 28\'h8200060;
+         298: out <= 28\'h6598041;
+         299: out <= 28\'h69a8041;
+         300: out <= 28\'h75d8041;
+         301: out <= 28\'h79e8041;
+         302: out <= 28\'h7df8041;
+         303: out <= 28\'h8208041;
+         304: out <= 28\'h659005d;
+         305: out <= 28\'h659005f;
+         306: out <= 28\'h69a005a;
+         307: out <= 28\'h69a405e;
+         308: out <= 28\'h69a4060;
+         309: out <= 28\'h75d405f;
+         310: out <= 28\'h7a0405e;
+         311: out <= 28\'h8200060;
+         312: out <= 28\'h85c0056;
+         313: out <= 28\'h897005b;
+         314: out <= 28\'h8d84040;
+         315: out <= 28\'h91cea18;
+         316: out <= 28\'h956ea00;
+         317: out <= 28\'h617ea18;
+         318: out <= 28\'h1bea00;
+         319: out <= 28\'h9a1ea23;
+         320: out <= 28\'h596ea17;
+         321: out <= 28\'h5dcea1b;
+         322: out <= 28\'h6e1ea22;
+         323: out <= 28\'h722ea23;
+         324: out <= 28\'h8560057;
+         325: out <= 28\'h6e1405b;
+         326: out <= 28\'h8580040;
+         327: out <= 28\'h8610061;
+         328: out <= 28\'h4058;
+         329: out <= 28\'h6254064;
+         330: out <= 28\'h6180066;
+         331: out <= 28\'h8820064;
+         332: out <= 28\'h8a20065;
+         333: out <= 28\'h8a24061;
+         334: out <= 28\'h5974056;
+         335: out <= 28\'h5980056;
+         336: out <= 28\'h5db0041;
+         337: out <= 28\'h8dc0040;
+         338: out <= 28\'h6230058;
+         339: out <= 28\'h6db0061;
+         340: out <= 28\'h6db005b;
+         341: out <= 28\'h1c0040;
+         342: out <= 28\'h40;
+         343: out <= 28\'h69a005a;
+         344: out <= 28\'h71e005e;
+         345: out <= 28\'h7a00060;
+         346: out <= 28\'h819005f;
+         347: out <= 28\'h860005d;
+         348: out <= 28\'h820405d;
+         349: out <= 28\'h8e2005b;
+         350: out <= 28\'h9230057;
+         351: out <= 28\'h8e34057;
+         352: out <= 28\'h659405f;
+         353: out <= 28\'h959405c;
+         354: out <= 28\'h659005c;
+         355: out <= 28\'h8a2405b;
+         356: out <= 28\'h9a24058;
+         357: out <= 28\'h8a20058;
+         358: out <= 28\'h9da005e;
+         359: out <= 28\'ha27005c;
+         360: out <= 28\'h727405c;
+         361: out <= 28\'h9d60040;
+         362: out <= 28\'ha670058;
+         363: out <= 28\'h6274058;
+         364: out <= 28\'h69a405e;
+         365: out <= 28\'h9da005d;
+         366: out <= 28\'h69a405d;
+         367: out <= 28\'h5964040;
+         368: out <= 28\'h7560057;
+         369: out <= 28\'h5964057;
+         370: out <= 28\'h5e10068;
+         371: out <= 28\'haa40069;
+         372: out <= 28\'hae50067;
+         373: out <= 28\'hb26005d;
+         374: out <= 28\'hb60005c;
+         375: out <= 28\'hba30058;
+         376: out <= 28\'hbd9005a;
+         377: out <= 28\'hc220056;
+         378: out <= 28\'hc5f005e;
+         379: out <= 28\'hc9b0040;
+         380: out <= 28\'h861ea24;
+         381: out <= 28\'h5d7ea2a;
+         382: out <= 28\'h928ea29;
+         383: out <= 28\'h965ea26;
+         384: out <= 28\'h9abea2c;
+         385: out <= 28\'h767ea1d;
+         386: out <= 28\'h820ea23;
+         387: out <= 28\'h8edea2e;
+         388: out <= 28\'h61cea18;
+         389: out <= 28\'h659ea22;
+         390: out <= 28\'h72fea30;
+         391: out <= 28\'h59aea16;
+         392: out <= 28\'h69fea1b;
+         393: out <= 28\'h6f1ea32;
+         394: out <= 28\'h1eea00;
+         395: out <= 28\'h7a10066;
+         396: out <= 28\'h79e005a;
+         397: out <= 28\'h7e4005c;
+         398: out <= 28\'h7df0040;
+         399: out <= 28\'h6a0005a;
+         400: out <= 28\'h180040;
+         401: out <= 28\'h40;
+         402: out <= 28\'h623005b;
+         403: out <= 28\'h8000064;
+         404: out <= 28\'h89a4061;
+         405: out <= 28\'h4064;
+         406: out <= 28\'h5d;
+         407: out <= 28\'h56;
+         408: out <= 28\'h69a0061;
+         409: out <= 28\'h69a4065;
+         410: out <= 28\'h69a4059;
+         411: out <= 28\'h25f405e;
+         412: out <= 28\'h2494065;
+         413: out <= 28\'h2490056;
+         414: out <= 28\'h29e005f;
+         415: out <= 28\'h28a4057;
+         416: out <= 28\'h28a005d;
+         417: out <= 28\'h28a0059;
+         418: out <= 28\'h28a405b;
+         419: out <= 28\'h2e00062;
+         420: out <= 28\'h3204062;
+         421: out <= 28\'h30c0058;
+         422: out <= 28\'h30c4057;
+         423: out <= 28\'h340005a;
+         424: out <= 28\'h380405a;
+         425: out <= 28\'h38e0058;
+         426: out <= 28\'h38e0057;
+         427: out <= 28\'h38e4066;
+         428: out <= 28\'h38e405c;
+         default: out <= 0;
+      endcase
+endmodule
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * the module of constants
+ *
+ * addr  out  effective
+ *    1   0     1
+ *    2   1     1
+ *    4   +     1
+ *    8   -     1
+ *   16 cubic   1
+ * other  0     0
+ */
+module const (clk, addr, out, effective);
+    input clk;
+    input [5:0] addr;
+    output reg [197:0] out;
+    output reg effective; // active high if out is effective
+    
+    always @ (posedge clk)
+      begin
+         effective <= 1;
+         case (addr)
+            1:  out <= 198\'d0;
+            2:  out <= 198\'d1;
+            4:  out <= {6\'b000101, 192\'d0};
+            8:  out <= {6\'b001001, 192\'d0};
+            16: out <= {6\'b010101, 192\'d0};
+            default: 
+               begin out <= 198\'d0; effective <= 0; end
+         endcase
+      end
+endmodule
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+`timescale 1ns / 1ps
+`define P 20 // clock period 
+`define M     593         // M is the degree of the irreducible polynomial
+`define WIDTH (2*`M-1)    // width for a GF(3^M) element
+`define WIDTH_D0 1187
+
+module test_pairing;
+
+\t// Inputs
+\treg clk;
+\treg reset;
+\treg sel;
+\treg [5:0] addr;
+\treg w;
+    reg update;
+    reg ready;
+    reg i;
+
+\t// Outputs
+\twire done;
+    wire o;
+
+    // Buffers
+\treg [`WIDTH_D0:0] out;
+
+\t// Instantiate the Unit Under Test (UUT)
+\tpairing uut (
+        .clk(clk), 
+        .reset(reset), 
+        .sel(sel), 
+        .addr(addr), 
+        .w(w), 
+        .update(update),
+        .ready(ready),
+        .i(i),
+        .o(o),
+        .done(done)
+\t);
+
+\tinitial begin
+\t\t// Initialize Inputs
+\t\tclk = 0;
+\t\treset = 0;
+\t\tsel = 0;
+\t\taddr = 0;
+\t\tw = 0;
+        update = 0;
+        ready = 0;
+        i = 0;
+        out = 0;
+
+\t\t// Wait 100 ns for global reset to finish
+\t\t#100;
+        
+\t\t// Add stimulus here
+        /* keep FSM silent */
+        reset = 1;
+            /* init xp, yp, xq, yq */
+            write(3, 1186\'h088a6aa4a8aa80a9aa922965a92a56510856606aa6400649a6004866466928a20090908210195560a8162a52442029a44a68004a8168496a0a8a8564962a0948118a5599a29450214995828245914a099051991602550105228289686988621a1a9126648644619a66111a026452641169158a4686884aa212199582406600921229a5948802528289a62454a2566a4122586a496);
+            write(5, 1186\'h05448582294062429a891a6509092496844141090214064988646241904502a0225046a54851a05454020044881088a2092411592909289861049124644a964a6188014aa25869a09890401a924048815a1008421459455411a4a65094410615a524458901026a9108a468650515a5aa50468005881a29055980995a145995146909841aa18890902264628884421894959956195);
+            write(6, 1186\'h088a6aa4a8aa80a9aa922965a92a56510856606aa6400649a6004866466928a20090908210195560a8162a52442029a44a68004a8168496a0a8a8564962a0948118a5599a29450214995828245914a099051991602550105228289686988621a1a9126648644619a66111a026452641169158a4686884aa212199582406600921229a5948802528289a62454a2566a4122586a496);
+            write(7, 1186\'h05448582294062429a891a6509092496844141090214064988646241904502a0225046a54851a05454020044881088a2092411592909289861049124644a964a6188014aa25869a09890401a924048815a1008421459455411a4a65094410615a524458901026a9108a468650515a5aa50468005881a29055980995a145995146909841aa18890902264628884421894959956195);
+            /* read back. uncomment me if error happens */
+            /* read(3);
+            $display(""xp = %h"", out);
+            read(5);
+            $display(""yp = %h"", out);
+            read(6);
+            $display(""xq = %h"", out);
+            read(7);
+            $display(""yq = %h"", out);*/
+        reset = 0;
+        
+        sel = 0; w = 0;
+        @(posedge done);
+        @(negedge clk);
+            read(9);
+            check(1186\'h20115a6958895a08585a412698a58250900a651a859448a4848125164545598a426119a09885802424154a08855a0042a168516099228606222540582026aa0a6029a88805a1888628856a2a64504120aa290491925284508921140a24a0a8641548a521512698985a610861a401208644612a4a52625119000006004518844899810191a056aaa680889958996508954685a0920);
+            read(10);
+            check(1186\'h228a9556506501a0258028a8856851a5466a205a2544849a12a10a018a40aaa461959859a4408245094969a44565a160a98229805169491120568121008a04918050a9022854868440662591221116889a9668a82aa84182a59025424469164015a56698a95989555601618402286696055608a82508125aaa5882000aaa96114998660a684582889a5a5190058a0411426145250);
+            read(11);
+            check(1186\'h001224a468a9154205488585aaa9a0a9882056194952001a88424522191052a96a21102915181a845a5509844985196696160900a0515956a2a10a100a12566408a14450049a586951896442400a8620148582958a8a51869990a161412406860012a61a66214a4461a86895640a48284528201852615921952aaaaa40802586168a929582128a985929990826a9110186891489a);
+            read(12);
+            check(1186\'h019618a9624a522a280a06a0654418906998059625a892054996a0560a941a842589189984190884426125114000aa60a0a568285221026662226a626a8600605095054405486561a95059449282969a5a10819101a620902609052a1294182962a020512196945a2aa42598a41842096596551544969262a12a86685214a952494a956166a199682a649249a990088296422051a);
+            read(13);
+            check(1186\'h1a6999a0105054aaa2145298116480601695482119a0619155a4414a8a82840918a512a5680a8000889a4905016868480211289860a8a5699a250245161a042846096a9866025094a189860a9829465281646040866a26959a61a18621848689101a9a95685016a9581224968461a0a108958a91205a0220a18865105928298299a642a906900289a95095845649aa41591069866);
+            read(14);
+            check(1186\'h15a4208a19a0405005900212505098a881a49445242619a12a12491844110169529a422046a684668819599891a411954196961160591865590a699a04908a6196928965a1686a664210420908115a5816919169662656a855099464680902514586265602510840a566a94a506961a615420a908aa91959610a1a0899589600902a10962460a664104126056a82551462459169a);
+            $display(""Good"");
+        $finish;
+\tend
+
+    initial #100 forever #(`P/2) clk = ~clk;
+
+    task write;
+        input [5:0] adr;
+        input [`WIDTH_D0:0] dat;
+        integer j;
+        begin
+            sel = 1; 
+            w = 0;
+            addr = adr;
+            update = 1;
+            #`P;
+            update = 0;
+            ready = 1;
+            for(j=0;j<`WIDTH_D0+1;j=j+1)
+               begin
+               i = dat[j];
+               #`P;
+               end
+            ready = 0;
+            w = 1; #`P; w = 0;
+        end
+    endtask
+
+    task read;
+        input [5:0] adr;
+        integer j;
+        begin
+            sel = 1;
+            w = 0;
+            addr = adr;
+            #`P;
+            update = 1;
+            #`P;
+            update = 0;
+            out = 0;
+            ready = 1;
+            for(j=0;j<`WIDTH_D0+1;j=j+1)
+               begin
+               out = {o, out[`WIDTH_D0:1]};
+               #`P;
+               end
+        end
+    endtask
+    
+    task check;
+        input [`WIDTH_D0:0] wish;
+        begin
+            if (out !== wish) 
+                begin $display(""Error!""); $finish; end
+        end
+    endtask    
+endmodule
+
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+`define M     593         // M is the degree of the irreducible polynomial
+`define WIDTH (2*`M-1)    // width for a GF(3^M) element
+`define WIDTH_D0 1187
+
+module pairing(clk, reset, sel, addr, w, update, ready, i, o, done);
+   input clk;
+   input reset; // for the arithmethic core
+   input sel;
+   input [5:0] addr;
+   input w;
+   input update; // update reg_in & reg_out
+   input ready;  // shift reg_in & reg_out
+   input i;
+   output o;
+   output done;
+   
+   reg [`WIDTH_D0:0] reg_in, reg_out;
+   wire [`WIDTH_D0:0] out;
+   
+   assign o = reg_out[0];
+   
+   tiny
+      tiny0 (clk, reset, sel, addr, w, reg_in, out, done);
+   
+   always @ (posedge clk) // write LSB firstly
+      if (update) reg_in <= 0;
+      else if (ready) reg_in <= {i,reg_in[`WIDTH_D0:1]};
+   
+   always @ (posedge clk) // read LSB firstly
+      if (update) reg_out <= out;
+      else if (ready) reg_out <= reg_out>>1;
+endmodule
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+`timescale 1ns / 1ps
+`define P 20 // clock period
+
+module test_fsm;
+
+\t// Inputs
+\treg clk;
+\treg reset;
+\treg [25:0] rom_q;
+
+\t// Outputs
+\twire [8:0] rom_addr;
+\twire [5:0] ram_a_addr;
+\twire [5:0] ram_b_addr;
+\twire ram_b_w;
+\twire [10:0] pe;
+\twire done;
+
+\t// Instantiate the Unit Under Test (UUT)
+\tFSM uut (
+\t\t.clk(clk), 
+\t\t.reset(reset), 
+\t\t.rom_addr(rom_addr), 
+\t\t.rom_q(rom_q), 
+\t\t.ram_a_addr(ram_a_addr), 
+\t\t.ram_b_addr(ram_b_addr), 
+\t\t.ram_b_w(ram_b_w), 
+\t\t.pe(pe), 
+\t\t.done(done)
+\t);
+
+\tinitial begin
+\t\t// Initialize Inputs
+\t\tclk = 0;
+\t\treset = 0;
+
+\t\t// Wait 100 ns for global reset to finish
+\t\t#100;
+        
+\t\t// Add stimulus here
+        #(`P/2); reset = 1; #(`P); reset = 0;
+        
+        @(posedge done);
+        $finish;
+\tend
+    
+    initial #100 forever #(`P/2) clk = ~clk;
+    
+    /* rom code format 
+     * wire [5:0] dest, src1, src2, times; wire [1:0] op;
+     * assign {dest, src1, op, times, src2} = rom_q;
+     */
+    parameter ADD=2\'d0, SUB=2\'d1, CUBIC=2\'d2, MULT=2\'d3;
+
+    always @ (posedge clk)
+        case(rom_addr)
+        0: rom_q <= {6\'d10, 6\'d11, ADD, 6\'d1, 6\'d12};
+        1: rom_q <= {6\'d20, 6\'d21, SUB, 6\'d1, 6\'d22};
+        2: rom_q <= {6\'d30, 6\'d31, CUBIC, 6\'d5, 6\'d32};
+        3: rom_q <= {6\'d40, 6\'d41, MULT, 6\'d33, 6\'d42};
+        default: rom_q <= 0;
+        endcase
+endmodule
+
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+`timescale 1ns / 1ps
+`define P 20 // clock period 
+`define M     503         // M is the degree of the irreducible polynomial
+`define WIDTH (2*`M-1)    // width for a GF(3^M) element
+`define WIDTH_D0 (1008-1)
+
+module test_tiny;
+
+\t// Inputs
+\treg clk;
+\treg reset;
+\treg sel;
+\treg [5:0] addr;
+\treg w;
+\treg [`WIDTH_D0:0] data;
+
+\t// Outputs
+\twire [`WIDTH_D0:0] out;
+\twire done;
+
+\t// Instantiate the Unit Under Test (UUT)
+\ttiny uut (
+\t\t.clk(clk), 
+\t\t.reset(reset), 
+\t\t.sel(sel), 
+\t\t.addr(addr), 
+\t\t.w(w), 
+\t\t.data(data), 
+\t\t.out(out), 
+\t\t.done(done)
+\t);
+
+\tinitial begin
+\t\t// Initialize Inputs
+\t\tclk = 0;
+\t\treset = 0;
+\t\tsel = 0;
+\t\taddr = 0;
+\t\tw = 0;
+\t\tdata = 0;
+
+\t\t// Wait 100 ns for global reset to finish
+\t\t#100;
+        
+\t\t// Add stimulus here
+        reset = 1; // keep FSM silent
+            // init x, y
+            write(3, 1006\'h0412500224298894260864922a0084a98a0454681a18164a08268062495a596469659050406960a191646a024a0aa26688240682059585a258a89664946584924a9a8a1a8145400889899a6a2601184a2596419a04161969169128281805669a9509145852901691690a8506a9145224850109a150110629229564901a00);
+            write(5, 1006\'h161181618265a480158208a088a01aa89a424001019a90912969511008944a806119a1429520105654089861546a912295590518a90842962660a665899405681aa510844840524240145a0295855920091640a66a5a044568510469454a18a06218922914510004a25409a81a5800456055996128a965624116289904aa);
+            write(6, 1006\'h0412500224298894260864922a0084a98a0454681a18164a08268062495a596469659050406960a191646a024a0aa26688240682059585a258a89664946584924a9a8a1a8145400889899a6a2601184a2596419a04161969169128281805669a9509145852901691690a8506a9145224850109a150110629229564901a00);
+            write(7, 1006\'h161181618265a480158208a088a01aa89a424001019a90912969511008944a806119a1429520105654089861546a912295590518a90842962660a665899405681aa510844840524240145a0295855920091640a66a5a044568510469454a18a06218922914510004a25409a81a5800456055996128a965624116289904aa);
+            /* read back. uncomment me if error happens */
+            /* read(3);
+            $display(""xp = %h"", out);
+            read(5);
+            $display(""yp = %h"", out);
+            read(6);
+            $display(""xq = %h"", out);
+            read(7);
+            $display(""yq = %h"", out);*/
+        reset = 0;
+        sel = 0; w = 0;
+        @(posedge done);
+        @(negedge clk);
+            read(9);
+            check(1006\'h2965a664a44a85426524a19821aa12a42605258540a056525248149a96061560451a6a95861496a8140985a8902955951552696a425948159a2141a0aaa5840442851218546a49a2a2496658644656a9a6162a5098a025645151aa668902aaa102a0805900488980545120462896204252584282868449488a00884995a9);
+            read(10);
+            check(1006\'h244151402864a58144a0509a26121148024224a299a4062a248944801589895a04a8a681a4245492a5aa5958901a142120515582941220529512012554699982594528256086220a55641a5a212511aa50a0a4a198200560a628994925551249659028459a8a24688191044a08529064119949a112564a52082068858890);
+            read(11);
+            check(1006\'h180645a168488aa651260a226a124a66080299922a8595404428610808262992a22682905a55625665824505a609882a88422a886296551a6221a29a16aa11141a12280942aa84094946860205964a26669684569054810a914124a086212a5a5821440119015a98844101854a9951141981221169224a1599a11914a504);
+            read(12);
+            check(1006\'h18a6911a415584242209a6a52629464160400a0a45554552866a9a20a8520a551856814024118140a144a151604449609aa24085a609a2a0851285445a96602a2461212641204a591a66a5604211004882191912920862a9860a861a88a005516611622a44880a48690412292244615156004952521664a84a5961510225);
+            read(13);
+            check(1006\'h250869062a008a1882940945a20441680111009595094282260a95488aaa4588262641912aa64a29a8526408451940619612014212441090209588888a004002462206a8294a158809258852650a15226a99808952201191614814166198a52a8151454968a288295994286919811691aa21048661a5288402182a558215);
+            read(14);
+            check(1006\'h016641111896469064656661124a160226a89485469954a6a5406aa28590655a018922965688045984585a61888165085289a61a051258a59459210842108082566966664250991442a2941521806608610a52182256042680a4881900605a8459260a9824295244629865a6a62a18958a66955152404814065588150894);
+            $display(""Good"");
+        $finish;
+\tend
+
+    initial #100 forever #(`P/2) clk = ~clk;
+
+    task write;
+        input [6:0] adr;
+        input [`WIDTH_D0:0] dat;
+        begin
+            sel = 1; 
+            w = 1;
+            addr = adr;
+            data = dat;
+            #(`P);
+        end
+    endtask
+
+    task read;
+        input [6:0] adr;
+        begin
+            sel = 1; 
+            w = 0;
+            addr = adr;
+            #(`P);
+        end
+    endtask
+
+    task check;
+        input [`WIDTH_D0:0] wish;
+        begin
+            if (out !== wish) 
+                begin $display(""Error! %h %h"", out, wish); end
+        end
+    endtask    
+endmodule
+
+"
+"/*
+ * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+module tiny(clk, reset, sel, addr, w, data, out, done);
+    input clk, reset;
+    input sel;
+    input [5:0] addr;
+    input w;
+    input [197:0] data;
+    output [197:0] out;
+    output done;
+
+    /* for FSM */
+    wire [5:0] fsm_addr;
+    /* for RAM */
+    wire [5:0] ram_a_addr, ram_b_addr;
+    wire [197:0] ram_b_data_in;
+    wire ram_a_w, ram_b_w;
+    wire [197:0] ram_a_data_out, ram_b_data_out;
+    /* for const */
+    wire [197:0] const0_out, const1_out;
+    wire const0_effective, const1_effective;
+    /* for muxer */
+    wire [197:0] muxer0_out, muxer1_out;
+    /* for ROM */
+    wire [8:0] rom_addr;
+    wire [25:0] rom_q;
+    /* for PE */
+    wire [10:0] pe_ctrl;
+    
+    assign out = ram_a_data_out;
+    
+    select 
+        select0 (sel, addr, fsm_addr, w, ram_a_addr, ram_a_w);
+    rom
+        rom0 (clk, rom_addr, rom_q);
+    FSM
+        fsm0 (clk, reset, rom_addr, rom_q, fsm_addr, ram_b_addr, ram_b_w, pe_ctrl, done);
+    const
+        const0 (clk, ram_a_addr, const0_out, const0_effective),
+        const1 (clk, ram_b_addr, const1_out, const1_effective);
+    ram
+        ram0 (clk, ram_a_w, ram_a_addr, data, ram_a_data_out, ram_b_w, ram_b_addr[5:0], ram_b_data_in, ram_b_data_out);
+    muxer
+        muxer0 (ram_a_data_out, const0_out, const0_effective, muxer0_out),
+        muxer1 (ram_b_data_out, const1_out, const1_effective, muxer1_out);
+    PE
+        pe0 (clk, reset, pe_ctrl, muxer1_out, muxer0_out[193:0], muxer0_out[193:0], ram_b_data_in[193:0]);
+    
+    assign ram_b_data_in[197:194] = 0;
+endmodule
+
+module select(sel, addr_in, addr_fsm_in, w_in, addr_out, w_out);
+    input sel;
+    input [5:0] addr_in;
+    input [5:0] addr_fsm_in;
+    input w_in;
+    output [5:0] addr_out;
+    output w_out;
+    
+    assign addr_out = sel ? addr_in : addr_fsm_in;
+    assign w_out = sel & w_in;
+endmodule
+
+module muxer(from_ram, from_const, const_effective, out);
+    input [197:0] from_ram, from_const;
+    input const_effective;
+    output [197:0] out;
+    
+    assign out = const_effective ? from_const : from_ram;
+endmodule
+"
+"Module Error.
+
+  Fixpoint evenb (n:nat) : bool :=
+    match n with
+      | O => true
+      | S O => false
+      | S (S n') => 1
+    end.
+
+End Error.
+"
+"module verilator_warning;
+   reg val;
+endmodule
+"
+"Module SyntaxError.
+
+  Fixpoint evenb (n:nat) : bool :=
+    match n with
+      | O => true
+       S O => false
+      | S (S n') => evenb n'
+    end.
+
+End SyntaxError.
+"
+"module verilog_verilator_error;
+   initial begin
+      forever begin
+         i = $fopen(""test.log"");
+      end
+   end
+endmodule
+"
+"module tb_calc_next_age;
+
+wire age_out;
+reg [3:0] live_count;
+reg step;
+reg clock;
+reg reset;
+
+initial begin
+    $from_myhdl(
+        live_count,
+        step,
+        clock,
+        reset
+    );
+    $to_myhdl(
+        age_out
+    );
+end
+
+calc_next_age dut(
+    age_out,
+    live_count,
+    step,
+    clock,
+    reset
+);
+
+endmodule
+"
+"// File: tb.v
+// Generated by MyHDL 0.8dev
+// Date: Sun Dec 16 22:45:16 2012
+
+
+`timescale 1ns/10ps
+
+module tb (
+
+);
+
+
+
+reg reset;
+reg [3:0] live_count;
+reg step;
+reg clock;
+wire age_out;
+reg dut_age;
+
+
+
+
+
+always @(posedge clock, posedge reset) begin: TB_DUT_SEQ
+    reg survival;
+    reg birth;
+    if (reset == 1) begin
+        dut_age <= 0;
+    end
+    else begin
+        birth = (live_count == 3);
+        survival = ((live_count == 2) || (live_count == 3));
+        if (step) begin
+            if (((dut_age == 0) && birth)) begin
+                dut_age <= 1;
+            end
+            else if (((dut_age == 1) && (!survival))) begin
+                dut_age <= 0;
+            end
+        end
+    end
+end
+
+
+
+assign age_out = dut_age;
+
+
+initial begin: TB_CLOCKGEN
+    reset <= 0;
+    clock <= 0;
+    # 10;
+    reset <= 1;
+    # 10;
+    reset <= 0;
+    while (1\'b1) begin
+        # 10;
+        clock <= (!clock);
+    end
+end
+
+
+initial begin: TB_CHECK
+    reg expected_age;
+    integer i;
+    integer v;
+    expected_age = 0;
+    for (i=0; i<1000; i=i+1) begin
+        @(negedge clock);
+        $write(""%0d"", age_out);
+        $write(""\
+"");
+        case (i)
+            0: v = 2;
+            1: v = 7;
+            2: v = 0;
+            3: v = 6;
+            4: v = 0;
+            5: v = 2;
+            6: v = 0;
+            7: v = 7;
+            8: v = 0;
+            9: v = 3;
+            10: v = 7;
+            11: v = 6;
+            12: v = 0;
+            13: v = 8;
+            14: v = 6;
+            15: v = 5;
+            16: v = 8;
+            17: v = 3;
+            18: v = 1;
+            19: v = 0;
+            20: v = 2;
+            21: v = 7;
+            22: v = 7;
+            23: v = 0;
+            24: v = 4;
+            25: v = 4;
+            26: v = 3;
+            27: v = 6;
+            28: v = 5;
+            29: v = 0;
+            30: v = 1;
+            31: v = 5;
+            32: v = 8;
+            33: v = 6;
+            34: v = 5;
+            35: v = 5;
+            36: v = 8;
+            37: v = 6;
+            38: v = 3;
+            39: v = 1;
+            40: v = 4;
+            41: v = 5;
+            42: v = 1;
+            43: v = 6;
+            44: v = 7;
+            45: v = 4;
+            46: v = 8;
+            47: v = 0;
+            48: v = 2;
+            49: v = 1;
+            50: v = 1;
+            51: v = 4;
+            52: v = 2;
+            53: v = 7;
+            54: v = 1;
+            55: v = 6;
+            56: v = 4;
+            57: v = 7;
+            58: v = 6;
+            59: v = 2;
+            60: v = 1;
+            61: v = 2;
+            62: v = 2;
+            63: v = 6;
+            64: v = 8;
+            65: v = 4;
+            66: v = 4;
+            67: v = 7;
+            68: v = 4;
+            69: v = 3;
+            70: v = 0;
+            71: v = 3;
+            72: v = 2;
+            73: v = 4;
+            74: v = 1;
+            75: v = 2;
+            76: v = 4;
+            77: v = 5;
+            78: v = 4;
+            79: v = 4;
+            80: v = 0;
+            81: v = 1;
+            82: v = 1;
+            83: v = 1;
+            84: v = 7;
+            85: v = 8;
+            86: v = 5;
+            87: v = 6;
+            88: v = 1;
+            89: v = 2;
+            90: v = 5;
+            91: v = 7;
+            92: v = 8;
+            93: v = 4;
+            94: v = 5;
+            95: v = 0;
+            96: v = 1;
+            97: v = 7;
+            98: v = 5;
+            99: v = 6;
+            100: v = 8;
+            101: v = 5;
+            102: v = 2;
+            103: v = 7;
+            104: v = 2;
+            105: v = 4;
+            106: v = 5;
+            107: v = 4;
+            108: v = 1;
+            109: v = 8;
+            110: v = 4;
+            111: v = 7;
+            112: v = 6;
+            113: v = 8;
+            114: v = 4;
+            115: v = 8;
+            116: v = 0;
+            117: v = 3;
+            118: v = 0;
+            119: v = 5;
+            120: v = 8;
+            121: v = 8;
+            122: v = 4;
+            123: v = 3;
+            124: v = 3;
+            125: v = 3;
+            126: v = 1;
+            127: v = 2;
+            128: v = 5;
+            129: v = 3;
+            130: v = 2;
+            131: v = 2;
+            132: v = 6;
+            133: v = 6;
+            134: v = 1;
+            135: v = 1;
+            136: v = 5;
+            137: v = 5;
+            138: v = 6;
+            139: v = 6;
+            140: v = 1;
+            141: v = 3;
+            142: v = 3;
+            143: v = 4;
+            144: v = 8;
+            145: v = 8;
+            146: v = 4;
+            147: v = 3;
+            148: v = 2;
+            149: v = 4;
+            150: v = 6;
+            151: v = 7;
+            152: v = 2;
+            153: v = 5;
+            154: v = 5;
+            155: v = 0;
+            156: v = 1;
+            157: v = 2;
+            158: v = 1;
+            159: v = 4;
+            160: v = 0;
+            161: v = 0;
+            162: v = 2;
+            163: v = 6;
+            164: v = 7;
+            165: v = 6;
+            166: v = 7;
+            167: v = 0;
+            168: v = 8;
+            169: v = 2;
+            170: v = 4;
+            171: v = 5;
+            172: v = 4;
+            173: v = 7;
+            174: v = 3;
+            175: v = 3;
+            176: v = 2;
+            177: v = 6;
+            178: v = 7;
+            179: v = 7;
+            180: v = 8;
+            181: v = 0;
+            182: v = 7;
+            183: v = 8;
+            184: v = 4;
+            185: v = 1;
+            186: v = 6;
+            187: v = 5;
+            188: v = 4;
+            189: v = 4;
+            190: v = 6;
+            191: v = 4;
+            192: v = 8;
+            193: v = 0;
+            194: v = 6;
+            195: v = 2;
+            196: v = 1;
+            197: v = 3;
+            198: v = 5;
+            199: v = 5;
+            200: v = 6;
+            201: v = 2;
+            202: v = 8;
+            203: v = 4;
+            204: v = 6;
+            205: v = 0;
+            206: v = 0;
+            207: v = 6;
+            208: v = 4;
+            209: v = 0;
+            210: v = 8;
+            211: v = 7;
+            212: v = 2;
+            213: v = 3;
+            214: v = 3;
+            215: v = 8;
+            216: v = 8;
+            217: v = 5;
+            218: v = 8;
+            219: v = 4;
+            220: v = 5;
+            221: v = 8;
+            222: v = 6;
+            223: v = 6;
+            224: v = 8;
+            225: v = 7;
+            226: v = 5;
+            227: v = 2;
+            228: v = 2;
+            229: v = 2;
+            230: v = 3;
+            231: v = 6;
+            232: v = 5;
+            233: v = 5;
+            234: v = 5;
+            235: v = 6;
+            236: v = 3;
+            237: v = 6;
+            238: v = 4;
+            239: v = 8;
+            240: v = 6;
+            241: v = 5;
+            242: v = 2;
+            243: v = 8;
+            244: v = 1;
+            245: v = 8;
+            246: v = 2;
+            247: v = 4;
+            248: v = 1;
+            249: v = 8;
+            250: v = 2;
+            251: v = 5;
+            252: v = 8;
+            253: v = 2;
+            254: v = 6;
+            255: v = 6;
+            256: v = 2;
+            257: v = 4;
+            258: v = 7;
+            259: v = 6;
+            260: v = 8;
+            261: v = 0;
+            262: v = 6;
+            263: v = 7;
+            264: v = 2;
+            265: v = 5;
+            266: v = 6;
+            267: v = 1;
+            268: v = 3;
+            269: v = 4;
+            270: v = 1;
+            271: v = 2;
+            272: v = 7;
+            273: v = 1;
+            274: v = 4;
+            275: v = 2;
+            276: v = 6;
+            277: v = 6;
+            278: v = 1;
+            279: v = 3;
+            280: v = 3;
+            281: v = 5;
+            282: v = 0;
+            283: v = 8;
+            284: v = 5;
+            285: v = 7;
+            286: v = 8;
+            287: v = 1;
+            288: v = 6;
+            289: v = 3;
+            290: v = 1;
+            291: v = 4;
+            292: v = 0;
+            293: v = 7;
+            294: v = 4;
+            295: v = 7;
+            296: v = 2;
+            297: v = 5;
+            298: v = 3;
+            299: v = 6;
+            300: v = 1;
+            301: v = 6;
+            302: v = 0;
+            303: v = 0;
+            304: v = 1;
+            305: v = 8;
+            306: v = 3;
+            307: v = 2;
+            308: v = 5;
+            309: v = 1;
+            310: v = 8;
+            311: v = 1;
+            312: v = 1;
+            313: v = 4;
+            314: v = 2;
+            315: v = 6;
+            316: v = 2;
+            317: v = 2;
+            318: v = 7;
+            319: v = 0;
+            320: v = 5;
+            321: v = 5;
+            322: v = 2;
+            323: v = 0;
+            324: v = 8;
+            325: v = 2;
+            326: v = 3;
+            327: v = 5;
+            328: v = 8;
+            329: v = 2;
+            330: v = 8;
+            331: v = 0;
+            332: v = 6;
+            333: v = 5;
+            334: v = 0;
+            335: v = 8;
+            336: v = 6;
+            337: v = 6;
+            338: v = 4;
+            339: v = 8;
+            340: v = 7;
+            341: v = 5;
+            342: v = 6;
+            343: v = 1;
+            344: v = 1;
+            345: v = 7;
+            346: v = 8;
+            347: v = 6;
+            348: v = 1;
+            349: v = 4;
+            350: v = 4;
+            351: v = 8;
+            352: v = 4;
+            353: v = 6;
+            354: v = 7;
+            355: v = 4;
+            356: v = 3;
+            357: v = 5;
+            358: v = 3;
+            359: v = 4;
+            360: v = 3;
+            361: v = 5;
+            362: v = 6;
+            363: v = 1;
+            364: v = 3;
+            365: v = 1;
+            366: v = 7;
+            367: v = 1;
+            368: v = 2;
+            369: v = 8;
+            370: v = 6;
+            371: v = 1;
+            372: v = 4;
+            373: v = 6;
+            374: v = 6;
+            375: v = 7;
+            376: v = 8;
+            377: v = 8;
+            378: v = 8;
+            379: v = 0;
+            380: v = 4;
+            381: v = 6;
+            382: v = 2;
+            383: v = 0;
+            384: v = 5;
+            385: v = 4;
+            386: v = 7;
+            387: v = 2;
+            388: v = 7;
+            389: v = 2;
+            390: v = 3;
+            391: v = 5;
+            392: v = 4;
+            393: v = 1;
+            394: v = 2;
+            395: v = 8;
+            396: v = 8;
+            397: v = 3;
+            398: v = 8;
+            399: v = 4;
+            400: v = 5;
+            401: v = 3;
+            402: v = 0;
+            403: v = 8;
+            404: v = 0;
+            405: v = 0;
+            406: v = 6;
+            407: v = 5;
+            408: v = 4;
+            409: v = 6;
+            410: v = 0;
+            411: v = 0;
+            412: v = 5;
+            413: v = 3;
+            414: v = 2;
+            415: v = 1;
+            416: v = 2;
+            417: v = 7;
+            418: v = 0;
+            419: v = 6;
+            420: v = 1;
+            421: v = 0;
+            422: v = 2;
+            423: v = 0;
+            424: v = 0;
+            425: v = 4;
+            426: v = 4;
+            427: v = 0;
+            428: v = 0;
+            429: v = 3;
+            430: v = 7;
+            431: v = 5;
+            432: v = 7;
+            433: v = 2;
+            434: v = 1;
+            435: v = 4;
+            436: v = 1;
+            437: v = 4;
+            438: v = 3;
+            439: v = 7;
+            440: v = 6;
+            441: v = 1;
+            442: v = 8;
+            443: v = 7;
+            444: v = 6;
+            445: v = 1;
+            446: v = 2;
+            447: v = 2;
+            448: v = 6;
+            449: v = 3;
+            450: v = 6;
+            451: v = 8;
+            452: v = 3;
+            453: v = 6;
+            454: v = 8;
+            455: v = 6;
+            456: v = 4;
+            457: v = 4;
+            458: v = 3;
+            459: v = 5;
+            460: v = 2;
+            461: v = 0;
+            462: v = 4;
+            463: v = 4;
+            464: v = 7;
+            465: v = 3;
+            466: v = 2;
+            467: v = 4;
+            468: v = 6;
+            469: v = 8;
+            470: v = 1;
+            471: v = 5;
+            472: v = 5;
+            473: v = 7;
+            474: v = 8;
+            475: v = 0;
+            476: v = 5;
+            477: v = 1;
+            478: v = 4;
+            479: v = 1;
+            480: v = 3;
+            481: v = 2;
+            482: v = 5;
+            483: v = 0;
+            484: v = 2;
+            485: v = 2;
+            486: v = 6;
+            487: v = 2;
+            488: v = 5;
+            489: v = 6;
+            490: v = 1;
+            491: v = 0;
+            492: v = 8;
+            493: v = 1;
+            494: v = 2;
+            495: v = 6;
+            496: v = 4;
+            497: v = 3;
+            498: v = 0;
+            499: v = 7;
+            500: v = 8;
+            501: v = 0;
+            502: v = 5;
+            503: v = 7;
+            504: v = 7;
+            505: v = 7;
+            506: v = 2;
+            507: v = 6;
+            508: v = 8;
+            509: v = 3;
+            510: v = 4;
+            511: v = 0;
+            512: v = 2;
+            513: v = 8;
+            514: v = 0;
+            515: v = 6;
+            516: v = 1;
+            517: v = 0;
+            518: v = 0;
+            519: v = 5;
+            520: v = 1;
+            521: v = 2;
+            522: v = 7;
+            523: v = 7;
+            524: v = 5;
+            525: v = 3;
+            526: v = 1;
+            527: v = 8;
+            528: v = 0;
+            529: v = 3;
+            530: v = 7;
+            531: v = 3;
+            532: v = 8;
+            533: v = 2;
+            534: v = 0;
+            535: v = 8;
+            536: v = 0;
+            537: v = 6;
+            538: v = 7;
+            539: v = 4;
+            540: v = 3;
+            541: v = 4;
+            542: v = 8;
+            543: v = 6;
+            544: v = 4;
+            545: v = 8;
+            546: v = 4;
+            547: v = 0;
+            548: v = 7;
+            549: v = 5;
+            550: v = 4;
+            551: v = 2;
+            552: v = 4;
+            553: v = 2;
+            554: v = 5;
+            555: v = 4;
+            556: v = 3;
+            557: v = 7;
+            558: v = 4;
+            559: v = 2;
+            560: v = 3;
+            561: v = 3;
+            562: v = 1;
+            563: v = 2;
+            564: v = 0;
+            565: v = 5;
+            566: v = 6;
+            567: v = 7;
+            568: v = 4;
+            569: v = 0;
+            570: v = 8;
+            571: v = 3;
+            572: v = 4;
+            573: v = 2;
+            574: v = 4;
+            575: v = 7;
+            576: v = 4;
+            577: v = 2;
+            578: v = 5;
+            579: v = 7;
+            580: v = 6;
+            581: v = 7;
+            582: v = 3;
+            583: v = 8;
+            584: v = 4;
+            585: v = 6;
+            586: v = 8;
+            587: v = 1;
+            588: v = 5;
+            589: v = 4;
+            590: v = 6;
+            591: v = 7;
+            592: v = 5;
+            593: v = 6;
+            594: v = 7;
+            595: v = 4;
+            596: v = 1;
+            597: v = 4;
+            598: v = 2;
+            599: v = 0;
+            600: v = 4;
+            601: v = 6;
+            602: v = 6;
+            603: v = 7;
+            604: v = 2;
+            605: v = 2;
+            606: v = 0;
+            607: v = 6;
+            608: v = 4;
+            609: v = 7;
+            610: v = 7;
+            611: v = 1;
+            612: v = 7;
+            613: v = 8;
+            614: v = 2;
+            615: v = 0;
+            616: v = 5;
+            617: v = 8;
+            618: v = 6;
+            619: v = 0;
+            620: v = 2;
+            621: v = 6;
+            622: v = 2;
+            623: v = 1;
+            624: v = 2;
+            625: v = 3;
+            626: v = 8;
+            627: v = 7;
+            628: v = 8;
+            629: v = 1;
+            630: v = 0;
+            631: v = 7;
+            632: v = 8;
+            633: v = 4;
+            634: v = 8;
+            635: v = 6;
+            636: v = 8;
+            637: v = 2;
+            638: v = 7;
+            639: v = 2;
+            640: v = 2;
+            641: v = 7;
+            642: v = 2;
+            643: v = 6;
+            644: v = 8;
+            645: v = 8;
+            646: v = 1;
+            647: v = 4;
+            648: v = 8;
+            649: v = 0;
+            650: v = 5;
+            651: v = 6;
+            652: v = 5;
+            653: v = 5;
+            654: v = 8;
+            655: v = 6;
+            656: v = 3;
+            657: v = 4;
+            658: v = 6;
+            659: v = 8;
+            660: v = 6;
+            661: v = 6;
+            662: v = 0;
+            663: v = 3;
+            664: v = 4;
+            665: v = 5;
+            666: v = 2;
+            667: v = 2;
+            668: v = 4;
+            669: v = 5;
+            670: v = 0;
+            671: v = 3;
+            672: v = 6;
+            673: v = 4;
+            674: v = 3;
+            675: v = 0;
+            676: v = 3;
+            677: v = 2;
+            678: v = 3;
+            679: v = 1;
+            680: v = 7;
+            681: v = 6;
+            682: v = 1;
+            683: v = 6;
+            684: v = 2;
+            685: v = 1;
+            686: v = 7;
+            687: v = 8;
+            688: v = 4;
+            689: v = 5;
+            690: v = 7;
+            691: v = 3;
+            692: v = 1;
+            693: v = 8;
+            694: v = 1;
+            695: v = 6;
+            696: v = 3;
+            697: v = 3;
+            698: v = 4;
+            699: v = 0;
+            700: v = 1;
+            701: v = 6;
+            702: v = 4;
+            703: v = 6;
+            704: v = 7;
+            705: v = 3;
+            706: v = 8;
+            707: v = 7;
+            708: v = 3;
+            709: v = 3;
+            710: v = 5;
+            711: v = 2;
+            712: v = 7;
+            713: v = 1;
+            714: v = 5;
+            715: v = 1;
+            716: v = 8;
+            717: v = 4;
+            718: v = 4;
+            719: v = 8;
+            720: v = 8;
+            721: v = 4;
+            722: v = 4;
+            723: v = 0;
+            724: v = 8;
+            725: v = 7;
+            726: v = 0;
+            727: v = 7;
+            728: v = 1;
+            729: v = 6;
+            730: v = 7;
+            731: v = 4;
+            732: v = 7;
+            733: v = 7;
+            734: v = 8;
+            735: v = 6;
+            736: v = 3;
+            737: v = 6;
+            738: v = 5;
+            739: v = 0;
+            740: v = 8;
+            741: v = 5;
+            742: v = 2;
+            743: v = 6;
+            744: v = 1;
+            745: v = 4;
+            746: v = 1;
+            747: v = 8;
+            748: v = 8;
+            749: v = 6;
+            750: v = 5;
+            751: v = 6;
+            752: v = 3;
+            753: v = 4;
+            754: v = 0;
+            755: v = 4;
+            756: v = 2;
+            757: v = 2;
+            758: v = 2;
+            759: v = 3;
+            760: v = 6;
+            761: v = 4;
+            762: v = 5;
+            763: v = 6;
+            764: v = 6;
+            765: v = 1;
+            766: v = 6;
+            767: v = 0;
+            768: v = 2;
+            769: v = 3;
+            770: v = 3;
+            771: v = 3;
+            772: v = 3;
+            773: v = 7;
+            774: v = 8;
+            775: v = 4;
+            776: v = 0;
+            777: v = 8;
+            778: v = 8;
+            779: v = 1;
+            780: v = 4;
+            781: v = 4;
+            782: v = 4;
+            783: v = 2;
+            784: v = 2;
+            785: v = 6;
+            786: v = 0;
+            787: v = 7;
+            788: v = 7;
+            789: v = 0;
+            790: v = 4;
+            791: v = 4;
+            792: v = 5;
+            793: v = 4;
+            794: v = 2;
+            795: v = 8;
+            796: v = 0;
+            797: v = 1;
+            798: v = 1;
+            799: v = 7;
+            800: v = 3;
+            801: v = 0;
+            802: v = 8;
+            803: v = 6;
+            804: v = 0;
+            805: v = 3;
+            806: v = 2;
+            807: v = 8;
+            808: v = 1;
+            809: v = 7;
+            810: v = 7;
+            811: v = 5;
+            812: v = 1;
+            813: v = 0;
+            814: v = 6;
+            815: v = 5;
+            816: v = 3;
+            817: v = 3;
+            818: v = 0;
+            819: v = 4;
+            820: v = 4;
+            821: v = 0;
+            822: v = 6;
+            823: v = 0;
+            824: v = 2;
+            825: v = 7;
+            826: v = 0;
+            827: v = 2;
+            828: v = 3;
+            829: v = 8;
+            830: v = 5;
+            831: v = 7;
+            832: v = 5;
+            833: v = 7;
+            834: v = 1;
+            835: v = 4;
+            836: v = 8;
+            837: v = 8;
+            838: v = 8;
+            839: v = 3;
+            840: v = 2;
+            841: v = 1;
+            842: v = 3;
+            843: v = 3;
+            844: v = 5;
+            845: v = 5;
+            846: v = 1;
+            847: v = 5;
+            848: v = 5;
+            849: v = 4;
+            850: v = 1;
+            851: v = 0;
+            852: v = 2;
+            853: v = 8;
+            854: v = 3;
+            855: v = 0;
+            856: v = 4;
+            857: v = 4;
+            858: v = 4;
+            859: v = 5;
+            860: v = 1;
+            861: v = 5;
+            862: v = 5;
+            863: v = 0;
+            864: v = 1;
+            865: v = 1;
+            866: v = 7;
+            867: v = 7;
+            868: v = 5;
+            869: v = 4;
+            870: v = 5;
+            871: v = 8;
+            872: v = 7;
+            873: v = 7;
+            874: v = 7;
+            875: v = 3;
+            876: v = 1;
+            877: v = 4;
+            878: v = 1;
+            879: v = 7;
+            880: v = 6;
+            881: v = 1;
+            882: v = 0;
+            883: v = 3;
+            884: v = 2;
+            885: v = 1;
+            886: v = 4;
+            887: v = 8;
+            888: v = 6;
+            889: v = 3;
+            890: v = 7;
+            891: v = 4;
+            892: v = 5;
+            893: v = 7;
+            894: v = 2;
+            895: v = 8;
+            896: v = 5;
+            897: v = 7;
+            898: v = 4;
+            899: v = 1;
+            900: v = 1;
+            901: v = 7;
+            902: v = 5;
+            903: v = 3;
+            904: v = 6;
+            905: v = 5;
+            906: v = 1;
+            907: v = 8;
+            908: v = 6;
+            909: v = 8;
+            910: v = 3;
+            911: v = 0;
+            912: v = 0;
+            913: v = 7;
+            914: v = 3;
+            915: v = 3;
+            916: v = 7;
+            917: v = 1;
+            918: v = 3;
+            919: v = 3;
+            920: v = 7;
+            921: v = 4;
+            922: v = 5;
+            923: v = 2;
+            924: v = 8;
+            925: v = 7;
+            926: v = 0;
+            927: v = 4;
+            928: v = 8;
+            929: v = 1;
+            930: v = 2;
+            931: v = 7;
+            932: v = 3;
+            933: v = 6;
+            934: v = 8;
+            935: v = 7;
+            936: v = 7;
+            937: v = 7;
+            938: v = 6;
+            939: v = 2;
+            940: v = 6;
+            941: v = 6;
+            942: v = 6;
+            943: v = 4;
+            944: v = 5;
+            945: v = 8;
+            946: v = 4;
+            947: v = 4;
+            948: v = 2;
+            949: v = 8;
+            950: v = 0;
+            951: v = 1;
+            952: v = 8;
+            953: v = 2;
+            954: v = 1;
+            955: v = 4;
+            956: v = 8;
+            957: v = 8;
+            958: v = 1;
+            959: v = 3;
+            960: v = 8;
+            961: v = 1;
+            962: v = 7;
+            963: v = 3;
+            964: v = 4;
+            965: v = 6;
+            966: v = 2;
+            967: v = 3;
+            968: v = 5;
+            969: v = 8;
+            970: v = 1;
+            971: v = 6;
+            972: v = 5;
+            973: v = 4;
+            974: v = 5;
+            975: v = 2;
+            976: v = 7;
+            977: v = 8;
+            978: v = 0;
+            979: v = 2;
+            980: v = 4;
+            981: v = 0;
+            982: v = 3;
+            983: v = 0;
+            984: v = 0;
+            985: v = 5;
+            986: v = 1;
+            987: v = 8;
+            988: v = 0;
+            989: v = 2;
+            990: v = 0;
+            991: v = 6;
+            992: v = 8;
+            993: v = 1;
+            994: v = 6;
+            995: v = 1;
+            996: v = 0;
+            997: v = 5;
+            998: v = 2;
+            default: v = 4;
+        endcase
+        if (((age_out == 0) && (v == 3))) begin
+            expected_age = 1;
+        end
+        if (((age_out == 1) && (!((v == 2) || (v == 3))))) begin
+            expected_age = 0;
+        end
+        live_count <= v;
+        step <= 1;
+        @(posedge clock);
+        # 1;
+        if ((age_out == expected_age) !== 1) begin
+            $display(""*** AssertionError ***"");
+        end
+    end
+    $finish;
+end
+
+endmodule
+"
+"// File: calc_next_age.v
+// Generated by MyHDL 0.8dev
+// Date: Sun Dec 16 22:44:22 2012
+
+
+`timescale 1ns/10ps
+
+module calc_next_age (
+    age_out,
+    live_count,
+    step,
+    clock,
+    reset
+);
+
+
+output age_out;
+wire age_out;
+input [3:0] live_count;
+input step;
+input clock;
+input reset;
+
+reg age;
+
+
+
+
+
+always @(posedge clock, posedge reset) begin: CALC_NEXT_AGE_SEQ
+    reg survival;
+    reg birth;
+    if (reset == 1) begin
+        age <= 0;
+    end
+    else begin
+        birth = (live_count == 3);
+        survival = ((live_count == 2) || (live_count == 3));
+        if (step) begin
+            if (((age == 0) && birth)) begin
+                age <= 1;
+            end
+            else if (((age == 1) && (!survival))) begin
+                age <= 0;
+            end
+        end
+    end
+end
+
+
+
+assign age_out = age;
+
+endmodule
+"
+"/* Read Only with one shot on read */
+module %(MODULE)s_ro1s_reg
+  #(
+    parameter             WIDTH = 1,
+    parameter [WIDTH-1:0] RVAL  = {(WIDTH){1'b0}}
+    )
+   (
+    input                  CLK,         // Clock
+    input                  RSTn,        // Reset
+    input                  BE,          // Byte Enable
+    input                  RD,          // Write Strobe
+    input [WIDTH-1:0]      DI,          // Data In
+    output reg [WIDTH-1:0] DO,          // Data Out
+    output                 DO_1S        // One Shot
+    );
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         DO <= RVAL;
+      end else begin
+         if (WE & %(BE_LEVEL)sBE) begin
+            DO <= DI;
+         end
+      end
+   end
+
+endmodule
+
+/* Read/Write */
+module %(MODULE)s_rw_reg
+  #(
+    parameter             WIDTH = 1,
+    parameter [WIDTH-1:0] RVAL  = {(WIDTH){1'b0}}
+    )
+   (
+    input                  CLK,         // Clock
+    input                  RSTn,        // Reset
+    input                  BE,          // Byte Enable
+    input                  WE,          // Write Strobe
+    input [WIDTH-1:0]      DI,          // Data In
+    output reg [WIDTH-1:0] DO           // Data Out
+    );
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         DO <= RVAL;
+      end else begin
+         if (WE & %(BE_LEVEL)sBE) begin
+            DO <= DI;
+         end
+      end
+   end
+
+endmodule
+
+/* Read/Write, Read Only on control signal */
+module %(MODULE)s_rwpr_reg
+  #(
+    parameter             WIDTH = 1,
+    parameter [WIDTH-1:0] RVAL  = {(WIDTH){1'b0}}
+    )
+   (
+    input                  CLK,         // Clock
+    input                  RSTn,        // Reset
+    input                  BE,          // Byte Enable
+    input                  WE,          // Write Strobe
+    input                  LD,          // Write protect when high
+    input [WIDTH-1:0]      DI,          // Data In
+    output reg [WIDTH-1:0] DO           // Data Out
+    );
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         DO <= RVAL;
+      end else begin
+         if (WE & %(BE_LEVEL)sBE & ~LD) begin
+            DO <= DI;
+         end
+      end
+   end
+
+endmodule
+
+/* Read/Write, Read Only on control signal */
+module %(MODULE)s_rwpr1s_reg
+  #(
+    parameter             WIDTH = 1,
+    parameter [WIDTH-1:0] RVAL  = {(WIDTH){1'b0}}
+    )
+   (
+    input                  CLK,         // Clock
+    input                  RSTn,        // Reset
+    input                  BE,          // Byte Enable
+    input                  WE,          // Write Strobe
+    input                  LD,          // Write protect when high
+    input [WIDTH-1:0]      DI,          // Data In
+    output reg [WIDTH-1:0] DO,          // Data Out
+    output                 DO_1S        // One Shot
+    );
+
+   reg                     ws;
+   reg                     ws_d;
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         DO <= RVAL;
+      end else begin
+         if (WE & %(BE_LEVEL)sBE & ~LD) begin
+            DO <= DI;
+         end
+      end
+   end
+
+   assign DO_1S = ws & !ws_d;
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         ws <= 1'b0;
+         ws_d <= 1'b0;
+      end else begin
+         ws <= WE & %(BE_LEVEL)sBE & ~LD;
+         ws_d <= ws;
+      end
+   end
+
+endmodule
+
+/* Read/Write with one shot on write */
+module %(MODULE)s_rw1s_reg
+  #(
+    parameter             WIDTH = 1,
+    parameter [WIDTH-1:0] RVAL  = {(WIDTH){1'b0}}
+    )
+   (
+    input                  CLK,         // Clock
+    input                  RSTn,        // Reset
+    input                  BE,          // Byte Enable
+    input                  WE,          // Write Strobe
+    input [WIDTH-1:0]      DI,          // Data In
+    output reg [WIDTH-1:0] DO,          // Data Out
+    output                 DO_1S        // One Shot
+    );
+
+   reg                     ws;
+   reg                     ws_d;
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         DO <= RVAL;
+      end else begin
+         if (WE & %(BE_LEVEL)sBE) begin
+            DO <= DI;
+         end
+      end
+   end
+
+   assign DO_1S = ws & !ws_d;
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         ws <= 1'b0;
+         ws_d <= 1'b0;
+      end else begin
+         ws <= WE & %(BE_LEVEL)sBE;
+         ws_d <= ws;
+      end
+   end
+
+endmodule
+
+/* Read/Write with one shot on write */
+module %(MODULE)s_rw1s1_reg
+  #(
+    parameter             WIDTH = 1,
+    parameter [WIDTH-1:0] RVAL = {(WIDTH){1'b0}}
+    )
+   (
+    input                  CLK,         // Clock
+    input                  RSTn,        // Reset
+    input                  BE,          // Byte Enable
+    input                  WE,          // Write Strobe
+    input [WIDTH-1:0]      DI,          // Data In
+    output reg [WIDTH-1:0] DO,          // Data Out
+    output                 DO_1S        // One Shot
+    );
+
+   reg                     ws;
+   reg                     ws_d;
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         DO <= RVAL;
+      end else begin
+         if (WE & %(BE_LEVEL)sBE) begin
+            DO <= DI;
+         end else begin
+            DO <= DO;
+         end
+      end
+   end
+
+   assign DO_1S = ws & !ws_d;
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         ws <= 1'b0;
+         ws_d <= 1'b0;
+      end else begin
+         ws <= WE & %(BE_LEVEL)sBE && DI != {WIDTH{1'b0}};
+         ws_d <= ws;
+      end
+   end
+
+endmodule
+
+/* Read/Write with parallel load */
+module %(MODULE)s_rwld_reg
+  #(
+    parameter             WIDTH = 1,
+    parameter [WIDTH-1:0] RVAL  = {(WIDTH){1'b0}}
+    )
+   (
+    input                  CLK,         // Clock
+    input                  RSTn,        // Reset
+    input                  BE,          // Byte Enable
+    input                  WE,          // Write Strobe
+    input                  LD,          // Load Control
+    input [WIDTH-1:0]      DI,          // Data In
+    input [WIDTH-1:0]      IN,          // Load Data
+    output reg [WIDTH-1:0] DO           // Data Out
+    );
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         DO <= RVAL;
+      end else begin
+         if (WE & %(BE_LEVEL)sBE) begin
+            DO <= DI;
+         end else begin
+            DO <= (LD) ? IN : DO;
+         end
+      end
+   end
+
+endmodule
+
+/* Read/Write with parallel load, with one shot on write */
+module %(MODULE)s_rwld1s_reg
+  #(
+    parameter             WIDTH = 1,
+    parameter [WIDTH-1:0] RVAL  = {(WIDTH){1'b0}}
+    )
+   (
+    input                  CLK,         // Clock
+    input                  RSTn,        // Reset
+    input                  BE,          // Byte Enable
+    input                  WE,          // Write Strobe
+    input                  LD,          // Load Control
+    input [WIDTH-1:0]      DI,          // Data In
+    input [WIDTH-1:0]      IN,          // Load Data
+    output reg [WIDTH-1:0] DO,          // Data Out
+    output                 DO_1S        // One Shot
+    );
+
+   reg                     ws;
+   reg                     ws_d;
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         DO <= RVAL;
+      end else begin
+         if (WE & %(BE_LEVEL)sBE) begin
+            DO <= DI;
+         end else begin
+            DO <= (LD) ? IN : DO;
+         end
+      end
+   end
+
+   assign DO_1S = ws & !ws_d;
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         ws <= 1'b0;
+         ws_d <= 1'b0;
+      end else begin
+         ws <= WE & %(BE_LEVEL)sBE;
+         ws_d <= ws;
+      end
+   end
+
+endmodule
+
+/* Read/Write with parallel load, with one shot on write */
+module %(MODULE)s_rwld1s1_reg
+  #(
+    parameter             WIDTH = 1,
+    parameter [WIDTH-1:0] RVAL  = {(WIDTH){1'b0}}
+    )
+   (
+    input                  CLK,         // Clock
+    input                  RSTn,        // Reset
+    input                  BE,          // Byte Enable
+    input                  WE,          // Write Strobe
+    input                  LD,          // Load Control
+    input [WIDTH-1:0]      DI,          // Data In
+    input [WIDTH-1:0]      IN,          // Load Data
+    output reg [WIDTH-1:0] DO,          // Data Out
+    output                 DO_1S        // One Shot
+    );
+
+   reg                     ws;
+   reg                     ws_d;
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         DO <= RVAL;
+      end else begin
+         if (WE & %(BE_LEVEL)sBE) begin
+            DO <= DI;
+         end else begin
+            DO <= (LD) ? IN : DO;
+         end
+      end
+   end
+
+   assign DO_1S = ws & !ws_d;
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         ws <= 1'b0;
+         ws_d <= 1'b0;
+      end else begin
+         ws <= WE & %(BE_LEVEL)sBE && DI != {WIDTH{1'b0}};
+         ws_d <= ws;
+      end
+   end
+
+endmodule
+
+/* Read/write with input signal that sets bits on one */
+module %(MODULE)s_rws_reg
+  #(
+    parameter             WIDTH = 1,
+    parameter [WIDTH-1:0] RVAL  = {(WIDTH){1'b0}}
+    )
+   (
+    input                  CLK,         // Clock
+    input                  RSTn,        // Reset
+    input                  BE,          // Byte Enable
+    input                  WE,          // Write Strobe
+    input [WIDTH-1:0]      DI,          // Data In
+    input [WIDTH-1:0]      IN,          // Load Data
+    output reg [WIDTH-1:0] DO           // Data Out
+    );
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         DO <= RVAL;
+      end else begin
+         if (WE & %(BE_LEVEL)sBE) begin
+            DO <= DI;
+         end else begin
+            DO <= IN | DO;
+         end
+      end
+   end
+
+endmodule
+
+/* Read/write with input signal that sets bits on one, one shot on write */
+module %(MODULE)s_rws1s_reg
+  #(
+    parameter             WIDTH = 1,
+    parameter [WIDTH-1:0] RVAL  = {(WIDTH){1'b0}}
+    )
+   (
+    input                  CLK,         // Clock
+    input                  RSTn,        // Reset
+    input                  BE,          // Byte Enable
+    input                  WE,          // Write Strobe
+    input [WIDTH-1:0]      DI,          // Data In
+    input [WIDTH-1:0]      IN,          // Load Data
+    output reg [WIDTH-1:0] DO,          // Data Out
+    output                 DO_1S        // One Shot
+    );
+
+   reg                     ws;
+   reg                     ws_d;
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         DO <= RVAL;
+      end else begin
+         if (WE & %(BE_LEVEL)sBE) begin
+            DO <= DI;
+         end else begin
+            DO <= IN | DO;
+         end
+      end
+   end
+
+   assign DO_1S = ws & !ws_d;
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         ws <= 1'b0;
+         ws_d <= 1'b0;
+      end else begin
+         ws <= WE & %(BE_LEVEL)sBE;
+         ws_d <= ws;
+      end
+   end
+
+endmodule
+
+/* Read/write with input signal that sets bits on one, one shot on write of 1 */
+module %(MODULE)s_rws1s1_reg
+  #(
+    parameter             WIDTH = 1,
+    parameter [WIDTH-1:0] RVAL  = {(WIDTH){1'b0}}
+    )
+   (
+    input                  CLK,         // Clock
+    input                  RSTn,        // Reset
+    input                  BE,          // Byte Enable
+    input                  WE,          // Write Strobe
+    input [WIDTH-1:0]      DI,          // Data In
+    input [WIDTH-1:0]      IN,          // Load Data
+    output reg [WIDTH-1:0] DO,          // Data Out
+    output                 DO_1S        // One Shot
+    );
+
+   reg                     ws;
+   reg                     ws_d;
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         DO <= RVAL;
+      end else begin
+         if (WE & %(BE_LEVEL)sBE) begin
+            DO <= DI;
+         end else begin
+            DO <= IN | DO;
+         end
+      end
+   end
+
+   assign DO_1S = ws & !ws_d;
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         ws <= 1'b0;
+         ws_d <= 1'b0;
+      end else begin
+         ws <= WE & %(BE_LEVEL)sBE && DI != {WIDTH{1'b0}};
+         ws_d <= ws;
+      end
+   end
+
+endmodule
+
+/* Write 1 to clear, bits set on input value */
+module %(MODULE)s_w1cs_reg
+  #(
+    parameter             WIDTH = 1,
+    parameter [WIDTH-1:0] RVAL  = {(WIDTH){1'b0}}
+    )
+   (
+    input                  CLK,         // Clock
+    input                  RSTn,        // Reset
+    input                  BE,          // Byte Enable
+    input                  WE,          // Write Strobe
+    input [WIDTH-1:0]      DI,          // Data In
+    input [WIDTH-1:0]      IN,          // Load Data
+    output reg [WIDTH-1:0] DO           // Data Out
+    );
+
+   genvar                  i;
+   generate
+      for(i = 0; i < WIDTH; i = i + 1) begin : u
+         always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+            if (%(RESET_CONDITION)sRSTn) begin
+               DO[i] <= RVAL[i];
+            end else begin
+               if (WE & %(BE_LEVEL)sBE & DI[i]) begin
+                  DO[i] <= 1'b0;
+               end else begin
+                  DO[i] <= IN[i] | DO[i];
+               end
+            end
+         end
+      end
+   endgenerate
+
+endmodule
+
+/* Write 1 to clear, bits set on input value, soft clear */
+module %(MODULE)s_w1csc_reg
+  #(
+    parameter             WIDTH = 1,
+    parameter [WIDTH-1:0] RVAL  = {(WIDTH){1'b0}}
+    )
+   (
+    input                  CLK,         // Clock
+    input                  RSTn,        // Reset
+    input                  BE,          // Byte Enable
+    input                  WE,          // Write Strobe
+    input                  LD,          // Soft Clear
+    input [WIDTH-1:0]      DI,          // Data In
+    input [WIDTH-1:0]      IN,          // Load Data
+    output reg [WIDTH-1:0] DO           // Data Out
+    );
+
+   genvar                  i;
+   generate
+      for(i = 0; i < WIDTH; i = i + 1) begin : u
+         always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+            if (%(RESET_CONDITION)sRSTn) begin
+               DO[i] <= RVAL[i];
+            end else begin
+               if ((WE & %(BE_LEVEL)sBE & DI[i]) | LD) begin
+                  DO[i] <= 1'b0;
+               end else begin
+                  DO[i] <= IN[i] | DO[i];
+               end
+            end
+         end
+      end
+   endgenerate
+
+endmodule
+
+/* Write 1 to clear, bits set on input, one shot on write */
+module %(MODULE)s_w1cs1s_reg
+  #(
+    parameter             WIDTH = 1,
+    parameter [WIDTH-1:0] RVAL = {(WIDTH){1'b0}}
+    )
+   (
+    input                  CLK,         // Clock
+    input                  RSTn,        // Reset
+    input                  BE,          // Byte Enable
+    input                  WE,          // Write Strobe
+    input [WIDTH-1:0]      DI,          // Data In
+    input [WIDTH-1:0]      IN,          // Load Data
+    output reg [WIDTH-1:0] DO,          // Data Out
+    output                 DO_1S        // One Shot
+    );
+
+   reg                     ws;
+   reg                     ws_d;
+
+   genvar                  i;
+   generate
+      for(i = 0; i < WIDTH; i = i + 1) begin : u
+         always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+            if (%(RESET_CONDITION)sRSTn) begin
+               DO[i] <= RVAL[i];
+            end else begin
+               if (WE & %(BE_LEVEL)sBE & DI[i]) begin
+                  DO[i] <= 1'b0;
+               end else begin
+                  DO[i] <= IN[i] | DO[i];
+               end
+            end
+         end
+      end
+   endgenerate
+
+   assign DO_1S = ws & !ws_d;
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         ws <= 1'b0;
+         ws_d <= 1'b0;
+      end else begin
+         ws <= WE & %(BE_LEVEL)sBE;
+         ws_d <= ws;
+      end
+   end
+
+endmodule
+
+/* Write 1 to clear, bits set on input, one shot on write */
+module %(MODULE)s_w1cs1s1_reg
+  #(
+    parameter             WIDTH = 1,
+    parameter [WIDTH-1:0] RVAL = {(WIDTH){1'b0}}
+    )
+   (
+    input                  CLK,         // Clock
+    input                  RSTn,        // Reset
+    input                  BE,          // Byte Enable
+    input                  WE,          // Write Strobe
+    input [WIDTH-1:0]      DI,          // Data In
+    input [WIDTH-1:0]      IN,          // Load Data
+    output reg [WIDTH-1:0] DO,          // Data Out
+    output                 DO_1S        // One Shot
+    );
+
+   reg                     ws;
+   reg                     ws_d;
+
+   genvar                  i;
+   generate
+      for(i = 0; i < WIDTH; i = i + 1) begin : u
+         always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+            if (%(RESET_CONDITION)sRSTn) begin
+               DO[i] <= RVAL[i];
+            end else begin
+               if (WE & %(BE_LEVEL)sBE & DI[i]) begin
+                  DO[i] <= 1'b0;
+               end else begin
+                  DO[i] <= IN[i] | DO[i];
+               end
+            end
+         end
+      end
+   endgenerate
+
+   assign DO_1S = ws & !ws_d;
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         ws <= 1'b0;
+         ws_d <= 1'b0;
+      end else begin
+         ws <= WE & %(BE_LEVEL)sBE && DI != {WIDTH{1'b0}};
+         ws_d <= ws;
+      end
+   end
+
+endmodule
+
+/* Write 1 to clear, bits set on load */
+module %(MODULE)s_w1cld_reg
+  #(
+    parameter             WIDTH = 1,
+    parameter [WIDTH-1:0] RVAL  = {(WIDTH){1'b0}}
+    )
+   (
+    input                  CLK,         // Clock
+    input                  RSTn,        // Reset
+    input                  BE,          // Byte Enable
+    input                  WE,          // Write Strobe
+    input                  LD,          // Load Control
+    input [WIDTH-1:0]      DI,          // Data In
+    input [WIDTH-1:0]      IN,          // Load Data
+    output reg [WIDTH-1:0] DO           // Data Out
+    );
+
+   genvar                  i;
+   generate
+      for(i = 0; i < WIDTH; i = i + 1) begin : u
+         always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+            if (%(RESET_CONDITION)sRSTn) begin
+               DO[i] <= RVAL[i];
+            end else begin
+               if (WE & %(BE_LEVEL)sBE & DI[i]) begin
+                  DO[i] <= 1'b0 ;
+               end else begin
+                  DO[i] <= (LD & IN[i]) | DO[i];
+               end
+            end
+         end
+      end
+   endgenerate
+
+endmodule
+
+/* Write 1 to clear, bits set on input, one shot on write */
+module %(MODULE)s_w1cld1s_reg
+  #(
+    parameter             WIDTH = 1,
+    parameter [WIDTH-1:0] RVAL  = {(WIDTH){1'b0}}
+    )
+   (
+    input                  CLK,         // Clock
+    input                  RSTn,        // Reset
+    input                  BE,          // Byte Enable
+    input                  WE,          // Write Strobe
+    input [WIDTH-1:0]      DI,          // Data In
+    input [WIDTH-1:0]      IN,          // Load Data
+    input                  LD,          // Load Control
+    output reg [WIDTH-1:0] DO,          // Data Out
+    output                 DO_1S        // One Shot
+    );
+
+   reg                     ws;
+   reg                     ws_d;
+
+   genvar                  i;
+   generate
+      for(i = 0; i < WIDTH; i = i + 1) begin : u
+         always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+            if (%(RESET_CONDITION)sRSTn) begin
+               DO[i] <= RVAL[i];
+            end else begin
+               if (WE & %(BE_LEVEL)sBE & DI[i]) begin
+                  DO[i] <= 1'b0;
+               end else begin
+                  DO[i] <= (LD & IN[i]) | DO[i];
+               end
+            end
+         end
+      end
+   endgenerate
+
+   assign DO_1S = ws & !ws_d;
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         ws <= 1'b0;
+         ws_d <= 1'b0;
+      end else begin
+         ws <= WE & %(BE_LEVEL)sBE;
+         ws_d <= ws;
+      end
+   end
+
+endmodule
+
+/* Write 1 to clear, bits set on input, one shot on write */
+module %(MODULE)s_w1cld1s1_reg
+  #(
+    parameter             WIDTH = 1,
+    parameter [WIDTH-1:0] RVAL  = {(WIDTH){1'b0}}
+    )
+   (
+    input                  CLK,         // Clock
+    input                  RSTn,        // Reset
+    input                  BE,          // Byte Enable
+    input                  WE,          // Write Strobe
+    input [WIDTH-1:0]      DI,          // Data In
+    input [WIDTH-1:0]      IN,          // Load Data
+    input                  LD,          // Load Control
+    output reg [WIDTH-1:0] DO,          // Data Out
+    output                 DO_1S        // One Shot
+    );
+
+   reg                     ws;
+   reg                     ws_d;
+
+   genvar                  i;
+   generate
+      for(i = 0; i < WIDTH; i = i + 1) begin : u
+         always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+            if (%(RESET_CONDITION)sRSTn) begin
+               DO[i] <= RVAL[i];
+            end else begin
+               if (WE & %(BE_LEVEL)sBE & DI[i]) begin
+                  DO[i] <= 1'b0;
+               end else begin
+                  DO[i] <= (LD & IN[i]) | DO[i];
+               end
+            end
+         end
+      end
+   endgenerate
+
+   assign DO_1S = ws & !ws_d;
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         ws <= 1'b0;
+         ws_d <= 1'b0;
+      end else begin
+         ws <= WE & %(BE_LEVEL)sBE && DI != {WIDTH{1'b0}};
+         ws_d <= ws;
+      end
+   end
+
+endmodule
+
+/* Read only, loaded on a control signal */
+module %(MODULE)s_rold_reg
+  #(
+    parameter             WIDTH = 1,
+    parameter [WIDTH-1:0] RVAL  = {(WIDTH){1'b0}}
+    )
+   (
+    input                  CLK,         // Clock
+    input                  RSTn,        // Reset
+    input                  LD,          // Load Control
+    input [WIDTH-1:0]      IN,          // Load Data
+    output reg [WIDTH-1:0] DO           // Data Out
+    );
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         DO <= RVAL;
+      end else if (LD) begin
+         DO <= IN;
+      end
+   end
+
+endmodule
+
+/* Read only, loaded on a control signal, clear on read */
+module %(MODULE)s_rcld_reg
+  #(
+    parameter             WIDTH = 1,
+    parameter [WIDTH-1:0] RVAL  = {(WIDTH){1'b0}}
+    )
+   (
+    input                  CLK,         // Clock
+    input                  RSTn,        // Reset
+    input                  RD,          // Read Strobe
+    input                  LD,          // Load Control
+    input [WIDTH-1:0]      IN,          // Load Data
+    output reg [WIDTH-1:0] DO           // Data Out
+    );
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         DO <= RVAL;
+      end else begin
+         if (LD) begin
+            DO <= IN;
+         end else begin
+            DO <= RD ? {WIDTH{1'b0}} : DO;
+         end
+      end
+   end
+
+endmodule
+
+/* Read only, loaded on a control signal, clear on read */
+module %(MODULE)s_rv1s_reg
+  #(
+    parameter             WIDTH = 1,
+    parameter [WIDTH-1:0] RVAL  = {(WIDTH){1'b0}}
+    )
+   (
+    input              CLK,  // Clock
+    input              RSTn, // Reset
+    input              RD,   // Read Strobe
+    input [WIDTH-1:0]  IN,   // Load Data
+    output [WIDTH-1:0] DO,   // Data Out
+    output             DO_1S // One shot on read
+    );
+
+   reg                 ws;
+   reg                 ws_d;
+
+   assign DO    = IN;
+   assign DO_1S = ws & !ws_d;
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         ws <= 1'b0;
+         ws_d <= 1'b0;
+      end else begin
+         ws <= RD;
+         ws_d <= ws;
+      end
+   end
+
+endmodule
+
+/* Read only, bits set on input, clear on read */
+module %(MODULE)s_rcs_reg
+  #(
+    parameter             WIDTH = 1,
+    parameter [WIDTH-1:0] RVAL  = {(WIDTH){1'b0}}
+    )
+   (
+    input                  CLK,         // Clock
+    input                  RSTn,        // Reset
+    input                  RD,          // Read Strobe
+    input                  LD,          // Load Control
+    input [WIDTH-1:0]      IN,          // Load Data
+    output reg [WIDTH-1:0] DO           // Data Out
+    );
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         DO <= RVAL;
+      end else begin
+         if (LD) begin
+            DO <= DO | IN;
+         end else begin
+            DO <= RD ? (WIDTH(1'b0)) : DO;
+         end
+      end
+   end
+
+endmodule
+
+module %(MODULE)s_wo_reg
+  #(
+    parameter             WIDTH = 1,
+    parameter [WIDTH-1:0] RVAL  = {(WIDTH){1'b0}}
+    )
+   (
+    input  CLK,                 // Clock
+    input  RSTn,                // Reset
+    input  BE,                  // Byte Enable
+    input  WE,                  // Write Strobe
+    input  [WIDTH-1:0] DI,      // Data In
+    output [WIDTH-1:0] DO       // Data Out
+    );
+
+   reg [WIDTH-1:0] ws;
+   reg [WIDTH-1:0] ws_d;
+
+   assign DO = ws & ~ws_d;
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         ws <= {WIDTH{1'b0}};
+         ws_d <= {WIDTH{1'b0}};
+      end else begin
+         if (WE & %(BE_LEVEL)sBE) begin
+            ws <= DI;
+         end else begin
+            ws <= {WIDTH{1'b0}};
+         end
+         ws_d <= ws;
+      end
+   end
+
+endmodule
+
+
+module %(MODULE)s_w1s_reg
+  #(
+    parameter             WIDTH = 1,
+    parameter [WIDTH-1:0] RVAL  = {(WIDTH){1'b0}}
+    )
+   (
+    input                  CLK,         // Clock
+    input                  RSTn,        // Reset
+    input                  BE,          // Byte Enable
+    input                  WE,          // Write Strobe
+    input [WIDTH-1:0]      DI,          // Data In
+    input [WIDTH-1:0]      IN,          // Load Data
+    output reg [WIDTH-1:0] DO           // Data Out
+    );
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         DO <= RVAL;
+      end else begin
+         if (WE & %(BE_LEVEL)sBE) begin
+            DO <= DO | DI;
+         end else begin
+            DO <= ~(IN) & DO;
+         end
+      end
+   end
+
+endmodule
+
+module %(MODULE)s_w1s1s1_reg
+  #(
+    parameter             WIDTH = 1,
+    parameter [WIDTH-1:0] RVAL  = {(WIDTH){1'b0}}
+    )
+   (
+    input      CLK,     // Clock
+    input      RSTn,    // Reset
+    input      BE,      // Byte Enable
+    input      WE,      // Write Strobe
+    input      DI,      // Data In
+    input      IN,      // Load Data
+    output reg DO,      // Data Out
+    output     DO_1S    // One Shot
+    );
+
+   reg         ws;
+   reg         ws_d;
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         DO <= RVAL;
+      end else begin
+         if (WE & %(BE_LEVEL)sBE) begin
+            DO <= DO | DI;
+         end else begin
+            DO <= ~(IN) & DO;
+         end
+      end
+   end
+
+   assign DO_1S = ws & !ws_d;
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         ws <= 1'b0;
+         ws_d <= 1'b0;
+      end else begin
+         ws <= WE & %(BE_LEVEL)sBE && DI != {WIDTH{1'b0}};
+         ws_d <= ws;
+      end
+   end
+
+endmodule
+
+module %(MODULE)s_w1s1s_reg
+  #(
+    parameter             WIDTH = 1,
+    parameter [WIDTH-1:0] RVAL  = {(WIDTH){1'b0}}
+    )
+   (
+    input      CLK,  // Clock
+    input      RSTn, // Reset
+    input      BE,   // Byte Enable
+    input      WE,   // Write Strobe
+    input      DI,   // Data In
+    input      IN,   // Load Data
+    output reg DO,   // Data Out
+    output     DO_1S // One Shot
+    );
+
+   reg         ws;
+   reg         ws_d;
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         DO <= RVAL;
+      end else begin
+         if (WE & %(BE_LEVEL)sBE) begin
+            DO <= DO | DI;
+         end else begin
+            DO <= ~(IN) & DO;
+         end
+      end
+   end
+
+   assign DO_1S = ws & !ws_d;
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         ws <= 1'b0;
+         ws_d <= 1'b0;
+      end else begin
+         ws <= WE & %(BE_LEVEL)sBE;
+         ws_d <= ws;
+      end
+   end
+
+endmodule
+
+/* Read/write with input signal that clears bits on one */
+module %(MODULE)s_rwc_reg
+  #(
+    parameter             WIDTH = 1,
+    parameter [WIDTH-1:0] RVAL  = {(WIDTH){1'b0}}
+    )
+   (
+    input                  CLK,  // Clock
+    input                  RSTn, // Reset
+    input                  BE,   // Byte Enable
+    input                  WE,   // Write Strobe
+    input [WIDTH-1:0]      DI,   // Data In
+    input [WIDTH-1:0]      IN,   // Load Data
+    output reg [WIDTH-1:0] DO    // Data Out
+    );
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         DO <= RVAL;
+      end else begin
+         if (WE & %(BE_LEVEL)sBE) begin
+            DO <= DI;
+         end else begin
+            DO <= ~(IN) & DO;
+         end
+      end
+   end
+
+endmodule
+
+/* Read/write with input signal that clears bits on one, one shot on any write */
+module %(MODULE)s_rwc1s_reg
+  #(
+    parameter             WIDTH = 1,
+    parameter [WIDTH-1:0] RVAL  = {(WIDTH){1'b0}}
+    )
+   (
+    input                  CLK,  // Clock
+    input                  RSTn, // Reset
+    input                  BE,   // Byte Enable
+    input                  WE,   // Write Strobe
+    input [WIDTH-1:0]      DI,   // Data In
+    input [WIDTH-1:0]      IN,   // Load Data
+    output reg [WIDTH-1:0] DO,   // Data Out
+    output                 DO_1S // One Shot
+    );
+
+   reg                     ws;
+   reg                     ws_d;
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         DO <= RVAL;
+      end else begin
+         if (WE & %(BE_LEVEL)sBE) begin
+            DO <= DI;
+         end else begin
+            DO <= ~(IN) & DO;
+         end
+      end
+   end
+
+   assign DO_1S = ws & !ws_d;
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         ws <= 1'b0;
+         ws_d <= 1'b0;
+      end else begin
+         ws <= WE & %(BE_LEVEL)sBE;
+         ws_d <= ws;
+      end
+   end
+
+endmodule
+
+/* Read/write with input signal that clears bits on one, one shot on write of 1 */
+module %(MODULE)s_rwc1s1_reg
+  #(
+    parameter             WIDTH = 1,
+    parameter [WIDTH-1:0] RVAL  = {(WIDTH){1'b0}}
+    )
+   (
+    input                  CLK,  // Clock
+    input                  RSTn, // Reset
+    input                  BE,   // Byte Enable
+    input                  WE,   // Write Strobe
+    input [WIDTH-1:0]      DI,   // Data In
+    input [WIDTH-1:0]      IN,   // Load Data
+    output reg [WIDTH-1:0] DO,   // Data Out
+    output                 DO_1S // One Shot
+    );
+
+   reg                     ws;
+   reg                     ws_d;
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         DO <= RVAL;
+      end else begin
+         if (WE & %(BE_LEVEL)sBE) begin
+            DO <= DI;
+         end else begin
+            DO <= ~(IN) & DO;
+         end
+      end
+   end
+
+   assign DO_1S = ws & !ws_d;
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         ws <= 1'b0;
+         ws_d <= 1'b0;
+      end else begin
+         ws <= WE & %(BE_LEVEL)sBE && DI != {WIDTH{1'b0}};
+         ws_d <= ws;
+      end
+   end
+
+endmodule
+
+/* Read/write when reset, reset on complement */
+module %(MODULE)s_rwrc_reg
+  #(
+    parameter             WIDTH = 1,
+    parameter [WIDTH-1:0] RVAL  = {(WIDTH){1'b0}}
+    )
+   (
+    input                  CLK,  // Clock
+    input                  RSTn, // Reset
+    input                  BE,   // Byte Enable
+    input                  WE,   // Write Strobe
+    input [WIDTH-1:0]      DI,   // Data In
+    output reg [WIDTH-1:0] DO    // Data Out
+    );
+
+
+   always @(posedge CLK or %(RESET_EDGE)s RSTn) begin
+      if (%(RESET_CONDITION)sRSTn) begin
+         DO <= RVAL;
+      end else begin
+        if (WE & %(BE_LEVEL)sBE) begin
+           if (DO == RVAL) begin
+              DO <= DI;
+           end else if (DO == ~DI) begin
+              DO <= RVAL;
+           end
+        end
+      end
+   end
+endmodule
+
+"
+"LIBAVDEVICE_$MAJOR {
+        global: avdevice_*;
+        local: *;
+};
+"
+"LIBAVCODEC_$MAJOR {
+        global: *;
+};
+"
+"LIBPOSTPROC_$MAJOR {
+        global: postproc_*; pp_*;
+        local: *;
+};
+"
+"LIBAVFORMAT_$MAJOR {
+        global: *;
+};
+"
+"LIBAVUTIL_$MAJOR {
+        global: av_*; ff_*; avutil_*;
+        local: *;
+};
+"
+"LIBSWSCALE_$MAJOR {
+        global: swscale_*; sws_*; ff_*;
+        local: *;
+};
+"
+"LIBAVFILTER_$MAJOR {
+        global: avfilter_*; av_*;
+        local: *;
+};
+"
+"//=================================================================
+//  Copyright(c) Alorium Technology Group Inc., 2016
+//  ALL RIGHTS RESERVED
+//  $Id:  $
+//=================================================================
+//
+// File name:  : xlr8_top.v
+// Author      : Matt Weber
+// Contact     : support@aloriumtech.com
+// Description : Simulation model of components on the XLR8
+//                board that we\'d like to simulate, most importantly
+//                the XLR8 chip, but also various pullups and
+//                enables
+//
+//=================================================================
+///////////////////////////////////////////////////////////////////
+
+module xlr8_board  #(parameter DESIGN_CONFIG = {28\'d0, // 31:4: reserved
+                               1\'b1, //  [3]  :   1 = 16K Instruction, 0 = 8K instruction
+                               2\'d0, // [2:1]:   clock speed[1:0]
+                               1\'b1}, // [0] = CFM FACTORY (1), CFM APPLICATION (0)
+    parameter APP_XB0_ENABLE = 32\'hffff_ffff // for APPLICATION design, each bit [i]  enables XB[i]
+    )
+  (
+   //Clock and Reset
+   input        Clock, // 16MHz
+   input        RESET_N,
+   //Arduino I/Os
+   inout wire       SCL,
+   inout wire       SDA,
+   inout [13:0] Digital, // Name to match names in original testbench
+   inout [5:0]  Ana_Dig  // Name to match names in original testbench
+   );
+
+   wire        PIN13LED;
+   // We can disconnect Ana_Dig from ADC inputs if necessary (don\'t know if it is) by driving
+   //   OE low. Else leave OE as high-Z (don\'t drive it high).
+   wire [5:0]  DIG_IO;
+   wire [5:0]  DIG_IO_OE;
+   wire        ANA_UP; // Choose ADC ref between AREF pin and regulated 3.3V             
+   wire        I2C_ENABLE; // More importantly; disable pullups when doing analog read on A4/A5
+   // JTAG connector reused as digial IO. On that connector, pin 4 is power, pins 2&10 are ground
+   //   and pin 8 selects between gpio (low) and jtag (high) modes and has a pulldown.
+   wire        JT9; // external pullup. JTAG function is TDI
+   wire        JT7; // no JTAG function
+   wire        JT6; // no JTAG function
+   wire        JT5; // external pullup. JTAG function is TMS
+   wire        JT3; // JTAG function TDO
+   wire        JT1; // external pulldown, JTAG function is TCK
+   // Interface to EEPROM or other device in SOIC-8 spot on the board
+   wire        SOIC7; // WP in the case of an 24AA128SM EEPROM
+   wire        SOIC6; // SCL in the case of an 24AA128SM EEPROM
+   wire        SOIC5; // SDA in the case of an 24AA128SM EEPROM
+   wire        SOIC3; // A2 in the case of an 24AA128SM EEPROM
+   wire        SOIC2; // A1 in the case of an 24AA128SM EEPROM
+   wire        SOIC1; // A0 in the case of an 24AA128SM EEPROM
+
+   /* xlr8_top AUTO_TEMPLATE (.D\\([0-9]*\\) (Digital[\\1]),
+                              .TX          (Digital[1]),
+                              .RX          (Digital[0]),
+                              .A\\([0-9]*\\) (DIG_IO[\\1]),
+    );*/
+
+   xlr8_top xlr8_top_inst (
+                     /*AUTOINST*/
+                     // Outputs
+                     .PIN13LED          (PIN13LED),
+                     .ANA_UP            (ANA_UP),
+                     .I2C_ENABLE        (I2C_ENABLE),
+                     // Inouts
+                     .SCL               (SCL),
+                     .SDA               (SDA),
+                     .D13               (Digital[13]),           // Templated
+                     .D12               (Digital[12]),           // Templated
+                     .D11               (Digital[11]),           // Templated
+                     .D10               (Digital[10]),           // Templated
+                     .D9                (Digital[9]),            // Templated
+                     .D8                (Digital[8]),            // Templated
+                     .D7                (Digital[7]),            // Templated
+                     .D6                (Digital[6]),            // Templated
+                     .D5                (Digital[5]),            // Templated
+                     .D4                (Digital[4]),            // Templated
+                     .D3                (Digital[3]),            // Templated
+                     .D2                (Digital[2]),            // Templated
+                     .TX                (Digital[1]),            // Templated
+                     .RX                (Digital[0]),            // Templated
+                     .A5                (DIG_IO[5]),             // Templated
+                     .A4                (DIG_IO[4]),             // Templated
+                     .A3                (DIG_IO[3]),             // Templated
+                     .A2                (DIG_IO[2]),             // Templated
+                     .A1                (DIG_IO[1]),             // Templated
+                     .A0                (DIG_IO[0]),             // Templated
+                     .DIG_IO_OE         (DIG_IO_OE[5:0]),
+                     .SOIC7             (SOIC7),
+                     .SOIC6             (SOIC6),
+                     .SOIC5             (SOIC5),
+                     .SOIC3             (SOIC3),
+                     .SOIC2             (SOIC2),
+                     .SOIC1             (SOIC1),
+                     .JT9               (JT9),
+                     .JT7               (JT7),
+                     .JT6               (JT6),
+                     .JT5               (JT5),
+                     .JT3               (JT3),
+                     .JT1               (JT1),
+                     // Inputs
+                     .Clock             (Clock),
+                     .RESET_N           (RESET_N));
+  
+  // The digital I/Os will likely always have pullups, either
+  //  on the board (current plan) or in the chip (green board
+  //  prototypes).
+  pullup(Digital[13]);
+  pullup(Digital[12]);
+  pullup(Digital[11]);
+  pullup(Digital[10]);
+  pullup(Digital[9]);
+  pullup(Digital[8]);
+  pullup(Digital[7]);
+  pullup(Digital[6]);
+  pullup(Digital[5]);
+  pullup(Digital[4]);
+  pullup(Digital[3]);
+  pullup(Digital[2]);
+  pullup(Digital[1]);
+  pullup(Digital[0]);
+  // The SDA/SCL pullups can be enabled/disabled
+  // when I2C_ENABLE is high, we should get pullups,
+  // when it is low, we should just set high-Z on
+  // SDA/SCL
+  rnmos Q19a (SDA,1\'b1,I2C_ENABLE); // (r)esistive version of nmos
+  rnmos Q19b (SCL,1\'b1,I2C_ENABLE); // should reduce 1\'b1 to pull strength
+  // DIG_IO_OE are used to disconnect the digital I/O
+  //  side of A5..A0 from the analog input side
+  //  When DIG_IO_OE is 0 they are disconnected, when
+  //   it is high-Z they are connected, when it is a
+  //   1 they are also connected, but bad, or at least
+  //   unintended things, could happen in the circuits
+  //   because the pullups are to 5V
+  pullup(DIG_IO_OE[5]);
+  pullup(DIG_IO_OE[4]);
+  pullup(DIG_IO_OE[3]);
+  pullup(DIG_IO_OE[2]);
+  pullup(DIG_IO_OE[1]);
+  pullup(DIG_IO_OE[0]);
+  tranif1(Ana_Dig[0],DIG_IO[0],DIG_IO_OE[0]);
+  tranif1(Ana_Dig[1],DIG_IO[1],DIG_IO_OE[1]);
+  tranif1(Ana_Dig[2],DIG_IO[2],DIG_IO_OE[2]);
+  tranif1(Ana_Dig[3],DIG_IO[3],DIG_IO_OE[3]);
+  tranif1(Ana_Dig[4],DIG_IO[4],DIG_IO_OE[4]);
+  tranif1(Ana_Dig[5],DIG_IO[5],DIG_IO_OE[5]);
+                
+endmodule: xlr8_board
+// Local Variables:
+// verilog-library-flags:(""-y ../../../rtl/"")
+// End:
+                
+"
+"///////////////////////////////////////////////////////////////////
+//=================================================================
+//  Copyright (c) Alorium Technology 2016
+//  ALL RIGHTS RESERVED
+//  $Id:  $
+//=================================================================
+//
+// File name:  : openxlr8.v
+// Author      : Steve Phillips
+// Description : Wrapper module to hold instantiations of 
+//               OpenXLR8 XB modules.
+//
+// This module is edited by the OpenXLR8 user to instantiate their
+// XB(s) into the design. This module provides the input, output and
+// control signals needed to connect the XB(s) into the logic in the
+// top verilog module. Some wiring is required beyond simply
+// instantiating the XB, especially in the case of multiple XBs, but
+// the comments included here should explain what is needed.
+//
+// This file is organized in to several sections with helpful 
+// comments in each. The sections are:
+//
+// 1.) Parameters
+//     NUM_PINS should not be edited, but NUM_OXBS should be set 
+//     to the number of XBs being instantiated in this file.
+// 2.) Inputs and Outputs
+//     No changes should be needed here. The inputs and outputs 
+//     are defined.
+// 3.) Regs and Wires
+//     This section starts with some required wire definitions 
+//     and then provides hints for addition regs and wires that 
+//     may be needed, You\'ll going to need to add at least a 
+//     few lines here.
+// 4.) Instantiate XBs
+//     This is where all the XBs should be specified by instantiating
+//     the XB module and setting the xbs_* signals for that XB. The
+//     basic template should be repeated for each XB being used. Don\'t
+//     forget to set the NUM_OXBS value back in section 1 to match the
+//     number of XBs!
+// 5.) Combining logic
+//     This section begins with some logic to cobine the xbs_* signals
+//     into the xb_* signals needed for the outputs. Then there are
+//     some hints and examples for how to write the logic to combine
+//     the dbusout and out_en signals from the XBs.
+// 6.) Interrupt logic 
+//     This section instantiates the xlr8_pcint.v module if there are
+//     interrupts needed for the OpenXLR8 implementation. The OpenXLR8
+//     module has a single IRQ output that ties into the AVR interrupt
+//     handler.
+//
+//=================================================================
+///////////////////////////////////////////////////////////////////
+`include ""xb_adr_pack.vh""
+
+module openxlr8
+  //======================================================================
+  // Normally the instantiation parameters and module I/O would be
+  // listed inline here. To make the module more easily updated, that
+  // code has been moved to an include file located in the XLR8Core. It
+  // is inserted here at compile time.
+`include ""../../../XLR8Core/extras/rtl/openxlr8_module_io.vh""
+
+  // Listed below is the instantiation parameters and module I/O of
+  // the current version. It is listed only to provide an example of
+  // what they should be. To see the actual code, see the file
+  // included above.
+
+  /* === Beginning of Sample Instantiation Parameters and Module I/O ===
+  // ----------------------------------------------------------------------
+  // 1.) Parameters
+
+  #(
+    parameter DESIGN_CONFIG = 8,
+    //    {
+    //     25\'d0, // [31:14] - reserved
+    //     8\'h8,  // [13:6]  - MAX10 Size,  ex: 0x8 = M08, 0x32 = M50
+    //     1\'b0,  //   [5]   - ADC_SWIZZLE, 0 = XLR8,            1 = Sno
+    //     1\'b0,  //   [4]   - PLL Speed,   0 = 16MHz PLL,       1 = 50Mhz PLL
+    //     1\'b1,  //   [3]   - PMEM Size,   0 = 8K (Sim Kludge), 1 = 16K
+    //     2\'d0,  //  [2:1]  - Clock Speed, 0 = 16MHZ,           1 = 32MHz, 2 = 64MHz, 3=na
+    //     1\'b0   //   [0]   - FPGA Image,  0 = CFM Application, 1 = CFM Factory
+    //     },
+    
+    parameter NUM_PINS = 20,// Default is Arduino Uno Digital 0-13 + Analog 0-5
+    // NUM_PINS should be 20 for the XLR8 board, ?? for the Sno board
+    
+    parameter OX8ICR_Address = 8\'h31,
+    parameter OX8IFR_Address = 8\'h32,
+    parameter OX8MSK_Address = 8\'h33
+    // The OX8*_Address parameters are used to control the interrupt module
+    
+    )
+   //----------------------------------------------------------------------
+   
+   //----------------------------------------------------------------------
+   // 2.) Inputs and Outputs
+   (
+    // Clock and Reset
+    // The clk input is the CPU core frequency, which could be 16, 32 or 64MHZ 
+    // depending on how the image was built
+    input                       clk, //       Clock
+    input                       rstn, //      Reset 
+    // These three clocks are always the stated frequency, regardless of the CPU 
+    // core frequency
+    input                       clk_64mhz, // 64MHz clock
+    input                       clk_32mhz, // 32MHz clock
+    input                       clk_16mhz, // 16MHz clock
+    input                       clk_option2, // Default: 64MHz, 45 degrees phase
+    input                       clk_option4, // Default: 32MHz, 22.5 degrees phase
+    // These enables have one shot pulses at the stated intrevals 
+    input                       en16mhz, //   Enable for  16MHz timer
+    input                       en1mhz, //    Enable for   1MHz timer
+    input                       en128khz, //  Enable for 128KHz timer
+    // I/O 
+    input [5:0]                 adr, //       Reg Address
+    input [7:0]                 dbus_in, //   Data Bus Input
+    output [7:0]                dbus_out, //  Data Bus Output
+    output                      io_out_en, // IO Output Enable
+    input                       iore, //      IO Reade Enable
+    input                       iowe, //      IO Write Enable
+    // DM
+    input [7:0]                 ramadr, //    RAM Address
+    input                       ramre, //     RAM Read Enable
+    input                       ramwe, //     RAM Write Enable
+    input                       dm_sel, //    DM Select
+    input [7:0]                 dm_dout_rg,// dout held during cpuwait, for UART
+
+    // Other
+    input [255:0]               gprf, //      Direct RO access to Reg File
+    input [NUM_PINS-1:0]        xb_pinx, //   pin inputs
+    inout                       JT9, //       JTAG pin
+    inout                       JT7, //       JTAG pin
+    inout                       JT6, //       JTAG pin
+    inout                       JT5, //       JTAG pin
+    inout                       JT3, //       JTAG pin
+    inout                       JT1, //       JTAG pin
+    // For iomux
+    output logic [NUM_PINS-1:0] xb_ddoe, //   override data direction
+    output logic [NUM_PINS-1:0] xb_ddov, //   data direction value if 
+                                         //     overridden (1=output)
+    output logic [NUM_PINS-1:0] xb_pvoe, //   override output value
+    output logic [NUM_PINS-1:0] xb_pvov, //    output value if overridden
+    // Interrupts
+    output logic                xb_irq //    To core
+    );
+   //----------------------------------------------------------------------
+      === End of Sample Instantiation Parameters and Module I/O === */
+
+   
+   //----------------------------------------------------------------------
+   // 3.) Params, Regs and Wires declarations
+   //
+
+  parameter NUM_OXBS  = 1; // !! EDIT THIS LINE !!
+   // NUM_OXBS should equal the number of XBs being instantiated within
+   // this module. However, in the case where no XB is being
+   // instantiated, the value should be set to 1 rather than zero, so
+   // that the logic compiles correctly and we can still provide the
+   // correct output values. Called it NUM_OXBS for OpenXLR8 XBs, to 
+   // differentiate is from the NUM_XBS parameter used in the top.
+   
+   
+   // These are required:
+
+   logic [NUM_OXBS-1:0][NUM_PINS-1:0] xbs_ddoe;
+   logic [NUM_OXBS-1:0][NUM_PINS-1:0] xbs_ddov;
+   logic [NUM_OXBS-1:0][NUM_PINS-1:0] xbs_pvoe;
+   logic [NUM_OXBS-1:0][NUM_PINS-1:0] xbs_pvov;
+   
+   // Add additional wires and regs here as needed to connect your XBs
+   // to the combining logic and to each other if needed. At minimum,
+   // with a single XB, you\'ll need at least something like this:
+   
+   logic [7:0]     spi_dbusout;
+   logic           spi_io_out_en;
+   logic           misoo, mosio;
+   logic           scko;
+   logic           spe;
+   logic           spimaster;
+   logic           ss_b;
+   logic           sckiii;  // FIXME: This is a hack, should probably remove
+                            //        the scki input to this module and
+                            //        make this the real scki
+   
+   //----------------------------------------------------------------------
+   
+   
+   //----------------------------------------------------------------------
+   // 4.) Instantiate XBs
+   
+   //----------------------------------------------------------------------
+   // Instantiate XB module and configure control signals
+   //
+
+   assign sckiii = xb_pinx[7];
+   assign misoi  = xb_pinx[6];
+   assign mosii  = xb_pinx[5];
+   assign ss_b   = xb_pinx[4];
+   
+   avr_spi
+     xlr8_spi_inst
+       (
+        // AVR Control
+        .adr        (adr),
+        .dbus_in    (dbus_in),
+        .dbus_out   (spi_dbusout),
+        .iore       (iore),
+        .iowe       (iowe),
+        .out_en     (spi_io_out_en),
+        // IRQ
+        .spiirq      (/* removing IRQ for extra SPI */),
+        .spiack      (/* removing IRQ for extra SPI */),
+        // Slave Programming Mode
+        .por         (1\'b0),
+        .spiextload  (1\'b0),
+        .spidwrite   (/*Not used*/),
+        .spiload     (/*Not used*/),
+        
+        // Outputs
+        .misoo       (misoo),
+        .mosio       (mosio),
+        .scko        (scko),
+        .spe         (spe),
+        .spimaster   (spimaster),
+        // Inputs
+        .rst_n       (rstn),
+        .clk         (clk),
+        .clken       (1\'b1),
+        // Former parameters converted to inputs
+        .param_design_config   (DESIGN_CONFIG),
+        .param_spcr_address    (XB_SPCR_Address),
+        .param_spsr_address    (XB_SPSR_Address),
+        .param_spdr_address    (XB_SPDR_Address),
+        .clk_scki    (clk_scki),
+        .misoi       (misoi),       // miso is assigned to D5
+        .mosii       (mosii),
+        .scki        (sckiii),
+        .ss_b        (ss_b),
+        .ramadr      (ramadr[7:0]),
+        .ramre       (ramre),
+        .ramwe       (ramwe),
+        .dm_sel      (dm_sel)
+        );
+   
+   // Set pin control bits for the above XB. If no XBs are being
+   // instantiated then leave these lines uncommented so values will
+   // be zeros
+   //
+   // NOTE: The xbs_* assign statements are required for every XB
+   // instantiated, even if it doesn\'t talk to the I/O. In that case
+   // the xbs_* busses should be tied low, as shown below.
+   
+   // Here are some definitions of the signals and guidelines for 
+   // definition:
+   //
+   // xbs_ddoe: This controls whether the xbs_ddov signal will be able
+   // to control the I/O pin. Setting this to a one allows xbs_ddov to
+   // control the pin direction.
+   //
+   // xbs_ddov: If the corresponding xbs_ddoe bit is set, then this
+   // controls the direction of the I/O pin. Setting xbs_ddov to a one
+   // will make the pin an output, setting it to a zero will make it
+   // an input.
+   //
+   // xbs_pvoe: This controls whether the xbs_pvov signal will be able
+   // to control the I/O pin. Setting this to a one allows xbs_pvov to
+   // control the pin value.
+   //
+   // xbs_pvov: If the corresponding xbs_pvoe bit is set, then this
+   // controls the value of the I/O pin. If the xbs_ddoe and xbs_ddov
+   // signals have set the pin to be an out put, then, if xbs_pvoe is
+   // set, the value of xbs_pvov will be the output value of the pin.
+   //
+   // Most often, the xbs_ddoe and xbs_ddov signals are controlled by
+   // the software library corresponding to the XB being
+   // instantiated. If the XB uses output pins, the the XB should
+   // provide signals as outputs from the XB that should be connected
+   // to the xbs_pvoe and xbs_pvov signals.
+   
+   // The following was added for XLR8SPI
+   
+   assign sck_ddoe  = spe && ~spimaster;
+   assign sck_ddov  = 1\'b0;
+   assign sck_pvoe  = spe && spimaster;
+   assign sck_pvov  = scko;
+ 
+   assign miso_ddoe = spe;
+   assign miso_ddov = ~spimaster && ~ss_b;
+   assign miso_pvoe = spe && ~spimaster;
+   assign miso_pvov = misoo;
+
+   assign mosi_ddoe = spe && ~spimaster;
+   assign mosi_ddov = 1\'b0;
+   assign mosi_pvoe = spe && spimaster;
+   assign mosi_pvov = spe && mosio;
+
+   assign ss_b_ddoe = spe && ~spimaster;
+   assign ss_b_ddov = 1\'b0;
+   assign ss_b_pvoe = 1\'b0;
+   assign ss_b_pvov = 1\'b0;
+
+   // On XLR8/UNO, bus is [19:0]={portc[5:0],portb[5:0],portd[7:0]}
+   // Assigning the SPI to D7:D4  {sck,     miso,     mosi,     ss_b     }
+   assign xbs_ddoe[0] = {12\'h000, {sck_ddoe,miso_ddoe,mosi_ddoe,ss_b_ddoe}, 4\'h0}; 
+   assign xbs_ddov[0] = {12\'h000, {sck_ddov,miso_ddov,mosi_ddov,ss_b_ddov}, 4\'h0};
+   assign xbs_pvoe[0] = {12\'h000, {sck_pvoe,miso_pvoe,mosi_pvoe,ss_b_pvoe}, 4\'h0};
+   assign xbs_pvov[0] = {12\'h000, {sck_pvov,miso_pvov,mosi_pvov,ss_b_pvov}, 4\'h0};
+
+   // End of XB instantiation
+   //----------------------------------------------------------------------
+
+
+   //----------------------------------------------------------------------
+   // Additional XB instantiations
+   //
+   // You can add additional XB instantiations as was done above by
+   // repeating the above format for each additional XB. Each must
+   // include the instantiation of the XB module and the definition of
+   // the xbs_* signals.
+   //----------------------------------------------------------------------
+   
+   
+   //----------------------------------------------------------------------
+   // 5.) Combine control and busses from multiple XB instantiations
+   //
+   // Combine the pin control signals from each of the XB
+   // instantiations by wire ORing then to form a single set of busses
+
+
+   //     -- \\/ -- Do not edit the below lines -- \\/ --
+   always_comb begin
+      // Initialize to zero
+      xb_ddoe = {NUM_PINS{1\'b0}};
+      xb_ddov = {NUM_PINS{1\'b0}};
+      xb_pvoe = {NUM_PINS{1\'b0}};
+      xb_pvov = {NUM_PINS{1\'b0}};
+      // Wire OR the pin control signals together
+      for (int i=0;i<NUM_OXBS;i++) begin
+\t xb_ddoe = xb_ddoe | xbs_ddoe[i];
+\t xb_ddov = xb_ddov | (xbs_ddoe[i] & xbs_ddov[i]);
+\t xb_pvoe = xb_pvoe | xbs_pvoe[i];
+\t xb_pvov = xb_pvov | (xbs_pvoe[i] & xbs_pvov[i]);
+      end
+   end
+   //     -- /\\ -- Do not edit the above lines -- /\\ --
+
+   // Combine the dbusout and io_out_en signals from the instantiated
+   // XBs here and then pass them up to the xlr8_top.
+   //
+   // Here is an example for a single XB:  
+   //   assign dbus_out  = xb1_out_en ? xb1_dbusout : 8\'h00;
+   //   assign io_out_en = xb1_out_en;
+   //      
+   // Here is an example for three XBs (xb1, xb2 and xb3):
+   //   assign dbus_out  = xb1_out_en ? xb1_dbusout :
+   //                      xb2_out_en ? xb2_dbusout :
+   //                      xb3_out_en ? xb3_dbusout :
+   //                                   8\'h00;
+   //   assign io_out_en = xb1_out_en || 
+   //                      xb2_out_en ||
+   //                      xb3_out_en;
+   //
+   // If no XBs are being instantiated then set values to zero like 
+   // this:
+   // assign dbus_out = 8\'h00;
+   // assign io_out_en = 1\'h0;
+   
+   assign dbus_out  = spi_io_out_en ? spi_dbusout : 8\'h00;
+   assign io_out_en = spi_io_out_en;
+   
+   // End of combining logic
+   //----------------------------------------------------------------------
+
+   
+   //----------------------------------------------------------------------
+   // 6.) Interrupts
+   //
+   // If you need to have interrupts for you XBs, then delete the
+   // following line that ties off the xb_irq output and instead
+   // uncomment the following instantiation of the xlr8_pcint module
+
+   assign xb_irq = 1\'b0; // DELETE THIS LINE IF YOU UNCOMMENT THE XLR8_PCINT
+   
+/* 
+   localparam NUM_INTS = 1; // EDIT to be equal to the number of interrupts
+
+   xlr8_pcint
+     #(
+       .XICR_Address (OX8ICR_Address),
+       .XIFR_Address (OX8IFR_Address),
+       .XMSK_Address (OX8MSK_Address),
+       .WIDTH        (NUM_INTS)
+       )
+   xb_pcint_inst
+     (
+      // Clock and Reset
+      .rstn         (rstn),
+      .clk          (clk),
+      // I/O
+      .adr          (adr),
+      .dbus_in      (dbusin),
+      .dbus_out     (dbus_out),
+      .iore         (iore),
+      .iowe         (iowe),
+      .out_en       (io_out_en),
+      // DM
+      .ramadr       (ramadr),
+      .ramre        (ramre),
+      .ramwe        (ramwe),
+      .dm_sel       (dm_sel),
+      // 
+      .x_int_in     (), // INSERT YOUR XB INTERRUPTS HERE 
+      .x_irq        (xb_irq),
+      .x_irq_ack    () // Don\'t use acks here
+      );
+*/   
+   
+endmodule // openxlr8
+
+"
+"module alu_control ( 
+  input [5:0] funct,
+  input [1:0] alu_op,
+  output [3:0] aluctrl);
+
+  always @(*) begin
+    case(funct
+  end
+
+endmodule
+"
+"`include ""../lib/mux_16to1.v""
+
+module test;
+
+  reg  [3:0] s;
+  reg  i15, i14, i13, i12, i11, i10, i9, i8, i7, i6, i5, i4, i3, i2, i1, i0;
+  wire z;
+
+  mux_16to1 mux(
+    .s  (s ),
+    .i15(i15),   
+    .i14(i14),
+    .i13(i13),
+    .i12(i12),
+    .i11(i11),
+    .i10(i10),
+    .i9 (i9 ),
+    .i8 (i8 ),
+    .i7 (i7 ),
+    .i6 (i6 ),
+    .i5 (i5 ),
+    .i4 (i4 ),
+    .i3 (i3 ),
+    .i2 (i2 ),
+    .i1 (i1 ),
+    .i0 (i0 ),
+    .z  (z ));
+  
+  initial begin
+    $monitor($time, "":  %b  %b  %b  %b  %b  %b  %b  %b  %b  %b  %b  %b  %b  %b  %b  %b | %b  %b  %b  %b | %b"",
+                      i15, i14, i13, i12,i11,i10,i9, i8,i7, i6, i5, i4, i3, i2, i1, i0,s[3], s[2],s[1],s[0],z);
+        
+    #5 i15  = 0; i14  = 0; i13  = 0; i12  = 0; i11 = 0; i10 = 0; i9 = 0; i8 = 0;  
+       i7   = 0; i6   = 0; i5   = 0; i4   = 0; i3  = 0; i2  = 0; i1 = 0; i0 = 0; 
+       s[3] = 0; s[2] = 0; s[1] = 0; s[0] = 0;
+
+    #5 i4 = 1; i5 = 1; i2 = 1; s[1] = 1; // 010 select i2
+    #5 s[0] = 1; // 0011 select i3
+    #5 s[2] = 1; // 0111 select i7
+    #5 i7 = 0;
+    #5 s[1] = 0; // 0101 select i5
+    #5 i15  = 1; s[1] = 1; s[3] = 1; //1111 select i15
+    #5 i10 = 1; s[0] = 0; s[2] = 0; // 1010 select i10
+  end
+
+// 0000 0
+// 0001 1
+// 0010 2
+// 0011 3
+// 0100 4
+// 0101 5
+// 0110 6
+// 0111 7
+// 1000 8
+// 1001 9
+// 1010 10
+// 1011 11
+// 1100 12
+// 1101 13
+// 1110 14
+// 1111 15
+ 
+endmodule
+"
+"/* Generated by Yosys 0.4+19 (git sha1 abf81d7, clang 3.4-1ubuntu3 -fPIC -Os) */
+
+(* src = ""../control/control.v:1"" *)
+module control(op, alu_op, regDst, aluSrc, memToReg, regWrite, memRead, memWrite, branch);
+  (* src = ""../control/control.v:2"" *)
+  input [5:0] op;
+  (* src = ""../control/control.v:3"" *)
+  output [1:0] alu_op;
+  (* src = ""../control/control.v:4"" *)
+  output regDst;
+  (* src = ""../control/control.v:4"" *)
+  output aluSrc;
+  (* src = ""../control/control.v:4"" *)
+  output memToReg;
+  (* src = ""../control/control.v:4"" *)
+  output regWrite;
+  (* src = ""../control/control.v:5"" *)
+  output memRead;
+  (* src = ""../control/control.v:5"" *)
+  output memWrite;
+  (* src = ""../control/control.v:5"" *)
+  output branch;
+  (* src = ""../control/control.v:8"" *)
+  wire int0;
+  (* src = ""../control/control.v:8"" *)
+  wire op0_bar;
+  (* src = ""../control/control.v:8"" *)
+  wire op1_bar;
+  (* src = ""../control/control.v:8"" *)
+  wire op2_bar;
+  (* src = ""../control/control.v:8"" *)
+  wire op3_bar;
+  (* src = ""../control/control.v:8"" *)
+  wire op4_bar;
+  (* src = ""../control/control.v:8"" *)
+  wire op5_bar;
+  (* src = ""../control/control.v:17"" *)
+  wire _00_;
+  (* src = ""../control/control.v:17"" *)
+  wire _01_;
+  (* src = ""../control/control.v:17"" *)
+  wire _02_;
+  (* src = ""../control/control.v:17"" *)
+  wire _03_;
+  (* src = ""../control/control.v:18"" *)
+  wire _04_;
+  (* src = ""../control/control.v:18"" *)
+  wire _05_;
+  (* src = ""../control/control.v:20"" *)
+  wire _06_;
+  (* src = ""../control/control.v:20"" *)
+  wire _07_;
+  (* src = ""../control/control.v:20"" *)
+  wire _08_;
+  (* src = ""../control/control.v:20"" *)
+  wire _09_;
+  (* src = ""../control/control.v:22"" *)
+  wire _10_;
+  (* src = ""../control/control.v:22"" *)
+  wire _11_;
+  (* src = ""../control/control.v:22"" *)
+  wire _12_;
+  (* src = ""../control/control.v:25"" *)
+  wire _13_;
+  (* src = ""../control/control.v:25"" *)
+  wire _14_;
+  assign op0_bar = ~op[0];
+  assign op1_bar = ~op[1];
+  assign op2_bar = ~op[2];
+  assign op3_bar = ~op[3];
+  assign op4_bar = ~op[4];
+  assign op5_bar = ~op[5];
+  assign _00_ = op5_bar & op4_bar;
+  assign _01_ = _00_ & op3_bar;
+  assign _02_ = _01_ & op[2];
+  assign _03_ = _02_ & op1_bar;
+  assign alu_op[0] = _03_ & op0_bar;
+  assign _04_ = _01_ & op2_bar;
+  assign _05_ = _04_ & op1_bar;
+  assign alu_op[1] = _05_ & op0_bar;
+  assign _06_ = op[5] & op4_bar;
+  assign _07_ = _06_ & op3_bar;
+  assign _08_ = _07_ & op2_bar;
+  assign _09_ = _08_ & op[1];
+  assign int0 = _09_ & op[0];
+  assign _10_ = _06_ & op[3];
+  assign _11_ = _10_ & op2_bar;
+  assign _12_ = _11_ & op[1];
+  assign memWrite = _12_ & op[0];
+  assign _13_ = _06_ & op2_bar;
+  assign _14_ = _13_ & op[1];
+  assign aluSrc = _14_ & op[0];
+  assign regWrite = int0 | alu_op[1];
+  assign regDst = alu_op[1];
+  assign memToReg = int0;
+  assign memRead = int0;
+  assign branch = alu_op[0];
+endmodule
+"
+"`include ""../RF/reg_32bits.v""
+`include ""../lib/mux32bits_32to1.v""
+`include ""../lib/dec_5to32.v""
+
+module reg_file (
+  input  [4:0]  readReg1, readReg2, writeReg,
+  input  [31:0] writeData,
+  input regWrite, clk,
+  output [31:0] readData1, readData2);
+
+  wire [31:0] regOutput0, regOutput1, regOutput2, regOutput3, regOutput4, regOutput5, regOutput6, regOutput7, regOutput8, regOutput9, regOutput10, regOutput11, regOutput12, regOutput13, regOutput14, regOutput15, regOutput16, regOutput17, regOutput18, regOutput19, regOutput20, regOutput21, regOutput22, regOutput23, regOutput24, regOutput25, regOutput26, regOutput27, regOutput28, regOutput29, regOutput30, regOutput31; 
+
+  wire [31:0] regInput0, regInput1, regInput2, regInput3, regInput4, regInput5, regInput6, regInput7, regInput8, regInput9, regInput10, regInput11, regInput12, regInput13, regInput14, regInput15, regInput16, regInput17, regInput18, regInput19, regInput20, regInput21, regInput22, regInput23, regInput24, regInput25, regInput26, regInput27, regInput28, regInput29, regInput30, regInput31;
+
+  wire [31:0] we, int;
+  wire [31:0] regOutput [31:0];
+
+  dec_5to32 dec (.b(int), .a(writeReg));
+
+  and (we[0 ], regWrite, int[0 ]);
+  and (we[1 ], regWrite, int[1 ]);
+  and (we[2 ], regWrite, int[2 ]);
+  and (we[3 ], regWrite, int[3 ]);
+  and (we[4 ], regWrite, int[4 ]);
+  and (we[5 ], regWrite, int[5 ]);
+  and (we[6 ], regWrite, int[6 ]);
+  and (we[7 ], regWrite, int[7 ]);
+  and (we[8 ], regWrite, int[8 ]);
+  and (we[9 ], regWrite, int[9 ]);
+  and (we[10], regWrite, int[10]);
+  and (we[11], regWrite, int[11]);
+  and (we[12], regWrite, int[12]);
+  and (we[13], regWrite, int[13]);
+  and (we[14], regWrite, int[14]);
+  and (we[15], regWrite, int[15]);
+  and (we[16], regWrite, int[16]);
+  and (we[17], regWrite, int[17]);
+  and (we[18], regWrite, int[18]);
+  and (we[19], regWrite, int[19]);
+  and (we[20], regWrite, int[20]);
+  and (we[21], regWrite, int[21]);
+  and (we[22], regWrite, int[22]);
+  and (we[23], regWrite, int[23]);
+  and (we[24], regWrite, int[24]);
+  and (we[25], regWrite, int[25]);
+  and (we[26], regWrite, int[26]);
+  and (we[27], regWrite, int[27]);
+  and (we[28], regWrite, int[28]);
+  and (we[29], regWrite, int[29]);
+  and (we[30], regWrite, int[30]);
+  and (we[31], regWrite, int[31]);
+
+  reg_32bits reg0 (.d(1\'b0     ), .q(regOutput0 ), .we(1\'b1  ), .clk(clk));
+  reg_32bits reg1 (.d(writeData), .q(regOutput1 ), .we(we[1 ]), .clk(clk));
+  reg_32bits reg2 (.d(writeData), .q(regOutput2 ), .we(we[2 ]), .clk(clk));
+  reg_32bits reg3 (.d(writeData), .q(regOutput3 ), .we(we[3 ]), .clk(clk));
+  reg_32bits reg4 (.d(writeData), .q(regOutput4 ), .we(we[4 ]), .clk(clk));
+  reg_32bits reg5 (.d(writeData), .q(regOutput5 ), .we(we[5 ]), .clk(clk));
+  reg_32bits reg6 (.d(writeData), .q(regOutput6 ), .we(we[6 ]), .clk(clk));
+  reg_32bits reg7 (.d(writeData), .q(regOutput7 ), .we(we[7 ]), .clk(clk));
+  reg_32bits reg8 (.d(writeData), .q(regOutput8 ), .we(we[8 ]), .clk(clk));
+  reg_32bits reg9 (.d(writeData), .q(regOutput9 ), .we(we[9 ]), .clk(clk));
+  reg_32bits reg10(.d(writeData), .q(regOutput10), .we(we[10]), .clk(clk));
+  reg_32bits reg11(.d(writeData), .q(regOutput11), .we(we[11]), .clk(clk));
+  reg_32bits reg12(.d(writeData), .q(regOutput12), .we(we[12]), .clk(clk));
+  reg_32bits reg13(.d(writeData), .q(regOutput13), .we(we[13]), .clk(clk));
+  reg_32bits reg14(.d(writeData), .q(regOutput14), .we(we[14]), .clk(clk));
+  reg_32bits reg15(.d(writeData), .q(regOutput15), .we(we[15]), .clk(clk));
+  reg_32bits reg16(.d(writeData), .q(regOutput16), .we(we[16]), .clk(clk));
+  reg_32bits reg17(.d(writeData), .q(regOutput17), .we(we[17]), .clk(clk));
+  reg_32bits reg18(.d(writeData), .q(regOutput18), .we(we[18]), .clk(clk));
+  reg_32bits reg19(.d(writeData), .q(regOutput19), .we(we[19]), .clk(clk));
+  reg_32bits reg20(.d(writeData), .q(regOutput20), .we(we[20]), .clk(clk));
+  reg_32bits reg21(.d(writeData), .q(regOutput21), .we(we[21]), .clk(clk));
+  reg_32bits reg22(.d(writeData), .q(regOutput22), .we(we[22]), .clk(clk));
+  reg_32bits reg23(.d(writeData), .q(regOutput23), .we(we[23]), .clk(clk));
+  reg_32bits reg24(.d(writeData), .q(regOutput24), .we(we[24]), .clk(clk));
+  reg_32bits reg25(.d(writeData), .q(regOutput25), .we(we[25]), .clk(clk));
+  reg_32bits reg26(.d(writeData), .q(regOutput26), .we(we[26]), .clk(clk));
+  reg_32bits reg27(.d(writeData), .q(regOutput27), .we(we[27]), .clk(clk));
+  reg_32bits reg28(.d(writeData), .q(regOutput28), .we(we[28]), .clk(clk));
+  reg_32bits reg29(.d(writeData), .q(regOutput29), .we(we[29]), .clk(clk));
+  reg_32bits reg30(.d(writeData), .q(regOutput30), .we(we[30]), .clk(clk));
+  reg_32bits reg31(.d(writeData), .q(regOutput31), .we(we[31]), .clk(clk));
+
+
+  mux32bits_32to1 rd1(.z(readData1), .s(readReg1),  .i0(regOutput0), .i1(regOutput1), .i2(regOutput2), .i3(regOutput3), .i4(regOutput4), .i5(regOutput5), .i6(regOutput6), .i7(regOutput7), .i8(regOutput8), .i9(regOutput9), .i10(regOutput10), .i11(regOutput11), .i12(regOutput12), .i13(regOutput13), .i14(regOutput14), .i15(regOutput15), .i16(regOutput16), .i17(regOutput17), .i18(regOutput18), .i19(regOutput19), .i20(regOutput20), .i21(regOutput21), .i22(regOutput22), .i23(regOutput23), .i24(regOutput24), .i25(regOutput25), .i26(regOutput26), .i27(regOutput27), .i28(regOutput28), .i29(regOutput29), .i30(regOutput30), .i31(regOutput31));
+
+
+  mux32bits_32to1 rd2(.z(readData2), .s(readReg2),  .i0(regOutput0), .i1(regOutput1), .i2(regOutput2), .i3(regOutput3), .i4(regOutput4), .i5(regOutput5), .i6(regOutput6), .i7(regOutput7), .i8(regOutput8), .i9(regOutput9), .i10(regOutput10), .i11(regOutput11), .i12(regOutput12), .i13(regOutput13), .i14(regOutput14), .i15(regOutput15), .i16(regOutput16), .i17(regOutput17), .i18(regOutput18), .i19(regOutput19), .i20(regOutput20), .i21(regOutput21), .i22(regOutput22), .i23(regOutput23), .i24(regOutput24), .i25(regOutput25), .i26(regOutput26), .i27(regOutput27), .i28(regOutput28), .i29(regOutput29), .i30(regOutput30), .i31(regOutput31));
+
+endmodule
+"
+"module control (
+    input [5:0] op,
+    output [2:0] alu_op,
+    output regDst0, regDst1, aluSrc, memToReg0, memToReg1, regWrite,
+    output memRead, memWrite, branch, branch_ne, jump
+  );
+
+  reg addi, andi, lw, sw, ori, beq, bne, j, jal, slti, r_format, x_found;
+
+  always @(*) begin
+    
+    addi     <= 1'b0;
+    lw       <= 1'b0;
+    sw       <= 1'b0;
+    ori      <= 1'b0;
+    beq      <= 1'b0;
+    bne      <= 1'b0;
+    j        <= 1'b0;
+    jal      <= 1'b0;
+    andi     <= 1'b0;
+    ori      <= 1'b0;
+    r_format <= 1'b0;
+    x_found  <= 1'b0;
+    case (op)
+      6'dx      : x_found  <= 1'b1;
+      6'b001000 : addi     <= 1'b1; 
+      6'b100011 : lw       <= 1'b1; 
+      6'b101011 : sw       <= 1'b1; 
+      6'b000100 : beq      <= 1'b1; 
+      6'b000101 : bne      <= 1'b1; 
+      6'b000010 : j        <= 1'b1; 
+      6'b000011 : jal      <= 1'b1; 
+      6'b001010 : slti     <= 1'b1; 
+      6'b000000 : r_format <= 1'b1;
+      6'b001100 : andi     <= 1'b1;
+      6'b001101 : ori      <= 1'b1;
+      6'b001000 : andi      <= 1'b1;
+    endcase
+  end
+
+  assign regDst0 = r_format & (~x_found);
+  assign regDst1 = jal & (~x_found);
+  assign aluSrc = (lw | sw | andi | ori | addi) & (~x_found);
+  assign memToReg0 = lw & (~x_found);
+  assign memToReg1 = jal & (~x_found);
+  assign regWrite = (r_format | lw | andi | ori | addi | jal) & (~x_found);
+  assign memRead = lw & (~x_found);
+  assign memWrite = sw & (~x_found); 
+  assign branch = (beq) & (~x_found);
+  assign branch_ne = (bne) & (~x_found);
+  assign jump = (j | jal) & (~x_found);
+  assign alu_op[0] = (beq | bne | andi) & (~x_found);
+  assign alu_op[1] = (r_format | andi) & (~x_found);
+  assign alu_op[2] = ori & (~x_found);
+  
+endmodule
+"
+"`define AND 0000
+`define OR  4'b0001
+`define ADD 4'b0010
+`define SUB 4'b0110
+`define SLT 4'b0111
+`define NOR 4'b1100
+`define AND_FUNCT 6'b100100
+`define OR_FUNCT  6'b100101
+`define ADD_FUNCT 6'b100000
+`define SUB_FUNCT 6'b100010
+`define SLT_FUNCT 6'b101010
+`define NOR_FUNCT 6'b100111
+`define SLL_FUNCT 6'b000000
+`define LW   3'b000 //lw || sw || addi
+`define BEQ  3'b001
+`define ORI  3'b100 
+`define ANDI 3'b011
+
+module alu_control (
+  input [5:0] funct,
+  input [2:0] alu_op,
+  output [3:0] aluctrl );
+
+  reg [3:0] funct_val;
+  
+  reg [3:0] aluctrl_val;
+  
+  always @(*) begin
+    case(funct)
+      `AND_FUNCT  : funct_val =  `AND;
+      `OR_FUNCT   : funct_val =  `OR ;
+      `ADD_FUNCT  : funct_val =  `ADD;
+      `SUB_FUNCT  : funct_val =  `SUB;
+      `SLT_FUNCT  : funct_val =  `SLT;
+      `NOR_FUNCT  : funct_val =  `NOR;
+      default: funct_val= 0;
+    endcase
+  end  
+  
+  always @(*) begin
+    
+    aluctrl_val <= 0;
+    
+    case (alu_op)
+      `LW  : aluctrl_val <= 4'd2;//lw sw addi
+      `BEQ : aluctrl_val <= 4'd6;//branch
+      `ORI : aluctrl_val <= 4'd1;//ori
+      `ANDI: aluctrl_val <= 4'd0;//andi
+      3'd2 : aluctrl_val <= funct_val;//r type
+      default: aluctrl_val <= 0;
+    endcase
+  end
+
+  assign aluctrl = aluctrl_val;
+
+endmodule
+"
+"
+module fileio; 
+ integer in,out,mon;
+ reg clk;
+ 
+ reg  enable;
+ wire valid;
+ reg [31:0] din;
+ reg [31:0] exp;
+ wire [31:0] dout;
+ integer statusI,statusO;
+ 
+ dut dut (clk,enable,din,dout,valid);
+ 
+ initial begin
+   clk = 0;
+   enable  = 0;
+   din = 0;
+   exp = 0;
+   in  = $fopen(""input.txt"",""r"");
+   out = $fopen(""output.txt"",""r"");
+   mon = $fopen(""monitor.txt"",""w"");
+ end
+ 
+ always  #  1 clk = ~clk;
+ 
+ // DUT input driver code
+ initial begin
+     repeat (10) @ (posedge clk);
+     while ( ! $feof(in)) begin
+       @ (negedge clk);
+       enable = 1;
+       statusI = $fscanf(in,""%h %h\
+"",din[31:16],din[15:0]);
+       @ (negedge clk);
+       enable = 0;
+     end
+     repeat (10) @ (posedge clk);
+     $fclose(in);
+     $fclose(out);
+     $fclose(mon);
+      #100  $finish;
+ end
+ 
+ // DUT output monitor and compare logic
+ always @ (posedge clk)
+  if (valid) begin
+    $fwrite(mon,""%h %h\
+"",dout[31:16],dout[15:0]);
+    statusO = $fscanf(out,""%h %h\
+"",exp[31:16],exp[15:0]);
+    if (dout  ! == exp) begin
+      $display(""%0dns Error : input and output does not match"",$time);
+      $display(""       Got  %h"",dout);
+      $display(""       Exp  %h"",exp);
+    end else begin
+      $display(""%0dns Match : input and output match"",$time);
+      $display(""       Got  %h"",dout);
+      $display(""       Exp  %h"",exp);
+    end
+  end
+ 
+ endmodule
+ 
+ // DUT model
+ module dut(
+   input wire clk,enable,
+   input wire [31:0] din,
+   output reg [31:0] dout,
+   output reg       valid
+ );
+ 
+ always @ (posedge clk)
+   begin
+     dout  <= din + 1;
+     valid  <= enable;
+   end
+ 
+ endmodule
+"
+"module sign_extend (
+  input  [15:0] a,
+  output [31:0] b);
+
+buf (b[31], a[15]);
+buf (b[30], a[15]);
+buf (b[29], a[15]);
+buf (b[28], a[15]);
+buf (b[27], a[15]);
+buf (b[26], a[15]);
+buf (b[25], a[15]);
+buf (b[24], a[15]);
+buf (b[23], a[15]);
+buf (b[22], a[15]);
+buf (b[21], a[15]);
+buf (b[20], a[15]);
+buf (b[19], a[15]);
+buf (b[18], a[15]);
+buf (b[17], a[15]);
+buf (b[16], a[15]);
+buf (b[15], a[15]);
+buf (b[14], a[14]);
+buf (b[13], a[13]);
+buf (b[12], a[12]);
+buf (b[11], a[11]);
+buf (b[10], a[10]);
+buf (b[9 ], a[9 ]);
+buf (b[8 ], a[8 ]);
+buf (b[7 ], a[7 ]);
+buf (b[6 ], a[6 ]);
+buf (b[5 ], a[5 ]);
+buf (b[4 ], a[4 ]);
+buf (b[3 ], a[3 ]);
+buf (b[2 ], a[2 ]);
+buf (b[1 ], a[1 ]);
+buf (b[0 ], a[0 ]);
+
+endmodule
+"
+"module control (
+    input [5:0] op,
+    output [1:0] alu_op,
+    output regDst, aluSrc, memToReg, regWrite,
+    output memRead, memWrite, branch
+  );
+
+wire int0, op0_bar, op1_bar, op2_bar, op3_bar, op4_bar, op5_bar;
+
+not (op0_bar, op[0]);
+not (op1_bar, op[1]);
+not (op2_bar, op[2]);
+not (op3_bar, op[3]);
+not (op4_bar, op[4]);
+not (op5_bar, op[5]);
+
+and (alu_op[0], op5_bar, op4_bar, op3_bar, op[2]  , op1_bar, op0_bar); 
+and (alu_op[1], op5_bar, op4_bar, op3_bar, op2_bar, op1_bar, op0_bar); 
+and (regDst   , op5_bar, op4_bar, op3_bar, op2_bar, op1_bar, op0_bar); 
+and (memToReg , op[5]  , op4_bar, op3_bar, op2_bar, op[1]  , op[0]  );
+and (memRead  , op[5]  , op4_bar, op3_bar, op2_bar, op[1]  , op[0]  ); 
+and (memWrite , op[5]  , op4_bar, op[3]  , op2_bar, op[1]  , op[0]  ); 
+and (branch   , op5_bar, op4_bar, op3_bar, op[2]  , op1_bar, op0_bar); 
+and (int0     , op[5]  , op4_bar, op3_bar, op2_bar, op[1]  , op[0]  );
+and (aluSrc   , op[5]  , op4_bar, op2_bar, op[1]  , op[0] ); 
+or  (regWrite , int0   , alu_op[1]);
+
+endmodule
+"
+"`include ""../mem/im.v""
+`include ""../RF/reg_file2.v""
+`include ""../ALU/alu.v""
+`include ""../lib/mux5bit_2to1_2.v""
+`include ""../lib/mux32bit_4to1.v""
+`include ""../lib/mux32bit_2to1.v""
+`include ""../lib/mux32bit_2to1_2.v""
+`include ""../lib/sign_extend.v""
+`include ""../control/control2.v""
+`include ""../ALU/alu_control2.v""
+`include ""../mem/dm.v""
+`include ""../lib/shift_left_2.v""
+`include ""../lib/jump_addr.v""
+
+module cpu(input clk,
+           output [31:0] alu_output, data, nxt_pc);
+
+  reg [31:0] pc;
+  wire [31:0] readData1, readData2, b;
+  wire regDest0, regDst1, regWrite, aluSrc, zero, memToReg0, memToReg1; 
+  wire memRead, memWrite, branch, branch_ne, s_branch, jump;
+  wire [31:0] sExtended, alu_output, memData, writeData, j_addr, mux3_output, mux4_output;
+  wire [3:0] alu_ctrl;
+  wire [2:0] alu_op;
+  wire [4:0] writeReg;
+  wire [31:0] fa1_output, ex_shifted, pc_4;
+  initial pc <= 32\'d0;
+  im i_mem(.clk(clk),
+           .data(data),
+           .addr(pc));
+  mux5bit_4to1 mux0(.i0(data[20:16]), 
+.i1(data[15:11]), 
+.i2(5\'d31), 
+.s({regDst1, regDst0}), 
+.z(writeReg));
+
+  reg_file        rf(.readReg1(data[25:21]),
+                     .readReg2(data[20:16]),
+                     .writeReg(writeReg),
+                     .clk(clk),
+                     .regWrite(regWrite),
+                     .readData1(readData1),
+                     .readData2(readData2),
+                     .writeData(writeData));
+
+  sign_extend     se(.a(data[15:0]), .b(sExtended));
+  mux32bit_2to1   mux1(.i0(readData2),
+                       .i1(sExtended), 
+                       .s(aluSrc), 
+                       .z(b));
+
+  alu             main_alu(.op(alu_ctrl), .a(readData1), .b(b), .z(alu_output), .zero(zero));
+  alu_control     ac  (.funct(data[5:0]), .alu_op(alu_op), .aluctrl(alu_ctrl));
+  control         c(.op(data[31:26]), 
+                    .alu_op(alu_op), 
+                    .regDst0(regDst0), 
+                    .regDst1(regDst1), 
+                    .aluSrc(aluSrc), 
+                    .memToReg0(memToReg0), 
+                    .memToReg1(memToReg1), 
+                    .regWrite(regWrite), 
+                    .memRead(memRead), 
+                    .memWrite(memWrite), 
+                    .branch(branch),
+                    .branch_ne(branch_ne),
+                    .jump(jump));
+  dm mem(.clk(clk), .addr(alu_output), .writeData(readData2), .memWrite(memWrite), .memRead(memRead), .readData(memData));  
+  
+  mux32bit_4to1 mux2(.i0(alu_output), .i1(memData), .i2(pc_4), .s({memToReg1, memToReg0}), .z(writeData));
+  shift_left_2 sll2(.a(sExtended), .b(ex_shifted));
+
+  //alu             fa1(.op(4\'d2), .a(pc_4), .b(ex_shifted), .z(fa1_output));
+  alu             fa1(.op(4\'d2), .a(pc_4), .b(sExtended), .z(fa1_output));
+  wire int0, int1;
+  and (int0, branch, zero);
+  and (int1, branch_ne, ~zero);
+  or (s_branch, int0, int1);
+  wire jr;
+  and and1(jr , ~data[5], ~data[4], data[3], ~data[2], ~data[1], ~data[0]
+              , ~data[26], ~data[27],~data[28], ~data[29], ~data[30], ~data[31] ); 
+  //always @(*) jr =  ~data[26] & ~data[27] & data[28] & ~data[29] & ~data[30] & ~data[31]; 
+  jump_addr ja(.inst(data[25:0]), .pc_4(pc_4[31:28]), .j_addr(j_addr));
+
+  //mux32bit_2to1 mux3(.i0(pc_4), .i1(fa1_output), .s(s_branch), .z(nxt_pc));
+  mux32bit_2to1_2 mux3(.i0(pc_4), .i1(fa1_output), .s(s_branch), .z(mux3_output));
+  mux32bit_2to1_2 mux4(.i0(mux3_output), .i1(j_addr), .s(jump), .z(mux4_output));
+  mux32bit_2to1_2 mux5(.i1(readData1), .i0(mux4_output), .z(nxt_pc), .s(jr)); 
+
+  //mux32bit_2to1 mux4(.i1(j_addr), .i0(mux3_output), .z(nxt_pc), .s(jump)); 
+    
+  alu             fa2(.op(4\'d2), .a(pc), .b(32\'d1), .z(pc_4));
+  
+  always @(posedge clk) begin
+    pc <= nxt_pc;
+  end
+  
+endmodule
+"
+"`include ""../lib/mux_2to1.v""
+
+module d_flip_flop (
+  input d, clk, we,
+  output q, q_bar);
+
+wire int0, int1, ff_input;
+
+mux_2to1 mux(
+    .z(ff_input),
+    .i0(q),
+    .i1(d),
+    .s(we));
+
+nand (int0, ff_input, clk);
+nand (int1, int0    , clk);
+
+nand (q    , int0, q_bar);
+nand (q_bar, int1, q    );
+
+endmodule
+"
+"`include ""../lib/mux_32to1.v""
+
+module mux32bits_32to1 (
+  input  [4:0 ] s,
+  input  [31:0] i31, i30, i29, i28, i27, i26, i25, i24, i23,i22, i21, i20, i19, i18, i17, i16,
+  input  [31:0] i15, i14, i13, i12, i11, i10, i9, i8, i7,i6, i5, i4, i3, i2, i1, i0,
+  output [31:0] z);
+
+mux_32to1 mux0 (.z(z[0 ]), .i31(i31[0 ]), .i30(i30[0 ]), .i29(i29[0 ]), .i28(i28[0 ]), .i27(i27[0 ]), .i26(i26[0 ]), .i25(i25[0 ]), .i24(i24[0 ]), .i23(i23[0 ]), .i22(i22[0 ]), .i21(i21[0 ]), .i20(i20[0 ]), .i19(i19[0 ]), .i18(i18[0 ]), .i17(i17[0 ]), .i16(i16[0 ]), .i15(i15[0 ]), .i14(i14[0 ]), .i13(i13[0 ]), .i12(i12[0 ]), .i11(i11[0 ]), .i10(i10[0 ]), .i9(i9[0 ]), .i8(i8[0 ]), .i7(i7[0 ]), .i6(i6[0 ]), .i5(i5[0 ]), .i4(i4[0 ]), .i3(i3[0 ]), .i2(i2[0 ]), .i1(i1[0 ]), .i0(i0[0 ]), .s(s));
+
+mux_32to1 mux1 (.z(z[1 ]), .i31(i31[1 ]), .i30(i30[1 ]), .i29(i29[1 ]), .i28(i28[1 ]), .i27(i27[1 ]), .i26(i26[1 ]), .i25(i25[1 ]), .i24(i24[1 ]), .i23(i23[1 ]), .i22(i22[1 ]), .i21(i21[1 ]), .i20(i20[1 ]), .i19(i19[1 ]), .i18(i18[1 ]), .i17(i17[1 ]), .i16(i16[1 ]), .i15(i15[1 ]), .i14(i14[1 ]), .i13(i13[1 ]), .i12(i12[1 ]), .i11(i11[1 ]), .i10(i10[1 ]), .i9(i9[1 ]), .i8(i8[1 ]), .i7(i7[1 ]), .i6(i6[1 ]), .i5(i5[1 ]), .i4(i4[1 ]), .i3(i3[1 ]), .i2(i2[1 ]), .i1(i1[1 ]), .i0(i0[1 ]), .s(s));
+
+mux_32to1 mux2 (.z(z[2 ]), .i31(i31[2 ]), .i30(i30[2 ]), .i29(i29[2 ]), .i28(i28[2 ]), .i27(i27[2 ]), .i26(i26[2 ]), .i25(i25[2 ]), .i24(i24[2 ]), .i23(i23[2 ]), .i22(i22[2 ]), .i21(i21[2 ]), .i20(i20[2 ]), .i19(i19[2 ]), .i18(i18[2 ]), .i17(i17[2 ]), .i16(i16[2 ]), .i15(i15[2 ]), .i14(i14[2 ]), .i13(i13[2 ]), .i12(i12[2 ]), .i11(i11[2 ]), .i10(i10[2 ]), .i9(i9[2 ]), .i8(i8[2 ]), .i7(i7[2 ]), .i6(i6[2 ]), .i5(i5[2 ]), .i4(i4[2 ]), .i3(i3[2 ]), .i2(i2[2 ]), .i1(i1[2 ]), .i0(i0[2 ]), .s(s));
+
+mux_32to1 mux3 (.z(z[3 ]), .i31(i31[3 ]), .i30(i30[3 ]), .i29(i29[3 ]), .i28(i28[3 ]), .i27(i27[3 ]), .i26(i26[3 ]), .i25(i25[3 ]), .i24(i24[3 ]), .i23(i23[3 ]), .i22(i22[3 ]), .i21(i21[3 ]), .i20(i20[3 ]), .i19(i19[3 ]), .i18(i18[3 ]), .i17(i17[3 ]), .i16(i16[3 ]), .i15(i15[3 ]), .i14(i14[3 ]), .i13(i13[3 ]), .i12(i12[3 ]), .i11(i11[3 ]), .i10(i10[3 ]), .i9(i9[3 ]), .i8(i8[3 ]), .i7(i7[3 ]), .i6(i6[3 ]), .i5(i5[3 ]), .i4(i4[3 ]), .i3(i3[3 ]), .i2(i2[3 ]), .i1(i1[3 ]), .i0(i0[3 ]), .s(s));
+
+mux_32to1 mux4 (.z(z[4 ]), .i31(i31[4 ]), .i30(i30[4 ]), .i29(i29[4 ]), .i28(i28[4 ]), .i27(i27[4 ]), .i26(i26[4 ]), .i25(i25[4 ]), .i24(i24[4 ]), .i23(i23[4 ]), .i22(i22[4 ]), .i21(i21[4 ]), .i20(i20[4 ]), .i19(i19[4 ]), .i18(i18[4 ]), .i17(i17[4 ]), .i16(i16[4 ]), .i15(i15[4 ]), .i14(i14[4 ]), .i13(i13[4 ]), .i12(i12[4 ]), .i11(i11[4 ]), .i10(i10[4 ]), .i9(i9[4 ]), .i8(i8[4 ]), .i7(i7[4 ]), .i6(i6[4 ]), .i5(i5[4 ]), .i4(i4[4 ]), .i3(i3[4 ]), .i2(i2[4 ]), .i1(i1[4 ]), .i0(i0[4 ]), .s(s));
+
+mux_32to1 mux5 (.z(z[5 ]), .i31(i31[5 ]), .i30(i30[5 ]), .i29(i29[5 ]), .i28(i28[5 ]), .i27(i27[5 ]), .i26(i26[5 ]), .i25(i25[5 ]), .i24(i24[5 ]), .i23(i23[5 ]), .i22(i22[5 ]), .i21(i21[5 ]), .i20(i20[5 ]), .i19(i19[5 ]), .i18(i18[5 ]), .i17(i17[5 ]), .i16(i16[5 ]), .i15(i15[5 ]), .i14(i14[5 ]), .i13(i13[5 ]), .i12(i12[5 ]), .i11(i11[5 ]), .i10(i10[5 ]), .i9(i9[5 ]), .i8(i8[5 ]), .i7(i7[5 ]), .i6(i6[5 ]), .i5(i5[5 ]), .i4(i4[5 ]), .i3(i3[5 ]), .i2(i2[5 ]), .i1(i1[5 ]), .i0(i0[5 ]), .s(s));
+
+mux_32to1 mux6 (.z(z[6 ]), .i31(i31[6 ]), .i30(i30[6 ]), .i29(i29[6 ]), .i28(i28[6 ]), .i27(i27[6 ]), .i26(i26[6 ]), .i25(i25[6 ]), .i24(i24[6 ]), .i23(i23[6 ]), .i22(i22[6 ]), .i21(i21[6 ]), .i20(i20[6 ]), .i19(i19[6 ]), .i18(i18[6 ]), .i17(i17[6 ]), .i16(i16[6 ]), .i15(i15[6 ]), .i14(i14[6 ]), .i13(i13[6 ]), .i12(i12[6 ]), .i11(i11[6 ]), .i10(i10[6 ]), .i9(i9[6 ]), .i8(i8[6 ]), .i7(i7[6 ]), .i6(i6[6 ]), .i5(i5[6 ]), .i4(i4[6 ]), .i3(i3[6 ]), .i2(i2[6 ]), .i1(i1[6 ]), .i0(i0[6 ]), .s(s));
+
+mux_32to1 mux7 (.z(z[7 ]), .i31(i31[7 ]), .i30(i30[7 ]), .i29(i29[7 ]), .i28(i28[7 ]), .i27(i27[7 ]), .i26(i26[7 ]), .i25(i25[7 ]), .i24(i24[7 ]), .i23(i23[7 ]), .i22(i22[7 ]), .i21(i21[7 ]), .i20(i20[7 ]), .i19(i19[7 ]), .i18(i18[7 ]), .i17(i17[7 ]), .i16(i16[7 ]), .i15(i15[7 ]), .i14(i14[7 ]), .i13(i13[7 ]), .i12(i12[7 ]), .i11(i11[7 ]), .i10(i10[7 ]), .i9(i9[7 ]), .i8(i8[7 ]), .i7(i7[7 ]), .i6(i6[7 ]), .i5(i5[7 ]), .i4(i4[7 ]), .i3(i3[7 ]), .i2(i2[7 ]), .i1(i1[7 ]), .i0(i0[7 ]), .s(s));
+
+mux_32to1 mux8 (.z(z[8 ]), .i31(i31[8 ]), .i30(i30[8 ]), .i29(i29[8 ]), .i28(i28[8 ]), .i27(i27[8 ]), .i26(i26[8 ]), .i25(i25[8 ]), .i24(i24[8 ]), .i23(i23[8 ]), .i22(i22[8 ]), .i21(i21[8 ]), .i20(i20[8 ]), .i19(i19[8 ]), .i18(i18[8 ]), .i17(i17[8 ]), .i16(i16[8 ]), .i15(i15[8 ]), .i14(i14[8 ]), .i13(i13[8 ]), .i12(i12[8 ]), .i11(i11[8 ]), .i10(i10[8 ]), .i9(i9[8 ]), .i8(i8[8 ]), .i7(i7[8 ]), .i6(i6[8 ]), .i5(i5[8 ]), .i4(i4[8 ]), .i3(i3[8 ]), .i2(i2[8 ]), .i1(i1[8 ]), .i0(i0[8 ]), .s(s));
+
+mux_32to1 mux9 (.z(z[9 ]), .i31(i31[9 ]), .i30(i30[9 ]), .i29(i29[9 ]), .i28(i28[9 ]), .i27(i27[9 ]), .i26(i26[9 ]), .i25(i25[9 ]), .i24(i24[9 ]), .i23(i23[9 ]), .i22(i22[9 ]), .i21(i21[9 ]), .i20(i20[9 ]), .i19(i19[9 ]), .i18(i18[9 ]), .i17(i17[9 ]), .i16(i16[9 ]), .i15(i15[9 ]), .i14(i14[9 ]), .i13(i13[9 ]), .i12(i12[9 ]), .i11(i11[9 ]), .i10(i10[9 ]), .i9(i9[9 ]), .i8(i8[9 ]), .i7(i7[9 ]), .i6(i6[9 ]), .i5(i5[9 ]), .i4(i4[9 ]), .i3(i3[9 ]), .i2(i2[9 ]), .i1(i1[9 ]), .i0(i0[9 ]), .s(s));
+
+mux_32to1 mux10(.z(z[10]), .i31(i31[10]), .i30(i30[10]), .i29(i29[10]), .i28(i28[10]), .i27(i27[10]), .i26(i26[10]), .i25(i25[10]), .i24(i24[10]), .i23(i23[10]), .i22(i22[10]), .i21(i21[10]), .i20(i20[10]), .i19(i19[10]), .i18(i18[10]), .i17(i17[10]), .i16(i16[10]), .i15(i15[10]), .i14(i14[10]), .i13(i13[10]), .i12(i12[10]), .i11(i11[10]), .i10(i10[10]), .i9(i9[10]), .i8(i8[10]), .i7(i7[10]), .i6(i6[10]), .i5(i5[10]), .i4(i4[10]), .i3(i3[10]), .i2(i2[10]), .i1(i1[10]), .i0(i0[10]), .s(s));
+
+mux_32to1 mux11(.z(z[11]), .i31(i31[11]), .i30(i30[11]), .i29(i29[11]), .i28(i28[11]), .i27(i27[11]), .i26(i26[11]), .i25(i25[11]), .i24(i24[11]), .i23(i23[11]), .i22(i22[11]), .i21(i21[11]), .i20(i20[11]), .i19(i19[11]), .i18(i18[11]), .i17(i17[11]), .i16(i16[11]), .i15(i15[11]), .i14(i14[11]), .i13(i13[11]), .i12(i12[11]), .i11(i11[11]), .i10(i10[11]), .i9(i9[11]), .i8(i8[11]), .i7(i7[11]), .i6(i6[11]), .i5(i5[11]), .i4(i4[11]), .i3(i3[11]), .i2(i2[11]), .i1(i1[11]), .i0(i0[11]), .s(s));
+
+mux_32to1 mux12(.z(z[12]), .i31(i31[12]), .i30(i30[12]), .i29(i29[12]), .i28(i28[12]), .i27(i27[12]), .i26(i26[12]), .i25(i25[12]), .i24(i24[12]), .i23(i23[12]), .i22(i22[12]), .i21(i21[12]), .i20(i20[12]), .i19(i19[12]), .i18(i18[12]), .i17(i17[12]), .i16(i16[12]), .i15(i15[12]), .i14(i14[12]), .i13(i13[12]), .i12(i12[12]), .i11(i11[12]), .i10(i10[12]), .i9(i9[12]), .i8(i8[12]), .i7(i7[12]), .i6(i6[12]), .i5(i5[12]), .i4(i4[12]), .i3(i3[12]), .i2(i2[12]), .i1(i1[12]), .i0(i0[12]), .s(s));
+
+mux_32to1 mux13(.z(z[13]), .i31(i31[13]), .i30(i30[13]), .i29(i29[13]), .i28(i28[13]), .i27(i27[13]), .i26(i26[13]), .i25(i25[13]), .i24(i24[13]), .i23(i23[13]), .i22(i22[13]), .i21(i21[13]), .i20(i20[13]), .i19(i19[13]), .i18(i18[13]), .i17(i17[13]), .i16(i16[13]), .i15(i15[13]), .i14(i14[13]), .i13(i13[13]), .i12(i12[13]), .i11(i11[13]), .i10(i10[13]), .i9(i9[13]), .i8(i8[13]), .i7(i7[13]), .i6(i6[13]), .i5(i5[13]), .i4(i4[13]), .i3(i3[13]), .i2(i2[13]), .i1(i1[13]), .i0(i0[13]), .s(s));
+
+mux_32to1 mux14(.z(z[14]), .i31(i31[14]), .i30(i30[14]), .i29(i29[14]), .i28(i28[14]), .i27(i27[14]), .i26(i26[14]), .i25(i25[14]), .i24(i24[14]), .i23(i23[14]), .i22(i22[14]), .i21(i21[14]), .i20(i20[14]), .i19(i19[14]), .i18(i18[14]), .i17(i17[14]), .i16(i16[14]), .i15(i15[14]), .i14(i14[14]), .i13(i13[14]), .i12(i12[14]), .i11(i11[14]), .i10(i10[14]), .i9(i9[14]), .i8(i8[14]), .i7(i7[14]), .i6(i6[14]), .i5(i5[14]), .i4(i4[14]), .i3(i3[14]), .i2(i2[14]), .i1(i1[14]), .i0(i0[14]), .s(s));
+
+mux_32to1 mux15(.z(z[15]), .i31(i31[15]), .i30(i30[15]), .i29(i29[15]), .i28(i28[15]), .i27(i27[15]), .i26(i26[15]), .i25(i25[15]), .i24(i24[15]), .i23(i23[15]), .i22(i22[15]), .i21(i21[15]), .i20(i20[15]), .i19(i19[15]), .i18(i18[15]), .i17(i17[15]), .i16(i16[15]), .i15(i15[15]), .i14(i14[15]), .i13(i13[15]), .i12(i12[15]), .i11(i11[15]), .i10(i10[15]), .i9(i9[15]), .i8(i8[15]), .i7(i7[15]), .i6(i6[15]), .i5(i5[15]), .i4(i4[15]), .i3(i3[15]), .i2(i2[15]), .i1(i1[15]), .i0(i0[15]), .s(s));
+
+mux_32to1 mux16(.z(z[16]), .i31(i31[16]), .i30(i30[16]), .i29(i29[16]), .i28(i28[16]), .i27(i27[16]), .i26(i26[16]), .i25(i25[16]), .i24(i24[16]), .i23(i23[16]), .i22(i22[16]), .i21(i21[16]), .i20(i20[16]), .i19(i19[16]), .i18(i18[16]), .i17(i17[16]), .i16(i16[16]), .i15(i15[16]), .i14(i14[16]), .i13(i13[16]), .i12(i12[16]), .i11(i11[16]), .i10(i10[16]), .i9(i9[16]), .i8(i8[16]), .i7(i7[16]), .i6(i6[16]), .i5(i5[16]), .i4(i4[16]), .i3(i3[16]), .i2(i2[16]), .i1(i1[16]), .i0(i0[16]), .s(s));
+
+mux_32to1 mux17(.z(z[17]), .i31(i31[17]), .i30(i30[17]), .i29(i29[17]), .i28(i28[17]), .i27(i27[17]), .i26(i26[17]), .i25(i25[17]), .i24(i24[17]), .i23(i23[17]), .i22(i22[17]), .i21(i21[17]), .i20(i20[17]), .i19(i19[17]), .i18(i18[17]), .i17(i17[17]), .i16(i16[17]), .i15(i15[17]), .i14(i14[17]), .i13(i13[17]), .i12(i12[17]), .i11(i11[17]), .i10(i10[17]), .i9(i9[17]), .i8(i8[17]), .i7(i7[17]), .i6(i6[17]), .i5(i5[17]), .i4(i4[17]), .i3(i3[17]), .i2(i2[17]), .i1(i1[17]), .i0(i0[17]), .s(s));
+
+mux_32to1 mux18(.z(z[18]), .i31(i31[18]), .i30(i30[18]), .i29(i29[18]), .i28(i28[18]), .i27(i27[18]), .i26(i26[18]), .i25(i25[18]), .i24(i24[18]), .i23(i23[18]), .i22(i22[18]), .i21(i21[18]), .i20(i20[18]), .i19(i19[18]), .i18(i18[18]), .i17(i17[18]), .i16(i16[18]), .i15(i15[18]), .i14(i14[18]), .i13(i13[18]), .i12(i12[18]), .i11(i11[18]), .i10(i10[18]), .i9(i9[18]), .i8(i8[18]), .i7(i7[18]), .i6(i6[18]), .i5(i5[18]), .i4(i4[18]), .i3(i3[18]), .i2(i2[18]), .i1(i1[18]), .i0(i0[18]), .s(s));
+
+mux_32to1 mux19(.z(z[19]), .i31(i31[19]), .i30(i30[19]), .i29(i29[19]), .i28(i28[19]), .i27(i27[19]), .i26(i26[19]), .i25(i25[19]), .i24(i24[19]), .i23(i23[19]), .i22(i22[19]), .i21(i21[19]), .i20(i20[19]), .i19(i19[19]), .i18(i18[19]), .i17(i17[19]), .i16(i16[19]), .i15(i15[19]), .i14(i14[19]), .i13(i13[19]), .i12(i12[19]), .i11(i11[19]), .i10(i10[19]), .i9(i9[19]), .i8(i8[19]), .i7(i7[19]), .i6(i6[19]), .i5(i5[19]), .i4(i4[19]), .i3(i3[19]), .i2(i2[19]), .i1(i1[19]), .i0(i0[19]), .s(s));
+
+mux_32to1 mux20(.z(z[20]), .i31(i31[20]), .i30(i30[20]), .i29(i29[20]), .i28(i28[20]), .i27(i27[20]), .i26(i26[20]), .i25(i25[20]), .i24(i24[20]), .i23(i23[20]), .i22(i22[20]), .i21(i21[20]), .i20(i20[20]), .i19(i19[20]), .i18(i18[20]), .i17(i17[20]), .i16(i16[20]), .i15(i15[20]), .i14(i14[20]), .i13(i13[20]), .i12(i12[20]), .i11(i11[20]), .i10(i10[20]), .i9(i9[20]), .i8(i8[20]), .i7(i7[20]), .i6(i6[20]), .i5(i5[20]), .i4(i4[20]), .i3(i3[20]), .i2(i2[20]), .i1(i1[20]), .i0(i0[20]), .s(s));
+
+mux_32to1 mux21(.z(z[21]), .i31(i31[21]), .i30(i30[21]), .i29(i29[21]), .i28(i28[21]), .i27(i27[21]), .i26(i26[21]), .i25(i25[21]), .i24(i24[21]), .i23(i23[21]), .i22(i22[21]), .i21(i21[21]), .i20(i20[21]), .i19(i19[21]), .i18(i18[21]), .i17(i17[21]), .i16(i16[21]), .i15(i15[21]), .i14(i14[21]), .i13(i13[21]), .i12(i12[21]), .i11(i11[21]), .i10(i10[21]), .i9(i9[21]), .i8(i8[21]), .i7(i7[21]), .i6(i6[21]), .i5(i5[21]), .i4(i4[21]), .i3(i3[21]), .i2(i2[21]), .i1(i1[21]), .i0(i0[21]), .s(s));
+
+mux_32to1 mux22(.z(z[22]), .i31(i31[22]), .i30(i30[22]), .i29(i29[22]), .i28(i28[22]), .i27(i27[22]), .i26(i26[22]), .i25(i25[22]), .i24(i24[22]), .i23(i23[22]), .i22(i22[22]), .i21(i21[22]), .i20(i20[22]), .i19(i19[22]), .i18(i18[22]), .i17(i17[22]), .i16(i16[22]), .i15(i15[22]), .i14(i14[22]), .i13(i13[22]), .i12(i12[22]), .i11(i11[22]), .i10(i10[22]), .i9(i9[22]), .i8(i8[22]), .i7(i7[22]), .i6(i6[22]), .i5(i5[22]), .i4(i4[22]), .i3(i3[22]), .i2(i2[22]), .i1(i1[22]), .i0(i0[22]), .s(s));
+
+
+mux_32to1 mux23(.z(z[23]), .i31(i31[23]), .i30(i30[23]), .i29(i29[23]), .i28(i28[23]), .i27(i27[23]), .i26(i26[23]), .i25(i25[23]), .i24(i24[23]), .i23(i23[23]), .i22(i22[23]), .i21(i21[23]), .i20(i20[23]), .i19(i19[23]), .i18(i18[23]), .i17(i17[23]), .i16(i16[23]), .i15(i15[23]), .i14(i14[23]), .i13(i13[23]), .i12(i12[23]), .i11(i11[23]), .i10(i10[23]), .i9(i9[23]), .i8(i8[23]), .i7(i7[23]), .i6(i6[23]), .i5(i5[23]), .i4(i4[23]), .i3(i3[23]), .i2(i2[23]), .i1(i1[23]), .i0(i0[23]), .s(s));
+
+mux_32to1 mux24(.z(z[24]), .i31(i31[24]), .i30(i30[24]), .i29(i29[24]), .i28(i28[24]), .i27(i27[24]), .i26(i26[24]), .i25(i25[24]), .i24(i24[24]), .i23(i23[24]), .i22(i22[24]), .i21(i21[24]), .i20(i20[24]), .i19(i19[24]), .i18(i18[24]), .i17(i17[24]), .i16(i16[24]), .i15(i15[24]), .i14(i14[24]), .i13(i13[24]), .i12(i12[24]), .i11(i11[24]), .i10(i10[24]), .i9(i9[24]), .i8(i8[24]), .i7(i7[24]), .i6(i6[24]), .i5(i5[24]), .i4(i4[24]), .i3(i3[24]), .i2(i2[24]), .i1(i1[24]), .i0(i0[24]), .s(s));
+
+mux_32to1 mux25(.z(z[25]), .i31(i31[25]), .i30(i30[25]), .i29(i29[25]), .i28(i28[25]), .i27(i27[25]), .i26(i26[25]), .i25(i25[25]), .i24(i24[25]), .i23(i23[25]), .i22(i22[25]), .i21(i21[25]), .i20(i20[25]), .i19(i19[25]), .i18(i18[25]), .i17(i17[25]), .i16(i16[25]), .i15(i15[25]), .i14(i14[25]), .i13(i13[25]), .i12(i12[25]), .i11(i11[25]), .i10(i10[25]), .i9(i9[25]), .i8(i8[25]), .i7(i7[25]), .i6(i6[25]), .i5(i5[25]), .i4(i4[25]), .i3(i3[25]), .i2(i2[25]), .i1(i1[25]), .i0(i0[25]), .s(s));
+
+mux_32to1 mux26(.z(z[26]), .i31(i31[26]), .i30(i30[26]), .i29(i29[26]), .i28(i28[26]), .i27(i27[26]), .i26(i26[26]), .i25(i25[26]), .i24(i24[26]), .i23(i23[26]), .i22(i22[26]), .i21(i21[26]), .i20(i20[26]), .i19(i19[26]), .i18(i18[26]), .i17(i17[26]), .i16(i16[26]), .i15(i15[26]), .i14(i14[26]), .i13(i13[26]), .i12(i12[26]), .i11(i11[26]), .i10(i10[26]), .i9(i9[26]), .i8(i8[26]), .i7(i7[26]), .i6(i6[26]), .i5(i5[26]), .i4(i4[26]), .i3(i3[26]), .i2(i2[26]), .i1(i1[26]), .i0(i0[26]), .s(s));
+
+mux_32to1 mux27(.z(z[27]), .i31(i31[27]), .i30(i30[27]), .i29(i29[27]), .i28(i28[27]), .i27(i27[27]), .i26(i26[27]), .i25(i25[27]), .i24(i24[27]), .i23(i23[27]), .i22(i22[27]), .i21(i21[27]), .i20(i20[27]), .i19(i19[27]), .i18(i18[27]), .i17(i17[27]), .i16(i16[27]), .i15(i15[27]), .i14(i14[27]), .i13(i13[27]), .i12(i12[27]), .i11(i11[27]), .i10(i10[27]), .i9(i9[27]), .i8(i8[27]), .i7(i7[27]), .i6(i6[27]), .i5(i5[27]), .i4(i4[27]), .i3(i3[27]), .i2(i2[27]), .i1(i1[27]), .i0(i0[27]), .s(s));
+
+mux_32to1 mux28(.z(z[28]), .i31(i31[28]), .i30(i30[28]), .i29(i29[28]), .i28(i28[28]), .i27(i27[28]), .i26(i26[28]), .i25(i25[28]), .i24(i24[28]), .i23(i23[28]), .i22(i22[28]), .i21(i21[28]), .i20(i20[28]), .i19(i19[28]), .i18(i18[28]), .i17(i17[28]), .i16(i16[28]), .i15(i15[28]), .i14(i14[28]), .i13(i13[28]), .i12(i12[28]), .i11(i11[28]), .i10(i10[28]), .i9(i9[28]), .i8(i8[28]), .i7(i7[28]), .i6(i6[28]), .i5(i5[28]), .i4(i4[28]), .i3(i3[28]), .i2(i2[28]), .i1(i1[28]), .i0(i0[28]), .s(s));
+
+mux_32to1 mux29(.z(z[29]), .i31(i31[29]), .i30(i30[29]), .i29(i29[29]), .i28(i28[29]), .i27(i27[29]), .i26(i26[29]), .i25(i25[29]), .i24(i24[29]), .i23(i23[29]), .i22(i22[29]), .i21(i21[29]), .i20(i20[29]), .i19(i19[29]), .i18(i18[29]), .i17(i17[29]), .i16(i16[29]), .i15(i15[29]), .i14(i14[29]), .i13(i13[29]), .i12(i12[29]), .i11(i11[29]), .i10(i10[29]), .i9(i9[29]), .i8(i8[29]), .i7(i7[29]), .i6(i6[29]), .i5(i5[29]), .i4(i4[29]), .i3(i3[29]), .i2(i2[29]), .i1(i1[29]), .i0(i0[29]), .s(s));
+
+mux_32to1 mux30(.z(z[30]), .i31(i31[30]), .i30(i30[30]), .i29(i29[30]), .i28(i28[30]), .i27(i27[30]), .i26(i26[30]), .i25(i25[30]), .i24(i24[30]), .i23(i23[30]), .i22(i22[30]), .i21(i21[30]), .i20(i20[30]), .i19(i19[30]), .i18(i18[30]), .i17(i17[30]), .i16(i16[30]), .i15(i15[30]), .i14(i14[30]), .i13(i13[30]), .i12(i12[30]), .i11(i11[30]), .i10(i10[30]), .i9(i9[30]), .i8(i8[30]), .i7(i7[30]), .i6(i6[30]), .i5(i5[30]), .i4(i4[30]), .i3(i3[30]), .i2(i2[30]), .i1(i1[30]), .i0(i0[30]), .s(s));
+
+mux_32to1 mux31(.z(z[31]), .i31(i31[31]), .i30(i30[31]), .i29(i29[31]), .i28(i28[31]), .i27(i27[31]), .i26(i26[31]), .i25(i25[31]), .i24(i24[31]), .i23(i23[31]), .i22(i22[31]), .i21(i21[31]), .i20(i20[31]), .i19(i19[31]), .i18(i18[31]), .i17(i17[31]), .i16(i16[31]), .i15(i15[31]), .i14(i14[31]), .i13(i13[31]), .i12(i12[31]), .i11(i11[31]), .i10(i10[31]), .i9(i9[31]), .i8(i8[31]), .i7(i7[31]), .i6(i6[31]), .i5(i5[31]), .i4(i4[31]), .i3(i3[31]), .i2(i2[31]), .i1(i1[31]), .i0(i0[31]), .s(s));
+
+endmodule
+"
+"module mux5bit_2to1(input [4:0] i0, i1,
+                    input s,
+                    output [4:0] z);
+
+  mux_2to1 mux0(.i0(i0[0]), .i1(i1[0]), .z(z[0]), .s(s));
+  mux_2to1 mux1(.i0(i0[1]), .i1(i1[1]), .z(z[1]), .s(s));
+  mux_2to1 mux2(.i0(i0[2]), .i1(i1[2]), .z(z[2]), .s(s));
+  mux_2to1 mux3(.i0(i0[3]), .i1(i1[3]), .z(z[3]), .s(s));
+  mux_2to1 mux4(.i0(i0[4]), .i1(i1[4]), .z(z[4]), .s(s));
+endmodule
+"
+"`include ""../lib/mux_2to1.v""
+
+module d_flip_flop (
+  input d, clk, we,
+  output q, q_bar);
+
+wire int0, int1, ff_input;
+
+mux_2to1 mux(
+    .z(ff_input),
+    .i0(q),
+    .i1(d),
+    .s(we));
+
+nand (int0, ff_input, ~clk);
+nand (int1, int0    , ~clk);
+
+nand (q    , int0, q_bar);
+nand (q_bar, int1, q    );
+
+endmodule
+"
+"`include ""../lib/flip_flop.v""
+
+module test;
+
+  reg d, clk;
+  wire q, q_bar;
+
+  d_flip_flop dff(
+    .d(d),
+    .clk(clk),
+    .q(q),
+    .q_bar(q_bar));
+
+  always #4 clk = ~clk;
+
+  initial begin
+    clk = 0;
+    #5 d = 0;
+    $display($time , "": d=%b, q=%b, q_bar=%b"", d, q, q_bar);
+    #5 d = 1;
+    $display($time , "": d=%b, q=%b, q_bar=%b"", d, q, q_bar);
+    #5 d = 1;
+    $display($time , "": d=%b, q=%b, q_bar=%b"", d, q, q_bar);
+    #5 d = 0;
+    $display($time , "": d=%b, q=%b, q_bar=%b"", d, q, q_bar);
+    #5 d = 1; 
+    $display($time , "": d=%b, q=%b, q_bar=%b"", d, q, q_bar);
+    $finish;
+  end
+
+endmodule
+"
+"`include ""../ALU/alu.v""
+
+module test;
+
+  reg  signed [31:0] a, b;
+  reg  [3:0] op;
+  wire signed [31:0] z; 
+  wire zero;
+
+  alu a0 (
+    .op(op),
+    .a(a), 
+    .b(b),
+    .z(z),
+    .zero(zero));
+  
+  initial begin
+    $monitor ($time, "": a=%0d\\tb=%0d\\top=%d\\tz=%0d\\tzero=%d"", a, b, op, z, zero);  
+    #5 a = 21; b = 3; op = 0;  
+    #5 a = 2; b = 5; op = 1;  
+    #5 a = 5; b = -4; op = 2;  
+    #5 a = 9; b = 10; op = 6;  
+    #5 a = 5; b = 5; op = 6;  
+    #5 a = 1; b = 3; op = 7;  
+    #5 a = 6; b = 5; op = 7;  
+    #5 a = 1; b = 3; op = 12;  
+
+  end
+
+endmodule
+"
+"module full_subtractor (
+  output Bor_out, d,
+  input a, b, Bor_in
+  );
+
+wire int1, int2, int3, int4, b_bar;
+
+// d = (a xor b) xor Bor_in
+xor (int1, a, b);
+xor (d, int1, Bor_in);
+
+// Bor_out = ((a xor b)' and Bor_in) or (a and b')
+not (int2, int1);
+and (int3, int2, Bor_in); //(a xor b)' and Bor_in
+not (b_bar, b);
+and (int4, b_bar, a); //a and b'
+or  (Bor_out, int4, int3);
+
+endmodule
+"
+"`include ""../ALU/alu_control.v""
+
+module test;
+
+  reg [5:0] funct;
+  reg [1:0] alu_op;
+  wire [3:0] aluctrl;
+  reg [3:0] expect; 
+  alu_control a0 (
+    .funct(funct),
+    .alu_op(alu_op), 
+    .aluctrl(aluctrl));
+  
+  initial begin
+    $monitor ($time, "": funct=%b\\top=%b\\taluctrl=%b\\texpect=%b"", funct, alu_op, aluctrl, expect);  
+    #5 funct  = 6\'b100000; alu_op = 2\'b00; expect = 4\'b0010;
+    #5 alu_op = 2\'b01;     expect = 4\'b0110;
+    #5 alu_op = 2\'b10;     expect = 4\'b0010; //add
+    #5 funct  = 6\'b100010; expect = 4\'b0110; //sub  
+    #5 funct  = 6\'b100100; expect = 4\'b0000; //and
+    #5 funct  = 6\'b100101; expect = 4\'b0001; //or
+    #5 funct  = 6\'b101010; expect = 4\'b0111; //slt
+    #5 funct  = 6\'b100111; expect = 4\'b1100; //nor
+
+  end
+
+endmodule
+"
+"`include ""../control/control.v""
+
+module test;
+
+  reg  [5:0] op;
+  wire [1:0] alu_op;
+  wire regDst, aluSrc, memToReg, regWrite;
+  wire memRead, memWrite, branch;
+  reg [8:0] expect;
+  control c(
+    .op(op),
+    .alu_op(alu_op),
+    .regDst(regDst),
+    .aluSrc(aluSrc),
+    .memToReg(memToReg),
+    .regWrite(regWrite),
+    .memRead(memRead),
+    .memWrite(memWrite),
+    .branch(branch));
+
+  initial begin
+    $monitor($time, "": op=%b\\t %b%b%b%b%b%b%b%b\\t expect=%b"", op, regDst, aluSrc, memToReg, regWrite, memRead, memWrite, branch, alu_op, expect);
+    #5 op = 0;          expect = 9\'b100100010;
+    #5 op = 6\'b 100011; expect = 9\'b011110000;
+    #5 op = 6\'b 101011; expect = 9\'bx1x001000;
+    #5 op = 6\'b 000100; expect = 9\'bx0x000101;
+
+  end
+endmodule
+"
+"`include ""../lib/sign_extend.v""
+
+module test;
+  reg  signed [15:0] a;
+  wire signed [31:0] b;
+
+  sign_extend se(.a(a), .b(b));
+
+  initial begin
+    $monitor($time, ""a=%5d\\t, b=%5d"", a, b);
+    #5 a = 0;
+    #5 a = 10;
+    #5 a = 170;
+    #5 a = -20;
+    #5 a = -220;
+  end
+endmodule
+
+"
+"module mux_16to1 (
+  input [3:0] s,
+  input  i15, i14, i13, i12, i11, i10, i9, i8, i7,i6, i5, i4, i3, i2, i1, i0,
+  output z);
+
+wire int0 , int1 , int2 , int3 , int4 , int5 , int6 , int7; 
+wire int8 , int9 , int10, int11, int12, int13, int14, int15;
+ 
+not (s0_bar, s[0]);
+not (s1_bar, s[1]);
+not (s2_bar, s[2]);
+not (s3_bar, s[3]);
+
+and(int0 , i0 , s3_bar , s2_bar , s1_bar , s0_bar );
+and(int1 , i1 , s3_bar , s2_bar , s1_bar , s[0]   );
+and(int2 , i2 , s3_bar , s2_bar , s[1]   , s0_bar );
+and(int3 , i3 , s3_bar , s2_bar , s[1]   , s[0]   );
+and(int4 , i4 , s3_bar , s[2]   , s1_bar , s0_bar );
+and(int5 , i5 , s3_bar , s[2]   , s1_bar , s[0]   );
+and(int6 , i6 , s3_bar , s[2]   , s[1]   , s0_bar );
+and(int7 , i7 , s3_bar , s[2]   , s[1]   , s[0]   );
+and(int8 , i8 , s[3]   , s2_bar , s1_bar , s0_bar );
+and(int9 , i9 , s[3]   , s2_bar , s1_bar , s[0]   );
+and(int10, i10, s[3]   , s2_bar , s[1]   , s0_bar );
+and(int11, i11, s[3]   , s2_bar , s[1]   , s[0]   );
+and(int12, i12, s[3]   , s[2]   , s1_bar , s0_bar );
+and(int13, i13, s[3]   , s[2]   , s1_bar , s[0]   );
+and(int14, i14, s[3]   , s[2]   , s[1]   , s0_bar );
+and(int15, i15, s[3]   , s[2]   , s[1]   , s[0]   );
+
+or (z, int0, int1, int2, int3, int4, int5, int6, int7, int8, int9, int10, int11, int12, int13, int14, int15); 
+
+//or (int16, int0 , int1 );
+//or (int17, int2 , int3 );
+//or (int18, int4 , int5 );
+//or (int19, int6 , int7 );
+//or (int20, int8 , int9 );
+//or (int21, int10, int11);
+//or (int22, int12, int13);
+//or (int23, int14, int15);
+//or (int24, int16, int17);
+//or (int25, int18, int19);
+//or (int26, int20, int21);
+//or (int27, int22, int23);
+//or (int28, int24, int25);
+//or (int29, int26, int27);
+//or (z    , int28, int29);
+
+endmodule
+"
+"`include ""../lib/mux_2to1.v""
+
+module mux32bit_2to1(input [31:0] i0, i1,
+                    input s,
+                    output [31:0] z);
+
+  mux_2to1 mux0 (.i0(i0[0 ]), .i1(i1[0 ]), .z(z[0 ]), .s(s));
+  mux_2to1 mux1 (.i0(i0[1 ]), .i1(i1[1 ]), .z(z[1 ]), .s(s));
+  mux_2to1 mux2 (.i0(i0[2 ]), .i1(i1[2 ]), .z(z[2 ]), .s(s));
+  mux_2to1 mux3 (.i0(i0[3 ]), .i1(i1[3 ]), .z(z[3 ]), .s(s));
+  mux_2to1 mux4 (.i0(i0[4 ]), .i1(i1[4 ]), .z(z[4 ]), .s(s));
+  mux_2to1 mux5 (.i0(i0[5 ]), .i1(i1[5 ]), .z(z[5 ]), .s(s));
+  mux_2to1 mux6 (.i0(i0[6 ]), .i1(i1[6 ]), .z(z[6 ]), .s(s));
+  mux_2to1 mux7 (.i0(i0[7 ]), .i1(i1[7 ]), .z(z[7 ]), .s(s));
+  mux_2to1 mux8 (.i0(i0[8 ]), .i1(i1[8 ]), .z(z[8 ]), .s(s));
+  mux_2to1 mux9 (.i0(i0[9 ]), .i1(i1[9 ]), .z(z[9 ]), .s(s));
+  mux_2to1 mux10(.i0(i0[10]), .i1(i1[10]), .z(z[10]), .s(s));
+  mux_2to1 mux11(.i0(i0[11]), .i1(i1[11]), .z(z[11]), .s(s));
+  mux_2to1 mux12(.i0(i0[12]), .i1(i1[12]), .z(z[12]), .s(s));
+  mux_2to1 mux13(.i0(i0[13]), .i1(i1[13]), .z(z[13]), .s(s));
+  mux_2to1 mux14(.i0(i0[14]), .i1(i1[14]), .z(z[14]), .s(s));
+  mux_2to1 mux15(.i0(i0[15]), .i1(i1[15]), .z(z[15]), .s(s));
+  mux_2to1 mux16(.i0(i0[16]), .i1(i1[16]), .z(z[16]), .s(s));
+  mux_2to1 mux17(.i0(i0[17]), .i1(i1[17]), .z(z[17]), .s(s));
+  mux_2to1 mux18(.i0(i0[18]), .i1(i1[18]), .z(z[18]), .s(s));
+  mux_2to1 mux19(.i0(i0[19]), .i1(i1[19]), .z(z[19]), .s(s));
+  mux_2to1 mux20(.i0(i0[20]), .i1(i1[20]), .z(z[20]), .s(s));
+  mux_2to1 mux21(.i0(i0[21]), .i1(i1[21]), .z(z[21]), .s(s));
+  mux_2to1 mux22(.i0(i0[22]), .i1(i1[22]), .z(z[22]), .s(s));
+  mux_2to1 mux23(.i0(i0[23]), .i1(i1[23]), .z(z[23]), .s(s));
+  mux_2to1 mux24(.i0(i0[24]), .i1(i1[24]), .z(z[24]), .s(s));
+  mux_2to1 mux25(.i0(i0[25]), .i1(i1[25]), .z(z[25]), .s(s));
+  mux_2to1 mux26(.i0(i0[26]), .i1(i1[26]), .z(z[26]), .s(s));
+  mux_2to1 mux27(.i0(i0[27]), .i1(i1[27]), .z(z[27]), .s(s));
+  mux_2to1 mux28(.i0(i0[28]), .i1(i1[28]), .z(z[28]), .s(s));
+  mux_2to1 mux29(.i0(i0[29]), .i1(i1[29]), .z(z[29]), .s(s));
+  mux_2to1 mux30(.i0(i0[30]), .i1(i1[30]), .z(z[30]), .s(s));
+  mux_2to1 mux31(.i0(i0[31]), .i1(i1[31]), .z(z[31]), .s(s));
+endmodule
+"
+"module mux_32to1 (
+  input  [4:0] s,
+  input  i31, i30, i29, i28, i27, i26, i25, i24, i23,i22, i21, i20, i19, i18, i17, i16,
+  input  i15, i14, i13, i12, i11, i10, i9, i8, i7,i6, i5, i4, i3, i2, i1, i0,
+  output z);
+
+wire int0 , int1 , int2 , int3 , int4 , int5 , int6 , int7; 
+wire int8 , int9 , int10, int11, int12, int13, int14, int15;
+ 
+not (s0_bar, s[0]);
+not (s1_bar, s[1]);
+not (s2_bar, s[2]);
+not (s3_bar, s[3]);
+not (s4_bar, s[4]);
+
+
+and(int0 , i0 , s4_bar, s3_bar , s2_bar , s1_bar , s0_bar );
+and(int1 , i1 , s4_bar, s3_bar , s2_bar , s1_bar , s[0]   );
+and(int2 , i2 , s4_bar, s3_bar , s2_bar , s[1]   , s0_bar );
+and(int3 , i3 , s4_bar, s3_bar , s2_bar , s[1]   , s[0]   );
+and(int4 , i4 , s4_bar, s3_bar , s[2]   , s1_bar , s0_bar );
+and(int5 , i5 , s4_bar, s3_bar , s[2]   , s1_bar , s[0]   );
+and(int6 , i6 , s4_bar, s3_bar , s[2]   , s[1]   , s0_bar );
+and(int7 , i7 , s4_bar, s3_bar , s[2]   , s[1]   , s[0]   );
+and(int8 , i8 , s4_bar, s[3]   , s2_bar , s1_bar , s0_bar );
+and(int9 , i9 , s4_bar, s[3]   , s2_bar , s1_bar , s[0]   );
+and(int10, i10, s4_bar, s[3]   , s2_bar , s[1]   , s0_bar );
+and(int11, i11, s4_bar, s[3]   , s2_bar , s[1]   , s[0]   );
+and(int12, i12, s4_bar, s[3]   , s[2]   , s1_bar , s0_bar );
+and(int13, i13, s4_bar, s[3]   , s[2]   , s1_bar , s[0]   );
+and(int14, i14, s4_bar, s[3]   , s[2]   , s[1]   , s0_bar );
+and(int15, i15, s4_bar, s[3]   , s[2]   , s[1]   , s[0]   );
+and(int16, i16, s[4]  ,s3_bar , s2_bar , s1_bar , s0_bar );
+and(int17, i17, s[4]  ,s3_bar , s2_bar , s1_bar , s[0]   );
+and(int18, i18, s[4]  ,s3_bar , s2_bar , s[1]   , s0_bar );
+and(int19, i19, s[4]  ,s3_bar , s2_bar , s[1]   , s[0]   );
+and(int20, i20, s[4]  ,s3_bar , s[2]   , s1_bar , s0_bar );
+and(int21, i21, s[4]  ,s3_bar , s[2]   , s1_bar , s[0]   );
+and(int22, i22, s[4]  ,s3_bar , s[2]   , s[1]   , s0_bar );
+and(int23, i23, s[4]  ,s3_bar , s[2]   , s[1]   , s[0]   );
+and(int24, i24, s[4]  ,s[3]   , s2_bar , s1_bar , s0_bar );
+and(int25, i25, s[4]  ,s[3]   , s2_bar , s1_bar , s[0]   );
+and(int26, i26, s[4]  ,s[3]   , s2_bar , s[1]   , s0_bar );
+and(int27, i27, s[4]  ,s[3]   , s2_bar , s[1]   , s[0]   );
+and(int28, i28, s[4]  ,s[3]   , s[2]   , s1_bar , s0_bar );
+and(int29, i29, s[4]  ,s[3]   , s[2]   , s1_bar , s[0]   );
+and(int30, i30, s[4]  ,s[3]   , s[2]   , s[1]   , s0_bar );
+and(int31, i31, s[4]  ,s[3]   , s[2]   , s[1]   , s[0]   );
+
+
+or (z, int31, int30, int29, int28, int27, int26, int25,
+    int24, int23,int22, int21, int20, int19, int18, int17,
+    int16, int0, int1, int2, int3, int4, int5, int6, int7, 
+    int8, int9, int10, int11, int12, int13, int14, int15);
+
+endmodule
+"
+"module mux_2to1 (
+  input i1, i0, s,
+  output z);
+
+wire int0, int1, s_bar;
+
+not (s_bar, s);
+
+and(int0, i0, s_bar);
+and(int1, i1, s    );
+
+or (z, int0, int1);
+
+endmodule
+"
+"`include ""../lib/mux_32to1.v""
+
+module mux32bits_32to1 (
+  input  [4:0 ] s,
+  input  [31:0] i31, i30, i29, i28, i27, i26, i25, i24, i23,i22, i21, i20, i19, i18, i17, i16,
+  input  [31:0] i15, i14, i13, i12, i11, i10, i9, i8, i7,i6, i5, i4, i3, i2, i1, i0,
+  output [31:0] z);
+
+mux_32to1 mux0 (.z(z[0 ]), .i31(i31[0 ]), .i30(i30[0 ]), .i29(i29[0 ]), .i28(i28[0 ]), .i27(i27[0 ]), .i26(i26[0 ]), .i25(i25[0 ]), .i24(i24[0 ]), .i23(i23[0 ]), .i22(i22[0 ]), .i21(i21[0 ]), .i20(i20[0 ]), .i19(i19[0 ]), .i18(i18[0 ]), .i17(i17[0 ]), .i16(i16[0 ]), .i15(i15[0 ]), .i14(i14[0 ]), .i13(i13[0 ]), .i12(i12[0 ]), .i11(i11[0 ]), .i10(i10[0 ]), .i9(i9[0 ]), .i8(i8[0 ]), .i7(i7[0 ]), .i6(i6[0 ]), .i5(i5[0 ]), .i4(i4[0 ]), .i3(i3[0 ]), .i2(i2[0 ]), .i1(i1[0 ]), .i0(i0[0 ]), .s(s));
+
+mux_32to1 mux1 (.z(z[1 ]), .i31(i31[1 ]), .i30(i30[1 ]), .i29(i29[1 ]), .i28(i28[1 ]), .i27(i27[1 ]), .i26(i26[1 ]), .i25(i25[1 ]), .i24(i24[1 ]), .i23(i23[1 ]), .i22(i22[1 ]), .i21(i21[1 ]), .i20(i20[1 ]), .i19(i19[1 ]), .i18(i18[1 ]), .i17(i17[1 ]), .i16(i16[1 ]), .i15(i15[1 ]), .i14(i14[1 ]), .i13(i13[1 ]), .i12(i12[1 ]), .i11(i11[1 ]), .i10(i10[1 ]), .i9(i9[1 ]), .i8(i8[1 ]), .i7(i7[1 ]), .i6(i6[1 ]), .i5(i5[1 ]), .i4(i4[1 ]), .i3(i3[1 ]), .i2(i2[1 ]), .i1(i1[1 ]), .i0(i0[1 ]), .s(s));
+
+mux_32to1 mux2 (.z(z[2 ]), .i31(i31[2 ]), .i30(i30[2 ]), .i29(i29[2 ]), .i28(i28[2 ]), .i27(i27[2 ]), .i26(i26[2 ]), .i25(i25[2 ]), .i24(i24[2 ]), .i23(i23[2 ]), .i22(i22[2 ]), .i21(i21[2 ]), .i20(i20[2 ]), .i19(i19[2 ]), .i18(i18[2 ]), .i17(i17[2 ]), .i16(i16[2 ]), .i15(i15[2 ]), .i14(i14[2 ]), .i13(i13[2 ]), .i12(i12[2 ]), .i11(i11[2 ]), .i10(i10[2 ]), .i9(i9[2 ]), .i8(i8[2 ]), .i7(i7[2 ]), .i6(i6[2 ]), .i5(i5[2 ]), .i4(i4[2 ]), .i3(i3[2 ]), .i2(i2[2 ]), .i1(i1[2 ]), .i0(i0[2 ]), .s(s));
+
+mux_32to1 mux3 (.z(z[3 ]), .i31(i31[3 ]), .i30(i30[3 ]), .i29(i29[3 ]), .i28(i28[3 ]), .i27(i27[3 ]), .i26(i26[3 ]), .i25(i25[3 ]), .i24(i24[3 ]), .i23(i23[3 ]), .i22(i22[3 ]), .i21(i21[3 ]), .i20(i20[3 ]), .i19(i19[3 ]), .i18(i18[3 ]), .i17(i17[3 ]), .i16(i16[3 ]), .i15(i15[3 ]), .i14(i14[3 ]), .i13(i13[3 ]), .i12(i12[3 ]), .i11(i11[3 ]), .i10(i10[3 ]), .i9(i9[3 ]), .i8(i8[3 ]), .i7(i7[3 ]), .i6(i6[3 ]), .i5(i5[3 ]), .i4(i4[3 ]), .i3(i3[3 ]), .i2(i2[3 ]), .i1(i1[3 ]), .i0(i0[3 ]), .s(s));
+
+mux_32to1 mux4 (.z(z[4 ]), .i31(i31[4 ]), .i30(i30[4 ]), .i29(i29[4 ]), .i28(i28[4 ]), .i27(i27[4 ]), .i26(i26[4 ]), .i25(i25[4 ]), .i24(i24[4 ]), .i23(i23[4 ]), .i22(i22[4 ]), .i21(i21[4 ]), .i20(i20[4 ]), .i19(i19[4 ]), .i18(i18[4 ]), .i17(i17[4 ]), .i16(i16[4 ]), .i15(i15[4 ]), .i14(i14[4 ]), .i13(i13[4 ]), .i12(i12[4 ]), .i11(i11[4 ]), .i10(i10[4 ]), .i9(i9[4 ]), .i8(i8[4 ]), .i7(i7[4 ]), .i6(i6[4 ]), .i5(i5[4 ]), .i4(i4[4 ]), .i3(i3[4 ]), .i2(i2[4 ]), .i1(i1[4 ]), .i0(i0[4 ]), .s(s));
+
+mux_32to1 mux5 (.z(z[5 ]), .i31(i31[5 ]), .i30(i30[5 ]), .i29(i29[5 ]), .i28(i28[5 ]), .i27(i27[5 ]), .i26(i26[5 ]), .i25(i25[5 ]), .i24(i24[5 ]), .i23(i23[5 ]), .i22(i22[5 ]), .i21(i21[5 ]), .i20(i20[5 ]), .i19(i19[5 ]), .i18(i18[5 ]), .i17(i17[5 ]), .i16(i16[5 ]), .i15(i15[5 ]), .i14(i14[5 ]), .i13(i13[5 ]), .i12(i12[5 ]), .i11(i11[5 ]), .i10(i10[5 ]), .i9(i9[5 ]), .i8(i8[5 ]), .i7(i7[5 ]), .i6(i6[5 ]), .i5(i5[5 ]), .i4(i4[5 ]), .i3(i3[5 ]), .i2(i2[5 ]), .i1(i1[5 ]), .i0(i0[5 ]), .s(s));
+
+mux_32to1 mux6 (.z(z[6 ]), .i31(i31[6 ]), .i30(i30[6 ]), .i29(i29[6 ]), .i28(i28[6 ]), .i27(i27[6 ]), .i26(i26[6 ]), .i25(i25[6 ]), .i24(i24[6 ]), .i23(i23[6 ]), .i22(i22[6 ]), .i21(i21[6 ]), .i20(i20[6 ]), .i19(i19[6 ]), .i18(i18[6 ]), .i17(i17[6 ]), .i16(i16[6 ]), .i15(i15[6 ]), .i14(i14[6 ]), .i13(i13[6 ]), .i12(i12[6 ]), .i11(i11[6 ]), .i10(i10[6 ]), .i9(i9[6 ]), .i8(i8[6 ]), .i7(i7[6 ]), .i6(i6[6 ]), .i5(i5[6 ]), .i4(i4[6 ]), .i3(i3[6 ]), .i2(i2[6 ]), .i1(i1[6 ]), .i0(i0[6 ]), .s(s));
+
+mux_32to1 mux7 (.z(z[7 ]), .i31(i31[7 ]), .i30(i30[7 ]), .i29(i29[7 ]), .i28(i28[7 ]), .i27(i27[7 ]), .i26(i26[7 ]), .i25(i25[7 ]), .i24(i24[7 ]), .i23(i23[7 ]), .i22(i22[7 ]), .i21(i21[7 ]), .i20(i20[7 ]), .i19(i19[7 ]), .i18(i18[7 ]), .i17(i17[7 ]), .i16(i16[7 ]), .i15(i15[7 ]), .i14(i14[7 ]), .i13(i13[7 ]), .i12(i12[7 ]), .i11(i11[7 ]), .i10(i10[7 ]), .i9(i9[7 ]), .i8(i8[7 ]), .i7(i7[7 ]), .i6(i6[7 ]), .i5(i5[7 ]), .i4(i4[7 ]), .i3(i3[7 ]), .i2(i2[7 ]), .i1(i1[7 ]), .i0(i0[7 ]), .s(s));
+
+mux_32to1 mux8 (.z(z[8 ]), .i31(i31[8 ]), .i30(i30[8 ]), .i29(i29[8 ]), .i28(i28[8 ]), .i27(i27[8 ]), .i26(i26[8 ]), .i25(i25[8 ]), .i24(i24[8 ]), .i23(i23[8 ]), .i22(i22[8 ]), .i21(i21[8 ]), .i20(i20[8 ]), .i19(i19[8 ]), .i18(i18[8 ]), .i17(i17[8 ]), .i16(i16[8 ]), .i15(i15[8 ]), .i14(i14[8 ]), .i13(i13[8 ]), .i12(i12[8 ]), .i11(i11[8 ]), .i10(i10[8 ]), .i9(i9[8 ]), .i8(i8[8 ]), .i7(i7[8 ]), .i6(i6[8 ]), .i5(i5[8 ]), .i4(i4[8 ]), .i3(i3[8 ]), .i2(i2[8 ]), .i1(i1[8 ]), .i0(i0[8 ]), .s(s));
+
+mux_32to1 mux9 (.z(z[9 ]), .i31(i31[9 ]), .i30(i30[9 ]), .i29(i29[9 ]), .i28(i28[9 ]), .i27(i27[9 ]), .i26(i26[9 ]), .i25(i25[9 ]), .i24(i24[9 ]), .i23(i23[9 ]), .i22(i22[9 ]), .i21(i21[9 ]), .i20(i20[9 ]), .i19(i19[9 ]), .i18(i18[9 ]), .i17(i17[9 ]), .i16(i16[9 ]), .i15(i15[9 ]), .i14(i14[9 ]), .i13(i13[9 ]), .i12(i12[9 ]), .i11(i11[9 ]), .i10(i10[9 ]), .i9(i9[9 ]), .i8(i8[9 ]), .i7(i7[9 ]), .i6(i6[9 ]), .i5(i5[9 ]), .i4(i4[9 ]), .i3(i3[9 ]), .i2(i2[9 ]), .i1(i1[9 ]), .i0(i0[9 ]), .s(s));
+
+mux_32to1 mux10(.z(z[10]), .i31(i31[10]), .i30(i30[10]), .i29(i29[10]), .i28(i28[10]), .i27(i27[10]), .i26(i26[10]), .i25(i25[10]), .i24(i24[10]), .i23(i23[10]), .i22(i22[10]), .i21(i21[10]), .i20(i20[10]), .i19(i19[10]), .i18(i18[10]), .i17(i17[10]), .i16(i16[10]), .i15(i15[10]), .i14(i14[10]), .i13(i13[10]), .i12(i12[10]), .i11(i11[10]), .i10(i10[10]), .i9(i9[10]), .i8(i8[10]), .i7(i7[10]), .i6(i6[10]), .i5(i5[10]), .i4(i4[10]), .i3(i3[10]), .i2(i2[10]), .i1(i1[10]), .i0(i0[10]), .s(s));
+
+mux_32to1 mux11(.z(z[11]), .i31(i31[11]), .i30(i30[11]), .i29(i29[11]), .i28(i28[11]), .i27(i27[11]), .i26(i26[11]), .i25(i25[11]), .i24(i24[11]), .i23(i23[11]), .i22(i22[11]), .i21(i21[11]), .i20(i20[11]), .i19(i19[11]), .i18(i18[11]), .i17(i17[11]), .i16(i16[11]), .i15(i15[11]), .i14(i14[11]), .i13(i13[11]), .i12(i12[11]), .i11(i11[11]), .i10(i10[11]), .i9(i9[11]), .i8(i8[11]), .i7(i7[11]), .i6(i6[11]), .i5(i5[11]), .i4(i4[11]), .i3(i3[11]), .i2(i2[11]), .i1(i1[11]), .i0(i0[11]), .s(s));
+
+mux_32to1 mux12(.z(z[12]), .i31(i31[12]), .i30(i30[12]), .i29(i29[12]), .i28(i28[12]), .i27(i27[12]), .i26(i26[12]), .i25(i25[12]), .i24(i24[12]), .i23(i23[12]), .i22(i22[12]), .i21(i21[12]), .i20(i20[12]), .i19(i19[12]), .i18(i18[12]), .i17(i17[12]), .i16(i16[12]), .i15(i15[12]), .i14(i14[12]), .i13(i13[12]), .i12(i12[12]), .i11(i11[12]), .i10(i10[12]), .i9(i9[12]), .i8(i8[12]), .i7(i7[12]), .i6(i6[12]), .i5(i5[12]), .i4(i4[12]), .i3(i3[12]), .i2(i2[12]), .i1(i1[12]), .i0(i0[12]), .s(s));
+
+mux_32to1 mux13(.z(z[13]), .i31(i31[13]), .i30(i30[13]), .i29(i29[13]), .i28(i28[13]), .i27(i27[13]), .i26(i26[13]), .i25(i25[13]), .i24(i24[13]), .i23(i23[13]), .i22(i22[13]), .i21(i21[13]), .i20(i20[13]), .i19(i19[13]), .i18(i18[13]), .i17(i17[13]), .i16(i16[13]), .i15(i15[13]), .i14(i14[13]), .i13(i13[13]), .i12(i12[13]), .i11(i11[13]), .i10(i10[13]), .i9(i9[13]), .i8(i8[13]), .i7(i7[13]), .i6(i6[13]), .i5(i5[13]), .i4(i4[13]), .i3(i3[13]), .i2(i2[13]), .i1(i1[13]), .i0(i0[13]), .s(s));
+
+mux_32to1 mux14(.z(z[14]), .i31(i31[14]), .i30(i30[14]), .i29(i29[14]), .i28(i28[14]), .i27(i27[14]), .i26(i26[14]), .i25(i25[14]), .i24(i24[14]), .i23(i23[14]), .i22(i22[14]), .i21(i21[14]), .i20(i20[14]), .i19(i19[14]), .i18(i18[14]), .i17(i17[14]), .i16(i16[14]), .i15(i15[14]), .i14(i14[14]), .i13(i13[14]), .i12(i12[14]), .i11(i11[14]), .i10(i10[14]), .i9(i9[14]), .i8(i8[14]), .i7(i7[14]), .i6(i6[14]), .i5(i5[14]), .i4(i4[14]), .i3(i3[14]), .i2(i2[14]), .i1(i1[14]), .i0(i0[14]), .s(s));
+
+mux_32to1 mux15(.z(z[15]), .i31(i31[15]), .i30(i30[15]), .i29(i29[15]), .i28(i28[15]), .i27(i27[15]), .i26(i26[15]), .i25(i25[15]), .i24(i24[15]), .i23(i23[15]), .i22(i22[15]), .i21(i21[15]), .i20(i20[15]), .i19(i19[15]), .i18(i18[15]), .i17(i17[15]), .i16(i16[15]), .i15(i15[15]), .i14(i14[15]), .i13(i13[15]), .i12(i12[15]), .i11(i11[15]), .i10(i10[15]), .i9(i9[15]), .i8(i8[15]), .i7(i7[15]), .i6(i6[15]), .i5(i5[15]), .i4(i4[15]), .i3(i3[15]), .i2(i2[15]), .i1(i1[15]), .i0(i0[15]), .s(s));
+
+mux_32to1 mux16(.z(z[16]), .i31(i31[16]), .i30(i30[16]), .i29(i29[16]), .i28(i28[16]), .i27(i27[16]), .i26(i26[16]), .i25(i25[16]), .i24(i24[16]), .i23(i23[16]), .i22(i22[16]), .i21(i21[16]), .i20(i20[16]), .i19(i19[16]), .i18(i18[16]), .i17(i17[16]), .i16(i16[16]), .i15(i15[16]), .i14(i14[16]), .i13(i13[16]), .i12(i12[16]), .i11(i11[16]), .i10(i10[16]), .i9(i9[16]), .i8(i8[16]), .i7(i7[16]), .i6(i6[16]), .i5(i5[16]), .i4(i4[16]), .i3(i3[16]), .i2(i2[16]), .i1(i1[16]), .i0(i0[16]), .s(s));
+
+mux_32to1 mux17(.z(z[17]), .i31(i31[17]), .i30(i30[17]), .i29(i29[17]), .i28(i28[17]), .i27(i27[17]), .i26(i26[17]), .i25(i25[17]), .i24(i24[17]), .i23(i23[17]), .i22(i22[17]), .i21(i21[17]), .i20(i20[17]), .i19(i19[17]), .i18(i18[17]), .i17(i17[17]), .i16(i16[17]), .i15(i15[17]), .i14(i14[17]), .i13(i13[17]), .i12(i12[17]), .i11(i11[17]), .i10(i10[17]), .i9(i9[17]), .i8(i8[17]), .i7(i7[17]), .i6(i6[17]), .i5(i5[17]), .i4(i4[17]), .i3(i3[17]), .i2(i2[17]), .i1(i1[17]), .i0(i0[17]), .s(s));
+
+mux_32to1 mux18(.z(z[18]), .i31(i31[18]), .i30(i30[18]), .i29(i29[18]), .i28(i28[18]), .i27(i27[18]), .i26(i26[18]), .i25(i25[18]), .i24(i24[18]), .i23(i23[18]), .i22(i22[18]), .i21(i21[18]), .i20(i20[18]), .i19(i19[18]), .i18(i18[18]), .i17(i17[18]), .i16(i16[18]), .i15(i15[18]), .i14(i14[18]), .i13(i13[18]), .i12(i12[18]), .i11(i11[18]), .i10(i10[18]), .i9(i9[18]), .i8(i8[18]), .i7(i7[18]), .i6(i6[18]), .i5(i5[18]), .i4(i4[18]), .i3(i3[18]), .i2(i2[18]), .i1(i1[18]), .i0(i0[18]), .s(s));
+
+mux_32to1 mux19(.z(z[19]), .i31(i31[19]), .i30(i30[19]), .i29(i29[19]), .i28(i28[19]), .i27(i27[19]), .i26(i26[19]), .i25(i25[19]), .i24(i24[19]), .i23(i23[19]), .i22(i22[19]), .i21(i21[19]), .i20(i20[19]), .i19(i19[19]), .i18(i18[19]), .i17(i17[19]), .i16(i16[19]), .i15(i15[19]), .i14(i14[19]), .i13(i13[19]), .i12(i12[19]), .i11(i11[19]), .i10(i10[19]), .i9(i9[19]), .i8(i8[19]), .i7(i7[19]), .i6(i6[19]), .i5(i5[19]), .i4(i4[19]), .i3(i3[19]), .i2(i2[19]), .i1(i1[19]), .i0(i0[19]), .s(s));
+
+mux_32to1 mux20(.z(z[20]), .i31(i31[20]), .i30(i30[20]), .i29(i29[20]), .i28(i28[20]), .i27(i27[20]), .i26(i26[20]), .i25(i25[20]), .i24(i24[20]), .i23(i23[20]), .i22(i22[20]), .i21(i21[20]), .i20(i20[20]), .i19(i19[20]), .i18(i18[20]), .i17(i17[20]), .i16(i16[20]), .i15(i15[20]), .i14(i14[20]), .i13(i13[20]), .i12(i12[20]), .i11(i11[20]), .i10(i10[20]), .i9(i9[20]), .i8(i8[20]), .i7(i7[20]), .i6(i6[20]), .i5(i5[20]), .i4(i4[20]), .i3(i3[20]), .i2(i2[20]), .i1(i1[20]), .i0(i0[20]), .s(s));
+
+mux_32to1 mux21(.z(z[21]), .i31(i31[21]), .i30(i30[21]), .i29(i29[21]), .i28(i28[21]), .i27(i27[21]), .i26(i26[21]), .i25(i25[21]), .i24(i24[21]), .i23(i23[21]), .i22(i22[21]), .i21(i21[21]), .i20(i20[21]), .i19(i19[21]), .i18(i18[21]), .i17(i17[21]), .i16(i16[21]), .i15(i15[21]), .i14(i14[21]), .i13(i13[21]), .i12(i12[21]), .i11(i11[21]), .i10(i10[21]), .i9(i9[21]), .i8(i8[21]), .i7(i7[21]), .i6(i6[21]), .i5(i5[21]), .i4(i4[21]), .i3(i3[21]), .i2(i2[21]), .i1(i1[21]), .i0(i0[21]), .s(s));
+
+mux_32to1 mux22(.z(z[22]), .i31(i31[22]), .i30(i30[22]), .i29(i29[22]), .i28(i28[22]), .i27(i27[22]), .i26(i26[22]), .i25(i25[22]), .i24(i24[22]), .i23(i23[22]), .i22(i22[22]), .i21(i21[22]), .i20(i20[22]), .i19(i19[22]), .i18(i18[22]), .i17(i17[22]), .i16(i16[22]), .i15(i15[22]), .i14(i14[22]), .i13(i13[22]), .i12(i12[22]), .i11(i11[22]), .i10(i10[22]), .i9(i9[22]), .i8(i8[22]), .i7(i7[22]), .i6(i6[22]), .i5(i5[22]), .i4(i4[22]), .i3(i3[22]), .i2(i2[22]), .i1(i1[22]), .i0(i0[22]), .s(s));
+
+
+mux_32to1 mux23(.z(z[23]), .i31(i31[23]), .i30(i30[23]), .i29(i29[23]), .i28(i28[23]), .i27(i27[23]), .i26(i26[23]), .i25(i25[23]), .i24(i24[23]), .i23(i23[23]), .i22(i22[23]), .i21(i21[23]), .i20(i20[23]), .i19(i19[23]), .i18(i18[23]), .i17(i17[23]), .i16(i16[23]), .i15(i15[23]), .i14(i14[23]), .i13(i13[23]), .i12(i12[23]), .i11(i11[23]), .i10(i10[23]), .i9(i9[23]), .i8(i8[23]), .i7(i7[23]), .i6(i6[23]), .i5(i5[23]), .i4(i4[23]), .i3(i3[23]), .i2(i2[23]), .i1(i1[23]), .i0(i0[23]), .s(s));
+
+mux_32to1 mux24(.z(z[24]), .i31(i31[24]), .i30(i30[24]), .i29(i29[24]), .i28(i28[24]), .i27(i27[24]), .i26(i26[24]), .i25(i25[24]), .i24(i24[24]), .i23(i23[24]), .i22(i22[24]), .i21(i21[24]), .i20(i20[24]), .i19(i19[24]), .i18(i18[24]), .i17(i17[24]), .i16(i16[24]), .i15(i15[24]), .i14(i14[24]), .i13(i13[24]), .i12(i12[24]), .i11(i11[24]), .i10(i10[24]), .i9(i9[24]), .i8(i8[24]), .i7(i7[24]), .i6(i6[24]), .i5(i5[24]), .i4(i4[24]), .i3(i3[24]), .i2(i2[24]), .i1(i1[24]), .i0(i0[24]), .s(s));
+
+mux_32to1 mux25(.z(z[25]), .i31(i31[25]), .i30(i30[25]), .i29(i29[25]), .i28(i28[25]), .i27(i27[25]), .i26(i26[25]), .i25(i25[25]), .i24(i24[25]), .i23(i23[25]), .i22(i22[25]), .i21(i21[25]), .i20(i20[25]), .i19(i19[25]), .i18(i18[25]), .i17(i17[25]), .i16(i16[25]), .i15(i15[25]), .i14(i14[25]), .i13(i13[25]), .i12(i12[25]), .i11(i11[25]), .i10(i10[25]), .i9(i9[25]), .i8(i8[25]), .i7(i7[25]), .i6(i6[25]), .i5(i5[25]), .i4(i4[25]), .i3(i3[25]), .i2(i2[25]), .i1(i1[25]), .i0(i0[25]), .s(s));
+
+mux_32to1 mux26(.z(z[26]), .i31(i31[26]), .i30(i30[26]), .i29(i29[26]), .i28(i28[26]), .i27(i27[26]), .i26(i26[26]), .i25(i25[26]), .i24(i24[26]), .i23(i23[26]), .i22(i22[26]), .i21(i21[26]), .i20(i20[26]), .i19(i19[26]), .i18(i18[26]), .i17(i17[26]), .i16(i16[26]), .i15(i15[26]), .i14(i14[26]), .i13(i13[26]), .i12(i12[26]), .i11(i11[26]), .i10(i10[26]), .i9(i9[26]), .i8(i8[26]), .i7(i7[26]), .i6(i6[26]), .i5(i5[26]), .i4(i4[26]), .i3(i3[26]), .i2(i2[26]), .i1(i1[26]), .i0(i0[26]), .s(s));
+
+mux_32to1 mux27(.z(z[27]), .i31(i31[27]), .i30(i30[27]), .i29(i29[27]), .i28(i28[27]), .i27(i27[27]), .i26(i26[27]), .i25(i25[27]), .i24(i24[27]), .i23(i23[27]), .i22(i22[27]), .i21(i21[27]), .i20(i20[27]), .i19(i19[27]), .i18(i18[27]), .i17(i17[27]), .i16(i16[27]), .i15(i15[27]), .i14(i14[27]), .i13(i13[27]), .i12(i12[27]), .i11(i11[27]), .i10(i10[27]), .i9(i9[27]), .i8(i8[27]), .i7(i7[27]), .i6(i6[27]), .i5(i5[27]), .i4(i4[27]), .i3(i3[27]), .i2(i2[27]), .i1(i1[27]), .i0(i0[27]), .s(s));
+
+mux_32to1 mux28(.z(z[28]), .i31(i31[28]), .i30(i30[28]), .i29(i29[28]), .i28(i28[28]), .i27(i27[28]), .i26(i26[28]), .i25(i25[28]), .i24(i24[28]), .i23(i23[28]), .i22(i22[28]), .i21(i21[28]), .i20(i20[28]), .i19(i19[28]), .i18(i18[28]), .i17(i17[28]), .i16(i16[28]), .i15(i15[28]), .i14(i14[28]), .i13(i13[28]), .i12(i12[28]), .i11(i11[28]), .i10(i10[28]), .i9(i9[28]), .i8(i8[28]), .i7(i7[28]), .i6(i6[28]), .i5(i5[28]), .i4(i4[28]), .i3(i3[28]), .i2(i2[28]), .i1(i1[28]), .i0(i0[28]), .s(s));
+
+mux_32to1 mux29(.z(z[29]), .i31(i31[29]), .i30(i30[29]), .i29(i29[29]), .i28(i28[29]), .i27(i27[29]), .i26(i26[29]), .i25(i25[29]), .i24(i24[29]), .i23(i23[29]), .i22(i22[29]), .i21(i21[29]), .i20(i20[29]), .i19(i19[29]), .i18(i18[29]), .i17(i17[29]), .i16(i16[29]), .i15(i15[29]), .i14(i14[29]), .i13(i13[29]), .i12(i12[29]), .i11(i11[29]), .i10(i10[29]), .i9(i9[29]), .i8(i8[29]), .i7(i7[29]), .i6(i6[29]), .i5(i5[29]), .i4(i4[29]), .i3(i3[29]), .i2(i2[29]), .i1(i1[29]), .i0(i0[29]), .s(s));
+
+mux_32to1 mux30(.z(z[30]), .i31(i31[30]), .i30(i30[30]), .i29(i29[30]), .i28(i28[30]), .i27(i27[30]), .i26(i26[30]), .i25(i25[30]), .i24(i24[30]), .i23(i23[30]), .i22(i22[30]), .i21(i21[30]), .i20(i20[30]), .i19(i19[30]), .i18(i18[30]), .i17(i17[30]), .i16(i16[30]), .i15(i15[30]), .i14(i14[30]), .i13(i13[30]), .i12(i12[30]), .i11(i11[30]), .i10(i10[30]), .i9(i9[30]), .i8(i8[30]), .i7(i7[30]), .i6(i6[30]), .i5(i5[30]), .i4(i4[30]), .i3(i3[30]), .i2(i2[30]), .i1(i1[30]), .i0(i0[30]), .s(s));
+
+mux_32to1 mux31(.z(z[31]), .i31(i31[31]), .i30(i30[31]), .i29(i29[31]), .i28(i28[31]), .i27(i27[31]), .i26(i26[31]), .i25(i25[31]), .i24(i24[31]), .i23(i23[31]), .i22(i22[31]), .i21(i21[31]), .i20(i20[31]), .i19(i19[31]), .i18(i18[31]), .i17(i17[31]), .i16(i16[31]), .i15(i15[31]), .i14(i14[31]), .i13(i13[31]), .i12(i12[31]), .i11(i11[31]), .i10(i10[31]), .i9(i9[31]), .i8(i8[31]), .i7(i7[31]), .i6(i6[31]), .i5(i5[31]), .i4(i4[31]), .i3(i3[31]), .i2(i2[31]), .i1(i1[31]), .i0(i0[31]), .s(s));
+
+endmodule
+"
+"module demux_32to1 (input [a
+"
+"module shift_left_2 (
+  input  [31:0] a,
+  output [31:0] b); 
+
+  buf (b[31], a[29]);
+  buf (b[30], a[28]);
+  buf (b[29], a[27]);
+  buf (b[28], a[26]);
+  buf (b[27], a[25]);
+  buf (b[26], a[24]);
+  buf (b[25], a[23]);
+  buf (b[24], a[22]);
+  buf (b[23], a[21]);
+  buf (b[22], a[20]);
+  buf (b[21], a[19]);
+  buf (b[20], a[18]);
+  buf (b[19], a[17]);
+  buf (b[18], a[16]);
+  buf (b[17], a[15]);
+  buf (b[16], a[14]);
+  buf (b[15], a[13]);
+  buf (b[14], a[12]);
+  buf (b[13], a[11]);
+  buf (b[12], a[10]);
+  buf (b[11], a[9 ]);
+  buf (b[10], a[8 ]);
+  buf (b[9 ], a[7 ]);
+  buf (b[8 ], a[6 ]);
+  buf (b[7 ], a[5 ]);
+  buf (b[6 ], a[4 ]);
+  buf (b[5 ], a[3 ]);
+  buf (b[4 ], a[2]);
+  buf (b[3 ], a[1 ]);
+  buf (b[2 ], a[0 ]);
+  buf (b[1 ], 1'b0 );
+  buf (b[0 ], 1'b0 );
+
+endmodule
+"
+"`include ""../lib/mux32bits_32to1.v""
+
+module test;
+
+  reg  [4:0] s;
+  reg  [31:0] i31, i30, i29, i28, i27, i26, i25, i24, i23,i22, i21, i20, i19, i18, i17, i16;
+  reg  [31:0] i15, i14, i13, i12, i11, i10, i9, i8, i7,i6, i5, i4, i3, i2, i1, i0;
+  wire [31:0] z;
+
+  reg [31:0] val, expect;
+  mux32bits_32to1 mux(
+    .s  (s ),
+    .i31(i31),  
+    .i30(i30),
+    .i29(i29),
+    .i28(i28),
+    .i27(i27),
+    .i26(i26),
+    .i25(i25),
+    .i24(i24),
+    .i23(i23),
+    .i22(i22),
+    .i21(i21),
+    .i20(i20),
+    .i19(i19),
+    .i18(i18),
+    .i17(i17),
+    .i16(i16),
+    .i15(i15),   
+    .i14(i14),
+    .i13(i13),
+    .i12(i12),
+    .i11(i11),
+    .i10(i10),
+    .i9 (i9 ),
+    .i8 (i8 ),
+    .i7 (i7 ),
+    .i6 (i6 ),
+    .i5 (i5 ),
+    .i4 (i4 ),
+    .i3 (i3 ),
+    .i2 (i2 ),
+    .i1 (i1 ),
+    .i0 (i0 ),
+    .z  (z ));
+ 
+  initial begin
+    $monitor($time, "": val=%d expect=%d"", val, expect);
+    #5 i31 = 5  ; val = i31; s = 5\'b11111; expect = 5  ;
+    #5 i25 = 345; val = i25; s = 5\'b11001; expect = 345;
+    #5 i6  = 35 ; val = i6 ; s = 5\'b00110; expect = 35 ;
+    #5 i16 = 276; val = i16; s = 5\'b10000; expect = 276; 
+  end
+
+endmodule
+"
+"`include ""../lib/dec_5to32.v""
+
+module test;
+
+  reg [4:0] a;
+  wire [31:0] b;
+
+  dec_5to32 dec (a, b);
+
+  initial begin
+
+    $monitor($time ,"": a=%5d, b=%5d"",a , b);
+
+    #5 a = 0; 
+    #5 a = 5\'b00001;
+    #5 a = 5\'b00100;
+    #5 a = 5\'b01000;
+  end
+
+endmodule
+"
+"`include ""../lib/flip_flop.v""
+
+module reg_32bits (
+  input [31:0] d,
+  input we, clk,
+  output [31:0] q);
+ 
+  d_flip_flop dff0 (.q(q[0 ]), .d(d[0 ]), .we(we), .clk(clk));
+  d_flip_flop dff1 (.q(q[1 ]), .d(d[1 ]), .we(we), .clk(clk));
+  d_flip_flop dff2 (.q(q[2 ]), .d(d[2 ]), .we(we), .clk(clk));
+  d_flip_flop dff3 (.q(q[3 ]), .d(d[3 ]), .we(we), .clk(clk));
+  d_flip_flop dff4 (.q(q[4 ]), .d(d[4 ]), .we(we), .clk(clk));
+  d_flip_flop dff5 (.q(q[5 ]), .d(d[5 ]), .we(we), .clk(clk));
+  d_flip_flop dff6 (.q(q[6 ]), .d(d[6 ]), .we(we), .clk(clk));
+  d_flip_flop dff7 (.q(q[7 ]), .d(d[7 ]), .we(we), .clk(clk));
+  d_flip_flop dff8 (.q(q[8 ]), .d(d[8 ]), .we(we), .clk(clk));
+  d_flip_flop dff9 (.q(q[9 ]), .d(d[9 ]), .we(we), .clk(clk));
+  d_flip_flop dff10(.q(q[10]), .d(d[10]), .we(we), .clk(clk));
+  d_flip_flop dff11(.q(q[11]), .d(d[11]), .we(we), .clk(clk));
+  d_flip_flop dff12(.q(q[12]), .d(d[12]), .we(we), .clk(clk));
+  d_flip_flop dff13(.q(q[13]), .d(d[13]), .we(we), .clk(clk));
+  d_flip_flop dff14(.q(q[14]), .d(d[14]), .we(we), .clk(clk));
+  d_flip_flop dff15(.q(q[15]), .d(d[15]), .we(we), .clk(clk));
+  d_flip_flop dff16(.q(q[16]), .d(d[16]), .we(we), .clk(clk));
+  d_flip_flop dff17(.q(q[17]), .d(d[17]), .we(we), .clk(clk));
+  d_flip_flop dff18(.q(q[18]), .d(d[18]), .we(we), .clk(clk));
+  d_flip_flop dff19(.q(q[19]), .d(d[19]), .we(we), .clk(clk));
+  d_flip_flop dff20(.q(q[20]), .d(d[20]), .we(we), .clk(clk));
+  d_flip_flop dff21(.q(q[21]), .d(d[21]), .we(we), .clk(clk));
+  d_flip_flop dff22(.q(q[22]), .d(d[22]), .we(we), .clk(clk));
+  d_flip_flop dff23(.q(q[23]), .d(d[23]), .we(we), .clk(clk));
+  d_flip_flop dff24(.q(q[24]), .d(d[24]), .we(we), .clk(clk));
+  d_flip_flop dff25(.q(q[25]), .d(d[25]), .we(we), .clk(clk));
+  d_flip_flop dff26(.q(q[26]), .d(d[26]), .we(we), .clk(clk));
+  d_flip_flop dff27(.q(q[27]), .d(d[27]), .we(we), .clk(clk));
+  d_flip_flop dff28(.q(q[28]), .d(d[28]), .we(we), .clk(clk));
+  d_flip_flop dff29(.q(q[29]), .d(d[29]), .we(we), .clk(clk));
+  d_flip_flop dff30(.q(q[30]), .d(d[30]), .we(we), .clk(clk));
+  d_flip_flop dff31(.q(q[31]), .d(d[31]), .we(we), .clk(clk));
+
+endmodule
+"
+"`include ""../lib/mux_2to1.v""
+
+module test;
+
+  reg s, i0, i1;
+  wire z;
+
+  mux_2to1 mux(
+    .s (s ),
+    .i1(i1),
+    .i0(i0),
+    .z (z));
+
+  initial begin
+    $monitor($time, "": %b  %b  | %b | %b"", i1,  i0, s, z);
+    
+    #5 i1 = 0; i0 = 0; s = 0;
+    #5 i1 = 1;
+    #5 i0 = 1;
+    #5 i1 = 0;
+    #5 s  = 1; 
+ end
+
+endmodule
+
+ 
+"
+"`include ""../CPU/cpu.v""
+
+module cpu_test;
+
+  reg clk;
+  reg [31:0] addr;
+  wire [31:0] alu_output, data;
+  wire [31:0] pc_4;
+  cpu c(.clk(clk), .alu_output(alu_output), .data(data), .nxt_pc(pc_4));
+  reg [31:0] regVal;
+  integer i;
+  always #1 clk = ~clk;
+  initial begin
+    $dumpfile(""cpu.vcd"");
+    $dumpvars(0, cpu_test);
+    clk = 0;
+   // for(i = 0; i < 223; i = i + 1) begin
+   // #2; $display(""pc_4 = %h, data = %h"", pc_4, data);
+     // if($isunknown(data)) begin 
+      //  break;
+     // end
+    //end
+    i = 0;
+    while (i < 233) begin
+    #2 ;//$display(""pc_4 = %h, data = %b"", pc_4, data);
+    i = i + 1;
+    end
+    
+    //for(i = 0; i < 32; i = i + 1) begin
+     // regVal = c.rf.regs[i];
+     // #2 $display(""pc_4 = %h, data = %h, $s%d  = %h"", pc_4, data, i,regVal);
+    //end
+    //#2; $display(""Final value of PC = %h"", pc_4 );
+    #2; $display(""$0  = %h"", c.rf.regs[0 ] );
+    #2; $display(""$at = %h"", c.rf.regs[1 ] );
+    #2; $display(""$v0 = %h"", c.rf.regs[2 ] );
+    #2; $display(""$v1 = %h"", c.rf.regs[3 ] );
+    #2; $display(""$a0 = %h"", c.rf.regs[4 ] );
+    #2; $display(""$a1 = %h"", c.rf.regs[5 ] );
+    #2; $display(""$a2 = %h"", c.rf.regs[6 ] );
+    #2; $display(""$a3 = %h"", c.rf.regs[7 ] );
+    #2; $display(""$t0 = %h"", c.rf.regs[8 ] );
+    #2; $display(""$t1 = %h"", c.rf.regs[9 ] );
+    #2; $display(""$t2 = %h"", c.rf.regs[10] );
+    #2; $display(""$t3 = %h"", c.rf.regs[11] );
+    #2; $display(""$t4 = %h"", c.rf.regs[12] );
+    #2; $display(""$t5 = %h"", c.rf.regs[13] );
+    #2; $display(""$t6 = %h"", c.rf.regs[14] );
+    #2; $display(""$t7 = %h"", c.rf.regs[15] );
+    #2; $display(""$s0 = %h"", c.rf.regs[16] );
+    #2; $display(""$s1 = %h"", c.rf.regs[17] );
+    #2; $display(""$s2 = %h"", c.rf.regs[18] );
+    #2; $display(""$s3 = %h"", c.rf.regs[19] );
+    #2; $display(""$s4 = %h"", c.rf.regs[20] );
+    #2; $display(""$s5 = %h"", c.rf.regs[21] );
+    #2; $display(""$s6 = %h"", c.rf.regs[22] );
+    #2; $display(""$s7 = %h"", c.rf.regs[23] );
+    #2; $display(""$t8 = %h"", c.rf.regs[24] );
+    #2; $display(""$t9 = %h"", c.rf.regs[25] );
+    #2; $display(""$k0 = %h"", c.rf.regs[26] );
+    #2; $display(""$k1 = %h"", c.rf.regs[27] );
+    #2; $display(""$gp = %h"", c.rf.regs[28] );
+    #2; $display(""$sp = %h"", c.rf.regs[29] );
+    #2; $display(""$fp = %h"", c.rf.regs[30] );
+    #2; $display(""$ra = %h"", c.rf.regs[31] );
+    $finish;                                      
+  end
+endmodule
+"
+"module jump_addr(
+  input [25:0] inst,
+  input [3:0] pc_4,
+  output[31:0] j_addr);
+
+  buf (j_addr[0 ] ,inst[0 ]);
+  buf (j_addr[1 ] ,inst[1 ]);
+  buf (j_addr[2 ] ,inst[2 ]);
+  buf (j_addr[3 ] ,inst[3 ]);
+  buf (j_addr[4 ] ,inst[4 ]);
+  buf (j_addr[5 ] ,inst[5 ]);
+  buf (j_addr[6 ] ,inst[6 ]);
+  buf (j_addr[7 ] ,inst[7 ]);
+  buf (j_addr[8 ] ,inst[8 ]);
+  buf (j_addr[9 ] ,inst[9 ]);
+  buf (j_addr[10] ,inst[10]);
+  buf (j_addr[11] ,inst[11]);
+  buf (j_addr[12] ,inst[12]);
+  buf (j_addr[13] ,inst[13]);
+  buf (j_addr[14] ,inst[14]);
+  buf (j_addr[15] ,inst[15]);
+  buf (j_addr[16] ,inst[16]);
+  buf (j_addr[17] ,inst[17]);
+  buf (j_addr[18] ,inst[18]);
+  buf (j_addr[19] ,inst[19]);
+  buf (j_addr[20] ,inst[20]);
+  buf (j_addr[21] ,inst[21]);
+  buf (j_addr[22] ,inst[22]);
+  buf (j_addr[23] ,inst[23]);
+  buf (j_addr[24] ,inst[24]);
+  buf (j_addr[25] ,inst[25]);
+  buf (j_addr[26] ,1'b0    );
+  buf (j_addr[27] ,1'b0    );
+  buf (j_addr[28] ,pc_4[0 ]);
+  buf (j_addr[29] ,pc_4[1 ]);
+  buf (j_addr[30] ,pc_4[2 ]);
+  buf (j_addr[31] ,pc_4[3 ]);
+
+endmodule
+"
+"`include ""../lib/full_adder.v""
+module add (
+  output cout,
+  output [31:0] sum,
+  input [31:0] a, b,
+  input cin
+  );
+wire [30:0] carry;
+
+full_adder addr0  (.cout(carry[ 0]), .sum(sum[ 0]), .a(a[ 0]), .b(b[ 0]), .cin(cin      ));
+full_adder addr1  (.cout(carry[ 1]), .sum(sum[ 1]), .a(a[ 1]), .b(b[ 1]), .cin(carry[ 0]));
+full_adder addr2  (.cout(carry[ 2]), .sum(sum[ 2]), .a(a[ 2]), .b(b[ 2]), .cin(carry[ 1]));
+full_adder addr3  (.cout(carry[ 3]), .sum(sum[ 3]), .a(a[ 3]), .b(b[ 3]), .cin(carry[ 2]));
+full_adder addr4  (.cout(carry[ 4]), .sum(sum[ 4]), .a(a[ 4]), .b(b[ 4]), .cin(carry[ 3]));
+full_adder addr5  (.cout(carry[ 5]), .sum(sum[ 5]), .a(a[ 5]), .b(b[ 5]), .cin(carry[ 4]));
+full_adder addr6  (.cout(carry[ 6]), .sum(sum[ 6]), .a(a[ 6]), .b(b[ 6]), .cin(carry[ 5]));
+full_adder addr7  (.cout(carry[ 7]), .sum(sum[ 7]), .a(a[ 7]), .b(b[ 7]), .cin(carry[ 6]));
+full_adder addr8  (.cout(carry[ 8]), .sum(sum[ 8]), .a(a[ 8]), .b(b[ 8]), .cin(carry[ 7]));
+full_adder addr9  (.cout(carry[ 9]), .sum(sum[ 9]), .a(a[ 9]), .b(b[ 9]), .cin(carry[ 8]));
+full_adder addr10 (.cout(carry[10]), .sum(sum[10]), .a(a[10]), .b(b[10]), .cin(carry[ 9]));
+full_adder addr11 (.cout(carry[11]), .sum(sum[11]), .a(a[11]), .b(b[11]), .cin(carry[10]));
+full_adder addr12 (.cout(carry[12]), .sum(sum[12]), .a(a[12]), .b(b[12]), .cin(carry[11]));
+full_adder addr13 (.cout(carry[13]), .sum(sum[13]), .a(a[13]), .b(b[13]), .cin(carry[12]));
+full_adder addr14 (.cout(carry[14]), .sum(sum[14]), .a(a[14]), .b(b[14]), .cin(carry[13]));
+full_adder addr15 (.cout(carry[15]), .sum(sum[15]), .a(a[15]), .b(b[15]), .cin(carry[14]));
+full_adder addr16 (.cout(carry[16]), .sum(sum[16]), .a(a[16]), .b(b[16]), .cin(carry[15]));
+full_adder addr17 (.cout(carry[17]), .sum(sum[17]), .a(a[17]), .b(b[17]), .cin(carry[16]));
+full_adder addr18 (.cout(carry[18]), .sum(sum[18]), .a(a[18]), .b(b[18]), .cin(carry[17]));
+full_adder addr19 (.cout(carry[19]), .sum(sum[19]), .a(a[19]), .b(b[19]), .cin(carry[18]));
+full_adder addr20 (.cout(carry[20]), .sum(sum[20]), .a(a[20]), .b(b[20]), .cin(carry[19]));
+full_adder addr21 (.cout(carry[21]), .sum(sum[21]), .a(a[21]), .b(b[21]), .cin(carry[20]));
+full_adder addr22 (.cout(carry[22]), .sum(sum[22]), .a(a[22]), .b(b[22]), .cin(carry[21]));
+full_adder addr23 (.cout(carry[23]), .sum(sum[23]), .a(a[23]), .b(b[23]), .cin(carry[22]));
+full_adder addr24 (.cout(carry[24]), .sum(sum[24]), .a(a[24]), .b(b[24]), .cin(carry[23]));
+full_adder addr25 (.cout(carry[25]), .sum(sum[25]), .a(a[25]), .b(b[25]), .cin(carry[24]));
+full_adder addr26 (.cout(carry[26]), .sum(sum[26]), .a(a[26]), .b(b[26]), .cin(carry[25]));
+full_adder addr27 (.cout(carry[27]), .sum(sum[27]), .a(a[27]), .b(b[27]), .cin(carry[26]));
+full_adder addr28 (.cout(carry[28]), .sum(sum[28]), .a(a[28]), .b(b[28]), .cin(carry[27]));
+full_adder addr29 (.cout(carry[29]), .sum(sum[29]), .a(a[29]), .b(b[29]), .cin(carry[28]));
+full_adder addr30 (.cout(carry[30]), .sum(sum[30]), .a(a[30]), .b(b[30]), .cin(carry[29]));
+full_adder addr31 (.cout(cout     ), .sum(sum[31]), .a(a[31]), .b(b[31]), .cin(carry[30]));
+
+endmodule
+"
+"`include ""../control/control2.v""
+
+module test;
+
+  reg  [5:0] op;
+  wire [2:0] alu_op;
+  wire regDst, aluSrc, memToReg, regWrite;
+  wire memRead, memWrite, branch;
+  reg [8:0] expect;
+  control c(
+    .op(op),
+    .alu_op(alu_op),
+    .regDst(regDst),
+    .aluSrc(aluSrc),
+    .memToReg(memToReg),
+    .regWrite(regWrite),
+    .memRead(memRead),
+    .memWrite(memWrite),
+    .branch(branch));
+
+  initial begin
+    $monitor($time, "": op=%b\\t %b%b%b%b%b%b%b%b\\t expect=%b"", op, regDst, aluSrc, memToReg, regWrite, memRead, memWrite, branch, alu_op, expect);
+    #5 op = 0;          expect = 9\'b100100010;
+    #5 op = 6\'b 100011; expect = 9\'b011110000;
+    #5 op = 6\'b 101011; expect = 9\'bx1x001000;
+    #5 op = 6\'b 000100; expect = 9\'bx0x000101;
+  end
+endmodule
+"
+"`include ""../RF/reg_file2.v""
+
+module test;
+
+  reg [4:0] readReg1, readReg2, writeReg;
+  reg [31:0] writeData;
+  reg regWrite, clk;
+  wire [31:0] readData1, readData2;
+
+  reg_file rf(.readReg1(readReg1),
+    .readReg2(readReg2),
+    .writeReg(writeReg),
+    .writeData(writeData),
+    .regWrite(regWrite),
+    .clk(clk),
+    .readData1(readData1),
+    .readData2(readData2));
+
+  initial begin
+    $dumpfile(""reg_file_wave.vcd"");
+    $dumpvars(0, test);
+    //$monitor($time, "": readReg1=%5d, readReg2=%5d, writeReg=%5d, writeData=%5d, regWrite=%b, readData1=%5d, readData2=%5d"",
+      //                  readReg1, readReg2, writeReg, writeData, regWrite, readData1, readData2);
+    clk = 0;
+    #5 writeReg = 0; writeData = 10; regWrite = 1;
+    #5 writeReg = 5; 
+    #5 writeReg = 6; 
+    #5 writeReg = 17; 
+    #5 writeReg = 18; 
+    #5 writeReg = 19; 
+    #5 writeReg = 20; 
+    #5 writeReg = 21; 
+    #5 writeReg = 22; 
+    #5 writeReg = 23; 
+    #5 writeReg = 24; 
+    #5 writeReg = 25; 
+    #5 writeReg = 26; 
+    #5 writeReg = 27; 
+    #5 writeReg = 28; 
+    #5 writeReg = 29; 
+    #5 writeReg = 30; 
+    #5 writeReg = 31; 
+    #5 readReg1 = 0; readReg2 = 2;
+    #5;
+    $display("": readReg1=%5d, readReg2=%5d, writeReg=%5d, writeData=%5d, regWrite=%b, readData1=%5d, readData2=%5d"",
+                        readReg1, readReg2, writeReg, writeData, regWrite, readData1, readData2);
+
+    $finish;
+  end
+
+  always #1 clk = ~clk;
+
+endmodule
+"
+"`include ""../RF/reg_file.v""
+
+module test;
+
+  reg [4:0] readReg1, readReg2, writeReg;
+  reg [31:0] writeData;
+  reg regWrite, clk;
+  wire [31:0] readData1, readData2;
+
+  reg_file rf(.readReg1(readReg1),
+    .readReg2(readReg2),
+    .writeReg(writeReg),
+    .writeData(writeData),
+    .regWrite(regWrite),
+    .clk(clk),
+    .readData1(readData1),
+    .readData2(readData2));
+
+  initial begin
+    $dumpfile(""reg_file_wave.vcd"");
+    $dumpvars(0, test);
+    //$monitor($time, "": readReg1=%5d, readReg2=%5d, writeReg=%5d, writeData=%5d, regWrite=%b, readData1=%5d, readData2=%5d"",
+      //                  readReg1, readReg2, writeReg, writeData, regWrite, readData1, readData2);
+    clk = 0;
+    #5 writeReg = 0; writeData = 10; regWrite = 1;
+    #5 writeReg = 1; 
+    #5 writeReg = 2; 
+    #5 writeReg = 3; 
+    #5 writeReg = 4; 
+    #5 writeReg = 5; 
+    #5 writeReg = 6; 
+    #5 writeReg = 7; 
+    #5 writeReg = 8; 
+    #5 writeReg = 9; 
+    #5 writeReg = 10; 
+    #5 writeReg = 11; 
+    #5 writeReg = 12; 
+    #5 writeReg = 13; 
+    #5 writeReg = 14; 
+    #5 writeReg = 15; 
+    #5 writeReg = 16; 
+    #5 writeReg = 17; 
+    #5 writeReg = 18; 
+    #5 writeReg = 19; 
+    #5 writeReg = 20; 
+    #5 writeReg = 21; 
+    #5 writeReg = 22; 
+    #5 writeReg = 23; 
+    #5 writeReg = 24; 
+    #5 writeReg = 25; 
+    #5 writeReg = 26; 
+    #5 writeReg = 27; 
+    #5 writeReg = 28; 
+    #5 writeReg = 29; 
+    #5 writeReg = 30; 
+    #5 writeReg = 31; 
+    #5 readReg1 = 0; readReg2 = 2;
+    #5;
+    $display("": readReg1=%5d, readReg2=%5d, writeReg=%5d, writeData=%5d, regWrite=%b, readData1=%5d, readData2=%5d"",
+                        readReg1, readReg2, writeReg, writeData, regWrite, readData1, readData2);
+
+    $finish;
+  end
+
+  always #1 clk = ~clk;
+
+endmodule
+"
+"module alu_control (
+  input [5:0] funct,
+  input [1:0] alu_op,
+  output [3:0] aluctrl );
+  
+  wire int0, int1, int2, int3, int4, int5;
+  wire funct0_bar, funct1_bar, funct2_bar, funct3_bar, funct4_bar, funct5_bar; 
+  wire [3:0] int6;
+
+  not (funct0_bar, funct[0]);
+  not (funct1_bar, funct[1]);
+  not (funct2_bar, funct[2]);
+  not (funct3_bar, funct[3]);
+  not (funct4_bar, funct[4]);
+  not (funct5_bar, funct[5]);
+  
+  and (int0, funct[5], funct4_bar, funct3_bar, funct2_bar, funct1_bar, funct0_bar);   //add 100000
+  and (int1, funct[5], funct4_bar, funct3_bar, funct2_bar, funct[1]  , funct0_bar);   //sub 100010
+  and (int2, funct[5], funct4_bar, funct3_bar, funct[2]  , funct1_bar, funct0_bar);   //and 100100
+  and (int3, funct[5], funct4_bar, funct3_bar, funct[2]  , funct1_bar, funct[0]  );   //or  100101
+  and (int4, funct[5], funct4_bar, funct[3]  , funct2_bar, funct[1]  , funct0_bar);   //slt 101010
+  and (int5, funct[5], funct4_bar, funct3_bar, funct[2]  , funct[1]  , funct[0]  );   //nor 100111
+
+  or  (int6[0], int4, int3);
+  or  (int6[1], int4, int1, int0);
+  or  (int6[2], int5, int4,int1);
+  buf (int6[3], int5);
+
+  mux_2to1 mux0(.z(aluctrl[0]), .i0(1'b0     ), .i1(int6[0]), .s(alu_op[1]));
+  mux_2to1 mux1(.z(aluctrl[1]), .i0(1'b1     ), .i1(int6[1]), .s(alu_op[1]));
+  mux_2to1 mux2(.z(aluctrl[2]), .i0(alu_op[0]), .i1(int6[2]), .s(alu_op[1]));
+  mux_2to1 mux3(.z(aluctrl[3]), .i0(1'b0     ), .i1(int6[3]), .s(alu_op[1]));
+
+endmodule
+"
+"`include ""../lib/full_subtractor.v""
+module sub (
+  output Bor_out,
+  output signed [31:0] d,
+  input  signed [31:0] a, b
+  );
+wire [30:0] bor;
+
+full_subtractor sub0  (.Bor_out(bor[ 0]), .d(d[ 0]), .b(a[ 0]), .a(b[ 0]), .Bor_in(0      ));
+full_subtractor sub1  (.Bor_out(bor[ 1]), .d(d[ 1]), .b(a[ 1]), .a(b[ 1]), .Bor_in(bor[ 0]));
+full_subtractor sub2  (.Bor_out(bor[ 2]), .d(d[ 2]), .b(a[ 2]), .a(b[ 2]), .Bor_in(bor[ 1]));
+full_subtractor sub3  (.Bor_out(bor[ 3]), .d(d[ 3]), .b(a[ 3]), .a(b[ 3]), .Bor_in(bor[ 2]));
+full_subtractor sub4  (.Bor_out(bor[ 4]), .d(d[ 4]), .b(a[ 4]), .a(b[ 4]), .Bor_in(bor[ 3]));
+full_subtractor sub5  (.Bor_out(bor[ 5]), .d(d[ 5]), .b(a[ 5]), .a(b[ 5]), .Bor_in(bor[ 4]));
+full_subtractor sub6  (.Bor_out(bor[ 6]), .d(d[ 6]), .b(a[ 6]), .a(b[ 6]), .Bor_in(bor[ 5]));
+full_subtractor sub7  (.Bor_out(bor[ 7]), .d(d[ 7]), .b(a[ 7]), .a(b[ 7]), .Bor_in(bor[ 6]));
+full_subtractor sub8  (.Bor_out(bor[ 8]), .d(d[ 8]), .b(a[ 8]), .a(b[ 8]), .Bor_in(bor[ 7]));
+full_subtractor sub9  (.Bor_out(bor[ 9]), .d(d[ 9]), .b(a[ 9]), .a(b[ 9]), .Bor_in(bor[ 8]));
+full_subtractor sub10 (.Bor_out(bor[10]), .d(d[10]), .b(a[10]), .a(b[10]), .Bor_in(bor[ 9]));
+full_subtractor sub11 (.Bor_out(bor[11]), .d(d[11]), .b(a[11]), .a(b[11]), .Bor_in(bor[10]));
+full_subtractor sub12 (.Bor_out(bor[12]), .d(d[12]), .b(a[12]), .a(b[12]), .Bor_in(bor[11]));
+full_subtractor sub13 (.Bor_out(bor[13]), .d(d[13]), .b(a[13]), .a(b[13]), .Bor_in(bor[12]));
+full_subtractor sub14 (.Bor_out(bor[14]), .d(d[14]), .b(a[14]), .a(b[14]), .Bor_in(bor[13]));
+full_subtractor sub15 (.Bor_out(bor[15]), .d(d[15]), .b(a[15]), .a(b[15]), .Bor_in(bor[14]));
+full_subtractor sub16 (.Bor_out(bor[16]), .d(d[16]), .b(a[16]), .a(b[16]), .Bor_in(bor[15]));
+full_subtractor sub17 (.Bor_out(bor[17]), .d(d[17]), .b(a[17]), .a(b[17]), .Bor_in(bor[16]));
+full_subtractor sub18 (.Bor_out(bor[18]), .d(d[18]), .b(a[18]), .a(b[18]), .Bor_in(bor[17]));
+full_subtractor sub19 (.Bor_out(bor[19]), .d(d[19]), .b(a[19]), .a(b[19]), .Bor_in(bor[18]));
+full_subtractor sub20 (.Bor_out(bor[20]), .d(d[20]), .b(a[20]), .a(b[20]), .Bor_in(bor[19]));
+full_subtractor sub21 (.Bor_out(bor[21]), .d(d[21]), .b(a[21]), .a(b[21]), .Bor_in(bor[20]));
+full_subtractor sub22 (.Bor_out(bor[22]), .d(d[22]), .b(a[22]), .a(b[22]), .Bor_in(bor[21]));
+full_subtractor sub23 (.Bor_out(bor[23]), .d(d[23]), .b(a[23]), .a(b[23]), .Bor_in(bor[22]));
+full_subtractor sub24 (.Bor_out(bor[24]), .d(d[24]), .b(a[24]), .a(b[24]), .Bor_in(bor[23]));
+full_subtractor sub25 (.Bor_out(bor[25]), .d(d[25]), .b(a[25]), .a(b[25]), .Bor_in(bor[24]));
+full_subtractor sub26 (.Bor_out(bor[26]), .d(d[26]), .b(a[26]), .a(b[26]), .Bor_in(bor[25]));
+full_subtractor sub27 (.Bor_out(bor[27]), .d(d[27]), .b(a[27]), .a(b[27]), .Bor_in(bor[26]));
+full_subtractor sub28 (.Bor_out(bor[28]), .d(d[28]), .b(a[28]), .a(b[28]), .Bor_in(bor[27]));
+full_subtractor sub29 (.Bor_out(bor[29]), .d(d[29]), .b(a[29]), .a(b[29]), .Bor_in(bor[28]));
+full_subtractor sub30 (.Bor_out(bor[30]), .d(d[30]), .b(a[30]), .a(b[30]), .Bor_in(bor[29]));
+full_subtractor sub31 (.Bor_out(Bor_out), .d(d[31]), .b(a[31]), .a(b[31]), .Bor_in(bor[30]));
+
+endmodule
+"
+"module mux_8to1 (
+  input [2:0] s,
+  input i7, i6, i5, i4, i3, i2, i1, i0,
+  output z);
+
+wire int0, int1, int2 , int3 , int4 , int5 , int6, int7; 
+wire int8, int9, int10, int11, int12, int13; 
+
+not (s0_bar, s[0]);
+not (s1_bar, s[1]);
+not (s2_bar, s[2]);
+
+and(int0, i0, s2_bar, s1_bar, s0_bar);
+and(int1, i1, s2_bar, s1_bar, s[0]  );
+and(int2, i2, s2_bar, s[1]  , s0_bar);
+and(int3, i3, s2_bar, s[1]  , s[0]  );
+and(int4, i4, s[2]  , s1_bar, s0_bar);
+and(int5, i5, s[2]  , s1_bar, s[0]  );
+and(int6, i6, s[2]  , s[1]  , s0_bar);
+and(int7, i7, s[2]  , s[1]  , s[0]  );
+
+or (int8 , int0 , int1 );
+or (int9 , int2 , int3 );
+or (int10, int4 , int5 );
+or (int11, int6 , int7 );
+or (int12, int8 , int9 );
+or (int13, int10, int11);
+or (z    , int12, int13);
+
+endmodule
+"
+"`include ""../mem/im.v""
+
+module im_test;
+
+  reg clk;
+  reg [31:0] addr;
+  wire [31:0] data;
+
+  always #1 clk = ~clk;
+
+  im m(clk, addr, data);
+  
+  initial begin
+    addr = 0; clk = 0;
+    repeat (224) begin
+      #1 addr = addr + 1;
+    end
+    repeat (30) begin
+      #1 addr = addr + 1;
+    $display($time, "": addr = %h, data= %h"", addr, data);
+    end
+    $finish;
+  end
+endmodule
+"
+"`include ""../lib/full_adder.v""
+module test;
+  reg a, b, cin;
+  wire cout, sum;
+
+  full_adder adder(
+    .cout(cout),
+    .sum(sum),
+    .a(a),
+    .b(b),
+    .cin(cin));
+
+  initial begin
+    $monitor ($time, "":  %b %b %b, %b %b"", a, b, cin, cout, sum);
+    #5 a = 0; b = 0; cin = 0;
+    #5 a = 1;
+    #5 a = 0; b = 1;
+    #5 a = 1;
+    #5 a = 0; b = 0; cin = 1;
+    #5 a = 1; 
+    #5 a = 0; b = 1;
+    #5 a = 1;
+    #7;
+  end
+endmodule
+"
+"`include ""../ALU/alu_control2.v""
+
+module test;
+
+  reg [5:0] funct;
+  reg [2:0] alu_op;
+  wire [3:0] aluctrl;
+  reg [3:0] expect; 
+  alu_control a0 (
+    .funct(funct),
+    .alu_op(alu_op), 
+    .aluctrl(aluctrl));
+  
+  initial begin
+    $monitor ($time, "": funct=%b\\top=%b\\taluctrl=%b\\texpect=%b"", funct, alu_op, aluctrl, expect);  
+    #5 funct  = 6\'b100000; alu_op = 3\'b00; expect = 4\'b0010;
+    #5 alu_op = 3\'b01;     expect = 4\'b0110;
+    #5 alu_op = 3\'b10;     expect = 4\'b0010; //add
+    #5 funct  = 6\'b100010; expect = 4\'b0110; //sub  
+    #5 funct  = 6\'b100100; expect = 4\'b0000; //and
+    #5 funct  = 6\'b100101; expect = 4\'b0001; //or
+    #5 funct  = 6\'b101010; expect = 4\'b0111; //slt
+    #5 funct  = 6\'b100111; expect = 4\'b1100; //nor
+
+  end
+
+endmodule
+"
+"/* Generated by Yosys 0.4+19 (git sha1 abf81d7, clang 3.4-1ubuntu3 -fPIC -Os) */
+
+(* src = ""../lib/mux_2to1.v:1"" *)
+module mux_2to1(i1, i0, s, z);
+  (* src = ""../lib/mux_2to1.v:2"" *)
+  input i1;
+  (* src = ""../lib/mux_2to1.v:2"" *)
+  input i0;
+  (* src = ""../lib/mux_2to1.v:2"" *)
+  input s;
+  (* src = ""../lib/mux_2to1.v:3"" *)
+  output z;
+  (* src = ""../lib/mux_2to1.v:5"" *)
+  wire int0;
+  (* src = ""../lib/mux_2to1.v:5"" *)
+  wire int1;
+  (* src = ""../lib/mux_2to1.v:5"" *)
+  wire s_bar;
+  assign z = int0 | int1;
+  assign int1 = i1 & s;
+  assign int0 = i0 & s_bar;
+  assign s_bar = ~s;
+endmodule
+
+(* src = ""../lib/flip_flop.v:3"" *)
+module d_flip_flop(d, clk, we, q, q_bar);
+  (* src = ""../lib/flip_flop.v:7"" *)
+  wire int0;
+  (* src = ""../lib/flip_flop.v:7"" *)
+  wire int1;
+  (* src = ""../lib/flip_flop.v:4"" *)
+  input d;
+  (* src = ""../lib/flip_flop.v:4"" *)
+  input clk;
+  (* src = ""../lib/flip_flop.v:4"" *)
+  input we;
+  (* src = ""../lib/flip_flop.v:5"" *)
+  output q;
+  (* src = ""../lib/flip_flop.v:5"" *)
+  output q_bar;
+  (* src = ""../lib/flip_flop.v:7"" *)
+  wire ff_input;
+  (* src = ""../lib/flip_flop.v:15"" *)
+  wire _00_;
+  (* src = ""../lib/flip_flop.v:15"" *)
+  wire _01_;
+  (* src = ""../lib/flip_flop.v:16"" *)
+  wire _02_;
+  (* src = ""../lib/flip_flop.v:18"" *)
+  wire _03_;
+  (* src = ""../lib/flip_flop.v:19"" *)
+  wire _04_;
+  (* src = ""../lib/flip_flop.v:9"" *)
+  mux_2to1 mux (
+    .i1(d),
+    .i0(q),
+    .s(we),
+    .z(ff_input)
+  );
+  assign q_bar = ~_04_;
+  assign _04_ = int1 & q;
+  assign q = ~_03_;
+  assign _03_ = int0 & q_bar;
+  assign int1 = ~_02_;
+  assign _02_ = int0 & _00_;
+  assign int0 = ~_01_;
+  assign _01_ = ff_input & _00_;
+  assign _00_ = ~clk;
+endmodule
+
+(* src = ""../RF/reg_32bits.v:3"" *)
+module reg_32bits(d, we, clk, q);
+  (* src = ""../RF/reg_32bits.v:4"" *)
+  input [31:0] d;
+  (* src = ""../RF/reg_32bits.v:5"" *)
+  input clk;
+  (* src = ""../RF/reg_32bits.v:5"" *)
+  input we;
+  (* src = ""../RF/reg_32bits.v:6"" *)
+  output [31:0] q;
+  (* src = ""../RF/reg_32bits.v:8"" *)
+  d_flip_flop dff0 (
+    .d(d[0]),
+    .clk(clk),
+    .we(we),
+    .q(q[0])
+  );
+  (* src = ""../RF/reg_32bits.v:9"" *)
+  d_flip_flop dff1 (
+    .d(d[1]),
+    .clk(clk),
+    .we(we),
+    .q(q[1])
+  );
+  (* src = ""../RF/reg_32bits.v:10"" *)
+  d_flip_flop dff2 (
+    .d(d[2]),
+    .clk(clk),
+    .we(we),
+    .q(q[2])
+  );
+  (* src = ""../RF/reg_32bits.v:11"" *)
+  d_flip_flop dff3 (
+    .d(d[3]),
+    .clk(clk),
+    .we(we),
+    .q(q[3])
+  );
+  (* src = ""../RF/reg_32bits.v:12"" *)
+  d_flip_flop dff4 (
+    .d(d[4]),
+    .clk(clk),
+    .we(we),
+    .q(q[4])
+  );
+  (* src = ""../RF/reg_32bits.v:13"" *)
+  d_flip_flop dff5 (
+    .d(d[5]),
+    .clk(clk),
+    .we(we),
+    .q(q[5])
+  );
+  (* src = ""../RF/reg_32bits.v:14"" *)
+  d_flip_flop dff6 (
+    .d(d[6]),
+    .clk(clk),
+    .we(we),
+    .q(q[6])
+  );
+  (* src = ""../RF/reg_32bits.v:15"" *)
+  d_flip_flop dff7 (
+    .d(d[7]),
+    .clk(clk),
+    .we(we),
+    .q(q[7])
+  );
+  (* src = ""../RF/reg_32bits.v:16"" *)
+  d_flip_flop dff8 (
+    .d(d[8]),
+    .clk(clk),
+    .we(we),
+    .q(q[8])
+  );
+  (* src = ""../RF/reg_32bits.v:17"" *)
+  d_flip_flop dff9 (
+    .d(d[9]),
+    .clk(clk),
+    .we(we),
+    .q(q[9])
+  );
+  (* src = ""../RF/reg_32bits.v:18"" *)
+  d_flip_flop dff10 (
+    .d(d[10]),
+    .clk(clk),
+    .we(we),
+    .q(q[10])
+  );
+  (* src = ""../RF/reg_32bits.v:19"" *)
+  d_flip_flop dff11 (
+    .d(d[11]),
+    .clk(clk),
+    .we(we),
+    .q(q[11])
+  );
+  (* src = ""../RF/reg_32bits.v:20"" *)
+  d_flip_flop dff12 (
+    .d(d[12]),
+    .clk(clk),
+    .we(we),
+    .q(q[12])
+  );
+  (* src = ""../RF/reg_32bits.v:21"" *)
+  d_flip_flop dff13 (
+    .d(d[13]),
+    .clk(clk),
+    .we(we),
+    .q(q[13])
+  );
+  (* src = ""../RF/reg_32bits.v:22"" *)
+  d_flip_flop dff14 (
+    .d(d[14]),
+    .clk(clk),
+    .we(we),
+    .q(q[14])
+  );
+  (* src = ""../RF/reg_32bits.v:23"" *)
+  d_flip_flop dff15 (
+    .d(d[15]),
+    .clk(clk),
+    .we(we),
+    .q(q[15])
+  );
+  (* src = ""../RF/reg_32bits.v:24"" *)
+  d_flip_flop dff16 (
+    .d(d[16]),
+    .clk(clk),
+    .we(we),
+    .q(q[16])
+  );
+  (* src = ""../RF/reg_32bits.v:25"" *)
+  d_flip_flop dff17 (
+    .d(d[17]),
+    .clk(clk),
+    .we(we),
+    .q(q[17])
+  );
+  (* src = ""../RF/reg_32bits.v:26"" *)
+  d_flip_flop dff18 (
+    .d(d[18]),
+    .clk(clk),
+    .we(we),
+    .q(q[18])
+  );
+  (* src = ""../RF/reg_32bits.v:27"" *)
+  d_flip_flop dff19 (
+    .d(d[19]),
+    .clk(clk),
+    .we(we),
+    .q(q[19])
+  );
+  (* src = ""../RF/reg_32bits.v:28"" *)
+  d_flip_flop dff20 (
+    .d(d[20]),
+    .clk(clk),
+    .we(we),
+    .q(q[20])
+  );
+  (* src = ""../RF/reg_32bits.v:29"" *)
+  d_flip_flop dff21 (
+    .d(d[21]),
+    .clk(clk),
+    .we(we),
+    .q(q[21])
+  );
+  (* src = ""../RF/reg_32bits.v:30"" *)
+  d_flip_flop dff22 (
+    .d(d[22]),
+    .clk(clk),
+    .we(we),
+    .q(q[22])
+  );
+  (* src = ""../RF/reg_32bits.v:31"" *)
+  d_flip_flop dff23 (
+    .d(d[23]),
+    .clk(clk),
+    .we(we),
+    .q(q[23])
+  );
+  (* src = ""../RF/reg_32bits.v:32"" *)
+  d_flip_flop dff24 (
+    .d(d[24]),
+    .clk(clk),
+    .we(we),
+    .q(q[24])
+  );
+  (* src = ""../RF/reg_32bits.v:33"" *)
+  d_flip_flop dff25 (
+    .d(d[25]),
+    .clk(clk),
+    .we(we),
+    .q(q[25])
+  );
+  (* src = ""../RF/reg_32bits.v:34"" *)
+  d_flip_flop dff26 (
+    .d(d[26]),
+    .clk(clk),
+    .we(we),
+    .q(q[26])
+  );
+  (* src = ""../RF/reg_32bits.v:35"" *)
+  d_flip_flop dff27 (
+    .d(d[27]),
+    .clk(clk),
+    .we(we),
+    .q(q[27])
+  );
+  (* src = ""../RF/reg_32bits.v:36"" *)
+  d_flip_flop dff28 (
+    .d(d[28]),
+    .clk(clk),
+    .we(we),
+    .q(q[28])
+  );
+  (* src = ""../RF/reg_32bits.v:37"" *)
+  d_flip_flop dff29 (
+    .d(d[29]),
+    .clk(clk),
+    .we(we),
+    .q(q[29])
+  );
+  (* src = ""../RF/reg_32bits.v:38"" *)
+  d_flip_flop dff30 (
+    .d(d[30]),
+    .clk(clk),
+    .we(we),
+    .q(q[30])
+  );
+  (* src = ""../RF/reg_32bits.v:39"" *)
+  d_flip_flop dff31 (
+    .d(d[31]),
+    .clk(clk),
+    .we(we),
+    .q(q[31])
+  );
+endmodule
+
+(* src = ""../lib/mux_32to1.v:1"" *)
+module mux_32to1(s, i31, i30, i29, i28, i27, i26, i25, i24, i23, i22, i21, i20, i19, i18, i17, i16, i15, i14, i13, i12, i11, i10, i9, i8, i7, i6, i5, i4, i3, i2, i1, i0, z);
+  (* src = ""../lib/mux_32to1.v:4"" *)
+  input i1;
+  (* src = ""../lib/mux_32to1.v:4"" *)
+  input i0;
+  (* src = ""../lib/mux_32to1.v:2"" *)
+  input [4:0] s;
+  (* src = ""../lib/mux_32to1.v:5"" *)
+  output z;
+  (* src = ""../lib/mux_32to1.v:7"" *)
+  wire int0;
+  (* src = ""../lib/mux_32to1.v:7"" *)
+  wire int1;
+  (* src = ""../lib/mux_32to1.v:3"" *)
+  input i31;
+  (* src = ""../lib/mux_32to1.v:3"" *)
+  input i30;
+  (* src = ""../lib/mux_32to1.v:3"" *)
+  input i29;
+  (* src = ""../lib/mux_32to1.v:3"" *)
+  input i28;
+  (* src = ""../lib/mux_32to1.v:3"" *)
+  input i27;
+  (* src = ""../lib/mux_32to1.v:3"" *)
+  input i26;
+  (* src = ""../lib/mux_32to1.v:3"" *)
+  input i25;
+  (* src = ""../lib/mux_32to1.v:3"" *)
+  input i24;
+  (* src = ""../lib/mux_32to1.v:3"" *)
+  input i23;
+  (* src = ""../lib/mux_32to1.v:3"" *)
+  input i22;
+  (* src = ""../lib/mux_32to1.v:3"" *)
+  input i21;
+  (* src = ""../lib/mux_32to1.v:3"" *)
+  input i20;
+  (* src = ""../lib/mux_32to1.v:3"" *)
+  input i19;
+  (* src = ""../lib/mux_32to1.v:3"" *)
+  input i18;
+  (* src = ""../lib/mux_32to1.v:3"" *)
+  input i17;
+  (* src = ""../lib/mux_32to1.v:3"" *)
+  input i16;
+  (* src = ""../lib/mux_32to1.v:4"" *)
+  input i15;
+  (* src = ""../lib/mux_32to1.v:4"" *)
+  input i14;
+  (* src = ""../lib/mux_32to1.v:4"" *)
+  input i13;
+  (* src = ""../lib/mux_32to1.v:4"" *)
+  input i12;
+  (* src = ""../lib/mux_32to1.v:4"" *)
+  input i11;
+  (* src = ""../lib/mux_32to1.v:4"" *)
+  input i10;
+  (* src = ""../lib/mux_32to1.v:4"" *)
+  input i9;
+  (* src = ""../lib/mux_32to1.v:4"" *)
+  input i8;
+  (* src = ""../lib/mux_32to1.v:4"" *)
+  input i7;
+  (* src = ""../lib/mux_32to1.v:4"" *)
+  input i6;
+  (* src = ""../lib/mux_32to1.v:4"" *)
+  input i5;
+  (* src = ""../lib/mux_32to1.v:4"" *)
+  input i4;
+  (* src = ""../lib/mux_32to1.v:4"" *)
+  input i3;
+  (* src = ""../lib/mux_32to1.v:4"" *)
+  input i2;
+  (* src = ""../lib/mux_32to1.v:7"" *)
+  wire int2;
+  (* src = ""../lib/mux_32to1.v:7"" *)
+  wire int3;
+  (* src = ""../lib/mux_32to1.v:7"" *)
+  wire int4;
+  (* src = ""../lib/mux_32to1.v:7"" *)
+  wire int5;
+  (* src = ""../lib/mux_32to1.v:7"" *)
+  wire int6;
+  (* src = ""../lib/mux_32to1.v:7"" *)
+  wire int7;
+  (* src = ""../lib/mux_32to1.v:8"" *)
+  wire int8;
+  (* src = ""../lib/mux_32to1.v:8"" *)
+  wire int9;
+  (* src = ""../lib/mux_32to1.v:8"" *)
+  wire int10;
+  (* src = ""../lib/mux_32to1.v:8"" *)
+  wire int11;
+  (* src = ""../lib/mux_32to1.v:8"" *)
+  wire int12;
+  (* src = ""../lib/mux_32to1.v:8"" *)
+  wire int13;
+  (* src = ""../lib/mux_32to1.v:8"" *)
+  wire int14;
+  (* src = ""../lib/mux_32to1.v:8"" *)
+  wire int15;
+  (* src = ""../lib/mux_32to1.v:10"" *)
+  wire s0_bar;
+  (* src = ""../lib/mux_32to1.v:11"" *)
+  wire s1_bar;
+  (* src = ""../lib/mux_32to1.v:12"" *)
+  wire s2_bar;
+  (* src = ""../lib/mux_32to1.v:13"" *)
+  wire s3_bar;
+  (* src = ""../lib/mux_32to1.v:14"" *)
+  wire s4_bar;
+  (* src = ""../lib/mux_32to1.v:17"" *)
+  wire _000_;
+  (* src = ""../lib/mux_32to1.v:17"" *)
+  wire _001_;
+  (* src = ""../lib/mux_32to1.v:17"" *)
+  wire _002_;
+  (* src = ""../lib/mux_32to1.v:17"" *)
+  wire _003_;
+  (* src = ""../lib/mux_32to1.v:18"" *)
+  wire _004_;
+  (* src = ""../lib/mux_32to1.v:18"" *)
+  wire _005_;
+  (* src = ""../lib/mux_32to1.v:18"" *)
+  wire _006_;
+  (* src = ""../lib/mux_32to1.v:18"" *)
+  wire _007_;
+  (* src = ""../lib/mux_32to1.v:19"" *)
+  wire _008_;
+  (* src = ""../lib/mux_32to1.v:19"" *)
+  wire _009_;
+  (* src = ""../lib/mux_32to1.v:19"" *)
+  wire _010_;
+  (* src = ""../lib/mux_32to1.v:19"" *)
+  wire _011_;
+  (* src = ""../lib/mux_32to1.v:20"" *)
+  wire _012_;
+  (* src = ""../lib/mux_32to1.v:20"" *)
+  wire _013_;
+  (* src = ""../lib/mux_32to1.v:20"" *)
+  wire _014_;
+  (* src = ""../lib/mux_32to1.v:20"" *)
+  wire _015_;
+  (* src = ""../lib/mux_32to1.v:21"" *)
+  wire _016_;
+  (* src = ""../lib/mux_32to1.v:21"" *)
+  wire _017_;
+  (* src = ""../lib/mux_32to1.v:21"" *)
+  wire _018_;
+  (* src = ""../lib/mux_32to1.v:21"" *)
+  wire _019_;
+  (* src = ""../lib/mux_32to1.v:22"" *)
+  wire _020_;
+  (* src = ""../lib/mux_32to1.v:22"" *)
+  wire _021_;
+  (* src = ""../lib/mux_32to1.v:22"" *)
+  wire _022_;
+  (* src = ""../lib/mux_32to1.v:22"" *)
+  wire _023_;
+  (* src = ""../lib/mux_32to1.v:23"" *)
+  wire _024_;
+  (* src = ""../lib/mux_32to1.v:23"" *)
+  wire _025_;
+  (* src = ""../lib/mux_32to1.v:23"" *)
+  wire _026_;
+  (* src = ""../lib/mux_32to1.v:23"" *)
+  wire _027_;
+  (* src = ""../lib/mux_32to1.v:24"" *)
+  wire _028_;
+  (* src = ""../lib/mux_32to1.v:24"" *)
+  wire _029_;
+  (* src = ""../lib/mux_32to1.v:24"" *)
+  wire _030_;
+  (* src = ""../lib/mux_32to1.v:24"" *)
+  wire _031_;
+  (* src = ""../lib/mux_32to1.v:25"" *)
+  wire _032_;
+  (* src = ""../lib/mux_32to1.v:25"" *)
+  wire _033_;
+  (* src = ""../lib/mux_32to1.v:25"" *)
+  wire _034_;
+  (* src = ""../lib/mux_32to1.v:25"" *)
+  wire _035_;
+  (* src = ""../lib/mux_32to1.v:26"" *)
+  wire _036_;
+  (* src = ""../lib/mux_32to1.v:26"" *)
+  wire _037_;
+  (* src = ""../lib/mux_32to1.v:26"" *)
+  wire _038_;
+  (* src = ""../lib/mux_32to1.v:26"" *)
+  wire _039_;
+  (* src = ""../lib/mux_32to1.v:27"" *)
+  wire _040_;
+  (* src = ""../lib/mux_32to1.v:27"" *)
+  wire _041_;
+  (* src = ""../lib/mux_32to1.v:27"" *)
+  wire _042_;
+  (* src = ""../lib/mux_32to1.v:27"" *)
+  wire _043_;
+  (* src = ""../lib/mux_32to1.v:28"" *)
+  wire _044_;
+  (* src = ""../lib/mux_32to1.v:28"" *)
+  wire _045_;
+  (* src = ""../lib/mux_32to1.v:28"" *)
+  wire _046_;
+  (* src = ""../lib/mux_32to1.v:28"" *)
+  wire _047_;
+  (* src = ""../lib/mux_32to1.v:29"" *)
+  wire _048_;
+  (* src = ""../lib/mux_32to1.v:29"" *)
+  wire _049_;
+  (* src = ""../lib/mux_32to1.v:29"" *)
+  wire _050_;
+  (* src = ""../lib/mux_32to1.v:29"" *)
+  wire _051_;
+  (* src = ""../lib/mux_32to1.v:30"" *)
+  wire _052_;
+  (* src = ""../lib/mux_32to1.v:30"" *)
+  wire _053_;
+  (* src = ""../lib/mux_32to1.v:30"" *)
+  wire _054_;
+  (* src = ""../lib/mux_32to1.v:30"" *)
+  wire _055_;
+  (* src = ""../lib/mux_32to1.v:31"" *)
+  wire _056_;
+  (* src = ""../lib/mux_32to1.v:31"" *)
+  wire _057_;
+  (* src = ""../lib/mux_32to1.v:31"" *)
+  wire _058_;
+  (* src = ""../lib/mux_32to1.v:31"" *)
+  wire _059_;
+  (* src = ""../lib/mux_32to1.v:32"" *)
+  wire _060_;
+  (* src = ""../lib/mux_32to1.v:32"" *)
+  wire _061_;
+  (* src = ""../lib/mux_32to1.v:32"" *)
+  wire _062_;
+  (* src = ""../lib/mux_32to1.v:32"" *)
+  wire _063_;
+  (* src = ""../lib/mux_32to1.v:33"" *)
+  wire _064_;
+  (* src = ""../lib/mux_32to1.v:33"" *)
+  wire _065_;
+  (* src = ""../lib/mux_32to1.v:33"" *)
+  wire _066_;
+  (* src = ""../lib/mux_32to1.v:33"" *)
+  wire _067_;
+  (* src = ""../lib/mux_32to1.v:33"" *)
+  wire int16;
+  (* src = ""../lib/mux_32to1.v:34"" *)
+  wire _068_;
+  (* src = ""../lib/mux_32to1.v:34"" *)
+  wire _069_;
+  (* src = ""../lib/mux_32to1.v:34"" *)
+  wire _070_;
+  (* src = ""../lib/mux_32to1.v:34"" *)
+  wire _071_;
+  (* src = ""../lib/mux_32to1.v:34"" *)
+  wire int17;
+  (* src = ""../lib/mux_32to1.v:35"" *)
+  wire _072_;
+  (* src = ""../lib/mux_32to1.v:35"" *)
+  wire _073_;
+  (* src = ""../lib/mux_32to1.v:35"" *)
+  wire _074_;
+  (* src = ""../lib/mux_32to1.v:35"" *)
+  wire _075_;
+  (* src = ""../lib/mux_32to1.v:35"" *)
+  wire int18;
+  (* src = ""../lib/mux_32to1.v:36"" *)
+  wire _076_;
+  (* src = ""../lib/mux_32to1.v:36"" *)
+  wire _077_;
+  (* src = ""../lib/mux_32to1.v:36"" *)
+  wire _078_;
+  (* src = ""../lib/mux_32to1.v:36"" *)
+  wire _079_;
+  (* src = ""../lib/mux_32to1.v:36"" *)
+  wire int19;
+  (* src = ""../lib/mux_32to1.v:37"" *)
+  wire _080_;
+  (* src = ""../lib/mux_32to1.v:37"" *)
+  wire _081_;
+  (* src = ""../lib/mux_32to1.v:37"" *)
+  wire _082_;
+  (* src = ""../lib/mux_32to1.v:37"" *)
+  wire _083_;
+  (* src = ""../lib/mux_32to1.v:37"" *)
+  wire int20;
+  (* src = ""../lib/mux_32to1.v:38"" *)
+  wire _084_;
+  (* src = ""../lib/mux_32to1.v:38"" *)
+  wire _085_;
+  (* src = ""../lib/mux_32to1.v:38"" *)
+  wire _086_;
+  (* src = ""../lib/mux_32to1.v:38"" *)
+  wire _087_;
+  (* src = ""../lib/mux_32to1.v:38"" *)
+  wire int21;
+  (* src = ""../lib/mux_32to1.v:39"" *)
+  wire _088_;
+  (* src = ""../lib/mux_32to1.v:39"" *)
+  wire _089_;
+  (* src = ""../lib/mux_32to1.v:39"" *)
+  wire _090_;
+  (* src = ""../lib/mux_32to1.v:39"" *)
+  wire _091_;
+  (* src = ""../lib/mux_32to1.v:39"" *)
+  wire int22;
+  (* src = ""../lib/mux_32to1.v:40"" *)
+  wire _092_;
+  (* src = ""../lib/mux_32to1.v:40"" *)
+  wire _093_;
+  (* src = ""../lib/mux_32to1.v:40"" *)
+  wire _094_;
+  (* src = ""../lib/mux_32to1.v:40"" *)
+  wire _095_;
+  (* src = ""../lib/mux_32to1.v:40"" *)
+  wire int23;
+  (* src = ""../lib/mux_32to1.v:41"" *)
+  wire _096_;
+  (* src = ""../lib/mux_32to1.v:41"" *)
+  wire _097_;
+  (* src = ""../lib/mux_32to1.v:41"" *)
+  wire _098_;
+  (* src = ""../lib/mux_32to1.v:41"" *)
+  wire _099_;
+  (* src = ""../lib/mux_32to1.v:41"" *)
+  wire int24;
+  (* src = ""../lib/mux_32to1.v:42"" *)
+  wire _100_;
+  (* src = ""../lib/mux_32to1.v:42"" *)
+  wire _101_;
+  (* src = ""../lib/mux_32to1.v:42"" *)
+  wire _102_;
+  (* src = ""../lib/mux_32to1.v:42"" *)
+  wire _103_;
+  (* src = ""../lib/mux_32to1.v:42"" *)
+  wire int25;
+  (* src = ""../lib/mux_32to1.v:43"" *)
+  wire _104_;
+  (* src = ""../lib/mux_32to1.v:43"" *)
+  wire _105_;
+  (* src = ""../lib/mux_32to1.v:43"" *)
+  wire _106_;
+  (* src = ""../lib/mux_32to1.v:43"" *)
+  wire _107_;
+  (* src = ""../lib/mux_32to1.v:43"" *)
+  wire int26;
+  (* src = ""../lib/mux_32to1.v:44"" *)
+  wire _108_;
+  (* src = ""../lib/mux_32to1.v:44"" *)
+  wire _109_;
+  (* src = ""../lib/mux_32to1.v:44"" *)
+  wire _110_;
+  (* src = ""../lib/mux_32to1.v:44"" *)
+  wire _111_;
+  (* src = ""../lib/mux_32to1.v:44"" *)
+  wire int27;
+  (* src = ""../lib/mux_32to1.v:45"" *)
+  wire _112_;
+  (* src = ""../lib/mux_32to1.v:45"" *)
+  wire _113_;
+  (* src = ""../lib/mux_32to1.v:45"" *)
+  wire _114_;
+  (* src = ""../lib/mux_32to1.v:45"" *)
+  wire _115_;
+  (* src = ""../lib/mux_32to1.v:45"" *)
+  wire int28;
+  (* src = ""../lib/mux_32to1.v:46"" *)
+  wire _116_;
+  (* src = ""../lib/mux_32to1.v:46"" *)
+  wire _117_;
+  (* src = ""../lib/mux_32to1.v:46"" *)
+  wire _118_;
+  (* src = ""../lib/mux_32to1.v:46"" *)
+  wire _119_;
+  (* src = ""../lib/mux_32to1.v:46"" *)
+  wire int29;
+  (* src = ""../lib/mux_32to1.v:47"" *)
+  wire _120_;
+  (* src = ""../lib/mux_32to1.v:47"" *)
+  wire _121_;
+  (* src = ""../lib/mux_32to1.v:47"" *)
+  wire _122_;
+  (* src = ""../lib/mux_32to1.v:47"" *)
+  wire _123_;
+  (* src = ""../lib/mux_32to1.v:47"" *)
+  wire int30;
+  (* src = ""../lib/mux_32to1.v:48"" *)
+  wire _124_;
+  (* src = ""../lib/mux_32to1.v:48"" *)
+  wire _125_;
+  (* src = ""../lib/mux_32to1.v:48"" *)
+  wire _126_;
+  (* src = ""../lib/mux_32to1.v:48"" *)
+  wire _127_;
+  (* src = ""../lib/mux_32to1.v:48"" *)
+  wire int31;
+  (* src = ""../lib/mux_32to1.v:51"" *)
+  wire _128_;
+  (* src = ""../lib/mux_32to1.v:51"" *)
+  wire _129_;
+  (* src = ""../lib/mux_32to1.v:51"" *)
+  wire _130_;
+  (* src = ""../lib/mux_32to1.v:51"" *)
+  wire _131_;
+  (* src = ""../lib/mux_32to1.v:51"" *)
+  wire _132_;
+  (* src = ""../lib/mux_32to1.v:51"" *)
+  wire _133_;
+  (* src = ""../lib/mux_32to1.v:51"" *)
+  wire _134_;
+  (* src = ""../lib/mux_32to1.v:51"" *)
+  wire _135_;
+  (* src = ""../lib/mux_32to1.v:51"" *)
+  wire _136_;
+  (* src = ""../lib/mux_32to1.v:51"" *)
+  wire _137_;
+  (* src = ""../lib/mux_32to1.v:51"" *)
+  wire _138_;
+  (* src = ""../lib/mux_32to1.v:51"" *)
+  wire _139_;
+  (* src = ""../lib/mux_32to1.v:51"" *)
+  wire _140_;
+  (* src = ""../lib/mux_32to1.v:51"" *)
+  wire _141_;
+  (* src = ""../lib/mux_32to1.v:51"" *)
+  wire _142_;
+  (* src = ""../lib/mux_32to1.v:51"" *)
+  wire _143_;
+  (* src = ""../lib/mux_32to1.v:51"" *)
+  wire _144_;
+  (* src = ""../lib/mux_32to1.v:51"" *)
+  wire _145_;
+  (* src = ""../lib/mux_32to1.v:51"" *)
+  wire _146_;
+  (* src = ""../lib/mux_32to1.v:51"" *)
+  wire _147_;
+  (* src = ""../lib/mux_32to1.v:51"" *)
+  wire _148_;
+  (* src = ""../lib/mux_32to1.v:51"" *)
+  wire _149_;
+  (* src = ""../lib/mux_32to1.v:51"" *)
+  wire _150_;
+  (* src = ""../lib/mux_32to1.v:51"" *)
+  wire _151_;
+  (* src = ""../lib/mux_32to1.v:51"" *)
+  wire _152_;
+  (* src = ""../lib/mux_32to1.v:51"" *)
+  wire _153_;
+  (* src = ""../lib/mux_32to1.v:51"" *)
+  wire _154_;
+  (* src = ""../lib/mux_32to1.v:51"" *)
+  wire _155_;
+  (* src = ""../lib/mux_32to1.v:51"" *)
+  wire _156_;
+  (* src = ""../lib/mux_32to1.v:51"" *)
+  wire _157_;
+  assign z = _157_ | int15;
+  assign _157_ = _156_ | int14;
+  assign _156_ = _155_ | int13;
+  assign _155_ = _154_ | int12;
+  assign _154_ = _153_ | int11;
+  assign _153_ = _152_ | int10;
+  assign _152_ = _151_ | int9;
+  assign _151_ = _150_ | int8;
+  assign _150_ = _149_ | int7;
+  assign _149_ = _148_ | int6;
+  assign _148_ = _147_ | int5;
+  assign _147_ = _146_ | int4;
+  assign _146_ = _145_ | int3;
+  assign _145_ = _144_ | int2;
+  assign _144_ = _143_ | int1;
+  assign _143_ = _142_ | int0;
+  assign _142_ = _141_ | int16;
+  assign _141_ = _140_ | int17;
+  assign _140_ = _139_ | int18;
+  assign _139_ = _138_ | int19;
+  assign _138_ = _137_ | int20;
+  assign _137_ = _136_ | int21;
+  assign _136_ = _135_ | int22;
+  assign _135_ = _134_ | int23;
+  assign _134_ = _133_ | int24;
+  assign _133_ = _132_ | int25;
+  assign _132_ = _131_ | int26;
+  assign _131_ = _130_ | int27;
+  assign _130_ = _129_ | int28;
+  assign _129_ = _128_ | int29;
+  assign _128_ = int31 | int30;
+  assign int31 = _127_ & s[0];
+  assign _127_ = _126_ & s[1];
+  assign _126_ = _125_ & s[2];
+  assign _125_ = _124_ & s[3];
+  assign _124_ = i31 & s[4];
+  assign int30 = _123_ & s0_bar;
+  assign _123_ = _122_ & s[1];
+  assign _122_ = _121_ & s[2];
+  assign _121_ = _120_ & s[3];
+  assign _120_ = i30 & s[4];
+  assign int29 = _119_ & s[0];
+  assign _119_ = _118_ & s1_bar;
+  assign _118_ = _117_ & s[2];
+  assign _117_ = _116_ & s[3];
+  assign _116_ = i29 & s[4];
+  assign int28 = _115_ & s0_bar;
+  assign _115_ = _114_ & s1_bar;
+  assign _114_ = _113_ & s[2];
+  assign _113_ = _112_ & s[3];
+  assign _112_ = i28 & s[4];
+  assign int27 = _111_ & s[0];
+  assign _111_ = _110_ & s[1];
+  assign _110_ = _109_ & s2_bar;
+  assign _109_ = _108_ & s[3];
+  assign _108_ = i27 & s[4];
+  assign int26 = _107_ & s0_bar;
+  assign _107_ = _106_ & s[1];
+  assign _106_ = _105_ & s2_bar;
+  assign _105_ = _104_ & s[3];
+  assign _104_ = i26 & s[4];
+  assign int25 = _103_ & s[0];
+  assign _103_ = _102_ & s1_bar;
+  assign _102_ = _101_ & s2_bar;
+  assign _101_ = _100_ & s[3];
+  assign _100_ = i25 & s[4];
+  assign int24 = _099_ & s0_bar;
+  assign _099_ = _098_ & s1_bar;
+  assign _098_ = _097_ & s2_bar;
+  assign _097_ = _096_ & s[3];
+  assign _096_ = i24 & s[4];
+  assign int23 = _095_ & s[0];
+  assign _095_ = _094_ & s[1];
+  assign _094_ = _093_ & s[2];
+  assign _093_ = _092_ & s3_bar;
+  assign _092_ = i23 & s[4];
+  assign int22 = _091_ & s0_bar;
+  assign _091_ = _090_ & s[1];
+  assign _090_ = _089_ & s[2];
+  assign _089_ = _088_ & s3_bar;
+  assign _088_ = i22 & s[4];
+  assign int21 = _087_ & s[0];
+  assign _087_ = _086_ & s1_bar;
+  assign _085_ = _084_ & s3_bar;
+  assign _084_ = i21 & s[4];
+  assign int20 = _083_ & s0_bar;
+  assign _083_ = _082_ & s1_bar;
+  assign _082_ = _081_ & s[2];
+  assign _081_ = _080_ & s3_bar;
+  assign _080_ = i20 & s[4];
+  assign int19 = _079_ & s[0];
+  assign _079_ = _078_ & s[1];
+  assign _078_ = _077_ & s2_bar;
+  assign _077_ = _076_ & s3_bar;
+  assign _076_ = i19 & s[4];
+  assign int18 = _075_ & s0_bar;
+  assign _075_ = _074_ & s[1];
+  assign _074_ = _073_ & s2_bar;
+  assign _073_ = _072_ & s3_bar;
+  assign _072_ = i18 & s[4];
+  assign int17 = _071_ & s[0];
+  assign _071_ = _070_ & s1_bar;
+  assign _070_ = _069_ & s2_bar;
+  assign _069_ = _068_ & s3_bar;
+  assign _068_ = i17 & s[4];
+  assign int16 = _067_ & s0_bar;
+  assign _067_ = _066_ & s1_bar;
+  assign _066_ = _065_ & s2_bar;
+  assign _065_ = _064_ & s3_bar;
+  assign _064_ = i16 & s[4];
+  assign int15 = _063_ & s[0];
+  assign _063_ = _062_ & s[1];
+  assign _062_ = _061_ & s[2];
+  assign _061_ = _060_ & s[3];
+  assign _060_ = i15 & s4_bar;
+  assign int14 = _059_ & s0_bar;
+  assign _059_ = _058_ & s[1];
+  assign _058_ = _057_ & s[2];
+  assign _057_ = _056_ & s[3];
+  assign _056_ = i14 & s4_bar;
+  assign int13 = _055_ & s[0];
+  assign _055_ = _054_ & s1_bar;
+  assign _054_ = _053_ & s[2];
+  assign _053_ = _052_ & s[3];
+  assign _052_ = i13 & s4_bar;
+  assign int12 = _051_ & s0_bar;
+  assign _051_ = _050_ & s1_bar;
+  assign _050_ = _049_ & s[2];
+  assign _086_ = _085_ & s[2];
+  assign _049_ = _048_ & s[3];
+  assign _048_ = i12 & s4_bar;
+  assign int11 = _047_ & s[0];
+  assign _047_ = _046_ & s[1];
+  assign _046_ = _045_ & s2_bar;
+  assign _044_ = i11 & s4_bar;
+  assign _045_ = _044_ & s[3];
+  assign int10 = _043_ & s0_bar;
+  assign _043_ = _042_ & s[1];
+  assign _042_ = _041_ & s2_bar;
+  assign _041_ = _040_ & s[3];
+  assign _040_ = i10 & s4_bar;
+  assign int9 = _039_ & s[0];
+  assign _039_ = _038_ & s1_bar;
+  assign _038_ = _037_ & s2_bar;
+  assign _037_ = _036_ & s[3];
+  assign _036_ = i9 & s4_bar;
+  assign int8 = _035_ & s0_bar;
+  assign _035_ = _034_ & s1_bar;
+  assign _034_ = _033_ & s2_bar;
+  assign _033_ = _032_ & s[3];
+  assign _032_ = i8 & s4_bar;
+  assign int7 = _031_ & s[0];
+  assign _031_ = _030_ & s[1];
+  assign _030_ = _029_ & s[2];
+  assign _029_ = _028_ & s3_bar;
+  assign _028_ = i7 & s4_bar;
+  assign int6 = _027_ & s0_bar;
+  assign _027_ = _026_ & s[1];
+  assign _026_ = _025_ & s[2];
+  assign _025_ = _024_ & s3_bar;
+  assign _024_ = i6 & s4_bar;
+  assign int5 = _023_ & s[0];
+  assign _023_ = _022_ & s1_bar;
+  assign _022_ = _021_ & s[2];
+  assign _021_ = _020_ & s3_bar;
+  assign _020_ = i5 & s4_bar;
+  assign int4 = _019_ & s0_bar;
+  assign _019_ = _018_ & s1_bar;
+  assign _018_ = _017_ & s[2];
+  assign _017_ = _016_ & s3_bar;
+  assign _016_ = i4 & s4_bar;
+  assign int3 = _015_ & s[0];
+  assign _015_ = _014_ & s[1];
+  assign _014_ = _013_ & s2_bar;
+  assign _013_ = _012_ & s3_bar;
+  assign _012_ = i3 & s4_bar;
+  assign int2 = _011_ & s0_bar;
+  assign _011_ = _010_ & s[1];
+  assign _010_ = _009_ & s2_bar;
+  assign _009_ = _008_ & s3_bar;
+  assign _008_ = i2 & s4_bar;
+  assign int1 = _007_ & s[0];
+  assign _007_ = _006_ & s1_bar;
+  assign _006_ = _005_ & s2_bar;
+  assign _005_ = _004_ & s3_bar;
+  assign _004_ = i1 & s4_bar;
+  assign int0 = _003_ & s0_bar;
+  assign _003_ = _002_ & s1_bar;
+  assign _002_ = _001_ & s2_bar;
+  assign _001_ = _000_ & s3_bar;
+  assign _000_ = i0 & s4_bar;
+  assign s4_bar = ~s[4];
+  assign s3_bar = ~s[3];
+  assign s2_bar = ~s[2];
+  assign s1_bar = ~s[1];
+  assign s0_bar = ~s[0];
+endmodule
+
+(* src = ""../lib/mux32bits_32to1.v:3"" *)
+module mux32bits_32to1(s, i31, i30, i29, i28, i27, i26, i25, i24, i23, i22, i21, i20, i19, i18, i17, i16, i15, i14, i13, i12, i11, i10, i9, i8, i7, i6, i5, i4, i3, i2, i1, i0, z);
+  (* src = ""../lib/mux32bits_32to1.v:6"" *)
+  input [31:0] i1;
+  (* src = ""../lib/mux32bits_32to1.v:6"" *)
+  input [31:0] i0;
+  (* src = ""../lib/mux32bits_32to1.v:4"" *)
+  input [4:0] s;
+  (* src = ""../lib/mux32bits_32to1.v:7"" *)
+  output [31:0] z;
+  (* src = ""../lib/mux32bits_32to1.v:5"" *)
+  input [31:0] i31;
+  (* src = ""../lib/mux32bits_32to1.v:5"" *)
+  input [31:0] i30;
+  (* src = ""../lib/mux32bits_32to1.v:5"" *)
+  input [31:0] i29;
+  (* src = ""../lib/mux32bits_32to1.v:5"" *)
+  input [31:0] i28;
+  (* src = ""../lib/mux32bits_32to1.v:5"" *)
+  input [31:0] i27;
+  (* src = ""../lib/mux32bits_32to1.v:5"" *)
+  input [31:0] i26;
+  (* src = ""../lib/mux32bits_32to1.v:5"" *)
+  input [31:0] i25;
+  (* src = ""../lib/mux32bits_32to1.v:5"" *)
+  input [31:0] i24;
+  (* src = ""../lib/mux32bits_32to1.v:5"" *)
+  input [31:0] i23;
+  (* src = ""../lib/mux32bits_32to1.v:5"" *)
+  input [31:0] i22;
+  (* src = ""../lib/mux32bits_32to1.v:5"" *)
+  input [31:0] i21;
+  (* src = ""../lib/mux32bits_32to1.v:5"" *)
+  input [31:0] i20;
+  (* src = ""../lib/mux32bits_32to1.v:5"" *)
+  input [31:0] i19;
+  (* src = ""../lib/mux32bits_32to1.v:5"" *)
+  input [31:0] i18;
+  (* src = ""../lib/mux32bits_32to1.v:5"" *)
+  input [31:0] i17;
+  (* src = ""../lib/mux32bits_32to1.v:5"" *)
+  input [31:0] i16;
+  (* src = ""../lib/mux32bits_32to1.v:6"" *)
+  input [31:0] i15;
+  (* src = ""../lib/mux32bits_32to1.v:6"" *)
+  input [31:0] i14;
+  (* src = ""../lib/mux32bits_32to1.v:6"" *)
+  input [31:0] i13;
+  (* src = ""../lib/mux32bits_32to1.v:6"" *)
+  input [31:0] i12;
+  (* src = ""../lib/mux32bits_32to1.v:6"" *)
+  input [31:0] i11;
+  (* src = ""../lib/mux32bits_32to1.v:6"" *)
+  input [31:0] i10;
+  (* src = ""../lib/mux32bits_32to1.v:6"" *)
+  input [31:0] i9;
+  (* src = ""../lib/mux32bits_32to1.v:6"" *)
+  input [31:0] i8;
+  (* src = ""../lib/mux32bits_32to1.v:6"" *)
+  input [31:0] i7;
+  (* src = ""../lib/mux32bits_32to1.v:6"" *)
+  input [31:0] i6;
+  (* src = ""../lib/mux32bits_32to1.v:6"" *)
+  input [31:0] i5;
+  (* src = ""../lib/mux32bits_32to1.v:6"" *)
+  input [31:0] i4;
+  (* src = ""../lib/mux32bits_32to1.v:6"" *)
+  input [31:0] i3;
+  (* src = ""../lib/mux32bits_32to1.v:6"" *)
+  input [31:0] i2;
+  (* src = ""../lib/mux32bits_32to1.v:9"" *)
+  mux_32to1 mux0 (
+    .i1(i1[0]),
+    .i0(i0[0]),
+    .s(s),
+    .z(z[0]),
+    .i31(i31[0]),
+    .i30(i30[0]),
+    .i29(i29[0]),
+    .i28(i28[0]),
+    .i27(i27[0]),
+    .i26(i26[0]),
+    .i25(i25[0]),
+    .i24(i24[0]),
+    .i23(i23[0]),
+    .i22(i22[0]),
+    .i21(i21[0]),
+    .i20(i20[0]),
+    .i19(i19[0]),
+    .i18(i18[0]),
+    .i17(i17[0]),
+    .i16(i16[0]),
+    .i15(i15[0]),
+    .i14(i14[0]),
+    .i13(i13[0]),
+    .i12(i12[0]),
+    .i11(i11[0]),
+    .i10(i10[0]),
+    .i9(i9[0]),
+    .i8(i8[0]),
+    .i7(i7[0]),
+    .i6(i6[0]),
+    .i5(i5[0]),
+    .i4(i4[0]),
+    .i3(i3[0]),
+    .i2(i2[0])
+  );
+  (* src = ""../lib/mux32bits_32to1.v:11"" *)
+  mux_32to1 mux1 (
+    .i1(i1[1]),
+    .i0(i0[1]),
+    .s(s),
+    .z(z[1]),
+    .i31(i31[1]),
+    .i30(i30[1]),
+    .i29(i29[1]),
+    .i28(i28[1]),
+    .i27(i27[1]),
+    .i26(i26[1]),
+    .i25(i25[1]),
+    .i24(i24[1]),
+    .i23(i23[1]),
+    .i22(i22[1]),
+    .i21(i21[1]),
+    .i20(i20[1]),
+    .i19(i19[1]),
+    .i18(i18[1]),
+    .i17(i17[1]),
+    .i16(i16[1]),
+    .i15(i15[1]),
+    .i14(i14[1]),
+    .i13(i13[1]),
+    .i12(i12[1]),
+    .i11(i11[1]),
+    .i10(i10[1]),
+    .i9(i9[1]),
+    .i8(i8[1]),
+    .i7(i7[1]),
+    .i6(i6[1]),
+    .i5(i5[1]),
+    .i4(i4[1]),
+    .i3(i3[1]),
+    .i2(i2[1])
+  );
+  (* src = ""../lib/mux32bits_32to1.v:13"" *)
+  mux_32to1 mux2 (
+    .i1(i1[2]),
+    .i0(i0[2]),
+    .s(s),
+    .z(z[2]),
+    .i31(i31[2]),
+    .i30(i30[2]),
+    .i29(i29[2]),
+    .i28(i28[2]),
+    .i27(i27[2]),
+    .i26(i26[2]),
+    .i25(i25[2]),
+    .i24(i24[2]),
+    .i23(i23[2]),
+    .i22(i22[2]),
+    .i21(i21[2]),
+    .i20(i20[2]),
+    .i19(i19[2]),
+    .i18(i18[2]),
+    .i17(i17[2]),
+    .i16(i16[2]),
+    .i15(i15[2]),
+    .i14(i14[2]),
+    .i13(i13[2]),
+    .i12(i12[2]),
+    .i11(i11[2]),
+    .i10(i10[2]),
+    .i9(i9[2]),
+    .i8(i8[2]),
+    .i7(i7[2]),
+    .i6(i6[2]),
+    .i5(i5[2]),
+    .i4(i4[2]),
+    .i3(i3[2]),
+    .i2(i2[2])
+  );
+  (* src = ""../lib/mux32bits_32to1.v:15"" *)
+  mux_32to1 mux3 (
+    .i1(i1[3]),
+    .i0(i0[3]),
+    .s(s),
+    .z(z[3]),
+    .i31(i31[3]),
+    .i30(i30[3]),
+    .i29(i29[3]),
+    .i28(i28[3]),
+    .i27(i27[3]),
+    .i26(i26[3]),
+    .i25(i25[3]),
+    .i24(i24[3]),
+    .i23(i23[3]),
+    .i22(i22[3]),
+    .i21(i21[3]),
+    .i20(i20[3]),
+    .i19(i19[3]),
+    .i18(i18[3]),
+    .i17(i17[3]),
+    .i16(i16[3]),
+    .i15(i15[3]),
+    .i14(i14[3]),
+    .i13(i13[3]),
+    .i12(i12[3]),
+    .i11(i11[3]),
+    .i10(i10[3]),
+    .i9(i9[3]),
+    .i8(i8[3]),
+    .i7(i7[3]),
+    .i6(i6[3]),
+    .i5(i5[3]),
+    .i4(i4[3]),
+    .i3(i3[3]),
+    .i2(i2[3])
+  );
+  (* src = ""../lib/mux32bits_32to1.v:17"" *)
+  mux_32to1 mux4 (
+    .i1(i1[4]),
+    .i0(i0[4]),
+    .s(s),
+    .z(z[4]),
+    .i31(i31[4]),
+    .i30(i30[4]),
+    .i29(i29[4]),
+    .i28(i28[4]),
+    .i27(i27[4]),
+    .i26(i26[4]),
+    .i25(i25[4]),
+    .i24(i24[4]),
+    .i23(i23[4]),
+    .i22(i22[4]),
+    .i21(i21[4]),
+    .i20(i20[4]),
+    .i19(i19[4]),
+    .i18(i18[4]),
+    .i17(i17[4]),
+    .i16(i16[4]),
+    .i15(i15[4]),
+    .i14(i14[4]),
+    .i13(i13[4]),
+    .i12(i12[4]),
+    .i11(i11[4]),
+    .i10(i10[4]),
+    .i9(i9[4]),
+    .i8(i8[4]),
+    .i7(i7[4]),
+    .i6(i6[4]),
+    .i5(i5[4]),
+    .i4(i4[4]),
+    .i3(i3[4]),
+    .i2(i2[4])
+  );
+  (* src = ""../lib/mux32bits_32to1.v:19"" *)
+  mux_32to1 mux5 (
+    .i1(i1[5]),
+    .i0(i0[5]),
+    .s(s),
+    .z(z[5]),
+    .i31(i31[5]),
+    .i30(i30[5]),
+    .i29(i29[5]),
+    .i28(i28[5]),
+    .i27(i27[5]),
+    .i26(i26[5]),
+    .i25(i25[5]),
+    .i24(i24[5]),
+    .i23(i23[5]),
+    .i22(i22[5]),
+    .i21(i21[5]),
+    .i20(i20[5]),
+    .i19(i19[5]),
+    .i18(i18[5]),
+    .i17(i17[5]),
+    .i16(i16[5]),
+    .i15(i15[5]),
+    .i14(i14[5]),
+    .i13(i13[5]),
+    .i12(i12[5]),
+    .i11(i11[5]),
+    .i10(i10[5]),
+    .i9(i9[5]),
+    .i8(i8[5]),
+    .i7(i7[5]),
+    .i6(i6[5]),
+    .i5(i5[5]),
+    .i4(i4[5]),
+    .i3(i3[5]),
+    .i2(i2[5])
+  );
+  (* src = ""../lib/mux32bits_32to1.v:21"" *)
+  mux_32to1 mux6 (
+    .i1(i1[6]),
+    .i0(i0[6]),
+    .s(s),
+    .z(z[6]),
+    .i31(i31[6]),
+    .i30(i30[6]),
+    .i29(i29[6]),
+    .i28(i28[6]),
+    .i27(i27[6]),
+    .i26(i26[6]),
+    .i25(i25[6]),
+    .i24(i24[6]),
+    .i23(i23[6]),
+    .i22(i22[6]),
+    .i21(i21[6]),
+    .i20(i20[6]),
+    .i19(i19[6]),
+    .i18(i18[6]),
+    .i17(i17[6]),
+    .i16(i16[6]),
+    .i15(i15[6]),
+    .i14(i14[6]),
+    .i13(i13[6]),
+    .i12(i12[6]),
+    .i11(i11[6]),
+    .i10(i10[6]),
+    .i9(i9[6]),
+    .i8(i8[6]),
+    .i7(i7[6]),
+    .i6(i6[6]),
+    .i5(i5[6]),
+    .i4(i4[6]),
+    .i3(i3[6]),
+    .i2(i2[6])
+  );
+  (* src = ""../lib/mux32bits_32to1.v:23"" *)
+  mux_32to1 mux7 (
+    .i1(i1[7]),
+    .i0(i0[7]),
+    .s(s),
+    .z(z[7]),
+    .i31(i31[7]),
+    .i30(i30[7]),
+    .i29(i29[7]),
+    .i28(i28[7]),
+    .i27(i27[7]),
+    .i26(i26[7]),
+    .i25(i25[7]),
+    .i24(i24[7]),
+    .i23(i23[7]),
+    .i22(i22[7]),
+    .i21(i21[7]),
+    .i20(i20[7]),
+    .i19(i19[7]),
+    .i18(i18[7]),
+    .i17(i17[7]),
+    .i16(i16[7]),
+    .i15(i15[7]),
+    .i14(i14[7]),
+    .i13(i13[7]),
+    .i12(i12[7]),
+    .i11(i11[7]),
+    .i10(i10[7]),
+    .i9(i9[7]),
+    .i8(i8[7]),
+    .i7(i7[7]),
+    .i6(i6[7]),
+    .i5(i5[7]),
+    .i4(i4[7]),
+    .i3(i3[7]),
+    .i2(i2[7])
+  );
+  (* src = ""../lib/mux32bits_32to1.v:25"" *)
+  mux_32to1 mux8 (
+    .i1(i1[8]),
+    .i0(i0[8]),
+    .s(s),
+    .z(z[8]),
+    .i31(i31[8]),
+    .i30(i30[8]),
+    .i29(i29[8]),
+    .i28(i28[8]),
+    .i27(i27[8]),
+    .i26(i26[8]),
+    .i25(i25[8]),
+    .i24(i24[8]),
+    .i23(i23[8]),
+    .i22(i22[8]),
+    .i21(i21[8]),
+    .i20(i20[8]),
+    .i19(i19[8]),
+    .i18(i18[8]),
+    .i17(i17[8]),
+    .i16(i16[8]),
+    .i15(i15[8]),
+    .i14(i14[8]),
+    .i13(i13[8]),
+    .i12(i12[8]),
+    .i11(i11[8]),
+    .i10(i10[8]),
+    .i9(i9[8]),
+    .i8(i8[8]),
+    .i7(i7[8]),
+    .i6(i6[8]),
+    .i5(i5[8]),
+    .i4(i4[8]),
+    .i3(i3[8]),
+    .i2(i2[8])
+  );
+  (* src = ""../lib/mux32bits_32to1.v:27"" *)
+  mux_32to1 mux9 (
+    .i1(i1[9]),
+    .i0(i0[9]),
+    .s(s),
+    .z(z[9]),
+    .i31(i31[9]),
+    .i30(i30[9]),
+    .i29(i29[9]),
+    .i28(i28[9]),
+    .i27(i27[9]),
+    .i26(i26[9]),
+    .i25(i25[9]),
+    .i24(i24[9]),
+    .i23(i23[9]),
+    .i22(i22[9]),
+    .i21(i21[9]),
+    .i20(i20[9]),
+    .i19(i19[9]),
+    .i18(i18[9]),
+    .i17(i17[9]),
+    .i16(i16[9]),
+    .i15(i15[9]),
+    .i14(i14[9]),
+    .i13(i13[9]),
+    .i12(i12[9]),
+    .i11(i11[9]),
+    .i10(i10[9]),
+    .i9(i9[9]),
+    .i8(i8[9]),
+    .i7(i7[9]),
+    .i6(i6[9]),
+    .i5(i5[9]),
+    .i4(i4[9]),
+    .i3(i3[9]),
+    .i2(i2[9])
+  );
+  (* src = ""../lib/mux32bits_32to1.v:29"" *)
+  mux_32to1 mux10 (
+    .i1(i1[10]),
+    .i0(i0[10]),
+    .s(s),
+    .z(z[10]),
+    .i31(i31[10]),
+    .i30(i30[10]),
+    .i29(i29[10]),
+    .i28(i28[10]),
+    .i27(i27[10]),
+    .i26(i26[10]),
+    .i25(i25[10]),
+    .i24(i24[10]),
+    .i23(i23[10]),
+    .i22(i22[10]),
+    .i21(i21[10]),
+    .i20(i20[10]),
+    .i19(i19[10]),
+    .i18(i18[10]),
+    .i17(i17[10]),
+    .i16(i16[10]),
+    .i15(i15[10]),
+    .i14(i14[10]),
+    .i13(i13[10]),
+    .i12(i12[10]),
+    .i11(i11[10]),
+    .i10(i10[10]),
+    .i9(i9[10]),
+    .i8(i8[10]),
+    .i7(i7[10]),
+    .i6(i6[10]),
+    .i5(i5[10]),
+    .i4(i4[10]),
+    .i3(i3[10]),
+    .i2(i2[10])
+  );
+  (* src = ""../lib/mux32bits_32to1.v:31"" *)
+  mux_32to1 mux11 (
+    .i1(i1[11]),
+    .i0(i0[11]),
+    .s(s),
+    .z(z[11]),
+    .i31(i31[11]),
+    .i30(i30[11]),
+    .i29(i29[11]),
+    .i28(i28[11]),
+    .i27(i27[11]),
+    .i26(i26[11]),
+    .i25(i25[11]),
+    .i24(i24[11]),
+    .i23(i23[11]),
+    .i22(i22[11]),
+    .i21(i21[11]),
+    .i20(i20[11]),
+    .i19(i19[11]),
+    .i18(i18[11]),
+    .i17(i17[11]),
+    .i16(i16[11]),
+    .i15(i15[11]),
+    .i14(i14[11]),
+    .i13(i13[11]),
+    .i12(i12[11]),
+    .i11(i11[11]),
+    .i10(i10[11]),
+    .i9(i9[11]),
+    .i8(i8[11]),
+    .i7(i7[11]),
+    .i6(i6[11]),
+    .i5(i5[11]),
+    .i4(i4[11]),
+    .i3(i3[11]),
+    .i2(i2[11])
+  );
+  (* src = ""../lib/mux32bits_32to1.v:33"" *)
+  mux_32to1 mux12 (
+    .i1(i1[12]),
+    .i0(i0[12]),
+    .s(s),
+    .z(z[12]),
+    .i31(i31[12]),
+    .i30(i30[12]),
+    .i29(i29[12]),
+    .i28(i28[12]),
+    .i27(i27[12]),
+    .i26(i26[12]),
+    .i25(i25[12]),
+    .i24(i24[12]),
+    .i23(i23[12]),
+    .i22(i22[12]),
+    .i21(i21[12]),
+    .i20(i20[12]),
+    .i19(i19[12]),
+    .i18(i18[12]),
+    .i17(i17[12]),
+    .i16(i16[12]),
+    .i15(i15[12]),
+    .i14(i14[12]),
+    .i13(i13[12]),
+    .i12(i12[12]),
+    .i11(i11[12]),
+    .i10(i10[12]),
+    .i9(i9[12]),
+    .i8(i8[12]),
+    .i7(i7[12]),
+    .i6(i6[12]),
+    .i5(i5[12]),
+    .i4(i4[12]),
+    .i3(i3[12]),
+    .i2(i2[12])
+  );
+  (* src = ""../lib/mux32bits_32to1.v:35"" *)
+  mux_32to1 mux13 (
+    .i1(i1[13]),
+    .i0(i0[13]),
+    .s(s),
+    .z(z[13]),
+    .i31(i31[13]),
+    .i30(i30[13]),
+    .i29(i29[13]),
+    .i28(i28[13]),
+    .i27(i27[13]),
+    .i26(i26[13]),
+    .i25(i25[13]),
+    .i24(i24[13]),
+    .i23(i23[13]),
+    .i22(i22[13]),
+    .i21(i21[13]),
+    .i20(i20[13]),
+    .i19(i19[13]),
+    .i18(i18[13]),
+    .i17(i17[13]),
+    .i16(i16[13]),
+    .i15(i15[13]),
+    .i14(i14[13]),
+    .i13(i13[13]),
+    .i12(i12[13]),
+    .i11(i11[13]),
+    .i10(i10[13]),
+    .i9(i9[13]),
+    .i8(i8[13]),
+    .i7(i7[13]),
+    .i6(i6[13]),
+    .i5(i5[13]),
+    .i4(i4[13]),
+    .i3(i3[13]),
+    .i2(i2[13])
+  );
+  (* src = ""../lib/mux32bits_32to1.v:37"" *)
+  mux_32to1 mux14 (
+    .i1(i1[14]),
+    .i0(i0[14]),
+    .s(s),
+    .z(z[14]),
+    .i31(i31[14]),
+    .i30(i30[14]),
+    .i29(i29[14]),
+    .i28(i28[14]),
+    .i27(i27[14]),
+    .i26(i26[14]),
+    .i25(i25[14]),
+    .i24(i24[14]),
+    .i23(i23[14]),
+    .i22(i22[14]),
+    .i21(i21[14]),
+    .i20(i20[14]),
+    .i19(i19[14]),
+    .i18(i18[14]),
+    .i17(i17[14]),
+    .i16(i16[14]),
+    .i15(i15[14]),
+    .i14(i14[14]),
+    .i13(i13[14]),
+    .i12(i12[14]),
+    .i11(i11[14]),
+    .i10(i10[14]),
+    .i9(i9[14]),
+    .i8(i8[14]),
+    .i7(i7[14]),
+    .i6(i6[14]),
+    .i5(i5[14]),
+    .i4(i4[14]),
+    .i3(i3[14]),
+    .i2(i2[14])
+  );
+  (* src = ""../lib/mux32bits_32to1.v:39"" *)
+  mux_32to1 mux15 (
+    .i1(i1[15]),
+    .i0(i0[15]),
+    .s(s),
+    .z(z[15]),
+    .i31(i31[15]),
+    .i30(i30[15]),
+    .i29(i29[15]),
+    .i28(i28[15]),
+    .i27(i27[15]),
+    .i26(i26[15]),
+    .i25(i25[15]),
+    .i24(i24[15]),
+    .i23(i23[15]),
+    .i22(i22[15]),
+    .i21(i21[15]),
+    .i20(i20[15]),
+    .i19(i19[15]),
+    .i18(i18[15]),
+    .i17(i17[15]),
+    .i16(i16[15]),
+    .i15(i15[15]),
+    .i14(i14[15]),
+    .i13(i13[15]),
+    .i12(i12[15]),
+    .i11(i11[15]),
+    .i10(i10[15]),
+    .i9(i9[15]),
+    .i8(i8[15]),
+    .i7(i7[15]),
+    .i6(i6[15]),
+    .i5(i5[15]),
+    .i4(i4[15]),
+    .i3(i3[15]),
+    .i2(i2[15])
+  );
+  (* src = ""../lib/mux32bits_32to1.v:41"" *)
+  mux_32to1 mux16 (
+    .i1(i1[16]),
+    .i0(i0[16]),
+    .s(s),
+    .z(z[16]),
+    .i31(i31[16]),
+    .i30(i30[16]),
+    .i29(i29[16]),
+    .i28(i28[16]),
+    .i27(i27[16]),
+    .i26(i26[16]),
+    .i25(i25[16]),
+    .i24(i24[16]),
+    .i23(i23[16]),
+    .i22(i22[16]),
+    .i21(i21[16]),
+    .i20(i20[16]),
+    .i19(i19[16]),
+    .i18(i18[16]),
+    .i17(i17[16]),
+    .i16(i16[16]),
+    .i15(i15[16]),
+    .i14(i14[16]),
+    .i13(i13[16]),
+    .i12(i12[16]),
+    .i11(i11[16]),
+    .i10(i10[16]),
+    .i9(i9[16]),
+    .i8(i8[16]),
+    .i7(i7[16]),
+    .i6(i6[16]),
+    .i5(i5[16]),
+    .i4(i4[16]),
+    .i3(i3[16]),
+    .i2(i2[16])
+  );
+  (* src = ""../lib/mux32bits_32to1.v:43"" *)
+  mux_32to1 mux17 (
+    .i1(i1[17]),
+    .i0(i0[17]),
+    .s(s),
+    .z(z[17]),
+    .i31(i31[17]),
+    .i30(i30[17]),
+    .i29(i29[17]),
+    .i28(i28[17]),
+    .i27(i27[17]),
+    .i26(i26[17]),
+    .i25(i25[17]),
+    .i24(i24[17]),
+    .i23(i23[17]),
+    .i22(i22[17]),
+    .i21(i21[17]),
+    .i20(i20[17]),
+    .i19(i19[17]),
+    .i18(i18[17]),
+    .i17(i17[17]),
+    .i16(i16[17]),
+    .i15(i15[17]),
+    .i14(i14[17]),
+    .i13(i13[17]),
+    .i12(i12[17]),
+    .i11(i11[17]),
+    .i10(i10[17]),
+    .i9(i9[17]),
+    .i8(i8[17]),
+    .i7(i7[17]),
+    .i6(i6[17]),
+    .i5(i5[17]),
+    .i4(i4[17]),
+    .i3(i3[17]),
+    .i2(i2[17])
+  );
+  (* src = ""../lib/mux32bits_32to1.v:45"" *)
+  mux_32to1 mux18 (
+    .i1(i1[18]),
+    .i0(i0[18]),
+    .s(s),
+    .z(z[18]),
+    .i31(i31[18]),
+    .i30(i30[18]),
+    .i29(i29[18]),
+    .i28(i28[18]),
+    .i27(i27[18]),
+    .i26(i26[18]),
+    .i25(i25[18]),
+    .i24(i24[18]),
+    .i23(i23[18]),
+    .i22(i22[18]),
+    .i21(i21[18]),
+    .i20(i20[18]),
+    .i19(i19[18]),
+    .i18(i18[18]),
+    .i17(i17[18]),
+    .i16(i16[18]),
+    .i15(i15[18]),
+    .i14(i14[18]),
+    .i13(i13[18]),
+    .i12(i12[18]),
+    .i11(i11[18]),
+    .i10(i10[18]),
+    .i9(i9[18]),
+    .i8(i8[18]),
+    .i7(i7[18]),
+    .i6(i6[18]),
+    .i5(i5[18]),
+    .i4(i4[18]),
+    .i3(i3[18]),
+    .i2(i2[18])
+  );
+  (* src = ""../lib/mux32bits_32to1.v:47"" *)
+  mux_32to1 mux19 (
+    .i1(i1[19]),
+    .i0(i0[19]),
+    .s(s),
+    .z(z[19]),
+    .i31(i31[19]),
+    .i30(i30[19]),
+    .i29(i29[19]),
+    .i28(i28[19]),
+    .i27(i27[19]),
+    .i26(i26[19]),
+    .i25(i25[19]),
+    .i24(i24[19]),
+    .i23(i23[19]),
+    .i22(i22[19]),
+    .i21(i21[19]),
+    .i20(i20[19]),
+    .i19(i19[19]),
+    .i18(i18[19]),
+    .i17(i17[19]),
+    .i16(i16[19]),
+    .i15(i15[19]),
+    .i14(i14[19]),
+    .i13(i13[19]),
+    .i12(i12[19]),
+    .i11(i11[19]),
+    .i10(i10[19]),
+    .i9(i9[19]),
+    .i8(i8[19]),
+    .i7(i7[19]),
+    .i6(i6[19]),
+    .i5(i5[19]),
+    .i4(i4[19]),
+    .i3(i3[19]),
+    .i2(i2[19])
+  );
+  (* src = ""../lib/mux32bits_32to1.v:49"" *)
+  mux_32to1 mux20 (
+    .i1(i1[20]),
+    .i0(i0[20]),
+    .s(s),
+    .z(z[20]),
+    .i31(i31[20]),
+    .i30(i30[20]),
+    .i29(i29[20]),
+    .i28(i28[20]),
+    .i27(i27[20]),
+    .i26(i26[20]),
+    .i25(i25[20]),
+    .i24(i24[20]),
+    .i23(i23[20]),
+    .i22(i22[20]),
+    .i21(i21[20]),
+    .i20(i20[20]),
+    .i19(i19[20]),
+    .i18(i18[20]),
+    .i17(i17[20]),
+    .i16(i16[20]),
+    .i15(i15[20]),
+    .i14(i14[20]),
+    .i13(i13[20]),
+    .i12(i12[20]),
+    .i11(i11[20]),
+    .i10(i10[20]),
+    .i9(i9[20]),
+    .i8(i8[20]),
+    .i7(i7[20]),
+    .i6(i6[20]),
+    .i5(i5[20]),
+    .i4(i4[20]),
+    .i3(i3[20]),
+    .i2(i2[20])
+  );
+  (* src = ""../lib/mux32bits_32to1.v:51"" *)
+  mux_32to1 mux21 (
+    .i1(i1[21]),
+    .i0(i0[21]),
+    .s(s),
+    .z(z[21]),
+    .i31(i31[21]),
+    .i30(i30[21]),
+    .i29(i29[21]),
+    .i28(i28[21]),
+    .i27(i27[21]),
+    .i26(i26[21]),
+    .i25(i25[21]),
+    .i24(i24[21]),
+    .i23(i23[21]),
+    .i22(i22[21]),
+    .i21(i21[21]),
+    .i20(i20[21]),
+    .i19(i19[21]),
+    .i18(i18[21]),
+    .i17(i17[21]),
+    .i16(i16[21]),
+    .i15(i15[21]),
+    .i14(i14[21]),
+    .i13(i13[21]),
+    .i12(i12[21]),
+    .i11(i11[21]),
+    .i10(i10[21]),
+    .i9(i9[21]),
+    .i8(i8[21]),
+    .i7(i7[21]),
+    .i6(i6[21]),
+    .i5(i5[21]),
+    .i4(i4[21]),
+    .i3(i3[21]),
+    .i2(i2[21])
+  );
+  (* src = ""../lib/mux32bits_32to1.v:53"" *)
+  mux_32to1 mux22 (
+    .i1(i1[22]),
+    .i0(i0[22]),
+    .s(s),
+    .z(z[22]),
+    .i31(i31[22]),
+    .i30(i30[22]),
+    .i29(i29[22]),
+    .i28(i28[22]),
+    .i27(i27[22]),
+    .i26(i26[22]),
+    .i25(i25[22]),
+    .i24(i24[22]),
+    .i23(i23[22]),
+    .i22(i22[22]),
+    .i21(i21[22]),
+    .i20(i20[22]),
+    .i19(i19[22]),
+    .i18(i18[22]),
+    .i17(i17[22]),
+    .i16(i16[22]),
+    .i15(i15[22]),
+    .i14(i14[22]),
+    .i13(i13[22]),
+    .i12(i12[22]),
+    .i11(i11[22]),
+    .i10(i10[22]),
+    .i9(i9[22]),
+    .i8(i8[22]),
+    .i7(i7[22]),
+    .i6(i6[22]),
+    .i5(i5[22]),
+    .i4(i4[22]),
+    .i3(i3[22]),
+    .i2(i2[22])
+  );
+  (* src = ""../lib/mux32bits_32to1.v:56"" *)
+  mux_32to1 mux23 (
+    .i1(i1[23]),
+    .i0(i0[23]),
+    .s(s),
+    .z(z[23]),
+    .i31(i31[23]),
+    .i30(i30[23]),
+    .i29(i29[23]),
+    .i28(i28[23]),
+    .i27(i27[23]),
+    .i26(i26[23]),
+    .i25(i25[23]),
+    .i24(i24[23]),
+    .i23(i23[23]),
+    .i22(i22[23]),
+    .i21(i21[23]),
+    .i20(i20[23]),
+    .i19(i19[23]),
+    .i18(i18[23]),
+    .i17(i17[23]),
+    .i16(i16[23]),
+    .i15(i15[23]),
+    .i14(i14[23]),
+    .i13(i13[23]),
+    .i12(i12[23]),
+    .i11(i11[23]),
+    .i10(i10[23]),
+    .i9(i9[23]),
+    .i8(i8[23]),
+    .i7(i7[23]),
+    .i6(i6[23]),
+    .i5(i5[23]),
+    .i4(i4[23]),
+    .i3(i3[23]),
+    .i2(i2[23])
+  );
+  (* src = ""../lib/mux32bits_32to1.v:58"" *)
+  mux_32to1 mux24 (
+    .i1(i1[24]),
+    .i0(i0[24]),
+    .s(s),
+    .z(z[24]),
+    .i31(i31[24]),
+    .i30(i30[24]),
+    .i29(i29[24]),
+    .i28(i28[24]),
+    .i27(i27[24]),
+    .i26(i26[24]),
+    .i25(i25[24]),
+    .i24(i24[24]),
+    .i23(i23[24]),
+    .i22(i22[24]),
+    .i21(i21[24]),
+    .i20(i20[24]),
+    .i19(i19[24]),
+    .i18(i18[24]),
+    .i17(i17[24]),
+    .i16(i16[24]),
+    .i15(i15[24]),
+    .i14(i14[24]),
+    .i13(i13[24]),
+    .i12(i12[24]),
+    .i11(i11[24]),
+    .i10(i10[24]),
+    .i9(i9[24]),
+    .i8(i8[24]),
+    .i7(i7[24]),
+    .i6(i6[24]),
+    .i5(i5[24]),
+    .i4(i4[24]),
+    .i3(i3[24]),
+    .i2(i2[24])
+  );
+  (* src = ""../lib/mux32bits_32to1.v:60"" *)
+  mux_32to1 mux25 (
+    .i1(i1[25]),
+    .i0(i0[25]),
+    .s(s),
+    .z(z[25]),
+    .i31(i31[25]),
+    .i30(i30[25]),
+    .i29(i29[25]),
+    .i28(i28[25]),
+    .i27(i27[25]),
+    .i26(i26[25]),
+    .i25(i25[25]),
+    .i24(i24[25]),
+    .i23(i23[25]),
+    .i22(i22[25]),
+    .i21(i21[25]),
+    .i20(i20[25]),
+    .i19(i19[25]),
+    .i18(i18[25]),
+    .i17(i17[25]),
+    .i16(i16[25]),
+    .i15(i15[25]),
+    .i14(i14[25]),
+    .i13(i13[25]),
+    .i12(i12[25]),
+    .i11(i11[25]),
+    .i10(i10[25]),
+    .i9(i9[25]),
+    .i8(i8[25]),
+    .i7(i7[25]),
+    .i6(i6[25]),
+    .i5(i5[25]),
+    .i4(i4[25]),
+    .i3(i3[25]),
+    .i2(i2[25])
+  );
+  (* src = ""../lib/mux32bits_32to1.v:62"" *)
+  mux_32to1 mux26 (
+    .i1(i1[26]),
+    .i0(i0[26]),
+    .s(s),
+    .z(z[26]),
+    .i31(i31[26]),
+    .i30(i30[26]),
+    .i29(i29[26]),
+    .i28(i28[26]),
+    .i27(i27[26]),
+    .i26(i26[26]),
+    .i25(i25[26]),
+    .i24(i24[26]),
+    .i23(i23[26]),
+    .i22(i22[26]),
+    .i21(i21[26]),
+    .i20(i20[26]),
+    .i19(i19[26]),
+    .i18(i18[26]),
+    .i17(i17[26]),
+    .i16(i16[26]),
+    .i15(i15[26]),
+    .i14(i14[26]),
+    .i13(i13[26]),
+    .i12(i12[26]),
+    .i11(i11[26]),
+    .i10(i10[26]),
+    .i9(i9[26]),
+    .i8(i8[26]),
+    .i7(i7[26]),
+    .i6(i6[26]),
+    .i5(i5[26]),
+    .i4(i4[26]),
+    .i3(i3[26]),
+    .i2(i2[26])
+  );
+  (* src = ""../lib/mux32bits_32to1.v:64"" *)
+  mux_32to1 mux27 (
+    .i1(i1[27]),
+    .i0(i0[27]),
+    .s(s),
+    .z(z[27]),
+    .i31(i31[27]),
+    .i30(i30[27]),
+    .i29(i29[27]),
+    .i28(i28[27]),
+    .i27(i27[27]),
+    .i26(i26[27]),
+    .i25(i25[27]),
+    .i24(i24[27]),
+    .i23(i23[27]),
+    .i22(i22[27]),
+    .i21(i21[27]),
+    .i20(i20[27]),
+    .i19(i19[27]),
+    .i18(i18[27]),
+    .i17(i17[27]),
+    .i16(i16[27]),
+    .i15(i15[27]),
+    .i14(i14[27]),
+    .i13(i13[27]),
+    .i12(i12[27]),
+    .i11(i11[27]),
+    .i10(i10[27]),
+    .i9(i9[27]),
+    .i8(i8[27]),
+    .i7(i7[27]),
+    .i6(i6[27]),
+    .i5(i5[27]),
+    .i4(i4[27]),
+    .i3(i3[27]),
+    .i2(i2[27])
+  );
+  (* src = ""../lib/mux32bits_32to1.v:66"" *)
+  mux_32to1 mux28 (
+    .i1(i1[28]),
+    .i0(i0[28]),
+    .s(s),
+    .z(z[28]),
+    .i31(i31[28]),
+    .i30(i30[28]),
+    .i29(i29[28]),
+    .i28(i28[28]),
+    .i27(i27[28]),
+    .i26(i26[28]),
+    .i25(i25[28]),
+    .i24(i24[28]),
+    .i23(i23[28]),
+    .i22(i22[28]),
+    .i21(i21[28]),
+    .i20(i20[28]),
+    .i19(i19[28]),
+    .i18(i18[28]),
+    .i17(i17[28]),
+    .i16(i16[28]),
+    .i15(i15[28]),
+    .i14(i14[28]),
+    .i13(i13[28]),
+    .i12(i12[28]),
+    .i11(i11[28]),
+    .i10(i10[28]),
+    .i9(i9[28]),
+    .i8(i8[28]),
+    .i7(i7[28]),
+    .i6(i6[28]),
+    .i5(i5[28]),
+    .i4(i4[28]),
+    .i3(i3[28]),
+    .i2(i2[28])
+  );
+  (* src = ""../lib/mux32bits_32to1.v:68"" *)
+  mux_32to1 mux29 (
+    .i1(i1[29]),
+    .i0(i0[29]),
+    .s(s),
+    .z(z[29]),
+    .i31(i31[29]),
+    .i30(i30[29]),
+    .i29(i29[29]),
+    .i28(i28[29]),
+    .i27(i27[29]),
+    .i26(i26[29]),
+    .i25(i25[29]),
+    .i24(i24[29]),
+    .i23(i23[29]),
+    .i22(i22[29]),
+    .i21(i21[29]),
+    .i20(i20[29]),
+    .i19(i19[29]),
+    .i18(i18[29]),
+    .i17(i17[29]),
+    .i16(i16[29]),
+    .i15(i15[29]),
+    .i14(i14[29]),
+    .i13(i13[29]),
+    .i12(i12[29]),
+    .i11(i11[29]),
+    .i10(i10[29]),
+    .i9(i9[29]),
+    .i8(i8[29]),
+    .i7(i7[29]),
+    .i6(i6[29]),
+    .i5(i5[29]),
+    .i4(i4[29]),
+    .i3(i3[29]),
+    .i2(i2[29])
+  );
+  (* src = ""../lib/mux32bits_32to1.v:70"" *)
+  mux_32to1 mux30 (
+    .i1(i1[30]),
+    .i0(i0[30]),
+    .s(s),
+    .z(z[30]),
+    .i31(i31[30]),
+    .i30(i30[30]),
+    .i29(i29[30]),
+    .i28(i28[30]),
+    .i27(i27[30]),
+    .i26(i26[30]),
+    .i25(i25[30]),
+    .i24(i24[30]),
+    .i23(i23[30]),
+    .i22(i22[30]),
+    .i21(i21[30]),
+    .i20(i20[30]),
+    .i19(i19[30]),
+    .i18(i18[30]),
+    .i17(i17[30]),
+    .i16(i16[30]),
+    .i15(i15[30]),
+    .i14(i14[30]),
+    .i13(i13[30]),
+    .i12(i12[30]),
+    .i11(i11[30]),
+    .i10(i10[30]),
+    .i9(i9[30]),
+    .i8(i8[30]),
+    .i7(i7[30]),
+    .i6(i6[30]),
+    .i5(i5[30]),
+    .i4(i4[30]),
+    .i3(i3[30]),
+    .i2(i2[30])
+  );
+  (* src = ""../lib/mux32bits_32to1.v:72"" *)
+  mux_32to1 mux31 (
+    .i1(i1[31]),
+    .i0(i0[31]),
+    .s(s),
+    .z(z[31]),
+    .i31(i31[31]),
+    .i30(i30[31]),
+    .i29(i29[31]),
+    .i28(i28[31]),
+    .i27(i27[31]),
+    .i26(i26[31]),
+    .i25(i25[31]),
+    .i24(i24[31]),
+    .i23(i23[31]),
+    .i22(i22[31]),
+    .i21(i21[31]),
+    .i20(i20[31]),
+    .i19(i19[31]),
+    .i18(i18[31]),
+    .i17(i17[31]),
+    .i16(i16[31]),
+    .i15(i15[31]),
+    .i14(i14[31]),
+    .i13(i13[31]),
+    .i12(i12[31]),
+    .i11(i11[31]),
+    .i10(i10[31]),
+    .i9(i9[31]),
+    .i8(i8[31]),
+    .i7(i7[31]),
+    .i6(i6[31]),
+    .i5(i5[31]),
+    .i4(i4[31]),
+    .i3(i3[31]),
+    .i2(i2[31])
+  );
+endmodule
+
+(* src = ""../lib/dec_5to32.v:1"" *)
+module dec_5to32(a, b);
+  (* src = ""../lib/dec_5to32.v:2"" *)
+  input [4:0] a;
+  (* src = ""../lib/dec_5to32.v:3"" *)
+  output [31:0] b;
+  (* src = ""../lib/dec_5to32.v:5"" *)
+  wire _00_;
+  (* src = ""../lib/dec_5to32.v:5"" *)
+  wire _01_;
+  (* src = ""../lib/dec_5to32.v:5"" *)
+  wire _02_;
+  (* src = ""../lib/dec_5to32.v:5"" *)
+  wire _03_;
+  (* src = ""../lib/dec_5to32.v:5"" *)
+  wire _04_;
+  (* src = ""../lib/dec_5to32.v:5"" *)
+  wire _05_;
+  (* src = ""../lib/dec_5to32.v:5"" *)
+  wire _06_;
+  (* src = ""../lib/dec_5to32.v:5"" *)
+  wire _07_;
+  (* src = ""../lib/dec_5to32.v:7"" *)
+  wire _08_;
+  (* src = ""../lib/dec_5to32.v:9"" *)
+  wire _09_;
+  (* src = ""../lib/dec_5to32.v:9"" *)
+  wire _10_;
+  (* src = ""../lib/dec_5to32.v:11"" *)
+  wire _11_;
+  (* src = ""../lib/dec_5to32.v:13"" *)
+  wire _12_;
+  (* src = ""../lib/dec_5to32.v:13"" *)
+  wire _13_;
+  (* src = ""../lib/dec_5to32.v:13"" *)
+  wire _14_;
+  (* src = ""../lib/dec_5to32.v:15"" *)
+  wire _15_;
+  (* src = ""../lib/dec_5to32.v:17"" *)
+  wire _16_;
+  (* src = ""../lib/dec_5to32.v:17"" *)
+  wire _17_;
+  (* src = ""../lib/dec_5to32.v:19"" *)
+  wire _18_;
+  (* src = ""../lib/dec_5to32.v:21"" *)
+  wire _19_;
+  (* src = ""../lib/dec_5to32.v:21"" *)
+  wire _20_;
+  (* src = ""../lib/dec_5to32.v:21"" *)
+  wire _21_;
+  (* src = ""../lib/dec_5to32.v:23"" *)
+  wire _22_;
+  (* src = ""../lib/dec_5to32.v:25"" *)
+  wire _23_;
+  (* src = ""../lib/dec_5to32.v:25"" *)
+  wire _24_;
+  (* src = ""../lib/dec_5to32.v:27"" *)
+  wire _25_;
+  (* src = ""../lib/dec_5to32.v:29"" *)
+  wire _26_;
+  (* src = ""../lib/dec_5to32.v:29"" *)
+  wire _27_;
+  (* src = ""../lib/dec_5to32.v:29"" *)
+  wire _28_;
+  (* src = ""../lib/dec_5to32.v:31"" *)
+  wire _29_;
+  (* src = ""../lib/dec_5to32.v:33"" *)
+  wire _30_;
+  (* src = ""../lib/dec_5to32.v:33"" *)
+  wire _31_;
+  (* src = ""../lib/dec_5to32.v:35"" *)
+  wire _32_;
+  assign b[5] = _10_ & a[0];
+  assign b[4] = _10_ & _07_;
+  assign _10_ = _09_ & _05_;
+  assign _09_ = _02_ & a[2];
+  assign b[3] = _08_ & a[0];
+  assign b[2] = _08_ & _07_;
+  assign _08_ = _04_ & a[1];
+  assign b[1] = _06_ & a[0];
+  assign b[0] = _06_ & _07_;
+  assign _07_ = ~a[0];
+  assign _06_ = _04_ & _05_;
+  assign _05_ = ~a[1];
+  assign _04_ = _02_ & _03_;
+  assign _03_ = ~a[2];
+  assign _02_ = _00_ & _01_;
+  assign _01_ = ~a[3];
+  assign _00_ = ~a[4];
+  assign b[31] = _32_ & a[0];
+  assign b[30] = _32_ & _07_;
+  assign _32_ = _30_ & a[1];
+  assign b[29] = _31_ & a[0];
+  assign b[28] = _31_ & _07_;
+  assign _31_ = _30_ & _05_;
+  assign _30_ = _26_ & a[2];
+  assign b[27] = _29_ & a[0];
+  assign b[26] = _29_ & _07_;
+  assign _29_ = _27_ & a[1];
+  assign b[25] = _28_ & a[0];
+  assign b[24] = _28_ & _07_;
+  assign _28_ = _27_ & _05_;
+  assign _27_ = _26_ & _03_;
+  assign _26_ = a[4] & a[3];
+  assign b[23] = _25_ & a[0];
+  assign b[22] = _25_ & _07_;
+  assign _25_ = _23_ & a[1];
+  assign b[21] = _24_ & a[0];
+  assign b[20] = _24_ & _07_;
+  assign _24_ = _23_ & _05_;
+  assign _23_ = _19_ & a[2];
+  assign b[19] = _22_ & a[0];
+  assign b[18] = _22_ & _07_;
+  assign _22_ = _20_ & a[1];
+  assign b[17] = _21_ & a[0];
+  assign b[16] = _21_ & _07_;
+  assign _21_ = _20_ & _05_;
+  assign _20_ = _19_ & _03_;
+  assign _19_ = a[4] & _01_;
+  assign b[15] = _18_ & a[0];
+  assign b[14] = _18_ & _07_;
+  assign _18_ = _16_ & a[1];
+  assign b[13] = _17_ & a[0];
+  assign b[12] = _17_ & _07_;
+  assign _17_ = _16_ & _05_;
+  assign _16_ = _12_ & a[2];
+  assign b[11] = _15_ & a[0];
+  assign b[10] = _15_ & _07_;
+  assign _15_ = _13_ & a[1];
+  assign b[9] = _14_ & a[0];
+  assign b[8] = _14_ & _07_;
+  assign _14_ = _13_ & _05_;
+  assign _13_ = _12_ & _03_;
+  assign _12_ = _00_ & a[3];
+  assign b[7] = _11_ & a[0];
+  assign b[6] = _11_ & _07_;
+  assign _11_ = _09_ & a[1];
+endmodule
+
+(* src = ""../RF/reg_file.v:5"" *)
+module reg_file(readReg1, readReg2, writeReg, writeData, regWrite, clk, readData1, readData2);
+  (* src = ""../RF/reg_file.v:8"" *)
+  input clk;
+  (* src = ""../RF/reg_file.v:15"" *)
+  wire [31:0] we;
+  (* src = ""../RF/reg_file.v:6"" *)
+  input [4:0] readReg1;
+  (* src = ""../RF/reg_file.v:6"" *)
+  input [4:0] readReg2;
+  (* src = ""../RF/reg_file.v:6"" *)
+  input [4:0] writeReg;
+  (* src = ""../RF/reg_file.v:7"" *)
+  input [31:0] writeData;
+  (* src = ""../RF/reg_file.v:8"" *)
+  input regWrite;
+  (* src = ""../RF/reg_file.v:9"" *)
+  output [31:0] readData1;
+  (* src = ""../RF/reg_file.v:9"" *)
+  output [31:0] readData2;
+  (* src = ""../RF/reg_file.v:11"" *)
+  wire [31:0] regOutput0;
+  (* src = ""../RF/reg_file.v:11"" *)
+  wire [31:0] regOutput1;
+  (* src = ""../RF/reg_file.v:11"" *)
+  wire [31:0] regOutput2;
+  (* src = ""../RF/reg_file.v:11"" *)
+  wire [31:0] regOutput3;
+  (* src = ""../RF/reg_file.v:11"" *)
+  wire [31:0] regOutput4;
+  (* src = ""../RF/reg_file.v:11"" *)
+  wire [31:0] regOutput5;
+  (* src = ""../RF/reg_file.v:11"" *)
+  wire [31:0] regOutput6;
+  (* src = ""../RF/reg_file.v:11"" *)
+  wire [31:0] regOutput7;
+  (* src = ""../RF/reg_file.v:11"" *)
+  wire [31:0] regOutput8;
+  (* src = ""../RF/reg_file.v:11"" *)
+  wire [31:0] regOutput9;
+  (* src = ""../RF/reg_file.v:11"" *)
+  wire [31:0] regOutput10;
+  (* src = ""../RF/reg_file.v:11"" *)
+  wire [31:0] regOutput11;
+  (* src = ""../RF/reg_file.v:11"" *)
+  wire [31:0] regOutput12;
+  (* src = ""../RF/reg_file.v:11"" *)
+  wire [31:0] regOutput13;
+  (* src = ""../RF/reg_file.v:11"" *)
+  wire [31:0] regOutput14;
+  (* src = ""../RF/reg_file.v:11"" *)
+  wire [31:0] regOutput15;
+  (* src = ""../RF/reg_file.v:11"" *)
+  wire [31:0] regOutput16;
+  (* src = ""../RF/reg_file.v:11"" *)
+  wire [31:0] regOutput17;
+  (* src = ""../RF/reg_file.v:11"" *)
+  wire [31:0] regOutput18;
+  (* src = ""../RF/reg_file.v:11"" *)
+  wire [31:0] regOutput19;
+  (* src = ""../RF/reg_file.v:11"" *)
+  wire [31:0] regOutput20;
+  (* src = ""../RF/reg_file.v:11"" *)
+  wire [31:0] regOutput21;
+  (* src = ""../RF/reg_file.v:11"" *)
+  wire [31:0] regOutput22;
+  (* src = ""../RF/reg_file.v:11"" *)
+  wire [31:0] regOutput23;
+  (* src = ""../RF/reg_file.v:11"" *)
+  wire [31:0] regOutput24;
+  (* src = ""../RF/reg_file.v:11"" *)
+  wire [31:0] regOutput25;
+  (* src = ""../RF/reg_file.v:11"" *)
+  wire [31:0] regOutput26;
+  (* src = ""../RF/reg_file.v:11"" *)
+  wire [31:0] regOutput27;
+  (* src = ""../RF/reg_file.v:11"" *)
+  wire [31:0] regOutput28;
+  (* src = ""../RF/reg_file.v:11"" *)
+  wire [31:0] regOutput29;
+  (* src = ""../RF/reg_file.v:11"" *)
+  wire [31:0] regOutput30;
+  (* src = ""../RF/reg_file.v:11"" *)
+  wire [31:0] regOutput31;
+  (* src = ""../RF/reg_file.v:15"" *)
+  wire [31:0] int;
+  assign we[31] = regWrite & int[31];
+  assign we[30] = regWrite & int[30];
+  assign we[29] = regWrite & int[29];
+  assign we[28] = regWrite & int[28];
+  assign we[27] = regWrite & int[27];
+  assign we[26] = regWrite & int[26];
+  assign we[25] = regWrite & int[25];
+  assign we[24] = regWrite & int[24];
+  assign we[23] = regWrite & int[23];
+  assign we[22] = regWrite & int[22];
+  assign we[21] = regWrite & int[21];
+  assign we[20] = regWrite & int[20];
+  assign we[19] = regWrite & int[19];
+  assign we[18] = regWrite & int[18];
+  assign we[17] = regWrite & int[17];
+  assign we[16] = regWrite & int[16];
+  assign we[15] = regWrite & int[15];
+  assign we[14] = regWrite & int[14];
+  assign we[13] = regWrite & int[13];
+  assign we[12] = regWrite & int[12];
+  assign we[11] = regWrite & int[11];
+  assign we[10] = regWrite & int[10];
+  assign we[9] = regWrite & int[9];
+  assign we[8] = regWrite & int[8];
+  assign we[7] = regWrite & int[7];
+  assign we[6] = regWrite & int[6];
+  assign we[5] = regWrite & int[5];
+  assign we[4] = regWrite & int[4];
+  assign we[3] = regWrite & int[3];
+  assign we[2] = regWrite & int[2];
+  assign we[1] = regWrite & int[1];
+  (* src = ""../RF/reg_file.v:18"" *)
+  dec_5to32 dec (
+    .a(writeReg),
+    .b(int)
+  );
+  (* src = ""../RF/reg_file.v:53"" *)
+  reg_32bits reg0 (
+    .d(1\'b0),
+    .clk(clk),
+    .we(1\'b1),
+    .q(regOutput0)
+  );
+  (* src = ""../RF/reg_file.v:54"" *)
+  reg_32bits reg1 (
+    .d(writeData),
+    .clk(clk),
+    .we(we[1]),
+    .q(regOutput1)
+  );
+  (* src = ""../RF/reg_file.v:55"" *)
+  reg_32bits reg2 (
+    .d(writeData),
+    .clk(clk),
+    .we(we[2]),
+    .q(regOutput2)
+  );
+  (* src = ""../RF/reg_file.v:56"" *)
+  reg_32bits reg3 (
+    .d(writeData),
+    .clk(clk),
+    .we(we[3]),
+    .q(regOutput3)
+  );
+  (* src = ""../RF/reg_file.v:57"" *)
+  reg_32bits reg4 (
+    .d(writeData),
+    .clk(clk),
+    .we(we[4]),
+    .q(regOutput4)
+  );
+  (* src = ""../RF/reg_file.v:58"" *)
+  reg_32bits reg5 (
+    .d(writeData),
+    .clk(clk),
+    .we(we[5]),
+    .q(regOutput5)
+  );
+  (* src = ""../RF/reg_file.v:59"" *)
+  reg_32bits reg6 (
+    .d(writeData),
+    .clk(clk),
+    .we(we[6]),
+    .q(regOutput6)
+  );
+  (* src = ""../RF/reg_file.v:60"" *)
+  reg_32bits reg7 (
+    .d(writeData),
+    .clk(clk),
+    .we(we[7]),
+    .q(regOutput7)
+  );
+  (* src = ""../RF/reg_file.v:61"" *)
+  reg_32bits reg8 (
+    .d(writeData),
+    .clk(clk),
+    .we(we[8]),
+    .q(regOutput8)
+  );
+  (* src = ""../RF/reg_file.v:62"" *)
+  reg_32bits reg9 (
+    .d(writeData),
+    .clk(clk),
+    .we(we[9]),
+    .q(regOutput9)
+  );
+  (* src = ""../RF/reg_file.v:63"" *)
+  reg_32bits reg10 (
+    .d(writeData),
+    .clk(clk),
+    .we(we[10]),
+    .q(regOutput10)
+  );
+  (* src = ""../RF/reg_file.v:64"" *)
+  reg_32bits reg11 (
+    .d(writeData),
+    .clk(clk),
+    .we(we[11]),
+    .q(regOutput11)
+  );
+  (* src = ""../RF/reg_file.v:65"" *)
+  reg_32bits reg12 (
+    .d(writeData),
+    .clk(clk),
+    .we(we[12]),
+    .q(regOutput12)
+  );
+  (* src = ""../RF/reg_file.v:66"" *)
+  reg_32bits reg13 (
+    .d(writeData),
+    .clk(clk),
+    .we(we[13]),
+    .q(regOutput13)
+  );
+  (* src = ""../RF/reg_file.v:67"" *)
+  reg_32bits reg14 (
+    .d(writeData),
+    .clk(clk),
+    .we(we[14]),
+    .q(regOutput14)
+  );
+  (* src = ""../RF/reg_file.v:68"" *)
+  reg_32bits reg15 (
+    .d(writeData),
+    .clk(clk),
+    .we(we[15]),
+    .q(regOutput15)
+  );
+  (* src = ""../RF/reg_file.v:69"" *)
+  reg_32bits reg16 (
+    .d(writeData),
+    .clk(clk),
+    .we(we[16]),
+    .q(regOutput16)
+  );
+  (* src = ""../RF/reg_file.v:70"" *)
+  reg_32bits reg17 (
+    .d(writeData),
+    .clk(clk),
+    .we(we[17]),
+    .q(regOutput17)
+  );
+  (* src = ""../RF/reg_file.v:71"" *)
+  reg_32bits reg18 (
+    .d(writeData),
+    .clk(clk),
+    .we(we[18]),
+    .q(regOutput18)
+  );
+  (* src = ""../RF/reg_file.v:72"" *)
+  reg_32bits reg19 (
+    .d(writeData),
+    .clk(clk),
+    .we(we[19]),
+    .q(regOutput19)
+  );
+  (* src = ""../RF/reg_file.v:73"" *)
+  reg_32bits reg20 (
+    .d(writeData),
+    .clk(clk),
+    .we(we[20]),
+    .q(regOutput20)
+  );
+  (* src = ""../RF/reg_file.v:74"" *)
+  reg_32bits reg21 (
+    .d(writeData),
+    .clk(clk),
+    .we(we[21]),
+    .q(regOutput21)
+  );
+  (* src = ""../RF/reg_file.v:75"" *)
+  reg_32bits reg22 (
+    .d(writeData),
+    .clk(clk),
+    .we(we[22]),
+    .q(regOutput22)
+  );
+  (* src = ""../RF/reg_file.v:76"" *)
+  reg_32bits reg2'b'3 (
+    .d(writeData),
+    .clk(clk),
+    .we(we[23]),
+    .q(regOutput23)
+  );
+  (* src = ""../RF/reg_file.v:77"" *)
+  reg_32bits reg24 (
+    .d(writeData),
+    .clk(clk),
+    .we(we[24]),
+    .q(regOutput24)
+  );
+  (* src = ""../RF/reg_file.v:78"" *)
+  reg_32bits reg25 (
+    .d(writeData),
+    .clk(clk),
+    .we(we[25]),
+    .q(regOutput25)
+  );
+  (* src = ""../RF/reg_file.v:79"" *)
+  reg_32bits reg26 (
+    .d(writeData),
+    .clk(clk),
+    .we(we[26]),
+    .q(regOutput26)
+  );
+  (* src = ""../RF/reg_file.v:80"" *)
+  reg_32bits reg27 (
+    .d(writeData),
+    .clk(clk),
+    .we(we[27]),
+    .q(regOutput27)
+  );
+  (* src = ""../RF/reg_file.v:81"" *)
+  reg_32bits reg28 (
+    .d(writeData),
+    .clk(clk),
+    .we(we[28]),
+    .q(regOutput28)
+  );
+  (* src = ""../RF/reg_file.v:82"" *)
+  reg_32bits reg29 (
+    .d(writeData),
+    .clk(clk),
+    .we(we[29]),
+    .q(regOutput29)
+  );
+  (* src = ""../RF/reg_file.v:83"" *)
+  reg_32bits reg30 (
+    .d(writeData),
+    .clk(clk),
+    .we(we[30]),
+    .q(regOutput30)
+  );
+  (* src = ""../RF/reg_file.v:84"" *)
+  reg_32bits reg31 (
+    .d(writeData),
+    .clk(clk),
+    .we(we[31]),
+    .q(regOutput31)
+  );
+  (* src = ""../RF/reg_file.v:87"" *)
+  mux32bits_32to1 rd1 (
+    .i1(regOutput1),
+    .i0(regOutput0),
+    .s(readReg1),
+    .z(readData1),
+    .i31(regOutput31),
+    .i30(regOutput30),
+    .i29(regOutput29),
+    .i28(regOutput28),
+    .i27(regOutput27),
+    .i26(regOutput26),
+    .i25(regOutput25),
+    .i24(regOutput24),
+    .i23(regOutput23),
+    .i22(regOutput22),
+    .i21(regOutput21),
+    .i20(regOutput20),
+    .i19(regOutput19),
+    .i18(regOutput18),
+    .i17(regOutput17),
+    .i16(regOutput16),
+    .i15(regOutput15),
+    .i14(regOutput14),
+    .i13(regOutput13),
+    .i12(regOutput12),
+    .i11(regOutput11),
+    .i10(regOutput10),
+    .i9(regOutput9),
+    .i8(regOutput8),
+    .i7(regOutput7),
+    .i6(regOutput6),
+    .i5(regOutput5),
+    .i4(regOutput4),
+    .i3(regOutput3),
+    .i2(regOutput2)
+  );
+  (* src = ""../RF/reg_file.v:90"" *)
+  mux32bits_32to1 rd2 (
+    .i1(regOutput1),
+    .i0(regOutput0),
+    .s(readReg2),
+    .z(readData2),
+    .i31(regOutput31),
+    .i30(regOutput30),
+    .i29(regOutput29),
+    .i28(regOutput28),
+    .i27(regOutput27),
+    .i26(regOutput26),
+    .i25(regOutput25),
+    .i24(regOutput24),
+    .i23(regOutput23),
+    .i22(regOutput22),
+    .i21(regOutput21),
+    .i20(regOutput20),
+    .i19(regOutput19),
+    .i18(regOutput18),
+    .i17(regOutput17),
+    .i16(regOutput16),
+    .i15(regOutput15),
+    .i14(regOutput14),
+    .i13(regOutput13),
+    .i12(regOutput12),
+    .i11(regOutput11),
+    .i10(regOutput10),
+    .i9(regOutput9),
+    .i8(regOutput8),
+    .i7(regOutput7),
+    .i6(regOutput6),
+    .i5(regOutput5),
+    .i4(regOutput4),
+    .i3(regOutput3),
+    .i2(regOutput2)
+  );
+endmodule
+"
+"module dec_5to32 (
+  input [4:0] a,
+  output [31:0] b);  
+
+  and (b[0 ], ~a[4], ~a[3], ~a[2], ~a[1], ~a[0]);
+  and (b[1 ], ~a[4], ~a[3], ~a[2], ~a[1],  a[0]);
+  and (b[2 ], ~a[4], ~a[3], ~a[2],  a[1], ~a[0]);
+  and (b[3 ], ~a[4], ~a[3], ~a[2],  a[1],  a[0]);
+  and (b[4 ], ~a[4], ~a[3],  a[2], ~a[1], ~a[0]);
+  and (b[5 ], ~a[4], ~a[3],  a[2], ~a[1],  a[0]);
+  and (b[6 ], ~a[4], ~a[3],  a[2],  a[1], ~a[0]);
+  and (b[7 ], ~a[4], ~a[3],  a[2],  a[1],  a[0]);
+  and (b[8 ], ~a[4],  a[3], ~a[2], ~a[1], ~a[0]);
+  and (b[9 ], ~a[4],  a[3], ~a[2], ~a[1],  a[0]);
+  and (b[10], ~a[4],  a[3], ~a[2],  a[1], ~a[0]);
+  and (b[11], ~a[4],  a[3], ~a[2],  a[1],  a[0]);
+  and (b[12], ~a[4],  a[3],  a[2], ~a[1], ~a[0]);
+  and (b[13], ~a[4],  a[3],  a[2], ~a[1],  a[0]);
+  and (b[14], ~a[4],  a[3],  a[2],  a[1], ~a[0]);
+  and (b[15], ~a[4],  a[3],  a[2],  a[1],  a[0]);
+  and (b[16],  a[4], ~a[3], ~a[2], ~a[1], ~a[0]);
+  and (b[17],  a[4], ~a[3], ~a[2], ~a[1],  a[0]);
+  and (b[18],  a[4], ~a[3], ~a[2],  a[1], ~a[0]);
+  and (b[19],  a[4], ~a[3], ~a[2],  a[1],  a[0]);
+  and (b[20],  a[4], ~a[3],  a[2], ~a[1], ~a[0]);
+  and (b[21],  a[4], ~a[3],  a[2], ~a[1],  a[0]);
+  and (b[22],  a[4], ~a[3],  a[2],  a[1], ~a[0]);
+  and (b[23],  a[4], ~a[3],  a[2],  a[1],  a[0]);
+  and (b[24],  a[4],  a[3], ~a[2], ~a[1], ~a[0]);
+  and (b[25],  a[4],  a[3], ~a[2], ~a[1],  a[0]);
+  and (b[26],  a[4],  a[3], ~a[2],  a[1], ~a[0]);
+  and (b[27],  a[4],  a[3], ~a[2],  a[1],  a[0]);
+  and (b[28],  a[4],  a[3],  a[2], ~a[1], ~a[0]);
+  and (b[29],  a[4],  a[3],  a[2], ~a[1],  a[0]);
+  and (b[30],  a[4],  a[3],  a[2],  a[1], ~a[0]);
+  and (b[31],  a[4],  a[3],  a[2],  a[1],  a[0]);
+
+endmodule
+"
+"`include ""../lib/shift_left_2.v""
+
+module test;
+
+  reg  [31:0] a;
+  wire [31:0] b;
+
+  shift_left_2 shift (
+    .a(a),
+    .b(b));
+  initial begin
+    $monitor ($time, "": a=%5d, b=%5d"", a, b);
+    #5 a = 0;
+    #5 a = 2;
+    #5 a = 9;
+  end
+
+endmodule
+"
+"`include ""../lib/mux_32to1.v""
+
+module test;
+
+  reg  [4:0] s;
+  reg  [31:0] i31, i30, i29, i28, i27, i26, i25, i24, i23,i22, i21, i20, i19, i18, i17, i16;
+  reg  [31:0] i15, i14, i13, i12, i11, i10, i9, i8, i7,i6, i5, i4, i3, i2, i1, i0;
+  wire [31:0] z;
+
+  reg [31:0] val, expect;
+  mux_32to1 mux(
+    .s  (s ),
+    .i31(i31),  
+    .i30(i30),
+    .i29(i29),
+    .i28(i28),
+    .i27(i27),
+    .i26(i26),
+    .i25(i25),
+    .i24(i24),
+    .i23(i23),
+    .i22(i22),
+    .i21(i21),
+    .i20(i20),
+    .i19(i19),
+    .i18(i18),
+    .i17(i17),
+    .i16(i16),
+    .i15(i15),   
+    .i14(i14),
+    .i13(i13),
+    .i12(i12),
+    .i11(i11),
+    .i10(i10),
+    .i9 (i9 ),
+    .i8 (i8 ),
+    .i7 (i7 ),
+    .i6 (i6 ),
+    .i5 (i5 ),
+    .i4 (i4 ),
+    .i3 (i3 ),
+    .i2 (i2 ),
+    .i1 (i1 ),
+    .i0 (i0 ),
+    .z  (z ));
+  
+  initial begin
+    $monitor($time, "": %d expect=%d"", val, expect);
+    #5 i31 = 5; val = i31; s = 5\'b11111;
+    
+  end
+
+// 0000 0
+// 0001 1
+// 0010 2
+// 0011 3
+// 0100 4
+// 0101 5
+// 0110 6
+// 0111 7
+// 1000 8
+// 1001 9
+// 1010 10
+// 1011 11
+// 1100 12
+// 1101 13
+// 1110 14
+// 1111 15
+ 
+endmodule
+"
+"`include ""../lib/mux_16to1.v""
+`include ""../lib/full_adder.v""
+`include ""../lib/full_subtractor.v""
+
+module one_bit_alu (
+  input  [3:0] op,
+  input  a, b, cin, less,
+  output r, cout, bout, set
+  );
+ 
+wire int0, int1, int2, int3, addOP, subOP, addOP_cout, subOP_bout;
+and (int0, a, b);
+or  (int1, a, b);
+xor (int2, a, b);
+nor (int3, a, b);
+
+xor (xorB, b, sub);
+
+full_adder       add     (.sum(addOP), .a(a), .b(b), .cin   (cin), .cout   (addOP_cout));
+full_subtractor  subtract(.d  (subOP), .a(b), .b(a), .Bor_in(cin), .Bor_out(subOP_bout));
+
+buf(set, subOP);
+
+mux_16to1 mux0(
+  .s  (op    ),
+  .i0 (int0  ), // and
+  .i1 (int1  ), // or
+  .i2 (addOP ), // add
+  .i6 (subOP ), // sub
+  .i7 (less  ), // less
+  .i12(int3  ), // nor
+  .z  (r    ));
+
+mux_16to1 mux1(
+  .s(op),
+  .i2(addOP_cout),
+  .i6(subOP_bout),
+  .i7(subOP_bout),  
+  .z(cout));
+endmodule
+
+"
+"`define MEM_SIZE 256
+`define INIT ""../lib/initRegisters.txt""
+`define VAL ""../lib/regVals.txt""
+
+module im (
+  input clk,
+  input [31:0] addr,
+  output [31:0] data
+);
+  reg [31:0] mem [0:`MEM_SIZE-1];  
+  reg [7:0] test_begin, test_end, regVals_begin, regVals_end;
+
+  `ifdef R_TYPE
+    parameter path = ""../program/r_type.txt"";
+  `elsif I_TYPE
+    parameter path = ""../program/i_type.txt"";
+  `elsif BRANCH
+    parameter path = ""../program/branch.txt"";
+ `elsif BRANCHN
+    parameter path = ""../program/branchn.txt"";
+  `elsif JUMP
+    parameter path = ""../program/jump.txt"";
+  `elsif JAL
+    parameter path = ""../program/jal.txt"";
+  `elsif LOOP
+    parameter path = ""../program/loop.txt"";
+  `else
+    parameter path = ""../program/test.txt"";
+  `endif 
+
+  parameter initRegisters = `INIT;
+  parameter regVals       = `VAL;
+ 
+ initial begin
+   /* 
+    test_begin    = 31;
+    test_end      = 30+`CODE_SIZE;
+    regVals_begin = 30+`CODE_SIZE+1;
+    regVals_end   = 30+`CODE_SIZE+32;
+  */
+    $readmemh(path, mem, 1, `MEM_SIZE-33 );
+   // $readmemh(initRegisters, mem, 0  , 30 );
+   // $readmemh(path         , mem, 31 , `MEM_SIZE-33);
+   // $readmemh(regVals      , mem, `MEM_SIZE-32, `MEM_SIZE-1);
+  end
+  assign data = mem[addr];
+ 
+endmodule
+
+"
+"`define AND 4\'b0000
+`define OR  4\'b0001
+`define ADD 4\'b0010
+`define SUB 4\'b0110
+`define SLT 4\'b0111
+`define NOR 4\'b1100
+
+`include ""../ALU/one_bit_alu.v""
+
+module alu (
+  input [3:0] op,
+  input signed [31:0] a, b,
+  output signed [31:0] z, 
+  output zero);
+
+wire set;
+wire [30:0] carry;
+
+one_bit_alu alu0  (.op(op), .r(z[0 ]), .a(a[0 ]), .b(b[0 ]), .cin(1\'b0     ), .cout(carry[0 ]), .less(set )); 
+one_bit_alu alu1  (.op(op), .r(z[1 ]), .a(a[1 ]), .b(b[1 ]), .cin(carry[0 ]), .cout(carry[1 ]), .less(1\'b0));
+one_bit_alu alu2  (.op(op), .r(z[2 ]), .a(a[2 ]), .b(b[2 ]), .cin(carry[1 ]), .cout(carry[2 ]), .less(1\'b0));
+one_bit_alu alu3  (.op(op), .r(z[3 ]), .a(a[3 ]), .b(b[3 ]), .cin(carry[2 ]), .cout(carry[3 ]), .less(1\'b0));
+one_bit_alu alu4  (.op(op), .r(z[4 ]), .a(a[4 ]), .b(b[4 ]), .cin(carry[3 ]), .cout(carry[4 ]), .less(1\'b0));
+one_bit_alu alu5  (.op(op), .r(z[5 ]), .a(a[5 ]), .b(b[5 ]), .cin(carry[4 ]), .cout(carry[5 ]), .less(1\'b0));
+one_bit_alu alu6  (.op(op), .r(z[6 ]), .a(a[6 ]), .b(b[6 ]), .cin(carry[5 ]), .cout(carry[6 ]), .less(1\'b0));
+one_bit_alu alu7  (.op(op), .r(z[7 ]), .a(a[7 ]), .b(b[7 ]), .cin(carry[6 ]), .cout(carry[7 ]), .less(1\'b0));
+one_bit_alu alu8  (.op(op), .r(z[8 ]), .a(a[8 ]), .b(b[8 ]), .cin(carry[7 ]), .cout(carry[8 ]), .less(1\'b0));
+one_bit_alu alu9  (.op(op), .r(z[9 ]), .a(a[9 ]), .b(b[9 ]), .cin(carry[8 ]), .cout(carry[9 ]), .less(1\'b0));
+one_bit_alu alu10 (.op(op), .r(z[10]), .a(a[10]), .b(b[10]), .cin(carry[9 ]), .cout(carry[10]), .less(1\'b0));
+one_bit_alu alu11 (.op(op), .r(z[11]), .a(a[11]), .b(b[11]), .cin(carry[10]), .cout(carry[11]), .less(1\'b0));
+one_bit_alu alu12 (.op(op), .r(z[12]), .a(a[12]), .b(b[12]), .cin(carry[11]), .cout(carry[12]), .less(1\'b0));
+one_bit_alu alu13 (.op(op), .r(z[13]), .a(a[13]), .b(b[13]), .cin(carry[12]), .cout(carry[13]), .less(1\'b0));
+one_bit_alu alu14 (.op(op), .r(z[14]), .a(a[14]), .b(b[14]), .cin(carry[13]), .cout(carry[14]), .less(1\'b0));
+one_bit_alu alu15 (.op(op), .r(z[15]), .a(a[15]), .b(b[15]), .cin(carry[14]), .cout(carry[15]), .less(1\'b0));
+one_bit_alu alu16 (.op(op), .r(z[16]), .a(a[16]), .b(b[16]), .cin(carry[15]), .cout(carry[16]), .less(1\'b0));
+one_bit_alu alu17 (.op(op), .r(z[17]), .a(a[17]), .b(b[17]), .cin(carry[16]), .cout(carry[17]), .less(1\'b0));
+one_bit_alu alu18 (.op(op), .r(z[18]), .a(a[18]), .b(b[18]), .cin(carry[17]), .cout(carry[18]), .less(1\'b0));
+one_bit_alu alu19 (.op(op), .r(z[19]), .a(a[19]), .b(b[19]), .cin(carry[18]), .cout(carry[19]), .less(1\'b0));
+one_bit_alu alu20 (.op(op), .r(z[20]), .a(a[20]), .b(b[20]), .cin(carry[19]), .cout(carry[20]), .less(1\'b0));
+one_bit_alu alu21 (.op(op), .r(z[21]), .a(a[21]), .b(b[21]), .cin(carry[20]), .cout(carry[21]), .less(1\'b0));
+one_bit_alu alu22 (.op(op), .r(z[22]), .a(a[22]), .b(b[22]), .cin(carry[21]), .cout(carry[22]), .less(1\'b0));
+one_bit_alu alu23 (.op(op), .r(z[23]), .a(a[23]), .b(b[23]), .cin(carry[22]), .cout(carry[23]), .less(1\'b0));
+one_bit_alu alu24 (.op(op), .r(z[24]), .a(a[24]), .b(b[24]), .cin(carry[23]), .cout(carry[24]), .less(1\'b0));
+one_bit_alu alu25 (.op(op), .r(z[25]), .a(a[25]), .b(b[25]), .cin(carry[24]), .cout(carry[25]), .less(1\'b0));
+one_bit_alu alu26 (.op(op), .r(z[26]), .a(a[26]), .b(b[26]), .cin(carry[25]), .cout(carry[26]), .less(1\'b0));
+one_bit_alu alu27 (.op(op), .r(z[27]), .a(a[27]), .b(b[27]), .cin(carry[26]), .cout(carry[27]), .less(1\'b0));
+one_bit_alu alu28 (.op(op), .r(z[28]), .a(a[28]), .b(b[28]), .cin(carry[27]), .cout(carry[28]), .less(1\'b0));
+one_bit_alu alu29 (.op(op), .r(z[29]), .a(a[29]), .b(b[29]), .cin(carry[28]), .cout(carry[29]), .less(1\'b0));
+one_bit_alu alu30 (.op(op), .r(z[30]), .a(a[30]), .b(b[30]), .cin(carry[29]), .cout(carry[30]), .less(1\'b0));
+one_bit_alu alu31 (.op(op), .r(z[31]), .a(a[31]), .b(b[31]), .cin(carry[30]), .set (set      ), .less(1\'b0));
+
+nor (zero, z[0 ], z[1 ], z[2 ], z[3 ], z[4 ], z[5 ], z[6 ], z[7 ], z[8 ], z[9 ],
+           z[10], z[11], z[12], z[13], z[14], z[15], z[16], z[17], z[18], z[19],
+           z[20], z[21], z[22], z[23], z[24], z[25], z[26], z[27], z[28], z[29], 
+           z[30], z[31]);
+
+endmodule
+"
+"`include ""../lib/sub.v""
+module test;
+
+reg  signed [31:0] a, b;
+wire signed [31:0] d;
+wire bout;
+
+sub Sub_op(
+  .a(a),
+  .b(b),
+  .Bor_out(bout),
+  .d(d));
+
+initial begin
+  $monitor ($time, "": %0d %0d | %0d %0d"", a, b, bout, d);
+  #5 a = 0; b = 0; 
+  #5 a = 2; b = 9; 
+  #5 a = 1; b = 1; 
+  #5 a = 10; b = 6;
+end
+
+endmodule
+
+"
+"`include ""../RF/reg_32bits.v""
+
+module test;
+
+  reg [31:0] d;
+  reg we, clk;
+  wire [31:0] q;
+
+  reg_32bits register (d, we, clk, q);
+
+  always #6 clk = ~clk;
+
+  initial begin
+ 
+    $dumpfile(""test22.vcd"");
+    $dumpvars(0, test); 
+    clk = 0;
+    $display ($time, "": d=%5d, q=%5d, we=%b"", d, q, we);
+    #5 d = 4; we = 1;
+    $display ($time, "": d=%5d, q=%5d, we=%b"", d, q, we);
+    #5 d = 53;
+    $display ($time, "": d=%5d, q=%5d, we=%b"", d, q, we);
+    #5 d = 6; we = 0;
+    $display ($time, "": d=%5d, q=%5d, we=%b"", d, q, we);
+    #5;
+    $display ($time, "": d=%5d, q=%5d, we=%b"", d, q, we);
+    $finish;
+  end
+
+endmodule
+"
+"`include ""../lib/mux_8to1.v""
+
+module test;
+
+  reg [2:0] s;
+  reg i7, i6, i5, i4, i3, i2, i1, i0;
+
+  wire z;
+  mux_8to1 mux(
+    .s (s ),
+    .i7(i7),
+    .i6(i6),
+    .i5(i5),
+    .i4(i4),
+    .i3(i3),
+    .i2(i2),
+    .i1(i1),
+    .i0(i0),
+    .z (z));
+
+// 000 0
+// 001 1
+// 010 2
+// 011 3
+// 100 4
+// 101 5
+// 110 6
+// 111 7
+ 
+  initial begin
+    $monitor($time, "": %b  %b  %b  %b  %b  %b  %b  %b | %b  %b  %b | %b"", i7,  i6,  i5,  i4,  i3,  i2,  i1,  i0,  s[2],  s[1],  s[0], z);
+    
+    #5 i7 = 0; i6 = 0; i5 = 0;  i4 = 0; i3 = 0; i2 = 0; i1 = 0; i0 = 0; s[2] = 0; s[1] = 0; s[0] = 0;
+    #5 i4 = 1; i5 = 1; i2 = 1; s[1] = 1; // 010 select i2
+    #5 s[0] = 1; // 011 select i3
+    #5 s[2] = 1; // 111 select i7
+    #5 i7 = 0;
+    #5 s[1] = 0; // 101 select i5
+    #5 i5 = 1;
+  end
+
+endmodule
+
+ 
+"
+"module dm (
+  input clk,
+  input [31:0] addr, writeData,
+  input memWrite, memRead,
+  output [31:0] readData
+);
+
+  reg [31:0] mem [0:255];  
+  
+  always @(posedge clk) begin 
+    if(memWrite)
+      mem[addr] <= writeData;
+  end
+
+  assign readData = memRead ? mem[addr] : 0;
+endmodule
+"
+"`include ""../lib/add.v""
+module test;
+
+reg [31:0] a, b;
+reg cin;
+wire [31:0] sum;
+wire cout;
+
+add Add_op(
+  .a(a),
+  .b(b),
+  .cin(cin),
+  .cout(cout),
+  .sum(sum));
+
+initial begin
+  $monitor ($time, "": %0d %0d %0d | %0d %0d"", a, b, cin, cout, sum);
+  #5 a = 0; b = 0; cin = 0;
+  #5 a = 2; b = 9; cin = 0;
+  #5 cin = 1;
+  #5 a = 1; b = 1; cin = 0;
+end
+
+endmodule
+
+"
+"module mux5bit_4to1 (
+  input [4:0] i0, i1, i2, i3,
+  input [1:0] s ,
+  output [4:0] z
+);
+  
+  reg [4:0] z;
+
+  initial z = 0;
+
+  always @(*) begin
+      case(s)
+        2'b00 : z = i0;
+        2'b01 : z = i1;
+        2'b10 : z = i2;
+        2'b11 : z = i3;
+      endcase
+  end
+
+endmodule
+"
+"module mux32bit_2to1_2(input [31:0] i0, i1,
+                    input s,
+                    output [31:0] z);
+  reg [31:0] z;
+
+  initial z = 0;
+
+  always @(*) begin
+    casex (s)
+      1'b0: z = i0;
+      1'b1: z = i1;
+    endcase
+  end
+endmodule
+"
+"`include ""../lib/full_subtractor.v""
+
+module test; 
+  reg a, b, bin;
+  wire bout, d;
+  
+  full_subtractor subtractor(
+    .a(a),
+    .b(b),
+    .d(d),
+    .Bor_in(bin),
+    .Bor_out(bout));
+
+  initial begin
+    $monitor ($time, "":  %b  %b  %b | %b %b"", a, b, bin, bout, d);
+    #5 a = 0; b = 0; bin = 0;
+    #5 a = 1;
+    #5 a = 0; b = 1;
+    #5 a = 1;
+    #5 a = 0; b = 0; bin = 1;
+    #5 a = 1;
+    #5 a = 0; b = 1;
+    #5 a = 1;
+    #7; 
+  end
+
+endmodule
+"
+"module reg_file (
+  input  [4:0]  readReg1, readReg2, writeReg,
+  input  [31:0] writeData,
+  input regWrite, clk,
+  output [31:0] readData1, readData2);
+  reg [5:0]i;
+  reg [31:0] regs [0:31];
+  initial begin
+    for(i = 0; i < 32; i = i + 1) begin
+      regs[i] = 0;
+    end
+  end
+
+  always @(negedge clk) begin
+    if(regWrite && writeReg != 0)  
+      regs[writeReg] = writeData;
+  end
+  
+  assign readData1 = (readReg1 != 0) ? regs[readReg1] : 0;
+  assign readData2 = (readReg2 != 0) ? regs[readReg2] : 0;
+
+endmodule
+"
+"`include ""../ALU/one_bit_alu.v""
+
+module test; 
+
+  reg [3:0] op;
+  reg a, b, cin, less;
+  wire z, cout, set;
+  wire op3_bar, op2_bar, op1_bar, op0_bar, sub;
+  
+  not ( op3_bar, op[3]);
+  not ( op2_bar, op[2]);
+  not ( op1_bar, op[1]);
+  not ( op0_bar, op[0]);
+  and ( sub, op3_bar, op[2], op[1], op0_bar);
+  
+  one_bit_alu alu0 (
+    .op(op), 
+    .a(a), 
+    .b(b), 
+    .cin(cin), 
+    .less(less), 
+    .sub(sub), 
+    .r(z), 
+    .cout(cout)); 
+    
+  initial begin
+    $monitor ($time, "": sub=%b\\ta=%b\\tb=%b\\tcin=%b\\top=%d\\tz=%b\\tcout=%b"", sub, a, b,cin, op, z, cout);
+    #5 a = 0; b = 1; op = 0 ; cin = 0; 
+    #5 op = 1 ;   
+    #5 a = 1; op = 2;   
+    #5 op = 6 ; 
+    #5 op = 12; a = 1; b = 0;
+    #7;
+  end
+endmodule
+"
+"module full_adder (
+  output cout, sum,
+  input a, b, cin
+  );
+
+wire int1, int2, int3;
+
+xor (int1, a   , b   );
+xor (sum , int1, cin );
+and (int2, int1, cin );
+and (int3, a   , b   );
+or  (cout, int2, int3);
+
+endmodule
+"
+"module mux32bit_4to1 (
+  input [31:0] i0, i1, i2, i3,
+  input [1:0] s,
+
+  output [31:0] z
+);
+  
+  reg [31:0] z;
+
+  initial z = 0;
+
+  always @(*) begin
+      case(s)
+        2'b00 : z = i0;
+        2'b01 : z = i1;
+        2'b10 : z = i2;
+        2'b11 : z = i3;
+      endcase
+  end
+
+endmodule
+"
+"module verilog_verilator_error;
+   initial begin
+      forever begin
+         i = $fopen(""test.log"");
+      end
+   end
+endmodule
+"
+"module verilator_warning;
+   reg val;
+endmodule
+"
+"Module Error.
+
+  Fixpoint evenb (n:nat) : bool :=
+    match n with
+      | O => true
+      | S O => false
+      | S (S n') => 1
+    end.
+
+End Error.
+"
+"Module SyntaxError.
+
+  Fixpoint evenb (n:nat) : bool :=
+    match n with
+      | O => true
+       S O => false
+      | S (S n') => evenb n'
+    end.
+
+End SyntaxError.
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    00:18:04 04/12/2016 
+// Design Name: 
+// Module Name:    decofdificador_cs_registros 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module decodificador_cs_registros(
+\tinput [1:0]funcion_conf,
+\toutput reg cs_seg_hora,
+\toutput reg cs_min_hora,
+\toutput reg cs_hora_hora,
+\toutput reg cs_dia_fecha,
+\toutput reg cs_mes_fecha,
+\toutput reg cs_jahr_fecha,
+\toutput reg cs_seg_timer,
+\toutput reg cs_min_timer,
+\toutput reg cs_hora_timer
+    );
+\t 
+always@*
+begin
+\tcase(funcion_conf)
+\t\t2'b00: begin
+\t\tcs_seg_hora = 1'b0;
+\t\tcs_min_hora= 1'b0;
+\t\tcs_hora_hora= 1'b0;
+\t\tcs_dia_fecha= 1'b0;
+\t\tcs_mes_fecha= 1'b0;
+\t\tcs_jahr_fecha= 1'b0;
+\t\tcs_seg_timer= 1'b0;
+\t\tcs_min_timer= 1'b0;
+\t\tcs_hora_timer= 1'b0;
+\t\t\tend
+\t\t2'b01: begin
+\t\tcs_seg_hora = 1'b1;
+\t\tcs_min_hora= 1'b1;
+\t\tcs_hora_hora= 1'b1;
+\t\tcs_dia_fecha= 1'b0;
+\t\tcs_mes_fecha= 1'b0;
+\t\tcs_jahr_fecha= 1'b0;
+\t\tcs_seg_timer= 1'b0;
+\t\tcs_min_timer= 1'b0;
+\t\tcs_hora_timer= 1'b0;
+\t\t\tend
+\t\t2'b10: begin
+\t\tcs_seg_hora = 1'b0;
+\t\tcs_min_hora= 1'b0;
+\t\tcs_hora_hora= 1'b0;
+\t\tcs_dia_fecha= 1'b1;
+\t\tcs_mes_fecha= 1'b1;
+\t\tcs_jahr_fecha= 1'b1;
+\t\tcs_seg_timer= 1'b0;
+\t\tcs_min_timer= 1'b0;
+\t\tcs_hora_timer= 1'b0;
+\t\t\tend
+\t\t2'b11:
+\t\t\tbegin
+\t\tcs_seg_hora = 1'b0;
+\t\tcs_min_hora= 1'b0;
+\t\tcs_hora_hora= 1'b0;
+\t\tcs_dia_fecha= 1'b0;
+\t\tcs_mes_fecha= 1'b0;
+\t\tcs_jahr_fecha= 1'b0;
+\t\tcs_seg_timer= 1'b1;
+\t\tcs_min_timer= 1'b1;
+\t\tcs_hora_timer= 1'b1;
+\tend
+\tdefault: begin
+\t\tcs_seg_hora = 1'b0;
+\t\tcs_min_hora= 1'b0;
+\t\tcs_hora_hora= 1'b0;
+\t\tcs_dia_fecha= 1'b0;
+\t\tcs_mes_fecha= 1'b0;
+\t\tcs_jahr_fecha= 1'b0;
+\t\tcs_seg_timer= 1'b0;
+\t\tcs_min_timer= 1'b0;
+\t\tcs_hora_timer= 1'b0;
+\tend
+endcase
+end
+
+endmodule
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: Jafet Chaves Barrantes
+// 
+// Create Date:    11:45:21 03/21/2016 
+// Design Name: 
+// Module Name:    timing_generator_VGA 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description:
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module timing_generator_VGA
+(
+input wire clk,reset,
+output wire hsync,vsync,video_on,p_tick,
+output wire [9:0] pixel_x, pixel_y
+);
+
+//Declaraci\xf3n de constantes
+
+//Par\xe1metros para VGA 640x480 
+localparam HD = 640;//\xe1rea de despliegue horizontal
+localparam HF = 48;// borde izquierdo horizontal
+localparam HB = 16;//borde derecho horizontal(16)
+localparam HR = 96;//retraso horizontal
+localparam VD = 480;//\xe1rea de despliegue vertical
+localparam VF = 10;//borde superior vertical
+localparam VB = 33;//borde inferior vertical
+localparam VR = 2;//retraso vertical
+
+//Contadores
+
+//Contador para la divisi\xf3n de frecuencia (100 MHz a 25 MHz)
+//reg mod2_reg;
+//wire mod2_next;
+
+reg cuenta, CV;
+
+//Contadores de ""timing"" vertical y horizontal
+reg[9:0] h_count_reg, h_count_next;
+reg[9:0] v_count_reg, v_count_next;
+reg h_sync_reg, v_sync_reg;
+wire h_sync_next, v_sync_next;
+
+//Se\xf1ales de status
+wire h_end, v_end; 
+wire pixel_tick;
+
+//Definici\xf3n de comportamiento
+
+//Registros
+always @(posedge clk, posedge reset)
+begin
+if(reset)
+\tbegin
+\t//mod2_reg <= 1\'b0;
+\th_count_reg <= 0;
+\tv_count_reg <= 0;
+\th_sync_reg <= 1\'b0;
+\tv_sync_reg <= 1\'b0;
+\tend
+
+else
+\tbegin
+\t//mod2_reg <= mod2_next;
+\th_count_reg <= h_count_next;
+\tv_count_reg <= v_count_next;
+\th_sync_reg <= h_sync_next;
+\tv_sync_reg <= v_sync_next;\t\t
+\tend
+end
+
+//Para generar 25 MHz
+
+always@(posedge clk, posedge reset)
+begin
+
+\tif(reset)
+\tbegin
+\tcuenta <= 0; 
+\tCV <= 0;
+\tend
+\t
+\telse
+\tbegin
+\t\tif (cuenta == 1\'b1)
+\t\t\tbegin
+\t\t\tcuenta <= 0;
+\t\t\tCV <= ~CV;
+\t\t\tend
+\t\telse
+\t\t\tcuenta <= cuenta + 1\'b1;
+\tend
+end\t
+//assign mod2_next = ~mod2_reg;
+assign pixel_tick = CV;
+
+
+//Definici\xf3n se\xf1ales de status
+
+//Final del contador horizontal (799)
+assign h_end = (h_count_reg == (HD+HF+HB+HR-1));
+
+//Final contador vertical (524)
+assign v_end = (v_count_reg == (VD+VF+VB+VR-1));
+
+//L\xf3gicas de estado siguiente de los contadores
+
+//Contador horizontal
+always@(negedge pixel_tick)
+begin
+\t//if(pixel_tick) //pulso de 25 MHz\t
+\t\tif(h_end)
+\t\th_count_next = 0;
+\t
+\t\telse
+\t\th_count_next = h_count_reg + 1\'b1;
+\t
+/*\telse
+\th_count_next = h_count_reg; //Mantiene la cuenta*/
+end
+
+//Contador vertical
+always@(negedge pixel_tick)
+begin
+\t//if(pixel_tick & h_end) //pulso de 25 MHz y final de fila
+\tif(h_end) //pulso de 25 MHz y final de fila
+\t\t
+\t\tif(v_end)
+\t\tv_count_next = 0;
+\t
+\t\telse
+\t\tv_count_next = v_count_reg + 1\'b1;
+\t
+\telse
+\tv_count_next = v_count_reg; //Mantiene la cuenta
+end
+
+/*h_sync_next puesto en bajo para generar retraso
+entre la cuentas 656 y 751*/
+assign h_sync_next = (h_count_reg >= (HD+HB)&&
+\t\t\t\t\t\t\t h_count_reg <=(HD+HB+HR-1));
+
+/*v_sync_next puesto en bajo para generar retraso
+entre la cuentas 490 y 491*/
+assign v_sync_next = (v_count_reg >= (VD+VB)&&
+\t\t\t\t\t\t\t v_count_reg <=(VD+VB+VR-1));
+
+//Asignaci\xf3n de salidas
+
+//Para generar se\xf1al video on/off
+assign video_on = (h_count_reg < HD) && (v_count_reg < VD); //Para mantener una forma de saber si el pixel est\xe1 en la regi\xf3n visible
+assign hsync = ~h_sync_reg;
+assign vsync = ~v_sync_reg;
+assign pixel_x = h_count_reg; //Coordenada x
+assign pixel_y = v_count_reg; //Coordenada y
+assign p_tick = pixel_tick; //Ayuda a coordinar la creaci\xf3n de im\xe1genes (m\xf3dulo de generaci\xf3n de p\xedxeles)
+
+endmodule
+
+/*Notas: 
+1. La frecuencia del ""timing"" vertical
+define el tiempo de refresco de la pantalla
+(30 fps, 60 fps,etc)
+2. 25 MHz es la frecuencia de escritura de cada
+p\xedxel (pixel_clk)
+3.video_on debe tener un per\xedodo igual al que corresponde escribir sobre la regi\xf3n visible*/
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: Jafet Chaves Barrantes
+// 
+// Create Date:    21:25:31 04/04/2016 
+// Design Name: 
+// Module Name:    contadores_configuracion 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module contadores_configuracion
+(
+input wire clk, 
+input wire reset,
+input wire [7:0] in_dato, port_id,
+input wire write_strobe, k_write_strobe,
+output wire [7:0] btn_data_SS, btn_data_MM, btn_data_HH, btn_data_YEAR, btn_data_MES, btn_data_DAY,
+btn_data_SS_T, btn_data_MM_T, btn_data_HH_T,//Decenas y unidades para los n\xfameros en pantalla(configuraci\xf3n)
+output wire [1:0] cursor_location,//Marca la posici\xf3n del cursor en modo configuraci\xf3n
+output wire [1:0] config_mode
+);
+
+//Declaraci\xf3n de par\xe1metros
+localparam N = 2;//Bits del contador de desplazamiento horizontal
+
+//Declaraci\xf3n de se\xf1ales
+reg [N-1:0] q_act, q_next;//Contador horizontal
+wire [N-1:0] count_horizontal;
+
+reg enLEFT_reg, enRIGHT_reg, enUP_reg, enDOWN_reg;
+reg [1:0] reg_config_mode, next_config_mode;
+
+reg [3:0]enable_counters;//9 contadores en total de hora, fecha, timer
+
+//===========================================================================
+// Registro para el modo de configuraci\xf3n
+//===========================================================================
+always@(posedge clk)
+begin
+\tif(reset) reg_config_mode <= 2'b0;
+\telse reg_config_mode <= next_config_mode;
+end
+always@*
+begin
+\tif((write_strobe == 1'b1 || k_write_strobe == 1'b1)&&(port_id == 8'h11)) next_config_mode = in_dato[4:3];
+\telse next_config_mode = reg_config_mode;
+end
+
+assign config_mode = reg_config_mode;
+//===========================================================================
+// Registro para generar el pulso de las teclas para modificar los contadores
+//===========================================================================
+always@(posedge clk)
+begin
+\tif(write_strobe == 1'b1 || k_write_strobe == 1'b1)
+\tbegin
+\t\tcase(port_id)
+\t\t8'h11:
+\t\t\tbegin
+\t\t\t\tif(in_dato[2] == 1'b1)
+\t\t\t\tbegin
+\t\t\t\t\tcase(in_dato[1:0])
+\t\t\t\t\t2'b00: enRIGHT_reg <= 1'b1;
+\t\t\t\t\t2'b01: enUP_reg <= 1'b1;
+\t\t\t\t\t2'b10: enDOWN_reg <= 1'b1;
+\t\t\t\t\t2'b11: enLEFT_reg <= 1'b1;
+\t\t\t\t\tendcase
+\t\t\t\tend
+\t\t\t\telse
+\t\t\t\tbegin
+\t\t\t\t\tenRIGHT_reg <= 1'b0;
+\t\t\t\t\tenUP_reg <= 1'b0;
+\t\t\t\t\tenDOWN_reg <= 1'b0;
+\t\t\t\t\tenLEFT_reg <= 1'b0;
+\t\t\t\tend
+\t\t\tend
+\t\tdefault:
+\t\tbegin
+\t\t\t\tenRIGHT_reg <= 1'b0;
+\t\t\t\tenUP_reg <= 1'b0;
+\t\t\t\tenDOWN_reg <= 1'b0;
+\t\t\t\tenLEFT_reg <= 1'b0;
+\t\tend
+\t\tendcase
+\tend
+\telse
+\tbegin
+\t\tenRIGHT_reg <= 1'b0;
+\t\tenUP_reg <= 1'b0;
+\t\tenDOWN_reg <= 1'b0;
+\t\tenLEFT_reg <= 1'b0;
+\tend
+end
+
+
+
+//Contador horizontal
+//Descripci\xf3n del comportamiento
+always@(posedge clk)
+begin\t
+\t
+\tif(reset)
+\tbegin
+\t\tq_act <= 2'b0;
+\tend
+\t
+\telse
+\tbegin
+\t\tq_act <= q_next;
+\tend
+end
+
+//L\xf3gica de salida
+always@*
+begin
+\tif(enLEFT_reg)
+\tbegin
+\tq_next = q_act + 1'b1;
+\tend
+\t
+\telse if(enRIGHT_reg)
+\tbegin
+\tq_next = q_act - 1'b1;
+\tend
+\t
+\telse if(enLEFT_reg && q_act == 2 && config_mode == 1)
+\tbegin
+\tq_next = 5'd0;
+\tend
+\t
+\telse if(enRIGHT_reg && q_act == 0 && config_mode == 1)
+\tbegin
+\tq_next = 5'd2;
+\tend
+\t
+\telse if(enLEFT_reg && q_act == 2 && config_mode == 4)
+\tbegin
+\tq_next = 5'd0;
+\tend
+\t
+\telse if(enRIGHT_reg && q_act == 0 && config_mode == 4)
+\tbegin
+\tq_next = 5'd2;
+\tend\t
+\t
+\telse
+\tbegin
+\tq_next = q_act;
+\tend
+end
+
+assign count_horizontal = q_act;
+
+//Instancias contadores de hora, fecha y timer
+
+contador_AD_SS_2dig Instancia_contador_SS//Segundos de la hora
+(
+.clk(clk),
+.reset(reset),
+.en_count(enable_counters),
+.enUP(enUP_reg),
+.enDOWN(enDOWN_reg),
+.data_SS(btn_data_SS)
+);
+
+contador_AD_MM_2dig Instancia_contador_MM//Minutos de la hora
+(
+.clk(clk),
+.reset(reset),
+.enUP(enUP_reg),
+.enDOWN(enDOWN_reg),
+.en_count(enable_counters),
+.data_MM(btn_data_MM)
+);
+
+contador_AD_HH_2dig Instancia_contador_HH//Horas de la hora
+(
+.clk(clk), 
+.reset(reset),
+.en_count(enable_counters),
+.enUP(enUP_reg),
+.enDOWN(enDOWN_reg),
+.data_HH(btn_data_HH)
+);   
+
+contador_AD_YEAR_2dig Instancia_contador_YEAR//A\xf1os de la fecha
+(
+.clk(clk),
+.reset(reset),
+.enUP(enUP_reg),
+.en_count(enable_counters),
+.enDOWN(enDOWN_reg),
+.data_YEAR(btn_data_YEAR)
+);
+
+contador_AD_MES_2dig Instancia_contador_MES//Meses de la fecha
+(
+.clk(clk),
+.reset(reset),
+.en_count(enable_counters),
+.enUP(enUP_reg),
+.enDOWN(enDOWN_reg),
+.data_MES(btn_data_MES)
+);
+
+contador_AD_DAY_2dig Instancia_contador_DAY//D\xeda de la fecha
+(
+.clk(clk),
+.reset(reset),
+.en_count(enable_counters),
+.enUP(enUP_reg),
+.enDOWN(enDOWN_reg),
+.data_DAY(btn_data_DAY)
+);
+
+contador_AD_SS_T_2dig Instancia_contador_SS_T//Segundos del timer
+(
+.clk(clk),
+.reset(reset),
+.en_count(enable_counters),
+.enUP(enUP_reg),
+.enDOWN(enDOWN_reg),
+.data_SS_T(btn_data_SS_T)
+);
+
+contador_AD_MM_T_2dig Instancia_contador_MM_T//Minutos del timer
+(
+.clk(clk),
+.reset(reset),
+.en_count(enable_counters),
+.enUP(enUP_reg),
+.enDOWN(enDOWN_reg),
+.data_MM_T(btn_data_MM_T)
+);
+
+contador_AD_HH_T_2dig Instancia_contador_HH_T //Horas del timer
+(
+.clk(clk),
+.reset(reset),
+.en_count(enable_counters),
+.enUP(enUP_reg),
+.enDOWN(enDOWN_reg),
+.data_HH_T(btn_data_HH_T)
+);
+
+//L\xf3gica de activaci\xf3n de cada contador dependiendo del modo configuraci\xf3n y la cuenta horizontal
+always@*
+
+\tcase(config_mode)//Eval\xfaa que se est\xe1 configurando (0: modo normal, 1: config.hora, 2: config.fecha, 3: config.timer)
+
+\t3'd0://Modo normal no habilita ning\xfan contador
+\tbegin
+\tenable_counters = 4'b0;
+\tend
+\t
+\t3'd1:
+\tbegin
+\t\tcase(count_horizontal)
+\t\t
+\t\t2'd0: enable_counters = 4'd1;//SS
+\t\t2'd1: enable_counters = 4'd2;//MM
+\t\t2'd2: enable_counters = 4'd3;//HH
+\t\tdefault: enable_counters = 4'd0;
+\t
+\t\tendcase
+\tend
+\t3'd2:
+\tbegin
+\t\tcase(count_horizontal)
+\t\t
+\t\t2'd0: enable_counters = 4'd4;//A\xf1o 
+\t\t2'd1: enable_counters = 4'd5;//Mes
+\t\t2'd2: enable_counters = 4'd6;//D\xeda
+\t\tdefault: enable_counters = 4'd0;
+\t\t
+\t\tendcase
+\tend
+\t3'd3:
+\tbegin
+\t\tcase(count_horizontal)
+\t\t
+\t\t2'd0: enable_counters = 4'd8;//SS_T
+\t\t2'd1: enable_counters = 4'd9;//MM_T
+\t\t2'd2: enable_counters = 4'd10;//HH_T
+\t\tdefault: enable_counters = 4'd0;
+\t\t
+\t\tendcase
+\tend
+\tdefault: enable_counters = 4'b0;
+\tendcase
+
+assign cursor_location = count_horizontal;
+endmodule
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    14:58:55 05/17/2016 
+// Design Name: 
+// Module Name:    escritor_lector_rtc 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module escritor_lector_rtc(
+\tinput clk,reset,
+\tinput [7:0]port_id,in_dato,
+\tinput write_strobe,read_strobe,
+\toutput reg_a_d,reg_cs,reg_rd,reg_wr,
+\toutput reg[7:0]out_dato,
+\toutput flag_done,
+\tinout [7:0]dato
+\t
+    );
+ 
+
+reg en_funcion;
+reg [7:0]addr_RAM,dato_escribir;
+wire [7:0]dato_leido;
+reg [7:0]next_out_dato;
+reg [7:0]reg_addr_RAM, reg_dato_escribir,reg_dato_leido;
+reg reg_escribir_leer,escribir_leer;
+wire direccion_dato;
+/// I/O Datos
+Driver_bus_bidireccional instance_driver_bus_bidireccional (
+    .in_flag_escritura(~reg_wr), 
+    .in_flag_lectura(~reg_rd), 
+    .in_direccion_dato(direccion_dato), 
+    .in_dato(dato_escribir), 
+    .out_reg_dato(dato_leido),  
+    .addr_RAM(addr_RAM), 
+    .dato(dato)
+    );
+
+//Generador de se\xf1ales de control
+signal_control_rtc_generator instance_signal_control_rtc_generator (
+    .clk(clk), 
+    .reset(reset), 
+    .in_escribir_leer(escribir_leer), 
+    .en_funcion(en_funcion), 
+    .reg_a_d(reg_a_d), 
+    .reg_cs(reg_cs), 
+    .reg_wr(reg_wr), 
+    .reg_rd(reg_rd), 
+    .out_direccion_dato(direccion_dato), 
+    .flag_done(flag_done)
+    );
+
+
+
+// logica secuencial
+always@(negedge clk , posedge reset) begin
+\tif (reset)begin
+\t\taddr_RAM <= 8'h0;
+\t\tdato_escribir <= 8'h0;
+\t\tescribir_leer <= 1'b0;
+\t\tout_dato <= 8'b0;
+\tend
+\telse begin
+\t\taddr_RAM <= reg_addr_RAM;
+\t\tdato_escribir <= reg_dato_escribir;
+\t\tescribir_leer <= reg_escribir_leer;
+\t\tout_dato <= next_out_dato;
+\t\t
+\tend
+end
+
+// logica combinacional para port_id
+always@* begin
+
+\tif (~reg_rd) next_out_dato = dato_leido;
+\tnext_out_dato = out_dato;
+\t
+\tif ( write_strobe == 1'b1 || read_strobe == 1'b1) begin
+\t// inicio de secuencia de lectura_escritura rtc
+\tif(port_id == 8'h0E) en_funcion = 1'b1;
+\telse en_funcion = 1'b0;
+\t
+\tcase (port_id)
+\t8'h00: begin //actualiza direccion
+\treg_addr_RAM = in_dato;
+\treg_dato_escribir = dato_escribir; 
+\treg_escribir_leer = escribir_leer;
+\tend
+\t8'h01: begin // actualiza dato
+\treg_dato_escribir = in_dato;
+\treg_addr_RAM = addr_RAM;
+\treg_escribir_leer = escribir_leer;
+\tend
+\t8'h0E: begin // inicia secuancia de rtc
+\treg_addr_RAM = addr_RAM;
+\treg_dato_escribir = dato_escribir;
+\treg_escribir_leer = in_dato[0];
+\tend
+\tdefault: begin
+\treg_addr_RAM = addr_RAM;
+\treg_dato_escribir = dato_escribir;
+\treg_escribir_leer = escribir_leer;
+\tend
+\tendcase\t
+\tend
+\t
+\telse begin
+\treg_addr_RAM = addr_RAM;
+\treg_dato_escribir = dato_escribir;
+\treg_escribir_leer = escribir_leer;
+\ten_funcion = 1'b0;
+\tend
+\t
+end
+
+
+endmodule
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    00:30:48 04/12/2016 
+// Design Name: 
+// Module Name:    Registro_timer 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module Registro_timer(
+\t\tinput wire hold,
+\t\tinput wire [7:0]in_rtc_dato,
+\t\tinput wire [7:0]in_count_dato,
+\t\tinput wire clk, //system clock
+\t\tinput wire reset, //system reset
+\t\tinput wire chip_select, //Control data
+\t\toutput wire [7:0]out_dato_vga,
+\t\toutput wire [7:0]out_dato_rtc
+    );
+
+reg [7:0]reg_dato;
+reg [7:0]next_dato;
+//reg [7:0]dato_temp;
+
+//Secuencial
+always@(negedge clk, posedge reset)
+begin
+\tif(reset) reg_dato <= 0;
+\telse reg_dato <= next_dato;
+end
+
+//Combinacional
+always@*
+\tbegin
+\tif (~hold) begin
+\tcase(chip_select)
+\t1'b0: next_dato = in_rtc_dato;
+\t1'b1: next_dato = in_count_dato;
+\tendcase
+\tend
+\telse next_dato = reg_dato;
+\tend
+
+/////////////////////////////////////////////////
+
+assign out_dato_vga = reg_dato;
+assign out_dato_rtc = 8'h00;
+
+endmodule
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    15:18:15 04/12/2016 
+// Design Name: 
+// Module Name:    deco_hold_registros 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module deco_hold_registros(
+\tinput write_strobe,
+\tinput [7:0] port_id,
+\tinput [1:0] config_mode,
+\toutput reg hold_seg_hora,
+\toutput reg hold_min_hora,
+\toutput reg hold_hora_hora,
+\toutput reg hold_dia_fecha,
+\toutput reg hold_mes_fecha,
+\toutput reg hold_jahr_fecha,
+\toutput reg hold_seg_timer,
+\toutput reg hold_min_timer,
+\toutput reg hold_hora_timer,
+\toutput reg hold_banderas_config
+    );
+\t 
+always@*
+begin
+case(config_mode)
+
+2'b00://Modo normal
+\tif (write_strobe) begin
+\tcase(port_id)
+\t8'h03: begin
+\t\thold_seg_hora = 1'b0;
+\t\thold_min_hora= 1'b1;
+\t\thold_hora_hora= 1'b1;
+\t\thold_dia_fecha= 1'b1;
+\t\thold_mes_fecha= 1'b1;
+\t\thold_jahr_fecha= 1'b1;
+\t\thold_seg_timer= 1'b1;
+\t\thold_min_timer= 1'b1;
+\t\thold_hora_timer= 1'b1;
+\t\thold_banderas_config = 1'b1;
+\tend
+\t8'h04: begin
+\t\thold_seg_hora = 1'b1;
+\t\thold_min_hora= 1'b0;
+\t\thold_hora_hora= 1'b1;
+\t\thold_dia_fecha= 1'b1;
+\t\thold_mes_fecha= 1'b1;
+\t\thold_jahr_fecha= 1'b1;
+\t\thold_seg_timer= 1'b1;
+\t\thold_min_timer= 1'b1;
+\t\thold_hora_timer= 1'b1;
+\t\thold_banderas_config = 1'b1;
+\tend
+\t8'h05: begin
+\t\thold_seg_hora = 1'b1;
+\t\thold_min_hora= 1'b1;
+\t\thold_hora_hora= 1'b0;
+\t\thold_dia_fecha= 1'b1;
+\t\thold_mes_fecha= 1'b1;
+\t\thold_jahr_fecha= 1'b1;
+\t\thold_seg_timer= 1'b1;
+\t\thold_min_timer= 1'b1;
+\t\thold_hora_timer= 1'b1;
+\t\thold_banderas_config = 1'b1;
+\tend
+\t8'h06: begin
+\t\thold_seg_hora = 1'b1;
+\t\thold_min_hora= 1'b1;
+\t\thold_hora_hora= 1'b1;
+\t\thold_dia_fecha= 1'b0;
+\t\thold_mes_fecha= 1'b1;
+\t\thold_jahr_fecha= 1'b1;
+\t\thold_seg_timer= 1'b1;
+\t\thold_min_timer= 1'b1;
+\t\thold_hora_timer= 1'b1;
+\t\thold_banderas_config = 1'b1;
+\tend
+\t8'h07: begin
+\t\thold_seg_hora = 1'b1;
+\t\thold_min_hora= 1'b1;
+\t\thold_hora_hora= 1'b1;
+\t\thold_dia_fecha= 1'b1;
+\t\thold_mes_fecha= 1'b0;
+\t\thold_jahr_fecha= 1'b1;
+\t\thold_seg_timer= 1'b1;
+\t\thold_min_timer= 1'b1;
+\t\thold_hora_timer= 1'b1;
+\t\thold_banderas_config = 1'b1;
+\tend
+\t8'h08: begin
+\t\thold_seg_hora = 1'b1;
+\t\thold_min_hora= 1'b1;
+\t\thold_hora_hora= 1'b1;
+\t\thold_dia_fecha= 1'b1;
+\t\thold_mes_fecha= 1'b1;
+\t\thold_jahr_fecha= 1'b0;
+\t\thold_seg_timer= 1'b1;
+\t\thold_min_timer= 1'b1;
+\t\thold_hora_timer= 1'b1;
+\t\thold_banderas_config = 1'b1;
+\tend
+\t8'h0A: begin
+\t\thold_seg_hora = 1'b1;
+\t\thold_min_hora= 1'b1;
+\t\thold_hora_hora= 1'b1;
+\t\thold_dia_fecha= 1'b1;
+\t\thold_mes_fecha= 1'b1;
+\t\thold_jahr_fecha= 1'b1;
+\t\thold_seg_timer= 1'b0;
+\t\thold_min_timer= 1'b1;
+\t\thold_hora_timer= 1'b1;
+\t\thold_banderas_config = 1'b1;
+\tend
+\t8'h0B: begin
+\t\thold_seg_hora = 1'b1;
+\t\thold_min_hora= 1'b1;
+\t\thold_hora_hora= 1'b1;
+\t\thold_dia_fecha= 1'b1;
+\t\thold_mes_fecha= 1'b1;
+\t\thold_jahr_fecha= 1'b1;
+\t\thold_seg_timer= 1'b1;
+\t\thold_min_timer= 1'b0;
+\t\thold_hora_timer= 1'b1;
+\t\thold_banderas_config = 1'b1;
+\tend
+\t8'h0C: begin
+\t\thold_seg_hora = 1'b1;
+\t\thold_min_hora= 1'b1;
+\t\thold_hora_hora= 1'b1;
+\t\thold_dia_fecha= 1'b1;
+\t\thold_mes_fecha= 1'b1;
+\t\thold_jahr_fecha= 1'b1;
+\t\thold_seg_timer= 1'b1;
+\t\thold_min_timer= 1'b1;
+\t\thold_hora_timer= 1'b0;
+\t\thold_banderas_config = 1'b1;
+\tend
+\t8'h0D: begin
+\t\thold_seg_hora = 1'b1;
+\t\thold_min_hora= 1'b1;
+\t\thold_hora_hora= 1'b1;
+\t\thold_dia_fecha= 1'b1;
+\t\thold_mes_fecha= 1'b1;
+\t\thold_jahr_fecha= 1'b1;
+\t\thold_seg_timer= 1'b1;
+\t\thold_min_timer= 1'b1;
+\t\thold_hora_timer= 1'b1;
+\t\thold_banderas_config = 1'b0;
+\tend 
+\tdefault: begin
+\t\thold_seg_hora = 1'b1;
+\t\thold_min_hora= 1'b1;
+\t\thold_hora_hora= 1'b1;
+\t\thold_dia_fecha= 1'b1;
+\t\thold_mes_fecha= 1'b1;
+\t\thold_jahr_fecha= 1'b1;
+\t\thold_seg_timer= 1'b1;
+\t\thold_min_timer= 1'b1;
+\t\thold_hora_timer= 1'b0;
+\t\thold_banderas_config = 1'b1;
+\tend
+\tendcase
+\tend
+\t
+\telse begin
+\thold_seg_hora = 1'b1;
+\t\thold_min_hora= 1'b1;
+\t\thold_hora_hora= 1'b1;
+\t\thold_dia_fecha= 1'b1;
+\t\thold_mes_fecha= 1'b1;
+\t\thold_jahr_fecha= 1'b1;
+\t\thold_seg_timer= 1'b1;
+\t\thold_min_timer= 1'b1;
+\t\thold_hora_timer= 1'b1;
+\t\thold_banderas_config = 1'b1;
+\tend
+
+2'b01://Configura hora
+begin
+\thold_seg_hora = 1'b0;
+\thold_min_hora= 1'b0;
+\thold_hora_hora= 1'b0;
+\t
+\tif (write_strobe) begin
+\tcase(port_id)
+\t
+\t8'h06: begin
+\t\thold_dia_fecha= 1'b0;
+\t\thold_mes_fecha= 1'b1;
+\t\thold_jahr_fecha= 1'b1;
+\t\thold_seg_timer= 1'b1;
+\t\thold_min_timer= 1'b1;
+\t\thold_hora_timer= 1'b1;
+\t\thold_banderas_config = 1'b1;
+\tend
+\t8'h07: begin
+\t\thold_dia_fecha= 1'b1;
+\t\thold_mes_fecha= 1'b0;
+\t\thold_jahr_fecha= 1'b1;
+\t\thold_seg_timer= 1'b1;
+\t\thold_min_timer= 1'b1;
+\t\thold_hora_timer= 1'b1;
+\t\thold_banderas_config = 1'b1;
+\tend
+\t8'h08: begin
+\t\thold_dia_fecha= 1'b1;
+\t\thold_mes_fecha= 1'b1;
+\t\thold_jahr_fecha= 1'b0;
+\t\thold_seg_timer= 1'b1;
+\t\thold_min_timer= 1'b1;
+\t\thold_hora_timer= 1'b1;
+\t\thold_banderas_config = 1'b1;
+\tend
+\t8'h0A: begin
+\t\thold_dia_fecha= 1'b1;
+\t\thold_mes_fecha= 1'b1;
+\t\thold_jahr_fecha= 1'b1;
+\t\thold_seg_timer= 1'b0;
+\t\thold_min_timer= 1'b1;
+\t\thold_hora_timer= 1'b1;
+\t\thold_banderas_config = 1'b1;
+\tend
+\t8'h0B: begin
+\t\thold_dia_fecha= 1'b1;
+\t\thold_mes_fecha= 1'b1;
+\t\thold_jahr_fecha= 1'b1;
+\t\thold_seg_timer= 1'b1;
+\t\thold_min_timer= 1'b0;
+\t\thold_hora_timer= 1'b1;
+\t\thold_banderas_config = 1'b1;
+\tend
+\t8'h0C: begin
+\t\thold_dia_fecha= 1'b1;
+\t\thold_mes_fecha= 1'b1;
+\t\thold_jahr_fecha= 1'b1;
+\t\thold_seg_timer= 1'b1;
+\t\thold_min_timer= 1'b1;
+\t\thold_hora_timer= 1'b0;
+\t\thold_banderas_config = 1'b1;
+\tend
+\t8'h0D: begin
+\t\thold_dia_fecha= 1'b1;
+\t\thold_mes_fecha= 1'b1;
+\t\thold_jahr_fecha= 1'b1;
+\t\thold_seg_timer= 1'b1;
+\t\thold_min_timer= 1'b1;
+\t\thold_hora_timer= 1'b1;
+\t\thold_banderas_config = 1'b0;
+\tend 
+\tdefault: begin
+\t\thold_dia_fecha= 1'b1;
+\t\thold_mes_fecha= 1'b1;
+\t\thold_jahr_fecha= 1'b1;
+\t\thold_seg_timer= 1'b1;
+\t\thold_min_timer= 1'b1;
+\t\thold_hora_timer= 1'b1;
+\t\thold_banderas_config = 1'b1;
+\tend
+\tendcase
+\tend
+\t
+\telse begin
+\t\thold_dia_fecha= 1'b1;
+\t\thold_mes_fecha= 1'b1;
+\t\thold_jahr_fecha= 1'b1;
+\t\thold_seg_timer= 1'b1;
+\t\thold_min_timer= 1'b1;
+\t\thold_hora_timer= 1'b1;
+\t\thold_banderas_config = 1'b1;
+\tend
+end
+
+2'b10://Configura fecha
+begin
+\thold_dia_fecha= 1'b0;
+\thold_mes_fecha= 1'b0;
+\thold_jahr_fecha= 1'b0;
+\t
+\tif (write_strobe) begin
+\tcase(port_id)
+\t8'h03:begin
+\t\thold_seg_hora = 1'b0;
+\t\thold_min_hora= 1'b1;
+\t\thold_hora_hora= 1'b1;
+\t\thold_seg_timer= 1'b1;
+\t\thold_min_timer= 1'b1;
+\t\thold_hora_timer= 1'b1;
+\t\thold_banderas_config = 1'b1;
+\tend
+\t8'h04:begin
+\t\thold_seg_hora = 1'b1;
+\t\thold_min_hora= 1'b0;
+\t\thold_hora_hora= 1'b1;
+\t\thold_seg_timer= 1'b1;
+\t\thold_min_timer= 1'b1;
+\t\thold_hora_timer= 1'b1;
+\t\thold_banderas_config = 1'b1;
+\tend
+\t8'h05:begin
+\t\thold_seg_hora = 1'b1;
+\t\thold_min_hora= 1'b1;
+\t\thold_hora_hora= 1'b0;
+\t\thold_seg_timer= 1'b1;
+\t\thold_min_timer= 1'b1;
+\t\thold_hora_timer= 1'b1;
+\t\thold_banderas_config = 1'b1;
+\tend
+\t8'h0A: begin
+\t\thold_seg_hora = 1'b1;
+\t\thold_min_hora= 1'b1;
+\t\thold_hora_hora= 1'b1;
+\t\thold_seg_timer= 1'b0;
+\t\thold_min_timer= 1'b1;
+\t\thold_hora_timer= 1'b1;
+\t\thold_banderas_config = 1'b1;
+\tend
+\t8'h0B: begin
+\t\thold_seg_hora = 1'b1;
+\t\thold_min_hora= 1'b1;
+\t\thold_hora_hora= 1'b1;
+\t\thold_seg_timer= 1'b1;
+\t\thold_min_timer= 1'b0;
+\t\thold_hora_timer= 1'b1;
+\t\thold_banderas_config = 1'b1;
+\tend
+\t8'h0C: begin
+\t\thold_seg_hora = 1'b1;
+\t\thold_min_hora= 1'b1;
+\t\thold_hora_hora= 1'b1;
+\t\thold_seg_timer= 1'b1;
+\t\thold_min_timer= 1'b1;
+\t\thold_hora_timer= 1'b0;
+\t\thold_banderas_config = 1'b1;
+\tend
+\t8'h0D: begin
+\t\thold_seg_hora = 1'b1;
+\t\thold_min_hora= 1'b1;
+\t\thold_hora_hora= 1'b1;
+\t\thold_seg_timer= 1'b1;
+\t\thold_min_timer= 1'b1;
+\t\thold_hora_timer= 1'b1;
+\t\thold_banderas_config = 1'b0;
+\tend\t
+\tdefault: begin
+\t\thold_seg_hora = 1'b1;
+\t\thold_min_hora= 1'b1;
+\t\thold_hora_hora= 1'b1;
+\t\thold_seg_timer= 1'b1;
+\t\thold_min_timer= 1'b1;
+\t\thold_hora_timer= 1'b1;
+\t\thold_banderas_config = 1'b1;
+\tend
+\tendcase
+\tend
+\t
+\telse begin
+\t\thold_seg_hora = 1'b1;
+\t\thold_min_hora= 1'b1;
+\t\thold_hora_hora= 1'b1;
+\t\thold_seg_timer= 1'b1;
+\t\thold_min_timer= 1'b1;
+\t\thold_hora_timer= 1'b1;
+\t\thold_banderas_config = 1'b1;
+\tend
+end
+
+2'b11://Configura timer
+begin
+\thold_seg_timer= 1'b0;
+\thold_min_timer= 1'b0;
+\thold_hora_timer= 1'b0;\t
+
+\tif (write_strobe) begin
+\tcase(port_id)
+\t8'h03: begin
+\t\thold_seg_hora = 1'b0;
+\t\thold_min_hora= 1'b1;
+\t\thold_hora_hora= 1'b1;
+\t\thold_dia_fecha= 1'b1;
+\t\thold_mes_fecha= 1'b1;
+\t\thold_jahr_fecha= 1'b1;
+\t\thold_banderas_config = 1'b1;
+\tend
+\t8'h04: begin
+\t\thold_seg_hora = 1'b1;
+\t\thold_min_hora= 1'b0;
+\t\thold_hora_hora= 1'b1;
+\t\thold_dia_fecha= 1'b1;
+\t\thold_mes_fecha= 1'b1;
+\t\thold_jahr_fecha= 1'b1;
+\t\thold_banderas_config = 1'b1;
+\tend
+\t8'h05: begin
+\t\thold_seg_hora = 1'b1;
+\t\thold_min_hora= 1'b1;
+\t\thold_hora_hora= 1'b0;
+\t\thold_dia_fecha= 1'b1;
+\t\thold_mes_fecha= 1'b1;
+\t\thold_jahr_fecha= 1'b1;
+\t\thold_banderas_config = 1'b1;
+\tend
+\t8'h06: begin
+\t\thold_seg_hora = 1'b1;
+\t\thold_min_hora= 1'b1;
+\t\thold_hora_hora= 1'b1;
+\t\thold_dia_fecha= 1'b0;
+\t\thold_mes_fecha= 1'b1;
+\t\thold_jahr_fecha= 1'b1;
+\t\thold_banderas_config = 1'b1;
+\tend
+\t8'h07: begin
+\t\thold_seg_hora = 1'b1;
+\t\thold_min_hora= 1'b1;
+\t\thold_hora_hora= 1'b1;
+\t\thold_dia_fecha= 1'b1;
+\t\thold_mes_fecha= 1'b0;
+\t\thold_jahr_fecha= 1'b1;
+\t\thold_banderas_config = 1'b1;
+\tend
+\t8'h08: begin
+\t\thold_seg_hora = 1'b1;
+\t\thold_min_hora= 1'b1;
+\t\thold_hora_hora= 1'b1;
+\t\thold_dia_fecha= 1'b1;
+\t\thold_mes_fecha= 1'b1;
+\t\thold_jahr_fecha= 1'b0;
+\t\thold_banderas_config = 1'b1;
+\tend
+\t8'h0D: begin
+\t\thold_seg_hora = 1'b1;
+\t\thold_min_hora= 1'b1;
+\t\thold_hora_hora= 1'b1;
+\t\thold_dia_fecha= 1'b1;
+\t\thold_mes_fecha= 1'b1;
+\t\thold_jahr_fecha= 1'b1;
+\t\thold_banderas_config = 1'b0;
+\tend
+\tdefault: begin
+\t\thold_seg_hora = 1'b1;
+\t\thold_min_hora= 1'b1;
+\t\thold_hora_hora= 1'b1;
+\t\thold_dia_fecha= 1'b1;
+\t\thold_mes_fecha= 1'b1;
+\t\thold_jahr_fecha= 1'b1;
+\t\thold_banderas_config = 1'b1;
+\tend
+\tendcase
+\tend
+\t
+\telse begin
+\t\thold_seg_hora = 1'b1;
+\t\thold_min_hora= 1'b1;
+\t\thold_hora_hora= 1'b1;
+\t\thold_dia_fecha= 1'b1;
+\t\thold_mes_fecha= 1'b1;
+\t\thold_jahr_fecha= 1'b1;
+\t\thold_banderas_config = 1'b1;
+\tend
+end
+default: begin
+\t\thold_seg_hora = 1'b0;
+\t\thold_min_hora= 1'b0;
+\t\thold_hora_hora= 1'b0;
+\t\thold_dia_fecha= 1'b0;
+\t\thold_mes_fecha= 1'b0;
+\t\thold_jahr_fecha= 1'b0;
+\t\thold_seg_timer = 1'b0;
+\t\thold_min_timer = 1'b0;
+\t\thold_hora_timer = 1'b0;
+end
+endcase
+end
+endmodule
+
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    15:02:11 05/12/2016 
+// Design Name: 
+// Module Name:    fifo 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module fifo
+#(
+ parameter B=8, // number of bits in a word
+\t\t\t  W=2  // number of address bits
+)
+(
+ input wire clk, reset,
+ input wire rd, wr,
+ input wire [B-1:0] w_data,
+ output wire empty, full,
+ output wire [B-1:0] r_data
+);
+
+//signal declaration
+reg [B-1:0] array_reg [2**W-1:0];  // register array
+reg [W-1:0] w_ptr_reg, w_ptr_next, w_ptr_succ;
+reg [W-1:0] r_ptr_reg, r_ptr_next, r_ptr_succ;
+reg full_reg, empty_reg, full_next, empty_next;
+wire wr_en;
+
+// body
+// register file write operation
+always @(posedge clk)
+\tif (wr_en)
+\t\tarray_reg[w_ptr_reg] <= w_data;
+// register file read operation
+assign r_data = array_reg[r_ptr_reg];
+// write enabled only when FIFO is not full
+assign wr_en = wr & ~full_reg;
+
+// fifo control logic
+// register for read and write pointers
+always @(posedge clk, posedge reset)
+\tif (reset)
+\t\tbegin
+\t\t\tw_ptr_reg <= 0;
+\t\t\tr_ptr_reg <= 0;
+\t\t\tfull_reg <= 1'b0;
+\t\t\tempty_reg <= 1'b1;
+\t\tend
+\telse
+\t\tbegin
+\t\t\tw_ptr_reg <= w_ptr_next;
+\t\t\tr_ptr_reg <= r_ptr_next;
+\t\t\tfull_reg <= full_next;
+\t\t\tempty_reg <= empty_next;
+\t\tend
+
+// next-state logic for read and write pointers
+always @*
+begin
+\t// successive pointer values
+\tw_ptr_succ = w_ptr_reg + 1'b1;
+\tr_ptr_succ = r_ptr_reg + 1'b1;
+\t// default: keep old values
+\tw_ptr_next = w_ptr_reg;
+\tr_ptr_next = r_ptr_reg;
+\tfull_next = full_reg;
+\tempty_next = empty_reg;
+\tcase ({wr, rd})
+\t\t// 2'b00:  no op
+\t\t2'b01: // read
+\t\t\tif (~empty_reg) // not empty
+\t\t\t\tbegin
+\t\t\t\t\tr_ptr_next = r_ptr_succ;
+\t\t\t\t\tfull_next = 1'b0;
+\t\t\t\t\tif (r_ptr_succ==w_ptr_reg)
+\t\t\t\t\t\tempty_next = 1'b1;
+\t\t\t\tend
+\t\t2'b10: // write
+\t\t\tif (~full_reg) // not full
+\t\t\t\tbegin
+\t\t\t\t\tw_ptr_next = w_ptr_succ;
+\t\t\t\t\tempty_next = 1'b0;
+\t\t\t\t\tif (w_ptr_succ==r_ptr_reg)
+\t\t\t\t\t\tfull_next = 1'b1;
+\t\t\t\tend
+\t\t2'b11: // write and read
+\t\t\tbegin
+\t\t\t\tw_ptr_next = w_ptr_succ;
+\t\t\t\tr_ptr_next = r_ptr_succ;
+\t\t\tend
+\tendcase
+end
+
+// output
+assign full = full_reg;
+assign empty = empty_reg;
+
+endmodule
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: Jafet Chaves Barrantes
+// 
+// Create Date:    15:45:17 04/03/2016 
+// Design Name: 
+// Module Name:    contador_AD_YEAR_2dig 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module contador_AD_YEAR_2dig
+(
+input wire clk,
+input wire reset,
+input wire [3:0] en_count,
+input wire enUP,
+input wire enDOWN,
+output wire [7:0] data_YEAR
+);
+
+localparam N = 7; // Para definir el n\xfamero de bits del contador (hasta 99->7 bits)
+//Declaraci\xf3n de se\xf1ales
+reg [N-1:0] q_act, q_next;
+wire [N-1:0] count_data;
+reg [3:0] digit1, digit0;
+
+//Descripci\xf3n del comportamiento
+always@(posedge clk, posedge reset)
+begin\t
+\t
+\tif(reset)
+\tbegin
+\t\tq_act <= 7'b0;
+\tend
+\t
+\telse
+\tbegin
+\t\tq_act <= q_next;
+\tend
+end
+
+
+//L\xf3gica de salida
+
+always@*
+begin
+
+\tif (en_count == 4)
+\tbegin
+\t\tif (enUP)
+\t\tbegin
+\t\t\tif (q_act >= 7'd99) q_next = 7'd0;
+\t\t\telse q_next = q_act + 7'd1;
+\t\tend
+\t\t
+\t\telse if (enDOWN)
+\t\tbegin
+\t\t\tif (q_act == 7'd0) q_next = 7'd99;
+\t\t\telse q_next = q_act - 7'd1;
+\t\tend
+\t\telse q_next = q_act;
+\tend
+\telse q_next = q_act;
+\t
+end
+
+assign count_data = q_act;
+
+//Decodificaci\xf3n BCD (2 d\xedgitos)
+
+always@*
+begin
+case(count_data)
+7'd0: begin digit1 = 4'b0000; digit0 = 4'b0000; end
+7'd1: begin digit1 = 4'b0000; digit0 = 4'b0001; end
+7'd2: begin digit1 = 4'b0000; digit0 = 4'b0010; end
+7'd3: begin digit1 = 4'b0000; digit0 = 4'b0011; end
+7'd4: begin digit1 = 4'b0000; digit0 = 4'b0100; end
+7'd5: begin digit1 = 4'b0000; digit0 = 4'b0101; end
+7'd6: begin digit1 = 4'b0000; digit0 = 4'b0110; end
+7'd7: begin digit1 = 4'b0000; digit0 = 4'b0111; end
+7'd8: begin digit1 = 4'b0000; digit0 = 4'b1000; end
+7'd9: begin digit1 = 4'b0000; digit0 = 4'b1001; end
+
+7'd10: begin digit1 = 4'b0001; digit0 = 4'b0000; end
+7'd11: begin digit1 = 4'b0001; digit0 = 4'b0001; end
+7'd12: begin digit1 = 4'b0001; digit0 = 4'b0010; end
+7'd13: begin digit1 = 4'b0001; digit0 = 4'b0011; end
+7'd14: begin digit1 = 4'b0001; digit0 = 4'b0100; end
+7'd15: begin digit1 = 4'b0001; digit0 = 4'b0101; end
+7'd16: begin digit1 = 4'b0001; digit0 = 4'b0110; end
+7'd17: begin digit1 = 4'b0001; digit0 = 4'b0111; end
+7'd18: begin digit1 = 4'b0001; digit0 = 4'b1000; end
+7'd19: begin digit1 = 4'b0001; digit0 = 4'b1001; end
+
+7'd20: begin digit1 = 4'b0010; digit0 = 4'b0000; end
+7'd21: begin digit1 = 4'b0010; digit0 = 4'b0001; end
+7'd22: begin digit1 = 4'b0010; digit0 = 4'b0010; end
+7'd23: begin digit1 = 4'b0010; digit0 = 4'b0011; end
+7'd24: begin digit1 = 4'b0010; digit0 = 4'b0100; end
+7'd25: begin digit1 = 4'b0010; digit0 = 4'b0101; end
+7'd26: begin digit1 = 4'b0010; digit0 = 4'b0110; end
+7'd27: begin digit1 = 4'b0010; digit0 = 4'b0111; end
+7'd28: begin digit1 = 4'b0010; digit0 = 4'b1000; end
+7'd29: begin digit1 = 4'b0010; digit0 = 4'b1001; end
+
+7'd30: begin digit1 = 4'b0011; digit0 = 4'b0000; end
+7'd31: begin digit1 = 4'b0011; digit0 = 4'b0001; end
+7'd32: begin digit1 = 4'b0011; digit0 = 4'b0010; end
+7'd33: begin digit1 = 4'b0011; digit0 = 4'b0011; end
+7'd34: begin digit1 = 4'b0011; digit0 = 4'b0100; end
+7'd35: begin digit1 = 4'b0011; digit0 = 4'b0101; end
+7'd36: begin digit1 = 4'b0011; digit0 = 4'b0110; end
+7'd37: begin digit1 = 4'b0011; digit0 = 4'b0111; end
+7'd38: begin digit1 = 4'b0011; digit0 = 4'b1000; end
+7'd39: begin digit1 = 4'b0011; digit0 = 4'b1001; end
+
+7'd40: begin digit1 = 4'b0100; digit0 = 4'b0000; end
+7'd41: begin digit1 = 4'b0100; digit0 = 4'b0001; end
+7'd42: begin digit1 = 4'b0100; digit0 = 4'b0010; end
+7'd43: begin digit1 = 4'b0100; digit0 = 4'b0011; end
+7'd44: begin digit1 = 4'b0100; digit0 = 4'b0100; end
+7'd45: begin digit1 = 4'b0100; digit0 = 4'b0101; end
+7'd46: begin digit1 = 4'b0100; digit0 = 4'b0110; end
+7'd47: begin digit1 = 4'b0100; digit0 = 4'b0111; end
+7'd48: begin digit1 = 4'b0100; digit0 = 4'b1000; end
+7'd49: begin digit1 = 4'b0100; digit0 = 4'b1001; end
+
+7'd50: begin digit1 = 4'b0101; digit0 = 4'b0000; end
+7'd51: begin digit1 = 4'b0101; digit0 = 4'b0001; end
+7'd52: begin digit1 = 4'b0101; digit0 = 4'b0010; end
+7'd53: begin digit1 = 4'b0101; digit0 = 4'b0011; end
+7'd54: begin digit1 = 4'b0101; digit0 = 4'b0100; end
+7'd55: begin digit1 = 4'b0101; digit0 = 4'b0101; end
+7'd56: begin digit1 = 4'b0101; digit0 = 4'b0110; end
+7'd57: begin digit1 = 4'b0101; digit0 = 4'b0111; end
+7'd58: begin digit1 = 4'b0101; digit0 = 4'b1000; end
+7'd59: begin digit1 = 4'b0101; digit0 = 4'b1001; end
+
+7'd60: begin digit1 = 4'b0110; digit0 = 4'b0000; end
+7'd61: begin digit1 = 4'b0110; digit0 = 4'b0001; end
+7'd62: begin digit1 = 4'b0110; digit0 = 4'b0010; end
+7'd63: begin digit1 = 4'b0110; digit0 = 4'b0011; end
+7'd64: begin digit1 = 4'b0110; digit0 = 4'b0100; end
+7'd65: begin digit1 = 4'b0110; digit0 = 4'b0101; end
+7'd66: begin digit1 = 4'b0110; digit0 = 4'b0110; end
+7'd67: begin digit1 = 4'b0110; digit0 = 4'b0111; end
+7'd68: begin digit1 = 4'b0110; digit0 = 4'b1000; end
+7'd69: begin digit1 = 4'b0110; digit0 = 4'b1001; end
+
+7'd70: begin digit1 = 4'b0111; digit0 = 4'b0000; end
+7'd71: begin digit1 = 4'b0111; digit0 = 4'b0001; end
+7'd72: begin digit1 = 4'b0111; digit0 = 4'b0010; end
+7'd73: begin digit1 = 4'b0111; digit0 = 4'b0011; end
+7'd74: begin digit1 = 4'b0111; digit0 = 4'b0100; end
+7'd75: begin digit1 = 4'b0111; digit0 = 4'b0101; end
+7'd76: begin digit1 = 4'b0111; digit0 = 4'b0110; end
+7'd77: begin digit1 = 4'b0111; digit0 = 4'b0111; end
+7'd78: begin digit1 = 4'b0111; digit0 = 4'b1000; end
+7'd79: begin digit1 = 4'b0111; digit0 = 4'b1001; end
+
+7'd80: begin digit1 = 4'b1000; digit0 = 4'b0000; end
+7'd81: begin digit1 = 4'b1000; digit0 = 4'b0001; end
+7'd82: begin digit1 = 4'b1000; digit0 = 4'b0010; end
+7'd83: begin digit1 = 4'b1000; digit0 = 4'b0011; end
+7'd84: begin digit1 = 4'b1000; digit0 = 4'b0100; end
+7'd85: begin digit1 = 4'b1000; digit0 = 4'b0101; end
+7'd86: begin digit1 = 4'b1000; digit0 = 4'b0110; end
+7'd87: begin digit1 = 4'b1000; digit0 = 4'b0111; end
+7'd88: begin digit1 = 4'b1000; digit0 = 4'b1000; end
+7'd89: begin digit1 = 4'b1000; digit0 = 4'b1001; end
+
+7'd90: begin digit1 = 4'b1001; digit0 = 4'b0000; end
+7'd91: begin digit1 = 4'b1001; digit0 = 4'b0001; end
+7'd92: begin digit1 = 4'b1001; digit0 = 4'b0010; end
+7'd93: begin digit1 = 4'b1001; digit0 = 4'b0011; end
+7'd94: begin digit1 = 4'b1001; digit0 = 4'b0100; end
+7'd95: begin digit1 = 4'b1001; digit0 = 4'b0101; end
+7'd96: begin digit1 = 4'b1001; digit0 = 4'b0110; end
+7'd97: begin digit1 = 4'b1001; digit0 = 4'b0111; end
+7'd98: begin digit1 = 4'b1001; digit0 = 4'b1000; end
+7'd99: begin digit1 = 4'b1001; digit0 = 4'b1001; end
+
+default:  begin digit1 = 0; digit0 = 0; end
+endcase
+end
+
+assign data_YEAR = {digit1,digit0};
+
+endmodule
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: Yermy Benavides Solano
+// 
+// Create Date:    22:59:01 05/16/2016 
+// Design Name: 
+// Module Name:    signal_control_rtc_generator 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module signal_control_rtc_generator(
+\tinput wire clk,
+\tinput wire reset,
+\tinput wire in_escribir_leer,
+\tinput wire en_funcion,
+\toutput reg reg_a_d, //Senales de control RTC
+\toutput reg reg_cs,
+\toutput reg reg_wr,
+\toutput reg reg_rd,
+\toutput reg out_direccion_dato,
+\toutput wire flag_done
+\t  
+    ); 
+/////parametros de estado
+localparam
+espera = 1'b1,
+leer_escribir = 1'b0;
+\t 
+// Bits del contador para generar una se\xf1al peri\xf3dica de (2^N)*10ns
+localparam N = 5;
+
+
+// Declaraci\xf3n de se\xf1ales
+reg [N-1:0] q_reg;
+reg [N-1:0] q_next;
+reg state_reg, state_next;
+reg reset_count;
+
+//Descripci\xf3n del comportamiento
+
+//=============================================
+// Contador para generar un pulso de(2^N)*10ns
+//=============================================
+always @(posedge clk, posedge reset_count)
+begin
+    if (reset_count) q_reg <= 0;
+\t else  q_reg <= q_next;\t 
+end
+always@*
+begin
+q_next <= q_reg + 1'b1;
+end
+
+
+
+// Pulso de salida
+assign flag_done = (q_reg == 23) ? 1'b1 : 1'b0;//Tbandera fin de proseso
+
+ 
+///logica secuencial
+always @(posedge clk, posedge reset)
+begin
+  if (reset)
+     state_reg <= espera;
+  else
+     state_reg <= state_next;
+end
+
+// L\xf3gica de estado siguiente y salida
+  always@*
+   begin
+\tstate_next = state_reg;  // default state: the same
+\tcase(state_reg)
+\tespera:
+\t
+\t\tbegin
+\t\t\treg_a_d = 1'b1;
+\t\t\treg_cs = 1'b1;
+\t\t\treg_wr = 1'b1;
+\t\t\treg_rd = 1'b1;
+\t\t\tout_direccion_dato = 1'b0;
+\t\t\treset_count = 1'b1;
+\t\t\tif(en_funcion) state_next = leer_escribir;
+\t\t\telse state_next = espera;
+\t\tend
+\t\t
+\tleer_escribir:
+\tbegin
+\treset_count = 1'b0;
+\t//Proseso de lectura_escritura\t
+\tcase(q_reg)
+\t\t5'd0: begin //inicia 
+\t\t\treg_a_d = 1'b1;
+\t\t\treg_cs = 1'b1;
+\t\t\treg_rd = 1'b1;
+\t\t\treg_wr = 1'b1;
+\t\t\tout_direccion_dato = 1'b0;
+\t\tend 
+\t\t5'd1: begin // baja salida a_d
+\t\t\treg_a_d = 1'b0;
+\t\t\treg_cs = 1'b1;
+\t\t\treg_wr = 1'b1;
+\t\t\treg_rd = 1'b1;
+\t\t\tout_direccion_dato = 1'b0;
+\t\tend
+\t\t
+\t\t5'd2: begin// baja cs con wr o rd incio de manipulacion del bis de datos
+\t\t\treg_a_d = 1'b0;
+\t\t\treg_cs = 1'b0;
+\t\t\treg_wr = 1'b0;
+\t\t\treg_rd = 1'b1;
+\t\t\tout_direccion_dato = 1'b0;
+\t\t\tend
+\t\t5'd3: begin
+\t\t\treg_a_d = 1'b0;
+\t\t\treg_cs = 1'b0;
+\t\t\treg_wr = 1'b0;
+\t\t\treg_rd = 1'b1;
+\t\t\tout_direccion_dato = 1'b0;
+\t\tend
+\t\t5'd4: begin
+\t\t\treg_a_d = 1'b0;
+\t\t\treg_cs = 1'b0;
+\t\t\treg_wr = 1'b0;
+\t\t\treg_rd = 1'b1;
+\t\t\tout_direccion_dato = 1'b0;
+\t\t\tend
+\t\t5'd5: begin
+\t\t\treg_a_d = 1'b0;
+\t\t\treg_cs = 1'b0;
+\t\t\treg_wr = 1'b0;
+\t\t\treg_rd = 1'b1;
+\t\t\tout_direccion_dato = 1'b0;
+\t\t\tend
+\t\t5'd6: begin
+\t\t\treg_a_d = 1'b0;
+\t\t\treg_cs = 1'b0;
+\t\t\treg_wr = 1'b0;
+\t\t\treg_rd = 1'b1;
+\t\t\tout_direccion_dato = 1'b0;
+\t\tend
+\t\t5'd7: begin
+\t\t\treg_a_d = 1'b0;
+\t\t\treg_cs = 1'b0;
+\t\t\treg_wr = 1'b0;
+\t\t\treg_rd = 1'b1;
+\t\t\tout_direccion_dato = 1'b0;
+\t\tend
+\t\t
+\t\t5'd8: begin
+\t\t\treg_a_d = 1'b0;
+\t\t\treg_cs = 1'b0;
+\t\t\treg_wr = 1'b0;
+\t\t\treg_rd = 1'b1;
+\t\t\tout_direccion_dato = 1'b0;
+\t\t\tend
+\t\t\t
+\t\t5'd9:begin 
+\t\t\treg_a_d = 1'b0;
+\t\t\treg_cs = 1'b1;
+\t\t\treg_wr = 1'b1;
+\t\t\treg_rd = 1'b1;
+\t\t\tout_direccion_dato = 1'b0;
+\t\tend
+\t\t5'd10: begin
+\t\t\treg_a_d = 1'b1;
+\t\t\treg_cs = 1'b1;
+\t\t\treg_wr = 1'b1;
+\t\t\treg_rd = 1'b1;
+\t\t\tout_direccion_dato = 1'b0;
+\t\tend
+\t\t5'd11: begin
+\t\t\treg_a_d = 1'b1;
+\t\t\treg_cs = 1'b1;
+\t\t\treg_wr = 1'b1;
+\t\t\treg_rd = 1'b1;
+\t\t\tout_direccion_dato = 1'b0;
+\t\tend
+\t\t5'd12: begin
+\t\t\treg_a_d = 1'b1;
+\t\t\treg_cs = 1'b1;
+\t\t\treg_wr = 1'b1;
+\t\t\treg_rd = 1'b1;
+\t\t\tout_direccion_dato = 1'b0;
+\t\tend
+\t\t5'd13: begin
+\t\t\treg_a_d = 1'b1;
+\t\t\treg_cs = 1'b1;
+\t\t\treg_wr = 1'b1;
+\t\t\treg_rd = 1'b1;
+\t\t\tout_direccion_dato = 1'b0;
+\t\t\tend
+\t\t5'd14: begin
+\t\t\treg_a_d = 1'b1;
+\t\t\treg_cs = 1'b1;
+\t\t\treg_wr = 1'b1;
+\t\t\treg_rd = 1'b1;
+\t\t\tout_direccion_dato = 1'b0;
+\t\tend
+\t\t5'd15: begin
+\t\t\treg_a_d = 1'b1;
+\t\t\tout_direccion_dato = 1'b1;
+\t\t\tif (in_escribir_leer)begin
+\t\t\treg_cs = 1'b0;
+\t\t\treg_wr = 1'b0;
+\t\t\treg_rd = 1'b1;
+\t\t\tend
+\t\t\telse begin
+\t\t\treg_cs = 1'b0;
+\t\t\treg_wr = 1'b1;
+\t\t\treg_rd = 1'b0;
+\t\tend
+\t\tend
+\t\t5'd16:begin
+\t\t\treg_a_d = 1'b1;
+\t\t\tout_direccion_dato = 1'b1;
+\t\t\tif (in_escribir_leer)begin
+\t\t\treg_cs = 1'b0;
+\t\t\treg_wr = 1'b0;
+\t\t\treg_rd = 1'b1;
+\t\t\tend
+\t\t\telse begin
+\t\t\treg_cs = 1'b0;
+\t\t\treg_wr = 1'b1;
+\t\t\treg_rd = 1'b0;
+\t\tend
+\t\tend
+\t\t5'd17:begin
+\t\t\treg_a_d = 1'b1;
+\t\t\tout_direccion_dato = 1'b1;
+\t\t\tif (in_escribir_leer)begin
+\t\t\treg_cs = 1'b0;
+\t\t\treg_wr = 1'b0;
+\t\t\treg_rd = 1'b1;
+\t\t\tend
+\t\t\telse begin
+\t\t\treg_cs = 1'b0;
+\t\t\treg_wr = 1'b1;
+\t\t\treg_rd = 1'b0;
+\t\t\tend
+\t\tend
+\t\t5'd18:begin
+\t\t\treg_a_d = 1'b1;
+\t\t\tout_direccion_dato = 1'b1;
+\t\t\tif (in_escribir_leer)begin
+\t\t\treg_cs = 1'b0;
+\t\t\treg_wr = 1'b0;
+\t\t\treg_rd = 1'b1;
+\t\t\tend
+\t\t\telse begin
+\t\t\treg_cs = 1'b0;
+\t\t\treg_wr = 1'b1;
+\t\t\treg_rd = 1'b0;
+\t\t\tend
+\t\tend
+\t\t5'd19: begin
+\t\t\treg_a_d = 1'b1;
+\t\t\tout_direccion_dato = 1'b1;
+\t\t\tif (in_escribir_leer)begin
+\t\t\treg_cs = 1'b0;
+\t\t\treg_wr = 1'b0;
+\t\t\treg_rd = 1'b1;
+\t\t\tend
+\t\t\telse begin
+\t\t\treg_cs = 1'b0;
+\t\t\treg_wr = 1'b1;
+\t\t\treg_rd = 1'b0;
+\t\tend
+\t\tend
+\t\t5'd20: begin
+\t\t\treg_a_d = 1'b1;
+\t\t\tout_direccion_dato = 1'b1;
+\t\t\tif (in_escribir_leer)begin
+\t\t\treg_cs = 1'b0;
+\t\t\treg_wr = 1'b0;
+\t\t\treg_rd = 1'b1;
+\t\t\tend
+\t\t\telse begin
+\t\t\treg_cs = 1'b0;
+\t\t\treg_wr = 1'b1;
+\t\t\treg_rd = 1'b0;
+\t\tend
+\t\tend
+\t\t5'd21: begin
+\t\t\treg_a_d = 1'b1;
+\t\t\tout_direccion_dato = 1'b1;
+\t\t\tif (in_escribir_leer)begin
+\t\t\treg_cs = 1'b0;
+\t\t\treg_wr = 1'b0;
+\t\t\treg_rd = 1'b1;
+\t\t\tend
+\t\t\telse begin
+\t\t\treg_cs = 1'b0;
+\t\t\treg_wr = 1'b1;
+\t\t\treg_rd = 1'b0;
+\t\tend end
+\t\t
+\t\t5'd22: begin reg_a_d = 1'b1;
+\t\t\treg_cs = 1'b1;
+\t\t\treg_wr = 1'b1;
+\t\t\treg_rd = 1'b1;
+\t\t\tout_direccion_dato = 1'b1;
+\t\t\tend
+\t\t5'd23:
+\t\tbegin reg_a_d = 1'b1;
+\t\t\treg_cs = 1'b1;
+\t\t\treg_wr = 1'b1;
+\t\t\treg_rd = 1'b1; 
+\t\t\tout_direccion_dato = 1'b0;
+\t\t\tstate_next = espera;
+\t\tend
+\t\t 
+\t\tdefault: begin 
+\t\tstate_next = leer_escribir;
+\t\treg_a_d = 1'b1;
+\t\treg_cs =  1'b1;
+\t\treg_rd =  1'b1;
+\t\treg_wr =  1'b1;
+\t\tout_direccion_dato =  1'b0;
+\t\tend 
+\t\tendcase\t 
+\tend
+\tdefault: begin
+\tstate_next = espera;
+\treg_cs = 1'd1;
+\treg_a_d = 1'd1;
+\treg_wr = 1'd1;
+\treg_rd = 1'd1;
+\tout_direccion_dato = 1'd0;
+\tend
+\tendcase
+\t
+   end
+
+
+
+endmodule
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    21:05:24 03/30/2016 
+// Design Name: 
+// Module Name:    Bloque_Top_pruebas 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+module Bloque_Top_pruebas
+(
+input clock_FPGA, reset,
+input [1:0]sw,
+output hsync, vsync,
+output [7:0]RGB
+);
+
+wire [3:0] digit0_HH, digit1_HH, digit0_MM, digit1_MM, digit0_SS, digit1_SS,//
+digit0_DAY, digit1_DAY, digit0_MES, digit1_MES, digit0_YEAR, digit1_YEAR,//
+digit0_HH_T, digit1_HH_T, digit0_MM_T, digit1_MM_T, digit0_SS_T, digit1_SS_T;
+
+wire AM_PM;
+wire [1:0] funcion;
+wire [1:0] cursor_location;
+wire timer_end;//bandera proveniente del RTC que indica la finalizaci\xf3n del tiempo del timer
+wire formato_hora;//Se\xf1al que indica si la hora esta en formato 12 hrs o 24 hrs (0->24 hrs)
+
+bloque_prueba_frames instancia_bloque_prueba_frames
+(
+.sw(sw),
+.digit0_HH(digit0_HH), .digit1_HH(digit1_HH), .digit0_MM(digit0_MM), .digit1_MM(digit1_MM), .digit0_SS(digit0_SS), .digit1_SS(digit1_SS),//
+.digit0_DAY(digit0_DAY), .digit1_DAY(digit1_DAY), .digit0_MES(digit0_MES), .digit1_MES(digit1_MES), .digit0_YEAR(digit0_YEAR), .digit1_YEAR(digit1_YEAR),//
+.digit0_HH_T(digit0_HH_T), .digit1_HH_T(digit1_HH_T), .digit0_MM_T(digit0_MM_T), .digit1_MM_T(digit1_MM_T), .digit0_SS_T(digit0_SS_T), .digit1_SS_T(digit1_SS_T),//Decenas y unidades para los n\xfameros en pantalla (18 inputs de 3 bits)
+.AM_PM(AM_PM),//Entrada para conocer si en la informaci\xf3n de hora se despliega AM o PM
+.funcion(funcion),//2-bits: cuatro estados del modo configuraci\xf3n
+.cursor_location(cursor_location),//Marca la posici\xf3n del cursor en modo configuraci\xf3n
+.timer_end(timer_end),//bandera proveniente del RTC que indica la finalizaci\xf3n del tiempo del timer
+.formato_hora(formato_hora)//Se\xf1al que indica si la hora esta en formato 12 hrs o 24 hrs (0->24 hrs)
+);
+
+controlador_VGA instancia_controlador_VGA
+(
+.clock(clock_FPGA), .reset(reset),
+.digit0_HH(digit0_HH), .digit1_HH(digit1_HH), .digit0_MM(digit0_MM), .digit1_MM(digit1_MM), .digit0_SS(digit0_SS), .digit1_SS(digit1_SS),//
+.digit0_DAY(digit0_DAY), .digit1_DAY(digit1_DAY), .digit0_MES(digit0_MES), .digit1_MES(digit1_MES), .digit0_YEAR(digit0_YEAR), .digit1_YEAR(digit1_YEAR),//
+.digit0_HH_T(digit0_HH_T), .digit1_HH_T(digit1_HH_T), .digit0_MM_T(digit0_MM_T), .digit1_MM_T(digit1_MM_T), .digit0_SS_T(digit0_SS_T), .digit1_SS_T(digit1_SS_T),//Decenas y unidades para los n\xfameros en pantalla (18 inputs de 3 bits)
+.AM_PM(AM_PM),//Entrada para conocer si en la informaci\xf3n de hora se despliega AM o PM
+.config_mode(funcion),//1-bit: OR de los tres estados del modo configuraci\xf3n
+.cursor_location(cursor_location),//Marca la posici\xf3n del cursor en modo configuraci\xf3n
+.formato_hora(formato_hora),//Se\xf1al que indica si la hora esta en formato 12 hrs o 24 hrs (0->24 hrs)
+.estado_alarma(timer_end),//bandera proveniente del RTC que indica la finalizaci\xf3n del tiempo del timer
+.hsync(hsync),.vsync(vsync),
+.RGB(RGB)
+);
+
+
+endmodule
+
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: Jafet Chaves Barrantes
+// 
+// Create Date:    21:28:51 04/04/2016 
+// Design Name: 
+// Module Name:    contador_AD_HH_2dig 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module contador_AD_HH_2dig
+(
+input wire clk, 
+input wire reset,
+input wire [3:0]en_count,
+input wire enUP,
+input wire enDOWN,
+output wire [7:0] data_HH//D\xedgitos BCD ya concatenados hacia los registros(8 bits)
+);                             
+
+
+localparam N = 5; // Para definir el n\xfamero de bits del contador (hasta 23->5 bits)
+//Declaraci\xf3n de se\xf1ales
+reg [N-1:0] q_act, q_next;
+wire [N-1:0] count_data;
+reg [3:0] digit1, digit0;
+
+//Descripci\xf3n del comportamiento
+always@(posedge clk, posedge reset)
+begin\t
+\t
+\tif(reset)
+\tbegin
+\t\tq_act <= 5'b0;
+\tend
+\t
+\telse
+\tbegin
+\t\tq_act <= q_next;
+\tend
+end
+
+
+//L\xf3gica de salida
+
+always@*
+begin
+
+\tif (en_count == 3)
+\tbegin
+\t\tif (enUP)
+\t\tbegin
+\t\t\tif (q_act >= 5'd23) q_next = 5'd0;
+\t\t\telse q_next = q_act + 5'd1;
+\t\tend
+\t\t
+\t\telse if (enDOWN)
+\t\tbegin
+\t\t\tif (q_act == 5'd0) q_next = 5'd23;
+\t\t\telse q_next = q_act - 5'd1;
+\t\tend
+\t\telse q_next = q_act;
+\tend
+\telse q_next = q_act;
+\t
+end
+
+assign count_data = q_act;
+
+//Decodificaci\xf3n BCD (2 d\xedgitos)
+
+always@*
+begin
+\tcase(count_data)
+\t\t5'd0: begin digit1 = 4'b0000; digit0 = 4'b0000; end
+\t\t5'd1: begin digit1 = 4'b0000; digit0 = 4'b0001; end
+\t\t5'd2: begin digit1 = 4'b0000; digit0 = 4'b0010; end
+\t\t5'd3: begin digit1 = 4'b0000; digit0 = 4'b0011; end
+\t\t5'd4: begin digit1 = 4'b0000; digit0 = 4'b0100; end
+\t\t5'd5: begin digit1 = 4'b0000; digit0 = 4'b0101; end
+\t\t5'd6: begin digit1 = 4'b0000; digit0 = 4'b0110; end
+\t\t5'd7: begin digit1 = 4'b0000; digit0 = 4'b0111; end
+\t\t5'd8: begin digit1 = 4'b0000; digit0 = 4'b1000; end
+\t\t5'd9: begin digit1 = 4'b0000; digit0 = 4'b1001; end
+
+\t\t5'd10: begin digit1 = 4'b0001; digit0 = 4'b0000; end
+\t\t5'd11: begin digit1 = 4'b0001; digit0 = 4'b0001; end
+\t\t5'd12: begin digit1 = 4'b0001; digit0 = 4'b0010; end
+\t\t5'd13: begin digit1 = 4'b0001; digit0 = 4'b0011; end
+\t\t5'd14: begin digit1 = 4'b0001; digit0 = 4'b0100; end
+\t\t5'd15: begin digit1 = 4'b0001; digit0 = 4'b0101; end
+\t\t5'd16: begin digit1 = 4'b0001; digit0 = 4'b0110; end
+\t\t5'd17: begin digit1 = 4'b0001; digit0 = 4'b0111; end
+\t\t5'd18: begin digit1 = 4'b0001; digit0 = 4'b1000; end
+\t\t5'd19: begin digit1 = 4'b0001; digit0 = 4'b1001; end
+
+\t\t5'd20: begin digit1 = 4'b0010; digit0 = 4'b0000; end
+\t\t5'd21: begin digit1 = 4'b0010; digit0 = 4'b0001; end
+\t\t5'd22: begin digit1 = 4'b0010; digit0 = 4'b0010; end
+\t\t5'd23: begin digit1 = 4'b0010; digit0 = 4'b0011; end
+\t\tdefault:  begin digit1 = 0; digit0 = 0; end
+\tendcase\t
+end
+
+assign data_HH = {digit1,digit0};
+
+endmodule
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    15:22:07 05/17/2016 
+// Design Name: 
+// Module Name:    prueba_imagenes 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module prueba_imagenes
+(
+input wire clk, reset,
+output wire hsync,vsync,pic_on,pixel_tick,
+output wire [7:0] RGB
+);
+
+wire video_on;
+wire [9:0] pixel_x, pixel_y;
+//reg [11:0] RGB_reg, RGB_next;
+
+timing_generator_VGA instancia_timing_generator_VGA
+(
+.clk(clk),.reset(reset),
+.hsync(hsync),.vsync(vsync),.video_on(video_on),.p_tick(pixel_tick),
+.pixel_x(pixel_x), .pixel_y(pixel_y)
+);
+
+picture_hora instancia_picture_hora
+(
+.video_on(video_on),//se\xf1al que indica que se encuentra en la regi\xf3n visible de resoluci\xf3n 640x480
+.pixel_x(pixel_x), .pixel_y(pixel_y),
+.pic_on(pic_on),
+.pic_RGB(RGB)
+);
+
+
+endmodule
+"
+"`timescale 1ns / 1ps
+
+////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:
+//
+// Create Date:   21:23:18 05/16/2016
+// Design Name:   controlador_teclado_ps2
+// Module Name:   C:/Users/Jafet/Documents/Proyectos Dis.Sist.Digitales/III_Proyecto_Laboratorio_Sistemas_Digitales/Archivos .v/proy_3_grupo_2_sem_1_2016/testbench_teclado_ps2.v
+// Project Name:  III_Proyecto_Laboratorio_Sistemas_Digitales
+// Target Device:  
+// Tool versions:  
+// Description: 
+//
+// Verilog Test Fixture created by ISE for module: controlador_teclado_ps2
+//
+// Dependencies:
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+////////////////////////////////////////////////////////////////////////////////
+
+module testbench_teclado_ps2;
+
+\t// Inputs
+\treg clk;
+\treg reset;
+\treg ps2data;
+\treg ps2clk;
+
+\t// Outputs
+\twire [7:0] ascii_code;
+
+\t// Instantiate the Unit Under Test (UUT)
+\tcontrolador_teclado_ps2 uut (
+\t\t.clk(clk), 
+\t\t.reset(reset), 
+\t\t.ps2data(ps2data), 
+\t\t.ps2clk(ps2clk), 
+\t\t.ascii_code(ascii_code)
+\t);
+\t
+\t//Para generar clock de 100 MHz
+\tinitial begin
+\tclk = 0;
+\tforever #5 clk = ~clk;
+\tend
+\t
+/*\t//Para generar clock de 10 kHz (ps2)
+\tinitial begin
+\tps2clk = 0;
+\tforever #50000 ps2clk = ~ps2clk;
+\tend
+*/
+
+\tinitial begin
+\t\t// Initialize Inputs
+\t\treset = 1;
+\t\tps2data = 0;
+\t\tps2clk = 1;
+
+\t\t// Wait 100 ns for global reset to finish
+\t\t#100;
+\t\t
+\t\treset = 0;
+        
+\t\t// Add stimulus here
+\t\t
+\t\t//F0
+\t\t#50005
+\t\tps2clk = 1;
+\t\tps2data = 0;//Bit de inicio
+\t\t
+\t\t#50000
+\t\tps2clk = 0;
+\t\t
+\t\t#50000
+\t\tps2clk = 1;
+\t\tps2data = 0;//Bit 0 (1C)
+
+\t\t#50000
+\t\tps2clk = 0;
+\t\t
+\t\t#50000
+\t\tps2clk = 1;
+\t\tps2data = 0;//Bit 1 (1C)
+
+\t\t#50000
+\t\tps2clk = 0;
+\t\t
+\t\t#50000
+\t\tps2clk = 1;
+\t\tps2data = 0;//Bit 2 (1C)
+\t\t
+\t\t#50000
+\t\tps2clk = 0;
+\t\t
+\t\t#50000
+\t\tps2clk = 1;
+\t\tps2data = 0;//Bit 3 (1C)
+\t\t
+\t\t#50000
+\t\tps2clk = 0;
+\t\t
+\t\t#50000
+\t\tps2clk = 1;
+\t\tps2data = 1;//Bit 4 (1C)
+
+\t\t#50000
+\t\tps2clk = 0;
+\t\t
+\t\t#50000
+\t\tps2clk = 1;
+\t\tps2data = 1;//Bit 5 (1C)
+
+\t\t#50000
+\t\tps2clk = 0;
+\t\t
+\t\t#50000
+\t\tps2clk = 1;
+\t\tps2data = 1;//Bit 6 (1C)
+
+\t\t#50000
+\t\tps2clk = 0;
+\t\t
+\t\t#50000
+\t\tps2clk = 1;
+\t\tps2data = 1;//Bit 7 (1C)
+
+\t\t#50000
+\t\tps2clk = 0;
+\t\t
+\t\t#50000
+\t\tps2clk = 1;
+\t\tps2data = 1;//Bit paridad (par=1)
+
+\t\t#50000
+\t\tps2clk = 0;
+\t\t
+\t\t#50000
+\t\tps2clk = 1;
+\t\tps2data = 1;//Bit parada
+\t\t
+\t\t#50000
+\t\tps2clk = 0;
+
+\t\t//1C
+\t\t#50000
+\t\tps2clk = 1;
+\t\tps2data = 0;//Bit de inicio
+\t\t
+\t\t#50000
+\t\tps2clk = 0;
+\t\t
+\t\t#50000
+\t\tps2clk = 1;
+\t\tps2data = 0;//Bit 0 (1C)
+
+\t\t#50000
+\t\tps2clk = 0;
+\t\t
+\t\t#50000
+\t\tps2clk = 1;
+\t\tps2data = 0;//Bit 1 (1C)
+
+\t\t#50000
+\t\tps2clk = 0;
+\t\t
+\t\t#50000
+\t\tps2clk = 1;
+\t\tps2data = 1;//Bit 2 (1C)
+\t\t
+\t\t#50000
+\t\tps2clk = 0;
+\t\t
+\t\t#50000
+\t\tps2clk = 1;
+\t\tps2data = 1;//Bit 3 (1C)
+\t\t
+\t\t#50000
+\t\tps2clk = 0;
+\t\t
+\t\t#50000
+\t\tps2clk = 1;
+\t\tps2data = 1;//Bit 4 (1C)
+
+\t\t#50000
+\t\tps2clk = 0;
+\t\t
+\t\t#50000
+\t\tps2clk = 1;
+\t\tps2data = 0;//Bit 5 (1C)
+
+\t\t#50000
+\t\tps2clk = 0;
+\t\t
+\t\t#50000
+\t\tps2clk = 1;
+\t\tps2data = 0;//Bit 6 (1C)
+
+\t\t#50000
+\t\tps2clk = 0;
+\t\t
+\t\t#50000
+\t\tps2clk = 1;
+\t\tps2data = 0;//Bit 7 (1C)
+
+\t\t#50000
+\t\tps2clk = 0;
+\t\t
+\t\t#50000
+\t\tps2clk = 1;
+\t\tps2data = 1;//Bit paridad (par=1)
+
+\t\t#50000
+\t\tps2clk = 0;
+\t\t
+\t\t#50000
+\t\tps2clk = 1;
+\t\tps2data = 1;//Bit parada
+\t\t
+\t\t#50000
+\t\tps2clk = 1;
+\t\t
+\t\t#200000$stop;\t\t
+\tend
+      
+endmodule
+
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: Jafet Chaves Barrantes
+// 
+// Create Date:    16:24:58 05/12/2016 
+// Design Name: 
+// Module Name:    keycode_to_ascii 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: Circuito combinacional que decodifica el c\xf3digo de tecla a c\xf3digo ASCII
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module keycode_to_ascii
+(
+input wire [7:0] key_code,
+output reg [7:0] ascii_code
+);
+
+always@*
+begin
+
+\tcase(key_code)
+\t\t8\'h05: ascii_code = 8\'h21;//F1(!) Reset del rtc
+\t\t8\'h06: ascii_code = 8\'h22;//F2("")
+\t\t8\'h1c: ascii_code = 8\'h41;//A Salida de configuracion sin configurar
+\t\t8\'h23: ascii_code = 8\'h44;//D Apagar alarma del timer
+\t\t8\'h2b: ascii_code = 8\'h46;//F entrar en configuracion fecha
+\t\t8\'h33: ascii_code = 8\'h48;//H entra en configuracion hora
+\t\t8\'h3a: ascii_code = 8\'h4d;//M
+\t\t8\'h2d: ascii_code = 8\'h52;//R 
+\t\t8\'h1b: ascii_code = 8\'h53;//S cambiar formato hora
+\t\t8\'h2c: ascii_code = 8\'h54;//T entra en configuracion timer
+\t\t8\'h72: ascii_code = 8\'h35;//flecha abajo (5) 
+\t\t8\'h6b: ascii_code = 8\'h34;//flecha izquierda (4) 
+\t\t8\'h74: ascii_code = 8\'h36;//flecha derecha (6)
+\t\t8\'h75: ascii_code = 8\'h38;//flecha arriba (8)
+\t\t8\'h5a: ascii_code = 8\'h0d;//Enter
+\t\tdefault ascii_code = 8\'b0;//NULL char
+\tendcase
+end
+
+
+endmodule
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    20:14:45 05/28/2016 
+// Design Name: 
+// Module Name:    prueba_lector_rtc_7_seg 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module prueba_lector_rtc_7_seg(
+
+input wire clk, reset, sw,
+inout [7:0]dato,
+output wire AD, CS, WR, RD,
+output [7:0] code_digitos_decimal,
+output [3:0] code_7seg
+//output [7:0] RGB,
+//output hsync, vsync
+);
+
+//Conexiones internas
+reg [7:0]in_port;
+wire [7:0]out_port;
+wire [7:0]port_id;
+wire write_strobe;
+wire k_write_strobe;
+wire read_strobe;
+wire interrupt;
+// conexiones banco de registros a VGA 
+
+wire [7:0]out_seg_hora,out_min_hora,out_hora_hora;
+wire [7:0]out_dia_fecha,out_mes_fecha,out_jahr_fecha,out_dia_semana;
+wire [7:0]out_seg_timer,out_min_timer,out_hora_timer;
+
+//////////////////////////// hold's
+wire hold_seg_hora; 
+wire hold_min_hora; 
+wire hold_hora_hora; 
+wire hold_dia_fecha; 
+wire hold_mes_fecha; 
+wire hold_jahr_fecha; 
+wire hold_dia_semana; 
+wire hold_seg_timer;
+wire hold_min_timer; 
+wire hold_hora_timer;
+// wire hold_banderas_config;
+//////////////////////
+
+
+wire flag_done;
+reg [7:0]fin_lectura_escritura;
+wire [7:0]wire_out_dato;
+
+reg state_reg_flag,state_next_flag;
+
+assign interrupt = 1'b0;
+
+microcontrolador instancia_microcontrolador 
+(
+    .clk(clk), 
+    .reset(reset), 
+    .interrupt(interrupt), 
+    .in_port(in_port), 
+    .write_strobe(write_strobe), 
+    .k_write_strobe(), 
+    .read_strobe(read_strobe), 
+    .interrupt_ack(), 
+    .port_id(port_id), 
+    .out_port(out_port)
+);
+/*
+controlador_VGA instancia_controlador_VGA 
+(
+    .clock(clk), 
+    .reset(reset), 
+    .digit0_HH(out_hora_hora[3:0]), .digit1_HH(out_hora_hora[7:4]), .digit0_MM(out_min_hora[3:0]), .digit1_MM(out_min_hora[7:4]), .digit0_SS(out_seg_hora[3:0]), .digit1_SS(out_seg_hora[7:4]),//
+\t .digit0_DAY(out_dia_fecha[3:0]), .digit1_DAY(out_dia_fecha[7:4]), .digit0_MES(out_mes_fecha[3:0]), .digit1_MES(out_mes_fecha[7:4]), .digit0_YEAR(out_jahr_fecha[3:0]), .digit1_YEAR(out_jahr_fecha[7:4]),//
+\t .digit0_HH_T(out_hora_timer[3:0]), .digit1_HH_T(out_hora_timer[7:4]), .digit0_MM_T(out_min_timer[3:0]), .digit1_MM_T(out_min_timer[7:4]), .digit0_SS_T(out_seg_timer[3:0]), .digit1_SS_T(out_seg_timer[7:4]),//Decenas y unidades para los n\xfameros en pantalla (18 inputs de 3 bits)
+    .AM_PM(1'b0), 
+    .config_mode(2'b0), 
+    .cursor_location(2'b0), 
+    .formato_hora(1'b1), 
+    .estado_alarma(1'b0), 
+    .hsync(hsync), 
+    .vsync(vsync), 
+    .RGB(RGB)
+    );
+*/
+memoria_registros_VGA instancia_memoria_registros_VGA 
+(
+    .clk(clk), 
+    .reset(reset), 
+    .cs_seg_hora(1'b0), 
+    .cs_min_hora(1'b0), 
+    .cs_hora_hora(1'b0), 
+    .cs_dia_fecha(1'b0), 
+    .cs_mes_fecha(1'b0), 
+    .cs_jahr_fecha(1'b0), 
+    .cs_seg_timer(1'b0), 
+    .cs_min_timer(1'b0), 
+    .cs_hora_timer(1'b0), 
+    .hold_seg_hora(hold_seg_hora), 
+    .hold_min_hora(hold_min_hora), 
+    .hold_hora_hora(hold_hora_hora), 
+    .hold_dia_fecha(hold_dia_fecha), 
+    .hold_mes_fecha(hold_mes_fecha), 
+    .hold_jahr_fecha(hold_jahr_fecha), 
+    .hold_seg_timer(hold_seg_timer), 
+    .hold_min_timer(hold_min_timer), 
+    .hold_hora_timer(hold_hora_timer), 
+    .hold_banderas_config(1'b1), 
+    .data_PicoBlaze(out_port), 
+    .count_seg_hora(8'b0), 
+    .count_min_hora(8'b0), 
+    .count_hora_hora(8'b0), 
+    .count_dia_fecha(8'b0), 
+    .count_mes_fecha(8'b0), 
+    .count_jahr_fecha(8'b0),   
+    .count_seg_timer(8'b0), 
+    .count_min_timer(8'b0), 
+    .count_hora_timer(8'b0), 
+    .out_seg_hora(out_seg_hora), 
+    .out_min_hora(out_min_hora), 
+    .out_hora_hora(out_hora_hora), 
+    .out_dia_fecha(out_dia_fecha), 
+    .out_mes_fecha(out_mes_fecha), 
+    .out_jahr_fecha(out_jahr_fecha), 
+    .out_seg_timer(out_seg_timer), 
+    .out_min_timer(out_min_timer), 
+    .out_hora_timer(out_hora_timer), 
+    .out_banderas_config()
+);
+
+deco_hold_registros instancia_deco_hold_registros (
+    .write_strobe(write_strobe), 
+    .port_id(port_id), 
+    .hold_seg_hora(hold_seg_hora), 
+    .hold_min_hora(hold_min_hora), 
+    .hold_hora_hora(hold_hora_hora), 
+    .hold_dia_fecha(hold_dia_fecha), 
+    .hold_mes_fecha(hold_mes_fecha), 
+    .hold_jahr_fecha(hold_jahr_fecha), 
+    .hold_seg_timer(hold_seg_timer), 
+    .hold_min_timer(hold_min_timer), 
+    .hold_hora_timer(hold_hora_timer)
+    );
+\t 
+escritor_lector_rtc instancia_escritor_lector_rtc (
+    .clk(clk), 
+    .reset(reset), 
+    .port_id(port_id), 
+    .in_dato(out_port), 
+    .write_strobe(write_strobe), 
+    .read_strobe(read_strobe), 
+    .reg_a_d(AD), 
+    .reg_cs(CS), 
+    .reg_rd(RD), 
+    .reg_wr(WR), 
+    .out_dato(wire_out_dato), 
+    .flag_done(flag_done), 
+    .dato(dato)
+    );
+reg [7:0]reg_seg,next_seg;
+reg [7:0]valor;
+ always @ (posedge clk)   begin
+\treg_seg = next_seg;
+      case (port_id) 
+\t\t\t8'h0F : in_port <= fin_lectura_escritura;
+\t\t\t8'h10 : in_port <= wire_out_dato;
+        default : in_port <= 8'bXXXXXXXX ;  
+      endcase
+  end
+  
+/// maquina de estados para manipular fin lectura escritura
+always @ (negedge clk,posedge reset) begin 
+\tif (reset) state_reg_flag = 1'b0;
+\telse state_reg_flag = state_next_flag;
+end
+
+always@ (*) begin
+\tif (sw) valor = 8'hAA;
+\telse valor = 8'h2C;
+\tif (port_id == 8'h03 && write_strobe == 1 ) next_seg = out_port;
+\telse\tnext_seg = reg_seg;
+\t
+state_next_flag = state_reg_flag;
+\tcase (state_reg_flag)
+\t1'b0: begin
+\t\tfin_lectura_escritura = 8'h00;
+\t\tif (flag_done == 1) state_next_flag = 1'b1;
+\t\telse state_next_flag = 1'b0;
+\t\tend
+\t1'b1: begin
+\t\tfin_lectura_escritura = 8'h01;
+\t\tif(port_id == 8'h0F && read_strobe == 1)  state_next_flag = 1'b0;
+\t\telse  state_next_flag = 1'b1; \t\t
+\tend
+\tendcase
+end
+
+\t disp_hex_mux instancia_disp_hex_mux (
+    .clk(clk), 
+    .reset(reset), 
+    .hex3(valor[7:4]), 
+    .hex2(valor[3:0]), 
+    .hex1(reg_seg[7:4]), 
+    .hex0(reg_seg[3:0]), 
+    .dp_in(), 
+    .an(code_7seg), 
+    .sseg(code_digitos_decimal)
+    );
+
+
+\t 
+ 
+
+endmodule
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    11:26:26 05/17/2016 
+// Design Name: 
+// Module Name:    Driver_bus_bidireccional 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module Driver_bus_bidireccional(
+\tinput clk,
+\tinput in_flag_escritura,//bandera para capturar dato
+\tinput in_flag_lectura,
+\tinput in_direccion_dato,
+\tinput [7:0]in_dato,//Datos de entrada para rtc
+\toutput reg [7:0]out_reg_dato,//Datos de salida para banco de registros
+\tinput [7:0]addr_RAM,//Dato de direccion para RAM
+\tinout tri [7:0]dato //Dato de RTC
+    );
+ 
+reg [7:0]dato_secundario;
+reg [7:0]next_out_dato;
+//*********************************************************
+ 
+// ASIGNACION DE BUS DE 3 ESTADOS
+assign dato = (in_flag_escritura)? dato_secundario : 8'bZ;
+
+//LOGICA SECUENCIAL
+always@(posedge clk) begin
+\tout_reg_dato <= next_out_dato;
+end
+
+//CONTROLADOR DE SALIDA
+always @(*)
+begin
+\tcase({in_flag_escritura,in_flag_lectura,in_direccion_dato})
+\t\t3'b000: begin dato_secundario = 8'd0; //NO DEBE PASAR
+\t\tnext_out_dato = out_reg_dato;
+\t\tend
+\t\t3'b011: begin dato_secundario = 8'd0;//LEER DATO
+\t\tnext_out_dato = dato;
+\t\tend 
+\t\t3'b100: begin dato_secundario = addr_RAM;// ESCRIBIR DIRECCION RAM
+\t\tnext_out_dato = out_reg_dato;
+\t\tend 
+\t\t3'b101: begin  dato_secundario = in_dato;// ESCRIBE DATO
+\t\tnext_out_dato = out_reg_dato;
+\t\tend
+\t\tdefault: begin
+\t\tdato_secundario = 8'd0; //NO DEBE PASAR
+\t\tnext_out_dato = out_reg_dato;
+\t\tend
+\t
+\tendcase
+end
+
+
+endmodule
+"
+"`timescale 1ns / 1ps
+
+////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:
+//
+// Create Date:   19:39:35 05/28/2016
+// Design Name:   prueba_lectura_rtc
+// Module Name:   D:/TEC/I 2016/Lab Digitales/Proyecto III/Proyecto Xillinx/Lab_Sistemas_Digitales_3_proyecto/TESTBENCH_prueba_lectura_rtc.v
+// Project Name:  Lab_Sistemas_Digitales_3_proyecto
+// Target Device:  
+// Tool versions:  
+// Description: 
+//
+// Verilog Test Fixture created by ISE for module: prueba_lectura_rtc
+//
+// Dependencies:
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+////////////////////////////////////////////////////////////////////////////////
+
+module TESTBENCH_prueba_lectura_rtc;
+
+\t// Inputs
+\treg clk;
+\treg reset;
+
+\t// Outputs
+\twire AD;
+\twire CS;
+\twire WR;
+\twire RD;
+\twire [7:0] RGB;
+\twire hsync;
+\twire vsync;
+\twire [7:0]port_id,out_port,wire_in_port;
+\twire [7:0]fin_lectura_escritura;
+\twire hold_seg_hora;
+
+\t// Bidirs
+\twire [7:0] dato;
+
+\t// Instantiate the Unit Under Test (UUT)
+\tprueba_lectura_rtc uut (
+\t\t.clk(clk), 
+\t\t.reset(reset), 
+\t\t.dato(dato), 
+\t\t.AD(AD), 
+\t\t.CS(CS), 
+\t\t.WR(WR), 
+\t\t.RD(RD), 
+\t\t.port_id(port_id),
+\t\t.out_port(out_port),
+\t\t.wire_in_port(wire_in_port),
+\t\t.fin_lectura_escritura(fin_lectura_escritura),
+\t\t.hold_seg_hora(hold_seg_hora),
+\t\t.RGB(RGB), 
+\t\t.hsync(hsync), 
+\t\t.vsync(vsync)
+\t);
+always #5 clk = !clk;
+\tinitial begin
+\t\t// Initialize Inputs
+\t\tclk = 0;
+\t\treset = 1;
+\t\t#5 reset = 0;
+\t\t// Wait 100 ns for global reset to finish
+\t\t#100;
+\t\t#100000 $stop;
+        
+\t\t// Add stimulus here
+
+\tend
+      
+endmodule
+
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: Jafet Chaves Barrantes
+// 
+// Create Date:    14:31:45 05/12/2016 
+// Design Name: 
+// Module Name:    identificador_teclas 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: FSM que eval\xfaa la detecci\xf3n el ""break code"" F0, y extraer codigo de la tecla correspondiente (c\xf3digo siguiente)
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module identificador_teclas
+(
+input wire clk, reset,
+input wire rx_done_tick,
+input wire [7:0] dout,//Utilizar solo los bits que realmente contienen el c\xf3digo de la tecla
+output reg gotten_code_flag //Bandera para actualizar el FIFO
+);
+
+//Declaraci\xf3n de constantes
+localparam break_code = 8\'hF0;
+
+//Declaraci\xf3n simb\xf3lica de estados
+localparam wait_break_code = 1\'b0;
+localparam get_code = 1\'b1;
+
+//Declaraci\xf3n de se\xf1ales
+reg state_next, state_reg;
+
+//=================================================
+// FSM
+//=================================================
+
+// Estado FSM y registros de datos
+
+always @(posedge clk, posedge reset)
+\tif (reset)
+\t\tstate_reg <= wait_break_code;
+\telse
+\t\tstate_reg <= state_next;
+\t\t
+// L\xf3gica de siguiente estado siguiente de la FSM
+always @*
+begin
+\tgotten_code_flag = 1\'b0;
+\tstate_next = state_reg;
+\tcase (state_reg)
+\t\twait_break_code:  // Espera ""break code""
+\t\t\tif (rx_done_tick == 1\'b1 && dout == break_code)
+\t\t\t\tstate_next = get_code;
+\t\tget_code:  // Obtener el pr\xf3ximo c\xf3digo
+\t\t\tif (rx_done_tick)
+\t\t\t\tbegin
+\t\t\t\t\tgotten_code_flag =1\'b1;
+\t\t\t\t\tstate_next = wait_break_code;
+\t\t\t\tend
+\tendcase
+end
+\t\t
+endmodule
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    14:58:55 05/17/2016 
+// Design Name: 
+// Module Name:    escritor_lector_rtc 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module escritor_lector_rtc_2
+(
+\tinput wire clk,reset,
+\tinput wire [7:0] in_dato, port_id,
+\tinput wire write_strobe, k_write_strobe, read_strobe,
+\toutput wire reg_a_d,reg_cs,reg_rd,reg_wr,
+\toutput wire[7:0]out_dato,
+\toutput reg flag_done,
+\tinout [7:0]dato
+);
+
+wire fin_lectura_escritura; 
+reg en_funcion;
+reg [7:0]addr_RAM,dato_escribir;
+reg [7:0]reg_addr_RAM, reg_dato_escribir;
+reg reg_escribir_leer,escribir_leer;
+
+
+reg state_reg_flag,state_next_flag;//Para la m\xe1quina de estados que controla el flag_done
+
+wire direccion_dato;//conexi\xf3n interna
+/// I/O Datos
+Driver_bus_bidireccional instance_driver_bus_bidireccional (
+\t .clk(clk),
+    .in_flag_escritura(~reg_wr), 
+    .in_flag_lectura(~reg_rd), 
+    .in_direccion_dato(direccion_dato), //bandera para saber si se debe escribir direccion/dato
+    .in_dato(dato_escribir), 
+    .out_reg_dato(out_dato),  
+    .addr_RAM(addr_RAM), 
+    .dato(dato)
+    );
+
+//Generador de se\xf1ales de control
+signal_control_rtc_generator instance_signal_control_rtc_generator (
+    .clk(clk), 
+    .reset(reset), 
+    .in_escribir_leer(escribir_leer), 
+    .en_funcion(en_funcion),
+    .reg_a_d(reg_a_d), \t\t
+    .reg_cs(reg_cs), 
+    .reg_wr(reg_wr), 
+    .reg_rd(reg_rd), 
+    .out_direccion_dato(direccion_dato), 
+    .flag_done(fin_lectura_escritura)
+    );
+\t 
+//Para habilitar el generador de se\xf1ales\t 
+always@(posedge clk)
+begin
+\tif(port_id == 8'h0E) en_funcion <= 1'b1;
+\telse en_funcion <= 1'b0;
+end
+
+// logica secuencial
+always@(negedge clk , posedge reset) begin
+\tif (reset)begin
+\t\taddr_RAM <= 8'h0;
+\t\tdato_escribir <= 8'h0;
+\t\tescribir_leer <= 1'b0;
+\tend
+\telse begin
+\t\taddr_RAM <= reg_addr_RAM;
+\t\tdato_escribir <= reg_dato_escribir;
+\t\tescribir_leer <= reg_escribir_leer;
+\t\t
+\tend
+end
+
+// logica combinacional para port_id
+always@* begin
+\tif (write_strobe == 1'b1 || k_write_strobe == 1'b1) begin
+\t// inicio de secuencia de lectura_escritura rtc
+\t
+\tcase (port_id)
+\t8'h00: begin //actualiza direccion
+\treg_addr_RAM = in_dato;
+\treg_dato_escribir = dato_escribir; 
+\treg_escribir_leer = escribir_leer;
+\tend
+\t8'h01: begin // actualiza dato 
+\treg_dato_escribir = in_dato;
+\treg_addr_RAM = addr_RAM;
+\treg_escribir_leer = escribir_leer;
+\tend
+\t8'h0E: begin // inicia secuancia de rtc
+\treg_addr_RAM = addr_RAM;
+\treg_dato_escribir = dato_escribir;
+\treg_escribir_leer = in_dato[0];
+\tend
+\tdefault: begin
+\treg_addr_RAM = addr_RAM;
+\treg_dato_escribir = dato_escribir;
+\treg_escribir_leer = escribir_leer;
+\tend
+\tendcase\t
+\tend
+\t
+\telse begin
+\treg_addr_RAM = addr_RAM;
+\treg_dato_escribir = dato_escribir;
+\treg_escribir_leer = escribir_leer;
+\tend
+\t
+end
+
+/// maquina de estados para manipular fin lectura escritura
+always @ (negedge clk, posedge reset) begin 
+\tif (reset) state_reg_flag <= 1'b0;
+\telse state_reg_flag <= state_next_flag;
+end
+
+always@* 
+begin
+state_next_flag = state_reg_flag;
+\tcase (state_reg_flag)
+\t1'b0: begin
+\t\tflag_done = 8'h00;
+\t\tif (fin_lectura_escritura == 1) state_next_flag = 1'b1;
+\t\telse state_next_flag = 1'b0;
+\t\tend
+\t1'b1: begin
+\t\tflag_done = 8'h01;
+\t\tif(port_id == 8'h0F && read_strobe == 1)  state_next_flag = 1'b0;//Cuando el micro lee el dato se baja la bandera
+\t\telse  state_next_flag = 1'b1; \t\t
+\tend
+\tendcase
+end
+
+endmodule
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    13:49:19 05/27/2016 
+// Design Name: 
+// Module Name:    prueba_lectura_rtc 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module prueba_lectura_rtc
+(
+input wire clk, reset,
+inout [7:0]dato,
+output wire AD, CS, WR, RD,
+output [7:0]port_id,out_port,wire_in_port,
+output reg[7:0]fin_lectura_escritura,
+output hold_seg_hora,
+output [7:0] RGB,
+output hsync, vsync
+); 
+
+//Conexiones internas
+reg [7:0]in_port;
+assign wire_in_port = in_port;
+//wire [7:0]out_port;
+//wire [7:0]port_id;
+wire write_strobe;
+wire k_write_strobe;
+wire read_strobe;
+wire interrupt;
+// conexiones banco de registros a VGA
+wire [7:0]out_seg_hora,out_min_hora,out_hora_hora;
+wire [7:0]out_dia_fecha,out_mes_fecha,out_jahr_fecha,out_dia_semana;
+wire [7:0]out_seg_timer,out_min_timer,out_hora_timer;
+
+//////////////////////////// hold's
+//wire hold_seg_hora; 
+wire hold_min_hora; 
+wire hold_hora_hora; 
+wire hold_dia_fecha; 
+wire hold_mes_fecha; 
+wire hold_jahr_fecha; 
+wire hold_dia_semana; 
+wire hold_seg_timer;
+wire hold_min_timer; 
+wire hold_hora_timer;
+// wire hold_banderas_config;
+//////////////////////
+
+
+wire flag_done;
+//reg [7:0]fin_lectura_escritura;
+wire [7:0]wire_out_dato;
+
+reg state_reg_flag,state_next_flag;
+
+assign interrupt = 1'b0;
+
+microcontrolador instancia_microcontrolador 
+(
+    .clk(clk), 
+    .reset(reset), 
+    .interrupt(interrupt), 
+    .in_port(in_port), 
+    .write_strobe(write_strobe), 
+    .k_write_strobe(), 
+    .read_strobe(read_strobe), 
+    .interrupt_ack(), 
+    .port_id(port_id), 
+    .out_port(out_port)
+);
+
+controlador_VGA instancia_controlador_VGA 
+(
+    .clock(clk), 
+    .reset(reset), 
+    .digit0_HH(out_hora_hora[3:0]), .digit1_HH(out_hora_hora[7:4]), .digit0_MM(out_min_hora[3:0]), .digit1_MM(out_min_hora[7:4]), .digit0_SS(out_seg_hora[3:0]), .digit1_SS(out_seg_hora[7:4]),//
+\t .digit0_DAY(out_dia_fecha[3:0]), .digit1_DAY(out_dia_fecha[7:4]), .digit0_MES(out_mes_fecha[3:0]), .digit1_MES(out_mes_fecha[7:4]), .digit0_YEAR(out_jahr_fecha[3:0]), .digit1_YEAR(out_jahr_fecha[7:4]),//
+\t .digit0_HH_T(out_hora_timer[3:0]), .digit1_HH_T(out_hora_timer[7:4]), .digit0_MM_T(out_min_timer[3:0]), .digit1_MM_T(out_min_timer[7:4]), .digit0_SS_T(out_seg_timer[3:0]), .digit1_SS_T(out_seg_timer[7:4]),//Decenas y unidades para los n\xfameros en pantalla (18 inputs de 3 bits)
+    .AM_PM(1'b0), 
+    .config_mode(2'b0), 
+    .cursor_location(2'b0), 
+    .formato_hora(1'b1), 
+    .estado_alarma(1'b0), 
+    .hsync(hsync), 
+    .vsync(vsync), 
+    .RGB(RGB)
+    );
+
+memoria_registros_VGA instancia_memoria_registros_VGA 
+(
+    .clk(clk), 
+    .reset(reset), 
+    .cs_seg_hora(1'b0), 
+    .cs_min_hora(1'b0), 
+    .cs_hora_hora(1'b0), 
+    .cs_dia_fecha(1'b0), 
+    .cs_mes_fecha(1'b0), 
+    .cs_jahr_fecha(1'b0), 
+    .cs_seg_timer(1'b0), 
+    .cs_min_timer(1'b0), 
+    .cs_hora_timer(1'b0), 
+    .hold_seg_hora(hold_seg_hora), 
+    .hold_min_hora(hold_min_hora), 
+    .hold_hora_hora(hold_hora_hora), 
+    .hold_dia_fecha(hold_dia_fecha), 
+    .hold_mes_fecha(hold_mes_fecha), 
+    .hold_jahr_fecha(hold_jahr_fecha), 
+    .hold_seg_timer(hold_seg_timer), 
+    .hold_min_timer(hold_min_timer), 
+    .hold_hora_timer(hold_hora_timer), 
+    .hold_banderas_config(1'b1), 
+    .data_PicoBlaze(out_port), 
+    .count_seg_hora(8'b0), 
+    .count_min_hora(8'b0), 
+    .count_hora_hora(8'b0), 
+    .count_dia_fecha(8'b0), 
+    .count_mes_fecha(8'b0), 
+    .count_jahr_fecha(8'b0), 
+    .count_seg_timer(8'b0), 
+    .count_min_timer(8'b0), 
+    .count_hora_timer(8'b0), 
+    .out_seg_hora(out_seg_hora), 
+    .out_min_hora(out_min_hora), 
+    .out_hora_hora(out_hora_hora), 
+    .out_dia_fecha(out_dia_fecha), 
+    .out_mes_fecha(out_mes_fecha), 
+    .out_jahr_fecha(out_jahr_fecha), 
+    .out_seg_timer(out_seg_timer), 
+    .out_min_timer(out_min_timer), 
+    .out_hora_timer(out_hora_timer), 
+    .out_banderas_config()
+);
+
+deco_hold_registros instancia_deco_hold_registros (
+    .write_strobe(write_strobe), 
+    .port_id(port_id), 
+    .hold_seg_hora(hold_seg_hora), 
+    .hold_min_hora(hold_min_hora), 
+    .hold_hora_hora(hold_hora_hora), 
+    .hold_dia_fecha(hold_dia_fecha), 
+    .hold_mes_fecha(hold_mes_fecha), 
+    .hold_jahr_fecha(hold_jahr_fecha), 
+    .hold_seg_timer(hold_seg_timer), 
+    .hold_min_timer(hold_min_timer), 
+    .hold_hora_timer(hold_hora_timer)
+    );
+\t 
+escritor_lector_rtc instancia_escritor_lector_rtc (
+    .clk(clk), 
+    .reset(reset), 
+    .port_id(port_id), 
+    .in_dato(out_port), 
+    .write_strobe(write_strobe), 
+    .read_strobe(read_strobe), 
+    .reg_a_d(AD), 
+    .reg_cs(CS), 
+    .reg_rd(RD), 
+    .reg_wr(WR), 
+    .out_dato(wire_out_dato), 
+    .flag_done(flag_done), 
+    .dato(dato)
+    );
+
+ always @ (posedge clk)
+  begin
+      case (port_id) 
+\t\t\t8'h0F : in_port <= fin_lectura_escritura;
+\t\t\t8'h10 : in_port <= wire_out_dato;
+        default : in_port <= 8'bXXXXXXXX ;  
+      endcase
+  end
+  
+/// maquina de estados para manipular fin lectura escritura
+always @ (negedge clk,posedge reset) begin 
+\tif (reset) state_reg_flag = 1'b0;
+\telse state_reg_flag = state_next_flag;
+end
+
+always@ (*) begin
+state_next_flag = state_reg_flag;
+\tcase (state_reg_flag)
+\t1'b0: begin
+\t\tfin_lectura_escritura = 8'h00;
+\t\tif (flag_done == 1) state_next_flag = 1'b1;
+\t\telse state_next_flag = 1'b0;
+\t\tend
+\t1'b1: begin
+\t\tfin_lectura_escritura = 8'h01;
+\t\tif(port_id == 8'h0F && read_strobe == 1)  state_next_flag = 1'b0;
+\t\telse  state_next_flag = 1'b1; \t\t
+\tend
+\tendcase
+end
+\t 
+\t 
+
+endmodule
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: Jafet Chaves Barrantes
+// 
+// Create Date:    15:45:17 04/03/2016 
+// Design Name: 
+// Module Name:    contador_AD_SS_2dig 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module contador_AD_SS_2dig
+(
+input wire clk,
+input wire reset,
+input wire [3:0] en_count,
+input wire enUP,
+input wire enDOWN,
+output wire [7:0] data_SS//D\xedgitos BCD ya concatenados hacia los registros(8 bits)
+);
+
+localparam N = 6; // Para definir el n\xfamero de bits del contador (hasta 59->6 bits)
+//Declaraci\xf3n de se\xf1ales
+reg [N-1:0] q_act, q_next;
+wire [N-1:0] count_data;
+reg [3:0] digit1, digit0;
+
+//Descripci\xf3n del comportamiento
+always@(posedge clk, posedge reset)
+begin\t
+\t
+\tif(reset)
+\tbegin
+\t\tq_act <= 6'b0;
+\tend
+\t
+\telse
+\tbegin
+\t\tq_act <= q_next;
+\tend
+end
+
+
+//L\xf3gica de salida
+
+always@*
+begin
+
+\tif (en_count == 1)
+\tbegin
+\t\tif (enUP)
+\t\tbegin
+\t\t\tif (q_act >= 6'd59) q_next = 6'd0;
+\t\t\telse q_next = q_act + 6'd1;
+\t\tend
+\t\t
+\t\telse if (enDOWN)
+\t\tbegin
+\t\t\tif (q_act == 6'd0) q_next = 6'd59;
+\t\t\telse q_next = q_act - 6'd1;
+\t\tend
+\t\telse q_next = q_act;
+\tend
+\telse q_next = q_act;
+\t
+end
+
+assign count_data = q_act;
+
+//Decodificaci\xf3n BCD (2 d\xedgitos)
+
+always@*
+begin
+case(count_data)
+6'd0: begin digit1 = 4'b0000; digit0 = 4'b0000; end
+6'd1: begin digit1 = 4'b0000; digit0 = 4'b0001; end
+6'd2: begin digit1 = 4'b0000; digit0 = 4'b0010; end
+6'd3: begin digit1 = 4'b0000; digit0 = 4'b0011; end
+6'd4: begin digit1 = 4'b0000; digit0 = 4'b0100; end
+6'd5: begin digit1 = 4'b0000; digit0 = 4'b0101; end
+6'd6: begin digit1 = 4'b0000; digit0 = 4'b0110; end
+6'd7: begin digit1 = 4'b0000; digit0 = 4'b0111; end
+6'd8: begin digit1 = 4'b0000; digit0 = 4'b1000; end
+6'd9: begin digit1 = 4'b0000; digit0 = 4'b1001; end
+
+6'd10: begin digit1 = 4'b0001; digit0 = 4'b0000; end
+6'd11: begin digit1 = 4'b0001; digit0 = 4'b0001; end
+6'd12: begin digit1 = 4'b0001; digit0 = 4'b0010; end
+6'd13: begin digit1 = 4'b0001; digit0 = 4'b0011; end
+6'd14: begin digit1 = 4'b0001; digit0 = 4'b0100; end
+6'd15: begin digit1 = 4'b0001; digit0 = 4'b0101; end
+6'd16: begin digit1 = 4'b0001; digit0 = 4'b0110; end
+6'd17: begin digit1 = 4'b0001; digit0 = 4'b0111; end
+6'd18: begin digit1 = 4'b0001; digit0 = 4'b1000; end
+6'd19: begin digit1 = 4'b0001; digit0 = 4'b1001; end
+
+6'd20: begin digit1 = 4'b0010; digit0 = 4'b0000; end
+6'd21: begin digit1 = 4'b0010; digit0 = 4'b0001; end
+6'd22: begin digit1 = 4'b0010; digit0 = 4'b0010; end
+6'd23: begin digit1 = 4'b0010; digit0 = 4'b0011; end
+6'd24: begin digit1 = 4'b0010; digit0 = 4'b0100; end
+6'd25: begin digit1 = 4'b0010; digit0 = 4'b0101; end
+6'd26: begin digit1 = 4'b0010; digit0 = 4'b0110; end
+6'd27: begin digit1 = 4'b0010; digit0 = 4'b0111; end
+6'd28: begin digit1 = 4'b0010; digit0 = 4'b1000; end
+6'd29: begin digit1 = 4'b0010; digit0 = 4'b1001; end
+
+6'd30: begin digit1 = 4'b0011; digit0 = 4'b0000; end
+6'd31: begin digit1 = 4'b0011; digit0 = 4'b0001; end
+6'd32: begin digit1 = 4'b0011; digit0 = 4'b0010; end
+6'd33: begin digit1 = 4'b0011; digit0 = 4'b0011; end
+6'd34: begin digit1 = 4'b0011; digit0 = 4'b0100; end
+6'd35: begin digit1 = 4'b0011; digit0 = 4'b0101; end
+6'd36: begin digit1 = 4'b0011; digit0 = 4'b0110; end
+6'd37: begin digit1 = 4'b0011; digit0 = 4'b0111; end
+6'd38: begin digit1 = 4'b0011; digit0 = 4'b1000; end
+6'd39: begin digit1 = 4'b0011; digit0 = 4'b1001; end
+
+6'd40: begin digit1 = 4'b0100; digit0 = 4'b0000; end
+6'd41: begin digit1 = 4'b0100; digit0 = 4'b0001; end
+6'd42: begin digit1 = 4'b0100; digit0 = 4'b0010; end
+6'd43: begin digit1 = 4'b0100; digit0 = 4'b0011; end
+6'd44: begin digit1 = 4'b0100; digit0 = 4'b0100; end
+6'd45: begin digit1 = 4'b0100; digit0 = 4'b0101; end
+6'd46: begin digit1 = 4'b0100; digit0 = 4'b0110; end
+6'd47: begin digit1 = 4'b0100; digit0 = 4'b0111; end
+6'd48: begin digit1 = 4'b0100; digit0 = 4'b1000; end
+6'd49: begin digit1 = 4'b0100; digit0 = 4'b1001; end
+
+6'd50: begin digit1 = 4'b0101; digit0 = 4'b0000; end
+6'd51: begin digit1 = 4'b0101; digit0 = 4'b0001; end
+6'd52: begin digit1 = 4'b0101; digit0 = 4'b0010; end
+6'd53: begin digit1 = 4'b0101; digit0 = 4'b0011; end
+6'd54: begin digit1 = 4'b0101; digit0 = 4'b0100; end
+6'd55: begin digit1 = 4'b0101; digit0 = 4'b0101; end
+6'd56: begin digit1 = 4'b0101; digit0 = 4'b0110; end
+6'd57: begin digit1 = 4'b0101; digit0 = 4'b0111; end
+6'd58: begin digit1 = 4'b0101; digit0 = 4'b1000; end
+6'd59: begin digit1 = 4'b0101; digit0 = 4'b1001; end
+
+default:  begin digit1 = 0; digit0 = 0; end
+endcase
+end
+
+assign data_SS = {digit1,digit0};
+endmodule
+"
+"`timescale 1ns / 1ps
+
+////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:
+//
+// Create Date:   13:56:16 05/24/2016
+// Design Name:   Controlador_reloj_digital
+// Module Name:   D:/TEC/I 2016/Lab Digitales/Proyecto III/Proyecto Xillinx/Proyecto_3/testbench_controlador_reloj_digital.v
+// Project Name:  Proyecto_3
+// Target Device:  
+// Tool versions:   
+// Description: 
+//
+// Verilog Test Fixture created by ISE for module: Controlador_reloj_digital
+//
+// Dependencies:
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// ////////////////////////////////////////////////////////////////////////////////
+
+module testbench_controlador_reloj_digital;
+
+\t// Inputs
+\treg clk;
+\treg reset;
+
+\t// Outputs
+\twire reg_a_d;
+\twire reg_cs;
+\twire reg_rd;
+\twire reg_wr;
+\twire [7:0]port_id;
+\twire [7:0]out_port;
+\twire[7:0]fin_lectura_escritura;
+
+\t// Bidirs
+\twire [7:0] dato; 
+
+\t// Instantiate the Unit Under Test (UUT)
+\tControlador_reloj_digital uut (
+\t\t.clk(clk), 
+\t\t.reset(reset), 
+\t\t.reg_a_d(reg_a_d), 
+\t\t.reg_cs(reg_cs), 
+\t\t.reg_rd(reg_rd), 
+\t\t.reg_wr(reg_wr), 
+\t\t.port_id(port_id),
+\t\t.out_port(out_port),
+\t\t.fin_lectura_escritura(fin_lectura_escritura),
+\t\t.dato(dato)
+\t);
+always #5 clk = ~clk;
+
+\tinitial begin
+\t\t// Initialize Inputs
+\t\tclk = 0;
+\t\treset = 1;
+\t\t#10 reset = 0;
+\t\t
+
+\t\t// Wait 100 ns for global reset to finish
+\t\t#100000 $stop;
+        
+\t\t// Add stimulus here
+
+\tend
+      
+endmodule
+
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: Jafet Chaves Barrantes
+// 
+// Create Date:    11:22:27 03/22/2016 
+// Design Name: 
+// Module Name:    generador_figuras 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: Este m\xf3dulo debe encargarse de generar recuadros que encierran a la hora, fecha, timer,
+//as\xed como la figura de ""ring"" para el timer.
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module generador_figuras
+(
+input wire video_on,//se\xf1al que indica que se encuentra en la regi\xf3n visible de resoluci\xf3n 640x480
+input wire [9:0] pixel_x, pixel_y,//coordenadas xy de cada pixel
+output wire graph_on,
+output reg [7:0] fig_RGB //8 bpp (Nexys 3)
+);
+
+//Declaraci\xf3n de constantes y se\xf1ales
+
+//Coordenas xy de la regi\xf3n visible
+localparam MAX_X = 640;
+localparam MAX_Y = 480;
+
+//L\xedmites del recuadro para la hora (320x192)
+localparam BOX_H_XL = 160; //L\xedmite izquierdo
+localparam BOX_H_XR = 479; //L\xedmite derecho
+localparam BOX_H_YT = 64;// L\xedmite superior
+localparam BOX_H_YB = 255;//L\xedmite inferior
+
+//L\xedmites del recuadro para la fecha (256x96)
+localparam BOX_F_XL = 48;//L\xedmite izquierdo
+localparam BOX_F_XR = 303;//L\xedmite derecho
+localparam BOX_F_YT = 352;//L\xedmite superior
+localparam BOX_F_YB = 447;//L\xedmite inferior
+
+//L\xedmites del recuadro para el timer (256x96)
+localparam BOX_T_XL = 336;//L\xedmite izquierdo
+localparam BOX_T_XR = 591;//L\xedmite derecho
+localparam BOX_T_YT = 352;//L\xedmite superior
+localparam BOX_T_YB = 447;//L\xedmite inferior
+
+//Se\xf1ales de salida de los objetos
+wire BOX_H_on, BOX_F_on, BOX_T_on;
+wire [7:0] BOX_H_RGB, BOX_F_RGB, BOX_T_RGB;
+
+/*Para rellenar con p\xedxeles dentro de los l\xedmites 
+de los objetos*/
+
+//Recuadro HORA
+assign BOX_H_on = (BOX_H_XL<=pixel_x)&&(pixel_x<=BOX_H_XR)
+\t\t\t\t\t\t&&(BOX_H_YT<=pixel_y)&&(pixel_y<=BOX_H_YB);
+
+assign BOX_H_RGB = 8\'h1E;//Turquesa oscuro
+
+//Recuadro FECHA
+assign BOX_F_on = (BOX_F_XL<=pixel_x)&&(pixel_x<=BOX_F_XR)
+\t\t\t\t\t\t&&(BOX_F_YT<=pixel_y)&&(pixel_y<=BOX_F_YB);
+
+assign BOX_F_RGB = 8\'h1E;//Turquesa oscuro
+
+//Recuadro TIMER
+assign BOX_T_on = (BOX_T_XL<=pixel_x)&&(pixel_x<=BOX_T_XR)
+\t\t\t\t\t\t&&(BOX_T_YT<=pixel_y)&&(pixel_y<=BOX_T_YB);
+
+assign BOX_T_RGB = 8\'h1E;//Turquesa oscuro
+
+//Multiplexar la salida RGB
+always @*
+begin\t
+\tif(~video_on)
+\t\tfig_RGB = 8\'b0;//fondo negro
+\t
+\telse
+\t\tif (BOX_H_on) fig_RGB = BOX_H_RGB;
+\t\telse if (BOX_F_on) fig_RGB = BOX_F_RGB;
+\t\telse if (BOX_T_on) fig_RGB = BOX_T_RGB;
+\t\telse fig_RGB = 8\'b0;//fondo negro
+end
+
+assign graph_on = BOX_H_on | BOX_F_on | BOX_T_on;
+\t
+endmodule
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: Jafet Chaves Barrantes
+// 
+// Create Date:    11:05:08 05/26/2016 
+// Design Name: 
+// Module Name:    microcontrolador 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module microcontrolador
+(
+input wire clk, reset,
+input wire interrupt,
+input wire\t[7:0]\tin_port,
+output wire write_strobe, k_write_strobe, read_strobe,
+output wire\tinterrupt_ack,
+output wire\t[7:0]\tport_id,
+output wire\t[7:0]\tout_port
+);
+
+//Conexiones entre la memoria de programa y el kcpsm6
+wire\t[11:0]\taddress;
+wire\t[17:0]\tinstruction;
+wire\tbram_enable;
+wire\tkcpsm6_sleep;         
+wire\tkcpsm6_reset;         
+wire\trdl;
+
+assign kcpsm6_reset = reset | rdl;
+assign kcpsm6_sleep = 1\'b0;
+
+//Instanciaciones del procesador y la memoria de programa
+kcpsm6 #(
+.interrupt_vector\t(12\'h3FF),
+.scratch_pad_memory_size(64),
+.hwbuild\t\t(8\'h00))
+instancia_processor(
+.address \t\t(address),
+.instruction \t(instruction),
+.bram_enable \t(bram_enable),
+.port_id \t\t(port_id),
+.write_strobe \t(write_strobe),
+.k_write_strobe \t(k_write_strobe),
+.out_port \t\t(out_port),
+.read_strobe \t(read_strobe),
+.in_port \t\t(in_port),
+.interrupt \t\t(interrupt),
+.interrupt_ack \t(interrupt_ack),
+.reset \t\t(kcpsm6_reset),
+.sleep\t\t(kcpsm6_sleep),
+.clk \t\t\t(clk));
+
+ROM_programa #(
+.C_FAMILY\t\t   (""S6""),   \t//Family \'S6\' or \'V6\'
+.C_RAM_SIZE_KWORDS\t(2),  \t//Program size \'1\', \'2\' or \'4\'
+.C_JTAG_LOADER_ENABLE\t(0))  \t//Include JTAG Loader when set to \'1\' 
+instancia_ROM_programa (    \t\t\t\t//Name to match your PSM file
+.rdl \t\t\t(rdl),
+.enable \t\t(bram_enable),
+.address \t\t(address),
+.instruction \t(instruction),
+.clk \t\t\t(clk));
+
+endmodule
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    14:55:17 05/31/2016 
+// Design Name: 
+// Module Name:    prueba_lectura_config_reloj 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module prueba_lectura_config_reloj
+(
+input wire clk, reset,
+input wire ps2data, 
+input wire ps2clk, 
+inout [7:0]dato,
+output wire AD, CS, WR, RD,
+output [7:0] RGB,
+output hsync, vsync
+);
+
+//Conexiones internas
+reg [7:0]in_port;
+wire [7:0]out_port;
+wire [7:0]port_id;
+wire write_strobe;
+wire k_write_strobe;
+wire read_strobe;
+wire interrupt;
+// conexiones banco de registros a VGA
+wire [7:0]out_seg_hora,out_min_hora,out_hora_hora;
+wire [7:0]out_dia_fecha,out_mes_fecha,out_jahr_fecha;
+wire [7:0]out_seg_timer,out_min_timer,out_hora_timer;
+
+///////////////////////////// hold's
+wire hold_seg_hora; 
+wire hold_min_hora; 
+wire hold_hora_hora; 
+wire hold_dia_fecha; 
+wire hold_mes_fecha; 
+wire hold_jahr_fecha; 
+wire hold_dia_semana; 
+wire hold_seg_timer;
+wire hold_min_timer; 
+wire hold_hora_timer;
+// wire hold_banderas_config;
+//////////////////////
+
+
+//Conexiones de controlador RTC
+wire fin_lectura_escritura;
+wire [7:0] out_dato;
+
+assign interrupt = 1'b0;
+
+microcontrolador instancia_microcontrolador 
+(
+    .clk(clk), 
+    .reset(reset), 
+    .interrupt(interrupt), 
+    .in_port(in_port), 
+    .write_strobe(write_strobe), 
+    .k_write_strobe(k_write_strobe), 
+    .read_strobe(read_strobe), 
+    .interrupt_ack(), 
+    .port_id(port_id), 
+    .out_port(out_port)
+);
+
+controlador_VGA instancia_controlador_VGA 
+(
+    .clock(clk), 
+    .reset(reset), 
+    .digit0_HH(out_hora_hora[3:0]), .digit1_HH(out_hora_hora[7:4]), .digit0_MM(out_min_hora[3:0]), .digit1_MM(out_min_hora[7:4]), .digit0_SS(out_seg_hora[3:0]), .digit1_SS(out_seg_hora[7:4]),//
+\t .digit0_DAY(out_dia_fecha[3:0]), .digit1_DAY(out_dia_fecha[7:4]), .digit0_MES(out_mes_fecha[3:0]), .digit1_MES(out_mes_fecha[7:4]), .digit0_YEAR(out_jahr_fecha[3:0]), .digit1_YEAR(out_jahr_fecha[7:4]),//
+\t .digit0_HH_T(out_hora_timer[3:0]), .digit1_HH_T(out_hora_timer[7:4]), .digit0_MM_T(out_min_timer[3:0]), .digit1_MM_T(out_min_timer[7:4]), .digit0_SS_T(out_seg_timer[3:0]), .digit1_SS_T(out_seg_timer[7:4]),//Decenas y unidades para los n\xfameros en pantalla (18 inputs de 3 bits)
+    .AM_PM(1'b0), 
+    .config_mode(2'b0), 
+    .cursor_location(2'b0), 
+    .formato_hora(1'b1), 
+    .estado_alarma(1'b0), 
+    .hsync(hsync), 
+    .vsync(vsync), 
+    .RGB(RGB)
+    );
+\t 
+memoria_registros_VGA instancia_memoria_registros_VGA 
+(
+    .clk(clk), 
+    .reset(reset), 
+    .cs_seg_hora(1'b0), 
+    .cs_min_hora(1'b0), 
+    .cs_hora_hora(1'b0), 
+    .cs_dia_fecha(1'b0), 
+    .cs_mes_fecha(1'b0), 
+    .cs_jahr_fecha(1'b0), 
+    .cs_seg_timer(1'b0), 
+    .cs_min_timer(1'b0), 
+    .cs_hora_timer(1'b0), 
+    .hold_seg_hora(hold_seg_hora), 
+    .hold_min_hora(hold_min_hora), 
+    .hold_hora_hora(hold_hora_hora), 
+    .hold_dia_fecha(hold_dia_fecha), 
+    .hold_mes_fecha(hold_mes_fecha), 
+    .hold_jahr_fecha(hold_jahr_fecha), 
+    .hold_seg_timer(hold_seg_timer), 
+    .hold_min_timer(hold_min_timer), 
+    .hold_hora_timer(hold_hora_timer), 
+    .hold_banderas_config(1'b1), 
+    .data_PicoBlaze(out_port), 
+    .count_seg_hora(8'b0), 
+    .count_min_hora(8'b0), 
+    .count_hora_hora(8'b0), 
+    .count_dia_fecha(8'b0), 
+    .count_mes_fecha(8'b0), 
+    .count_jahr_fecha(8'b0), 
+    .count_seg_timer(8'b0), 
+    .count_min_timer(8'b0), 
+    .count_hora_timer(8'b0), 
+    .out_seg_hora(out_seg_hora), 
+    .out_min_hora(out_min_hora), 
+    .out_hora_hora(out_hora_hora), 
+    .out_dia_fecha(out_dia_fecha), 
+    .out_mes_fecha(out_mes_fecha), 
+    .out_jahr_fecha(out_jahr_fecha), 
+    .out_seg_timer(out_seg_timer), 
+    .out_min_timer(out_min_timer), 
+    .out_hora_timer(out_hora_timer), 
+    .out_banderas_config()
+);
+
+deco_hold_registros instancia_deco_hold_registros (
+    .write_strobe(write_strobe), 
+    .port_id(port_id), 
+    .hold_seg_hora(hold_seg_hora), 
+    .hold_min_hora(hold_min_hora), 
+    .hold_hora_hora(hold_hora_hora), 
+    .hold_dia_fecha(hold_dia_fecha), 
+    .hold_mes_fecha(hold_mes_fecha), 
+    .hold_jahr_fecha(hold_jahr_fecha), 
+    .hold_seg_timer(hold_seg_timer), 
+    .hold_min_timer(hold_min_timer), 
+    .hold_hora_timer(hold_hora_timer)
+    );
+\t 
+escritor_lector_rtc_2 instancia_escritor_lector_rtc_2 (
+    .clk(clk), 
+    .reset(reset), 
+    .in_dato(out_port),
+\t .port_id(port_id),
+\t .write_strobe(write_strobe), 
+\t .k_write_strobe(k_write_strobe),
+    .read_strobe(read_strobe),
+    .reg_a_d(AD), 
+    .reg_cs(CS), 
+    .reg_rd(RD), 
+    .reg_wr(WR), 
+    .out_dato(out_dato), 
+    .flag_done(fin_lectura_escritura), 
+    .dato(dato)
+    );
+\t 
+controlador_teclado_ps2 instancia_controlador_teclado_ps2 (
+    .clk(clk), 
+    .reset(reset), 
+    .ps2data(ps2data), 
+    .ps2clk(ps2clk), 
+    .port_id(port_id), 
+    .read_strobe(read_strobe), 
+    .ascii_code(ascii_code)
+    );
+\t 
+//Decodificaci\xf3n del puerto de entrada del microcontrolador
+
+always@(posedge clk)
+begin
+\t\tcase (port_id) 
+\t\t8'h0F : in_port <= fin_lectura_escritura;
+\t\t8'h10 : in_port <= out_dato;
+\t\t8'h02 : in_port <= ascii_code;
+\t  default : in_port <= 8'bXXXXXXXX;  
+\tendcase
+end
+\t \t 
+endmodule
+
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: Jafet Chaves Barrantes
+// 
+// Create Date:    15:45:17 04/03/2016 
+// Design Name: 
+// Module Name:    contador_AD_DAY_2dig 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module contador_AD_DAY_2dig
+(
+input wire clk,
+input wire reset,
+input wire [3:0] en_count,
+input wire enUP,
+input wire enDOWN,
+output wire [7:0] data_DAY
+);
+
+localparam N = 5; // Para definir el n\xfamero de bits del contador (hasta 31->5 bits)
+//Declaraci\xf3n de se\xf1ales
+reg [N-1:0] q_act, q_next;
+wire [N-1:0] count_data;
+reg [3:0] digit1, digit0;
+
+//Descripci\xf3n del comportamiento
+always@(posedge clk, posedge reset)
+begin\t
+\t
+\tif(reset)
+\tbegin
+\t\tq_act <= 5'b0;
+\tend
+\t
+\telse
+\tbegin
+\t\tq_act <= q_next;
+\tend
+end
+
+
+//L\xf3gica de salida
+always@*
+begin
+
+\tif (en_count == 6)
+\tbegin
+\t\tif (enUP)
+\t\tbegin
+\t\t\tif (q_act >= 5'd30) q_next = 5'd0;
+\t\t\telse q_next = q_act + 5'd1;
+\t\tend
+\t\t
+\t\telse if (enDOWN)
+\t\tbegin
+\t\t\tif (q_act == 5'd0) q_next = 5'd30;
+\t\t\telse q_next = q_act - 5'd1;
+\t\tend
+\t\telse q_next = q_act;
+\tend
+\telse q_next = q_act;
+\t
+end
+
+assign count_data = q_act + 5'b1;//Suma 1 a todas las cuentas de 0->30 a 1->31
+
+//Decodificaci?n BCD (2 d?gitos)
+
+always@*
+begin
+case(count_data)
+
+5'd1: begin digit1 = 4'b0000; digit0 = 4'b0001; end
+5'd2: begin digit1 = 4'b0000; digit0 = 4'b0010; end
+5'd3: begin digit1 = 4'b0000; digit0 = 4'b0011; end
+5'd4: begin digit1 = 4'b0000; digit0 = 4'b0100; end
+5'd5: begin digit1 = 4'b0000; digit0 = 4'b0101; end
+5'd6: begin digit1 = 4'b0000; digit0 = 4'b0110; end
+5'd7: begin digit1 = 4'b0000; digit0 = 4'b0111; end
+5'd8: begin digit1 = 4'b0000; digit0 = 4'b1000; end
+5'd9: begin digit1 = 4'b0000; digit0 = 4'b1001; end
+
+5'd10: begin digit1 = 4'b0001; digit0 = 4'b0000; end
+5'd11: begin digit1 = 4'b0001; digit0 = 4'b0001; end
+5'd12: begin digit1 = 4'b0001; digit0 = 4'b0010; end
+5'd13: begin digit1 = 4'b0001; digit0 = 4'b0011; end
+5'd14: begin digit1 = 4'b0001; digit0 = 4'b0100; end
+5'd15: begin digit1 = 4'b0001; digit0 = 4'b0101; end
+5'd16: begin digit1 = 4'b0001; digit0 = 4'b0110; end
+5'd17: begin digit1 = 4'b0001; digit0 = 4'b0111; end
+5'd18: begin digit1 = 4'b0001; digit0 = 4'b1000; end
+5'd19: begin digit1 = 4'b0001; digit0 = 4'b1001; end
+
+5'd20: begin digit1 = 4'b0010; digit0 = 4'b0000; end
+5'd21: begin digit1 = 4'b0010; digit0 = 4'b0001; end
+5'd22: begin digit1 = 4'b0010; digit0 = 4'b0010; end
+5'd23: begin digit1 = 4'b0010; digit0 = 4'b0011; end
+5'd24: begin digit1 = 4'b0010; digit0 = 4'b0100; end
+5'd25: begin digit1 = 4'b0010; digit0 = 4'b0101; end
+5'd26: begin digit1 = 4'b0010; digit0 = 4'b0110; end
+5'd27: begin digit1 = 4'b0010; digit0 = 4'b0111; end
+5'd28: begin digit1 = 4'b0010; digit0 = 4'b1000; end
+5'd29: begin digit1 = 4'b0010; digit0 = 4'b1001; end
+
+5'd30: begin digit1 = 4'b0011; digit0 = 4'b0000; end
+5'd31: begin digit1 = 4'b0011; digit0 = 4'b0001; end
+
+default:  begin digit1 = 0; digit0 = 0; end
+endcase
+end
+
+assign data_DAY = {digit1,digit0};
+
+endmodule
+
+
+
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: Jafet Chaves Barrantes
+// 
+// Create Date:    20:32:40 05/17/2016 
+// Design Name: 
+// Module Name:    picture_timer 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module generador_imagenes
+(
+input clk,
+input reset,
+input wire video_on,//se\xf1al que indica que se encuentra en la regi\xf3n visible de resoluci\xf3n 640x480
+input wire [9:0] pixel_x, pixel_y,
+output wire pic_on,
+output wire [7:0] pic_RGB
+);
+
+//Declaraci\xf3n de constantes
+localparam pic_hora_XL = 256; //L\xedmite izquierdo
+localparam pic_hora_XR = 384; //L\xedmite derecho
+localparam pic_hora_YB = 64; //L\xedmite inferior
+localparam pic_hora_size = 8192;// (128x64)
+
+localparam pic_timer_XL = 416; //L\xedmite izquierdo
+localparam pic_timer_XR = 496; //L\xedmite derecho
+localparam pic_timer_YT = 416;\t//L\xedmite superior
+localparam pic_timer_YB = 479; //L\xedmite inferior
+localparam pic_timer_size = 2560;// (80x32)
+
+localparam pic_ring_XL = 512; //L\xedmite izquierdo
+localparam pic_ring_XR = 639; //L\xedmite derecho
+localparam pic_ring_YT = 128;\t//L\xedmite superior
+localparam pic_ring_YB = 191; //L\xedmite inferior
+localparam pic_ring_size = 8192;// (128x64)
+
+localparam pic_ringball_XL = 544; //L\xedmite izquierdo
+localparam pic_ringball_XR = 592; //L\xedmite derecho
+localparam pic_ringball_YT = 64;\t//L\xedmite superior
+localparam pic_ringball_YB = 112; //L\xedmite inferior
+localparam pic_ringball_size = 2304;// (48x48)
+
+localparam pic_logo_XR = 128; //L\xedmite derecho
+localparam pic_logo_YB = 16; //L\xedmite inferior
+localparam pic_logo_size = 2048;// (128x16)
+
+//Declaraci\xf3n de se\xf1ales
+reg [7:0] pic_RGB_aux;
+reg [7:0] colour_data_hora [0:pic_hora_size-1];\t//datos de los colores
+reg [7:0] colour_data_timer [0:pic_timer_size-1];\t//datos de los colores
+reg [7:0] colour_data_ring [0:pic_ring_size-1];\t//datos de los colores
+reg [7:0] colour_data_ringball [0:pic_ringball_size-1];\t//datos de los colores
+reg [7:0] colour_data_logo [0:pic_logo_size-1];\t//datos de los colores
+wire pic_hora_on, pic_timer_on, pic_ring_on, pic_ringball_on, pic_logo_on;
+
+reg [12:0] index_counter_hora_reg, index_counter_hora_next;
+wire [12:0] index_counter_hora;
+
+reg [11:0] index_counter_timer_reg, index_counter_timer_next;
+wire [11:0] index_counter_timer;
+
+reg [12:0] index_counter_ring_reg, index_counter_ring_next;
+wire [12:0] index_counter_ring;
+
+reg [11:0] index_counter_ringball_reg, index_counter_ringball_next;
+wire [11:0] index_counter_ringball;
+
+reg [10:0] index_counter_logo_reg, index_counter_logo_next;
+wire [10:0] index_counter_logo;
+
+//Contadores para recorrer la memoria
+always @(posedge clk)//Todos los contadores tienen la misma l\xf3gica de asignaci\xf3n de estados
+\tbegin
+\t\tif(reset)
+\t\t\tbegin
+\t\t\tindex_counter_hora_reg <= 0;
+\t\t\tindex_counter_timer_reg <= 0;
+\t\t\tindex_counter_ring_reg <= 0;
+\t\t\tindex_counter_ringball_reg <= 0;
+\t\t\tindex_counter_logo_reg <= 0;
+\t\t\tend
+\t\telse
+\t\t\tbegin
+\t\t\tindex_counter_hora_reg <= index_counter_hora_next;
+\t\t\tindex_counter_timer_reg <= index_counter_timer_next;
+\t\t\tindex_counter_ring_reg <= index_counter_ring_next;
+\t\t\tindex_counter_ringball_reg <= index_counter_ringball_next;
+\t\t\tindex_counter_logo_reg <= index_counter_logo_next;
+\t\t\tend\t\t
+\tend
+\t
+
+//===================================================
+// Imagen HORA
+//===================================================
+initial
+$readmemh (""hora.list"", colour_data_hora);//Leer datos RBG de archivo de texto, sintetiza una ROM
+
+//Imprime la imagen de hora dentro de la regi\xf3n
+assign pic_hora_on = (pic_hora_XL<=pixel_x)&&(pixel_x<=pic_hora_XR)&&(pixel_y<=pic_hora_YB);//Para saber cuando se est\xe1 imprimiendo la imagen
+
+always@*
+\tbegin
+\t\tif(pic_hora_on)
+\t\t\tbegin
+\t\t\tindex_counter_hora_next = index_counter_hora_reg + 1\'b1;
+\t\t\tend
+\t\t\t
+\t\telse
+\t\t\tbegin
+\t\t\tindex_counter_hora_next = 0;
+\t\t\tend
+\tend
+
+assign index_counter_hora = index_counter_hora_reg;
+
+//===================================================
+// Imagen TIMER
+//===================================================
+initial
+$readmemh (""timer.list"", colour_data_timer);//Leer datos RBG de archivo de texto, sintetiza una ROM
+
+//Imprime la imagen de hora dentro de la regi\xf3n
+assign pic_timer_on = (pic_timer_XL<=pixel_x)&&(pixel_x<=pic_timer_XR)&&(pic_timer_YT<=pixel_y)&&(pixel_y<=pic_timer_YB);//Para saber cuando se est\xe1 imprimiendo la imagen
+
+always@*
+\tbegin
+\t\tif(pic_timer_on)
+\t\t\tbegin
+\t\t\tindex_counter_timer_next = index_counter_timer_reg + 1\'b1;
+\t\t\tend
+\t\t\t
+\t\telse
+\t\t\tbegin
+\t\t\tindex_counter_timer_next = 0;
+\t\t\tend
+\tend
+
+assign index_counter_timer = index_counter_timer_reg;
+
+//===================================================
+// Imagen RING
+//===================================================
+initial
+$readmemh (""ring.list"", colour_data_ring);//Leer datos RBG de archivo de texto, sintetiza una ROM
+
+//Imprime la imagen de hora dentro de la regi\xf3n
+assign pic_ring_on = (pic_ring_XL<=pixel_x)&&(pixel_x<=pic_ring_XR)&&(pic_ring_YT<=pixel_y)&&(pixel_y<=pic_ring_YB);//Para saber cuando se est\xe1 imprimiendo la imagen
+
+always@*
+\tbegin
+\t\tif(pic_ring_on)
+\t\t\tbegin
+\t\t\tindex_counter_ring_next = index_counter_ring_reg + 1\'b1;
+\t\t\tend
+\t\t\t
+\t\telse
+\t\t\tbegin
+\t\t\tindex_counter_ring_next = 0;
+\t\t\tend
+\tend
+
+assign index_counter_ring = index_counter_ring_reg;
+
+//===================================================
+// Imagen RING BALL
+//===================================================
+initial
+$readmemh (""ring_ball.list"", colour_data_ringball);//Leer datos RBG de archivo de texto, sintetiza una ROM
+
+//Imprime la imagen de hora dentro de la regi\xf3n
+assign pic_ringball_on = (pic_ringball_XL<=pixel_x)&&(pixel_x<=pic_ringball_XR)&&(pic_ringball_YT<=pixel_y)&&(pixel_y<=pic_ringball_YB);//Para saber cuando se est\xe1 imprimiendo la imagen
+
+always@*
+\tbegin
+\t\tif(pic_ringball_on)
+\t\t\tbegin
+\t\t\tindex_counter_ringball_next = index_counter_ringball_reg + 1\'b1;
+\t\t\tend
+\t\t\t
+\t\telse
+\t\t\tbegin
+\t\t\tindex_counter_ringball_next = 0;
+\t\t\tend
+\tend
+
+assign index_counter_ringball = index_counter_ringball_reg;
+
+//===================================================
+// Imagen LOGO
+//===================================================
+initial
+$readmemh (""logo.list"", colour_data_logo);//Leer datos RBG de archivo de texto, sintetiza una ROM
+
+//Imprime la imagen de hora dentro de la regi\xf3n
+assign pic_logo_on = (pixel_x<=pic_logo_XR)&&(pixel_y<=pic_logo_YB);//Para saber cuando se est\xe1 imprimiendo la imagen
+
+always@*
+\tbegin
+\t\tif(pic_logo_on)
+\t\t\tbegin
+\t\t\tindex_counter_logo_next = index_counter_logo_reg + 1\'b1;
+\t\t\tend
+\t\t\t
+\t\telse
+\t\t\tbegin
+\t\t\tindex_counter_logo_next = 0;
+\t\t\tend
+\tend
+
+assign index_counter_logo = index_counter_logo_reg;
+
+//------------------------------------------------------------------------------------------------------------------------
+
+//Multiplexa el RGB
+always @*
+begin\t
+\tif(~video_on)
+\t\tpic_RGB_aux = 12\'b0;//fondo negro
+\t
+\telse 
+\t\tif(pic_hora_on) pic_RGB_aux = colour_data_hora[index_counter_hora];
+\t\telse if (pic_timer_on) pic_RGB_aux = colour_data_timer[index_counter_timer];
+\t\telse if (pic_ring_on) pic_RGB_aux = colour_data_ring[index_counter_ring];
+\t\telse if (pic_ringball_on) pic_RGB_aux = colour_data_ringball[index_counter_ringball];
+\t\telse if (pic_logo_on) pic_RGB_aux = colour_data_logo[index_counter_logo];
+\t\telse pic_RGB_aux = 12\'b0;//fondo negro\t
+end
+
+//assign pic_RGB = \t{pic_RGB_aux[7:5],1\'b0,pic_RGB_aux[4:2],1\'b0,pic_RGB_aux[1:0],2\'b0};\t//Rellena pic_RGB para pasar de 8 bits a 12 bits
+assign pic_RGB = pic_RGB_aux;//Para 8 bits (Nexys 3)
+assign pic_on = pic_hora_on | pic_timer_on| pic_ring_on| pic_ringball_on| pic_logo_on;
+
+endmodule
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: Jafet Chaves Barrantes
+// 
+// Create Date:    16:10:41 03/22/2016 
+// Design Name: 
+// Module Name:    Clock_screen_top 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module controlador_VGA
+(
+input wire clock, reset,
+input wire [7:0] in_dato, port_id,
+input wire write_strobe, k_write_strobe,
+output wire [7:0]out_seg_hora,out_min_hora,out_hora_hora,
+output wire [7:0]out_dia_fecha,out_mes_fecha,out_jahr_fecha,
+output wire [7:0]out_seg_timer,out_min_timer,out_hora_timer,
+output reg alarma_sonora,//Para sacar la se\xf1al para la alarma sonora
+output wire hsync, vsync,
+output wire [7:0] RGB
+//output wire pixel_tick
+);
+
+
+//Declaraci\xf3n de conexiones internas
+wire [9:0] pixel_x,pixel_y;
+wire video_on; 
+wire pixel_tick;
+reg [7:0] RGB_reg, RGB_next;
+wire text_on, graph_on, pic_on;
+wire [7:0] fig_RGB, text_RGB, pic_RGB;
+wire pic_ring_on;
+wire pic_ringball_on, AMPM_on;
+
+//Se\xf1ales de selecci\xf3n cs para los registros
+wire cs_seg_hora; 
+wire cs_min_hora; 
+wire cs_hora_hora; 
+wire cs_dia_fecha; 
+wire cs_mes_fecha; 
+wire cs_jahr_fecha; 
+wire cs_seg_timer;
+wire cs_min_timer; 
+wire cs_hora_timer;
+
+//Se\xf1ales de control hold para los registros
+wire hold_seg_hora; 
+wire hold_min_hora; 
+wire hold_hora_hora; 
+wire hold_dia_fecha; 
+wire hold_mes_fecha; 
+wire hold_jahr_fecha; 
+wire hold_seg_timer;
+wire hold_min_timer; 
+wire hold_hora_timer;
+wire hold_banderas_config;
+
+//Salida de los contadores hacia los registros
+wire [7:0]count_seg_hora; 
+wire [7:0]count_min_hora; 
+wire [7:0]count_hora_hora; 
+wire [7:0]count_dia_fecha; 
+wire [7:0]count_mes_fecha; 
+wire [7:0]count_jahr_fecha; 
+wire [7:0]count_seg_timer;
+wire [7:0]count_min_timer; 
+wire [7:0]count_hora_timer;
+
+wire [1:0]out_banderas_config;
+ 
+wire [1:0] config_mode, cursor_location;
+wire AM_PM;
+
+//Para generar parpadeo de 4 Hz
+// Bits del contador para generar una se\xf1al peri\xf3dica de (2^N)*10ns
+localparam N =24;//~3Hz
+
+reg [N-1:0] blink_reg;
+reg blink;
+
+localparam N_cursor = 25;//~2Hz
+
+reg [N_cursor-1:0] blink_cursor_reg;
+reg blink_cursor;
+
+//Instanciaciones
+
+timing_generator_VGA instancia_timing_generator_VGA
+(
+.clk(clock),
+.reset(reset),
+.hsync(hsync),
+.vsync(vsync),
+.video_on(video_on),
+.p_tick(pixel_tick),
+.pixel_x(pixel_x), 
+.pixel_y(pixel_y)
+);
+
+generador_figuras instancia_generador_figuras
+(
+.video_on(video_on),//se\xf1al que indica que se encuentra en la regi\xf3n visible de resoluci\xf3n 640x480
+.pixel_x(pixel_x), 
+.pixel_y(pixel_y),//coordenadas xy de cada pixel
+.graph_on(graph_on),
+.fig_RGB(fig_RGB) //12 bpp (4 bits para cada color)
+);
+
+generador_caracteres instancia_generador_caracteres
+(
+.clk(clock),
+.digit0_HH(out_hora_hora[3:0]), .digit1_HH(out_hora_hora[7:4]), .digit0_MM(out_min_hora[3:0]), .digit1_MM(out_min_hora[7:4]), .digit0_SS(out_seg_hora[3:0]), .digit1_SS(out_seg_hora[7:4]),//
+.digit0_DAY(out_dia_fecha[3:0]), .digit1_DAY(out_dia_fecha[7:4]), .digit0_MES(out_mes_fecha[3:0]), .digit1_MES(out_mes_fecha[7:4]), .digit0_YEAR(out_jahr_fecha[3:0]), .digit1_YEAR(out_jahr_fecha[7:4]),//
+.digit0_HH_T(out_hora_timer[3:0]), .digit1_HH_T(out_hora_timer[7:4]), .digit0_MM_T(out_min_timer[3:0]), .digit1_MM_T(out_min_timer[7:4]), .digit0_SS_T(out_seg_timer[3:0]), .digit1_SS_T(out_seg_timer[7:4]),//Decenas y unidades para los n\xfameros en pantalla (18 inputs de 3 bits)
+.AM_PM(AM_PM),//Entrada para conocer si en la informaci\xf3n de hora se despliega AM o PM
+.config_mode(config_mode),
+.cursor_location(cursor_location),//Marca la posici\xf3n del cursor en modo configuraci\xf3n
+.pixel_x(pixel_x), .pixel_y(pixel_y),
+.parpadeo(blink_cursor),
+.text_on(text_on),
+.AMPM_on(AMPM_on), //Localizaci\xf3n de esos respectivos textos
+.text_RGB(text_RGB) //8 bpp
+);
+
+generador_imagenes instancia_generador_imagenes
+(
+.video_on(video_on),//se\xf1al que indica que se encuentra en la regi\xf3n visible de resoluci\xf3n 640x480
+.pixel_x(pixel_x), 
+.pixel_y(pixel_y),
+.pic_ring_on(pic_ring_on),
+.pic_ringball_on(pic_ringball_on),
+.pic_on(pic_on),
+.pic_RGB(pic_RGB)
+);
+
+memoria_registros_VGA instancia_memoria_registros_VGA 
+(
+    .clk(clock), 
+    .reset(reset),
+\t .formato_hora(out_banderas_config[1]),
+    .cs_seg_hora(cs_seg_hora), 
+    .cs_min_hora(cs_min_hora), 
+    .cs_hora_hora(cs_hora_hora), 
+    .cs_dia_fecha(cs_dia_fecha), 
+    .cs_mes_fecha(cs_mes_fecha), 
+    .cs_jahr_fecha(cs_jahr_fecha), 
+    .cs_seg_timer(cs_seg_timer), 
+    .cs_min_timer(cs_min_timer), 
+    .cs_hora_timer(cs_hora_timer), 
+    .hold_seg_hora(hold_seg_hora), 
+    .hold_min_hora(hold_min_hora), 
+    .hold_hora_hora(hold_hora_hora), 
+    .hold_dia_fecha(hold_dia_fecha), 
+    .hold_mes_fecha(hold_mes_fecha), 
+    .hold_jahr_fecha(hold_jahr_fecha), 
+    .hold_seg_timer(hold_seg_timer), 
+    .hold_min_timer(hold_min_timer), 
+    .hold_hora_timer(hold_hora_timer), 
+    .hold_banderas_config(hold_banderas_config), 
+    .data_PicoBlaze(in_dato), 
+    .count_seg_hora(count_seg_hora), 
+    .count_min_hora(count_min_hora), 
+    .count_hora_hora(count_hora_hora), 
+    .count_dia_fecha(count_dia_fecha), 
+    .count_mes_fecha(count_mes_fecha), 
+    .count_jahr_fecha(count_jahr_fecha), 
+    .count_seg_timer(count_seg_timer), 
+    .count_min_timer(count_min_timer), 
+    .count_hora_timer(count_hora_timer), 
+    .out_seg_hora(out_seg_hora), 
+    .out_min_hora(out_min_hora), 
+    .out_hora_hora(out_hora_hora), 
+    .out_dia_fecha(out_dia_fecha), 
+    .out_mes_fecha(out_mes_fecha), 
+    .out_jahr_fecha(out_jahr_fecha), 
+    .out_seg_timer(out_seg_timer), 
+    .out_min_timer(out_min_timer), 
+    .out_hora_timer(out_hora_timer), 
+    .out_banderas_config(out_banderas_config),
+\t .AM_PM(AM_PM)
+);
+
+contadores_configuracion instancia_contadores_configuracion (
+    .clk(clock), 
+    .reset(reset), 
+    .in_dato(in_dato), 
+    .port_id(port_id), 
+    .write_strobe(write_strobe), 
+    .k_write_strobe(k_write_strobe), 
+    .btn_data_SS(count_seg_hora), 
+    .btn_data_MM(count_min_hora), 
+    .btn_data_HH(count_hora_hora), 
+    .btn_data_YEAR(count_jahr_fecha), 
+    .btn_data_MES(count_mes_fecha), 
+    .btn_data_DAY(count_dia_fecha), 
+    .btn_data_SS_T(count_seg_timer), 
+    .btn_data_MM_T(count_min_timer), 
+    .btn_data_HH_T(count_hora_timer), 
+    .cursor_location(cursor_location), 
+    .config_mode(config_mode)
+    );
+
+deco_hold_registros instancia_deco_hold_registros (
+    .write_strobe(write_strobe), 
+    .port_id(port_id),
+\t .config_mode(config_mode),
+    .hold_seg_hora(hold_seg_hora), 
+    .hold_min_hora(hold_min_hora), 
+    .hold_hora_hora(hold_hora_hora), 
+    .hold_dia_fecha(hold_dia_fecha), 
+    .hold_mes_fecha(hold_mes_fecha), 
+    .hold_jahr_fecha(hold_jahr_fecha), 
+    .hold_seg_timer(hold_seg_timer), 
+    .hold_min_timer(hold_min_timer), 
+    .hold_hora_timer(hold_hora_timer),
+\t .hold_banderas_config(hold_banderas_config)
+    );
+\t 
+decodificador_cs_registros instancia_decodificador_cs_registros (
+    .funcion_conf(config_mode), 
+    .cs_seg_hora(cs_seg_hora), 
+    .cs_min_hora(cs_min_hora), 
+    .cs_hora_hora(cs_hora_hora), 
+    .cs_dia_fecha(cs_dia_fecha), 
+    .cs_mes_fecha(cs_mes_fecha), 
+    .cs_jahr_fecha(cs_jahr_fecha), 
+    .cs_seg_timer(cs_seg_timer), 
+    .cs_min_timer(cs_min_timer), 
+    .cs_hora_timer(cs_hora_timer)
+    );
+
+//=============================================
+// Contador para generar pulso de parpadeo
+//=============================================
+
+always @(posedge clock, posedge reset)
+begin
+\tif (reset)begin blink_reg <= 0; blink <= 0; end
+\t
+\telse
+\tbegin
+\t\tif (blink_reg == 24\'d16666666)
+\t\t\tbegin
+\t\t\tblink_reg <= 0;
+\t\t\tblink <= ~blink;
+\t\t\tend
+\t\telse
+\t\t\tblink_reg <= blink_reg + 1\'b1;
+\tend
+end
+
+//Generaci\xf3n de alarma sonora
+always@*
+begin
+\tif (out_banderas_config[0] && blink) alarma_sonora = 1\'b1;
+\telse alarma_sonora = 1\'b0;
+end
+
+//Parpadeo cursor
+always @(posedge clock, posedge reset)
+begin
+\tif (reset)begin blink_cursor_reg <= 0; blink_cursor <= 0; end
+\t
+\telse
+\tbegin
+\t\tif (blink_cursor_reg == 25\'d24999999)
+\t\t\tbegin
+\t\t\tblink_cursor_reg <= 0;
+\t\t\tblink_cursor <= ~blink_cursor;
+\t\t\tend
+\t\telse
+\t\t\tblink_cursor_reg <= blink_cursor_reg + 1\'b1;
+\tend
+end\t\t
+//____________________________________________________________________________________________________________
+
+//Multiplexaci\xf3n entre texto, figuras o im\xe1genes
+
+always@*
+begin
+
+\tif(~video_on)
+\tRGB_next = ""0"";//Fuera la pantalla visible
+\t
+\telse
+\t\tif(text_on) RGB_next = text_RGB;
+\t\telse if (AMPM_on && out_banderas_config[1]) RGB_next = text_RGB;
+\t\telse if (graph_on) RGB_next = fig_RGB;
+\t\telse if (pic_on) RGB_next = pic_RGB;
+\t\telse if (pic_ringball_on && out_banderas_config[0] && blink) RGB_next = pic_RGB;
+\t\telse if (pic_ring_on && out_banderas_config[0] && blink) RGB_next = pic_RGB;
+\t\telse RGB_next = 8\'h00;//Fondo negro
+end
+
+always @(posedge clock)
+if (pixel_tick) RGB_reg <= RGB_next;
+
+//Salida al monitor VGA
+assign RGB = RGB_reg;
+
+endmodule
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    14:51:45 05/17/2016 
+// Design Name: 
+// Module Name:    ROM_16x32 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module ROM_16x32(
+\t input wire clk,
+    input wire [11:0] addr,
+    output reg [15:0] data
+\t );
+\t 
+\t reg [11:0] addr_reg;
+\t 
+\t always @(posedge clk) 
+      addr_reg <= addr;\t
+\t 
+\t always @*
+\t\tcase (addr_reg)
+\t\t//code x00 y x01
+         12\'h000: data = 16\'b0000000000000000; // 
+         12\'h001: data = 16\'b0000000000000000; // 
+         12\'h002: data = 16\'b0000000000000000; // 
+         12\'h003: data = 16\'b0000000000000000; // 
+         12\'h004: data = 16\'b0000000000000000; // 
+         12\'h005: data = 16\'b0000000000000000; // 
+         12\'h006: data = 16\'b0000000000000000; // 
+         12\'h007: data = 16\'b0000000000000000; // 
+         12\'h008: data = 16\'b0000000000000000; // 
+         12\'h009: data = 16\'b0000000000000000; // 
+         12\'h00a: data = 16\'b0000000000000000; // 
+         12\'h00b: data = 16\'b0000000000000000; // 
+         12\'h00c: data = 16\'b0000000000000000; // 
+         12\'h00d: data = 16\'b0000000000000000; // 
+         12\'h00e: data = 16\'b0000000000000000; // 
+         12\'h00f: data = 16\'b0000000000000000; //
+\t\t\t12\'h010: data = 16\'b0000000000000000; // 
+         12\'h011: data = 16\'b0000000000000000; // 
+         12\'h012: data = 16\'b0000000000000000; // 
+         12\'h013: data = 16\'b0000000000000000; // 
+         12\'h014: data = 16\'b0000000000000000; // 
+         12\'h015: data = 16\'b0000000000000000; // 
+         12\'h016: data = 16\'b0000000000000000; // 
+         12\'h017: data = 16\'b0000000000000000; // 
+         12\'h018: data = 16\'b0000000000000000; // 
+         12\'h019: data = 16\'b0000000000000000; // 
+         12\'h01a: data = 16\'b0000000000000000; // 
+         12\'h01b: data = 16\'b0000000000000000; // 
+         12\'h01c: data = 16\'b0000000000000000; // 
+         12\'h01d: data = 16\'b0000000000000000; // 
+         12\'h01e: data = 16\'b0000000000000000; // 
+         12\'h01f: data = 16\'b0000000000000000; //
+
+\t\t//code x5E0 y x5F0 ""/""
+         12\'h5e0: data = 16\'b0000000000000000; // 
+         12\'h5e1: data = 16\'b0000000000000000; // 
+         12\'h5e2: data = 16\'b0000000000000000; // 
+         12\'h5e3: data = 16\'b0000000000000000; // 
+         12\'h5e4: data = 16\'b0000000000000000; // 
+         12\'h5e5: data = 16\'b0000000000000000; // 
+         12\'h5e6: data = 16\'b0000000000000000; // 
+         12\'h5e7: data = 16\'b0000000000000000; //                 
+         12\'h5e8: data = 16\'b0000000000000110; //              ++
+         12\'h5e9: data = 16\'b0000000000000111; //             +++ 
+         12\'h5ea: data = 16\'b0000000000001110; //            +++ 
+         12\'h5eb: data = 16\'b0000000000011100; //           +++ 
+         12\'h5ec: data = 16\'b0000000000111000; //          +++   
+         12\'h5ed: data = 16\'b0000000001110000; //         +++    
+         12\'h5ee: data = 16\'b0000000011100000; //        +++     
+         12\'h5ef: data = 16\'b0000000111000000; //       +++      
+\t\t\t12\'h5f0: data = 16\'b0000001110000000; //      +++       
+         12\'h5f1: data = 16\'b0000011100000000; //     +++        
+         12\'h5f2: data = 16\'b0000111000000000; //    +++         
+         12\'h5f3: data = 16\'b0001110000000000; //   +++          
+         12\'h5f4: data = 16\'b0011100000000000; //  +++           
+         12\'h5f5: data = 16\'b0111000000000000; // +++            
+         12\'h5f6: data = 16\'b1110000000000000; //+++             
+         12\'h5f7: data = 16\'b1100000000000000; //++              
+         12\'h5f8: data = 16\'b0000000000000000; //                 
+         12\'h5f9: data = 16\'b0000000000000000; // 
+         12\'h5fa: data = 16\'b0000000000000000; // 
+         12\'h5fb: data = 16\'b0000000000000000; // 
+         12\'h5fc: data = 16\'b0000000000000000; // 
+         12\'h5fd: data = 16\'b0000000000000000; // 
+         12\'h5fe: data = 16\'b0000000000000000; // 
+         12\'h5ff: data = 16\'b0000000000000000; //
+\t\t\t
+\t\t//code x60 y x61      NUMERO 0
+         12\'h600: data = 16\'b0000000000000000; // 
+         12\'h601: data = 16\'b0000000000000000; // 
+         12\'h602: data = 16\'b0000000000000000; // 
+         12\'h603: data = 16\'b0000000000000000; // 
+         12\'h604: data = 16\'b0000000000000000; // 
+         12\'h605: data = 16\'b0001111111100000; //    ********
+         12\'h606: data = 16\'b0011111111110000; //   **********
+         12\'h607: data = 16\'b0111100001111000; //  ****    ****
+         12\'h608: data = 16\'b1111000000111100; // ****      ****
+         12\'h609: data = 16\'b1111000000111100; // ****      ****
+         12\'h60a: data = 16\'b1111000000111100; // ****      ****
+         12\'h60b: data = 16\'b1111000001111100; // ****     *****
+         12\'h60c: data = 16\'b1111000011111100; // ****    ******
+         12\'h60d: data = 16\'b1111000111111100; // ****   *******
+         12\'h60e: data = 16\'b1111001111111100; // ****  ********
+         12\'h60f: data = 16\'b1111011111111100; // **** *********
+\t\t\t12\'h610: data = 16\'b1111111110111100; // ********* ****
+         12\'h611: data = 16\'b1111111100111100; // ********  ****
+         12\'h612: data = 16\'b1111111000111100; // *******   ****
+         12\'h613: data = 16\'b1111110000111100; // ******    ****
+         12\'h614: data = 16\'b1111100000111100; // *****     ****
+         12\'h615: data = 16\'b1111000000111100; // ****      ****
+         12\'h616: data = 16\'b1111000000111100; // ****      ****
+         12\'h617: data = 16\'b1111000000111100; // ****      ****
+         12\'h618: data = 16\'b0111100001111000; //  ****    ****
+         12\'h619: data = 16\'b0011111111110000; //   **********
+         12\'h61a: data = 16\'b0001111111100000; //    ********
+         12\'h61b: data = 16\'b0000000000000000; // 
+         12\'h61c: data = 16\'b0000000000000000; // 
+         12\'h61d: data = 16\'b0000000000000000; // 
+         12\'h61e: data = 16\'b0000000000000000; // 
+         12\'h61f: data = 16\'b0000000000000000; //
+\t\t\t
+\t\t//code x62 y x63      NUMERO 1
+         12\'h620: data = 16\'b0000000000000000; // 
+         12\'h621: data = 16\'b0000000000000000; // 
+         12\'h622: data = 16\'b0000000000000000; // 
+         12\'h623: data = 16\'b0000000000000000; // 
+         12\'h624: data = 16\'b0000000000000000; // 
+         12\'h625: data = 16\'b0000000001000000; //          *
+         12\'h626: data = 16\'b0000000011000000; //         **
+         12\'h627: data = 16\'b0000000111000000; //        ***
+         12\'h628: data = 16\'b0000001111000000; //       ****
+         12\'h629: data = 16\'b0000011111000000; //      *****
+         12\'h62a: data = 16\'b0000111111000000; //     ******
+         12\'h62b: data = 16\'b0001111111000000; //    *******
+         12\'h62c: data = 16\'b0011111111000000; //   ********    
+         12\'h62d: data = 16\'b0000001111000000; //       ****    
+         12\'h62e: data = 16\'b0000001111000000; //       ****    
+         12\'h62f: data = 16\'b0000001111000000; //       ****    
+\t\t\t12\'h630: data = 16\'b0000001111000000; //       ****    
+         12\'h631: data = 16\'b0000001111000000; //       ****    
+         12\'h632: data = 16\'b0000001111000000; //       ****    
+         12\'h633: data = 16\'b0000001111000000; //       ****    
+         12\'h634: data = 16\'b0000001111000000; //       ****    
+         12\'h635: data = 16\'b0000001111000000; //       ****    
+         12\'h636: data = 16\'b0000001111000000; //       ****    
+         12\'h637: data = 16\'b0000001111000000; //       ****    
+         12\'h638: data = 16\'b0000001111000000; //       ****    
+         12\'h639: data = 16\'b0011111111111100; //   ************
+         12\'h63a: data = 16\'b0011111111111100; //   ************
+         12\'h63b: data = 16\'b0000000000000000; // 
+         12\'h63c: data = 16\'b0000000000000000; // 
+         12\'h63d: data = 16\'b0000000000000000; // 
+         12\'h63e: data = 16\'b0000000000000000; // 
+         12\'h63f: data = 16\'b0000000000000000; //
+\t\t
+\t\t//code x64 y x65      NUMERO 2
+         12\'h640: data = 16\'b0000000000000000; // 
+         12\'h641: data = 16\'b0000000000000000; // 
+         12\'h642: data = 16\'b0000000000000000; // 
+         12\'h643: data = 16\'b0000000000000000; // 
+         12\'h644: data = 16\'b0000000000000000; // 
+         12\'h645: data = 16\'b0000111111110000; //     ********
+         12\'h646: data = 16\'b0001111111111000; //    **********
+         12\'h647: data = 16\'b0011110001111100; //   ****   *****
+         12\'h648: data = 16\'b0111100000111100; //  ****     ****
+         12\'h649: data = 16\'b1111000000111100; // ****      ****
+         12\'h64a: data = 16\'b1111000000111100; // ****      ****
+         12\'h64b: data = 16\'b0000000000111100; //           ****
+         12\'h64c: data = 16\'b0000000000111100; //           ****
+         12\'h64d: data = 16\'b0000000001111000; //          ****
+         12\'h64e: data = 16\'b0000000011110000; //         ****    
+         12\'h64f: data = 16\'b0000000111100000; //        ****    
+\t\t\t12\'h650: data = 16\'b0000001111000000; //       ****    
+         12\'h651: data = 16\'b0000011110000000; //      ****    
+         12\'h652: data = 16\'b0000111100000000; //     ****    
+         12\'h653: data = 16\'b0001111000000000; //    ****    
+         12\'h654: data = 16\'b0011110000000000; //   ****    
+         12\'h655: data = 16\'b0111100000000000; //  ****    
+         12\'h656: data = 16\'b1111000000000000; // ****          
+         12\'h657: data = 16\'b1111000000111100; // ****      ****
+         12\'h658: data = 16\'b1111000000111100; // ****      ****    
+         12\'h659: data = 16\'b1111111111111100; // **************
+         12\'h65a: data = 16\'b1111111111111100; // **************
+         12\'h65b: data = 16\'b0000000000000000; // 
+         12\'h65c: data = 16\'b0000000000000000; // 
+         12\'h65d: data = 16\'b0000000000000000; // 
+         12\'h65e: data = 16\'b0000000000000000; // 
+         12\'h65f: data = 16\'b0000000000000000; //
+\t\t\t
+\t\t//code x66 y x67      NUMERO 3
+         12\'h660: data = 16\'b0000000000000000; // 
+         12\'h661: data = 16\'b0000000000000000; // 
+         12\'h662: data = 16\'b0000000000000000; // 
+         12\'h663: data = 16\'b0000000000000000; // 
+         12\'h664: data = 16\'b0000000000000000; // 
+         12\'h665: data = 16\'b0001111111100000; //    ********
+         12\'h666: data = 16\'b0011111111110000; //   **********
+         12\'h667: data = 16\'b0111100001111000; //  ****    ****
+         12\'h668: data = 16\'b1111000000111100; // ****      ****
+         12\'h669: data = 16\'b0000000000111100; //           ****
+         12\'h66a: data = 16\'b0000000000111100; //           ****
+         12\'h66b: data = 16\'b0000000000111100; //           ****
+         12\'h66c: data = 16\'b0000000000111100; //           ****
+         12\'h66d: data = 16\'b0000000001111000; //          ****
+         12\'h66e: data = 16\'b0000011111110000; //      *******    
+         12\'h66f: data = 16\'b0000011111100000; //      ******    
+\t\t\t12\'h670: data = 16\'b0000011111110000; //      *******    
+         12\'h671: data = 16\'b0000000001111000; //          ****    
+         12\'h672: data = 16\'b0000000000111100; //           ****    
+         12\'h673: data = 16\'b0000000000111100; //           ****    
+         12\'h674: data = 16\'b0000000000111100; //           ****    
+         12\'h675: data = 16\'b0000000000111100; //           ****    
+         12\'h676: data = 16\'b0000000000111100; //           ****          
+         12\'h677: data = 16\'b1111000000111100; // ****      ****
+         12\'h678: data = 16\'b0111100001111000; //  ****    ****    
+         12\'h679: data = 16\'b0011111111110000; //   **********
+         12\'h67a: data = 16\'b0001111111100000; //    ********
+         12\'h67b: data = 16\'b0000000000000000; // 
+         12\'h67c: data = 16\'b0000000000000000; // 
+         12\'h67d: data = 16\'b0000000000000000; // 
+         12\'h67e: data = 16\'b0000000000000000; // 
+         12\'h67f: data = 16\'b0000000000000000; //
+\t\t\t
+\t\t//code x68 y x69      NUMERO 4
+         12\'h680: data = 16\'b0000000000000000; // 
+         12\'h681: data = 16\'b0000000000000000; // 
+         12\'h682: data = 16\'b0000000000000000; // 
+         12\'h683: data = 16\'b0000000000000000; // 
+         12\'h684: data = 16\'b0000000000000000; // 
+         12\'h685: data = 16\'b0000000000010000; //            *
+         12\'h686: data = 16\'b0000000000110000; //           **
+         12\'h687: data = 16\'b0000000001110000; //          ***
+         12\'h688: data = 16\'b0000000011110000; //         ****
+         12\'h689: data = 16\'b0000000111110000; //        *****
+         12\'h68a: data = 16\'b0000001111110000; //       ******
+         12\'h68b: data = 16\'b0000011111110000; //      *******
+         12\'h68c: data = 16\'b0000111011110000; //     *** ****    
+         12\'h68d: data = 16\'b0001110011110000; //    ***  ****  
+         12\'h68e: data = 16\'b0011100011110000; //   ***   **** 
+         12\'h68f: data = 16\'b0111000011110000; //  ***    ****    
+\t\t\t12\'h690: data = 16\'b1111111111111100; // **************    
+         12\'h691: data = 16\'b1111111111111100; // **************    
+         12\'h692: data = 16\'b0000000011110000; //         ****    
+         12\'h693: data = 16\'b0000000011110000; //         ****    
+         12\'h694: data = 16\'b0000000011110000; //         ****    
+         12\'h695: data = 16\'b0000000011110000; //         ****    
+         12\'h696: data = 16\'b0000000011110000; //         ****    
+         12\'h697: data = 16\'b0000000011110000; //         ****    
+         12\'h698: data = 16\'b0000000011110000; //         ****    
+         12\'h699: data = 16\'b0000000011110000; //         ****
+         12\'h69a: data = 16\'b0000000111111000; //        ******
+         12\'h69b: data = 16\'b0000000000000000; // 
+         12\'h69c: data = 16\'b0000000000000000; // 
+         12\'h69d: data = 16\'b0000000000000000; // 
+         12\'h69e: data = 16\'b0000000000000000; // 
+         12\'h69f: data = 16\'b0000000000000000; //
+\t\t\t
+\t\t//code x6a y x6b      NUMERO 5
+         12\'h6a0: data = 16\'b0000000000000000; // 
+         12\'h6a1: data = 16\'b0000000000000000; // 
+         12\'h6a2: data = 16\'b0000000000000000; // 
+         12\'h6a3: data = 16\'b0000000000000000; // 
+         12\'h6a4: data = 16\'b0000000000000000; // 
+         12\'h6a5: data = 16\'b1111111111111100; // **************
+         12\'h6a6: data = 16\'b1111111111111100; // **************
+         12\'h6a7: data = 16\'b1111000000000000; // ****  
+         12\'h6a8: data = 16\'b1111000000000000; // ****      
+         12\'h6a9: data = 16\'b1111000000000000; // ****      
+         12\'h6aa: data = 16\'b1111000000000000; // ****      
+         12\'h6ab: data = 16\'b1111000000000000; // ****    
+         12\'h6ac: data = 16\'b1111000000000000; // ****   
+         12\'h6ad: data = 16\'b1111111111100000; // **********
+         12\'h6ae: data = 16\'b1111111111110000; // ************
+         12\'h6af: data = 16\'b0000000001111000; //          ****
+\t\t\t12\'h6b0: data = 16\'b0000000000111100; //           ****
+         12\'h6b1: data = 16\'b0000000000111100; //           ****
+         12\'h6b2: data = 16\'b0000000000111100; //           ****
+         12\'h6b3: data = 16\'b0000000000111100; //           ****
+         12\'h6b4: data = 16\'b0000000000111100; //           ****
+         12\'h6b5: data = 16\'b0000000000111100; //           ****
+         12\'h6b6: data = 16\'b0000000000111100; //           ****
+         12\'h6b7: data = 16\'b1111000000111100; // ****      ****
+         12\'h6b8: data = 16\'b0111100001111000; //  ****    ****
+         12\'h6b9: data = 16\'b0011111111110000; //   **********
+         12\'h6ba: data = 16\'b0001111111100000; //    ********
+         12\'h6bb: data = 16\'b0000000000000000; // 
+         12\'h6bc: data = 16\'b0000000000000000; // 
+         12\'h6bd: data = 16\'b0000000000000000; // 
+         12\'h6be: data = 16\'b0000000000000000; // 
+         12\'h6bf: data = 16\'b0000000000000000; //
+\t\t\t
+\t\t//code x6c y x6d      NUMERO 6
+         12\'h6c0: data = 16\'b0000000000000000; // 
+         12\'h6c1: data = 16\'b0000000000000000; // 
+         12\'h6c2: data = 16\'b0000000000000000; // 
+         12\'h6c3: data = 16\'b0000000000000000; // 
+         12\'h6c4: data = 16\'b0000000000000000; // 
+         12\'h6c5: data = 16\'b0000011110000000; //      *****
+         12\'h6c6: data = 16\'b0000111100000000; //     ****
+         12\'h6c7: data = 16\'b0001111000000000; //    ****  
+         12\'h6c8: data = 16\'b0011110000000000; //   ****      
+         12\'h6c9: data = 16\'b0111100000000000; //  ****      
+         12\'h6ca: data = 16\'b1111000000000000; // ****      
+         12\'h6cb: data = 16\'b1111000000000000; // ****    
+         12\'h6cc: data = 16\'b1111000000000000; // ****   
+         12\'h6cd: data = 16\'b1111000000000000; // ****
+         12\'h6ce: data = 16\'b1111111111110000; // ************
+         12\'h6cf: data = 16\'b1111111111111000; // *************
+\t\t\t12\'h6d0: data = 16\'b1111100001111100; // *****    *****
+         12\'h6d1: data = 16\'b1111000000111100; // ****      ****
+         12\'h6d2: data = 16\'b1111000000111100; // ****      ****
+         12\'h6d3: data = 16\'b1111000000111100; // ****      ****
+         12\'h6d4: data = 16\'b1111000000111100; // ****      ****
+         12\'h6d5: data = 16\'b1111000000111100; // ****      ****
+         12\'h6d6: data = 16\'b1111000000111100; // ****      ****
+         12\'h6d7: data = 16\'b1111000000111100; // ****      ****
+         12\'h6d8: data = 16\'b0111100001111000; //  ****    ****
+         12\'h6d9: data = 16\'b0011111111110000; //   **********
+         12\'h6da: data = 16\'b0001111111100000; //    ********
+         12\'h6db: data = 16\'b0000000000000000; // 
+         12\'h6dc: data = 16\'b0000000000000000; // 
+         12\'h6dd: data = 16\'b0000000000000000; // 
+         12\'h6de: data = 16\'b0000000000000000; // 
+         12\'h6df: data = 16\'b0000000000000000; //
+\t\t\t
+\t\t//code x6e y x6f      NUMERO 7
+         12\'h6e0: data = 16\'b0000000000000000; // 
+         12\'h6e1: data = 16\'b0000000000000000; // 
+         12\'h6e2: data = 16\'b0000000000000000; // 
+         12\'h6e3: data = 16\'b0000000000000000; // 
+         12\'h6e4: data = 16\'b0000000000000000; // 
+         12\'h6e5: data = 16\'b1111111111111100; // **************
+         12\'h6e6: data = 16\'b1111111111111100; // **************
+         12\'h6e7: data = 16\'b1111000000111100; // ****      ****
+         12\'h6e8: data = 16\'b0000000000111100; //           ****      
+         12\'h6e9: data = 16\'b0000000000111100; //           ****      
+         12\'h6ea: data = 16\'b0000000000111100; //           ****      
+         12\'h6eb: data = 16\'b0000000000111100; //           ****    
+         12\'h6ec: data = 16\'b0000000000111100; //           ****   
+         12\'h6ed: data = 16\'b0000000001111000; //          ****
+         12\'h6ee: data = 16\'b0000000011110000; //         ****
+         12\'h6ef: data = 16\'b0000000111100000; //        ****
+\t\t\t12\'h6f0: data = 16\'b0000001111000000; //       ****
+         12\'h6f1: data = 16\'b0000011110000000; //      ****
+         12\'h6f2: data = 16\'b0000011110000000; //      ****
+         12\'h6f3: data = 16\'b0000011110000000; //      ****
+         12\'h6f4: data = 16\'b0000011110000000; //      ****
+         12\'h6f5: data = 16\'b0000011110000000; //      ****
+         12\'h6f6: data = 16\'b0000011110000000; //      ****
+         12\'h6f7: data = 16\'b0000011110000000; //      ****
+         12\'h6f8: data = 16\'b0000011110000000; //      ****
+         12\'h6f9: data = 16\'b0000011110000000; //      ****
+         12\'h6fa: data = 16\'b0000011110000000; //      ****
+         12\'h6fb: data = 16\'b0000000000000000; // 
+         12\'h6fc: data = 16\'b0000000000000000; // 
+         12\'h6fd: data = 16\'b0000000000000000; // 
+         12\'h6fe: data = 16\'b0000000000000000; // 
+         12\'h6ff: data = 16\'b0000000000000000; //
+\t\t\t
+\t\t//code x70 y x71      NUMERO 8
+         12\'h700: data = 16\'b0000000000000000; // 
+         12\'h701: data = 16\'b0000000000000000; // 
+         12\'h702: data = 16\'b0000000000000000; // 
+         12\'h703: data = 16\'b0000000000000000; // 
+         12\'h704: data = 16\'b0000000000000000; // 
+         12\'h705: data = 16\'b0001111111100000; //    ********
+         12\'h706: data = 16\'b0011111111110000; //   **********
+         12\'h707: data = 16\'b0111100001111000; //  ****    ****  
+         12\'h708: data = 16\'b1111000000111100; // ****      ****      
+         12\'h709: data = 16\'b1111000000111100; // ****      ****      
+         12\'h70a: data = 16\'b1111000000111100; // ****      ****
+         12\'h70b: data = 16\'b1111000000111100; // ****      ****
+         12\'h70c: data = 16\'b1111000000111100; // ****      ****
+         12\'h70d: data = 16\'b1111000000111100; // ****      ****
+         12\'h70e: data = 16\'b0111100001111000; //  ****    ****
+         12\'h70f: data = 16\'b0011111111110000; //   **********
+\t\t\t12\'h710: data = 16\'b0011111111110000; //   **********
+         12\'h711: data = 16\'b0111100000111100; //  ****    ****
+         12\'h712: data = 16\'b1111000000111100; // ****      ****
+         12\'h713: data = 16\'b1111000000111100; // ****      ****
+         12\'h714: data = 16\'b1111000000111100; // ****      ****
+         12\'h715: data = 16\'b1111000000111100; // ****      ****
+         12\'h716: data = 16\'b1111000000111100; // ****      ****
+         12\'h717: data = 16\'b1111000000111100; // ****      ****
+         12\'h718: data = 16\'b0111100001111000; //  ****    ****
+         12\'h719: data = 16\'b0011111111110000; //   **********
+         12\'h71a: data = 16\'b0001111111100000; //    ********
+         12\'h71b: data = 16\'b0000000000000000; // 
+         12\'h71c: data = 16\'b0000000000000000; // 
+         12\'h71d: data = 16\'b0000000000000000; // 
+         12\'h71e: data = 16\'b0000000000000000; // 
+         12\'h71f: data = 16\'b0000000000000000; //
+\t\t\t
+\t\t//code x72 y x73      NUMERO 9
+         12\'h720: data = 16\'b0000000000000000; // 
+         12\'h721: data = 16\'b0000000000000000; // 
+         12\'h722: data = 16\'b0000000000000000; // 
+         12\'h723: data = 16\'b0000000000000000; // 
+         12\'h724: data = 16\'b0000000000000000; // 
+         12\'h725: data = 16\'b0001111111100000; //    ********
+         12\'h726: data = 16\'b0011111111110000; //   **********
+         12\'h727: data = 16\'b0111100001111000; //  ****    ****          
+         12\'h728: data = 16\'b1111000000111100; // ****      ****       
+         12\'h729: data = 16\'b1111000000111100; // ****      ****      
+         12\'h72a: data = 16\'b1111000000111100; // ****      ****     
+         12\'h72b: data = 16\'b1111000000111100; // ****      ****       
+         12\'h72c: data = 16\'b1111000000111100; // ****      ****       
+         12\'h72d: data = 16\'b1111000000111100; // ****      ****
+         12\'h72e: data = 16\'b0111100000111100; //  ****     ****
+         12\'h72f: data = 16\'b0011111111111100; //   ************
+\t\t\t12\'h730: data = 16\'b0001111111111100; //    ***********
+         12\'h731: data = 16\'b0000000000111100; //           ****
+         12\'h732: data = 16\'b0000000000111100; //           ****
+         12\'h733: data = 16\'b0000000000111100; //           ****       
+         12\'h734: data = 16\'b0000000000111100; //           ****       
+         12\'h735: data = 16\'b0000000000111100; //           ****     
+         12\'h736: data = 16\'b0000000000111100; //           ****      
+         12\'h737: data = 16\'b0000000000111100; //           ****       
+         12\'h738: data = 16\'b0111100001111000; //  ****    ****            
+         12\'h739: data = 16\'b0011111111110000; //   **********
+         12\'h73a: data = 16\'b0001111111100000; //    ********
+         12\'h73b: data = 16\'b0000000000000000; // 
+         12\'h73c: data = 16\'b0000000000000000; // 
+         12\'h73d: data = 16\'b0000000000000000; // 
+         12\'h73e: data = 16\'b0000000000000000; // 
+         12\'h73f: data = 16\'b0000000000000000; //
+\t\t\t
+\t\t//code x74 y x75
+         12\'h740: data = 16\'b0000000000000000; // 
+         12\'h741: data = 16\'b0000000000000000; // 
+         12\'h742: data = 16\'b0000000000000000; // 
+         12\'h743: data = 16\'b0000000000000000; // 
+         12\'h744: data = 16\'b0000000000000000; // 
+         12\'h745: data = 16\'b0000000000000000; // 
+         12\'h746: data = 16\'b0000000000000000; // 
+         12\'h747: data = 16\'b0000000000000000; // 
+         12\'h748: data = 16\'b0000001110000000; //        ***
+         12\'h749: data = 16\'b0000011111000000; //       *****
+         12\'h74a: data = 16\'b0000011111000000; //       ***** 
+         12\'h74b: data = 16\'b0000011111000000; //       ***** 
+         12\'h74c: data = 16\'b0000001110000000; //        ***
+         12\'h74d: data = 16\'b0000000000000000; // 
+         12\'h74e: data = 16\'b0000000000000000; // 
+         12\'h74f: data = 16\'b0000000000000000; //
+\t\t\t12\'h750: data = 16\'b0000000000000000; // 
+         12\'h751: data = 16\'b0000000000000000; // 
+         12\'h752: data = 16\'b0000000000000000; // 
+         12\'h753: data = 16\'b0000001110000000; //        *** 
+         12\'h754: data = 16\'b0000011111000000; //       ***** 
+         12\'h755: data = 16\'b0000011111000000; //       ***** 
+         12\'h756: data = 16\'b0000011111000000; //       ***** 
+         12\'h757: data = 16\'b0000001110000000; //        *** 
+         12\'h758: data = 16\'b0000000000000000; // 
+         12\'h759: data = 16\'b0000000000000000; // 
+         12\'h75a: data = 16\'b0000000000000000; // 
+         12\'h75b: data = 16\'b0000000000000000; // 
+         12\'h75c: data = 16\'b0000000000000000; // 
+         12\'h75d: data = 16\'b0000000000000000; // 
+         12\'h75e: data = 16\'b0000000000000000; // 
+         12\'h75f: data = 16\'b0000000000000000; //
+
+\t\t//code xc2 y xc3\t\t\ta
+         12\'hc20: data = 16\'b0000000000000000; // 
+         12\'hc21: data = 16\'b0000000000000000; // 
+         12\'hc22: data = 16\'b0000000000000000; // 
+         12\'hc23: data = 16\'b0000000000000000; // 
+         12\'hc24: data = 16\'b0000000000000000; // 
+         12\'hc25: data = 16\'b0000000000000000; // 
+         12\'hc26: data = 16\'b0000000000000000; // 
+         12\'hc27: data = 16\'b0000000000000000; // 
+         12\'hc28: data = 16\'b0000000000000000; // 
+         12\'hc29: data = 16\'b0000000000000000; // 
+         12\'hc2a: data = 16\'b0111111111000000; //  *********
+         12\'hc2b: data = 16\'b0111111111100000; //  **********
+         12\'hc2c: data = 16\'b0000000011110000; //         ****
+         12\'hc2d: data = 16\'b0000000011110000; //         ****
+         12\'hc2e: data = 16\'b0011111111110000; //   **********
+         12\'hc2f: data = 16\'b0111111111110000; //  ***********
+\t\t\t12\'hc30: data = 16\'b1111100111110000; // *****  *****
+         12\'hc31: data = 16\'b1111000011110000; // ****    ****
+         12\'hc32: data = 16\'b1111000011110000; // ****    ****
+         12\'hc33: data = 16\'b1111000011110000; // ****    ****
+         12\'hc34: data = 16\'b1111000011110000; // ****    ****
+         12\'hc35: data = 16\'b1111100111110000; // *****  *****
+         12\'hc36: data = 16\'b0111111110111000; //  ******** ***
+         12\'hc37: data = 16\'b0011111100011100; //   ******   ***
+         12\'hc38: data = 16\'b0000000000000000; // 
+         12\'hc39: data = 16\'b0000000000000000; // 
+         12\'hc3a: data = 16\'b0000000000000000; // 
+         12\'hc3b: data = 16\'b0000000000000000; // 
+         12\'hc3c: data = 16\'b0000000000000000; // 
+         12\'hc3d: data = 16\'b0000000000000000; // 
+         12\'hc3e: data = 16\'b0000000000000000; // 
+         12\'hc3f: data = 16\'b0000000000000000; //
+\t
+\t\t//code xc6 y xc7    m
+         12\'hc60: data = 16\'b0000000000000000; // 
+         12\'hc61: data = 16\'b0000000000000000; // 
+         12\'hc62: data = 16\'b0000000000000000; // 
+         12\'hc63: data = 16\'b0000000000000000; // 
+         12\'hc64: data = 16\'b0000000000000000; // 
+         12\'hc65: data = 16\'b0000000000000000; // 
+         12\'hc66: data = 16\'b0000000000000000; // 
+         12\'hc67: data = 16\'b0000000000000000; // 
+         12\'hc68: data = 16\'b0000000000000000; // 
+         12\'hc69: data = 16\'b0000000000000000; // 
+         12\'hc6a: data = 16\'b0000000000000000; // 
+         12\'hc6b: data = 16\'b0011110000111100; //  ****    ****
+         12\'hc6c: data = 16\'b0111111001111110; // ******  ******
+         12\'hc6d: data = 16\'b0111111111111111; // ***************
+         12\'hc6e: data = 16\'b0111101111101111; // **** ***** ****
+         12\'hc6f: data = 16\'b0111000111000111; // ***   ***   ***
+\t\t\t12\'hc70: data = 16\'b0111000111000111; // ***   ***   ***
+         12\'hc71: data = 16\'b0111000111000111; // ***   ***   ***  
+         12\'hc72: data = 16\'b0111000111000111; // ***   ***   ***
+         12\'hc73: data = 16\'b0111000111000111; // ***   ***   ***
+         12\'hc74: data = 16\'b0111000111000111; // ***   ***   ***
+         12\'hc75: data = 16\'b0111000111000111; // ***   ***   ***
+         12\'hc76: data = 16\'b0111000111000111; // ***   ***   ***
+         12\'hc77: data = 16\'b0111000111000111; // ***   ***   ***
+         12\'hc78: data = 16\'b0000000000000000; // 
+         12\'hc79: data = 16\'b0000000000000000; // 
+         12\'hc7a: data = 16\'b0000000000000000; // 
+         12\'hc7b: data = 16\'b0000000000000000; // 
+         12\'hc7c: data = 16\'b0000000000000000; // 
+         12\'hc7d: data = 16\'b0000000000000000; // 
+         12\'hc7e: data = 16\'b0000000000000000; // 
+         12\'hc7f: data = 16\'b0000000000000000; //
+\t\t\t
+\t\t//code xc8 y xc9    \t\tp
+         12\'hc80: data = 16\'b0000000000000000; // 
+         12\'hc81: data = 16\'b0000000000000000; // 
+         12\'hc82: data = 16\'b0000000000000000; // 
+         12\'hc83: data = 16\'b0000000000000000; // 
+         12\'hc84: data = 16\'b0000000000000000; // 
+         12\'hc85: data = 16\'b0000000000000000; // 
+         12\'hc86: data = 16\'b0000000000000000; // 
+         12\'hc87: data = 16\'b0000000000000000; // 
+         12\'hc88: data = 16\'b0000000000000000; // 
+         12\'hc89: data = 16\'b0000000000000000; // 
+         12\'hc8a: data = 16\'b1110001111110000; // ***   ******
+         12\'hc8b: data = 16\'b0111011111111000; //  *** ********
+         12\'hc8c: data = 16\'b0011111001111100; //   *****  *****
+         12\'hc8d: data = 16\'b0011110000111100; //   ****    ****
+         12\'hc8e: data = 16\'b0011110000111100; //   ****    ****
+         12\'hc8f: data = 16\'b0011110000111100; //   ****    ****
+\t\t\t12\'hc90: data = 16\'b0011110000111100; //   ****    ****
+         12\'hc91: data = 16\'b0011110000111100; //   ****    ****
+         12\'hc92: data = 16\'b0011110000111100; //   ****    ****
+         12\'hc93: data = 16\'b0011110000111100; //   ****    ****
+         12\'hc94: data = 16\'b0011110000111100; //   ****    ****
+         12\'hc95: data = 16\'b0011111001111100; //   *****  *****
+         12\'hc96: data = 16\'b0011111111111000; //   ***********
+         12\'hc97: data = 16\'b0011111111110000; //   **********
+         12\'hc98: data = 16\'b0011110000000000; //   ****
+         12\'hc99: data = 16\'b0011110000000000; //   ****
+         12\'hc9a: data = 16\'b0011110000000000; //   ****
+         12\'hc9b: data = 16\'b0011110000000000; //   ****
+         12\'hc9c: data = 16\'b0011110000000000; //   ****
+         12\'hc9d: data = 16\'b1111111100000000; // ********
+         12\'hc9e: data = 16\'b0000000000000000; // 
+         12\'hc9f: data = 16\'b0000000000000000; //
+\t\t\t
+\t\tdefault: data = 16\'b0000000000000000;
+\t\t
+\t\tendcase
+\t 
+endmodule
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: Jafet Chaves Barrantes
+// 
+// Create Date:    12:44:02 05/14/2016 
+// Design Name: 
+// Module Name:    picture_hora 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module generador_imagenes
+(
+input wire video_on,//se\xf1al que indica que se encuentra en la regi\xf3n visible de resoluci\xf3n 640x480
+input wire [9:0] pixel_x, pixel_y,
+output wire pic_ring_on, pic_ringball_on,
+output wire pic_on,
+output wire [7:0] pic_RGB
+);
+
+//Declaraci\xf3n de constantes
+//Imagen HORA
+localparam pic_hora_XL = 9\'d256; //L\xedmite izquierdo
+localparam pic_hora_XR = 9\'d384; //L\xedmite derecho
+localparam pic_hora_Y = 7\'d64; //L\xedmite inferior
+localparam hora_size = 14\'d8192;//Cuantas l\xedneas de texto se deben leer (valor se encuentra en Matlab, variable COLOR_HEX)
+localparam pic_hora_XY = 7\'d64;
+
+//Imagen FECHA
+localparam pic_fecha_XL = 8\'d128; //L\xedmite izquierdo
+localparam pic_fecha_XR = 8\'d208; //L\xedmite derecho
+localparam pic_fecha_YT = 9\'d320;\t//L\xedmite superior
+localparam pic_fecha_YB = 9\'d352; //L\xedmite inferior
+localparam pic_fecha_size = 12\'d2560;// (80x32)
+localparam pic_fecha_XY = 6\'d32;
+
+//Imagen TIMER
+localparam pic_timer_XL = 9\'d416; //L\xedmite izquierdo
+localparam pic_timer_XR = 9\'d496; //L\xedmite derecho
+localparam pic_timer_YT = 9\'d320;\t//L\xedmite superior
+localparam pic_timer_YB = 9\'d352; //L\xedmite inferior
+localparam pic_timer_size = 12\'d2560;// (80x32)
+localparam pic_timer_XY = 6\'d32;
+
+//Imagen RING
+localparam pic_ring_XL = 10\'d512; //L\xedmite izquierdo
+localparam pic_ring_XR = 10\'d639; //L\xedmite derecho
+localparam pic_ring_YT = 8\'d128;\t//L\xedmite superior
+localparam pic_ring_YB = 8\'d192; //L\xedmite inferior
+localparam pic_ring_size = 14\'d8192;// (128x64)
+localparam pic_ring_XY = 7\'d64;
+
+//Imagen RING ball
+localparam pic_ringball_XL = 10\'d544; //L\xedmite izquierdo
+localparam pic_ringball_XR = 10\'d592; //L\xedmite derecho
+localparam pic_ringball_YT = 7\'d64;\t//L\xedmite superior
+localparam pic_ringball_YB = 7\'d112; //L\xedmite inferior
+localparam pic_ringball_size = 12\'d2304;// (48x48)
+localparam pic_ringball_XY = 6\'d48;
+
+//Imagen LOGO
+localparam pic_logo_XL = 12\'d0; //L\xedmite derecho
+localparam pic_logo_XR = 8\'d128; //L\xedmite derecho
+localparam pic_logo_YT = 5\'d0; //L\xedmite inferior
+localparam pic_logo_YB = 5\'d16; //L\xedmite inferior
+localparam pic_logo_size = 12\'d2048;// (128x16)
+localparam pic_logo_XY = 5\'d16;
+
+//Declaraci\xf3n de se\xf1ales
+reg [7:0] colour_data_hora [0:hora_size-1];\t//datos de los colores
+reg [7:0] colour_data_fecha [0:pic_fecha_size-1];\t//datos de los colores
+reg [7:0] colour_data_timer [0:pic_timer_size-1];\t//datos de los colores
+reg [7:0] colour_data_ring [0:pic_ring_size-1];\t//datos de los colores
+reg [7:0] colour_data_ringball [0:pic_ringball_size-1];\t//datos de los colores
+reg [7:0] colour_data_logo [0:pic_logo_size-1];\t//datos de los colores
+wire [13:0] STATE_hora; //Bits dependen de hora_size
+wire [11:0] STATE_fecha; //Bits dependen de hora_size
+wire [11:0] STATE_timer; //Bits dependen de hora_size
+wire [13:0] STATE_ring; //Bits dependen de hora_size
+wire [11:0] STATE_ringball; //Bits dependen de hora_size
+wire [11:0] STATE_logo; //Bits dependen de hora_size
+wire pic_hora_on, pic_fecha_on, pic_timer_on, pic_logo_on;
+reg [7:0] pic_RGB_aux;
+
+//===================================================
+// Imagen HORA
+//===================================================
+initial 
+$readmemh (""hora.list"", colour_data_hora);
+
+//Imprime la imagen de hora dentro de la regi\xf3n
+assign pic_hora_on = (pic_hora_XL<=pixel_x)&&(pixel_x<=pic_hora_XR)&&(pixel_y<=pic_hora_Y);//Para saber cuando se est\xe1 imprimiendo la imagen
+
+assign STATE_hora = ((pixel_x-pic_hora_XL)*pic_hora_XY)+(pixel_y-pic_hora_Y); //Para generar el \xedndice de la memoria
+
+//===================================================
+// Imagen FECHA
+//===================================================
+initial
+$readmemh (""fecha.list"", colour_data_fecha);//Leer datos RBG de archivo de texto, sintetiza una ROM
+
+//Imprime la imagen de hora dentro de la regi\xf3n
+assign pic_fecha_on = (pic_fecha_XL<=pixel_x)&&(pixel_x<=pic_fecha_XR)&&(pic_fecha_YT<=pixel_y)&&(pixel_y<=pic_fecha_YB);//Para saber cuando se est\xe1 imprimiendo la imagen
+
+assign STATE_fecha = ((pixel_x-pic_fecha_XL)*pic_fecha_XY)+(pixel_y-pic_fecha_YT); //Para generar el \xedndice de la memoria
+
+//===================================================
+// Imagen TIMER
+//===================================================
+initial
+$readmemh (""timer.list"", colour_data_timer);//Leer datos RBG de archivo de texto, sintetiza una ROM
+
+//Imprime la imagen de hora dentro de la regi\xf3n
+assign pic_timer_on = (pic_timer_XL<=pixel_x)&&(pixel_x<=pic_timer_XR)&&(pic_timer_YT<=pixel_y)&&(pixel_y<=pic_timer_YB);//Para saber cuando se est\xe1 imprimiendo la imagen
+
+assign STATE_timer = ((pixel_x-pic_timer_XL)*pic_timer_XY)+(pixel_y-pic_timer_YT); //Para generar el \xedndice de la memoria
+
+//===================================================
+// Imagen RING
+//===================================================
+initial
+$readmemh (""ring.list"", colour_data_ring);//Leer datos RBG de archivo de texto, sintetiza una ROM
+
+//Imprime la imagen de hora dentro de la regi\xf3n
+assign pic_ring_on = (pic_ring_XL<=pixel_x)&&(pixel_x<=pic_ring_XR)&&(pic_ring_YT<=pixel_y)&&(pixel_y<=pic_ring_YB);//Para saber cuando se est\xe1 imprimiendo la imagen
+
+assign STATE_ring = ((pixel_x-pic_ring_XL)*pic_ring_XY)+(pixel_y-pic_ring_YT); //Para generar el \xedndice de la memoria
+
+//===================================================
+// Imagen RING BALL
+//===================================================
+initial
+$readmemh (""ring_ball_2.list"", colour_data_ringball);//Leer datos RBG de archivo de texto, sintetiza una ROM
+
+//Imprime la imagen de hora dentro de la regi\xf3n
+assign pic_ringball_on = (pic_ringball_XL<=pixel_x)&&(pixel_x<=pic_ringball_XR)&&(pic_ringball_YT<=pixel_y)&&(pixel_y<=pic_ringball_YB);//Para saber cuando se est\xe1 imprimiendo la imagen
+
+assign STATE_ringball = ((pixel_x-pic_ringball_XL)*pic_ringball_XY)+(pixel_y-pic_ringball_YT); //Para generar el \xedndice de la memoria
+
+//===================================================
+// Imagen LOGO
+//===================================================
+initial
+$readmemh (""logo.list"", colour_data_logo);//Leer datos RBG de archivo de texto, sintetiza una ROM
+
+//Imprime la imagen de hora dentro de la regi\xf3n
+assign pic_logo_on = (pixel_x<=pic_logo_XR)&&(pixel_y<=pic_logo_YB);//Para saber cuando se est\xe1 imprimiendo la imagen
+
+assign STATE_logo = ((pixel_x-pic_logo_XL)*pic_logo_XY)+(pixel_y-pic_logo_YT); //Para generar el \xedndice de la memoria
+
+
+//Multiplexa el RGB
+always @*
+begin\t
+\tif(~video_on)
+\t\tpic_RGB_aux = 8\'b0;//fondo negro
+\t
+\telse 
+\t\tif(pic_hora_on) pic_RGB_aux = colour_data_hora[{STATE_hora}];
+\t\telse if (pic_fecha_on) pic_RGB_aux = colour_data_fecha[{STATE_fecha}];
+\t\telse if (pic_timer_on) pic_RGB_aux = colour_data_timer[{STATE_timer}];
+\t\telse if (pic_ring_on) pic_RGB_aux = colour_data_ring[{STATE_ring}];
+\t\telse if (pic_ringball_on) pic_RGB_aux = colour_data_ringball[{STATE_ringball}];
+\t\telse if (pic_logo_on) pic_RGB_aux = colour_data_logo[{STATE_logo}];
+\t\telse pic_RGB_aux = 8\'b0;//fondo negro\t
+end
+//assign pic_RGB = \t{pic_RGB_aux[7:5],1\'b0,pic_RGB_aux[4:2],1\'b0,pic_RGB_aux[1:0],2\'b0};\t//Rellena pic_RGB para pasar de 8 bits a 12 bits
+assign pic_RGB = pic_RGB_aux;//Para 8 bits (Nexys 3)
+assign pic_on = pic_hora_on | pic_timer_on | pic_fecha_on | pic_logo_on;
+
+endmodule
+"
+"`timescale 1ns / 1ps
+
+////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:
+//
+// Create Date:   11:02:53 05/24/2016
+// Design Name:   escritor_lector_rtc
+// Module Name:   D:/TEC/I 2016/Lab Digitales/Proyecto III/Proyecto Xillinx/Proyecto_3/testbench_escitor_lector_rtc.v
+// Project Name:  Proyecto_3
+// Target Device:  
+// Tool versions:  
+// Description: 
+//
+// Verilog Test Fixture created by ISE for module: escritor_lector_rtc
+//
+// Dependencies:
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+////////////////////////////////////////////////////////////////////////////////
+
+module testbench_escitor_lector_rtc;
+
+\t// Inputs
+\treg clk;
+\treg reset;
+\treg [7:0] port_id;
+\treg [7:0] in_dato;
+\treg write_strobe;
+\treg read_strobe;
+
+\t// Outputs
+\twire reg_a_d;
+\twire reg_cs;
+\twire reg_rd;
+\twire reg_wr;
+\twire [7:0] out_dato;
+\twire [7:0] fin_lectura_escritura;
+
+\t// Bidirs
+\twire [7:0] dato;
+
+\t// Instantiate the Unit Under Test (UUT)
+\tescritor_lector_rtc uut (
+\t\t.clk(clk), 
+\t\t.reset(reset), 
+\t\t.port_id(port_id), 
+\t\t.in_dato(in_dato), 
+\t\t.write_strobe(write_strobe), 
+\t\t.read_strobe(read_strobe), 
+\t\t.reg_a_d(reg_a_d), 
+\t\t.reg_cs(reg_cs), 
+\t\t.reg_rd(reg_rd), 
+\t\t.reg_wr(reg_wr), 
+\t\t.out_dato(out_dato), 
+\t\t.fin_lectura_escritura(fin_lectura_escritura), 
+\t\t.dato(dato)
+\t);
+always #10 clk = ~clk;
+/*
+reg count;
+always @ (posedge clk) begin
+\tcount = count + 1'b1;
+end
+always @(negedge count) begin
+\t
+end
+*/
+\tinitial begin
+\t\t// Initialize Inputs
+\t\tclk = 0;
+\t\treset = 1;
+\t\tport_id = 0;
+\t\tin_dato = 0;
+\t\twrite_strobe = 0;
+\t\tread_strobe = 0;
+\t\t#10 reset = 0;
+\t\t#20 port_id = 8'h10;
+\t\tin_dato = 8'h01;
+\t\t#20 port_id = 8'h00;
+\t\tin_dato = 8'h21;
+\t\t#20 port_id = 8'h01;
+\t\tin_dato = 8'h01;
+\t\t
+\t\t
+\t\t
+\t\t#100000 $stop;
+\t\t
+\t\t// Wait 100 ns for global reset to finish
+\t\t
+        
+\t\t// Add stimulus here
+\tend
+      
+endmodule
+
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    01:23:16 04/12/2016 
+// Design Name: 
+// Module Name:    memoria_registros 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module memoria_registros_VGA
+( 
+\tinput clk, reset,
+\t
+\tinput wire formato_hora,
+\t
+\tinput cs_seg_hora,cs_min_hora,cs_hora_hora,
+\tinput cs_dia_fecha,cs_mes_fecha,cs_jahr_fecha,
+\tinput cs_seg_timer,cs_min_timer,cs_hora_timer,
+\t
+\tinput hold_seg_hora,hold_min_hora,hold_hora_hora,
+\tinput hold_dia_fecha,hold_mes_fecha,hold_jahr_fecha,
+\tinput hold_seg_timer,hold_min_timer,hold_hora_timer,
+\t
+\tinput hold_banderas_config,
+\t
+\tinput [7:0] data_PicoBlaze,
+\t
+\tinput [7:0] count_seg_hora,count_min_hora,count_hora_hora,
+\tinput [7:0] count_dia_fecha,count_mes_fecha,count_jahr_fecha,
+\tinput [7:0] count_seg_timer,count_min_timer,count_hora_timer,
+\t
+\toutput wire[7:0] out_seg_hora,out_min_hora,out_hora_hora,
+\toutput wire[7:0] out_dia_fecha,out_mes_fecha,out_jahr_fecha,
+\toutput wire[7:0] out_seg_timer,out_min_timer,out_hora_timer,
+\t
+\toutput[1:0] out_banderas_config,
+\t
+\toutput reg AM_PM
+);
+\t 
+//wire flag1,flag2,flag3;
+reg flag_done_timer;
+//assign flag_done_timer = (flag1 && flag2 && flag3)? 1'b1:1'b0;
+wire cs_banderas_config;
+
+assign cs_banderas_config = 1'b0;
+
+wire [7:0]data_HH;//Dato de hora del registro
+reg [3:0]digit0_HH, digit1_HH;
+
+////////instancia reg seg_hora
+Registro_Universal #(.N(8))
+instancia_seg_hora (
+\t .hold(hold_seg_hora),
+    .in_rtc_dato(data_PicoBlaze), 
+    .in_count_dato(count_seg_hora), 
+    .clk(clk), 
+    .reset(reset), 
+    .chip_select(cs_seg_hora), 
+    .out_dato(out_seg_hora)
+    );
+////////instancia reg min_hora
+Registro_Universal #(.N(8))
+ instancia_min_hora (
+\t .hold(hold_min_hora),
+    .in_rtc_dato(data_PicoBlaze), 
+    .in_count_dato(count_min_hora), 
+    .clk(clk), 
+    .reset(reset), 
+    .chip_select(cs_min_hora), 
+    .out_dato(out_min_hora)
+    );
+////////instancia reg hora_hora
+Registro_Universal #(.N(8))
+instancia_hora_hora (
+\t .hold(hold_hora_hora),
+    .in_rtc_dato(data_PicoBlaze), 
+    .in_count_dato(count_hora_hora), 
+    .clk(clk), 
+    .reset(reset), 
+    .chip_select(cs_hora_hora), 
+    .out_dato(data_HH)
+    );
+////////instancia reg dia_fecha
+Registro_Universal #(.N(8))
+instancia_dia_fecha (
+\t .hold(hold_dia_fecha),
+    .in_rtc_dato(data_PicoBlaze), 
+    .in_count_dato(count_dia_fecha), 
+    .clk(clk), 
+    .reset(reset), 
+    .chip_select(cs_dia_fecha), 
+    .out_dato(out_dia_fecha)
+    );
+////////instancia reg mes_fecha
+Registro_Universal #(.N(8))
+instancia_mes_fecha (
+\t .hold(hold_mes_fecha),
+    .in_rtc_dato(data_PicoBlaze), 
+    .in_count_dato(count_mes_fecha), 
+    .clk(clk), 
+    .reset(reset),  
+    .chip_select(cs_mes_fecha), 
+    .out_dato(out_mes_fecha)
+    );
+////////instancia reg jahr_fecha
+Registro_Universal #(.N(8))
+instancia_jahr_fecha (
+\t .hold(hold_jahr_fecha),\t
+    .in_rtc_dato(data_PicoBlaze), 
+    .in_count_dato(count_jahr_fecha), 
+    .clk(clk), 
+    .reset(reset), 
+    .chip_select(cs_jahr_fecha), 
+    .out_dato(out_jahr_fecha)
+    );
+////////instancia reg seg_timer
+Registro_Universal #(.N(8))
+instancia_seg_timer (
+\t .hold(hold_seg_timer),
+    .in_rtc_dato(data_PicoBlaze), 
+    .in_count_dato(count_seg_timer), 
+    .clk(clk), 
+    .reset(reset), 
+    .chip_select(cs_seg_timer),
+    .out_dato(out_seg_timer) 
+    );
+////////instancia reg min_timer
+Registro_Universal #(.N(8))
+instancia_min_timer (
+\t .hold(hold_min_timer),
+    .in_rtc_dato(data_PicoBlaze), 
+    .in_count_dato(count_min_timer), 
+    .clk(clk), 
+    .reset(reset), 
+    .chip_select(cs_min_timer), 
+    .out_dato(out_min_timer)
+    );
+////////instancia reg hora_timer
+Registro_Universal #(.N(8))
+instancia_hora_timer(
+\t .hold(hold_hora_timer),
+    .in_rtc_dato(data_PicoBlaze), 
+    .in_count_dato(count_hora_timer), 
+    .clk(clk), 
+    .reset(reset), 
+    .chip_select(cs_hora_timer),
+    .out_dato(out_hora_timer)
+    );
+////////instancia reg banderas_config
+Registro_Universal #(.N(2))
+instancia_bandera_config(
+\t .hold(hold_banderas_config),
+    .in_rtc_dato(data_PicoBlaze[1:0]), 
+    .in_count_dato(2'b0), 
+    .clk(clk), 
+    .reset(reset), 
+    .chip_select(cs_banderas_config),
+    .out_dato(out_banderas_config)
+    );
+\t 
+//=============================================
+// BLOQUE PARA TRADUCIR FORMATO DE LA HORA
+//=============================================
+always@*
+begin
+\tif(formato_hora)//12 hrs (Traduce a formato 12 hrs)
+\tbegin
+\t\tcase(data_HH)
+\t\t8'd0: begin digit1_HH = 4'b0001; digit0_HH = 4'b0010; AM_PM = 0; end//00 BCD en 8 bits
+\t\t8'd1: begin digit1_HH = 4'b0000; digit0_HH = 4'b0001; AM_PM = 0; end//01 BCD en 8 bits
+\t\t8'd2: begin digit1_HH = 4'b0000; digit0_HH = 4'b0010; AM_PM = 0; end//02 BCD en 8 bits
+\t\t8'd3: begin digit1_HH = 4'b0000; digit0_HH = 4'b0011; AM_PM = 0; end//03 BCD en 8 bits
+\t\t8'd4: begin digit1_HH = 4'b0000; digit0_HH = 4'b0100; AM_PM = 0; end//04 BCD en 8 bits
+\t\t8'd5: begin digit1_HH = 4'b0000; digit0_HH = 4'b0101; AM_PM = 0; end//05 BCD en 8 bits
+\t\t8'd6: begin digit1_HH = 4'b0000; digit0_HH = 4'b0110; AM_PM = 0; end//06 BCD en 8 bits
+\t\t8'd7: begin digit1_HH = 4'b0000; digit0_HH = 4'b0111; AM_PM = 0; end//07 BCD en 8 bits
+\t\t8'd8: begin digit1_HH = 4'b0000; digit0_HH = 4'b1000; AM_PM = 0; end//08 BCD en 8 bits
+\t\t8'd9: begin digit1_HH = 4'b0000; digit0_HH = 4'b1001; AM_PM = 0; end//09 BCD en 8 bits
+\t\t8'd16: begin digit1_HH = 4'b0001; digit0_HH = 4'b0000; AM_PM = 0; end//10 BCD en 8 bits
+\t\t8'd17: begin digit1_HH = 4'b0001; digit0_HH = 4'b0001; AM_PM = 0; end//11 BCD en 8 bits
+\t\t
+\t\t8'd18: begin digit1_HH = 4'b0001; digit0_HH = 4'b0010; AM_PM = 1; end//12 BCD en 8 bits
+\t\t8'd19: begin digit1_HH = 4'b0000; digit0_HH = 4'b0001; AM_PM = 1; end//13 BCD en 8 bits
+\t\t8'd20: begin digit1_HH = 4'b0000; digit0_HH = 4'b0010; AM_PM = 1; end//14 BCD en 8 bits
+\t\t8'd21: begin digit1_HH = 4'b0000; digit0_HH = 4'b0011; AM_PM = 1; end//15 BCD en 8 bits
+\t\t8'd22: begin digit1_HH = 4'b0000; digit0_HH = 4'b0100; AM_PM = 1; end//16 BCD en 8 bits
+\t\t8'd23: begin digit1_HH = 4'b0000; digit0_HH = 4'b0101; AM_PM = 1; end//17 BCD en 8 bits
+\t\t8'd24: begin digit1_HH = 4'b0000; digit0_HH = 4'b0110; AM_PM = 1; end//18 BCD en 8 bits
+\t\t8'd25: begin digit1_HH = 4'b0000; digit0_HH = 4'b0111; AM_PM = 1; end//19 BCD en 8 bits
+\t\t8'd32: begin digit1_HH = 4'b0000; digit0_HH = 4'b1000; AM_PM = 1; end//20 BCD en 8 bits
+\t\t8'd33: begin digit1_HH = 4'b0000; digit0_HH = 4'b1001; AM_PM = 1; end//21 BCD en 8 bits
+\t\t8'd34: begin digit1_HH = 4'b0001; digit0_HH = 4'b0000; AM_PM = 1; end//22 BCD en 8 bits
+\t\t8'd35: begin digit1_HH = 4'b0001; digit0_HH = 4'b0001; AM_PM = 1; end//23 BCD en 8 bits
+\t\tdefault:  begin digit1_HH = 0; digit0_HH = 0; AM_PM = 0; end
+\t\tendcase
+\tend
+\t
+\telse //24 hrs (Transfiere el dato simplemente)
+\tbegin
+\t\tdigit1_HH = data_HH[7:4];
+\t\tdigit0_HH = data_HH[3:0];
+\t\tAM_PM = 0;
+\tend
+end
+
+assign out_hora_hora = {digit1_HH,digit0_HH};
+/*
+//Para generar flag_done_timer
+always@(posedge clk)
+begin
+\tif(reset) flag_done_timer <= 1'b0;
+\telse if((rtc_seg_timer == count_seg_timer)&&(rtc_min_timer == count_min_timer)&&((count_hora_timer!=0)||(count_min_timer!=0)||(count_seg_timer!=0))&&(estado_alarma==0)) flag_done_timer <= 1'b1;
+\telse flag_done_timer <= 1'b0;
+end
+\t 
+\t 
+///////  FSM para alarma timer //////////
+
+localparam [1:0]
+espera_conf = 2'b00,
+conf = 2'b01,
+timer_run = 2'b10,
+alarma_on = 2'b11;
+
+reg [1:0] state_reg , state_next;
+//// secuancial
+always@(posedge clk , posedge reset) 
+begin
+if (reset) state_reg = espera_conf;
+else state_reg = state_next;
+end
+/// combinacional
+always@*
+begin
+state_next = state_reg ; 
+case (state_reg)
+\tespera_conf: begin
+\tflag_mostrar_count = 1'b1;
+\testado_alarma = 1'b0;
+\t\tif(sw2) state_next = conf;
+\t\telse state_next = espera_conf;
+\tend
+\tconf: begin
+\tflag_mostrar_count = 1'b1;
+\testado_alarma = 1'b0;
+\tif(~sw2) state_next = timer_run;
+\telse state_next = conf;
+\tend
+\ttimer_run: begin
+\tflag_mostrar_count = 1'b0;
+\testado_alarma = 1'b0;
+\tif (flag_done_timer) state_next = alarma_on;
+\telse state_next = timer_run;
+\tend
+\talarma_on: begin
+\tflag_mostrar_count = 1'b1;
+\testado_alarma = 1'b1;
+\tif (desactivar_alarma) state_next = espera_conf;
+\telse state_next = alarma_on;
+\tend
+endcase
+end
+
+/////////////////////////////////////////
+*/
+endmodule 
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: Jafet Chaves Barrantes
+// 
+// Create Date:    15:45:17 04/03/2016 
+// Design Name: 
+// Module Name:    contador_AD_HH_T_2dig
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module contador_AD_HH_T_2dig
+(
+input wire clk,
+input wire reset,
+input wire [3:0] en_count,
+input wire enUP,
+input wire enDOWN,
+output wire [7:0] data_HH_T
+);
+
+localparam N = 5; // Para definir el n\xfamero de bits del contador (hasta 23->5 bits)
+//Declaraci\xf3n de se\xf1ales
+reg [N-1:0] q_act, q_next;
+wire [N-1:0] count_data;
+reg [3:0] digit1, digit0;
+
+//Descripci\xf3n del comportamiento
+always@(posedge clk, posedge reset)
+begin\t
+\t
+\tif(reset)
+\tbegin
+\t\tq_act <= 5'b0;
+\tend
+\t
+\telse
+\tbegin
+\t\tq_act <= q_next;
+\tend
+end
+
+
+//L\xf3gica de salida
+
+always@*
+begin
+
+\tif (en_count == 10)
+\tbegin
+\t\tif (enUP)
+\t\tbegin
+\t\t\tif (q_act >= 5'd23) q_next = 5'd0;
+\t\t\telse q_next = q_act + 5'd1;
+\t\tend
+\t\t
+\t\telse if (enDOWN)
+\t\tbegin
+\t\t\tif (q_act == 5'd0) q_next = 5'd23;
+\t\t\telse q_next = q_act - 5'd1;
+\t\tend
+\t\telse q_next = q_act;
+\tend
+\telse q_next = q_act;
+\t
+end
+
+assign count_data = q_act;
+
+//Decodificaci\xf3n BCD (2 d\xedgitos)
+
+always@*
+begin
+case(count_data)
+5'd0: begin digit1 = 4'b0000; digit0 = 4'b0000; end
+5'd1: begin digit1 = 4'b0000; digit0 = 4'b0001; end
+5'd2: begin digit1 = 4'b0000; digit0 = 4'b0010; end
+5'd3: begin digit1 = 4'b0000; digit0 = 4'b0011; end
+5'd4: begin digit1 = 4'b0000; digit0 = 4'b0100; end
+5'd5: begin digit1 = 4'b0000; digit0 = 4'b0101; end
+5'd6: begin digit1 = 4'b0000; digit0 = 4'b0110; end
+5'd7: begin digit1 = 4'b0000; digit0 = 4'b0111; end
+5'd8: begin digit1 = 4'b0000; digit0 = 4'b1000; end
+5'd9: begin digit1 = 4'b0000; digit0 = 4'b1001; end
+
+5'd10: begin digit1 = 4'b0001; digit0 = 4'b0000; end
+5'd11: begin digit1 = 4'b0001; digit0 = 4'b0001; end
+5'd12: begin digit1 = 4'b0001; digit0 = 4'b0010; end
+5'd13: begin digit1 = 4'b0001; digit0 = 4'b0011; end
+5'd14: begin digit1 = 4'b0001; digit0 = 4'b0100; end
+5'd15: begin digit1 = 4'b0001; digit0 = 4'b0101; end
+5'd16: begin digit1 = 4'b0001; digit0 = 4'b0110; end
+5'd17: begin digit1 = 4'b0001; digit0 = 4'b0111; end
+5'd18: begin digit1 = 4'b0001; digit0 = 4'b1000; end
+5'd19: begin digit1 = 4'b0001; digit0 = 4'b1001; end
+
+5'd20: begin digit1 = 4'b0010; digit0 = 4'b0000; end
+5'd21: begin digit1 = 4'b0010; digit0 = 4'b0001; end
+5'd22: begin digit1 = 4'b0010; digit0 = 4'b0010; end
+5'd23: begin digit1 = 4'b0010; digit0 = 4'b0011; end
+
+default:  begin digit1 = 0; digit0 = 0; end
+endcase
+end
+
+assign data_HH_T = {digit1,digit0};
+
+endmodule
+"
+"//
+///////////////////////////////////////////////////////////////////////////////////////////
+// Copyright \xa9 2010-2013, Xilinx, Inc.
+// This file contains confidential and proprietary information of Xilinx, Inc. and is
+// protected under U.S. and international copyright and other intellectual property laws.
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+// Disclaimer:
+// This disclaimer is not a license and does not grant any rights to the materials
+// distributed herewith. Except as otherwise provided in a valid license issued to
+// you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
+// MATERIALS ARE MADE AVAILABLE ""AS IS"" AND WITH ALL FAULTS, AND XILINX HEREBY
+// DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
+// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
+// OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
+// (whether in contract or tort, including negligence, or under any other theory
+// of liability) for any loss or damage of any kind or nature related to, arising
+// under or in connection with these materials, including for any direct, or any
+// indirect, special, incidental, or consequential loss or damage (including loss
+// of data, profits, goodwill, or any type of loss or damage suffered as a result
+// of any action brought by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-safe, or for use in any
+// application requiring fail-safe performance, such as life-support or safety
+// devices or systems, Class III medical devices, nuclear facilities, applications
+// related to the deployment of airbags, or any other applications that could lead
+// to death, personal injury, or severe property or environmental damage
+// (individually and collectively, ""Critical Applications""). Customer assumes the
+// sole risk and liability of any use of Xilinx products in Critical Applications,
+// subject only to applicable laws and regulations governing limitations on product
+// liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+//
+// Definition of a program memory for KCPSM6 including generic parameters for the 
+// convenient selection of device family, program memory size and the ability to include 
+// the JTAG Loader hardware for rapid software development.
+//
+// This file is primarily for use during code development and it is recommended that the 
+// appropriate simplified program memory definition be used in a final production design. 
+//
+//
+//    Generic                  Values             Comments
+//    Parameter                Supported
+//  
+//    C_FAMILY                 ""S6""               Spartan-6 device
+//                             ""V6""               Virtex-6 device
+//                             ""7S""               7-Series device 
+//                                                  (Artix-7, Kintex-7, Virtex-7 or Zynq)
+//
+//    C_RAM_SIZE_KWORDS        1, 2 or 4          Size of program memory in K-instructions
+//
+//    C_JTAG_LOADER_ENABLE     0 or 1             Set to \'1\' to include JTAG Loader
+//
+// Notes
+//
+// If your design contains MULTIPLE KCPSM6 instances then only one should have the 
+// JTAG Loader enabled at a time (i.e. make sure that C_JTAG_LOADER_ENABLE is only set to 
+// \'1\' on one instance of the program memory). Advanced users may be interested to know 
+// that it is possible to connect JTAG Loader to multiple memories and then to use the 
+// JTAG Loader utility to specify which memory contents are to be modified. However, 
+// this scheme does require some effort to set up and the additional connectivity of the 
+// multiple BRAMs can impact the placement, routing and performance of the complete 
+// design. Please contact the author at Xilinx for more detailed information. 
+//
+// Regardless of the size of program memory specified by C_RAM_SIZE_KWORDS, the complete 
+// 12-bit address bus is connected to KCPSM6. This enables the generic to be modified 
+// without requiring changes to the fundamental hardware definition. However, when the 
+// program memory is 1K then only the lower 10-bits of the address are actually used and 
+// the valid address range is 000 to 3FF hex. Likewise, for a 2K program only the lower 
+// 11-bits of the address are actually used and the valid address range is 000 to 7FF hex.
+//
+// Programs are stored in Block Memory (BRAM) and the number of BRAM used depends on the 
+// size of the program and the device family. 
+//
+// In a Spartan-6 device a BRAM is capable of holding 1K instructions. Hence a 2K program 
+// will require 2 BRAMs to be used and a 4K program will require 4 BRAMs to be used. It 
+// should be noted that a 4K program is not such a natural fit in a Spartan-6 device and 
+// the implementation also requires a small amount of logic resulting in slightly lower 
+// performance. A Spartan-6 BRAM can also be split into two 9k-bit memories suggesting 
+// that a program containing up to 512 instructions could be implemented. However, there 
+// is a silicon errata which makes this unsuitable and therefore it is not supported by 
+// this file.
+//
+// In a Virtex-6 or any 7-Series device a BRAM is capable of holding 2K instructions so 
+// obviously a 2K program requires only a single BRAM. Each BRAM can also be divided into 
+// 2 smaller memories supporting programs of 1K in half of a 36k-bit BRAM (generally 
+// reported as being an 18k-bit BRAM). For a program of 4K instructions, 2 BRAMs are used.
+//
+//
+// Program defined by \'set_intrucciones_3_proyecto.fidex.psm\'.
+//
+// Generated by KCPSM6 Assembler: 2016-06-02 10:54:40 . 
+//
+// Assembler used ROM_form template: ROM_form_JTAGLoader_14March13.v
+//
+//
+`timescale 1ps/1ps
+module ROM_programa (address, instruction, enable, rdl, clk);
+//
+parameter integer C_JTAG_LOADER_ENABLE = 1;                        
+parameter         C_FAMILY = ""S6"";                        
+parameter integer C_RAM_SIZE_KWORDS = 1;                        
+//
+input         clk;        
+input  [11:0] address;        
+input         enable;        
+output [17:0] instruction;        
+output        rdl;
+//
+//
+wire [15:0] address_a;
+wire        pipe_a11;
+wire [35:0] data_in_a;
+wire [35:0] data_out_a;
+wire [35:0] data_out_a_l;
+wire [35:0] data_out_a_h;
+wire [35:0] data_out_a_ll;
+wire [35:0] data_out_a_lh;
+wire [35:0] data_out_a_hl;
+wire [35:0] data_out_a_hh;
+wire [15:0] address_b;
+wire [35:0] data_in_b;
+wire [35:0] data_in_b_l;
+wire [35:0] data_in_b_ll;
+wire [35:0] data_in_b_hl;
+wire [35:0] data_out_b;
+wire [35:0] data_out_b_l;
+wire [35:0] data_out_b_ll;
+wire [35:0] data_out_b_hl;
+wire [35:0] data_in_b_h;
+wire [35:0] data_in_b_lh;
+wire [35:0] data_in_b_hh;
+wire [35:0] data_out_b_h;
+wire [35:0] data_out_b_lh;
+wire [35:0] data_out_b_hh;
+wire        enable_b;
+wire        clk_b;
+wire [7:0]  we_b;
+wire [3:0]  we_b_l;
+wire [3:0]  we_b_h;
+//
+wire [11:0] jtag_addr;
+wire        jtag_we;
+wire        jtag_clk;
+wire [17:0] jtag_din;
+wire [17:0] jtag_dout;
+wire [17:0] jtag_dout_1;
+wire [0:0]  jtag_en;
+//
+wire [0:0]  picoblaze_reset;
+wire [0:0]  rdl_bus;
+//
+parameter integer BRAM_ADDRESS_WIDTH = addr_width_calc(C_RAM_SIZE_KWORDS);
+//
+//
+function integer addr_width_calc;
+  input integer size_in_k;
+    if (size_in_k == 1) begin addr_width_calc = 10; end
+      else if (size_in_k == 2) begin addr_width_calc = 11; end
+      else if (size_in_k == 4) begin addr_width_calc = 12; end
+      else begin
+        if (C_RAM_SIZE_KWORDS != 1 && C_RAM_SIZE_KWORDS != 2 && C_RAM_SIZE_KWORDS != 4) begin
+          //#0;
+          $display(""Invalid BlockRAM size. Please set to 1, 2 or 4 K words..\
+"");
+          $finish;
+        end
+    end
+endfunction
+//
+//
+generate
+  if (C_RAM_SIZE_KWORDS == 1) begin : ram_1k_generate 
+    //
+    if (C_FAMILY == ""S6"") begin: s6 
+      //
+      assign address_a[13:0] = {address[9:0], 4\'b0000};
+      assign instruction = {data_out_a[33:32], data_out_a[15:0]};
+      assign data_in_a = {34\'b0000000000000000000000000000000000, address[11:10]};
+      assign jtag_dout = {data_out_b[33:32], data_out_b[15:0]};
+      //
+      if (C_JTAG_LOADER_ENABLE == 0) begin : no_loader
+        assign data_in_b = {2\'b00, data_out_b[33:32], 16\'b0000000000000000, data_out_b[15:0]};
+        assign address_b[13:0] = 14\'b00000000000000;
+        assign we_b[3:0] = 4\'b0000;
+        assign enable_b = 1\'b0;
+        assign rdl = 1\'b0;
+        assign clk_b = 1\'b0;
+      end // no_loader;
+      //
+      if (C_JTAG_LOADER_ENABLE == 1) begin : loader
+        assign data_in_b = {2\'b00, jtag_din[17:16], 16\'b0000000000000000, jtag_din[15:0]};
+        assign address_b[13:0] = {jtag_addr[9:0], 4\'b0000};
+        assign we_b[3:0] = {jtag_we, jtag_we, jtag_we, jtag_we};
+        assign enable_b = jtag_en[0];
+        assign rdl = rdl_bus[0];
+        assign clk_b = jtag_clk;
+      end // loader;
+      // 
+      RAMB16BWER #(.DATA_WIDTH_A        (18),
+                   .DOA_REG             (0),
+                   .EN_RSTRAM_A         (""FALSE""),
+                   .INIT_A              (9\'b000000000),
+                   .RST_PRIORITY_A      (""CE""),
+                   .SRVAL_A             (9\'b000000000),
+                   .WRITE_MODE_A        (""WRITE_FIRST""),
+                   .DATA_WIDTH_B        (18),
+                   .DOB_REG             (0),
+                   .EN_RSTRAM_B         (""FALSE""),
+                   .INIT_B              (9\'b000000000),
+                   .RST_PRIORITY_B      (""CE""),
+                   .SRVAL_B             (9\'b000000000),
+                   .WRITE_MODE_B        (""WRITE_FIRST""),
+                   .RSTTYPE             (""SYNC""),
+                   .INIT_FILE           (""NONE""),
+                   .SIM_COLLISION_CHECK (""ALL""),
+                   .SIM_DEVICE          (""SPARTAN6""),
+                   .INIT_00             (256\'hD61136E0200E00B100C911D2101000C9110000C917FF17FF17FF111010021B00),
+                   .INIT_01             (256\'h200E0075006000EAD2530043D2540031D2460020D24800E4D24400B1D2219202),
+                   .INIT_02             (256\'h0075200ED241009CD20D0054D238005DD2360057D235005AD2349202D6111608),
+                   .INIT_03             (256\'h200ED241009CD20D0054D238005DD2360057D235005AD2349202D61116102020),
+                   .INIT_04             (256\'h0088D20D0054D238005DD2360057D235005AD2349202D6111618203100750060),
+                   .INIT_05             (256\'h5000D61116045000D61116075000D61116065000D611160520430060200ED241),
+                   .INIT_06             (256\'h00CF1025D10600CF1024D10500CF1023D10400CF1022D10300CF102100CF10F0),
+                   .INIT_07             (256\'hD10B00CF104200D9C170D10A00CF104100CF10F01A005000D10800CF1026D107),
+                   .INIT_08             (256\'h11000910911A08109119071091181A00500000D9C190D10C00CF104300D9C180),
+                   .INIT_09             (256\'h102200C991121021200E00C91108100000C910F200C9104300C9104200C91041),
+                   .INIT_0A             (256\'h00C910F100C99117102600C99116102500C99115102400C99114102300C99113),
+                   .INIT_0B             (256\'h00C91026110000C9102500C91024110100C9102300C9102200C910211100200E),
+                   .INIT_0C             (256\'h1400500000D5D40ED101D0001401500000C910F000C9104300C9104200C91041),
+                   .INIT_0D             (256\'h1A00DB0D5B01500000DDDA031A01500060D5D301930F5000911000D5D40ED000),
+                   .INIT_0E             (256\'h000000005000DB0D1B023B03500019FF18FF17FFDB0D3B02500000C911001000),
+                   .INIT_0F             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_10             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_11             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_12             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_13             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_14             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_15             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_16             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_17             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_18             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_19             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1A             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1B             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1C             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1D             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1E             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1F             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
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+                   .INIT_21             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
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+                   .INIT_28             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_29             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2A             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2B             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2C             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2D             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2E             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2F             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_30             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_31             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_32             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_33             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_34             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_35             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_36             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_37             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_38             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_39             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3A             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3B             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3C             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3D             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3E             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3F             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_00            (256\'hA36882A28A28A288A69A69ADDDDDD22ADDDDDD22B7777748AB7777748A822000),
+                   .INITP_01            (256\'h000000000A4808A022D6D22A2AA28888822088828820820820A088880000B68D),
+                   .INITP_02            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_03            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_04            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_05            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_06            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_07            (256\'h0000000000000000000000000000000000000000000000000000000000000000))
+       kcpsm6_rom( .ADDRA               (address_a[13:0]),
+                   .ENA                 (enable),
+                   .CLKA                (clk),
+                   .DOA                 (data_out_a[31:0]),
+                   .DOPA                (data_out_a[35:32]), 
+                   .DIA                 (data_in_a[31:0]),
+                   .DIPA                (data_in_a[35:32]), 
+                   .WEA                 (4\'b0000),
+                   .REGCEA              (1\'b0),
+                   .RSTA                (1\'b0),
+                   .ADDRB               (address_b[13:0]),
+                   .ENB                 (enable_b),
+                   .CLKB                (clk_b),
+                   .DOB                 (data_out_b[31:0]),
+                   .DOPB                (data_out_b[35:32]), 
+                   .DIB                 (data_in_b[31:0]),
+                   .DIPB                (data_in_b[35:32]), 
+                   .WEB                 (we_b[3:0]),
+                   .REGCEB              (1\'b0),
+                   .RSTB                (1\'b0));
+    end // s6;
+    // 
+    //
+    if (C_FAMILY == ""V6"") begin: v6 
+      //
+      assign address_a[13:0] = {address[9:0], 4\'b1111};
+      assign instruction = data_out_a[17:0];
+      assign data_in_a[17:0] = {16\'b0000000000000000, address[11:10]};
+      assign jtag_dout = data_out_b[17:0];
+      //
+      if (C_JTAG_LOADER_ENABLE == 0) begin : no_loader
+        assign data_in_b[17:0] = data_out_b[17:0];
+        assign address_b[13:0] = 14\'b11111111111111;
+        assign we_b[3:0] = 4\'b0000;
+        assign enable_b = 1\'b0;
+        assign rdl = 1\'b0;
+        assign clk_b = 1\'b0;
+      end // no_loader;
+      //
+      if (C_JTAG_LOADER_ENABLE == 1) begin : loader
+        assign data_in_b[17:0] = jtag_din[17:0];
+        assign address_b[13:0] = {jtag_addr[9:0], 4\'b1111};
+        assign we_b[3:0] = {jtag_we, jtag_we, jtag_we, jtag_we};
+        assign enable_b = jtag_en[0];
+        assign rdl = rdl_bus[0];
+        assign clk_b = jtag_clk;
+      end // loader;
+      // 
+      RAMB18E1 #(.READ_WIDTH_A              (18),
+                 .WRITE_WIDTH_A             (18),
+                 .DOA_REG                   (0),
+                 .INIT_A                    (18\'b000000000000000000),
+                 .RSTREG_PRIORITY_A         (""REGCE""),
+                 .SRVAL_A                   (18\'b000000000000000000),
+                 .WRITE_MODE_A              (""WRITE_FIRST""),
+                 .READ_WIDTH_B              (18),
+                 .WRITE_WIDTH_B             (18),
+                 .DOB_REG                   (0),
+                 .INIT_B                    (18\'b000000000000000000),
+                 .RSTREG_PRIORITY_B         (""REGCE""),
+                 .SRVAL_B                   (18\'b000000000000000000),
+                 .WRITE_MODE_B              (""WRITE_FIRST""),
+                 .INIT_FILE                 (""NONE""),
+                 .SIM_COLLISION_CHECK       (""ALL""),
+                 .RAM_MODE                  (""TDP""),
+                 .RDADDR_COLLISION_HWCONFIG (""DELAYED_WRITE""),
+                 .SIM_DEVICE                (""VIRTEX6""),
+                 .INIT_00                   (256\'hD61136E0200E00B100C911D2101000C9110000C917FF17FF17FF111010021B00),
+                 .INIT_01                   (256\'h200E0075006000EAD2530043D2540031D2460020D24800E4D24400B1D2219202),
+                 .INIT_02                   (256\'h0075200ED241009CD20D0054D238005DD2360057D235005AD2349202D6111608),
+                 .INIT_03                   (256\'h200ED241009CD20D0054D238005DD2360057D235005AD2349202D61116102020),
+                 .INIT_04                   (256\'h0088D20D0054D238005DD2360057D235005AD2349202D6111618203100750060),
+                 .INIT_05                   (256\'h5000D61116045000D61116075000D61116065000D611160520430060200ED241),
+                 .INIT_06                   (256\'h00CF1025D10600CF1024D10500CF1023D10400CF1022D10300CF102100CF10F0),
+                 .INIT_07                   (256\'hD10B00CF104200D9C170D10A00CF104100CF10F01A005000D10800CF1026D107),
+                 .INIT_08                   (256\'h11000910911A08109119071091181A00500000D9C190D10C00CF104300D9C180),
+                 .INIT_09                   (256\'h102200C991121021200E00C91108100000C910F200C9104300C9104200C91041),
+                 .INIT_0A                   (256\'h00C910F100C99117102600C99116102500C99115102400C99114102300C99113),
+                 .INIT_0B                   (256\'h00C91026110000C9102500C91024110100C9102300C9102200C910211100200E),
+                 .INIT_0C                   (256\'h1400500000D5D40ED101D0001401500000C910F000C9104300C9104200C91041),
+                 .INIT_0D                   (256\'h1A00DB0D5B01500000DDDA031A01500060D5D301930F5000911000D5D40ED000),
+                 .INIT_0E                   (256\'h000000005000DB0D1B023B03500019FF18FF17FFDB0D3B02500000C911001000),
+                 .INIT_0F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_10                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_11                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_12                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_13                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_14                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_15                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_16                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_17                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_18                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_19                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_20                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_21                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_22                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_23                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_24                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_25                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_26                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_27                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_28                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_29                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_30                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_31                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_32                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_33                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_34                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_35                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_36                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_37                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_38                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_39                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_00                  (256\'hA36882A28A28A288A69A69ADDDDDD22ADDDDDD22B7777748AB7777748A822000),
+                 .INITP_01                  (256\'h000000000A4808A022D6D22A2AA28888822088828820820820A088880000B68D),
+                 .INITP_02                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_03                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_04                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_05                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_06                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_07                  (256\'h0000000000000000000000000000000000000000000000000000000000000000))
+     kcpsm6_rom( .ADDRARDADDR               (address_a[13:0]),
+                 .ENARDEN                   (enable),
+                 .CLKARDCLK                 (clk),
+                 .DOADO                     (data_out_a[15:0]),
+                 .DOPADOP                   (data_out_a[17:16]), 
+                 .DIADI                     (data_in_a[15:0]),
+                 .DIPADIP                   (data_in_a[17:16]), 
+                 .WEA                       (2\'b00),
+                 .REGCEAREGCE               (1\'b0),
+                 .RSTRAMARSTRAM             (1\'b0),
+                 .RSTREGARSTREG             (1\'b0),
+                 .ADDRBWRADDR               (address_b[13:0]),
+                 .ENBWREN                   (enable_b),
+                 .CLKBWRCLK                 (clk_b),
+                 .DOBDO                     (data_out_b[15:0]),
+                 .DOPBDOP                   (data_out_b[17:16]), 
+                 .DIBDI                     (data_in_b[15:0]),
+                 .DIPBDIP                   (data_in_b[17:16]), 
+                 .WEBWE                     (we_b[3:0]),
+                 .REGCEB                    (1\'b0),
+                 .RSTRAMB                   (1\'b0),
+                 .RSTREGB                   (1\'b0));
+    end // v6;  
+    // 
+    //
+    if (C_FAMILY == ""7S"") begin: akv7 
+      //
+      assign address_a[13:0] = {address[9:0], 4\'b1111};
+      assign instruction = data_out_a[17:0];
+      assign data_in_a[17:0] = {16\'b0000000000000000, address[11:10]};
+      assign jtag_dout = data_out_b[17:0];
+      //
+      if (C_JTAG_LOADER_ENABLE == 0) begin : no_loader
+        assign data_in_b[17:0] = data_out_b[17:0];
+        assign address_b[13:0] = 14\'b11111111111111;
+        assign we_b[3:0] = 4\'b0000;
+        assign enable_b = 1\'b0;
+        assign rdl = 1\'b0;
+        assign clk_b = 1\'b0;
+      end // no_loader;
+      //
+      if (C_JTAG_LOADER_ENABLE == 1) begin : loader
+        assign data_in_b[17:0] = jtag_din[17:0];
+        assign address_b[13:0] = {jtag_addr[9:0], 4\'b1111};
+        assign we_b[3:0] = {jtag_we, jtag_we, jtag_we, jtag_we};
+        assign enable_b = jtag_en[0];
+        assign rdl = rdl_bus[0];
+        assign clk_b = jtag_clk;
+      end // loader;
+      // 
+      RAMB18E1 #(.READ_WIDTH_A              (18),
+                 .WRITE_WIDTH_A             (18),
+                 .DOA_REG                   (0),
+                 .INIT_A                    (18\'b000000000000000000),
+                 .RSTREG_PRIORITY_A         (""REGCE""),
+                 .SRVAL_A                   (18\'b000000000000000000),
+                 .WRITE_MODE_A              (""WRITE_FIRST""),
+                 .READ_WIDTH_B              (18),
+                 .WRITE_WIDTH_B             (18),
+                 .DOB_REG                   (0),
+                 .INIT_B                    (18\'b000000000000000000),
+                 .RSTREG_PRIORITY_B         (""REGCE""),
+                 .SRVAL_B                   (18\'b000000000000000000),
+                 .WRITE_MODE_B              (""WRITE_FIRST""),
+                 .INIT_FILE                 (""NONE""),
+                 .SIM_COLLISION_CHECK       (""ALL""),
+                 .RAM_MODE                  (""TDP""),
+                 .RDADDR_COLLISION_HWCONFIG (""DELAYED_WRITE""),
+                 .SIM_DEVICE                (""7SERIES""),
+                 .INIT_00                   (256\'hD61136E0200E00B100C911D2101000C9110000C917FF17FF17FF111010021B00),
+                 .INIT_01                   (256\'h200E0075006000EAD2530043D2540031D2460020D24800E4D24400B1D2219202),
+                 .INIT_02                   (256\'h0075200ED241009CD20D0054D238005DD2360057D235005AD2349202D6111608),
+                 .INIT_03                   (256\'h200ED241009CD20D0054D238005DD2360057D235005AD2349202D61116102020),
+                 .INIT_04                   (256\'h0088D20D0054D238005DD2360057D235005AD2349202D6111618203100750060),
+                 .INIT_05                   (256\'h5000D61116045000D61116075000D61116065000D611160520430060200ED241),
+                 .INIT_06                   (256\'h00CF1025D10600CF1024D10500CF1023D10400CF1022D10300CF102100CF10F0),
+                 .INIT_07                   (256\'hD10B00CF104200D9C170D10A00CF104100CF10F01A005000D10800CF1026D107),
+                 .INIT_08                   (256\'h11000910911A08109119071091181A00500000D9C190D10C00CF104300D9C180),
+                 .INIT_09                   (256\'h102200C991121021200E00C91108100000C910F200C9104300C9104200C91041),
+                 .INIT_0A                   (256\'h00C910F100C99117102600C99116102500C99115102400C99114102300C99113),
+                 .INIT_0B                   (256\'h00C91026110000C9102500C91024110100C9102300C9102200C910211100200E),
+                 .INIT_0C                   (256\'h1400500000D5D40ED101D0001401500000C910F000C9104300C9104200C91041),
+                 .INIT_0D                   (256\'h1A00DB0D5B01500000DDDA031A01500060D5D301930F5000911000D5D40ED000),
+                 .INIT_0E                   (256\'h000000005000DB0D1B023B03500019FF18FF17FFDB0D3B02500000C911001000),
+                 .INIT_0F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_10                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_11                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_12                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_13                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_14                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_15                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_16                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_17                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_18                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_19                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_20                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_21                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_22                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_23                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_24                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_25                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_26                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_27                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_28                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_29                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_30                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_31                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_32                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_33                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_34                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_35                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_36                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_37                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_38                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_39                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_00                  (256\'hA36882A28A28A288A69A69ADDDDDD22ADDDDDD22B7777748AB7777748A822000),
+                 .INITP_01                  (256\'h000000000A4808A022D6D22A2AA28888822088828820820820A088880000B68D),
+                 .INITP_02                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_03                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_04                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_05                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_06                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_07                  (256\'h0000000000000000000000000000000000000000000000000000000000000000))
+     kcpsm6_rom( .ADDRARDADDR               (address_a[13:0]),
+                 .ENARDEN                   (enable),
+                 .CLKARDCLK                 (clk),
+                 .DOADO                     (data_out_a[15:0]),
+                 .DOPADOP                   (data_out_a[17:16]), 
+                 .DIADI                     (data_in_a[15:0]),
+                 .DIPADIP                   (data_in_a[17:16]), 
+                 .WEA                       (2\'b00),
+                 .REGCEAREGCE               (1\'b0),
+                 .RSTRAMARSTRAM             (1\'b0),
+                 .RSTREGARSTREG             (1\'b0),
+                 .ADDRBWRADDR               (address_b[13:0]),
+                 .ENBWREN                   (enable_b),
+                 .CLKBWRCLK                 (clk_b),
+                 .DOBDO                     (data_out_b[15:0]),
+                 .DOPBDOP                   (data_out_b[17:16]), 
+                 .DIBDI                     (data_in_b[15:0]),
+                 .DIPBDIP                   (data_in_b[17:16]), 
+                 .WEBWE                     (we_b[3:0]),
+                 .REGCEB                    (1\'b0),
+                 .RSTRAMB                   (1\'b0),
+                 .RSTREGB                   (1\'b0));
+    end // akv7;  
+    // 
+  end // ram_1k_generate;
+endgenerate
+//  
+generate
+  if (C_RAM_SIZE_KWORDS == 2) begin : ram_2k_generate 
+    //
+    if (C_FAMILY == ""S6"") begin: s6 
+      //
+      assign address_a[13:0] = {address[10:0], 3\'b000};
+      assign instruction = {data_out_a_h[32], data_out_a_h[7:0], data_out_a_l[32], data_out_a_l[7:0]};
+      assign data_in_a = {35\'b00000000000000000000000000000000000, address[11]};
+      assign jtag_dout = {data_out_b_h[32], data_out_b_h[7:0], data_out_b_l[32], data_out_b_l[7:0]};
+      //
+      if (C_JTAG_LOADER_ENABLE == 0) begin : no_loader
+        assign data_in_b_l = {3\'b000, data_out_b_l[32], 24\'b000000000000000000000000, data_out_b_l[7:0]};
+        assign data_in_b_h = {3\'b000, data_out_b_h[32], 24\'b000000000000000000000000, data_out_b_h[7:0]};
+        assign address_b[13:0] = 14\'b00000000000000;
+        assign we_b[3:0] = 4\'b0000;
+        assign enable_b = 1\'b0;
+        assign rdl = 1\'b0;
+        assign clk_b = 1\'b0;
+      end // no_loader;
+      //
+      if (C_JTAG_LOADER_ENABLE == 1) begin : loader
+        assign data_in_b_h = {3\'b000, jtag_din[17], 24\'b000000000000000000000000, jtag_din[16:9]};
+        assign data_in_b_l = {3\'b000, jtag_din[8],  24\'b000000000000000000000000, jtag_din[7:0]};
+        assign address_b[13:0] = {jtag_addr[10:0], 3\'b000};
+        assign we_b[3:0] = {jtag_we, jtag_we, jtag_we, jtag_we};
+        assign enable_b = jtag_en[0];
+        assign rdl = rdl_bus[0];
+        assign clk_b = jtag_clk;
+      end // loader;
+      // 
+      RAMB16BWER #(.DATA_WIDTH_A        (9),
+                   .DOA_REG             (0),
+                   .EN_RSTRAM_A         (""FALSE""),
+                   .INIT_A              (9\'b000000000),
+                   .RST_PRIORITY_A      (""CE""),
+                   .SRVAL_A             (9\'b000000000),
+                   .WRITE_MODE_A        (""WRITE_FIRST""),
+                   .DATA_WIDTH_B        (9),
+                   .DOB_REG             (0),
+                   .EN_RSTRAM_B         (""FALSE""),
+                   .INIT_B              (9\'b000000000),
+                   .RST_PRIORITY_B      (""CE""),
+                   .SRVAL_B             (9\'b000000000),
+                   .WRITE_MODE_B        (""WRITE_FIRST""),
+                   .RSTTYPE             (""SYNC""),
+                   .INIT_FILE           (""NONE""),
+                   .SIM_COLLISION_CHECK (""ALL""),
+                   .SIM_DEVICE          (""SPARTAN6""),
+                   .INIT_00             (256\'h0E7560EA53435431462048E444B1210211E00EB1C9D210C900C9FFFFFF100200),
+                   .INIT_01             (256\'h0E419C0D54385D3657355A3402111020750E419C0D54385D3657355A34021108),
+                   .INIT_02             (256\'h00110400110700110600110543600E41880D54385D3657355A34021118317560),
+                   .INIT_03             (256\'h0BCF42D9700ACF41CFF0000008CF2607CF2506CF2405CF2304CF2203CF21CFF0),
+                   .INIT_04             (256\'h22C912210EC90800C9F2C943C942C94100101A101910180000D9900CCF43D980),
+                   .INIT_05             (256\'hC92600C925C92401C923C922C921000EC9F1C91726C91625C91524C91423C913),
+                   .INIT_06             (256\'h000D0100DD030100D5010F0010D50E000000D50E01000100C9F0C943C942C941),
+                   .INIT_07             (256\'h000000000000000000000000000000000000000D020300FFFFFF0D0200C90000),
+                   .INIT_08             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_09             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0A             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0B             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0C             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0D             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0E             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0F             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_10             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_11             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_12             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_13             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_14             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_15             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_16             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_17             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_18             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_19             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1A             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1B             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1C             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1D             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1E             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1F             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_20             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_21             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_22             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_23             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_24             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_25             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_26             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_27             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_28             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_29             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2A             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2B             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2C             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2D             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2E             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2F             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_30             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_31             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_32             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_33             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_34             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_35             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_36             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_37             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_38             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_39             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3A             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3B             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3C             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3D             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3E             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3F             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_00            (256\'h00001D7260680800210212492200EE318C0924900000000000000000000004BD),
+                   .INITP_01            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_02            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_03            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_04            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_05            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_06            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_07            (256\'h0000000000000000000000000000000000000000000000000000000000000000))
+     kcpsm6_rom_l( .ADDRA               (address_a[13:0]),
+                   .ENA                 (enable),
+                   .CLKA                (clk),
+                   .DOA                 (data_out_a_l[31:0]),
+                   .DOPA                (data_out_a_l[35:32]), 
+                   .DIA                 (data_in_a[31:0]),
+                   .DIPA                (data_in_a[35:32]), 
+                   .WEA                 (4\'b0000),
+                   .REGCEA              (1\'b0),
+                   .RSTA                (1\'b0),
+                   .ADDRB               (address_b[13:0]),
+                   .ENB                 (enable_b),
+                   .CLKB                (clk_b),
+                   .DOB                 (data_out_b_l[31:0]),
+                   .DOPB                (data_out_b_l[35:32]), 
+                   .DIB                 (data_in_b_l[31:0]),
+                   .DIPB                (data_in_b_l[35:32]), 
+                   .WEB                 (we_b[3:0]),
+                   .REGCEB              (1\'b0),
+                   .RSTB                (1\'b0));
+      // 
+      RAMB16BWER #(.DATA_WIDTH_A        (9),
+                   .DOA_REG             (0),
+                   .EN_RSTRAM_A         (""FALSE""),
+                   .INIT_A              (9\'b000000000),
+                   .RST_PRIORITY_A      (""CE""),
+                   .SRVAL_A             (9\'b000000000),
+                   .WRITE_MODE_A        (""WRITE_FIRST""),
+                   .DATA_WIDTH_B        (9),
+                   .DOB_REG             (0),
+                   .EN_RSTRAM_B         (""FALSE""),
+                   .INIT_B              (9\'b000000000),
+                   .RST_PRIORITY_B      (""CE""),
+                   .SRVAL_B             (9\'b000000000),
+                   .WRITE_MODE_B        (""WRITE_FIRST""),
+                   .RSTTYPE             (""SYNC""),
+                   .INIT_FILE           (""NONE""),
+                   .SIM_COLLISION_CHECK (""ALL""),
+                   .SIM_DEVICE          (""SPARTAN6""),
+                   .INIT_00             (256\'h10000080E980E980E980E980E980E9496B1B10000008080008000B0B0B08080D),
+                   .INIT_01             (256\'h90E980E980E980E980E980E9496B0B100090E980E980E980E980E980E9496B0B),
+                   .INIT_02             (256\'h286B8B286B8B286B8B286B8B100090E980E980E980E980E980E9496B0B100000),
+                   .INIT_03             (256\'h68000880E068000800080D286800086800086800086800086800086800080008),
+                   .INIT_04             (256\'h08004808100008080008000800080008080448044803480D2880E068000880E0),
+                   .INIT_05             (256\'h0008080008000808000800080008081000080048080048080048080048080048),
+                   .INIT_06             (256\'h0D6D2D2880ED8D28B0E9492848006A680A28006A68680A280008000800080008),
+                   .INIT_07             (256\'h000000000000000000000000000000000000286D8D1D280C0C0B6D1D28000808),
+                   .INIT_08             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_09             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0A             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0B             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0C             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0D             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0E             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0F             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_10             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_11             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_12             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_13             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_14             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_15             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_16             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_17             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_18             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_19             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1A             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1B             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1C             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1D             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1E             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1F             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_20             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_21             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_22             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_23             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_24             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_25             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_26             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_27             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_28             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_29             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2A             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2B             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2C             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2D             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2E             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2F             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_30             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_31             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_32             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_33             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_34             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_35             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_36             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_37             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_38             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_39             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3A             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3B             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3C             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3D             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3E             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3F             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_00            (256\'h0000322C59977DAA94A9A4924CAA00DAD69DB6DADB6EAA97AAA5D552F554B940),
+                   .INITP_01            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_02            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_03            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_04            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_05            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_06            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_07            (256\'h0000000000000000000000000000000000000000000000000000000000000000))
+     kcpsm6_rom_h( .ADDRA               (address_a[13:0]),
+                   .ENA                 (enable),
+                   .CLKA                (clk),
+                   .DOA                 (data_out_a_h[31:0]),
+                   .DOPA                (data_out_a_h[35:32]), 
+                   .DIA                 (data_in_a[31:0]),
+                   .DIPA                (data_in_a[35:32]), 
+                   .WEA                 (4\'b0000),
+                   .REGCEA              (1\'b0),
+                   .RSTA                (1\'b0),
+                   .ADDRB               (address_b[13:0]),
+                   .ENB                 (enable_b),
+                   .CLKB                (clk_b),
+                   .DOB                 (data_out_b_h[31:0]),
+                   .DOPB                (data_out_b_h[35:32]), 
+                   .DIB                 (data_in_b_h[31:0]),
+                   .DIPB                (data_in_b_h[35:32]), 
+                   .WEB                 (we_b[3:0]),
+                   .REGCEB              (1\'b0),
+                   .RSTB                (1\'b0));
+    end // s6;
+    // 
+    // 
+    if (C_FAMILY == ""V6"") begin: v6 
+      //
+      assign address_a = {1\'b1, address[10:0], 4\'b1111};
+      assign instruction = {data_out_a[33:32], data_out_a[15:0]};
+      assign data_in_a = {35\'b00000000000000000000000000000000000, address[11]};
+      assign jtag_dout = {data_out_b[33:32], data_out_b[15:0]};
+      //
+      if (C_JTAG_LOADER_ENABLE == 0) begin : no_loader
+        assign data_in_b = {2\'b00, data_out_b[33:32], 16\'b0000000000000000, data_out_b[15:0]};
+        assign address_b = 16\'b1111111111111111;
+        assign we_b = 8\'b00000000;
+        assign enable_b = 1\'b0;
+        assign rdl = 1\'b0;
+        assign clk_b = 1\'b0;
+      end // no_loader;
+      //
+      if (C_JTAG_LOADER_ENABLE == 1) begin : loader
+        assign data_in_b = {2\'b00, jtag_din[17:16], 16\'b0000000000000000, jtag_din[15:0]};
+        assign address_b = {1\'b1, jtag_addr[10:0], 4\'b1111};
+        assign we_b = {jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we};
+        assign enable_b = jtag_en[0];
+        assign rdl = rdl_bus[0];
+        assign clk_b = jtag_clk;
+      end // loader;
+      // 
+      RAMB36E1 #(.READ_WIDTH_A              (18),
+                 .WRITE_WIDTH_A             (18),
+                 .DOA_REG                   (0),
+                 .INIT_A                    (36\'h000000000),
+                 .RSTREG_PRIORITY_A         (""REGCE""),
+                 .SRVAL_A                   (36\'h000000000),
+                 .WRITE_MODE_A              (""WRITE_FIRST""),
+                 .READ_WIDTH_B              (18),
+                 .WRITE_WIDTH_B             (18),
+                 .DOB_REG                   (0),
+                 .INIT_B                    (36\'h000000000),
+                 .RSTREG_PRIORITY_B         (""REGCE""),
+                 .SRVAL_B                   (36\'h000000000),
+                 .WRITE_MODE_B              (""WRITE_FIRST""),
+                 .INIT_FILE                 (""NONE""),
+                 .SIM_COLLISION_CHECK       (""ALL""),
+                 .RAM_MODE                  (""TDP""),
+                 .RDADDR_COLLISION_HWCONFIG (""DELAYED_WRITE""),
+                 .EN_ECC_READ               (""FALSE""),
+                 .EN_ECC_WRITE              (""FALSE""),
+                 .RAM_EXTENSION_A           (""NONE""),
+                 .RAM_EXTENSION_B           (""NONE""),
+                 .SIM_DEVICE                (""VIRTEX6""),
+                 .INIT_00                   (256\'hD61136E0200E00B100C911D2101000C9110000C917FF17FF17FF111010021B00),
+                 .INIT_01                   (256\'h200E0075006000EAD2530043D2540031D2460020D24800E4D24400B1D2219202),
+                 .INIT_02                   (256\'h0075200ED241009CD20D0054D238005DD2360057D235005AD2349202D6111608),
+                 .INIT_03                   (256\'h200ED241009CD20D0054D238005DD2360057D235005AD2349202D61116102020),
+                 .INIT_04                   (256\'h0088D20D0054D238005DD2360057D235005AD2349202D6111618203100750060),
+                 .INIT_05                   (256\'h5000D61116045000D61116075000D61116065000D611160520430060200ED241),
+                 .INIT_06                   (256\'h00CF1025D10600CF1024D10500CF1023D10400CF1022D10300CF102100CF10F0),
+                 .INIT_07                   (256\'hD10B00CF104200D9C170D10A00CF104100CF10F01A005000D10800CF1026D107),
+                 .INIT_08                   (256\'h11000910911A08109119071091181A00500000D9C190D10C00CF104300D9C180),
+                 .INIT_09                   (256\'h102200C991121021200E00C91108100000C910F200C9104300C9104200C91041),
+                 .INIT_0A                   (256\'h00C910F100C99117102600C99116102500C99115102400C99114102300C99113),
+                 .INIT_0B                   (256\'h00C91026110000C9102500C91024110100C9102300C9102200C910211100200E),
+                 .INIT_0C                   (256\'h1400500000D5D40ED101D0001401500000C910F000C9104300C9104200C91041),
+                 .INIT_0D                   (256\'h1A00DB0D5B01500000DDDA031A01500060D5D301930F5000911000D5D40ED000),
+                 .INIT_0E                   (256\'h000000005000DB0D1B023B03500019FF18FF17FFDB0D3B02500000C911001000),
+                 .INIT_0F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_10                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_11                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_12                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_13                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_14                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_15                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_16                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_17                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_18                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_19                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_20                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_21                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_22                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_23                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_24                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_25                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_26                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_27                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_28                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_29                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_30                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_31                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_32                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_33                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_34                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_35                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_36                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_37                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_38                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_39                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_'b'3A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_40                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_41                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_42                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_43                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_44                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_45                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_46                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_47                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_48                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_49                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_50                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_51                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_52                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_53                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_54                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_55                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_56                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_57                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_58                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_59                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_60                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_61                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_62                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_63                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_64                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_65                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_66                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_67                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_68                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_69                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_70                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_71                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_72                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_73                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_74                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_75                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_76                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_77                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_78                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_79                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_00                  (256\'hA36882A28A28A288A69A69ADDDDDD22ADDDDDD22B7777748AB7777748A822000),
+                 .INITP_01                  (256\'h000000000A4808A022D6D22A2AA28888822088828820820820A088880000B68D),
+                 .INITP_02                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_03                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_04                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_05                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_06                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_07                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_08                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_09                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0A                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0B                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0C                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0D                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0E                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0F                  (256\'h0000000000000000000000000000000000000000000000000000000000000000))
+     kcpsm6_rom( .ADDRARDADDR               (address_a),
+                 .ENARDEN                   (enable),
+                 .CLKARDCLK                 (clk),
+                 .DOADO                     (data_out_a[31:0]),
+                 .DOPADOP                   (data_out_a[35:32]), 
+                 .DIADI                     (data_in_a[31:0]),
+                 .DIPADIP                   (data_in_a[35:32]), 
+                 .WEA                       (4\'b0000),
+                 .REGCEAREGCE               (1\'b0),
+                 .RSTRAMARSTRAM             (1\'b0),
+                 .RSTREGARSTREG             (1\'b0),
+                 .ADDRBWRADDR               (address_b),
+                 .ENBWREN                   (enable_b),
+                 .CLKBWRCLK                 (clk_b),
+                 .DOBDO                     (data_out_b[31:0]),
+                 .DOPBDOP                   (data_out_b[35:32]), 
+                 .DIBDI                     (data_in_b[31:0]),
+                 .DIPBDIP                   (data_in_b[35:32]), 
+                 .WEBWE                     (we_b),
+                 .REGCEB                    (1\'b0),
+                 .RSTRAMB                   (1\'b0),
+                 .RSTREGB                   (1\'b0),
+                 .CASCADEINA                (1\'b0),
+                 .CASCADEINB                (1\'b0),
+                 .CASCADEOUTA               (),
+                 .CASCADEOUTB               (),
+                 .DBITERR                   (),
+                 .ECCPARITY                 (),
+                 .RDADDRECC                 (),
+                 .SBITERR                   (),
+                 .INJECTDBITERR             (1\'b0),       
+                 .INJECTSBITERR             (1\'b0));   
+    end // v6;  
+    // 
+    // 
+    if (C_FAMILY == ""7S"") begin: akv7 
+      //
+      assign address_a = {1\'b1, address[10:0], 4\'b1111};
+      assign instruction = {data_out_a[33:32], data_out_a[15:0]};
+      assign data_in_a = {35\'b00000000000000000000000000000000000, address[11]};
+      assign jtag_dout = {data_out_b[33:32], data_out_b[15:0]};
+      //
+      if (C_JTAG_LOADER_ENABLE == 0) begin : no_loader
+        assign data_in_b = {2\'b00, data_out_b[33:32], 16\'b0000000000000000, data_out_b[15:0]};
+        assign address_b = 16\'b1111111111111111;
+        assign we_b = 8\'b00000000;
+        assign enable_b = 1\'b0;
+        assign rdl = 1\'b0;
+        assign clk_b = 1\'b0;
+      end // no_loader;
+      //
+      if (C_JTAG_LOADER_ENABLE == 1) begin : loader
+        assign data_in_b = {2\'b00, jtag_din[17:16], 16\'b0000000000000000, jtag_din[15:0]};
+        assign address_b = {1\'b1, jtag_addr[10:0], 4\'b1111};
+        assign we_b = {jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we};
+        assign enable_b = jtag_en[0];
+        assign rdl = rdl_bus[0];
+        assign clk_b = jtag_clk;
+      end // loader;
+      // 
+      RAMB36E1 #(.READ_WIDTH_A              (18),
+                 .WRITE_WIDTH_A             (18),
+                 .DOA_REG                   (0),
+                 .INIT_A                    (36\'h000000000),
+                 .RSTREG_PRIORITY_A         (""REGCE""),
+                 .SRVAL_A                   (36\'h000000000),
+                 .WRITE_MODE_A              (""WRITE_FIRST""),
+                 .READ_WIDTH_B              (18),
+                 .WRITE_WIDTH_B             (18),
+                 .DOB_REG                   (0),
+                 .INIT_B                    (36\'h000000000),
+                 .RSTREG_PRIORITY_B         (""REGCE""),
+                 .SRVAL_B                   (36\'h000000000),
+                 .WRITE_MODE_B              (""WRITE_FIRST""),
+                 .INIT_FILE                 (""NONE""),
+                 .SIM_COLLISION_CHECK       (""ALL""),
+                 .RAM_MODE                  (""TDP""),
+                 .RDADDR_COLLISION_HWCONFIG (""DELAYED_WRITE""),
+                 .EN_ECC_READ               (""FALSE""),
+                 .EN_ECC_WRITE              (""FALSE""),
+                 .RAM_EXTENSION_A           (""NONE""),
+                 .RAM_EXTENSION_B           (""NONE""),
+                 .SIM_DEVICE                (""7SERIES""),
+                 .INIT_00                   (256\'hD61136E0200E00B100C911D2101000C9110000C917FF17FF17FF111010021B00),
+                 .INIT_01                   (256\'h200E0075006000EAD2530043D2540031D2460020D24800E4D24400B1D2219202),
+                 .INIT_02                   (256\'h0075200ED241009CD20D0054D238005DD2360057D235005AD2349202D6111608),
+                 .INIT_03                   (256\'h200ED241009CD20D0054D238005DD2360057D235005AD2349202D61116102020),
+                 .INIT_04                   (256\'h0088D20D0054D238005DD2360057D235005AD2349202D6111618203100750060),
+                 .INIT_05                   (256\'h5000D61116045000D61116075000D61116065000D611160520430060200ED241),
+                 .INIT_06                   (256\'h00CF1025D10600CF1024D10500CF1023D10400CF1022D10300CF102100CF10F0),
+                 .INIT_07                   (256\'hD10B00CF104200D9C170D10A00CF104100CF10F01A005000D10800CF1026D107),
+                 .INIT_08                   (256\'h11000910911A08109119071091181A00500000D9C190D10C00CF104300D9C180),
+                 .INIT_09                   (256\'h102200C991121021200E00C91108100000C910F200C9104300C9104200C91041),
+                 .INIT_0A                   (256\'h00C910F100C99117102600C99116102500C99115102400C99114102300C99113),
+                 .INIT_0B                   (256\'h00C91026110000C9102500C91024110100C9102300C9102200C910211100200E),
+                 .INIT_0C                   (256\'h1400500000D5D40ED101D0001401500000C910F000C9104300C9104200C91041),
+                 .INIT_0D                   (256\'h1A00DB0D5B01500000DDDA031A01500060D5D301930F5000911000D5D40ED000),
+                 .INIT_0E                   (256\'h000000005000DB0D1B023B03500019FF18FF17FFDB0D3B02500000C911001000),
+                 .INIT_0F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_10                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_11                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_12                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_13                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_14                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_15                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_16                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_17                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_18                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_19                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_20                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_21                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_22                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_23                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_24                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_25                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_26                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_27                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_28                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_29                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_30                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_31                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_32                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_33                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_34                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_35                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_36                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_37                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_38                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_39                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_40                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_41                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_42                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_43                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_44                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_45                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_46                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_47                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_48                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_49                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_50                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_51                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_52                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_53                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_54                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_55                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_56                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_57                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_58                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_59                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_60                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_61                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_62                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_63                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_64                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_65                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_66                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_67                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_68                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_69                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_70                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_71                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_72                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_73                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_74                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_75                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_76                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_77                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_78                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_79                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_00                  (256\'hA36882A28A28A288A69A69ADDDDDD22ADDDDDD22B7777748AB7777748A822000),
+                 .INITP_01                  (256\'h000000000A4808A022D6D22A2AA28888822088828820820820A088880000B68D),
+                 .INITP_02                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_03                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_04                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_05                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_06                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_07                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_08                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_09                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0A                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0B                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0C                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0D                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0E                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0F                  (256\'h0000000000000000000000000000000000000000000000000000000000000000))
+     kcpsm6_rom( .ADDRARDADDR               (address_a),
+                 .ENARDEN                   (enable),
+                 .CLKARDCLK                 (clk),
+                 .DOADO                     (data_out_a[31:0]),
+                 .DOPADOP                   (data_out_a[35:32]), 
+                 .DIADI                     (data_in_a[31:0]),
+                 .DIPADIP                   (data_in_a[35:32]), 
+                 .WEA                       (4\'b0000),
+                 .REGCEAREGCE               (1\'b0),
+                 .RSTRAMARSTRAM             (1\'b0),
+                 .RSTREGARSTREG             (1\'b0),
+                 .ADDRBWRADDR               (address_b),
+                 .ENBWREN                   (enable_b),
+                 .CLKBWRCLK                 (clk_b),
+                 .DOBDO                     (data_out_b[31:0]),
+                 .DOPBDOP                   (data_out_b[35:32]), 
+                 .DIBDI                     (data_in_b[31:0]),
+                 .DIPBDIP                   (data_in_b[35:32]), 
+                 .WEBWE                     (we_b),
+                 .REGCEB                    (1\'b0),
+                 .RSTRAMB                   (1\'b0),
+                 .RSTREGB                   (1\'b0),
+                 .CASCADEINA                (1\'b0),
+                 .CASCADEINB                (1\'b0),
+                 .CASCADEOUTA               (),
+                 .CASCADEOUTB               (),
+                 .DBITERR                   (),
+                 .ECCPARITY                 (),
+                 .RDADDRECC                 (),
+                 .SBITERR                   (),
+                 .INJECTDBITERR             (1\'b0),       
+                 .INJECTSBITERR             (1\'b0));   
+    end // akv7;  
+    // 
+  end // ram_2k_generate;
+endgenerate              
+//
+generate
+  if (C_RAM_SIZE_KWORDS == 4) begin : ram_4k_generate 
+    if (C_FAMILY == ""S6"") begin: s6 
+      //
+      assign address_a[13:0] = {address[10:0], 3\'b000};
+      assign data_in_a = 36\'b000000000000000000000000000000000000;
+      //
+      FD s6_a11_flop ( .D      (address[11]),
+                       .Q      (pipe_a11),
+                       .C      (clk));
+      //
+      LUT6_2 # (       .INIT   (64\'hFF00F0F0CCCCAAAA))
+       s6_4k_mux0_lut( .I0     (data_out_a_ll[0]),
+                       .I1     (data_out_a_hl[0]),
+                       .I2     (data_out_a_ll[1]),
+                       .I3     (data_out_a_hl[1]),
+                       .I4     (pipe_a11),
+                       .I5     (1\'b1),
+                       .O5     (instruction[0]),
+                       .O6     (instruction[1]));
+      //
+      LUT6_2 # (       .INIT   (64\'hFF00F0F0CCCCAAAA))
+       s6_4k_mux2_lut( .I0     (data_out_a_ll[2]),
+                       .I1     (data_out_a_hl[2]),
+                       .I2     (data_out_a_ll[3]),
+                       .I3     (data_out_a_hl[3]),
+                       .I4     (pipe_a11),
+                       .I5     (1\'b1),
+                       .O5     (instruction[2]),
+                       .O6     (instruction[3]));
+      //
+      LUT6_2 # (       .INIT   (64\'hFF00F0F0CCCCAAAA))
+       s6_4k_mux4_lut( .I0     (data_out_a_ll[4]),
+                       .I1     (data_out_a_hl[4]),
+                       .I2     (data_out_a_ll[5]),
+                       .I3     (data_out_a_hl[5]),
+                       .I4     (pipe_a11),
+                       .I5     (1\'b1),
+                       .O5     (instruction[4]),
+                       .O6     (instruction[5]));
+      //
+      LUT6_2 # (       .INIT   (64\'hFF00F0F0CCCCAAAA))
+       s6_4k_mux6_lut( .I0     (data_out_a_ll[6]),
+                       .I1     (data_out_a_hl[6]),
+                       .I2     (data_out_a_ll[7]),
+                       .I3     (data_out_a_hl[7]),
+                       .I4     (pipe_a11),
+                       .I5     (1\'b1),
+                       .O5     (instruction[6]),
+                       .O6     (instruction[7]));
+      //
+      LUT6_2 # (       .INIT   (64\'hFF00F0F0CCCCAAAA))
+       s6_4k_mux8_lut( .I0     (data_out_a_ll[32]),
+                       .I1     (data_out_a_hl[32]),
+                       .I2     (data_out_a_lh[0]),
+                       .I3     (data_out_a_hh[0]),
+                       .I4     (pipe_a11),
+                       .I5     (1\'b1),
+                       .O5     (instruction[8]),
+                       .O6     (instruction[9]));
+      //
+      LUT6_2 # (       .INIT   (64\'hFF00F0F0CCCCAAAA))
+      s6_4k_mux10_lut( .I0     (data_out_a_lh[1]),
+                       .I1     (data_out_a_hh[1]),
+                       .I2     (data_out_a_lh[2]),
+                       .I3     (data_out_a_hh[2]),
+                       .I4     (pipe_a11),
+                       .I5     (1\'b1),
+                       .O5     (instruction[10]),
+                       .O6     (instruction[11]));
+      //
+      LUT6_2 # (       .INIT   (64\'hFF00F0F0CCCCAAAA))
+      s6_4k_mux12_lut( .I0     (data_out_a_lh[3]),
+                       .I1     (data_out_a_hh[3]),
+                       .I2     (data_out_a_lh[4]),
+                       .I3     (data_out_a_hh[4]),
+                       .I4     (pipe_a11),
+                       .I5     (1\'b1),
+                       .O5     (instruction[12]),
+                       .O6     (instruction[13]));
+      //
+      LUT6_2 # (       .INIT   (64\'hFF00F0F0CCCCAAAA))
+      s6_4k_mux14_lut( .I0     (data_out_a_lh[5]),
+                       .I1     (data_out_a_hh[5]),
+                       .I2     (data_out_a_lh[6]),
+                       .I3     (data_out_a_hh[6]),
+                       .I4     (pipe_a11),
+                       .I5     (1\'b1),
+                       .O5     (instruction[14]),
+                       .O6     (instruction[15]));
+      //
+      LUT6_2 # (       .INIT   (64\'hFF00F0F0CCCCAAAA))
+      s6_4k_mux16_lut( .I0     (data_out_a_lh[7]),
+                       .I1     (data_out_a_hh[7]),
+                       .I2     (data_out_a_lh[32]),
+                       .I3     (data_out_a_hh[32]),
+                       .I4     (pipe_a11),
+                       .I5     (1\'b1),
+                       .O5     (instruction[16]),
+                       .O6     (instruction[17]));
+      //
+      if (C_JTAG_LOADER_ENABLE == 0) begin : no_loader
+        assign data_in_b_ll = {3\'b000, data_out_b_ll[32], 24\'b000000000000000000000000, data_out_b_ll[7:0]};
+        assign data_in_b_lh = {3\'b000, data_out_b_lh[32], 24\'b000000000000000000000000, data_out_b_lh[7:0]};
+        assign data_in_b_hl = {3\'b000, data_out_b_hl[32], 24\'b000000000000000000000000, data_out_b_hl[7:0]};
+        assign data_in_b_hh = {3\'b000, data_out_b_hh[32], 24\'b000000000000000000000000, data_out_b_hh[7:0]};
+        assign address_b[13:0] = 14\'b00000000000000;
+        assign we_b_l[3:0] = 4\'b0000;
+        assign we_b_h[3:0] = 4\'b0000;
+        assign enable_b = 1\'b0;
+        assign rdl = 1\'b0;
+        assign clk_b = 1\'b0;
+        assign jtag_dout = {data_out_b_h[32], data_out_b_h[7:0], data_out_b_l[32], data_out_b_l[7:0]};
+      end // no_loader;
+      //
+      if (C_JTAG_LOADER_ENABLE == 1) begin : loader
+        assign data_in_b_lh = {3\'b000, jtag_din[17], 24\'b000000000000000000000000, jtag_din[16:9]};
+        assign data_in_b_ll = {3\'b000, jtag_din[8],  24\'b000000000000000000000000, jtag_din[7:0]};
+        assign data_in_b_hh = {3\'b000, jtag_din[17], 24\'b000000000000000000000000, jtag_din[16:9]};
+        assign data_in_b_hl = {3\'b000, jtag_din[8],  24\'b000000000000000000000000, jtag_din[7:0]};
+        assign address_b[13:0] = {jtag_addr[10:0], 3\'b000};
+        //
+        LUT6_2 # (         .INIT   (64\'h8000000020000000))
+        s6_4k_jtag_we_lut( .I0     (jtag_we),
+                           .I1     (jtag_addr[11]),
+                           .I2     (1\'b1),
+                           .I3     (1\'b1),
+                           .I4     (1\'b1),
+                           .I5     (1\'b1),
+                           .O5     (jtag_we_l),
+                           .O6     (jtag_we_h));
+        //
+        assign we_b_l[3:0] = {jtag_we_l, jtag_we_l, jtag_we_l, jtag_we_l};
+        assign we_b_h[3:0] = {jtag_we_h, jtag_we_h, jtag_we_h, jtag_we_h};
+        //
+        assign enable_b = jtag_en[0];
+        assign rdl = rdl_bus[0];
+        assign clk_b = jtag_clk;
+        //
+        LUT6_2 # (            .INIT   (64\'hFF00F0F0CCCCAAAA))
+         s6_4k_jtag_mux0_lut( .I0     (data_out_b_ll[0]),
+                              .I1     (data_out_b_hl[0]),
+                              .I2     (data_out_b_ll[1]),
+                              .I3     (data_out_b_hl[1]),
+                              .I4     (jtag_addr[11]),
+                              .I5     (1\'b1),
+                              .O5     (jtag_dout[0]),
+                              .O6     (jtag_dout[1]));
+        //
+        LUT6_2 # (            .INIT   (64\'hFF00F0F0CCCCAAAA))
+         s6_4k_jtag_mux2_lut( .I0     (data_out_b_ll[2]),
+                              .I1     (data_out_b_hl[2]),
+                              .I2     (data_out_b_ll[3]),
+                              .I3     (data_out_b_hl[3]),
+                              .I4     (jtag_addr[11]),
+                              .I5     (1\'b1),
+                              .O5     (jtag_dout[2]),
+                              .O6     (jtag_dout[3]));
+        //
+        LUT6_2 # (            .INIT   (64\'hFF00F0F0CCCCAAAA))
+         s6_4k_jtag_mux4_lut( .I0     (data_out_b_ll[4]),
+                              .I1     (data_out_b_hl[4]),
+                              .I2     (data_out_b_ll[5]),
+                              .I3     (data_out_b_hl[5]),
+                              .I4     (jtag_addr[11]),
+                              .I5     (1\'b1),
+                              .O5     (jtag_dout[4]),
+                              .O6     (jtag_dout[5]));
+        //
+        LUT6_2 # (            .INIT   (64\'hFF00F0F0CCCCAAAA))
+         s6_4k_jtag_mux6_lut( .I0     (data_out_b_ll[6]),
+                              .I1     (data_out_b_hl[6]),
+                              .I2     (data_out_b_ll[7]),
+                              .I3     (data_out_b_hl[7]),
+                              .I4     (jtag_addr[11]),
+                              .I5     (1\'b1),
+                              .O5     (jtag_dout[6]),
+                              .O6     (jtag_dout[7]));
+        //
+        LUT6_2 # (            .INIT   (64\'hFF00F0F0CCCCAAAA))
+         s6_4k_jtag_mux8_lut( .I0     (data_out_b_ll[32]),
+                              .I1     (data_out_b_hl[32]),
+                              .I2     (data_out_b_lh[0]),
+                              .I3     (data_out_b_hh[0]),
+                              .I4     (jtag_addr[11]),
+                              .I5     (1\'b1),
+                              .O5     (jtag_dout[8]),
+                              .O6     (jtag_dout[9]));
+        //
+        LUT6_2 # (            .INIT   (64\'hFF00F0F0CCCCAAAA))
+        s6_4k_jtag_mux10_lut( .I0     (data_out_b_lh[1]),
+                              .I1     (data_out_b_hh[1]),
+                              .I2     (data_out_b_lh[2]),
+                              .I3     (data_out_b_hh[2]),
+                              .I4     (jtag_addr[11]),
+                              .I5     (1\'b1),
+                              .O5     (jtag_dout[10]),
+                              .O6     (jtag_dout[11]));
+        //
+        LUT6_2 # (            .INIT   (64\'hFF00F0F0CCCCAAAA))
+        s6_4k_jtag_mux12_lut( .I0     (data_out_b_lh[3]),
+                              .I1     (data_out_b_hh[3]),
+                              .I2     (data_out_b_lh[4]),
+                              .I3     (data_out_b_hh[4]),
+                              .I4     (jtag_addr[11]),
+                              .I5     (1\'b1),
+                              .O5     (jtag_dout[12]),
+                              .O6     (jtag_dout[13]));
+        //
+        LUT6_2 # (            .INIT   (64\'hFF00F0F0CCCCAAAA))
+        s6_4k_jtag_mux14_lut( .I0     (data_out_b_lh[5]),
+                              .I1     (data_out_b_hh[5]),
+                              .I2     (data_out_b_lh[6]),
+                              .I3     (data_out_b_hh[6]),
+                              .I4     (jtag_addr[11]),
+                              .I5     (1\'b1),
+                              .O5     (jtag_dout[14]),
+                              .O6     (jtag_dout[15]));
+        //
+        LUT6_2 # (            .INIT   (64\'hFF00F0F0CCCCAAAA))
+        s6_4k_jtag_mux16_lut( .I0     (data_out_b_lh[7]),
+                              .I1     (data_out_b_hh[7]),
+                              .I2     (data_out_b_lh[32]),
+                              .I3     (data_out_b_hh[32]),
+                              .I4     (jtag_addr[11]),
+                              .I5     (1\'b1),
+                              .O5     (jtag_dout[16]),
+                              .O6     (jtag_dout[17]));
+        //
+      end // loader;
+      // 
+      RAMB16BWER #(.DATA_WIDTH_A        (9),
+                   .DOA_REG             (0),
+                   .EN_RSTRAM_A         (""FALSE""),
+                   .INIT_A              (9\'b000000000),
+                   .RST_PRIORITY_A      (""CE""),
+                   .SRVAL_A             (9\'b000000000),
+                   .WRITE_MODE_A        (""WRITE_FIRST""),
+                   .DATA_WIDTH_B        (9),
+                   .DOB_REG             (0),
+                   .EN_RSTRAM_B         (""FALSE""),
+                   .INIT_B              (9\'b000000000),
+                   .RST_PRIORITY_B      (""CE""),
+                   .SRVAL_B             (9\'b000000000),
+                   .WRITE_MODE_B        (""WRITE_FIRST""),
+                   .RSTTYPE             (""SYNC""),
+                   .INIT_FILE           (""NONE""),
+                   .SIM_COLLISION_CHECK (""ALL""),
+                   .SIM_DEVICE          (""SPARTAN6""),
+                   .INIT_00             (256\'h0E7560EA53435431462048E444B1210211E00EB1C9D210C900C9FFFFFF100200),
+                   .INIT_01             (256\'h0E419C0D54385D3657355A3402111020750E419C0D54385D3657355A34021108),
+                   .INIT_02             (256\'h00110400110700110600110543600E41880D54385D3657355A34021118317560),
+                   .INIT_03             (256\'h0BCF42D9700ACF41CFF0000008CF2607CF2506CF2405CF2304CF2203CF21CFF0),
+                   .INIT_04             (256\'h22C912210EC90800C9F2C943C942C94100101A101910180000D9900CCF43D980),
+                   .INIT_05             (256\'hC92600C925C92401C923C922C921000EC9F1C91726C91625C91524C91423C913),
+                   .INIT_06             (256\'h000D0100DD030100D5010F0010D50E000000D50E01000100C9F0C943C942C941),
+                   .INIT_07             (256\'h000000000000000000000000000000000000000D020300FFFFFF0D0200C90000),
+                   .INIT_08             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_09             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0A             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0B             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0C             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0D             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0E             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0F             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_10             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_11             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_12             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_13             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_14             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_15             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_16             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_17             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_18             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_19             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1A             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1B             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1C             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1D             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1E             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1F             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_20             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_21             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_22             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_23             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_24             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_25             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_26             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_27             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_28             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_29             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2A             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2B             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2C             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2D             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2E             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2F             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_30             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_31             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_32             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_33             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_34             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_35             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_36             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_37             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_38             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_39             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3A             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3B             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3C             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3D             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3E             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3F             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_00            (256\'h00001D7260680800210212492200EE318C0924900000000000000000000004BD),
+                   .INITP_01            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_02            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_03            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_04            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_05            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_06            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_07            (256\'h0000000000000000000000000000000000000000000000000000000000000000))
+    kcpsm6_rom_ll( .ADDRA               (address_a[13:0]),
+                   .ENA                 (enable),
+                   .CLKA                (clk),
+                   .DOA                 (data_out_a_ll[31:0]),
+                   .DOPA                (data_out_a_ll[35:32]), 
+                   .DIA                 (data_in_a[31:0]),
+                   .DIPA                (data_in_a[35:32]), 
+                   .WEA                 (4\'b0000),
+                   .REGCEA              (1\'b0),
+                   .RSTA                (1\'b0),
+                   .ADDRB               (address_b[13:0]),
+                   .ENB                 (enable_b),
+                   .CLKB                (clk_b),
+                   .DOB                 (data_out_b_ll[31:0]),
+                   .DOPB                (data_out_b_ll[35:32]), 
+                   .DIB                 (data_in_b_ll[31:0]),
+                   .DIPB                (data_in_b_ll[35:32]), 
+                   .WEB                 (we_b_l[3:0]),
+                   .REGCEB              (1\'b0),
+                   .RSTB                (1\'b0));
+      // 
+      RAMB16BWER #(.DATA_WIDTH_A        (9),
+                   .DOA_REG             (0),
+                   .EN_RSTRAM_A         (""FALSE""),
+                   .INIT_A              (9\'b000000000),
+                   .RST_PRIORITY_A      (""CE""),
+                   .SRVAL_A             (9\'b000000000),
+                   .WRITE_MODE_A        (""WRITE_FIRST""),
+                   .DATA_WIDTH_B        (9),
+                   .DOB_REG             (0),
+                   .EN_RSTRAM_B         (""FALSE""),
+                   .INIT_B              (9\'b000000000),
+                   .RST_PRIORITY_B      (""CE""),
+                   .SRVAL_B             (9\'b000000000),
+                   .WRITE_MODE_B        (""WRITE_FIRST""),
+                   .RSTTYPE             (""SYNC""),
+                   .INIT_FILE           (""NONE""),
+                   .SIM_COLLISION_CHECK (""ALL""),
+                   .SIM_DEVICE          (""SPARTAN6""),
+                   .INIT_00             (256\'h10000080E980E980E980E980E980E9496B1B10000008080008000B0B0B08080D),
+                   .INIT_01             (256\'h90E980E980E980E980E980E9496B0B100090E980E980E980E980E980E9496B0B),
+                   .INIT_02             (256\'h286B8B286B8B286B8B286B8B100090E980E980E980E980E980E9496B0B100000),
+                   .INIT_03             (256\'h68000880E068000800080D286800086800086800086800086800086800080008),
+                   .INIT_04             (256\'h08004808100008080008000800080008080448044803480D2880E068000880E0),
+                   .INIT_05             (256\'h0008080008000808000800080008081000080048080048080048080048080048),
+                   .INIT_06             (256\'h0D6D2D2880ED8D28B0E9492848006A680A28006A68680A280008000800080008),
+                   .INIT_07             (256\'h000000000000000000000000000000000000286D8D1D280C0C0B6D1D28000808),
+                   .INIT_08             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_09             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0A             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0B             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0C             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0D             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0E             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0F             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_10             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_11             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_12             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_13             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_14             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_15             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_16             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_17             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_18             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_19             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1A             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1B             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1C             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1D             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1E             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1F             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_20             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_21             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_22             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_23             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_24             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_25             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_26             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_27             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_28             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_29             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2A             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2B             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2C             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2D             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2E             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2F             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_30             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_31             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_32             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_33             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_34             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_35             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_36             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_37             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_38             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_39             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3A             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3B             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3C             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3D             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3E             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3F             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_00            (256\'h0000322C59977DAA94A9A4924CAA00DAD69DB6DADB6EAA97AAA5D552F554B940),
+                   .INITP_01            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_02            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_03            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_04            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_05            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_06            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_07            (256\'h0000000000000000000000000000000000000000000000000000000000000000))
+    kcpsm6_rom_lh( .ADDRA               (address_a[13:0]),
+                   .ENA                 (enable),
+                   .CLKA                (clk),
+                   .DOA                 (data_out_a_lh[31:0]),
+                   .DOPA                (data_out_a_lh[35:32]), 
+                   .DIA                 (data_in_a[31:0]),
+                   .DIPA                (data_in_a[35:32]), 
+                   .WEA                 (4\'b0000),
+                   .REGCEA              (1\'b0),
+                   .RSTA                (1\'b0),
+                   .ADDRB               (address_b[13:0]),
+                   .ENB                 (enable_b),
+                   .CLKB                (clk_b),
+                   .DOB                 (data_out_b_lh[31:0]),
+                   .DOPB                (data_out_b_lh[35:32]), 
+                   .DIB                 (data_in_b_lh[31:0]),
+                   .DIPB                (data_in_b_lh[35:32]), 
+                   .WEB                 (we_b_l[3:0]),
+                   .REGCEB              (1\'b0),
+                   .RSTB                (1\'b0));
+      // 
+      RAMB16BWER #(.DATA_WIDTH_A        (9),
+                   .DOA_REG             (0),
+                   .EN_RSTRAM_A         (""FALSE""),
+                   .INIT_A              (9\'b000000000),
+                   .RST_PRIORITY_A      (""CE""),
+                   .SRVAL_A             (9\'b000000000),
+                   .WRITE_MODE_A        (""WRITE_FIRST""),
+                   .DATA_WIDTH_B        (9),
+                   .DOB_REG             (0),
+                   .EN_RSTRAM_B         (""FALSE""),
+                   .INIT_B              (9\'b000000000),
+                   .RST_PRIORITY_B      (""CE""),
+                   .SRVAL_B             (9\'b000000000),
+                   .WRITE_MODE_B        (""WRITE_FIRST""),
+                   .RSTTYPE             (""SYNC""),
+                   .INIT_FILE           (""NONE""),
+                   .SIM_COLLISION_CHECK (""ALL""),
+                   .SIM_DEVICE          (""SPARTAN6""),
+                   .INIT_00             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_01             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_02             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_03             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_04             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_05             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_06             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_07             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_08             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_09             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0A             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0B             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0C             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0D             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0E             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0F             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_10             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_11             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_12             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_13             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_14             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_15             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_16             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_17             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_18             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_19             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1A             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1B             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1C             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1D             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1E             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1F             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_20             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_21             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_22             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_23             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_24             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_25             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_26             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_27             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_28             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_29             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2A             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2B             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2C             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2D             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2E             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2F             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_30             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_31             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_32             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_33             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_34             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_35             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_36             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_37             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_38             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_39             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3A             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3B             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3C             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3D             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3E             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3F             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_00            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_01            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_02            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_03            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_04            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_05            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_06            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_07            (256\'h0000000000000000000000000000000000000000000000000000000000000000))
+    kcpsm6_rom_hl( .ADDRA               (address_a[13:0]),
+                   .ENA                 (enable),
+                   .CLKA                (clk),
+                   .DOA                 (data_out_a_hl[31:0]),
+                   .DOPA                (data_out_a_hl[35:32]), 
+                   .DIA                 (data_in_a[31:0]),
+                   .DIPA                (data_in_a[35:32]), 
+                   .WEA                 (4\'b0000),
+                   .REGCEA              (1\'b0),
+                   .RSTA                (1\'b0),
+                   .ADDRB               (address_b[13:0]),
+                   .ENB                 (enable_b),
+                   .CLKB                (clk_b),
+                   .DOB                 (data_out_b_hl[31:0]),
+                   .DOPB                (data_out_b_hl[35:32]), 
+                   .DIB                 (data_in_b_hl[31:0]),
+                   .DIPB                (data_in_b_hl[35:32]), 
+                   .WEB                 (we_b_h[3:0]),
+                   .REGCEB              (1\'b0),
+                   .RSTB                (1\'b0));
+      // 
+      RAMB16BWER #(.DATA_WIDTH_A        (9),
+                   .DOA_REG             (0),
+                   .EN_RSTRAM_A         (""FALSE""),
+                   .INIT_A              (9\'b000000000),
+                   .RST_PRIORITY_A      (""CE""),
+                   .SRVAL_A             (9\'b000000000),
+                   .WRITE_MODE_A        (""WRITE_FIRST""),
+                   .DATA_WIDTH_B        (9),
+                   .DOB_REG             (0),
+                   .EN_RSTRAM_B         (""FALSE""),
+                   .INIT_B              (9\'b000000000),
+                   .RST_PRIORITY_B      (""CE""),
+                   .SRVAL_B             (9\'b000000000),
+                   .WRITE_MODE_B        (""WRITE_FIRST""),
+                   .RSTTYPE             (""SYNC""),
+                   .INIT_FILE           (""NONE""),
+                   .SIM_COLLISION_CHECK (""ALL""),
+                   .SIM_DEVICE          (""SPARTAN6""),
+                   .INIT_00             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_01             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_02             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_03             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_04             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_05             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_06             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_07             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_08             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_09             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0A             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0B             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0C             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0D             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0E             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_0F             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_10             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_11             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_12             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_13             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_14             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_15             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_16             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_17             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_18             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_19             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1A             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1B             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1C             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1D             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1E             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_1F             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_20             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_21             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_22             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_23             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_24             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_25             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_26             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_27             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_28             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_29             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2A             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2B             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2C             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2D             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2E             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_2F             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_30             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_31             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_32             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_33             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_34             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_35             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_36             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_37             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_38             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_39             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3A             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3B             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3C             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3D             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3E             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INIT_3F             (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_00            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_01            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_02            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_03            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_04            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_05            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_06            (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                   .INITP_07            (256\'h0000000000000000000000000000000000000000000000000000000000000000))
+    kcpsm6_rom_hh( .ADDRA               (address_a[13:0]),
+                   .ENA                 (enable),
+                   .CLKA                (clk),
+                   .DOA                 (data_out_a_hh[31:0]),
+                   .DOPA                (data_out_a_hh[35:32]), 
+                   .DIA                 (data_in_a[31:0]),
+                   .DIPA                (data_in_a[35:32]), 
+                   .WEA                 (4\'b0000),
+                   .REGCEA              (1\'b0),
+                   .RSTA                (1\'b0),
+                   .ADDRB               (address_b[13:0]),
+                   .ENB                 (enable_b),
+                   .CLKB                (clk_b),
+                   .DOB                 (data_out_b_hh[31:0]),
+                   .DOPB                (data_out_b_hh[35:32]), 
+                   .DIB                 (data_in_b_hh[31:0]),
+                   .DIPB                (data_in_b_hh[35:32]), 
+                   .WEB                 (we_b_h[3:0]),
+                   .REGCEB              (1\'b0),
+                   .RSTB                (1\'b0));
+      //
+    end // s6;
+    //
+    //
+    if (C_FAMILY == ""V6"") begin: v6 
+      //
+      assign address_a = {1\'b1, address[11:0], 3\'b111};
+      assign instruction = {data_out_a_h[32], data_out_a_h[7:0], data_out_a_l[32], data_out_a_l[7:0]};
+      assign data_in_a = 36\'b00000000000000000000000000000000000;
+      assign jtag_dout = {data_out_b_h[32], data_out_b_h[7:0], data_out_b_l[32], data_out_b_l[7:0]};
+      //
+      if (C_JTAG_LOADER_ENABLE == 0) begin : no_loader
+        assign data_in_b_l = {3\'b000, data_out_b_l[32], 24\'b000000000000000000000000, data_out_b_l[7:0]};
+        assign data_in_b_h = {3\'b000, data_out_b_h[32], 24\'b000000000000000000000000, data_out_b_h[7:0]};
+        assign address_b = 16\'b1111111111111111;
+        assign we_b = 8\'b00000000;
+        assign enable_b = 1\'b0;
+        assign rdl = 1\'b0;
+        assign clk_b = 1\'b0;
+      end // no_loader;
+      //
+      if (C_JTAG_LOADER_ENABLE == 1) begin : loader
+        assign data_in_b_h = {3\'b000, jtag_din[17], 24\'b000000000000000000000000, jtag_din[16:9]};
+        assign data_in_b_l = {3\'b000, jtag_din[8],  24\'b000000000000000000000000, jtag_din[7:0]};
+        assign address_b = {1\'b1, jtag_addr[11:0], 3\'b111};
+        assign we_b = {jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we};
+        assign enable_b = jtag_en[0];
+        assign rdl = rdl_bus[0];
+        assign clk_b = jtag_clk;
+      end // loader;
+      // 
+      RAMB36E1 #(.READ_WIDTH_A              (9),
+                 .WRITE_WIDTH_A             (9),
+                 .DOA_REG                   (0),
+                 .INIT_A                    (36\'h000000000),
+                 .RSTREG_PRIORITY_A         (""REGCE""),
+                 .SRVAL_A                   (36\'h000000000),
+                 .WRITE_MODE_A              (""WRITE_FIRST""),
+                 .READ_WIDTH_B              (9),
+                 .WRITE_WIDTH_B             (9),
+                 .DOB_REG                   (0),
+                 .INIT_B                    (36\'h000000000),
+                 .RSTREG_PRIORITY_B         (""REGCE""),
+                 .SRVAL_B                   (36\'h000000000),
+                 .WRITE_MODE_B              (""WRITE_FIRST""),
+                 .INIT_FILE                 (""NONE""),
+                 .SIM_COLLISION_CHECK       (""ALL""),
+                 .RAM_MODE                  (""TDP""),
+                 .RDADDR_COLLISION_HWCONFIG (""DELAYED_WRITE""),
+                 .EN_ECC_READ               (""FALSE""),
+                 .EN_ECC_WRITE              (""FALSE""),
+                 .RAM_EXTENSION_A           (""NONE""),
+                 .RAM_EXTENSION_B           (""NONE""),
+                 .SIM_DEVICE                (""VIRTEX6""),
+                 .INIT_00                   (256\'h0E7560EA53435431462048E444B1210211E00EB1C9D210C900C9FFFFFF100200),
+                 .INIT_01                   (256\'h0E419C0D54385D3657355A3402111020750E419C0D54385D3657355A34021108),
+                 .INIT_02                   (256\'h00110400110700110600110543600E41880D54385D3657355A34021118317560),
+                 .INIT_03                   (256\'h0BCF42D9700ACF41CFF0000008CF2607CF2506CF2405CF2304CF2203CF21CFF0),
+                 .INIT_04                   (256\'h22C912210EC90800C9F2C943C942C94100101A101910180000D9900CCF43D980),
+                 .INIT_05                   (256\'hC92600C925C92401C923C922C921000EC9F1C91726C91625C91524C91423C913),
+                 .INIT_06                   (256\'h000D0100DD030100D5010F0010D50E000000D50E01000100C9F0C943C942C941),
+                 .INIT_07                   (256\'h000000000000000000000000000000000000000D020300FFFFFF0D0200C90000),
+                 .INIT_08                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_09                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_0A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_0B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_0C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_0D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_0E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_0F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_10                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_11                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_12                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_13                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_14                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_15                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_16                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_17                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_18                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_19                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_20                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_21                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_22                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_23                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_24                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_25                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_26                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_27                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_28                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_29                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_30                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_31                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_32                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_33                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_34                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_35                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_36                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_37                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_38                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_39                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_40                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_41                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_42                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_43                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_44                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_45                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_46                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_47                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_48                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_49                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_50                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_51                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_52                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_53                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_54                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_55                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_56                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_57                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_58                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_59                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_60                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_61                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_62                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_63                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_64                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_65                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_66                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_67                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_68                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_69                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_70                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_71                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_72                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_73                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_74                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_75                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_76                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_77                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_78                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_79                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_00                  (256\'h00001D7260680800210212492200EE318C0924900000000000000000000004BD),
+                 .INITP_01                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_02                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_03                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_04                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_05                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_06                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_07                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_08                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_09                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0A                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0B                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0C                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0D                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0E                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0F                  (256\'h0000000000000000000000000000000000000000000000000000000000000000))
+   kcpsm6_rom_l( .ADDRARDADDR               (address_a),
+                 .ENARDEN                   (enable),
+                 .CLKARDCLK                 (clk),
+                 .DOADO                     (data_out_a_l[31:0]),
+                 .DOPADOP                   (data_out_a_l[35:32]), 
+                 .DIADI                     (data_in_a[31:0]),
+                 .DIPADIP                   (data_in_a[35:32]), 
+                 .WEA                       (4\'b0000),
+                 .REGCEAREGCE               (1\'b0),
+                 .RSTRAMARSTRAM             (1\'b0),
+                 .RSTREGARSTREG             (1\'b0),
+                 .ADDRBWRADDR               (address_b),
+                 .ENBWREN                   (enable_b),
+                 .CLKBWRCLK                 (clk_b),
+                 .DOBDO                     (data_out_b_l[31:0]),
+                 .DOPBDOP                   (data_out_b_l[35:32]), 
+                 .DIBDI                     (data_in_b_l[31:0]),
+                 .DIPBDIP                   (data_in_b_l[35:32]), 
+                 .WEBWE                     (we_b),
+                 .REGCEB                    (1\'b0),
+                 .RSTRAMB                   (1\'b0),
+                 .RSTREGB                   (1\'b0),
+                 .CASCADEINA                (1\'b0),
+                 .CASCADEINB                (1\'b0),
+                 .CASCADEOUTA               (),
+                 .CASCADEOUTB               (),
+                 .DBITERR                   (),
+                 .ECCPARITY                 (),
+                 .RDADDRECC                 (),
+                 .SBITERR                   (),
+                 .INJECTDBITERR             (1\'b0),      
+                 .INJECTSBITERR             (1\'b0));   
+      //
+      RAMB36E1 #(.READ_WIDTH_A              (9),
+                 .WRITE_WIDTH_A             (9),
+                 .DOA_REG                   (0),
+                 .INIT_A                    (36\'h000000000),
+                 .RSTREG_PRIORITY_A         (""REGCE""),
+                 .SRVAL_A                   (36\'h000000000),
+                 .WRITE_MODE_A              (""WRITE_FIRST""),
+                 .READ_WIDTH_B              (9),
+                 .WRITE_WIDTH_B             (9),
+                 .DOB_REG                   (0),
+                 .INIT_B                    (36\'h000000000),
+                 .RSTREG_PRIORITY_B         (""REGCE""),
+                 .SRVAL_B                   (36\'h000000000),
+                 .WRITE_MODE_B              (""WRITE_FIRST""),
+                 .INIT_FILE                 (""NONE""),
+                 .SIM_COLLISION_CHECK       (""ALL""),
+                 .RAM_MODE                  (""TDP""),
+                 .RDADDR_COLLISION_HWCONFIG (""DELAYED_WRITE""),
+                 .EN_ECC_READ               (""FALSE""),
+                 .EN_ECC_WRITE              (""FALSE""),
+                 .RAM_EXTENSION_A           (""NONE""),
+                 .RAM_EXTENSION_B           (""NONE""),
+                 .SIM_DEVICE                (""VIRTEX6""),
+                 .INIT_00                   (256\'h10000080E980E980E980E980E980E9496B1B10000008080008000B0B0B08080D),
+                 .INIT_01                   (256\'h90E980E980E980E980E980E9496B0B100090E980E980E980E980E980E9496B0B),
+                 .INIT_02                   (256\'h286B8B286B8B286B8B286B8B100090E980E980E980E980E980E9496B0B100000),
+                 .INIT_03                   (256\'h68000880E068000800080D286800086800086800086800086800086800080008),
+                 .INIT_04                   (256\'h08004808100008080008000800080008080448044803480D2880E068000880E0),
+                 .INIT_05                   (256\'h0008080008000808000800080008081000080048080048080048080048080048),
+                 .INIT_06                   (256\'h0D6D2D2880ED8D28B0E9492848006A680A28006A68680A280008000800080008),
+                 .INIT_07                   (256\'h000000000000000000000000000000000000286D8D1D280C0C0B6D1D28000808),
+                 .INIT_08                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_09                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_0A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_0B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_0C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_0D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_0E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_0F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_10                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_11                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_12                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_13                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_14                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_15                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_16                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_17                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_18                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_19                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_20                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_21                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_22                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_23                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_24                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_25                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_26                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_27                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_28                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_29                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_30                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_31                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_32                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_33                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_34                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_35                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_36                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_37                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_38                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_39                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_40                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_41                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_42                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_43                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_44                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_45                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_46                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_47                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_48                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_49                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_50                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_51                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_52                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_53                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_54                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_55                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_56                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_57                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_58                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_59                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_60                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_61                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_62                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_63                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_64                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_65                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_66                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_67                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_68                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_69                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_70                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_71                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_72                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_73                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_74                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_75                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_76                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_77                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_78                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_79                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_00                  (256\'h0000322C59977DAA94A9A4924CAA00DAD69DB6DADB6EAA97AAA5D552F554B940),
+                 .INITP_01                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_02                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_03                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_04                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_05                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_06                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_07                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_08                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_09                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0A                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0B                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0C                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0D                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0E                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0F                  (256\'h0000000000000000000000000000000000000000000000000000000000000000))
+   kcpsm6_rom_h( .ADDRARDADDR               (address_a),
+                 .ENARDEN                   (enable),
+                 .CLKARDCLK                 (clk),
+                 .DOADO                     (data_out_a_h[31:0]),
+                 .DOPADOP                   (data_out_a_h[35:32]), 
+                 .DIADI                     (data_in_a[31:0]),
+                 .DIPADIP                   (data_in_a[35:32]), 
+                 .WEA                       (4\'b0000),
+                 .REGCEAREGCE               (1\'b0),
+                 .RSTRAMARSTRAM             (1\'b0),
+                 .RSTREGARSTREG             (1\'b0),
+                 .ADDRBWRADDR               (address_b),
+                 .ENBWREN                   (enable_b),
+                 .CLKBWRCLK                 (clk_b),
+                 .DOBDO                     (data_out_b_h[31:0]),
+                 .DOPBDOP                   (data_out_b_h[35:32]), 
+                 .DIBDI                     (data_in_b_h[31:0]),
+                 .DIPBDIP                   (data_in_b_h[35:32]), 
+                 .WEBWE                     (we_b),
+                 .REGCEB                    (1\'b0),
+                 .RSTRAMB                   (1\'b0),
+                 .RSTREGB                   (1\'b0),
+                 .CASCADEINA                (1\'b0),
+                 .CASCADEINB                (1\'b0),
+                 .CASCADEOUTA               (),
+                 .CASCADEOUTB               (),
+                 .DBITERR                   (),
+                 .ECCPARITY                 (),
+                 .RDADDRECC                 (),
+                 .SBITERR                   (),
+                 .INJECTDBITERR             (1\'b0),      
+                 .INJECTSBITERR             (1\'b0));  
+    end // v6;  
+    //
+    //
+    if (C_FAMILY == ""7S"") begin: akv7 
+      //
+      assign address_a = {1\'b1, address[11:0], 3\'b111};
+      assign instruction = {data_out_a_h[32], data_out_a_h[7:0], data_out_a_l[32], data_out_a_l[7:0]};
+      assign data_in_a = 36\'b00000000000000000000000000000000000;
+      assign jtag_dout = {data_out_b_h[32], data_out_b_h[7:0], data_out_b_l[32], data_out_b_l[7:0]};
+      //
+      if (C_JTAG_LOADER_ENABLE == 0) begin : no_loader
+        assign data_in_b_l = {3\'b000, data_out_b_l[32], 24\'b000000000000000000000000, data_out_b_l[7:0]};
+        assign data_in_b_h = {3\'b000, data_out_b_h[32], 24\'b000000000000000000000000, data_out_b_h[7:0]};
+        assign address_b = 16\'b1111111111111111;
+        assign we_b = 8\'b00000000;
+        assign enable_b = 1\'b0;
+        assign rdl = 1\'b0;
+        assign clk_b = 1\'b0;
+      end // no_loader;
+      //
+      if (C_JTAG_LOADER_ENABLE == 1) begin : loader
+        assign data_in_b_h = {3\'b000, jtag_din[17], 24\'b000000000000000000000000, jtag_din[16:9]};
+        assign data_in_b_l = {3\'b000, jtag_din[8],  24\'b000000000000000000000000, jtag_din[7:0]};
+        assign address_b = {1\'b1, jtag_addr[11:0], 3\'b111};
+        assign we_b = {jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we, jtag_we};
+        assign enable_b = jtag_en[0];
+        assign rdl = rdl_bus[0];
+        assign clk_b = jtag_clk;
+      end // loader;
+      // 
+      RAMB36E1 #(.READ_WIDTH_A              (9),
+                 .WRITE_WIDTH_A             (9),
+                 .DOA_REG                   (0),
+                 .INIT_A                    (36\'h000000000),
+                 .RSTREG_PRIORITY_A         (""REGCE""),
+                 .SRVAL_A                   (36\'h000000000),
+                 .WRITE_MODE_A              (""WRITE_FIRST""),
+                 .READ_WIDTH_B              (9),
+                 .WRITE_WIDTH_B             (9),
+                 .DOB_REG                   (0),
+                 .INIT_B                    (36\'h000000000),
+                 .RSTREG_PRIORITY_B         (""REGCE""),
+                 .SRVAL_B                   (36\'h000000000),
+                 .WRITE_MODE_B              (""WRITE_FIRST""),
+                 .INIT_FILE                 (""NONE""),
+                 .SIM_COLLISION_CHECK       (""ALL""),
+                 .RAM_MODE                  (""TDP""),
+                 .RDADDR_COLLISION_HWCONFIG (""DELAYED_WRITE""),
+                 .EN_ECC_READ               (""FALSE""),
+                 .EN_ECC_WRITE              (""FALSE""),
+                 .RAM_EXTENSION_A           (""NONE""),
+                 .RAM_EXTENSION_B           (""NONE""),
+                 .SIM_DEVICE                (""7SERIES""),
+                 .INIT_00                   (256\'h0E7560EA53435431462048E444B1210211E00EB1C9D210C900C9FFFFFF100200),
+                 .INIT_01                   (256\'h0E419C0D54385D3657355A3402111020750E419C0D54385D3657355A34021108),
+                 .INIT_02                   (256\'h00110400110700110600110543600E41880D54385D3657355A34021118317560),
+                 .INIT_03                   (256\'h0BCF42D9700ACF41CFF0000008CF2607CF2506CF2405CF2304CF2203CF21CFF0),
+                 .INIT_04                   (256\'h22C912210EC90800C9F2C943C942C94100101A101910180000D9900CCF43D980),
+                 .INIT_05                   (256\'hC92600C925C92401C923C922C921000EC9F1C91726C91625C91524C91423C913),
+                 .INIT_06                   (256\'h000D0100DD030100D5010F0010D50E000000D50E01000100C9F0C943C942C941),
+                 .INIT_07                   (256\'h000000000000000000000000000000000000000D020300FFFFFF0D0200C90000),
+                 .INIT_08                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_09                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_0A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_0B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_0C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_0D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_0E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_0F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_10                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_11                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_12                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_13                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_14                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_15                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_16                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_17                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_18                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_19                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_20                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_21                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_22                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_23                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_24                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_25                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_26                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_27                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_28                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_29                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_30                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_31                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_32                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_33                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_34                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_35                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_36                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_37                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_38                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_39                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_40                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_41                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_42                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_43                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_44                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_45                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_46                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_47                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_48                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_49                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_50                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_51                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_52                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_53                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_54                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_55                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_56                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_57                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_58                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_59                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_60                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_61                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_62                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_63                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_64                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_65                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_66                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_67                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_68                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_69                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_70                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_71                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_72                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_73                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_74                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_75                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_76                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_77                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_78                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_79                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_00                  (256\'h00001D7260680800210212492200EE318C0924900000000000000000000004BD),
+                 .INITP_01                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_02                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_03                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_04                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_05                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_06                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_07                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_08                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_09                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0A                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0B                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0C                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0D                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0E                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0F                  (256\'h0000000000000000000000000000000000000000000000000000000000000000))
+   kcpsm6_rom_l( .ADDRARDADDR               (address_a),
+                 .ENARDEN                   (enable),
+                 .CLKARDCLK                 (clk),
+                 .DOADO                     (data_out_a_l[31:0]),
+                 .DOPADOP                   (data_out_a_l[35:32]), 
+                 .DIADI                     (data_in_a[31:0]),
+                 .DIPADIP                   (data_in_a[35:32]), 
+                 .WEA                       (4\'b0000),
+                 .REGCEAREGCE               (1\'b0),
+                 .RSTRAMARSTRAM             (1\'b0),
+                 .RSTREGARSTREG             (1\'b0),
+                 .ADDRBWRADDR               (address_b),
+                 .ENBWREN                   (enable_b),
+                 .CLKBWRCLK                 (clk_b),
+                 .DOBDO                     (data_out_b_l[31:0]),
+                 .DOPBDOP                   (data_out_b_l[35:32]), 
+                 .DIBDI                     (data_in_b_l[31:0]),
+                 .DIPBDIP                   (data_in_b_l[35:32]), 
+                 .WEBWE                     (we_b),
+                 .REGCEB                    (1\'b0),
+                 .RSTRAMB                   (1\'b0),
+                 .RSTREGB                   (1\'b0),
+                 .CASCADEINA                (1\'b0),
+                 .CASCADEINB                (1\'b0),
+                 .CASCADEOUTA               (),
+                 .CASCADEOUTB               (),
+                 .DBITERR                   (),
+                 .ECCPARITY                 (),
+                 .RDADDRECC                 (),
+                 .SBITERR                   (),
+                 .INJECTDBITERR             (1\'b0),      
+                 .INJECTSBITERR             (1\'b0));   
+      //
+      RAMB36E1 #(.READ_WIDTH_A              (9),
+                 .WRITE_WIDTH_A             (9),
+                 .DOA_REG                   (0),
+                 .INIT_A                    (36\'h000000000),
+                 .RSTREG_PRIORITY_A         (""REGCE""),
+                 .SRVAL_A                   (36\'h000000000),
+                 .WRITE_MODE_A              (""WRITE_FIRST""),
+                 .READ_WIDTH_B              (9),
+                 .WRITE_WIDTH_B             (9),
+                 .DOB_REG                   (0),
+                 .INIT_B                    (36\'h000000000),
+                 .RSTREG_PRIORITY_B         (""REGCE""),
+                 .SRVAL_B                   (36\'h000000000),
+                 .WRITE_MODE_B              (""WRITE_FIRST""),
+                 .INIT_FILE                 (""NONE""),
+                 .SIM_COLLISION_CHECK       (""ALL""),
+                 .RAM_MODE                  (""TDP""),
+                 .RDADDR_COLLISION_HWCONFIG (""DELAYED_WRITE""),
+                 .EN_ECC_READ               (""FALSE""),
+                 .EN_ECC_WRITE              (""FALSE""),
+                 .RAM_EXTENSION_A           (""NONE""),
+                 .RAM_EXTENSION_B           (""NONE""),
+                 .SIM_DEVICE                (""7SERIES""),
+                 .INIT_00                   (256\'h10000080E980E980E980E980E980E9496B1B10000008080008000B0B0B08080D),
+                 .INIT_01                   (256\'h90E980E980E980E980E980E9496B0B100090E980E980E980E980E980E9496B0B),
+                 .INIT_02                   (256\'h286B8B286B8B286B8B286B8B100090E980E980E980E980E980E9496B0B100000),
+                 .INIT_03                   (256\'h68000880E068000800080D286800086800086800086800086800086800080008),
+                 .INIT_04                   (256\'h08004808100008080008000800080008080448044803480D2880E068000880E0),
+                 .INIT_05                   (256\'h0008080008000808000800080008081000080048080048080048080048080048),
+                 .INIT_06                   (256\'h0D6D2D2880ED8D28B0E9492848006A680A28006A68680A280008000800080008),
+                 .INIT_07                   (256\'h000000000000000000000000000000000000286D8D1D280C0C0B6D1D28000808),
+                 .INIT_08                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_09                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_0A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_0B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_0C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_0D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_0E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_0F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_10                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_11                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_12                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_13                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_14                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_15                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_16                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_17                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_18                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_19                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_1F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_20                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_21                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_22                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_23                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_24                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_25                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_26                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_27                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_28                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_29                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_2F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_30                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_31                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_32                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_33                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_34                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_35                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_36                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_37                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_38                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_39                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_3F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_40                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_41                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_42                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_43                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_44                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_45                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_46                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_47                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_48                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_49                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_4F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_50                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_51                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_52                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_53                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_54                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_55                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_56                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_57                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_58                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_59                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_5F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_60                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_61                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_62                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_63                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_64                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_65                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_66                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_67                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_68                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_69                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_6F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_70                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_71                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_72                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_73                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_74                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_75                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_76                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_77                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_78                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_79                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7A                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7B                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7C                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7D                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7E                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INIT_7F                   (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_00                  (256\'h0000322C59977DAA94A9A4924CAA00DAD69DB6DADB6EAA97AAA5D552F554B940),
+                 .INITP_01                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_02                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_03                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_04                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_05                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_06                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_07                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_08                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_09                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0A                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0B                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0C                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0D                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0E                  (256\'h0000000000000000000000000000000000000000000000000000000000000000),
+                 .INITP_0F                  (256\'h0000000000000000000000000000000000000000000000000000000000000000))
+   kcpsm6_rom_h( .ADDRARDADDR               (address_a),
+                 .ENARDEN                   (enable),
+                 .CLKARDCLK                 (clk),
+                 .DOADO                     (data_out_a_h[31:0]),
+                 .DOPADOP                   (data_out_a_h[35:32]), 
+                 .DIADI                     (data_in_a[31:0]),
+                 .DIPADIP                   (data_in_a[35:32]), 
+                 .WEA                       (4\'b0000),
+                 .REGCEAREGCE               (1\'b0),
+                 .RSTRAMARSTRAM             (1\'b0),
+                 .RSTREGARSTREG             (1\'b0),
+                 .ADDRBWRADDR               (address_b),
+                 .ENBWREN                   (enable_b),
+                 .CLKBWRCLK                 (clk_b),
+                 .DOBDO                     (data_out_b_h[31:0]),
+                 .DOPBDOP                   (data_out_b_h[35:32]), 
+                 .DIBDI                     (data_in_b_h[31:0]),
+                 .DIPBDIP                   (data_in_b_h[35:32]), 
+                 .WEBWE                     (we_b),
+                 .REGCEB                    (1\'b0),
+                 .RSTRAMB                   (1\'b0),
+                 .RSTREGB                   (1\'b0),
+                 .CASCADEINA                (1\'b0),
+                 .CASCADEINB                (1\'b0),
+                 .CASCADEOUTA               (),
+                 .CASCADEOUTB               (),
+                 .DBITERR                   (),
+                 .ECCPARITY                 (),
+                 .RDADDRECC                 (),
+                 .SBITERR                   (),
+                 .INJECTDBITERR             (1\'b0),      
+                 .INJECTSBITERR             (1\'b0));  
+    end // akv7;  
+    //
+  end // ram_4k_generate;
+endgenerate      
+//
+// JTAG Loader 
+//
+generate
+  if (C_JTAG_LOADER_ENABLE == 1) begin: instantiate_loader
+    jtag_loader_6  #(  .C_FAMILY              (C_FAMILY),
+                       .C_NUM_PICOBLAZE       (1),
+                       .C_JTAG_LOADER_ENABLE  (C_JTAG_LOADER_ENABLE),        
+                       .C_BRAM_MAX_ADDR_WIDTH (BRAM_ADDRESS_WIDTH),        
+                       .C_ADDR_WIDTH_0        (BRAM_ADDRESS_WIDTH))
+    jtag_loader_6_inst(.picoblaze_reset       (rdl_bus),
+                       .jtag_en               (jtag_en),
+                       .jtag_din              (jtag_din),
+                       .jtag_addr             (jtag_addr[BRAM_ADDRESS_WIDTH-1 : 0]),
+                       .jtag_clk              (jtag_clk),
+                       .jtag_we               (jtag_we),
+                       .jtag_dout_0           (jtag_dout),
+                       .jtag_dout_1           (jtag_dout),  // ports 1-7 are not used
+                       .jtag_dout_2           (jtag_dout),  // in a 1 device debug 
+                       .jtag_dout_3           (jtag_dout),  // session.  However, Synplify
+                       .jtag_dout_4           (jtag_dout),  // etc require all ports are
+                       .jtag_dout_5           (jtag_dout),  // connected
+                       .jtag_dout_6           (jtag_dout),
+                       .jtag_dout_7           (jtag_dout));  
+    
+  end //instantiate_loader
+endgenerate 
+//
+//
+endmodule
+//
+//
+//
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+// JTAG Loader 
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+//
+// JTAG Loader 6 - Version 6.00
+//
+// Kris Chaplin - 4th February 2010
+// Nick Sawyer  - 3rd March 2011 - Initial conversion to Verilog
+// Ken Chapman  - 16th August 2011 - Revised coding style
+//
+`timescale 1ps/1ps
+module jtag_loader_6 (picoblaze_reset, jtag_en, jtag_din, jtag_addr, jtag_clk, jtag_we, jtag_dout_0, jtag_dout_1, jtag_dout_2, jtag_dout_3, jtag_dout_4, jtag_dout_5, jtag_dout_6, jtag_dout_7);
+//
+parameter integer C_JTAG_LOADER_ENABLE = 1;
+parameter         C_FAMILY = ""V6"";
+parameter integer C_NUM_PICOBLAZE = 1;
+parameter integer C_BRAM_MAX_ADDR_WIDTH = 10;
+parameter integer C_PICOBLAZE_INSTRUCTION_DATA_WIDTH = 18;
+parameter integer C_JTAG_CHAIN = 2;
+parameter [4:0]   C_ADDR_WIDTH_0 = 10;
+parameter [4:0]   C_ADDR_WIDTH_1 = 10;
+parameter [4:0]   C_ADDR_WIDTH_2 = 10;
+parameter [4:0]   C_ADDR_WIDTH_3 = 10;
+parameter [4:0]   C_ADDR_WIDTH_4 = 10;
+parameter [4:0]   C_ADDR_WIDTH_5 = 10;
+parameter [4:0]   C_ADDR_WIDTH_6 = 10;
+parameter [4:0]   C_ADDR_WIDTH_7 = 10;
+//
+output [C_NUM_PICOBLAZE-1:0]                    picoblaze_reset;
+output [C_NUM_PICOBLAZE-1:0]                    jtag_en;
+output [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_din;
+output [C_BRAM_MAX_ADDR_WIDTH-1:0]              jtag_addr;
+output                                          jtag_clk ;
+output                                          jtag_we;  
+input  [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_0;
+input  [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_1;
+input  [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_2;
+input  [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_3;
+input  [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_4;
+input  [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_5;
+input  [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_6;
+input  [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_7;
+//
+//
+wire   [2:0]                                    num_picoblaze;        
+wire   [4:0]                                    picoblaze_instruction_'b'data_width; 
+//
+wire                                            drck;
+wire                                            shift_clk;
+wire                                            shift_din;
+wire                                            shift_dout;
+wire                                            shift;
+wire                                            capture;
+//
+reg                                             control_reg_ce;
+reg    [C_NUM_PICOBLAZE-1:0]                    bram_ce;
+wire   [C_NUM_PICOBLAZE-1:0]                    bus_zero;
+wire   [C_NUM_PICOBLAZE-1:0]                    jtag_en_int;
+wire   [7:0]                                    jtag_en_expanded;
+reg    [C_BRAM_MAX_ADDR_WIDTH-1:0]              jtag_addr_int;
+reg    [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_din_int;
+wire   [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] control_din;
+wire   [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] control_dout;
+reg    [7:0]                                    control_dout_int;
+wire   [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] bram_dout_int;
+reg                                             jtag_we_int;
+wire                                            jtag_clk_int;
+wire                                            bram_ce_valid;
+reg                                             din_load;
+//                                                
+wire   [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_0_masked;
+wire   [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_1_masked;
+wire   [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_2_masked;
+wire   [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_3_masked;
+wire   [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_4_masked;
+wire   [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_5_masked;
+wire   [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_6_masked;
+wire   [C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:0] jtag_dout_7_masked;
+reg    [C_NUM_PICOBLAZE-1:0]                    picoblaze_reset_int;
+//
+initial picoblaze_reset_int = 0;
+//
+genvar i;
+//
+generate
+  for (i = 0; i <= C_NUM_PICOBLAZE-1; i = i+1)
+    begin : npzero_loop
+      assign bus_zero[i] = 1\'b0;
+    end
+endgenerate
+//
+generate
+  //
+  if (C_JTAG_LOADER_ENABLE == 1)
+    begin : jtag_loader_gen
+      //
+      // Insert BSCAN primitive for target device architecture.
+      //
+      if (C_FAMILY == ""S6"")
+        begin : BSCAN_SPARTAN6_gen
+          BSCAN_SPARTAN6 # (.JTAG_CHAIN (C_JTAG_CHAIN))
+          BSCAN_BLOCK_inst (.CAPTURE    (capture),
+                            .DRCK       (drck),
+                            .RESET      (),
+                            .RUNTEST    (),
+                            .SEL        (bram_ce_valid),
+                            .SHIFT      (shift),
+                            .TCK        (),
+                            .TDI        (shift_din),
+                            .TMS        (),
+                            .UPDATE     (jtag_clk_int),
+                            .TDO        (shift_dout)); 
+            
+        end 
+      //
+      if (C_FAMILY == ""V6"")
+        begin : BSCAN_VIRTEX6_gen
+          BSCAN_VIRTEX6 # ( .JTAG_CHAIN   (C_JTAG_CHAIN),
+                            .DISABLE_JTAG (""FALSE""))
+          BSCAN_BLOCK_inst (.CAPTURE      (capture),
+                            .DRCK         (drck),
+                            .RESET        (),
+                            .RUNTEST      (),
+                            .SEL          (bram_ce_valid),
+                            .SHIFT        (shift),
+                            .TCK          (),
+                            .TDI          (shift_din),
+                            .TMS          (),
+                            .UPDATE       (jtag_clk_int),
+                            .TDO          (shift_dout));
+        end 
+      //
+      if (C_FAMILY == ""7S"")
+        begin : BSCAN_7SERIES_gen
+          BSCANE2 # (       .JTAG_CHAIN   (C_JTAG_CHAIN),
+                            .DISABLE_JTAG (""FALSE""))
+          BSCAN_BLOCK_inst (.CAPTURE      (capture),
+                            .DRCK         (drck),
+                            .RESET        (),
+                            .RUNTEST      (),
+                            .SEL          (bram_ce_valid),
+                            .SHIFT        (shift),
+                            .TCK          (),
+                            .TDI          (shift_din),
+                            .TMS          (),
+                            .UPDATE       (jtag_clk_int),
+                            .TDO          (shift_dout));
+        end 
+      //
+      // Insert clock buffer to ensure reliable shift operations.
+      //
+      BUFG upload_clock (.I (drck), .O (shift_clk));
+      //        
+      //
+      // Shift Register 
+      //
+      always @ (posedge shift_clk) begin
+        if (shift == 1\'b1) begin
+          control_reg_ce <= shift_din;
+        end
+      end
+      // 
+      always @ (posedge shift_clk) begin
+        if (shift == 1\'b1) begin
+          bram_ce[0] <= control_reg_ce;
+        end
+      end 
+      //
+      for (i = 0; i <= C_NUM_PICOBLAZE-2; i = i+1)
+      begin : loop0 
+        if (C_NUM_PICOBLAZE > 1) begin
+          always @ (posedge shift_clk) begin
+            if (shift == 1\'b1) begin
+              bram_ce[i+1] <= bram_ce[i];
+            end
+          end
+        end 
+      end
+      // 
+      always @ (posedge shift_clk) begin
+        if (shift == 1\'b1) begin
+          jtag_we_int <= bram_ce[C_NUM_PICOBLAZE-1];
+        end
+      end
+      // 
+      always @ (posedge shift_clk) begin 
+        if (shift == 1\'b1) begin
+          jtag_addr_int[0] <= jtag_we_int;
+        end
+      end
+      //
+      for (i = 0; i <= C_BRAM_MAX_ADDR_WIDTH-2; i = i+1)
+      begin : loop1
+        always @ (posedge shift_clk) begin
+          if (shift == 1\'b1) begin
+            jtag_addr_int[i+1] <= jtag_addr_int[i];
+          end
+        end 
+      end
+      // 
+      always @ (posedge shift_clk) begin 
+        if (din_load == 1\'b1) begin
+          jtag_din_int[0] <= bram_dout_int[0];
+        end
+        else if (shift == 1\'b1) begin
+          jtag_din_int[0] <= jtag_addr_int[C_BRAM_MAX_ADDR_WIDTH-1];
+        end
+      end       
+      //
+      for (i = 0; i <= C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-2; i = i+1)
+      begin : loop2
+        always @ (posedge shift_clk) begin
+          if (din_load == 1\'b1) begin
+            jtag_din_int[i+1] <= bram_dout_int[i+1];
+          end
+          if (shift == 1\'b1) begin
+            jtag_din_int[i+1] <= jtag_din_int[i];
+          end
+        end 
+      end
+      //
+      assign shift_dout = jtag_din_int[C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1];
+      //
+      //
+      always @ (bram_ce or din_load or capture or bus_zero or control_reg_ce) begin
+        if ( bram_ce == bus_zero ) begin
+          din_load <= capture & control_reg_ce;
+        end else begin
+          din_load <= capture;
+        end
+      end
+      //
+      //
+      // Control Registers 
+      //
+      assign num_picoblaze = C_NUM_PICOBLAZE-3\'h1;
+      assign picoblaze_instruction_data_width = C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-5\'h01;
+      //
+      always @ (posedge jtag_clk_int) begin
+        if (bram_ce_valid == 1\'b1 && jtag_we_int == 1\'b0 && control_reg_ce == 1\'b1) begin
+          case (jtag_addr_int[3:0]) 
+            0 : // 0 = version - returns (7:4) illustrating number of PB
+                // and [3:0] picoblaze instruction data width
+                control_dout_int <= {num_picoblaze, picoblaze_instruction_data_width};
+            1 : // 1 = PicoBlaze 0 reset / status
+                if (C_NUM_PICOBLAZE >= 1) begin 
+                  control_dout_int <= {picoblaze_reset_int[0], 2\'b00, C_ADDR_WIDTH_0-5\'h01};
+                end else begin
+                  control_dout_int <= 8\'h00;
+                end
+            2 : // 2 = PicoBlaze 1 reset / status
+                if (C_NUM_PICOBLAZE >= 2) begin 
+                  control_dout_int <= {picoblaze_reset_int[1], 2\'b00, C_ADDR_WIDTH_1-5\'h01};
+                end else begin
+                  control_dout_int <= 8\'h00;
+                end
+            3 : // 3 = PicoBlaze 2 reset / status
+                if (C_NUM_PICOBLAZE >= 3) begin 
+                  control_dout_int <= {picoblaze_reset_int[2], 2\'b00, C_ADDR_WIDTH_2-5\'h01};
+                end else begin
+                  control_dout_int <= 8\'h00;
+                end
+            4 : // 4 = PicoBlaze 3 reset / status
+                if (C_NUM_PICOBLAZE >= 4) begin 
+                  control_dout_int <= {picoblaze_reset_int[3], 2\'b00, C_ADDR_WIDTH_3-5\'h01};
+                end else begin
+                  control_dout_int <= 8\'h00;
+                end
+            5:  // 5 = PicoBlaze 4 reset / status
+                if (C_NUM_PICOBLAZE >= 5) begin 
+                  control_dout_int <= {picoblaze_reset_int[4], 2\'b00, C_ADDR_WIDTH_4-5\'h01};
+                end else begin
+                  control_dout_int <= 8\'h00;
+                end
+            6 : // 6 = PicoBlaze 5 reset / status
+                if (C_NUM_PICOBLAZE >= 6) begin 
+                  control_dout_int <= {picoblaze_reset_int[5], 2\'b00, C_ADDR_WIDTH_5-5\'h01};
+                end else begin
+                  control_dout_int <= 8\'h00;
+                end
+            7 : // 7 = PicoBlaze 6 reset / status
+                if (C_NUM_PICOBLAZE >= 7) begin 
+                  control_dout_int <= {picoblaze_reset_int[6], 2\'b00, C_ADDR_WIDTH_6-5\'h01};
+                end else begin
+                  control_dout_int <= 8\'h00;
+                end
+            8 : // 8 = PicoBlaze 7 reset / status
+                if (C_NUM_PICOBLAZE >= 8) begin 
+                  control_dout_int <= {picoblaze_reset_int[7], 2\'b00, C_ADDR_WIDTH_7-5\'h01};
+                end else begin
+                  control_dout_int <= 8\'h00;
+                end
+            15 : control_dout_int <= C_BRAM_MAX_ADDR_WIDTH -1;
+            default : control_dout_int <= 8\'h00;
+            //
+          endcase
+        end else begin
+          control_dout_int <= 8\'h00;
+        end
+      end 
+      //
+      assign control_dout[C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1:C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-8] = control_dout_int;
+      //
+      always @ (posedge jtag_clk_int) begin
+        if (bram_ce_valid == 1\'b1 && jtag_we_int == 1\'b1 && control_reg_ce == 1\'b1) begin
+          picoblaze_reset_int[C_NUM_PICOBLAZE-1:0] <= control_din[C_NUM_PICOBLAZE-1:0];
+        end
+      end     
+      //
+      //
+      // Assignments 
+      //
+      if (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH > 8) begin
+        assign control_dout[C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-9:0] = 10\'h000;
+      end
+      //
+      // Qualify the blockram CS signal with bscan select output
+      assign jtag_en_int = (bram_ce_valid) ? bram_ce : bus_zero;
+      //
+      assign jtag_en_expanded[C_NUM_PICOBLAZE-1:0] = jtag_en_int; 
+      //
+      for (i = 7; i >= C_NUM_PICOBLAZE; i = i-1)
+        begin : loop4 
+          if (C_NUM_PICOBLAZE < 8) begin : jtag_en_expanded_gen
+            assign jtag_en_expanded[i] = 1\'b0;
+          end
+        end
+      //
+      assign bram_dout_int = control_dout | jtag_dout_0_masked | jtag_dout_1_masked | jtag_dout_2_masked | jtag_dout_3_masked | jtag_dout_4_masked | jtag_dout_5_masked | jtag_dout_6_masked | jtag_dout_7_masked;
+      //
+      assign control_din = jtag_din_int;
+      //
+      assign jtag_dout_0_masked = (jtag_en_expanded[0]) ? jtag_dout_0 : 18\'h00000;
+      assign jtag_dout_1_masked = (jtag_en_expanded[1]) ? jtag_dout_1 : 18\'h00000;
+      assign jtag_dout_2_masked = (jtag_en_expanded[2]) ? jtag_dout_2 : 18\'h00000;
+      assign jtag_dout_3_masked = (jtag_en_expanded[3]) ? jtag_dout_3 : 18\'h00000;
+      assign jtag_dout_4_masked = (jtag_en_expanded[4]) ? jtag_dout_4 : 18\'h00000;
+      assign jtag_dout_5_masked = (jtag_en_expanded[5]) ? jtag_dout_5 : 18\'h00000;
+      assign jtag_dout_6_masked = (jtag_en_expanded[6]) ? jtag_dout_6 : 18\'h00000;
+      assign jtag_dout_7_masked = (jtag_en_expanded[7]) ? jtag_dout_7 : 18\'h00000;
+      //       
+      assign jtag_en = jtag_en_int;
+      assign jtag_din = jtag_din_int;
+      assign jtag_addr = jtag_addr_int;
+      assign jtag_clk = jtag_clk_int;
+      assign jtag_we = jtag_we_int;
+      assign picoblaze_reset = picoblaze_reset_int;
+      //
+    end
+endgenerate
+   //
+endmodule
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+//  END OF FILE ROM_programa.v
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    15:31:09 05/12/2016 
+// Design Name: 
+// Module Name:    controlador_teclado_ps2 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module controlador_teclado_ps2
+(
+input wire clk, reset,
+input wire ps2data, ps2clk,
+input wire [7:0] port_id,
+input wire read_strobe,
+output wire [7:0] ascii_code
+);
+
+//Declaraci\xf3n de se\xf1ales de conexi\xf3n
+wire [10:0] dout;
+wire rx_done_tick;
+wire gotten_code_flag;
+wire [7:0] key_code;
+reg [7:0] key_code_reg, key_code_next;
+
+//Para la m\xe1quina de estados del registro de la tecla
+reg [1:0] state_current, state_next;
+
+localparam [1:0] hold_key_code = 2'b0, read_key_code = 2'b01, reset_key_code = 2'b10;
+
+receptor_teclado_ps2 instancia_receptor_teclado_ps2   
+(
+.clk(clk),
+.reset(reset),
+.ps2data(ps2data),
+.ps2clk(ps2clk),
+.rx_en(1'b1),
+.rx_done_tick(rx_done_tick),
+.dout(dout)
+);
+
+identificador_teclas instancia_identificador_teclas
+(
+.clk(clk),
+.reset(reset),
+.rx_done_tick(rx_done_tick),
+.dout(dout[8:1]),//Utilizar solo los bits que realmente contienen el c\xf3digo de la tecla [8:1]
+.gotten_code_flag(gotten_code_flag) //Bandera para actualizar el FIFO
+);
+
+keycode_to_ascii instancia_keycode_to_ascii
+(
+.key_code(key_code),
+.ascii_code(ascii_code)
+);
+
+//===================================================
+// Registro para conservar la \xfaltima tecla presionada
+//===================================================
+//Secuencial
+always@(posedge clk)
+begin
+\tif(reset) begin
+\t\tkey_code_reg <= 8'b0;
+\t\tstate_current <= hold_key_code;
+\tend
+\telse begin
+\t\tkey_code_reg <= key_code_next;
+\t\tstate_current <= state_next;
+\tend
+end
+//L\xf3gica de estado siguiente
+always@*
+\tbegin
+\t\tcase(state_current)
+\t\t\thold_key_code://Hold
+\t\t\tbegin
+\t\t\tkey_code_next = key_code_reg;
+\t\t\t\tif(gotten_code_flag) state_next = read_key_code;
+\t\t\t\telse state_next = state_current;
+\t\t\tend
+\t\t\t
+\t\t\tread_key_code://Escribe registro/Espera lectura del micro
+\t\t\tbegin\t
+\t\t\tkey_code_next = dout[8:1]; //Utilizar solo los bits que realmente contienen el c\xf3digo de la tecla
+\t\t\t\tif(port_id == 8'h02 && read_strobe == 1) state_next = reset_key_code;
+\t\t\t\telse state_next = state_current;
+\t\t\tend
+\t\t\treset_key_code:
+\t\t\tbegin
+\t\t\tkey_code_next = 8'b0;
+\t\t\t\tstate_next = hold_key_code;
+\t\t\tend
+\t\t\tdefault:
+\t\t\tbegin
+\t\t\t\tkey_code_next = key_code_reg;
+\t\t\t\tstate_next = state_current;
+\t\t\tend
+\t\tendcase
+\tend
+assign key_code = key_code_reg;
+endmodule
+
+/*//===================================================
+// Registro para conservar la \xfaltima tecla presionada
+//===================================================
+
+//Secuencial
+always@(posedge clk)
+\tbegin
+\t\tif(reset)
+\t\t\tkey_code_reg <= 8'b0;
+\t\telse
+\t\t\tkey_code_reg <= key_code_next;
+\tend
+//L\xf3gica de estado siguiente
+always@*
+\tbegin
+\t\tcase(gotten_code_flag)
+\t\t\t1'b0://Hold
+\t\t\t\tkey_code_next = key_code_reg;
+\t\t\t1'b1://Escribe
+\t\t\t\tkey_code_next = dout[8:1]; //Utilizar solo los bits que realmente contienen el c\xf3digo de la tecla
+\t\tendcase
+\tend
+assign key_code = key_code_reg;
+endmodule
+*/"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: Jafet Chaves Barrantes
+// 
+// Create Date:    22:16:58 05/10/2016 
+// Design Name: 
+// Module Name:    receptor_teclado_ps2 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module receptor_teclado_ps2   
+(
+input wire clk, reset,
+input wire ps2data, ps2clk, rx_en,
+output reg rx_done_tick,
+output wire [10:0] dout
+);
+
+// Declaraci\xf3n simb\xf3lica de estados
+localparam [1:0]
+\tidle = 2'b00,
+\tdps  = 2'b01,
+\tload = 2'b10;
+
+// Declaraci\xf3n de se\xf1ales
+reg [1:0] state_reg, state_next;
+reg [7:0] filter_reg;
+wire [7:0] filter_next;
+reg f_ps2clk_reg;
+wire f_ps2clk_next;
+reg [3:0] n_reg, n_next;//Contador auxiliar para manejar el n\xfamero de bits ensamblados
+reg [10:0] assembled_data_reg, assembled_data_next; //Buffer para guardar el dato
+wire fall_edge;
+
+//======================================================
+// Filtrado y detecci\xf3n del flanco negativo de ps2_clk
+//======================================================
+always @(posedge clk, posedge reset)
+if (reset)
+\tbegin
+\t\tfilter_reg <= 0;
+\t\tf_ps2clk_reg <= 0;
+\tend
+else
+\tbegin
+\t\tfilter_reg <= filter_next;
+\t\tf_ps2clk_reg <= f_ps2clk_next;
+\tend
+
+assign filter_next = {ps2clk, filter_reg[7:1]};
+assign f_ps2clk_next = (filter_reg==8'b11111111) ? 1'b1 :
+\t\t\t\t\t\t\t(filter_reg==8'b00000000) ? 1'b0 :
+\t\t\t\t\t\t\t f_ps2clk_reg;
+assign fall_edge = f_ps2clk_reg & ~f_ps2clk_next;//Detecci\xf3n del flanco negativo del clk del teclado
+
+//=================================================
+// FSMD
+//=================================================
+// Estado FSMD y registros de datos
+always @(posedge clk, posedge reset)
+\tif (reset)
+\t\tbegin
+\t\t\tstate_reg <= idle;
+\t\t\tn_reg <= 0;
+\t\t\tassembled_data_reg <= 0;
+\t\tend
+\telse
+\t\tbegin
+\t\t\tstate_reg <= state_next;
+\t\t\tn_reg <= n_next;
+\t\t\tassembled_data_reg <= assembled_data_next;
+\t\tend
+// L\xf3gica de siguiente estado de la FSMD
+always @*
+begin
+\tstate_next = state_reg;
+\trx_done_tick = 1'b0;
+\tn_next = n_reg;
+\tassembled_data_next = assembled_data_reg;
+\tcase (state_reg)
+\t\tidle:
+\t\t\tif (fall_edge & rx_en)
+\t\t\t\tbegin
+\t\t\t\t\t// shift al bit entrante
+\t\t\t\t\tassembled_data_next = {ps2data, assembled_data_reg[10:1]};
+\t\t\t\t\tn_next = 4'b1001;
+\t\t\t\t\tstate_next = dps;
+\t\t\t\tend
+\t\tdps: //Ensamblar 8 bits de datos + 1 paridad + 1 parada
+\t\t\tif (fall_edge)
+\t\t\t\tbegin
+\t\t\t\t\tassembled_data_next = {ps2data, assembled_data_reg[10:1]};
+\t\t\t\t\tif (n_reg==0)
+\t\t\t\t\t\tstate_next = load;
+\t\t\t\t\telse
+\t\t\t\t\t\tn_next = n_reg - 1'b1;
+\t\t\t\tend
+\t\tload: // Ciclo de reloj extra para terminar el ensamblaje del dato del teclado
+\t\t\tbegin
+\t\t\t\tstate_next = idle;
+\t\t\t\trx_done_tick = 1'b1;
+\t\t\tend
+\tendcase
+end
+// Salida
+assign dout = assembled_data_reg[10:0]; // bits de datos (se incluyen bit de inicio, paridad y parada)
+//Nota: Bits del c\xf3digo de la teclado [8:1]
+endmodule
+"
+"//
+///////////////////////////////////////////////////////////////////////////////////////////
+// Copyright \xa9 2010-2014, Xilinx, Inc.
+// This file contains confidential and proprietary information of Xilinx, Inc. and is
+// protected under U.S. and international copyright and other intellectual property laws.
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+// Disclaimer:
+// This disclaimer is not a license and does not grant any rights to the materials
+// distributed herewith. Except as otherwise provided in a valid license issued to
+// you by Xilinx, and to the maximum extent permitted by applicable law: [1] THESE
+// MATERIALS ARE MADE AVAILABLE ""AS IS"" AND WITH ALL FAULTS, AND XILINX HEREBY
+// DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
+// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
+// OR FITNESS FOR ANY PARTICULAR PURPOSE; and [2] Xilinx shall not be liable
+// (whether in contract or tort, including negligence, or under any other theory
+// of liability) for any loss or damage of any kind or nature related to, arising
+// under or in connection with these materials, including for any direct, or any
+// indirect, special, incidental, or consequential loss or damage (including loss
+// of data, profits, goodwill, or any type of loss or damage suffered as a result
+// of any action brought by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-safe, or for use in any
+// application requiring fail-safe performance, such as life-support or safety
+// devices or systems, Class III medical devices, nuclear facilities, applications
+// related to the deployment of airbags, or any other applications that could lead
+// to death, personal injury, or severe property or environmental damage
+// (individually and collectively, ""Critical Applications)). Customer assumes the
+// sole risk and liability of any use of Xilinx products in Critical Applications,
+// subject only to applicable laws and regulations governing limitations on product
+// liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+// KCPSM6 - PicoBlaze for Spartan-6 and Virtex-6 devices.
+//
+// Version 1.1 - 4th March 2010. 
+//               Derived from kcpsm6.vhd Version 1.1 (9th February 2011) by Nick Sawyer.
+// Version 1.2 - 4th October 2012. 
+//               Addition of WebTalk information.
+// Version 1.3 - 21st May 2014. 
+//               Disassembly of \'STAR sX, kk\' instruction added to the simulation
+//               code. No changes to functionality or the physical implementation.
+//
+// Ken Chapman
+// Xilinx Ltd
+// Benchmark House
+// 203 Brooklands Road
+// Weybridge
+// Surrey KT13 ORH
+// United Kingdom
+//
+// chapman@xilinx.com
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+// Format of this file.
+//
+// The module defines the implementation of the logic using Xilinx primitives.
+// These ensure predictable synthesis results and maximise the density of the implementation. 
+// The Unisim Library is used to define Xilinx primitives. It is also used during
+// simulation. The source can be viewed at %XILINX%\\vhdl\\src\\unisims\\unisim_VCOMP.vhd
+// 
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+`timescale 1ps/1ps
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+// Main Entity for kcpsm6 with WebTalk Attributes
+//
+(* CORE_GENERATION_INFO = ""kcpsm6,kcpsm6_v1_3,{component_name=kcpsm6}"" *)
+module kcpsm6 (address, instruction, bram_enable, in_port, out_port, port_id, write_strobe, k_write_strobe, read_strobe, interrupt, interrupt_ack, sleep, reset, clk) ;
+
+parameter [7:0] \thwbuild = 8\'h00 ;
+parameter [11:0] \tinterrupt_vector = 12\'h3FF ;
+parameter integer scratch_pad_memory_size = 64 ;   
+
+output [11:0]\taddress ;
+input\t [17:0]    \tinstruction ;
+output\t\tbram_enable ;
+input\t [7:0]\tin_port ;
+output [7:0]\tout_port ;
+output [7:0]\tport_id ;
+output\t\twrite_strobe ;
+output\t\tk_write_strobe ;
+output\t\tread_strobe ;
+input\t\t\tinterrupt ;
+output\t\tinterrupt_ack ;
+input\t\t\tsleep ;
+input\t\t\treset ;
+input\t\t\tclk ;
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+// Start of Main Architecture for kcpsm6
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+// Signals used in kcpsm6
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+// State Machine and Interrupt
+//\t 
+wire\t[2:1]\t\tt_state_value ;
+wire\t[2:1]\t\tt_state ;
+wire \t\t\trun_value ;
+wire              run ;
+wire  \t\tinternal_reset_value ;
+wire \t\t\tinternal_reset ;
+wire \t\t\tsync_sleep ;
+wire \t\t\tint_enable_type ;
+wire \t\t\tinterrupt_enable_value ;
+wire\t\t\tinterrupt_enable ;
+wire\t\t\tsync_interrupt ;
+wire \t\t\tactive_interrupt_value ;
+wire \t\t\tactive_interrupt ;
+//
+// Arithmetic and Logical Functions
+//\t 
+wire\t[2:0]\t\tarith_logical_sel ;
+wire\t\t\tarith_carry_in ;
+wire\t\t\tarith_carry_value ;
+wire\t\t\tarith_carry ;
+wire \t[7:0]\t\thalf_arith_logical ;
+wire \t[7:0]\t\tlogical_carry_mask ;
+wire \t[7:0]\t\tcarry_arith_logical ;
+wire \t[7:0]\t\tarith_logical_value ;
+wire \t[7:0]\t\tarith_logical_result ;
+//
+// Shift and Rotate Functions
+//\t 
+wire \t[7:0]\t\tshift_rotate_value ;
+wire \t[7:0]\t\tshift_rotate_result ;
+wire\t\t\tshift_in_bit ;
+//
+// ALU structure
+//\t 
+wire \t[7:0]\t\talu_result ;
+wire \t[1:0]\t\talu_mux_sel_value ;
+wire \t[1:0]\t\talu_mux_sel ;
+//
+// Strobes
+//\t
+wire\t\t\tstrobe_type ;
+wire \t\t\twrite_strobe_value ;
+wire \t\t\tk_write_strobe_value ;
+wire\t\t\tread_strobe_value ;
+//
+// Flags
+//\t
+wire\t\t\tflag_enable_type ;
+wire\t\t\tflag_enable_value ;
+wire\t\t\tflag_enable ; 
+wire\t\t\tlower_parity ;
+wire\t\t\tlower_parity_sel ;
+wire\t\t\tcarry_lower_parity ;
+wire \t\t\tupper_parity ;
+wire\t\t\tparity ;
+wire\t\t\tshift_carry_value ;
+wire\t\t\tshift_carry ;
+wire\t\t\tcarry_flag_value ;
+wire\t\t\tcarry_flag ;
+
+wire \t\t\tuse_zero_flag_value ;
+wire\t\t\tuse_zero_flag ;
+wire \t\t\tdrive_carry_in_zero ;
+wire          \tcarry_in_zero ;
+wire             \tlower_zero ;
+wire         \tlower_zero_sel ;
+wire       \t\tcarry_lower_zero ;
+wire           \tmiddle_zero ;
+wire        \tmiddle_zero_sel ;
+wire      \t\tcarry_middle_zero ;
+wire         \tupper_zero_sel ;
+wire        \tzero_flag_value ;
+wire              zero_flag ;
+//
+// Scratch Pad Memory
+//\t 
+wire       \t\tspm_enable_value ;
+wire             \tspm_enable ;
+wire \t[7:0]\t\tspm_ram_data ;
+wire \t[7:0]\t\tspm_data  ;
+//
+// Registers
+//\t 
+wire           \tregbank_type ;
+wire             \tbank_value ;
+wire              bank ;
+wire          \tloadstar_type ;
+wire         \tsx_addr4_value ;
+wire   \t\tregister_enable_type ;
+wire  \t\tregister_enable_value ;
+wire        \tregister_enable ;
+wire \t[4:0]\t\tsx_addr ;
+wire \t[4:0]\t\tsy_addr ;
+wire \t[7:0]\t\tsx ;
+wire \t[7:0]\t\tsy ;
+//
+// Second Operand 
+//\t 
+wire \t[7:0]\t\tsy_or_kk ;
+//
+// Program Counter 
+//\t 
+wire       \t\tpc_move_is_valid ;
+wire              move_type ;
+wire           \treturni_type ;
+wire \t[2:0]\t\tpc_mode ;
+wire \t[11:0]\tregister_vector ;
+wire \t[11:0]\thalf_pc ;
+wire \t[10:0]\tcarry_pc ;
+wire \t[11:0]\tpc_value ;
+wire \t[11:0]\tpc ;
+wire \t[11:0]\tpc_vector ;
+//
+// Program Counter Stack 
+//\t 
+wire             \tpush_stack ;
+wire              pop_stack ;
+wire \t[11:0]\tstack_memory ;
+wire \t[11:0]\treturn_vector ;
+wire       \t\tstack_carry_flag ;
+wire      \t\tshadow_carry_flag ;
+wire        \tstack_zero_flag ;
+wire      \t\tshadow_zero_value ;
+wire       \t\tshadow_zero_flag ;
+wire             \tstack_bank ;
+wire            \tshadow_bank ;
+wire              stack_bit ;
+wire            \tspecial_bit ;
+wire \t[4:0]\t\thalf_pointer_value ;
+wire \t[4:0]\t\tfeed_pointer_value ;
+wire \t[4:0]\t\tstack_pointer_carry ;
+wire \t[4:0]\t\tstack_pointer_value ;
+wire \t[4:0]\t\tstack_pointer ;
+//
+//
+//
+//**********************************************************************************
+//
+// Signals between these *** lines are only made visible during simulation 
+//
+//synthesis translate_off
+//
+reg\t[1:152]\tkcpsm6_opcode ;
+reg\t[1:128]\tkcpsm6_status ;
+reg\t[7:0]\t      sim_s0 ;
+reg\t[7:0]\t      sim_s1 ;
+reg\t[7:0]\t      sim_s2 ;
+reg\t[7:0]\t      sim_s3 ;
+reg\t[7:0]\t      sim_s4 ;
+reg\t[7:0]\t      sim_s5 ;
+reg\t[7:0]\t      sim_s6 ;
+reg\t[7:0]\t      sim_s7 ;
+reg\t[7:0]\t      sim_s8 ;
+reg\t[7:0]\t      sim_s9 ;
+reg\t[7:0]\t      sim_sA ;
+reg\t[7:0]\t      sim_sB ;
+reg\t[7:0]\t      sim_sC ;
+reg\t[7:0]\t      sim_sD ;
+reg\t[7:0]\t      sim_sE ;
+reg\t[7:0]\t      sim_sF ;
+reg\t[7:0]\t     \tsim_spm00 ;
+reg\t[7:0]\t\tsim_spm01 ;
+reg\t[7:0]\t\tsim_spm02 ;
+reg\t[7:0]\t\tsim_spm03 ;
+reg\t[7:0]\t\tsim_spm04 ;
+reg\t[7:0]\t\tsim_spm05 ;
+reg\t[7:0]\t\tsim_spm06 ;
+reg\t[7:0]\t\tsim_spm07 ;
+reg\t[7:0]\t\tsim_spm08 ;
+reg\t[7:0]\t\tsim_spm09 ;
+reg\t[7:0]\t\tsim_spm0A ;
+reg\t[7:0]\t\tsim_spm0B ;
+reg\t[7:0]\t\tsim_spm0C ;
+reg\t[7:0]\t\tsim_spm0D ;
+reg\t[7:0]\t\tsim_spm0E ;
+reg\t[7:0]\t\tsim_spm0F ;
+reg\t[7:0]\t\tsim_spm10 ;
+reg\t[7:0]\t\tsim_spm11 ;
+reg\t[7:0]\t\tsim_spm12 ;
+reg\t[7:0]\t\tsim_spm13 ;
+reg\t[7:0]\t\tsim_spm14 ;
+reg\t[7:0]\t\tsim_spm15 ;
+reg\t[7:0]\t\tsim_spm16 ;
+reg\t[7:0]\t\tsim_spm17 ;
+reg\t[7:0]\t\tsim_spm18 ;
+reg\t[7:0]\t\tsim_spm19 ;
+reg\t[7:0]\t\tsim_spm1A ;
+reg\t[7:0]\t\tsim_spm1B ;
+reg\t[7:0]\t\tsim_spm1C ;
+reg\t[7:0]\t\tsim_spm1D ;
+reg\t[7:0]\t\tsim_spm1E ;
+reg\t[7:0]\t\tsim_spm1F ;
+reg\t[7:0]\t\tsim_spm20 ;
+reg\t[7:0]\t\tsim_spm21 ;
+reg\t[7:0]\t\tsim_spm22 ;
+reg\t[7:0]\t\tsim_spm23 ;
+reg\t[7:0]\t\tsim_spm24 ;
+reg\t[7:0]\t\tsim_spm25 ;
+reg\t[7:0]\t\tsim_spm26 ;
+reg\t[7:0]\t\tsim_spm27 ;
+reg\t[7:0]\t\tsim_spm28 ;
+reg\t[7:0]\t\tsim_spm29 ;
+reg\t[7:0]\t\tsim_spm2A ;
+reg\t[7:0]\t\tsim_spm2B ;
+reg\t[7:0]\t\tsim_spm2C ;
+reg\t[7:0]\t\tsim_spm2D ;
+reg\t[7:0]\t\tsim_spm2E ;
+reg\t[7:0]\t\tsim_spm2F ;
+reg\t[7:0]\t\tsim_spm30 ;
+reg\t[7:0]\t\tsim_spm31 ;
+reg\t[7:0]\t\tsim_spm32 ;
+reg\t[7:0]\t\tsim_spm33 ;
+reg\t[7:0]\t\tsim_spm34 ;
+reg\t[7:0]\t\tsim_spm35 ;
+reg\t[7:0]\t\tsim_spm36 ;
+reg\t[7:0]\t\tsim_spm37 ;
+reg\t[7:0]\t\tsim_spm38 ;
+reg\t[7:0]\t\tsim_spm39 ;
+reg\t[7:0]\t\tsim_spm3A ;
+reg\t[7:0]\t\tsim_spm3B ;
+reg\t[7:0]\t\tsim_spm3C ;
+reg\t[7:0]\t\tsim_spm3D ;
+reg\t[7:0]\t\tsim_spm3E ;
+reg\t[7:0]\t\tsim_spm3F ;
+reg\t[7:0]\t\tsim_spm40 ;
+reg\t[7:0]\t\tsim_spm41 ;
+reg\t[7:0]\t\tsim_spm42 ;
+reg\t[7:0]\t\tsim_spm43 ;
+reg\t[7:0]\t\tsim_spm44 ;
+reg\t[7:0]\t\tsim_spm45 ;
+reg\t[7:0]\t\tsim_spm46 ;
+reg\t[7:0]\t\tsim_spm47 ;
+reg\t[7:0]\t\tsim_spm48 ;
+reg\t[7:0]\t\tsim_spm49 ;
+reg\t[7:0]\t\tsim_spm4A ;
+reg\t[7:0]\t\tsim_spm4B ;
+reg\t[7:0]\t\tsim_spm4C ;
+reg\t[7:0]\t\tsim_spm4D ;
+reg\t[7:0]\t\tsim_spm4E ;
+reg\t[7:0]\t\tsim_spm4F ;
+reg\t[7:0]\t\tsim_spm50 ;
+reg\t[7:0]\t\tsim_spm51 ;
+reg\t[7:0]\t\tsim_spm52 ;
+reg\t[7:0]\t\tsim_spm53 ;
+reg\t[7:0]\t\tsim_spm54 ;
+reg\t[7:0]\t\tsim_spm55 ;
+reg\t[7:0]\t\tsim_spm56 ;
+reg\t[7:0]\t\tsim_spm57 ;
+reg\t[7:0]\t\tsim_spm58 ;
+reg\t[7:0]\t\tsim_spm59 ;
+reg\t[7:0]\t\tsim_spm5A ;
+reg\t[7:0]\t\tsim_spm5B ;
+reg\t[7:0]\t\tsim_spm5C ;
+reg\t[7:0]\t\tsim_spm5D ;
+reg\t[7:0]\t\tsim_spm5E ;
+reg\t[7:0]\t\tsim_spm5F ;
+reg\t[7:0]\t\tsim_spm60 ;
+reg\t[7:0]\t\tsim_spm61 ;
+reg\t[7:0]\t\tsim_spm62 ;
+reg\t[7:0]\t\tsim_spm63 ;
+reg\t[7:0]\t\tsim_spm64 ;
+reg\t[7:0]\t\tsim_spm65 ;
+reg\t[7:0]\t\tsim_spm66 ;
+reg\t[7:0]\t\tsim_spm67 ;
+reg\t[7:0]\t\tsim_spm68 ;
+reg\t[7:0]\t\tsim_spm69 ;
+reg\t[7:0]\t\tsim_spm6A ;
+reg\t[7:0]\t\tsim_spm6B ;
+reg\t[7:0]\t\tsim_spm6C ;
+reg\t[7:0]\t\tsim_spm6D ;
+reg\t[7:0]\t\tsim_spm6E ;
+reg\t[7:0]\t\tsim_spm6F ;
+reg\t[7:0]\t\tsim_spm70 ;
+reg\t[7:0]\t\tsim_spm71 ;
+reg\t[7:0]\t\tsim_spm72 ;
+reg\t[7:0]\t\tsim_spm73 ;
+reg\t[7:0]\t\tsim_spm74 ;
+reg\t[7:0]\t\tsim_spm75 ;
+reg\t[7:0]\t\tsim_spm76 ;
+reg\t[7:0]\t\tsim_spm77 ;
+reg\t[7:0]\t\tsim_spm78 ;
+reg\t[7:0]\t\tsim_spm79 ;
+reg\t[7:0]\t\tsim_spm7A ;
+reg\t[7:0]\t\tsim_spm7B ;
+reg\t[7:0]\t\tsim_spm7C ;
+reg\t[7:0]\t\tsim_spm7D ;
+reg\t[7:0]\t\tsim_spm7E ;
+reg\t[7:0]\t\tsim_spm7F ;
+reg\t[7:0]\t\tsim_spm80 ;
+reg\t[7:0]\t\tsim_spm81 ;
+reg\t[7:0]\t\tsim_spm82 ;
+reg\t[7:0]\t\tsim_spm83 ;
+reg\t[7:0]\t\tsim_spm84 ;
+reg\t[7:0]\t\tsim_spm85 ;
+reg\t[7:0]\t\tsim_spm86 ;
+reg\t[7:0]\t\tsim_spm87 ;
+reg\t[7:0]\t\tsim_spm88 ;
+reg\t[7:0]\t\tsim_spm89 ;
+reg\t[7:0]\t\tsim_spm8A ;
+reg\t[7:0]\t\tsim_spm8B ;
+reg\t[7:0]\t\tsim_spm8C ;
+reg\t[7:0]\t\tsim_spm8D ;
+reg\t[7:0]\t\tsim_spm8E ;
+reg\t[7:0]\t\tsim_spm8F ;
+reg\t[7:0]\t\tsim_spm90 ;
+reg\t[7:0]\t\tsim_spm91 ;
+reg\t[7:0]\t\tsim_spm92 ;
+reg\t[7:0]\t\tsim_spm93 ;
+reg\t[7:0]\t\tsim_spm94 ;
+reg\t[7:0]\t\tsim_spm95 ;
+reg\t[7:0]\t\tsim_spm96 ;
+reg\t[7:0]\t\tsim_spm97 ;
+reg\t[7:0]\t\tsim_spm98 ;
+reg\t[7:0]\t\tsim_spm99 ;
+reg\t[7:0]\t\tsim_spm9A ;
+reg\t[7:0]\t\tsim_spm9B ;
+reg\t[7:0]\t\tsim_spm9C ;
+reg\t[7:0]\t\tsim_spm9D ;
+reg\t[7:0]\t\tsim_spm9E ;
+reg\t[7:0]\t\tsim_spm9F ;
+reg\t[7:0]\t\tsim_spmA0 ;
+reg\t[7:0]\t\tsim_spmA1 ;
+reg\t[7:0]\t\tsim_spmA2 ;
+reg\t[7:0]\t\tsim_spmA3 ;
+reg\t[7:0]\t\tsim_spmA4 ;
+reg\t[7:0]\t\tsim_spmA5 ;
+reg\t[7:0]\t\tsim_spmA6 ;
+reg\t[7:0]\t\tsim_spmA7 ;
+reg\t[7:0]\t\tsim_spmA8 ;
+reg\t[7:0]\t\tsim_spmA9 ;
+reg\t[7:0]\t\tsim_spmAA ;
+reg\t[7:0]\t\tsim_spmAB ;
+reg\t[7:0]\t\tsim_spmAC ;
+reg\t[7:0]\t\tsim_spmAD ;
+reg\t[7:0]\t\tsim_spmAE ;
+reg\t[7:0]\t\tsim_spmAF ;
+reg\t[7:0]\t\tsim_spmB0 ;
+reg\t[7:0]\t\tsim_spmB1 ;
+reg\t[7:0]\t\tsim_spmB2 ;
+reg\t[7:0]\t\tsim_spmB3 ;
+reg\t[7:0]\t\tsim_spmB4 ;
+reg\t[7:0]\t\tsim_spmB5 ;
+reg\t[7:0]\t\tsim_spmB6 ;
+reg\t[7:0]\t\tsim_spmB7 ;
+reg\t[7:0]\t\tsim_spmB8 ;
+reg\t[7:0]\t\tsim_spmB9 ;
+reg\t[7:0]\t\tsim_spmBA ;
+reg\t[7:0]\t\tsim_spmBB ;
+reg\t[7:0]\t\tsim_spmBC ;
+reg\t[7:0]\t\tsim_spmBD ;
+reg\t[7:0]\t\tsim_spmBE ;
+reg\t[7:0]\t\tsim_spmBF ;
+reg\t[7:0]\t\tsim_spmC0 ;
+reg\t[7:0]\t\tsim_spmC1 ;
+reg\t[7:0]\t\tsim_spmC2 ;
+reg\t[7:0]\t\tsim_spmC3 ;
+reg\t[7:0]\t\tsim_spmC4 ;
+reg\t[7:0]\t\tsim_spmC5 ;
+reg\t[7:0]\t\tsim_spmC6 ;
+reg\t[7:0]\t\tsim_spmC7 ;
+reg\t[7:0]\t\tsim_spmC8 ;
+reg\t[7:0]\t\tsim_spmC9 ;
+reg\t[7:0]\t\tsim_spmCA ;
+reg\t[7:0]\t\tsim_spmCB ;
+reg\t[7:0]\t\tsim_spmCC ;
+reg\t[7:0]\t\tsim_spmCD ;
+reg\t[7:0]\t\tsim_spmCE ;
+reg\t[7:0]\t\tsim_spmCF ;
+reg\t[7:0]\t\tsim_spmD0 ;
+reg\t[7:0]\t\tsim_spmD1 ;
+reg\t[7:0]\t\tsim_spmD2 ;
+reg\t[7:0]\t\tsim_spmD3 ;
+reg\t[7:0]\t\tsim_spmD4 ;
+reg\t[7:0]\t\tsim_spmD5 ;
+reg\t[7:0]\t\tsim_spmD6 ;
+reg\t[7:0]\t\tsim_spmD7 ;
+reg\t[7:0]\t\tsim_spmD8 ;
+reg\t[7:0]\t\tsim_spmD9 ;
+reg\t[7:0]\t\tsim_spmDA ;
+reg\t[7:0]\t\tsim_spmDB ;
+reg\t[7:0]\t\tsim_spmDC ;
+reg\t[7:0]\t\tsim_spmDD ;
+reg\t[7:0]\t\tsim_spmDE ;
+reg\t[7:0]\t\tsim_spmDF ;
+reg\t[7:0]\t\tsim_spmE0 ;
+reg\t[7:0]\t\tsim_spmE1 ;
+reg\t[7:0]\t\tsim_spmE2 ;
+reg\t[7:0]\t\tsim_spmE3 ;
+reg\t[7:0]\t\tsim_spmE4 ;
+reg\t[7:0]\t\tsim_spmE5 ;
+reg\t[7:0]\t\tsim_spmE6 ;
+reg\t[7:0]\t\tsim_spmE7 ;
+reg\t[7:0]\t\tsim_spmE8 ;
+reg\t[7:0]\t\tsim_spmE9 ;
+reg\t[7:0]\t\tsim_spmEA ;
+reg\t[7:0]\t\tsim_spmEB ;
+reg\t[7:0]\t\tsim_spmEC ;
+reg\t[7:0]\t\tsim_spmED ;
+reg\t[7:0]\t\tsim_spmEE ;
+reg\t[7:0]\t\tsim_spmEF ;
+reg\t[7:0]\t\tsim_spmF0 ;
+reg\t[7:0]\t\tsim_spmF1 ;
+reg\t[7:0]\t\tsim_spmF2 ;
+reg\t[7:0]\t\tsim_spmF3 ;
+reg\t[7:0]\t\tsim_spmF4 ;
+reg\t[7:0]\t\tsim_spmF5 ;
+reg\t[7:0]\t\tsim_spmF6 ;
+reg\t[7:0]\t\tsim_spmF7 ;
+reg\t[7:0]\t\tsim_spmF8 ;
+reg\t[7:0]\t\tsim_spmF9 ;
+reg\t[7:0]\t\tsim_spmFA ;
+reg\t[7:0]\t\tsim_spmFB ;
+reg\t[7:0]\t\tsim_spmFC ;
+reg\t[7:0]\t\tsim_spmFD ;
+reg\t[7:0]\t\tsim_spmFE ;
+reg\t[7:0]\t\tsim_spmFF ;
+//
+// initialise the values
+//
+initial begin
+kcpsm6_status = ""A,NZ,NC,ID,Reset"" ;
+kcpsm6_opcode = ""LOAD s0, s0        "" ;
+
+sim_s0 = 8\'h00 ;
+sim_s1 = 8\'h00 ;
+sim_s2 = 8\'h00 ;
+sim_s3 = 8\'h00 ;
+sim_s4 = 8\'h00 ;
+sim_s5 = 8\'h00 ;
+sim_s6 = 8\'h00 ;
+sim_s7 = 8\'h00 ;
+sim_s8 = 8\'h00 ;
+sim_s9 = 8\'h00 ;
+sim_sA = 8\'h00 ;
+sim_sB = 8\'h00 ;
+sim_sC = 8\'h00 ;
+sim_sD = 8\'h00 ;
+sim_sE = 8\'h00 ;
+sim_sF = 8\'h00 ;
+
+sim_spm00 = 8\'h00 ;
+sim_spm01 = 8\'h00 ;
+sim_spm02 = 8\'h00 ;
+sim_spm03 = 8\'h00 ;
+sim_spm04 = 8\'h00 ;
+sim_spm05 = 8\'h00 ;
+sim_spm06 = 8\'h00 ;
+sim_spm07 = 8\'h00 ;
+sim_spm08 = 8\'h00 ;
+sim_spm09 = 8\'h00 ;
+sim_spm0A = 8\'h00 ;
+sim_spm0B = 8\'h00 ;
+sim_spm0C = 8\'h00 ;
+sim_spm0D = 8\'h00 ;
+sim_spm0E = 8\'h00 ;
+sim_spm0F = 8\'h00 ;
+sim_spm10 = 8\'h00 ;
+sim_spm11 = 8\'h00 ;
+sim_spm12 = 8\'h00 ;
+sim_spm13 = 8\'h00 ;
+sim_spm14 = 8\'h00 ;
+sim_spm15 = 8\'h00 ;
+sim_spm16 = 8\'h00 ;
+sim_spm17 = 8\'h00 ;
+sim_spm18 = 8\'h00 ;
+sim_spm19 = 8\'h00 ;
+sim_spm1A = 8\'h00 ;
+sim_spm1B = 8\'h00 ;
+sim_spm1C = 8\'h00 ;
+sim_spm1D = 8\'h00 ;
+sim_spm1E = 8\'h00 ;
+sim_spm1F = 8\'h00 ;
+sim_spm20 = 8\'h00 ;
+sim_spm21 = 8\'h00 ;
+sim_spm22 = 8\'h00 ;
+sim_spm23 = 8\'h00 ;
+sim_spm24 = 8\'h00 ;
+sim_spm25 = 8\'h00 ;
+sim_spm26 = 8\'h00 ;
+sim_spm27 = 8\'h00 ;
+sim_spm28 = 8\'h00 ;
+sim_spm29 = 8\'h00 ;
+sim_spm2A = 8\'h00 ;
+sim_spm2B = 8\'h00 ;
+sim_spm2C = 8\'h00 ;
+sim_spm2D = 8\'h00 ;
+sim_spm2E = 8\'h00 ;
+sim_spm2F = 8\'h00 ;
+sim_spm30 = 8\'h00 ;
+sim_spm31 = 8\'h00 ;
+sim_spm32 = 8\'h00 ;
+sim_spm33 = 8\'h00 ;
+sim_spm34 = 8\'h00 ;
+sim_spm35 = 8\'h00 ;
+sim_spm36 = 8\'h00 ;
+sim_spm37 = 8\'h00 ;
+sim_spm38 = 8\'h00 ;
+sim_spm39 = 8\'h00 ;
+sim_spm3A = 8\'h00 ;
+sim_spm3B = 8\'h00 ;
+sim_spm3C = 8\'h00 ;
+sim_spm3D = 8\'h00 ;
+sim_spm3E = 8\'h00 ;
+sim_spm3F = 8\'h00 ;
+sim_spm40 = 8\'h00 ;
+sim_spm41 = 8\'h00 ;
+sim_spm42 = 8\'h00 ;
+sim_spm43 = 8\'h00 ;
+sim_spm44 = 8\'h00 ;
+sim_spm45 = 8\'h00 ;
+sim_spm46 = 8\'h00 ;
+sim_spm47 = 8\'h00 ;
+sim_spm48 = 8\'h00 ;
+sim_spm49 = 8\'h00 ;
+sim_spm4A = 8\'h00 ;
+sim_spm4B = 8\'h00 ;
+sim_spm4C = 8\'h00 ;
+sim_spm4D = 8\'h00 ;
+sim_spm4E = 8\'h00 ;
+sim_spm4F = 8\'h00 ;
+sim_spm50 = 8\'h00 ;
+sim_spm51 = 8\'h00 ;
+sim_spm52 = 8\'h00 ;
+sim_spm53 = 8\'h00 ;
+sim_spm54 = 8\'h00 ;
+sim_spm55 = 8\'h00 ;
+sim_spm56 = 8\'h00 ;
+sim_spm57 = 8\'h00 ;
+sim_spm58 = 8\'h00 ;
+sim_spm59 = 8\'h00 ;
+sim_spm5A = 8\'h00 ;
+sim_spm5B = 8\'h00 ;
+sim_spm5C = 8\'h00 ;
+sim_spm5D = 8\'h00 ;
+sim_spm5E = 8\'h00 ;
+sim_spm5F = 8\'h00 ;
+sim_spm60 = 8\'h00 ;
+sim_spm61 = 8\'h00 ;
+sim_spm62 = 8\'h00 ;
+sim_spm63 = 8\'h00 ;
+sim_spm64 = 8\'h00 ;
+sim_spm65 = 8\'h00 ;
+sim_spm66 = 8\'h00 ;
+sim_spm67 = 8\'h00 ;
+sim_spm68 = 8\'h00 ;
+sim_spm69 = 8\'h00 ;
+sim_spm6A = 8\'h00 ;
+sim_spm6B = 8\'h00 ;
+sim_spm6C = 8\'h00 ;
+sim_spm6D = 8\'h00 ;
+sim_spm6E = 8\'h00 ;
+sim_spm6F = 8\'h00 ;
+sim_spm70 = 8\'h00 ;
+sim_spm71 = 8\'h00 ;
+sim_spm72 = 8\'h00 ;
+sim_spm73 = 8\'h00 ;
+sim_spm74 = 8\'h00 ;
+sim_spm75 = 8\'h00 ;
+sim_spm76 = 8\'h00 ;
+sim_spm77 = 8\'h00 ;
+sim_spm78 = 8\'h00 ;
+sim_spm79 = 8\'h00 ;
+sim_spm7A = 8\'h00 ;
+sim_spm7B = 8\'h00 ;
+sim_spm7C = 8\'h00 ;
+sim_spm7D = 8\'h00 ;
+sim_spm7E = 8\'h00 ;
+sim_spm7F = 8\'h00 ;
+sim_spm80 = 8\'h00 ;
+sim_spm81 = 8\'h00 ;
+sim_spm82 = 8\'h00 ;
+sim_spm83 = 8\'h00 ;
+sim_spm84 = 8\'h00 ;
+sim_spm85 = 8\'h00 ;
+sim_spm86 = 8\'h00 ;
+sim_spm87 = 8\'h00 ;
+sim_spm88 = 8\'h00 ;
+sim_spm89 = 8\'h00 ;
+sim_spm8A = 8\'h00 ;
+sim_spm8B = 8\'h00 ;
+sim_spm8C = 8\'h00 ;
+sim_spm8D = 8\'h00 ;
+sim_spm8E = 8\'h00 ;
+sim_spm8F = 8\'h00 ;
+sim_spm90 = 8\'h00 ;
+sim_spm91 = 8\'h00 ;
+sim_spm92 = 8\'h00 ;
+sim_spm93 = 8\'h00 ;
+sim_spm94 = 8\'h00 ;
+sim_spm95 = 8\'h00 ;
+sim_spm96 = 8\'h00 ;
+sim_spm97 = 8\'h00 ;
+sim_spm98 = 8\'h00 ;
+sim_spm99 = 8\'h00 ;
+sim_spm9A = 8\'h00 ;
+sim_spm9B = 8\'h00 ;
+sim_spm9C = 8\'h00 ;
+sim_spm9D = 8\'h00 ;
+sim_spm9E = 8\'h00 ;
+sim_spm9F = 8\'h00 ;
+sim_spmA0 = 8\'h00 ;
+sim_spmA1 = 8\'h00 ;
+sim_spmA2 = 8\'h00 ;
+sim_spmA3 = 8\'h00 ;
+sim_spmA4 = 8\'h00 ;
+sim_spmA5 = 8\'h00 ;
+sim_spmA6 = 8\'h00 ;
+sim_spmA7 = 8\'h00 ;
+sim_spmA8 = 8\'h00 ;
+sim_spmA9 = 8\'h00 ;
+sim_spmAA = 8\'h00 ;
+sim_spmAB = 8\'h00 ;
+sim_spmAC = 8\'h00 ;
+sim_spmAD = 8\'h00 ;
+sim_spmAE = 8\'h00 ;
+sim_spmAF = 8\'h00 ;
+sim_spmB0 = 8\'h00 ;
+sim_spmB1 = 8\'h00 ;
+sim_spmB2 = 8\'h00 ;
+sim_spmB3 = 8\'h00 ;
+sim_spmB4 = 8\'h00 ;
+sim_spmB5 = 8\'h00 ;
+sim_spmB6 = 8\'h00 ;
+sim_spmB7 = 8\'h00 ;
+sim_spmB8 = 8\'h00 ;
+sim_spmB9 = 8\'h00 ;
+sim_spmBA = 8\'h00 ;
+sim_spmBB = 8\'h00 ;
+sim_spmBC = 8\'h00 ;
+sim_spmBD = 8\'h00 ;
+sim_spmBE = 8\'h00 ;
+sim_spmBF = 8\'h00 ;
+sim_spmC0 = 8\'h00 ;
+sim_spmC1 = 8\'h00 ;
+sim_spmC2 = 8\'h00 ;
+sim_spmC3 = 8\'h00 ;
+sim_spmC4 = 8\'h00 ;
+sim_spmC5 = 8\'h00 ;
+sim_spmC6 = 8\'h00 ;
+sim_spmC7 = 8\'h00 ;
+sim_spmC8 = 8\'h00 ;
+sim_spmC9 = 8\'h00 ;
+sim_spmCA = 8\'h00 ;
+sim_spmCB = 8\'h00 ;
+sim_spmCC = 8\'h00 ;
+sim_spmCD = 8\'h00 ;
+sim_spmCE = 8\'h00 ;
+sim_spmCF = 8\'h00 ;
+sim_spmD0 = 8\'h00 ;
+sim_spmD1 = 8\'h00 ;
+sim_spmD2 = 8\'h00 ;
+sim_spmD3 = 8\'h00 ;
+sim_spmD4 = 8\'h00 ;
+sim_spmD5 = 8\'h00 ;
+sim_spmD6 = 8\'h00 ;
+sim_spmD7 = 8\'h00 ;
+sim_spmD8 = 8\'h00 ;
+sim_spmD9 = 8\'h00 ;
+sim_spmDA = 8\'h00 ;
+sim_spmDB = 8\'h00 ;
+sim_spmDC = 8\'h00 ;
+sim_spmDD = 8\'h00 ;
+sim_spmDE = 8\'h00 ;
+sim_spmDF = 8\'h00 ;
+sim_spmE0 = 8\'h00 ;
+sim_spmE1 = 8\'h00 ;
+sim_spmE2 = 8\'h00 ;
+sim_spmE3 = 8\'h00 ;
+sim_spmE4 = 8\'h00 ;
+sim_spmE5 = 8\'h00 ;
+sim_spmE6 = 8\'h00 ;
+sim_spmE7 = 8\'h00 ;
+sim_spmE8 = 8\'h00 ;
+sim_spmE9 = 8\'h00 ;
+sim_spmEA = 8\'h00 ;
+sim_spmEB = 8\'h00 ;
+sim_spmEC = 8\'h00 ;
+sim_spmED = 8\'h00 ;
+sim_spmEE = 8\'h00 ;
+sim_spmEF = 8\'h00 ;
+sim_spmF0 = 8\'h00 ;
+sim_spmF1 = 8\'h00 ;
+sim_spmF2 = 8\'h00 ;
+sim_spmF3 = 8\'h00 ;
+sim_spmF4 = 8\'h00 ;
+sim_spmF5 = 8\'h00 ;
+sim_spmF6 = 8\'h00 ;
+sim_spmF7 = 8\'h00 ;
+sim_spmF8 = 8\'h00 ;
+sim_spmF9 = 8\'h00 ;
+sim_spmFA = 8\'h00 ;
+sim_spmFB = 8\'h00 ;
+sim_spmFC = 8\'h00 ;
+sim_spmFD = 8\'h00 ;
+sim_spmFE = 8\'h00 ;
+sim_spmFF = 8\'h00 ;
+end
+//
+//synthesis translate_on
+//
+//**********************************************************************************
+//
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+//\t
+// Start of kcpsm6 circuit description
+//
+// Summary of all primitives defined.
+//
+//     29 x LUT6             79 LUTs
+//     50 x LUT6_2
+//     48 x FD               82 flip-flops
+//     20 x FDR       (Depending on the value of \'hwbuild\' up)
+//      0 x FDS       (to eight FDR will be replaced by FDS  )          
+//     14 x FDRE
+//     29 x MUXCY
+//     27 x XORCY
+//      4 x RAM32M    (16 LUTs)
+//
+//      2 x RAM64M   or  8 x RAM128X1S   or  8 x RAM256X1S
+//       (8 LUTs)          (16 LUTs)           (32 LUTs)
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//\t
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+// Perform check of generic to report error as soon as possible.
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+initial begin
+if (scratch_pad_memory_size != 64 && scratch_pad_memory_size != 128 && scratch_pad_memory_size != 256) begin
+#1;
+$display(""\
+\
+Invalid \'scratch_pad_memory_size\'. Please set to 64, 128 or 256.\
+\
+"");
+$finish;
+end
+end
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+// State Machine and Control 
+//
+//
+//     1 x LUT6
+//     4 x LUT6_2
+//     9 x FD
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+
+(* HBLKNM = ""kcpsm6_control"" *)
+LUT6_2 #(
+\t.INIT\t(64\'hFFFFF55500000EEE))
+reset_lut( 
+\t.I0 \t(run),
+\t.I1 \t(internal_reset),
+\t.I2 \t(stack_pointer_carry[4]),
+\t.I3 \t(t_state[2]),
+\t.I4 \t(reset),
+\t.I5 \t(1\'b1),
+\t.O5 \t(run_value),
+\t.O6 \t(internal_reset_value));
+
+(* HBLKNM = ""kcpsm6_control"" *)
+FD run_flop (  
+\t.D \t(run_value),
+\t.Q \t(run),
+\t.C \t(clk));
+
+(* HBLKNM = ""kcpsm6_control"" *)
+FD internal_reset_flop(
+\t.D\t(internal_reset_value),
+\t.Q\t(internal_reset),
+\t.C\t(clk));
+
+(* HBLKNM = ""kcpsm6_decode2"" *)
+FD sync_sleep_flop(
+\t.D \t(sleep),
+\t.Q \t(sync_sleep),
+\t.C \t(clk));
+
+(* HBLKNM = ""kcpsm6_control"" *)
+LUT6_2 #(
+\t.INIT    (64\'h0083000B00C4004C))
+t_state_lut( 
+\t.I0     (t_state[1]),
+\t.I1     (t_state[2]),
+\t.I2     (sync_sleep),
+\t.I3     (internal_reset),
+\t.I4     (special_bit),
+\t.I5     (1\'b1),
+\t.O5     (t_state_value[1]),
+\t.O6     (t_state_value[2]));
+
+(* HBLKNM = ""kcpsm6_control"" *)
+FD t_state1_flop (  
+\t.D      (t_state_value[1]),
+\t.Q      (t_state[1]),
+\t.C      (clk));
+
+(* HBLKNM = ""kcpsm6_control"" *)
+FD t_state2_flop (  
+\t.D      (t_state_value[2]),
+\t.Q      (t_state[2]),
+\t.C      (clk));
+
+
+(* HBLKNM = ""kcpsm6_decode0"" *)
+LUT6_2 #(
+\t.INIT\t(64\'h0010000000000800))
+int_enable_type_lut( 
+\t.I0     (instruction[13]),
+\t.I1     (instruction[14]),
+\t.I2     (instruction[15]),
+\t.I3     (instruction[16]),
+\t.I4     (instruction[17]),
+\t.I5     (1\'b1),
+\t.O5     (loadstar_type),
+\t.O6     (int_enable_type)) ;
+
+(* HBLKNM = ""kcpsm6_decode0"" *)
+LUT6 #(
+\t.INIT    (64\'h000000000000CAAA))
+interrupt_enable_lut( 
+\t.I0     (interrupt_enable),
+\t.I1     (instruction[0]),
+\t.I2     (int_enable_type),
+\t.I3     (t_state[1]),
+\t.I4     (active_interrupt),
+\t.I5     (internal_reset),
+\t.O      (interrupt_enable_value));                     
+
+(* HBLKNM = ""kcpsm6_decode0"" *)
+FD interrupt_enable_flop (  
+\t.D      (interrupt_enable_value),
+\t.Q      (interrupt_enable),
+\t.C      (clk));
+
+(* HBLKNM = ""kcpsm6_decode2"" *)
+FD sync_interrupt_flop (  
+\t.D      (interrupt),
+\t.Q      (sync_interrupt),
+\t.C      (clk));
+
+(* HBLKNM = ""kcpsm6_control"" *)
+LUT6_2 # (
+\t.INIT    (64\'hCC33FF0080808080))
+active_interrupt_lut( 
+\t.I0     (interrupt_enable),
+\t.I1     (t_state[2]),
+\t.I2     (sync_interrupt),
+\t.I3     (bank),
+\t.I4     (loadstar_type),
+\t.I5     (1\'b1),
+\t.O5     (active_interrupt_value), 
+\t.O6     (sx_addr4_value));
+
+(* HBLKNM = ""kcpsm6_control"" *)
+FD active_interrupt_flop (  
+\t.D      (active_interrupt_value),
+\t.Q      (active_interrupt),
+\t.C      (clk));
+
+(* HBLKNM = ""kcpsm6_decode1"" *)
+FD interrupt_ack_flop (  
+\t.D      (active_interrupt),
+\t.Q      (interrupt_ack),
+\t.C      (clk));
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+// Decoders 
+//
+//
+//     2 x LUT6
+//    10 x LUT6_2
+//     2 x FD
+//     6 x FDR
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+
+//
+// Decoding for Program Counter and Stack
+//
+
+(* HBLKNM = ""kcpsm6_decode0"" *)
+LUT6 #(
+\t.INIT    (64\'h5A3CFFFF00000000))
+pc_move_is_valid_lut( 
+\t.I0     (carry_flag),
+\t.I1     (zero_flag),
+\t.I2     (instruction[14]),
+\t.I3     (instruction[15]),
+\t.I4     (instruction[16]),
+\t.I5     (instruction[17]),
+\t.O      (pc_move_is_valid)) ;
+
+(* HBLKNM = ""kcpsm6_decode0"" *)
+LUT6_2 # (
+\t.INIT    (64\'h7777027700000200))
+move_type_lut( 
+\t.I0     (instruction[12]),
+\t.I1     (instruction[13]),
+\t.I2     (instruction[14]),
+\t.I3     (instruction[15]),
+\t.I4     (instruction[16]),
+\t.I5     (1\'b1),
+\t.O5     (returni_type), 
+\t.O6     (move_type)) ;
+
+(* HBLKNM = ""kcpsm6_vector1"" *)
+LUT6_2 # (
+\t.INIT    (64\'h0000F000000023FF))
+pc_mode1_lut( 
+\t.I0     (instruction[12]),
+\t.I1     (returni_type),
+\t.I2     (move_type),
+\t.I3     (pc_move_is_valid),
+\t.I4     (active_interrupt),
+\t.I5     (1\'b1),
+\t.O5     (pc_mode[0]),
+\t.O6     (pc_mode[1])) ;
+
+(* HBLKNM = ""kcpsm6_vector1"" *)
+LUT6 # (
+\t.INIT    (64\'hFFFFFFFF00040000))
+pc_mode2_lut( 
+\t.I0     (instruction[12]),
+\t.I1     (instruction[14]),
+\t.I2     (instruction[15]),
+\t.I3     (instruction[16]),
+\t.I4     (instruction[17]),
+\t.I5     (active_interrupt),
+\t.O      (pc_mode[2])) ;
+
+(* HBLKNM = ""kcpsm6_stack1"" *)
+LUT6_2 # (
+\t.INIT    (64\'hFFFF100000002000))
+push_pop_lut( 
+\t.I0     (instruction[12]),
+\t.I1     (instruction[13]),
+\t.I2     (move_type),
+\t.I3     (pc_move_is_valid),
+\t.I4     (active_interrupt),
+\t.I5     (1\'b1),
+\t.O5     (pop_stack),
+\t.O6     (push_stack)) ;
+
+//
+// Decoding for ALU
+//
+
+(* HBLKNM = ""kcpsm6_decode2"" *)
+LUT6_2 #(
+\t.INIT    (64\'h03CA000004200000))
+alu_decode0_lut( 
+\t.I0     (instruction[13]),
+\t.I1     (instruction[14]),
+\t.I2     (instruction[15]),
+\t.I3     (instruction[16]),
+\t.I4     (1\'b1),
+\t.I5     (1\'b1),
+\t.O5     (alu_mux_sel_value[0]),
+\t.O6     (arith_logical_sel[0])) ;
+
+(* HBLKNM = ""kcpsm6_decode2"" *)
+FD alu_mux_sel0_flop(  
+\t.D      (alu_mux_sel_value[0]),
+\t.Q      (alu_mux_sel[0]),
+\t.C      (clk)) ;
+
+(* HBLKNM = ""kcpsm6_decode1"" *)
+LUT6_2 #(
+\t.INIT    (64\'h7708000000000F00))
+alu_decode1_lut( 
+\t.I0     (carry_flag),
+\t.I1     (instruction[13]),
+\t.I2     (instruction[14]),
+\t.I3     (instruction[15]),
+\t.I4     (instruction[16]),
+\t.I5     (1\'b1),
+\t.O5     (alu_mux_sel_value[1]),
+\t.O6     (arith_carry_in)) ;                     
+
+(* HBLKNM = ""kcpsm6_decode1"" *)
+FD alu_mux_sel1_flop (  
+\t.D      (alu_mux_sel_value[1]),
+\t.Q      (alu_mux_sel[1]),
+\t.C      (clk)) ;
+
+
+(* HBLKNM = ""kcpsm6_decode2"" *)
+LUT6_2 # (
+\t.INIT    (64\'hD000000002000000))
+alu_decode2_lut( 
+\t.I0     (instruction[14]),
+\t.I1     (instruction[15]),
+\t.I2     (instruction[16]),
+\t.I3     (1\'b1),
+\t.I4     (1\'b1),
+\t.I5     (1\'b1),
+\t.O5     (arith_logical_sel[1]),
+\t.O6     (arith_logical_sel[2])) ;
+
+//
+// Decoding for strobes and enables
+//
+
+(* HBLKNM = ""kcpsm6_strobes"" *)
+LUT6_2 # (
+\t.INIT    (64\'h00013F3F0010F7CE))
+register_enable_type_lut( 
+\t.I0     (instruction[13]),
+\t.I1     (instruction[14]),
+\t.I2     (instruction[15]),
+\t.I3     (instruction[16]),
+\t.I4     (instruction[17]),
+\t.I5     (1\'b1),
+\t.O5     (flag_enable_type),
+\t.O6     (register_enable_type)) ;
+
+(* HBLKNM = ""kcpsm6_strobes"" *)
+LUT6_2 # (
+\t.INIT    (64\'hC0CC0000A0AA0000))
+register_enable_lut( 
+\t.I0     (flag_enable_type),
+\t.I1     (register_enable_type),
+\t.I2     (instruction[12]),
+\t.I3     (instruction[17]),
+\t.I4     (t_state[1]),
+\t.I5     (1\'b1),
+\t.O5     (flag_enable_value),
+\t.O6     (register_enable_value)) ;
+
+(* HBLKNM = ""kcpsm6_strobes"" *)
+FDR flag_enable_flop (  
+\t.D      (flag_enable_value),
+\t.Q      (flag_enable),
+\t.R      (active_interrupt),
+\t.C      (clk)) ;
+
+(* HBLKNM = ""kcpsm6_strobes"" *)
+FDR register_enable_flop (  
+\t.D      (register_enable_value),
+\t.Q      (register_enable),
+\t.R      (active_interrupt),
+\t.C      (clk)) ;
+
+(* HBLKNM = ""kcpsm6_strobes"" *)
+LUT6_2 # (
+\t.INIT    (64\'h8000000020000000))
+spm_enable_lut( 
+\t.I0     (instruction[13]),
+\t.I1     (instruction[14]),
+\t.I2     (instruction[17]),
+\t.I3     (strobe_type),
+\t.I4     (t_state[1]),
+\t.I5     (1\'b1),
+\t.O5     (k_write_strobe_value),
+\t.O6     (spm_enable_value)) ;
+
+(* HBLKNM = ""kcpsm6_strobes"" *)
+FDR k_write_strobe_flop (  
+\t.D      (k_write_strobe_value),
+\t.Q      (k_write_strobe),
+\t.R      (active_interrupt),
+\t.C      (clk)) ;
+
+(* HBLKNM = ""kcpsm6_strobes"" *)
+FDR spm_enable_flop (  
+\t.D      (spm_enable_value),
+\t.Q      (spm_enable),
+\t.R      (active_interrupt),
+\t.C      (clk)) ;
+
+(* HBLKNM = ""kcpsm6_strobes"" *)
+LUT6_2 # (
+\t.INIT    (64\'h4000000001000000))
+read_strobe_lut( 
+\t.I0     (instruction[13]),
+\t.I1     (instruction[14]),
+\t.I2     (instruction[17]),
+\t.I3     (strobe_type),
+\t.I4     (t_state[1]),
+\t.I5     (1\'b1),
+\t.O5     (read_strobe_value),
+\t.O6     (write_strobe_value)) ;
+
+(* HBLKNM = ""kcpsm6_strobes"" *)
+FDR write_strobe_flop (  
+\t.D      (write_strobe_value),
+\t.Q      (write_strobe),
+\t.R      (active_interrupt),
+\t.C      (clk)) ;
+
+(* HBLKNM = ""kcpsm6_strobes"" *)
+FDR read_strobe_flop (  
+\t.D      (read_strobe_value),
+\t.Q      (read_strobe),
+\t.R      (active_interrupt),
+\t.C      (clk)) ;
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+// Register bank control
+//
+//
+//     2 x LUT6
+//     1 x FDR
+//     1 x FD
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+(* HBLKNM = ""kcpsm6_stack1"" *)
+LUT6 # (
+\t.INIT    (64\'h0080020000000000))
+regbank_type_lut( 
+\t.I0     (instruction[12]),
+\t.I1     (instruction[13]),
+\t.I2     (instruction[14]),
+\t.I3     (instruction[15]),
+\t.I4     (instruction[16]),
+\t.I5     (instruction[17]),
+\t.O      (regbank_type)) ;
+
+(* HBLKNM = ""kcpsm6_stack1"" *)
+LUT6 # (
+\t.INIT    (64\'hACACFF00FF00FF00))
+bank_lut( 
+\t.I0     (instruction[0]),
+\t.I1     (shadow_bank),
+\t.I2     (instruction[16]),
+\t.I3     (bank),
+\t.I4     (regbank_type),
+\t.I5     (t_state[1]),
+\t.O      (bank_value)) ;                     
+
+(* HBLKNM = ""kcpsm6_stack1"" *)
+FDR bank_flop (  
+\t.D      (bank_value),
+\t.Q      (bank),
+\t.R      (internal_reset),
+\t.C      (clk)) ;
+
+(* HBLKNM = ""kcpsm6_control"" *)
+FD sx_addr4_flop (  
+\t.D      (sx_addr4_value),
+\t.Q      (sx_addr[4]),
+\t.C      (clk)) ;
+
+assign sx_addr[3:0] = instruction[11:8] ;
+assign sy_addr = {bank, instruction[7:4]} ;
+
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+// Flags
+//
+//
+//     3 x LUT6
+//     5 x LUT6_2
+//     3 x FD
+//     2 x FDRE
+//     2 x XORCY
+//     5 x MUXCY
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+
+(* HBLKNM = ""kcpsm6_control"" *)
+XORCY arith_carry_xorcy ( 
+\t.LI \t(1\'b0),
+\t.CI \t(carry_arith_logical[7]),
+\t.O      (arith_carry_value)) ;
+
+(* HBLKNM = ""kcpsm6_control"" *)
+FD arith_carry_flop (  
+\t.D      (arith_carry_value),
+\t.Q      (arith_carry),
+\t.C      (clk)) ;
+
+(* HBLKNM = ""kcpsm6_decode2"" *)
+LUT6_2 # (
+\t.INIT    (64\'h0000000087780000))
+lower_parity_lut( 
+\t.I0     (instruction[13]),
+\t.I1     (carry_flag),
+\t.I2     (arith_logical_result[0]),
+\t.I3     (arith_logical_result[1]),
+\t.I4     (1\'b1),
+\t.I5     (1\'b1),
+\t.O5     (lower_parity),
+\t.O6     (lower_parity_sel)) ;  
+                 
+(* HBLKNM = ""kcpsm6_decode2"" *)
+MUXCY parity_muxcy ( 
+\t.DI\t(lower_parity),
+\t.CI\t(1\'b0),                     
+\t.S\t(lower_parity_sel),
+\t.O      (carry_lower_parity)) ;
+
+(* HBLKNM = ""kcpsm6_decode2"" *)
+LUT6 #(
+\t.INIT    (64\'h6996966996696996))
+upper_parity_lut( 
+\t.I0     (arith_logical_result[2]),
+\t.I1     (arith_logical_result[3]),
+\t.I2     (arith_logical_result[4]),
+\t.I3     (arith_logical_result[5]),
+\t.I4     (arith_logical_result[6]),
+\t.I5     (arith_logical_result[7]),
+\t.O      (upper_parity)) ;                     
+
+(* HBLKNM = ""kcpsm6_decode2"" *)
+XORCY parity_xorcy( 
+\t.LI\t(upper_parity),
+        .CI\t(carry_lower_parity),
+\t.O      (parity)) ;
+
+(* HBLKNM = ""kcpsm6_decode1"" *)
+LUT6 #(
+\t.INIT    (64\'hFFFFAACCF0F0F0F0))
+shift_carry_lut( 
+\t.I0     (sx[0]),
+\t.I1     (sx[7]),
+\t.I2     (shadow_carry_flag),
+\t.I3     (instruction[3]),
+\t.I4     (instruction[7]),
+\t.I5     (instruction[16]),
+\t.O      (shift_carry_value)) ;                     
+
+(* HBLKNM = ""kcpsm6_decode1"" *)
+FD shift_carry_flop(  
+\t.D      (shift_carry_value),
+\t.Q      (shift_carry),
+\t.C      (clk)) ;
+
+(* HBLKNM = ""kcpsm6_flags"" *)
+LUT6_2 #(
+\t.INIT    (64\'h3333AACCF0AA0000))
+carry_flag_lut( 
+\t.I0     (shift_carry),
+\t.I1     (arith_carry),
+\t.I2     (parity),
+\t.I3     (instruction[14]),
+\t.I4     (instruction[15]),
+\t.I5     (instruction[16]),
+\t.O5     (drive_carry_in_zero),
+\t.O6     (carry_flag_value)) ;  
+
+(* HBLKNM = ""kcpsm6_flags"" *)
+FDRE carry_flag_flop(  
+\t.D      (carry_flag_value),
+\t.Q      (carry_flag),
+       \t.CE     (flag_enable),
+\t.R      (internal_reset),
+\t.C      (clk)) ;
+
+(* HBLKNM = ""kcpsm6_flags"" *)
+MUXCY init_zero_muxcy( 
+\t.DI\t(drive_carry_in_zero),
+\t.CI\t(1\'b0),
+\t.S\t(carry_flag_value),
+\t.O      (carry_in_zero)) ;
+
+(* HBLKNM = ""kcpsm6_decode1"" *)
+LUT6_2 # (
+\t.INIT    (64\'hA280000000F000F0))
+use_zero_flag_lut( 
+\t.I0     (instruction[13]),
+\t.I1     (instruction[14]),
+\t.I2     (instruction[15]),
+\t.I3     (instruction[16]),
+\t.I4     (1\'b1),
+\t.I5     (1\'b1),
+\t.O5     (strobe_type),
+\t.O6     (use_zero_flag_value)) ;                     
+
+(* HBLKNM = ""kcpsm6_decode1"" *)
+FD use_zero_flag_flop(  
+\t.D      (use_zero_flag_value),
+\t.Q      (use_zero_flag),
+\t.C      (clk)) ;
+
+(* HBLKNM = ""kcpsm6_flags"" *)
+LUT6_2 #(
+\t.INIT    (64\'h0000000000000001))
+lower_zero_lut( 
+\t.I0     (alu_result[0]),
+\t.I1     (alu_result[1]),
+\t.I2     (alu_result[2]),
+\t.I3     (alu_result[3]),
+\t.I4     (alu_result[4]),
+\t.I5     (1\'b1),
+\t.O5     (lower_zero),
+\t.O6     (lower_zero_sel)) ;                     
+
+(* HBLKNM = ""kcpsm6_flags"" *)
+MUXCY lower_zero_muxcy( 
+\t.DI\t(lower_zero),
+\t.CI\t(carry_in_zero),
+\t.S\t(lower_zero_sel),
+\t.O      (carry_lower_zero)) ;
+
+(* HBLKNM = ""kcpsm6_flags"" *)
+LUT6_2 # (
+\t.INIT    (64\'h0000000D00000000))
+middle_zero_lut( 
+\t.I0     (use_zero_flag),
+\t.I1     (zero_flag),
+\t.I2     (alu_result[5]),
+\t.I3     (alu_result[6]),
+\t.I4     (alu_result[7]),
+\t.I5     (1\'b1),
+\t.O5     (middle_zero),
+\t.O6     (middle_zero_sel)) ;                     
+
+(* HBLKNM = ""kcpsm6_flags"" *)
+MUXCY middle_zero_muxcy( 
+\t.DI\t(middle_zero),
+\t.CI\t(carry_lower_zero),                     
+\t.S \t(middle_zero_sel),
+  \t.O      (carry_middle_zero)) ;
+
+(* HBLKNM = ""kcpsm6_flags"" *)
+LUT6 #(
+\t.INIT    (64\'hFBFF000000000000))
+upper_zero_lut( 
+\t.I0     (instruction[14]),
+\t.I1     (instruction[15]),
+\t.I2     (instruction[16]),
+\t.I3     (1\'b1),
+\t.I4     (1\'b1),
+\t.I5     (1\'b1),
+\t.O      (upper_zero_sel)) ;                     
+
+(* HBLKNM = ""kcpsm6_flags"" *)
+MUXCY upper_zero_muxcy( 
+\t.DI\t(shadow_zero_flag),
+\t.CI\t(carry_middle_zero),                    
+\t.S\t(upper_zero_sel),
+\t.O      (zero_flag_value)) ;
+
+(* HBLKNM = ""kcpsm6_flags"" *)
+FDRE zero_flag_flop(  
+\t.D      (zero_flag_value),
+\t.Q      (zero_flag),
+\t.CE     (flag_enable),
+\t.R      (internal_reset),
+\t.C      (clk)) ;
+
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+// 12-bit Program Address Generation 
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+
+//
+// Prepare 12-bit vector from the sX and sY register outputs.
+//
+
+assign register_vector = {sx[3:0], sy} ;
+
+genvar i ;
+
+generate
+for (i = 0 ; i <= 11 ; i = i+1)
+begin : address_loop
+parameter [7:0] id4 = 8\'h30 + i/4 ;
+parameter [7:0] id8 = 8\'h30 + i/8 ;
+parameter [7:0] ip4d8 = 8\'h30 + (i+4)/8 ;\t  
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+// Selection of vector to load program counter
+//
+// instruction[12]
+//              0  Constant aaa from instruction(11:0)
+//              1  Return vector from stack 
+//
+// \'aaa\' is used during \'JUMP aaa\', \'JUMP c, aaa\', \'CALL aaa\' and \'CALL c, aaa\'.
+// Return vector is used during \'RETURN\', \'RETURN c\', \'RETURN&LOAD\' and \'RETURNI\'.
+//
+//     6 x LUT6_2
+//     12 x FD
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+
+//
+// Pipeline output of the stack memory
+//
+(* HBLKNM = {""kcpsm6_stack_ram"",ip4d8} *)
+FD return_vector_flop(  
+\t.D      (stack_memory[i]),
+\t.Q      (return_vector[i]),
+\t.C      (clk));
+//
+// Multiplex instruction constant address and output from stack.
+// 2 bits per LUT so only generate when \'i\' is even.
+//
+if (i % 2 == 0) begin: output_data
+
+(* HBLKNM = {""kcpsm6_vector"",id8} *)
+LUT6_2 #(
+\t.INIT   (64\'hFF00F0F0CCCCAAAA))
+pc_vector_mux_lut( 
+\t.I0     (instruction[i]),
+\t.I1     (return_vector[i]),
+\t.I2     (instruction[i+1]),
+\t.I3     (return_vector[i+1]),
+\t.I4     (instruction[12]),
+\t.I5     (1\'b1),
+\t.O5     (pc_vector[i]),
+\t.O6     (pc_vector[i+1]));
+
+end //output_data
+
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+// Program Counter
+//
+// Reset by internal_reset has highest priority.
+// Enabled by t_state[1] has second priority.
+//
+// The function performed is defined by pc_mode(2:0).
+//
+// pc_mode [2] [1] [0] 
+//          0   0   1  pc+1 for normal program flow.
+//          1   0   0  Forces interrupt vector value (+0) during active interrupt.
+//                     The vector is defined by a generic with default value FF0 hex.
+//          1   1   0  register_vector (+0) for \'JUMP (sX, sY)\' and \'CALL (sX, sY)\'.
+//          0   1   0  pc_vector (+0) for \'JUMP/CALL aaa\' and \'RETURNI\'.
+//          0   1   1  pc_vector+1 for \'RETURN\'.
+//
+// Note that pc_mode[0] is High during operations that require an increment to occur.
+// The LUT6 associated with the LSB must invert pc or pc_vector in these cases and 
+// pc_mode[0] also has to be connected to the start of the carry chain.
+//
+// 3 Slices 
+//     12 x LUT6
+//     11 x MUXCY
+//     12 x XORCY
+//     12 x FDRE
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+(* HBLKNM = {""kcpsm6_pc"",id4} *)
+FDRE pc_flop(  
+\t.D      (pc_value[i]),
+\t.Q      (pc[i]),
+\t.R      (internal_reset),
+\t.CE     (t_state[1]),
+\t.C      (clk));
+
+if (i == 0) begin: lsb_pc
+
+//
+// Logic of LSB must invert selected value when pc_mode[0] is High.
+// The interrupt vector is defined by a generic.
+//
+
+if (interrupt_vector[i] == 1\'b0) begin: low_int_vector
+
+(* HBLKNM = {""kcpsm6_pc"",id4} *)
+LUT6 #(
+\t.INIT    (64\'h00AA000033CC0F00))
+pc_lut( 
+\t.I0     (register_vector[i]),
+\t.I1     (pc_vector[i]),
+\t.I2     (pc[i]),
+\t.I3     (pc_mode[0]),
+\t.I4     (pc_mode[1]),
+\t.I5     (pc_mode[2]), 
+\t.O      (half_pc[i]));
+
+end //low_int_vector
+
+if (interrupt_vector[i] == 1\'b1) begin: high_int_vector
+
+(* HBLKNM = {""kcpsm6_pc"",id4} *)
+LUT6 #(
+\t.INIT    (64\'h00AA00FF33CC0F00))
+pc_lut( 
+\t.I0     (register_vector[i]),
+\t.I1     (pc_vector[i]),
+\t.I2     (pc[i]),
+\t.I3     (pc_mode[0]),
+\t.I4     (pc_mode[1]),
+\t.I5     (pc_mode[2]), 
+\t.O      (half_pc[i]));
+
+end //high_int_vector
+
+//
+// pc_mode[0] 'b'connected to first MUXCY and carry input is 1\'b0
+//
+
+(* HBLKNM = {""kcpsm6_pc"",id4} *)
+XORCY pc_xorcy( 
+\t.LI\t(half_pc[i]),
+\t.CI\t(1\'b0),
+\t.O      (pc_value[i]));
+
+(* HBLKNM = {""kcpsm6_pc"",id4} *)
+MUXCY pc_muxcy( 
+\t.DI \t(pc_mode[0]),
+\t.CI \t(1\'b0),
+\t.S\t(half_pc[i]),
+        .O      (carry_pc[i]));
+
+end //lsb_pc
+
+if (i > 0) begin : upper_pc
+
+//
+// Logic of upper section selects required value.
+// The interrupt vector is defined by a generic.
+//
+
+if (interrupt_vector[i] == 1\'b0) begin: low_int_vector
+
+(* HBLKNM = {""kcpsm6_pc"",id4} *)
+LUT6 #(
+\t.INIT    (64\'h00AA0000CCCCF000))
+pc_lut( 
+\t.I0     (register_vector[i]),
+\t.I1     (pc_vector[i]),
+\t.I2     (pc[i]),
+\t.I3     (pc_mode[0]),
+\t.I4     (pc_mode[1]),
+\t.I5     (pc_mode[2]), 
+\t.O      (half_pc[i]));
+
+end //low_int_vector
+
+if (interrupt_vector[i] == 1\'b1) begin: high_int_vector
+
+(* HBLKNM = {""kcpsm6_pc"",id4} *)
+LUT6 #(
+\t.INIT    (64\'h00AA00FFCCCCF000))
+pc_lut( 
+\t.I0     (register_vector[i]),
+\t.I1     (pc_vector[i]),
+\t.I2     (pc[i]),
+\t.I3     (pc_mode[0]),
+\t.I4     (pc_mode[1]),
+\t.I5     (pc_mode[2]), 
+\t.O      (half_pc[i]));
+
+end //high_int_vector
+
+//
+// Carry chain implementing remainder of increment function
+//
+(* HBLKNM = {""kcpsm6_pc"",id4} *)
+XORCY pc_xorcy( 
+\t.LI\t(half_pc[i]),
+\t.CI\t(carry_pc[i-1]),
+\t.O      (pc_value[i]));
+
+
+//
+// No MUXCY required at the top of the chain
+//
+if (i < 11) begin: mid_pc
+
+(* HBLKNM = {""kcpsm6_pc"",id4} *)
+MUXCY pc_muxcy( 
+\t.DI \t(1\'b0),
+\t.CI \t(carry_pc[i-1]),
+\t.S \t(half_pc[i]),
+\t.O     \t(carry_pc[i]));
+
+end //mid_pc
+
+end //upper_pc
+
+
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+end //address_loop
+endgenerate
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+// Stack 
+//  Preserves upto 31 nested values of the Program Counter during CALL and RETURN.
+//  Also preserves flags and bank selection during interrupt.
+//
+//     2 x RAM32M 
+//     4 x FD
+//     5 x FDR
+//     1 x LUT6
+//     4 x LUT6_2
+//     5 x XORCY
+//     5 x MUXCY
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+
+(* HBLKNM = ""kcpsm6_stack_ram0"" *)
+FD shadow_carry_flag_flop(  
+\t.D      (stack_carry_flag),
+\t.Q      (shadow_carry_flag),
+\t.C      (clk)) ;
+
+(* HBLKNM = ""kcpsm6_stack_ram0"" *)
+FD stack_zero_flop(  
+\t.D      (stack_zero_flag),
+\t.Q      (shadow_zero_value),
+\t.C      (clk)) ;
+
+(* HBLKNM = ""kcpsm6_decode1"" *)
+FD shadow_zero_flag_flop(  
+\t.D      (shadow_zero_value),
+\t.Q      (shadow_zero_flag),
+\t.C      (clk)) ;
+
+(* HBLKNM = ""kcpsm6_stack_ram0"" *)
+FD shadow_bank_flop(  
+\t.D      (stack_bank),
+\t.Q      (shadow_bank),
+\t.C      (clk)) ;
+
+(* HBLKNM = ""kcpsm6_stack_ram0"" *)
+FD stack_bit_flop(  
+\t.D      (stack_bit),
+\t.Q      (special_bit),
+\t.C      (clk)) ;
+
+(* HBLKNM = ""kcpsm6_stack_ram0"" *)
+RAM32M #(
+\t.INIT_A\t(64\'h0000000000000000), 
+\t.INIT_B\t(64\'h0000000000000000), 
+\t.INIT_C (64\'h0000000000000000), 
+\t.INIT_D (64\'h0000000000000000)) 
+stack_ram_low ( 
+\t.DOA\t({stack_zero_flag, stack_carry_flag}), 
+\t.DOB\t({stack_bit, stack_bank}),
+\t.DOC    (stack_memory[1:0]), 
+\t.DOD    (stack_memory[3:2]),
+\t.ADDRA\t(stack_pointer[4:0]), 
+\t.ADDRB\t(stack_pointer[4:0]), 
+\t.ADDRC  (stack_pointer[4:0]), 
+\t.ADDRD  (stack_pointer[4:0]),
+\t.DIA\t({zero_flag, carry_flag}), 
+\t.DIB\t({run, bank}),
+\t.DIC    (pc[1:0]),
+\t.DID    (pc[3:2]),
+\t.WE \t(t_state[1]), 
+\t.WCLK\t(clk));
+
+(* HBLKNM = ""kcpsm6_stack_ram1"" *)
+RAM32M #(
+\t.INIT_A\t(64\'h0000000000000000), 
+\t.INIT_B\t(64\'h0000000000000000), 
+\t.INIT_C\t(64\'h0000000000000000), 
+\t.INIT_D\t(64\'h0000000000000000)) 
+stack_ram_high(    
+\t.DOA\t(stack_memory[5:4]), 
+\t.DOB\t(stack_memory[7:6]),
+\t.DOC   \t(stack_memory[9:8]),
+\t.DOD   \t(stack_memory[11:10]),
+\t.ADDRA \t(stack_pointer[4:0]), 
+\t.ADDRB \t(stack_pointer[4:0]), 
+\t.ADDRC  (stack_pointer[4:0]), 
+\t.ADDRD  (stack_pointer[4:0]),
+\t.DIA    (pc[5:4]),
+\t.DIB    (pc[7:6]),
+\t.DIC    (pc[9:8]),
+\t.DID    (pc[11:10]),
+\t.WE \t(t_state[1]),  
+\t.WCLK \t(clk));
+
+generate
+for (i = 0 ; i <= 4 ; i = i+1)
+begin : stack_loop
+
+parameter [7:0]\tid4 = 8\'h30 + i/4 ;
+
+if (i == 0) begin: lsb_stack
+
+(* HBLKNM = {""kcpsm6_stack"",id4} *)
+FDR pointer_flop(  
+\t.D      (stack_pointer_value[i]),
+\t.Q      (stack_pointer[i]),
+\t.R      (internal_reset),
+\t.C      (clk)) ;
+
+(* HBLKNM = {""kcpsm6_stack"",id4} *)
+LUT6_2 #(
+\t.INIT    (64\'h001529AAAAAAAAAA))
+stack_pointer_lut( 
+\t.I0     (stack_pointer[i]),
+\t.I1     (pop_stack),
+\t.I2     (push_stack),
+\t.I3     (t_state[1]),
+\t.I4     (t_state[2]),
+\t.I5     (1\'b1), 
+\t.O5     (feed_pointer_value[i]),
+\t.O6     (half_pointer_value[i]));
+
+(* HBLKNM = {""kcpsm6_stack"",id4} *)
+XORCY stack_xorcy( 
+\t.LI \t(half_pointer_value[i]),
+\t.CI \t(1\'b0),
+\t.O      (stack_pointer_value[i]));
+
+(* HBLKNM = {""kcpsm6_stack"",id4} *)
+MUXCY stack_muxcy( 
+\t.DI\t(feed_pointer_value[i]),
+\t.CI\t(1\'b0),
+\t.S \t(half_pointer_value[i]),
+\t.O      (stack_pointer_carry[i]));
+
+end //lsb_stack
+
+if (i > 0) begin: upper_stack
+
+(* HBLKNM = {""kcpsm6_stack"",id4} *)
+FDR pointer_flop(  
+\t.D      (stack_pointer_value[i]),
+\t.Q      (stack_pointer[i]),
+\t.R      (internal_reset),
+\t.C      (clk)) ;
+
+(* HBLKNM = {""kcpsm6_stack"",id4} *)
+LUT6_2 #(
+\t.INIT    (64\'h002A252AAAAAAAAA))
+stack_pointer_lut( 
+\t.I0     (stack_pointer[i]),
+\t.I1     (pop_stack),
+\t.I2     (push_stack),
+\t.I3     (t_state[1]),
+\t.I4     (t_state[2]),
+\t.I5     (1\'b1), 
+\t.O5     (feed_pointer_value[i]),
+\t.O6     (half_pointer_value[i]));
+
+(* HBLKNM = {""kcpsm6_stack"",id4} *)
+XORCY stack_xorcy( 
+\t.LI \t(half_pointer_value[i]),
+\t.CI \t(stack_pointer_carry[i-1]),
+\t.O      (stack_pointer_value[i]));
+
+(* HBLKNM = {""kcpsm6_stack"",id4} *)
+MUXCY stack_muxcy( 
+\t.DI \t(feed_pointer_value[i]),
+\t.CI \t(stack_pointer_carry[i-1]),
+\t.S \t(half_pointer_value[i]),
+\t.O      (stack_pointer_carry[i]));
+
+end //upper_stack
+
+end //stack_loop
+endgenerate
+
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+// 8-bit Data Path 
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+generate
+for (i = 0 ; i <= 7 ; i = i+1)
+begin : data_path_loop
+parameter [7:0]\tid1 = 8\'h30 + i ;
+parameter [7:0]\tid2 = 8\'h30 + i/2 ;
+parameter [7:0]\tid4 = 8\'h30 + i/4 ;
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+// Selection of second operand to ALU and port_id
+//
+// instruction[12]
+//           0  Register sY
+//           1  Constant kk 
+//
+//     4 x LUT6_2
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+//
+// 2 bits per LUT so only generate when \'i\' is even
+//
+if (i % 2 == 0) begin: output_data
+
+(* HBLKNM = ""kcpsm6_port_id"" *)
+LUT6_2 #(
+\t.INIT    (64\'hFF00F0F0CCCCAAAA))
+sy_kk_mux_lut( 
+\t.I0     (sy[i]),
+\t.I1     (instruction[i]),
+\t.I2     (sy[i+1]),
+\t.I3     (instruction[i+1]),
+\t.I4     (instruction[12]),
+\t.I5     (1\'b1),
+\t.O5     (sy_or_kk[i]),
+\t.O6     (sy_or_kk[i+1]));
+
+end //output_data
+
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+// Selection of out_port value
+//
+// instruction[13]
+//              0  Register sX
+//              1  Constant kk from instruction(11:4)
+//
+//     4 x LUT6_2
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+//
+// 2 bits per LUT so only generate when \'i\' is even
+//
+
+if (i % 2 == 0) begin: second_operand
+
+(* HBLKNM = ""kcpsm6_out_port"" *)
+LUT6_2 #(
+\t.INIT    (64\'hFF00F0F0CCCCAAAA))
+out_port_lut( 
+\t.I0     (sx[i]),
+\t.I1     (instruction[i+4]),
+\t.I2     (sx[i+1]),
+\t.I3     (instruction[i+5]),
+\t.I4     (instruction[13]),
+\t.I5     (1\'b1),
+\t.O5     (out_port[i]),
+\t.O6     (out_port[i+1]));
+
+end //second_operand;
+
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+// Arithmetic and Logical operations
+//
+// Definition of....
+//    ADD and SUB also used for ADDCY, SUBCY, COMPARE and COMPARECY.
+//    LOAD, AND, OR and XOR also used for LOAD*, RETURN&LOAD, TEST and TESTCY.
+//
+// arith_logical_sel [2] [1] [0]
+//                    0   0   0  - LOAD
+//                    0   0   1  - AND
+//                    0   1   0  - OR
+//                    0   1   1  - XOR
+//                    1   X   0  - SUB
+//                    1   X   1  - ADD
+//
+// Includes pipeline stage.
+//
+// 2 Slices
+//     8 x LUT6_2
+//     8 x MUXCY
+//     8 x XORCY
+//     8 x FD
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+
+(* HBLKNM = {""kcpsm6_add"",id4} *)
+LUT6_2 #(
+\t.INIT    (64\'h69696E8ACCCC0000))
+arith_logical_lut( 
+\t.I0     (sy_or_kk[i]),
+\t.I1     (sx[i]),
+\t.I2     (arith_logical_sel[0]),
+\t.I3     (arith_logical_sel[1]),
+\t.I4     (arith_logical_sel[2]),
+\t.I5     (1\'b1),
+\t.O5     (logical_carry_mask[i]),
+\t.O6     (half_arith_logical[i]));
+
+(* HBLKNM = {""kcpsm6_add"",id4} *)
+FD arith_logical_flop( 
+\t.D      (arith_logical_value[i]),
+\t.Q      (arith_logical_result[i]),
+\t.C      (clk)) ;
+
+if (i == 0) begin: lsb_arith_logical
+//
+// Carry input to first MUXCY and XORCY
+//
+(* HBLKNM = {""kcpsm6_add"",id4} *)
+MUXCY arith_logical_muxcy( 
+\t.DI \t(logical_carry_mask[i]),
+\t.CI \t(arith_carry_in),
+\t.S \t(half_arith_logical[i]),
+\t.O      (carry_arith_logical[i]));
+
+(* HBLKNM = {""kcpsm6_add"",id4} *)
+XORCY arith_logical_xorcy( 
+\t.LI \t(half_arith_logical[i]),
+\t.CI \t(arith_carry_in),
+\t.O      (arith_logical_value[i]));
+
+end //lsb_arith_logical
+
+if (i > 0) begin: upper_arith_logical
+//
+// Main carry chain  
+//
+(* HBLKNM = {""kcpsm6_add"",id4} *)
+MUXCY arith_logical_muxcy( 
+\t.DI \t(logical_carry_mask[i]),
+\t.CI \t(carry_arith_logical[i-1]),
+\t.S \t(half_arith_logical[i]),
+\t.O      (carry_arith_logical[i]));
+
+(* HBLKNM = {""kcpsm6_add"",id4} *)
+XORCY arith_logical_xorcy( 
+\t.LI \t(half_arith_logical[i]),
+\t.CI \t(carry_arith_logical[i-1]),
+\t.O      (arith_logical_value[i]));
+
+end //upper_arith_logical;
+
+
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+// Shift and Rotate operations
+//
+// Definition of SL0, SL1, SLX, SLA, RL, SR0, SR1, SRX, SRA, and RR 
+//
+// instruction [3] [2] [1] [0]
+//              0   1   1   0  - SL0
+//              0   1   1   1  - SL1
+//              0   1   0   0  - SLX         
+//              0   0   0   0  - SLA
+//              0   0   1   0  - RL
+//              1   1   1   0  - SR0
+//              1   1   1   1  - SR1
+//              1   0   1   0  - SRX
+//              1   0   0   0  - SRA
+//              1   1   0   0  - RR
+//
+// instruction[3] 
+//             0 - Left
+//             1 - Right
+//
+// instruction [2] [1]  Bit shifted in 
+//              0   0   Carry_flag
+//              0   1   sX[7]
+//              1   0   sX[0]
+//              1   1   instruction[0]
+//
+// Includes pipeline stage.
+//
+//     4 x LUT6_2
+//     1 x LUT6
+//     8 x FD
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+
+if (hwbuild[i] == 1\'b0) begin: low_hwbuild 
+//
+// Reset Flip-flop to form 1\'b0 for this bit of HWBUILD 
+//
+(* HBLKNM = ""kcpsm6_sandr"" *)
+FDR shift_rotate_flop( 
+\t.D      (shift_rotate_value[i]),
+\t.Q      (shift_rotate_result[i]),
+\t.R      (instruction[7]),
+\t.C      (clk)) ;
+           
+end // low_hwbuild;
+
+if (hwbuild[i] == 1\'b1) begin: high_hwbuild 
+//
+// Set Flip-flop to form 1\'b1 for this bit of HWBUILD 
+//
+(* HBLKNM = ""kcpsm6_sandr"" *)
+FDS shift_rotate_flop( 
+\t.D      (shift_rotate_value[i]),
+\t.Q      (shift_rotate_result[i]),
+\t.S \t(instruction[7]),
+\t.C      (clk)) ;
+
+end // high_hwbuild;
+
+if (i == 0) begin: lsb_shift_rotate
+//
+// Select bit to be shifted or rotated into result
+//
+(* HBLKNM = ""kcpsm6_decode1"" *)
+LUT6 #(
+\t.INIT    (64\'hBFBC8F8CB3B08380))
+shift_bit_lut( 
+\t.I0     (instruction[0]),
+\t.I1     (instruction[1]),
+\t.I2     (instruction[2]),
+\t.I3     (carry_flag),
+\t.I4     (sx[0]),
+\t.I5     (sx[7]),
+\t.O      (shift_in_bit));
+
+//
+// Define lower bits of result
+//
+(* HBLKNM = ""kcpsm6_sandr"" *)
+LUT6_2 #(
+\t.INIT    (64\'hFF00F0F0CCCCAAAA))
+shift_rotate_lut( 
+\t.I0     (shift_in_bit),
+\t.I1     (sx[i+1]),
+\t.I2     (sx[i]),
+\t.I3     (sx[i+2]),
+\t.I4     (instruction[3]),
+\t.I5     (1\'b1),
+\t.O5     (shift_rotate_value[i]),
+\t.O6     (shift_rotate_value[i+1]));
+
+end // lsb_shift_rotate;
+
+if (i == 2 || i == 4) begin: mid_shift_rotate
+//
+// Define middle bits of result
+//
+(* HBLKNM = ""kcpsm6_sandr"" *)
+LUT6_2 #(
+\t.INIT    (64\'hFF00F0F0CCCCAAAA))
+shift_rotate_lut( 
+\t.I0     (sx[i-1]),
+\t.I1     (sx[i+1]),
+\t.I2     (sx[i]),
+\t.I3     (sx[i+2]),
+\t.I4     (instruction[3]),
+\t.I5     (1\'b1),
+\t.O5     (shift_rotate_value[i]),
+\t.O6     (shift_rotate_value[i+1]));
+
+end // mid_shift_rotate;
+
+if (i == 6) begin: msb_shift_rotate
+//
+// Define upper bits of result
+//
+(* HBLKNM = ""kcpsm6_sandr"" *)
+LUT6_2 #(
+\t.INIT    (64\'hFF00F0F0CCCCAAAA))
+shift_rotate_lut( 
+\t.I0     (sx[i-1]),
+\t.I1     (sx[i+1]),
+\t.I2     (sx[i]),
+\t.I3     (shift_in_bit),
+\t.I4     (instruction[3]),
+\t.I5     (1\'b1),
+\t.O5     (shift_rotate_value[i]),
+\t.O6     (shift_rotate_value[i+1]));
+
+end // msb_shift_rotate;
+
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+// Multiplex outputs from ALU functions, scratch pad memory and input port.
+//
+// alu_mux_sel [1] [0]  
+//              0   0  Arithmetic and Logical Instructions
+//              0   1  Shift and Rotate Instructions
+//              1   0  Input Port
+//              1   1  Scratch Pad Memory
+//
+//     8 x LUT6
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+
+(* HBLKNM = {""kcpsm6_alu"",id4} *)
+LUT6 #(
+\t.INIT    (64\'hFF00F0F0CCCCAAAA))
+alu_mux_lut( 
+\t.I0     (arith_logical_result[i]),
+\t.I1     (shift_rotate_result[i]),
+\t.I2     (in_port[i]),
+\t.I3     (spm_data[i]),
+\t.I4     (alu_mux_sel[0]),
+\t.I5     (alu_mux_sel[1]),
+\t.O      (alu_result[i]));
+
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+// Scratchpad Memory with output register.
+//
+// The size of the scratch pad memory is defined by the \'scratch_pad_memory_size\' generic.
+// The default size is 64 bytes the same as KCPSM3 but this can be increased to 128 or 256 
+// bytes at an additional cost of 2 and 6 Slices.
+//
+//
+// 8 x RAM256X1S (256 bytes).
+// 8 x RAM128X1S (128 bytes).
+// 2 x RAM64M    (64 bytes).
+//
+// 8 x FD.
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+
+if (scratch_pad_memory_size == 64) begin : small_spm
+
+(* HBLKNM = {""kcpsm6_spm"",id4} *)
+FD spm_flop( 
+\t.D      (spm_ram_data[i]),
+\t.Q      (spm_data[i]),
+\t.C      (clk)) ;
+
+if (i == 0 || i == 4) begin: small_spm_ram
+
+RAM64M #( 
+\t.INIT_A\t(64\'h0000000000000000),
+\t.INIT_B\t(64\'h0000000000000000),
+\t.INIT_C\t(64\'h0000000000000000),
+\t.INIT_D\t(64\'h0000000000000000)) 
+spm_ram(   
+\t.DOA \t(spm_ram_data[i]),
+\t.DOB \t(spm_ram_data[i+1]),
+\t.DOC    (spm_ram_data[i+2]),
+\t.DOD    (spm_ram_data[i+3]),
+\t.ADDRA \t(sy_or_kk[5:0]),
+\t.ADDRB \t(sy_or_kk[5:0]),
+\t.ADDRC  (sy_or_kk[5:0]),
+\t.ADDRD  (sy_or_kk[5:0]),
+\t.DIA \t(sx[i]),
+\t.DIB \t(sx[i+1]),
+\t.DIC    (sx[i+2]),
+\t.DID    (sx[i+3]),
+\t.WE \t(spm_enable),
+\t.WCLK \t(clk));
+
+end // small_spm_ram;
+
+end // small_spm;
+
+if (scratch_pad_memory_size == 128) begin : medium_spm
+
+(* HBLKNM = {""kcpsm6_spm"",id2} *)
+RAM128X1S  #(
+\t.INIT\t(128\'h00000000000000000000000000000000))
+spm_ram(       
+\t.D      (sx[i]),
+\t.WE \t(spm_enable),
+\t.WCLK \t(clk),
+\t.A0 \t(sy_or_kk[0]),
+\t.A1 \t(sy_or_kk[1]),
+\t.A2 \t(sy_or_kk[2]),
+\t.A3 \t(sy_or_kk[3]),
+\t.A4 \t(sy_or_kk[4]),
+\t.A5 \t(sy_or_kk[5]),
+\t.A6 \t(sy_or_kk[6]),
+\t.O      (spm_ram_data[i]));
+
+(* HBLKNM = {""kcpsm6_spm"",id2} *)
+FD spm_flop( 
+\t.D      (spm_ram_data[i]),
+\t.Q      (spm_data[i]),
+\t.C      (clk)) ;
+
+end // medium_spm;
+
+if (scratch_pad_memory_size == 256) begin : large_spm
+
+(* HBLKNM = {""kcpsm6_spm"",id1} *)
+RAM256X1S #(
+\t.INIT\t(256\'h0000000000000000000000000000000000000000000000000000000000000000))
+spm_ram (       
+\t.D      (sx[i]),
+\t.WE \t(spm_enable),
+\t.WCLK \t(clk),
+\t.A \t(sy_or_kk),
+\t.O      (spm_ram_data[i]));
+
+(* HBLKNM = {""kcpsm6_spm"",id1} *)
+FD spm_flop( 
+\t.D      (spm_ram_data[i]),
+\t.Q      (spm_data[i]),
+\t.C      (clk)) ;
+
+end // large_spm;
+
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+
+end // data_path_loop;
+endgenerate
+
+
+
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+// Two Banks of 16 General Purpose Registers.
+//
+// sx_addr - Address for sX is formed by bank select and instruction[11:8]
+// sy_addr - Address for sY is formed by bank select and instruction[7:4]
+//
+// 2 Slices
+//     2 x RAM32M
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+
+(* HBLKNM = ""kcpsm6_reg0"" *)
+RAM32M #(
+\t.INIT_A\t(64\'h0000000000000000), 
+\t.INIT_B\t(64\'h0000000000000000), 
+\t.INIT_C (64\'h0000000000000000), 
+\t.INIT_D (64\'h0000000000000000)) 
+lower_reg_banks(    
+\t.DOA \t(sy[1:0]), 
+\t.DOB \t(sx[1:0]),
+\t.DOC    (sy[3:2]),
+\t.DOD    (sx[3:2]),
+\t.ADDRA \t(sy_addr), 
+\t.ADDRB \t(sx_addr), 
+\t.ADDRC  (sy_addr), 
+\t.ADDRD  (sx_addr), 
+\t.DIA \t(alu_result[1:0]),
+\t.DIB \t(alu_result[1:0]),
+\t.DIC    (alu_result[3:2]),
+\t.DID    (alu_result[3:2]),
+\t.WE \t(register_enable), 
+\t.WCLK\t(clk));
+
+(* HBLKNM = ""kcpsm6_reg1"" *)
+RAM32M #(
+\t.INIT_A\t(64\'h0000000000000000), 
+\t.INIT_B\t(64\'h0000000000000000), 
+\t.INIT_C (64\'h0000000000000000),  
+\t.INIT_D (64\'h0000000000000000)) 
+upper_reg_banks(    
+\t.DOA \t(sy[5:4]), 
+\t.DOB \t(sx[5:4]),
+\t.DOC    (sy[7:6]),
+\t.DOD    (sx[7:6]),
+\t.ADDRA \t(sy_addr),
+\t.ADDRB \t(sx_addr),
+\t.ADDRC  (sy_addr), 
+\t.ADDRD  (sx_addr), 
+\t.DIA \t(alu_result[5:4]),
+\t.DIB \t(alu_result[5:4]),
+\t.DIC    (alu_result[7:6]),
+\t.DID    (alu_result[7:6]),
+\t.WE \t(register_enable), 
+\t.WCLK\t(clk));
+
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+// Connections to KCPSM6 outputs.
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+
+
+assign address = pc;
+assign bram_enable = t_state[2];
+
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+// Connections KCPSM6 Outputs.
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+
+assign port_id = sy_or_kk;
+
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+// End of description for kcpsm6 macro.
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+// *****************************************************
+// * Code for simulation purposes only after this line *
+// *****************************************************
+//
+//
+// Disassemble the instruction codes to form a text string for display.
+// Determine status of reset and flags and present in the form of a text string.
+// Provide signals to simulate the contents of each register and scratch pad memory 
+// location.
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+//All of this section is ignored during synthesis.
+//synthesis translate_off
+// 
+//
+// Variables for contents of each register in each bank
+//
+reg\t[7:0]\t\tbank_a_s0 ;
+reg\t[7:0]\t\tbank_a_s1 ;
+reg\t[7:0]\t\tbank_a_s2 ;
+reg\t[7:0]\t\tbank_a_s3 ;
+reg\t[7:0]\t\tbank_a_s4 ;
+reg\t[7:0]\t\tbank_a_s5 ;
+reg\t[7:0]\t\tbank_a_s6 ;
+reg\t[7:0]\t\tbank_a_s7 ;
+reg\t[7:0]\t\tbank_a_s8 ;
+reg\t[7:0]\t\tbank_a_s9 ;
+reg\t[7:0]\t\tbank_a_sa ;
+reg\t[7:0]\t\tbank_a_sb ;
+reg\t[7:0]\t\tbank_a_sc ;
+reg\t[7:0]\t\tbank_a_sd ;
+reg\t[7:0]\t\tbank_a_se ;
+reg\t[7:0]\t\tbank_a_sf ;
+reg\t[7:0]\t\tbank_b_s0 ;
+reg\t[7:0]\t\tbank_b_s1 ;
+reg\t[7:0]\t\tbank_b_s2 ;
+reg\t[7:0]\t\tbank_b_s3 ;
+reg\t[7:0]\t\tbank_b_s4 ;
+reg\t[7:0]\t\tbank_b_s5 ;
+reg\t[7:0]\t\tbank_b_s6 ;
+reg\t[7:0]\t\tbank_b_s7 ;
+reg\t[7:0]\t\tbank_b_s8 ;
+reg\t[7:0]\t\tbank_b_s9 ;
+reg\t[7:0]\t\tbank_b_sa ;
+reg\t[7:0]\t\tbank_b_sb ;
+reg\t[7:0]\t\tbank_b_sc ;
+reg\t[7:0]\t\tbank_b_sd ;
+reg\t[7:0]\t\tbank_b_se ;
+reg\t[7:0]\t\tbank_b_sf ;
+//
+initial begin
+bank_a_s0 = 8\'h00 ;
+bank_a_s1 = 8\'h00 ;
+bank_a_s2 = 8\'h00 ;
+bank_a_s3 = 8\'h00 ;
+bank_a_s4 = 8\'h00 ;
+bank_a_s5 = 8\'h00 ;
+bank_a_s6 = 8\'h00 ;
+bank_a_s7 = 8\'h00 ;
+bank_a_s8 = 8\'h00 ;
+bank_a_s9 = 8\'h00 ;
+bank_a_sa = 8\'h00 ;
+bank_a_sb = 8\'h00 ;
+bank_a_sc = 8\'h00 ;
+bank_a_sd = 8\'h00 ;
+bank_a_se = 8\'h00 ;
+bank_a_sf = 8\'h00 ;
+bank_b_s0 = 8\'h00 ;
+bank_b_s1 = 8\'h00 ;
+bank_b_s2 = 8\'h00 ;
+bank_b_s3 = 8\'h00 ;
+bank_b_s4 = 8\'h00 ;
+bank_b_s5 = 8\'h00 ;
+bank_b_s6 = 8\'h00 ;
+bank_b_s7 = 8\'h00 ;
+bank_b_s8 = 8\'h00 ;
+bank_b_s9 = 8\'h00 ;
+bank_b_sa = 8\'h00 ;
+bank_b_sb = 8\'h00 ;
+bank_b_sc = 8\'h00 ;
+bank_b_sd = 8\'h00 ;
+bank_b_se = 8\'h00 ;
+bank_b_sf = 8\'h00 ;  
+end
+//
+// Temporary variables for instruction decoding
+//
+wire\t[1:16] \t\tsx_decode ; \t//sX register specification
+wire \t[1:16]  \tsy_decode ; \t//sY register specification
+wire \t[1:16]\t\tkk_decode ; \t//constant value specification
+wire \t[1:24]\t\taaa_decode ; \t//address specification
+wire\t\t\tclk_del ;\t// Delayed clock for simulation
+//
+/////////////////////////////////////////////////////////////////////////////////////////
+//
+// Function to convert 4-bit binary nibble to hexadecimal character
+//
+/////////////////////////////////////////////////////////////////////////////////////////
+//
+ function [1:8] hexcharacter ;
+ input [3:0] nibble ;
+ begin
+ case (nibble)
+ 4\'b0000 : hexcharacter = ""0"" ;
+ 4\'b0001 : hexcharacter = ""1"" ;
+ 4\'b0010 : hexcharacter = ""2"" ;
+ 4\'b0011 : hexcharacter = ""3"" ;
+ 4\'b0100 : hexcharacter = ""4"" ;
+ 4\'b0101 : hexcharacter = ""5"" ;
+ 4\'b0110 : hexcharacter = ""6"" ;
+ 4\'b0111 : hexcharacter = ""7"" ;
+ 4\'b1000 : hexcharacter = ""8"" ;
+ 4\'b1001 : hexcharacter = ""9"" ;
+ 4\'b1010 : hexcharacter = ""A"" ;
+ 4\'b1011 : hexcharacter = ""B"" ;
+ 4\'b1100 : hexcharacter = ""C"" ;
+ 4\'b1101 : hexcharacter = ""D"" ;
+ 4\'b1110 : hexcharacter = ""E"" ;
+ 4\'b1111 : hexcharacter = ""F"" ;
+ endcase
+ end
+ endfunction
+//
+/////////////////////////////////////////////////////////////////////////////////////////
+//
+// decode first register sX
+
+assign sx_decode[1:8]  = ""s"";
+assign sx_decode[9:16] = hexcharacter(instruction[11:8]);             
+
+// decode second register sY
+assign sy_decode[1:8]  = ""s"";
+assign sy_decode[9:16] = hexcharacter(instruction[7:4]);  
+
+// decode constant value
+assign kk_decode[1:8]  = hexcharacter(instruction[7:4]);
+assign kk_decode[9:16] = hexcharacter(instruction[3:0]);
+
+// address value
+assign aaa_decode[1:8]   = hexcharacter(instruction[11:8]);
+assign aaa_decode[9:16]  = hexcharacter(instruction[7:4]);
+assign aaa_decode[17:24] = hexcharacter(instruction[3:0]);
+
+assign #200 clk_del = clk ;
+// decode instruction
+//always @ (clk or instruction or carry_flag or zero_flag or bank or interrupt_enable) 
+always @ (posedge clk_del) 
+begin : simulation
+case (instruction[17:12])
+\t6\'b000000\t: kcpsm6_opcode <= {""LOAD "", sx_decode, "", "", sy_decode, ""        ""} ;
+\t6\'b000001\t: kcpsm6_opcode <= {""LOAD "", sx_decode, "", "", kk_decode, ""        ""} ;
+\t6\'b010110\t: kcpsm6_opcode <= {""STAR "", sx_decode, "", "", sy_decode, ""        ""} ;
+\t6\'b010111\t: kcpsm6_opcode <= {""STAR "", sx_decode, "", "", kk_decode, ""        ""} ;
+\t6\'b000010\t: kcpsm6_opcode <= {""AND "", sx_decode, "", "", sy_decode, ""         ""} ;
+\t6\'b000011\t: kcpsm6_opcode <= {""AND "", sx_decode, "", "", kk_decode, ""         ""} ;
+\t6\'b000100\t: kcpsm6_opcode <= {""OR "", sx_decode, "", "", sy_decode, ""          ""} ;
+\t6\'b000101\t: kcpsm6_opcode <= {""OR "", sx_decode, "", "", kk_decode, ""          ""} ;
+\t6\'b000110\t: kcpsm6_opcode <= {""XOR "", sx_decode, "", "", sy_decode, ""         ""} ;
+\t6\'b000111\t: kcpsm6_opcode <= {""XOR "", sx_decode, "", "", kk_decode, ""         ""} ;
+\t6\'b001100\t: kcpsm6_opcode <= {""TEST "", sx_decode, "", "", sy_decode, ""        ""} ;
+\t6\'b001101\t: kcpsm6_opcode <= {""TEST "", sx_decode, "", "", kk_decode, ""        ""} ;
+\t6\'b001110\t: kcpsm6_opcode <= {""TESTCY "", sx_decode, "", "", sy_decode, ""      ""} ;
+\t6\'b001111\t: kcpsm6_opcode <= {""TESTCY "", sx_decode, "", "", kk_decode, ""      ""} ;
+\t6\'b010000\t: kcpsm6_opcode <= {""ADD "", sx_decode, "", "", sy_decode, ""         ""} ;
+\t6\'b010001\t: kcpsm6_opcode <= {""ADD "", sx_decode, "", "", kk_decode, ""         ""} ;
+\t6\'b010010\t: kcpsm6_opcode <= {""ADDCY "", sx_decode, "", "", sy_decode, ""       ""} ;
+\t6\'b010011\t: kcpsm6_opcode <= {""ADDCY "", sx_decode, "", "", kk_decode, ""       ""} ;
+\t6\'b011000\t: kcpsm6_opcode <= {""SUB "", sx_decode, "", "", sy_decode, ""         ""} ;
+\t6\'b011001\t: kcpsm6_opcode <= {""SUB "", sx_decode, "", "", kk_decode, ""         ""} ;
+\t6\'b011010\t: kcpsm6_opcode <= {""SUBCY "", sx_decode, "", "", sy_decode, ""       ""} ;
+\t6\'b011011\t: kcpsm6_opcode <= {""SUBCY "", sx_decode, "", "", kk_decode, ""       ""} ;
+\t6\'b011100\t: kcpsm6_opcode <= {""COMPARE "", sx_decode, "", "", sy_decode, ""     ""} ;
+\t6\'b011101\t: kcpsm6_opcode <= {""COMPARE "", sx_decode, "", "", kk_decode, ""     ""} ;
+\t6\'b011110\t: kcpsm6_opcode <= {""COMPARECY "", sx_decode, "", "", sy_decode, ""   ""} ;
+\t6\'b011111\t: kcpsm6_opcode <= {""COMPARECY "", sx_decode, "", "", kk_decode, ""   ""} ;
+\t6\'b010100\t: begin
+\t\t\t\tif (instruction[7] == 1\'b1) 
+\t\t\t\t  \tkcpsm6_opcode <= {""HWBUILD "", sx_decode, ""         ""} ;
+\t\t\t\telse
+\t\t\t\t  \tcase (instruction[3:0])
+\t\t\t\t    \t\t4\'b0110\t: kcpsm6_opcode <= {""SL0 "", sx_decode, ""             ""} ;
+\t\t\t\t    \t\t4\'b0111\t: kcpsm6_opcode <= {""SL1 "", sx_decode, ""             ""} ;
+\t\t\t\t    \t\t4\'b0100\t: kcpsm6_opcode <= {""SLX "", sx_decode, ""             ""} ;
+\t\t\t\t    \t\t4\'b0000\t: kcpsm6_opcode <= {""SLA "", sx_decode, ""             ""} ;
+\t\t\t\t    \t\t4\'b0010\t: kcpsm6_opcode <= {""RL "", sx_decode, ""              ""} ;
+\t\t\t\t    \t\t4\'b1110\t: kcpsm6_opcode <= {""SR0 "", sx_decode, ""             ""} ;
+\t\t\t\t    \t\t4\'b1111\t: kcpsm6_opcode <= {""SR1 "", sx_decode, ""             ""} ;
+\t\t\t\t    \t\t4\'b1010\t: kcpsm6_opcode <= {""SRX "", sx_decode, ""             ""} ;
+\t\t\t\t    \t\t4\'b1000\t: kcpsm6_opcode <= {""SRA "", sx_decode, ""             ""} ;
+\t\t\t\t    \t\t4\'b1100\t: kcpsm6_opcode <= {""RR "", sx_decode, ""              ""} ;
+\t\t\t\t    \t\tdefault\t: kcpsm6_opcode <= ""Invalid Instruction"";
+\t\t\t\t  \tendcase
+\t\t\tend
+\t6\'b101100 \t: kcpsm6_opcode <= {""OUTPUT "", sx_decode, "", ("", sy_decode, "")    ""} ;
+\t6\'b101101 \t: kcpsm6_opcode <= {""OUTPUT "", sx_decode, "", "", kk_decode, ""      ""} ;
+\t6\'b101011 \t: kcpsm6_opcode <= {""OUTPUTK "", aaa_decode[1:16], "", "", aaa_decode[17:24], ""      "" };
+\t6\'b001000 \t: kcpsm6_opcode <= {""INPUT "", sx_decode, "", ("", sy_decode, "")     ""} ;
+\t6\'b001001 \t: kcpsm6_opcode <= {""INPUT "", sx_decode, "", "", kk_decode, ""       ""} ;
+\t6\'b101110 \t: kcpsm6_opcode <= {""STORE "", sx_decode, "", ("", sy_decode, "")     ""} ;
+\t6\'b101111 \t: kcpsm6_opcode <= {""STORE "", sx_decode, "", "", kk_decode, ""       ""} ;
+\t6\'b001010 \t: kcpsm6_opcode <= {""FETCH "", sx_decode, "", ("", sy_decode, "")     ""} ;
+\t6\'b001011 \t: kcpsm6_opcode <= {""FETCH "", sx_decode, "", "", kk_decode, ""       ""} ;
+\t6\'b100010 \t: kcpsm6_opcode <= {""JUMP "", aaa_decode, ""           ""} ;
+\t6\'b110010 \t: kcpsm6_opcode <= {""JUMP Z, "", aaa_decode, ""        ""} ;
+\t6\'b110110 \t: kcpsm6_opcode <= {""JUMP NZ, "", aaa_decode, ""       ""} ;
+\t6\'b111010 \t: kcpsm6_opcode <= {""JUMP C, "", aaa_decode, ""        ""} ;
+\t6\'b111110 \t: kcpsm6_opcode <= {""JUMP NC, "", aaa_decode, ""       ""} ;
+\t6\'b100110 \t: kcpsm6_opcode <= {""JUMP@ ("", sx_decode, "", "", sy_decode, "")     ""} ;
+\t6\'b100000 \t: kcpsm6_opcode <= {""CALL "", aaa_decode, ""           ""} ;
+\t6\'b110000 \t: kcpsm6_opcode <= {""CALL Z, "", aaa_decode, ""        ""} ;
+\t6\'b110100 \t: kcpsm6_opcode <= {""CALL NZ, "", aaa_decode, ""       ""} ;
+\t6\'b111000 \t: kcpsm6_opcode <= {""CALL C, "", aaa_decode, ""        ""} ;
+\t6\'b111100 \t: kcpsm6_opcode <= {""CALL NC, "", aaa_decode, ""       ""} ;
+\t6\'b100100 \t: kcpsm6_opcode <= {""CALL@ ("", sx_decode, "", "", sy_decode, "")     ""} ;
+\t6\'b100101 \t: kcpsm6_opcode <= {""RETURN             ""} ;
+\t6\'b110001 \t: kcpsm6_opcode <= {""RETURN Z           ""} ;
+\t6\'b110101 \t: kcpsm6_opcode <= {""RETURN NZ          ""} ;
+\t6\'b111001 \t: kcpsm6_opcode <= {""RETURN C           ""} ;
+\t6\'b111101 \t: kcpsm6_opcode <= {""RETURN NC          ""} ;
+\t6\'b100001 \t: kcpsm6_opcode <= {""LOAD&RETURN "", sx_decode, "", "", kk_decode, "" ""} ;
+\t6\'b101001\t: begin
+\t\t\t\tcase (instruction[0])
+\t\t\t\t  1\'b0    : kcpsm6_opcode <= ""RETURNI DISABLE    "";
+\t\t\t\t  1\'b1    : kcpsm6_opcode <= ""RETURNI ENABLE     "";
+\t\t\t\t  default : kcpsm6_opcode <= ""Invalid Instruction"";
+\t\t\t\tendcase
+\t\t\tend
+\t6\'b101000\t: begin
+\t\t\t\tcase (instruction[0])
+\t\t\t\t  1\'b0    : kcpsm6_opcode <= ""DISABLE INTERRUPT  "";
+\t\t\t\t  1\'b1    : kcpsm6_opcode <= ""ENABLE INTERRUPT   "";
+\t\t\t\t  default : kcpsm6_opcode <= ""Invalid Instruction"";
+\t\t\t\tendcase
+\t\t\tend
+\t6\'b110111\t: begin
+\t\t\t\tcase (instruction[0])
+\t\t\t\t  1\'b0 \t  : kcpsm6_opcode <= ""REGBANK A          "";
+\t\t\t\t  1\'b1 \t  : kcpsm6_opcode <= ""REGBANK B          "";
+\t\t\t\t  default : kcpsm6_opcode <= ""Invalid Instruction"";
+\t\t\t\tendcase
+\t\t\tend
+\tdefault \t: kcpsm6_opcode <= ""Invalid Instruction"";
+endcase
+
+
+
+// Flag status information
+
+if (zero_flag == 1\'b0) 
+  \tkcpsm6_status[17:40] <= ""NZ,"";
+else
+  \tkcpsm6_status[17:40] <= "" Z,"";
+
+
+if (carry_flag == 1\'b0) 
+  \tkcpsm6_status[41:64] <= ""NC,"";
+else
+  \tkcpsm6_status[41:64] <= "" C,"";
+
+
+if (interrupt_enable == 1\'b0) 
+   \tkcpsm6_status[65:80] <= ""ID"";
+else
+  \tkcpsm6_status[65:80] <= ""IE"";
+
+
+// Operational status 
+
+if (clk) begin
+if (internal_reset == 1\'b1)
+    \tkcpsm6_status[81 : 128] <= "",Reset"";
+else
+    \tif (sync_sleep == 1\'b1 && t_state == 2\'b00) 
+      \t\tkcpsm6_status[81 : 128] <= "",Sleep"";
+     \telse
+      \t\tkcpsm6_status[81 : 128] <= ""      "";
+end
+
+
+// Simulation of register contents
+if (clk) begin
+\tif (register_enable == 1\'b1) begin
+\t\tcase (sx_addr)
+\t\t\t5\'b00000\t: bank_a_s0 <= alu_result ;
+\t\t\t5\'b00001\t: bank_a_s1 <= alu_result ;
+\t\t\t5\'b00010\t: bank_a_s2 <= alu_result ;
+\t\t\t5\'b00011\t: bank_a_s3 <= alu_result ;
+\t\t\t5\'b00100\t: bank_a_s4 <= alu_result ;
+\t\t\t5\'b00101\t: bank_a_s5 <= alu_result ;
+\t\t\t5\'b00110\t: bank_a_s6 <= alu_result ;
+\t\t\t5\'b00111\t: bank_a_s7 <= alu_result ;
+\t\t\t5\'b01000\t: bank_a_s8 <= alu_result ;
+\t\t\t5\'b01001\t: bank_a_s9 <= alu_result ;
+\t\t\t5\'b01010\t: bank_a_sa <= alu_result ;
+\t\t\t5\'b01011\t: bank_a_sb <= alu_result ;
+\t\t\t5\'b01100\t: bank_a_sc <= alu_result ;
+\t\t\t5\'b01101\t: bank_a_sd <= alu_result ;
+\t\t\t5\'b01110\t: bank_a_se <= alu_result ;
+\t\t\t5\'b01111\t: bank_a_sf <= alu_result ;
+\t\t\t5\'b10000\t: bank_b_s0 <= alu_result ;
+\t\t\t5\'b10001\t: bank_b_s1 <= alu_result ;
+\t\t\t5\'b10010\t: bank_b_s2 <= alu_result ;
+\t\t\t5\'b10011\t: bank_b_s3 <= alu_result ;
+\t\t\t5\'b10100\t: bank_b_s4 <= alu_result ;
+\t\t\t5\'b10101\t: bank_b_s5 <= alu_result ;
+\t\t\t5\'b10110\t: bank_b_s6 <= alu_result ;
+\t\t\t5\'b10111\t: bank_b_s7 <= alu_result ;
+\t\t\t5\'b11000\t: bank_b_s8 <= alu_result ;
+\t\t\t5\'b11001\t: bank_b_s9 <= alu_result ;
+\t\t\t5\'b11010\t: bank_b_sa <= alu_result ;
+\t\t\t5\'b11011\t: bank_b_sb <= alu_result ;
+\t\t\t5\'b11100\t: bank_b_sc <= alu_result ;
+\t\t\t5\'b11101\t: bank_b_sd <= alu_result ;
+\t\t\t5\'b11110\t: bank_b_se <= alu_result ;
+\t\t\t5\'b11111\t: bank_b_sf <= alu_result ;
+\t\tendcase
+\tend
+
+//simulation of scratch pad memory contents
+if (spm_enable == 1\'b1) begin
+\tcase (sy_or_kk)
+\t\t8\'b00000000\t: sim_spm00 <= sx;
+\t\t8\'b00000001\t: sim_spm01 <= sx;
+\t\t8\'b00000010\t: sim_spm02 <= sx;
+\t\t8\'b00000011\t: sim_spm03 <= sx;
+\t\t8\'b00000100\t: sim_spm04 <= sx;
+\t\t8\'b00000101\t: sim_spm05 <= sx;
+\t\t8\'b00000110\t: sim_spm06 <= sx;
+\t\t8\'b00000111\t: sim_spm07 <= sx;
+\t\t8\'b00001000\t: sim_spm08 <= sx;
+\t\t8\'b00001001\t: sim_spm09 <= sx;
+\t\t8\'b00001010\t: sim_spm0A <= sx;
+\t\t8\'b00001011\t: sim_spm0B <= sx;
+\t\t8\'b00001100\t: sim_spm0C <= sx;
+\t\t8\'b00001101\t: sim_spm0D <= sx;
+\t\t8\'b00001110\t: sim_spm0E <= sx;
+\t\t8\'b00001111\t: sim_spm0F <= sx;
+\t\t8\'b00010000\t: sim_spm10 <= sx;
+\t\t8\'b00010001\t: sim_spm11 <= sx;
+\t\t8\'b00010010\t: sim_spm12 <= sx;
+\t\t8\'b00010011\t: sim_spm13 <= sx;
+\t\t8\'b00010100\t: sim_spm14 <= sx;
+\t\t8\'b00010101\t: sim_spm15 <= sx;
+\t\t8\'b00010110\t: sim_spm16 <= sx;
+\t\t8\'b00010111\t: sim_spm17 <= sx;
+\t\t8\'b00011000\t: sim_spm18 <= sx;
+\t\t8\'b00011001\t: sim_spm19 <= sx;
+\t\t8\'b00011010\t: sim_spm1A <= sx;
+\t\t8\'b00011011\t: sim_spm1B <= sx;
+\t\t8\'b00011100\t: sim_spm1C <= sx;
+\t\t8\'b00011101\t: sim_spm1D <= sx;
+\t\t8\'b00011110\t: sim_spm1E <= sx;
+\t\t8\'b00011111\t: sim_spm1F <= sx;
+\t\t8\'b00100000\t: sim_spm20 <= sx;
+\t\t8\'b00100001\t: sim_spm21 <= sx;
+\t\t8\'b00100010\t: sim_spm22 <= sx;
+\t\t8\'b00100011\t: sim_spm23 <= sx;
+\t\t8\'b00100100\t: sim_spm24 <= sx;
+\t\t8\'b00100101\t: sim_spm25 <= sx;
+\t\t8\'b00100110\t: sim_spm26 <= sx;
+\t\t8\'b00100111\t: sim_spm27 <= sx;
+\t\t8\'b00101000\t: sim_spm28 <= sx;
+\t\t8\'b00101001\t: sim_spm29 <= sx;
+\t\t8\'b00101010\t: sim_spm2A <= sx;
+\t\t8\'b00101011\t: sim_spm2B <= sx;
+\t\t8\'b00101100\t: sim_spm2C <= sx;
+\t\t8\'b00101101\t: sim_spm2D <= sx;
+\t\t8\'b00101110\t: sim_spm2E <= sx;
+\t\t8\'b00101111\t: sim_spm2F <= sx;
+\t\t8\'b00110000\t: sim_spm30 <= sx;
+\t\t8\'b00110001\t: sim_spm31 <= sx;
+\t\t8\'b00110010\t: sim_spm32 <= sx;
+\t\t8\'b00110011\t: sim_spm33 <= sx;
+\t\t8\'b00110100\t: sim_spm34 <= sx;
+\t\t8\'b00110101\t: sim_spm35 <= sx;
+\t\t8\'b00110110\t: sim_spm36 <= sx;
+\t\t8\'b00110111\t: sim_spm37 <= sx;
+\t\t8\'b00111000\t: sim_spm38 <= sx;
+\t\t8\'b00111001\t: sim_spm39 <= sx;
+\t\t8\'b00111010\t: sim_spm3A <= sx;
+\t\t8\'b00111011\t: sim_spm3B <= sx;
+\t\t8\'b00111100\t: sim_spm3C <= sx;
+\t\t8\'b00111101\t: sim_spm3D <= sx;
+\t\t8\'b00111110\t: sim_spm3E <= sx;
+\t\t8\'b00111111\t: sim_spm3F <= sx;
+\t\t8\'b01000000\t: sim_spm40 <= sx;
+\t\t8\'b01000001\t: sim_spm41 <= sx;
+\t\t8\'b01000010\t: sim_spm42 <= sx;
+\t\t8\'b01000011\t: sim_spm43 <= sx;
+\t\t8\'b01000100\t: sim_spm44 <= sx;
+\t\t8\'b01000101\t: sim_spm45 <= sx;
+\t\t8\'b01000110\t: sim_spm46 <= sx;
+\t\t8\'b01000111\t: sim_spm47 <= sx;
+\t\t8\'b01001000\t: sim_spm48 <= sx;
+\t\t8\'b01001001\t: sim_spm49 <= sx;
+\t\t8\'b01001010\t: sim_spm4A <= sx;
+\t\t8\'b01001011\t: sim_spm4B <= sx;
+\t\t8\'b01001100\t: sim_spm4C <= sx;
+\t\t8\'b01001101\t: sim_spm4D <= sx;
+\t\t8\'b01001110\t: sim_spm4E <= sx;
+\t\t8\'b01001111\t: sim_spm4F <= sx;
+\t\t8\'b01010000\t: sim_spm50 <= sx;
+\t\t8\'b01010001\t: sim_spm51 <= sx;
+\t\t8\'b01010010\t: sim_spm52 <= sx;
+\t\t8\'b01010011\t: sim_spm53 <= sx;
+\t\t8\'b01010100\t: sim_spm54 <= sx;
+\t\t8\'b01010101\t: sim_spm55 <= sx;
+\t\t8\'b01010110\t: sim_spm56 <= sx;
+\t\t8\'b01010111\t: sim_spm57 <= sx;
+\t\t8\'b01011000\t: sim_spm58 <= sx;
+\t\t8\'b01011001\t: sim_spm59 <= sx;
+\t\t8\'b01011010\t: sim_spm5A <= sx;
+\t\t8\'b01011011\t: sim_spm5B <= sx;
+\t\t8\'b01011100\t: sim_spm5C <= sx;
+\t\t8\'b01011101\t: sim_spm5D <= sx;
+\t\t8\'b01011110\t: sim_spm5E <= sx;
+\t\t8\'b01011111\t: sim_spm5F <= sx;
+\t\t8\'b01100000\t: sim_spm60 <= sx;
+\t\t8\'b01100001\t: sim_spm61 <= sx;
+\t\t8\'b01100010\t: sim_spm62 <= sx;
+\t\t8\'b01100011\t: sim_spm63 <= sx;
+\t\t8\'b01100100\t: sim_spm64 <= sx;
+\t\t8\'b01100101\t: sim_spm65 <= sx;
+\t\t8\'b01100110\t: sim_spm66 <= sx;
+\t\t8\'b01100111\t: sim_spm67 <= sx;
+\t\t8\'b01101000\t: sim_spm68 <= sx;
+\t\t8\'b01101001\t: sim_spm69 <= sx;
+\t\t8\'b01101010\t: sim_spm6A <= sx;
+\t\t8\'b01101011\t: sim_spm6B <= sx;
+\t\t8\'b01101100\t: sim_spm6C <= sx;
+\t\t8\'b01101101\t: sim_spm6D <= sx;
+\t\t8\'b01101110\t: sim_spm6E <= sx;
+\t\t8\'b01101111\t: sim_spm6F <= sx;
+\t\t8\'b01110000\t: sim_spm70 <= sx;
+\t\t8\'b01110001\t: sim_spm71 <= sx;
+\t\t8\'b01110010\t: sim_spm72 <= sx;
+\t\t8\'b01110011\t: sim_spm73 <= sx;
+\t\t8\'b01110100\t: sim_spm74 <= sx;
+\t\t8\'b01110101\t: sim_spm75 <= sx;
+\t\t8\'b01110110\t: sim_spm76 <= sx;
+\t\t8\'b01110111\t: sim_spm77 <= sx;
+\t\t8\'b01111000\t: sim_spm78 <= sx;
+\t\t8\'b01111001\t: sim_spm79 <= sx;
+\t\t8\'b01111010\t: sim_spm7A <= sx;
+\t\t8\'b01111011\t: sim_spm7B <= sx;
+\t\t8\'b01111100\t: sim_spm7C <= sx;
+\t\t8\'b01111101\t: sim_spm7D <= sx;
+\t\t8\'b01111110\t: sim_spm7E <= sx;
+\t\t8\'b01111111\t: sim_spm7F <= sx;
+\t\t8\'b10000000\t: sim_spm80 <= sx;
+\t\t8\'b10000001\t: sim_spm81 <= sx;
+\t\t8\'b10000010\t: sim_spm82 <= sx;
+\t\t8\'b10000011\t: sim_spm83 <= sx;
+\t\t8\'b10000100\t: sim_spm84 <= sx;
+\t\t8\'b10000101\t: sim_spm85 <= sx;
+\t\t8\'b10000110\t: sim_spm86 <= sx;
+\t\t8\'b10000111\t: sim_spm87 <= sx;
+\t\t8\'b10001000\t: sim_spm88 <= sx;
+\t\t8\'b10001001\t: sim_spm89 <= sx;
+\t\t8\'b10001010\t: sim_spm8A <= sx;
+\t\t8\'b10001011\t: sim_spm8B <= sx;
+\t\t8\'b10001100\t: sim_spm8C <= sx;
+\t\t8\'b10001101\t: sim_spm8D <= sx;
+\t\t8\'b10001110\t: sim_spm8E <= sx;
+\t\t8\'b10001111\t: sim_spm8F <= sx;
+\t\t8\'b10010000\t: sim_spm90 <= sx;
+\t\t8\'b10010001\t: sim_spm91 <= sx;
+\t\t8\'b10010010\t: sim_spm92 <= sx;
+\t\t8\'b10010011\t: sim_spm93 <= sx;
+\t\t8\'b10010100\t: sim_spm94 <= sx;
+\t\t8\'b10010101\t: sim_spm95 <= sx;
+\t\t8\'b10010110\t: sim_spm96 <= sx;
+\t\t8\'b10010111\t: sim_spm97 <= sx;
+\t\t8\'b10011000\t: sim_spm98 <= sx;
+\t\t8\'b10011001\t: sim_spm99 <= sx;
+\t\t8\'b10011010\t: sim_spm9A <= sx;
+\t\t8\'b10011011\t: sim_spm9B <= sx;
+\t\t8\'b10011100\t: sim_spm9C <= sx;
+\t\t8\'b10011101\t: sim_spm9D <= sx;
+\t\t8\'b10011110\t: sim_spm9E <= sx;
+\t\t8\'b10011111\t: sim_spm9F <= sx;
+\t\t8\'b10100000\t: sim_spmA0 <= sx;
+\t\t8\'b10100001\t: sim_spmA1 <= sx;
+\t\t8\'b10100010\t: sim_spmA2 <= sx;
+\t\t8\'b10100011\t: sim_spmA3 <= sx;
+\t\t8\'b10100100\t: sim_spmA4 <= sx;
+\t\t8\'b10100101\t: sim_spmA5 <= sx;
+\t\t8\'b10100110\t: sim_spmA6 <= sx;
+\t\t8\'b10100111\t: sim_spmA7 <= sx;
+\t\t8\'b10101000\t: sim_spmA8 <= sx;
+\t\t8\'b10101001\t: sim_spmA9 <= sx;
+\t\t8\'b10101010\t: sim_spmAA <= sx;
+\t\t8\'b10101011\t: sim_spmAB <= sx;
+\t\t8\'b10101100\t: sim_spmAC <= sx;
+\t\t8\'b10101101\t: sim_spmAD <= sx;
+\t\t8\'b10101110\t: sim_spmAE <= sx;
+\t\t8\'b10101111\t: sim_spmAF <= sx;
+\t\t8\'b10110000\t: sim_spmB0 <= sx;
+\t\t8\'b10110001\t: sim_spmB1 <= sx;
+\t\t8\'b10110010\t: sim_spmB2 <= sx;
+\t\t8\'b10110011\t: sim_spmB3 <= sx;
+\t\t8\'b10110100\t: sim_spmB4 <= sx;
+\t\t8\'b10110101\t: sim_spmB5 <= sx;
+\t\t8\'b10110110\t: sim_spmB6 <= sx;
+\t\t8\'b10110111\t: sim_spmB7 <= sx;
+\t\t8\'b10111000\t: sim_spmB8 <= sx;
+\t\t8\'b10111001\t: sim_spmB9 <= sx;
+\t\t8\'b10111010\t: sim_spmBA <= sx;
+\t\t8\'b10111011\t: sim_spmBB <= sx;
+\t\t8\'b10111100\t: sim_spmBC <= sx;
+\t\t8\'b10111101\t: sim_spmBD <= sx;
+\t\t8\'b10111110\t: sim_spmBE <= sx;
+\t\t8\'b10111111\t: sim_spmBF <= sx;
+\t\t8\'b11000000\t: sim_spmC0 <= sx;
+\t\t8\'b11000001\t: sim_spmC1 <= sx;
+\t\t8\'b11000010\t: sim_spmC2 <= sx;
+\t\t8\'b11000011\t: sim_spmC3 <= sx;
+\t\t8\'b11000100\t: sim_spmC4 <= sx;
+\t\t8\'b11000101\t: sim_spmC5 <= sx;
+\t\t8\'b11000110\t: sim_spmC6 <= sx;
+\t\t8\'b11000111\t: sim_spmC7 <= sx;
+\t\t8\'b11001000\t: sim_spmC8 <= sx;
+\t\t8\'b11001001\t: sim_spmC9 <= sx;
+\t\t8\'b11001010\t: sim_spmCA <= sx;
+\t\t8\'b11001011\t: sim_spmCB <= sx;
+\t\t8\'b11001100\t: sim_spmCC <= sx;
+\t\t8\'b11001101\t: sim_spmCD <= sx;
+\t\t8\'b11001110\t: sim_spmCE <= sx;
+\t\t8\'b11001111\t: sim_spmCF <= sx;
+\t\t8\'b11010000\t: sim_spmD0 <= sx;
+\t\t8\'b11010001\t: sim_spmD1 <= sx;
+\t\t8\'b11010010\t: sim_spmD2 <= sx;
+\t\t8\'b11010011\t: sim_spmD3 <= sx;
+\t\t8\'b11010100\t: sim_spmD4 <= sx;
+\t\t8\'b11010101\t: sim_spmD5 <= sx;
+\t\t8\'b11010110\t: sim_spmD6 <= sx;
+\t\t8\'b11010111\t: sim_spmD7 <= sx;
+\t\t8\'b11011000\t: sim_spmD8 <= sx;
+\t\t8\'b11011001\t: sim_spmD9 <= sx;
+\t\t8\'b11011010\t: sim_spmDA <= sx;
+\t\t8\'b11011011\t: sim_spmDB <= sx;
+\t\t8\'b11011100\t: sim_spmDC <= sx;
+\t\t8\'b11011101\t: sim_spmDD <= sx;
+\t\t8\'b11011110\t: sim_spmDE <= sx;
+\t\t8\'b11011111\t: sim_spmDF <= sx;
+\t\t8\'b11100000\t: sim_spmE0 <= sx;
+\t\t8\'b11100001\t: sim_spmE1 <= sx;
+\t\t8\'b11100010\t: sim_spmE2 <= sx;
+\t\t8\'b11100011\t: sim_spmE3 <= sx;
+\t\t8\'b11100100\t: sim_spmE4 <= sx;
+\t\t8\'b11100101\t: sim_spmE5 <= sx;
+\t\t8\'b11100110\t: sim_spmE6 <= sx;
+\t\t8\'b11100111\t: sim_spmE7 <= sx;
+\t\t8\'b11101000\t: sim_spmE8 <= sx;
+\t\t8\'b11101001\t: sim_spmE9 <= sx;
+\t\t8\'b11101010\t: sim_spmEA <= sx;
+\t\t8\'b11101011\t: sim_spmEB <= sx;
+\t\t8\'b11101100\t: sim_spmEC <= sx;
+\t\t8\'b11101101\t: sim_spmED <= sx;
+\t\t8\'b11101110\t: sim_spmEE <= sx;
+\t\t8\'b11101111\t: sim_spmEF <= sx;
+\t\t8\'b11110000\t: sim_spmF0 <= sx;
+\t\t8\'b11110001\t: sim_spmF1 <= sx;
+\t\t8\'b11110010\t: sim_spmF2 <= sx;
+\t\t8\'b11110011\t: sim_spmF3 <= sx;
+\t\t8\'b11110100\t: sim_spmF4 <= sx;
+\t\t8\'b11110101\t: sim_spmF5 <= sx;
+\t\t8\'b11110110\t: sim_spmF6 <= sx;
+\t\t8\'b11110111\t: sim_spmF7 <= sx;
+\t\t8\'b11111000\t: sim_spmF8 <= sx;
+\t\t8\'b11111001\t: sim_spmF9 <= sx;
+\t\t8\'b11111010\t: sim_spmFA <= sx;
+\t\t8\'b11111011\t: sim_spmFB <= sx;
+\t\t8\'b11111100\t: sim_spmFC <= sx;
+\t\t8\'b11111101\t: sim_spmFD <= sx;
+\t\t8\'b11111110\t: sim_spmFE <= sx;
+\t\t8\'b11111111\t: sim_spmFF <= sx;
+    endcase
+end
+
+end
+
+//
+// Assignment of internal register variables to active registers 
+//
+if (bank == 1\'b0) begin
+\tkcpsm6_status[1:16] <= ""A,"";
+\tsim_s0 <= bank_a_s0 ;
+\tsim_s1 <= bank_a_s1 ;
+\tsim_s2 <= bank_a_s2 ;
+\tsim_s3 <= bank_a_s3 ;
+\tsim_s4 <= bank_a_s4 ;
+\tsim_s5 <= bank_a_s5 ;
+\tsim_s6 <= bank_a_s6 ;
+\tsim_s7 <= bank_a_s7 ;
+\tsim_s8 <= bank_a_s8 ;
+\tsim_s9 <= bank_a_s9 ;
+\tsim_sA <= bank_a_sa ;
+\tsim_sB <= bank_a_sb ;
+\tsim_sC <= bank_a_sc ;
+\tsim_sD <= bank_a_sd ;
+\tsim_sE <= bank_a_se ;
+\tsim_sF <= bank_a_sf ;
+end
+else begin
+\tkcpsm6_status[1:16] <= ""B,"";
+\tsim_s0 <= bank_b_s0 ;
+\tsim_s1 <= bank_b_s1 ;
+\tsim_s2 <= bank_b_s2 ;
+\tsim_s3 <= bank_b_s3 ;
+\tsim_s4 <= bank_b_s4 ;
+\tsim_s5 <= bank_b_s5 ;
+\tsim_s6 <= bank_b_s6 ;
+\tsim_s7 <= bank_b_s7 ;
+\tsim_s8 <= bank_b_s8 ;
+\tsim_s9 <= bank_b_s9 ;
+\tsim_sA <= bank_b_sa ;
+\tsim_sB <= bank_b_sb ;
+\tsim_sC <= bank_b_sc ;
+\tsim_sD <= bank_b_sd ;
+\tsim_sE <= bank_b_se ;
+\tsim_sF <= bank_b_sf ;
+end
+// 
+//
+end //process simulation;
+  
+  //synthesis translate_on
+//
+// **************************
+// * End of simulation code *
+// **************************
+//
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+endmodule
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+//
+// END OF FILE kcpsm6.v
+//
+///////////////////////////////////////////////////////////////////////////////////////////
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: Jafet Chaves Barrantes
+// 
+// Create Date:    15:45:17 04/03/2016 
+// Design Name: 
+// Module Name:    contador_AD_MM_T_2dig 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module contador_AD_MM_T_2dig
+(
+input wire clk,
+input wire reset,
+input wire [3:0] en_count,
+input wire enUP,
+input wire enDOWN,
+output wire [7:0] data_MM_T
+);
+localparam N = 6; // Para definir el n\xfamero de bits del contador (hasta 59->6 bits)
+//Declaraci\xf3n de se\xf1ales
+reg [N-1:0] q_act, q_next;
+wire [N-1:0] count_data;
+reg [3:0] digit1, digit0;
+
+//Descripci\xf3n del comportamiento
+always@(posedge clk, posedge reset)
+begin\t
+\t
+\tif(reset)
+\tbegin
+\t\tq_act <= 6'b0;
+\tend
+\t
+\telse
+\tbegin
+\t\tq_act <= q_next;
+\tend
+end
+
+
+//L\xf3gica de salida
+
+always@*
+begin
+
+\tif (en_count == 9)
+\tbegin
+\t\tif (enUP)
+\t\tbegin
+\t\t\tif (q_act >= 6'd59) q_next = 6'd0;
+\t\t\telse q_next = q_act + 6'd1;
+\t\tend
+\t\t
+\t\telse if (enDOWN)
+\t\tbegin
+\t\t\tif (q_act == 6'd0) q_next = 6'd59;
+\t\t\telse q_next = q_act - 6'd1;
+\t\tend
+\t\telse q_next = q_act;
+\tend
+\telse q_next = q_act;
+\t
+end
+
+assign count_data = q_act;
+
+//Decodificaci\xf3n BCD (2 d\xedgitos)
+
+always@*
+begin
+case(count_data)
+6'd0: begin digit1 = 4'b0000; digit0 = 4'b0000; end
+6'd1: begin digit1 = 4'b0000; digit0 = 4'b0001; end
+6'd2: begin digit1 = 4'b0000; digit0 = 4'b0010; end
+6'd3: begin digit1 = 4'b0000; digit0 = 4'b0011; end
+6'd4: begin digit1 = 4'b0000; digit0 = 4'b0100; end
+6'd5: begin digit1 = 4'b0000; digit0 = 4'b0101; end
+6'd6: begin digit1 = 4'b0000; digit0 = 4'b0110; end
+6'd7: begin digit1 = 4'b0000; digit0 = 4'b0111; end
+6'd8: begin digit1 = 4'b0000; digit0 = 4'b1000; end
+6'd9: begin digit1 = 4'b0000; digit0 = 4'b1001; end
+
+6'd10: begin digit1 = 4'b0001; digit0 = 4'b0000; end
+6'd11: begin digit1 = 4'b0001; digit0 = 4'b0001; end
+6'd12: begin digit1 = 4'b0001; digit0 = 4'b0010; end
+6'd13: begin digit1 = 4'b0001; digit0 = 4'b0011; end
+6'd14: begin digit1 = 4'b0001; digit0 = 4'b0100; end
+6'd15: begin digit1 = 4'b0001; digit0 = 4'b0101; end
+6'd16: begin digit1 = 4'b0001; digit0 = 4'b0110; end
+6'd17: begin digit1 = 4'b0001; digit0 = 4'b0111; end
+6'd18: begin digit1 = 4'b0001; digit0 = 4'b1000; end
+6'd19: begin digit1 = 4'b0001; digit0 = 4'b1001; end
+
+6'd20: begin digit1 = 4'b0010; digit0 = 4'b0000; end
+6'd21: begin digit1 = 4'b0010; digit0 = 4'b0001; end
+6'd22: begin digit1 = 4'b0010; digit0 = 4'b0010; end
+6'd23: begin digit1 = 4'b0010; digit0 = 4'b0011; end
+6'd24: begin digit1 = 4'b0010; digit0 = 4'b0100; end
+6'd25: begin digit1 = 4'b0010; digit0 = 4'b0101; end
+6'd26: begin digit1 = 4'b0010; digit0 = 4'b0110; end
+6'd27: begin digit1 = 4'b0010; digit0 = 4'b0111; end
+6'd28: begin digit1 = 4'b0010; digit0 = 4'b1000; end
+6'd29: begin digit1 = 4'b0010; digit0 = 4'b1001; end
+
+6'd30: begin digit1 = 4'b0011; digit0 = 4'b0000; end
+6'd31: begin digit1 = 4'b0011; digit0 = 4'b0001; end
+6'd32: begin digit1 = 4'b0011; digit0 = 4'b0010; end
+6'd33: begin digit1 = 4'b0011; digit0 = 4'b0011; end
+6'd34: begin digit1 = 4'b0011; digit0 = 4'b0100; end
+6'd35: begin digit1 = 4'b0011; digit0 = 4'b0101; end
+6'd36: begin digit1 = 4'b0011; digit0 = 4'b0110; end
+6'd37: begin digit1 = 4'b0011; digit0 = 4'b0111; end
+6'd38: begin digit1 = 4'b0011; digit0 = 4'b1000; end
+6'd39: begin digit1 = 4'b0011; digit0 = 4'b1001; end
+
+6'd40: begin digit1 = 4'b0100; digit0 = 4'b0000; end
+6'd41: begin digit1 = 4'b0100; digit0 = 4'b0001; end
+6'd42: begin digit1 = 4'b0100; digit0 = 4'b0010; end
+6'd43: begin digit1 = 4'b0100; digit0 = 4'b0011; end
+6'd44: begin digit1 = 4'b0100; digit0 = 4'b0100; end
+6'd45: begin digit1 = 4'b0100; digit0 = 4'b0101; end
+6'd46: begin digit1 = 4'b0100; digit0 = 4'b0110; end
+6'd47: begin digit1 = 4'b0100; digit0 = 4'b0111; end
+6'd48: begin digit1 = 4'b0100; digit0 = 4'b1000; end
+6'd49: begin digit1 = 4'b0100; digit0 = 4'b1001; end
+
+6'd50: begin digit1 = 4'b0101; digit0 = 4'b0000; end
+6'd51: begin digit1 = 4'b0101; digit0 = 4'b0001; end
+6'd52: begin digit1 = 4'b0101; digit0 = 4'b0010; end
+6'd53: begin digit1 = 4'b0101; digit0 = 4'b0011; end
+6'd54: begin digit1 = 4'b0101; digit0 = 4'b0100; end
+6'd55: begin digit1 = 4'b0101; digit0 = 4'b0101; end
+6'd56: begin digit1 = 4'b0101; digit0 = 4'b0110; end
+6'd57: begin digit1 = 4'b0101; digit0 = 4'b0111; end
+6'd58: begin digit1 = 4'b0101; digit0 = 4'b1000; end
+6'd59: begin digit1 = 4'b0101; digit0 = 4'b1001; end
+
+
+default:  begin digit1 = 0; digit0 = 0; end
+endcase
+end
+
+assign data_MM_T = {digit1,digit0};
+
+endmodule
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: Jafet Chaves Barrantes
+// 
+// Create Date:    18:28:34 03/22/2016 
+// Design Name: 
+// Module Name:    Generador_Caracteres 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: Este m\xf3dulo se encarga de generar el texto que se requiere en la imagen del monitor.
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module generador_caracteres
+(
+input wire clk,
+input wire [3:0] digit0_HH, digit1_HH, digit0_MM, digit1_MM, digit0_SS, digit1_SS,//
+digit0_DAY, digit1_DAY, digit0_MES, digit1_MES, digit0_YEAR, digit1_YEAR,//
+digit0_HH_T, digit1_HH_T, digit0_MM_T, digit1_MM_T, digit0_SS_T, digit1_SS_T,//Decenas y unidades para los n\xfameros en pantalla (18 inputs de 3 bits)
+input wire AM_PM,//Entrada para conocer si en la informaci\xf3n de hora se despliega AM o PM
+input wire parpadeo,//parpadeo del cursor
+input wire [1:0] config_mode,//Cuatro estados del modo configuraci\xf3n
+input wire [1:0] cursor_location,//Marca la posici\xf3n del cursor en modo configuraci\xf3n
+input wire [9:0] pixel_x, pixel_y,//Coordenada de cada pixel
+output wire AMPM_on, //Localizaci\xf3n de esos respectivos textos
+output wire text_on, //10 ""textos"" en total en pantalla (bandera de indica que se debe escribir texto)
+output reg [7:0] text_RGB //8 bpp (Nexys 3)
+);
+
+//Declaraci\xf3n de se\xf1ales
+
+//Font ROM (caracteres 16x32)
+wire [11:0] rom_addr; //ASCII 7-bits + Fila 5-bits
+reg [6:0] char_addr; //ASCII 7-bits
+reg [4:0] row_addr; //Direccion de fila del patr\xf3n de caracter en particular(5 bits)
+reg [3:0] bit_addr; //Columna del pixel particular de un patr\xf3n de caracter (4 bits)
+wire [15:0] font_word;//Fila de pixeles del patr\xf3n de caracter en particular (16 bits)
+wire font_bit;//1 pixel del font_word espec\xedficado por bit_addr
+
+//Direcciones ""auxiliares"" para cada uno de los d\xedgitos de los n\xfameros a mostrar
+reg [6:0] char_addr_digHORA, char_addr_digFECHA, char_addr_digTIMER, char_addr_AMPM;
+wire [4:0] row_addr_digHORA, row_addr_digFECHA, row_addr_digTIMER,  row_addr_AMPM;
+wire [3:0] bit_addr_digHORA, bit_addr_digFECHA, bit_addr_digTIMER, bit_addr_AMPM; 
+wire digHORA_on, digFECHA_on, digTIMER_on;
+\t
+//Instanciaci\xf3n de la font ROM
+ROM_16x32 Instancia_ROM_16x32
+(.clk(clk), .addr(rom_addr), .data(font_word));
+
+//Descripci\xf3n de comportamiento
+
+//1.D\xedgitos para representar la HORA(tama\xf1o de fuente 16x32)
+assign digHORA_on = (pixel_y[9:5]==4)&&(pixel_x[9:4]>=16)&&(pixel_x[9:4]<=23);
+assign row_addr_digHORA = pixel_y[4:0];
+assign bit_addr_digHORA = pixel_x[3:0];
+
+always@*
+begin
+
+\tcase(pixel_x[6:4])
+\t3\'b000: char_addr_digHORA = {3\'b011, digit1_HH};//(decenas hrs)
+\t3\'b001: char_addr_digHORA = {3\'b011, digit0_HH};//(unidades hrs)
+\t3\'b010: char_addr_digHORA = 7\'h3a;//:
+\t3\'b011: char_addr_digHORA = {3\'b011, digit1_MM};//(decenas min)
+\t3\'b100: char_addr_digHORA = {3\'b011, digit0_MM};//(unidades min)
+\t3\'b101: char_addr_digHORA = 7\'h3a;//:
+\t3\'b110: char_addr_digHORA = {3\'b011, digit1_SS};//(decenas s)
+\t3\'b111: char_addr_digHORA = {3\'b011, digit0_SS};//(unidades s)
+\tendcase
+\t
+end
+
+//2.D\xedgitos para representar la FECHA(tama\xf1o de fuente 16x32)
+assign digFECHA_on = (pixel_y[9:5]==12)&&(pixel_x[9:4]>=7)&&(pixel_x[9:4]<=14);
+assign row_addr_digFECHA = pixel_y[4:0];
+assign bit_addr_digFECHA = pixel_x[3:0];
+
+always@*
+begin
+\tcase(pixel_x[6:4])
+\t3\'b111: char_addr_digFECHA = {3\'b011, digit1_DAY};//(decenas DIA)
+\t3\'b000: char_addr_digFECHA = {3\'b011, digit0_DAY};//(unidades DIA)
+\t3\'b001: char_addr_digFECHA = 7\'h2f;//""/""
+\t3\'b010: char_addr_digFECHA = {3\'b011, digit1_MES};//(decenas MES)
+\t3\'b011: char_addr_digFECHA = {3\'b011, digit0_MES};//(unidades MES)
+\t3\'b100: char_addr_digFECHA = 7\'h2f;//""/""
+\t3\'b101: char_addr_digFECHA = {3\'b011, digit1_YEAR};//(decenas A\xd1O)
+\t3\'b110: char_addr_digFECHA = {3\'b011, digit0_YEAR};//(unidades\tA\xd1O)
+\tendcase\t
+end
+
+//3.D\xedgitos para la cuenta del TIMER(tama\xf1o de fuente 16x32)
+assign digTIMER_on = (pixel_y[9:5]==12)&&(pixel_x[9:4]>=25)&&(pixel_x[9:4]<=32);
+assign row_addr_digTIMER = pixel_y[4:0];
+assign bit_addr_digTIMER = pixel_x[3:0];
+
+always@*
+begin
+\tcase(pixel_x[6:4])
+\t3\'b001: char_addr_digTIMER = {3\'b011, digit1_HH_T};//(decenas hrs)
+\t3\'b010: char_addr_digTIMER = {3\'b011, digit0_HH_T};//(unidades hrs)
+\t3\'b011: char_addr_digTIMER = 7\'h3a;//:
+\t3\'b100: char_addr_digTIMER = {3\'b011, digit1_MM_T};//(decenas min)
+\t3\'b101: char_addr_digTIMER = {3\'b011, digit0_MM_T};//(unidades min)
+\t3\'b110: char_addr_digTIMER = 7\'h3a;//:
+\t3\'b111: char_addr_digTIMER = {3\'b011, digit1_SS_T};//(decenas s)
+\t3\'b000: char_addr_digTIMER = {3\'b011, digit0_SS_T};//(decenas s)
+\tendcase\t
+end
+
+//4.Palabra AM o PM(tama\xf1o de fuente 16x32)
+assign AMPM_on = (pixel_y[9:5]==1)&&(pixel_x[9:4]>=26)&&(pixel_x[9:4]<=27);
+assign row_addr_AMPM = pixel_y[4:0];
+assign bit_addr_AMPM = pixel_x[3:0];
+
+always@*
+begin
+\tcase(pixel_x[4])
+\t
+\t1\'b0:
+\tbegin
+\tcase(AM_PM)//AM_PM = 0: se escribe AM
+\t1\'b0: char_addr_AMPM = 7\'h61;//A
+\t1\'b1: char_addr_AMPM = 7\'h64;//P
+\tendcase
+\tend
+\t
+\t1\'b1: char_addr_AMPM = 7\'h63;//M
+\tendcase\t
+end
+
+//Multiplexar las direcciones para font ROM y salida RBG
+always @*
+begin
+
+text_RGB = 8\'b0;//Fondo negro
+\t
+\tif(digHORA_on)
+\t\tbegin
+\t\tchar_addr = char_addr_digHORA;
+      row_addr = row_addr_digHORA;
+      bit_addr = bit_addr_digHORA;
+\t\t\t//(0: Los dos d\xedgitos a la derecha, 1: Los dos d\xedgitos intermedios, 2: Los dos d\xedgitos a la izquierda, 3: Ubicaci\xf3n de AM/PM)
+\t\t\t//Eval\xfaa que se est\xe1 configurando (0: modo normal, 1: config.hora, 2: config.fecha, 3: config.timer)
+\t\t\tif(font_bit) text_RGB = 8\'h00; //Negro
+\t\t\telse if ((parpadeo)&&(~font_bit)&&(config_mode == 1)&&(pixel_y[9:5]==4)&&(pixel_x[9:4]>=16)&&(pixel_x[9:4]<=17)&&(cursor_location==2)) 
+\t\t\ttext_RGB =8\'hFF;//Hace un cursor si se est\xe1 en modo configuraci\xf3n
+\t\t\telse if ((parpadeo)&&(~font_bit)&&(config_mode == 1)&&(pixel_y[9:5]==4)&&(pixel_x[9:4]>=19)&&(pixel_x[9:4]<=20)&&(cursor_location==1))
+\t\t\ttext_RGB = 8\'hFF;//Hace un cursor si se est\xe1 en modo configuraci\xf3n
+\t\t\telse if ((parpadeo)&&(~font_bit)&&(config_mode == 1)&&(pixel_y[9:5]==4)&&(pixel_x[9:4]>=22)&&(pixel_x[9:4]<=23)&&(cursor_location==0))
+\t\t\ttext_RGB = 8\'hFF;//Hace un cursor si se est\xe1 en modo configuraci\xf3n
+\t\t\telse if(~font_bit) text_RGB = 8\'h1E;//Fondo del texto igual al de los recuadros
+\t\tend
+
+\telse if(digFECHA_on)
+\t\tbegin
+\t\tchar_addr = char_addr_digFECHA;
+      row_addr = row_addr_digFECHA;
+      bit_addr = bit_addr_digFECHA;
+\t\t\t//(0: Los dos d\xedgitos a la derecha, 1: Los dos d\xedgitos intermedios, 2: Los dos d\xedgitos a la izquierda, 3: Ubicaci\xf3n de d\xeda semana)
+\t\t\tif(font_bit) text_RGB =8\'h00; //Negro
+\t\t\telse if ((parpadeo)&&(~font_bit)&&(config_mode == 2)&&(pixel_y[9:5]==12)&&(pixel_x[9:4]>=7)&&(pixel_x[9:4]<=8)&&(cursor_location==2))
+\t\t\ttext_RGB = 8\'hFF;//Hace un cursor si se est\xe1 en modo configuraci\xf3n
+\t\t\telse if ((parpadeo)&&(~font_bit)&&(config_mode == 2)&&(pixel_y[9:5]==12)&&(pixel_x[9:4]>=10)&&(pixel_x[9:4]<=11)&&(cursor_location==1))
+\t\t\ttext_RGB = 8\'hFF;//Hace un cursor si se est\xe1 en modo configuraci\xf3n
+\t\t\telse if ((parpadeo)&&(~font_bit)&&(config_mode == 2)&&(pixel_y[9:5]==12)&&(pixel_x[9:4]>=13)&&(pixel_x[9:4]<=14)&&(cursor_location==0))
+\t\t\ttext_RGB = 8\'hFF;//Hace un cursor si se est\xe1 en modo configuraci\xf3n
+\t\t\telse if(~font_bit) text_RGB = 8\'h1E;//Fondo del texto igual al de los recuadros
+\t\tend
+\t
+\telse if ((digTIMER_on))
+\t\tbegin
+\t\tchar_addr = char_addr_digTIMER;
+      row_addr = row_addr_digTIMER;
+      bit_addr = bit_addr_digTIMER;
+\t\t\t//(0: Los dos d\xedgitos a la derecha, 1: Los dos d\xedgitos intermedios, 2: Los dos d\xedgitos a la izquierda)
+\t\t\tif(font_bit) text_RGB = 8\'h00; //Negro
+\t\t\telse if ((parpadeo)&&(~font_bit)&&(config_mode == 3)&&(pixel_y[9:5]==12)&&(pixel_x[9:4]>=25)&&(pixel_x[9:4]<=26)&&(cursor_location==2)) 
+\t\t\ttext_RGB = 8\'hFF;//Hace un cursor si se est\xe1 en modo configuraci\xf3n
+\t\t\telse if ((parpadeo)&&(~font_bit)&&(config_mode == 3)&&(pixel_y[9:5]==12)&&(pixel_x[9:4]>=28)&&(pixel_x[9:4]<=29)&&(cursor_location==1))
+\t\t\ttext_RGB = 8\'hFF;//Hace un cursor si se est\xe1 en modo configuraci\xf3n
+\t\t\telse if ((parpadeo)&&(~font_bit)&&(config_mode == 3)&&(pixel_y[9:5]==12)&&(pixel_x[9:4]>=31)&&(pixel_x[9:4]<=32)&&(cursor_location==0))
+\t\t\ttext_RGB = 8\'hFF;//Hace un cursor si se est\xe1 en modo configuraci\xf3n
+\t\t\telse if(~font_bit) text_RGB = 8\'h1E;//Fondo del texto igual al de los recuadros
+\t\tend
+\t\t
+\telse
+\t\tbegin
+\t\tchar_addr = char_addr_AMPM;
+      row_addr = row_addr_AMPM;
+      bit_addr = bit_addr_AMPM;
+\t\t\tif(font_bit) text_RGB = 8\'hFF; //Blanco
+\t\tend
+\t\t
+end
+
+assign text_on = digHORA_on|digFECHA_on|digTIMER_on;//3 bloques de texto en total
+
+//Interfaz con la font ROM
+assign rom_addr = {char_addr, row_addr};
+assign font_bit = font_word[~bit_addr];
+
+endmodule
+/*
+Nota: Los 10 textos a mostrar son
+1.La palabra HORA
+2.Los d\xedgitos para la hora
+3.Los n\xfameros de la fecha
+4.El d\xeda de la semana
+5.La palabra TIMER
+6.Los d\xedgitos para la cuenta del timer
+7.La palabra RING
+8.AM o PM
+9.RTC DISPLAY v1.0
+*/"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    13:49:19 05/27/2016 
+// Design Name: 
+// Module Name:    prueba_lectura_rtc 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module prueba_lectura_rtc_2
+(
+input wire clk, reset,
+input wire sw,
+inout [7:0]dato,
+output wire AD, CS, WR, RD,
+output [7:0] RGB,
+output hsync, vsync
+);
+
+//Conexiones internas
+reg [7:0]in_port;
+wire [7:0]out_port;
+wire [7:0]port_id;
+wire write_strobe;
+wire k_write_strobe;
+wire read_strobe;
+wire interrupt;
+// conexiones banco de registros a VGA
+wire [7:0]out_seg_hora,out_min_hora,out_hora_hora;
+wire [7:0]out_dia_fecha,out_mes_fecha,out_jahr_fecha;
+wire [7:0]out_seg_timer,out_min_timer,out_hora_timer;
+
+///////////////////////////// hold's
+wire hold_seg_hora; 
+wire hold_min_hora; 
+wire hold_hora_hora; 
+wire hold_dia_fecha; 
+wire hold_mes_fecha; 
+wire hold_jahr_fecha; 
+wire hold_dia_semana; 
+wire hold_seg_timer;
+wire hold_min_timer; 
+wire hold_hora_timer;
+// wire hold_banderas_config;
+//////////////////////
+
+
+//Conexiones de controlador RTC
+wire fin_lectura_escritura;
+wire [7:0] out_dato;
+
+assign interrupt = 1'b0;
+
+wire wire_sw;
+assign wire_sw = {7'b0,sw};
+
+microcontrolador instancia_microcontrolador 
+(
+    .clk(clk), 
+    .reset(reset), 
+    .interrupt(interrupt), 
+    .in_port(in_port), 
+    .write_strobe(write_strobe), 
+    .k_write_strobe(k_write_strobe), 
+    .read_strobe(read_strobe), 
+    .interrupt_ack(), 
+    .port_id(port_id), 
+    .out_port(out_port)
+);
+
+controlador_VGA instancia_controlador_VGA 
+(
+    .clock(clk), 
+    .reset(reset), 
+    .digit0_HH(out_hora_hora[3:0]), .digit1_HH(out_hora_hora[7:4]), .digit0_MM(out_min_hora[3:0]), .digit1_MM(out_min_hora[7:4]), .digit0_SS(out_seg_hora[3:0]), .digit1_SS(out_seg_hora[7:4]),//
+\t .digit0_DAY(out_dia_fecha[3:0]), .digit1_DAY(out_dia_fecha[7:4]), .digit0_MES(out_mes_fecha[3:0]), .digit1_MES(out_mes_fecha[7:4]), .digit0_YEAR(out_jahr_fecha[3:0]), .digit1_YEAR(out_jahr_fecha[7:4]),//
+\t .digit0_HH_T(out_hora_timer[3:0]), .digit1_HH_T(out_hora_timer[7:4]), .digit0_MM_T(out_min_timer[3:0]), .digit1_MM_T(out_min_timer[7:4]), .digit0_SS_T(out_seg_timer[3:0]), .digit1_SS_T(out_seg_timer[7:4]),//Decenas y unidades para los n\xfameros en pantalla (18 inputs de 3 bits)
+    .AM_PM(1'b0), 
+    .config_mode(2'b0), 
+    .cursor_location(2'b0), 
+    .formato_hora(1'b1), 
+    .estado_alarma(1'b0), 
+    .hsync(hsync), 
+    .vsync(vsync), 
+    .RGB(RGB)
+    );
+\t 
+memoria_registros_VGA instancia_memoria_registros_VGA 
+(
+    .clk(clk), 
+    .reset(reset), 
+    .cs_seg_hora(1'b0), 
+    .cs_min_hora(1'b0), 
+    .cs_hora_hora(1'b0), 
+    .cs_dia_fecha(1'b0), 
+    .cs_mes_fecha(1'b0), 
+    .cs_jahr_fecha(1'b0), 
+    .cs_seg_timer(1'b0), 
+    .cs_min_timer(1'b0), 
+    .cs_hora_timer(1'b0), 
+    .hold_seg_hora(hold_seg_hora), 
+    .hold_min_hora(hold_min_hora), 
+    .hold_hora_hora(hold_hora_hora), 
+    .hold_dia_fecha(hold_dia_fecha), 
+    .hold_mes_fecha(hold_mes_fecha), 
+    .hold_jahr_fecha(hold_jahr_fecha), 
+    .hold_seg_timer(hold_seg_timer), 
+    .hold_min_timer(hold_min_timer), 
+    .hold_hora_timer(hold_hora_timer), 
+    .hold_banderas_config(1'b1), 
+    .data_PicoBlaze(out_port), 
+    .count_seg_hora(8'b0), 
+    .count_min_hora(8'b0), 
+    .count_hora_hora(8'b0), 
+    .count_dia_fecha(8'b0), 
+    .count_mes_fecha(8'b0), 
+    .count_jahr_fecha(8'b0), 
+    .count_seg_timer(8'b0), 
+    .count_min_timer(8'b0), 
+    .count_hora_timer(8'b0), 
+    .out_seg_hora(out_seg_hora), 
+    .out_min_hora(out_min_hora), 
+    .out_hora_hora(out_hora_hora), 
+    .out_dia_fecha(out_dia_fecha), 
+    .out_mes_fecha(out_mes_fecha), 
+    .out_jahr_fecha(out_jahr_fecha), 
+    .out_seg_timer(out_seg_timer), 
+    .out_min_timer(out_min_timer), 
+    .out_hora_timer(out_hora_timer), 
+    .out_banderas_config()
+);
+
+deco_hold_registros instancia_deco_hold_registros (
+    .write_strobe(write_strobe), 
+    .port_id(port_id), 
+    .hold_seg_hora(hold_seg_hora), 
+    .hold_min_hora(hold_min_hora), 
+    .hold_hora_hora(hold_hora_hora), 
+    .hold_dia_fecha(hold_dia_fecha), 
+    .hold_mes_fecha(hold_mes_fecha), 
+    .hold_jahr_fecha(hold_jahr_fecha), 
+    .hold_seg_timer(hold_seg_timer), 
+    .hold_min_timer(hold_min_timer), 
+    .hold_hora_timer(hold_hora_timer)
+    );
+\t 
+escritor_lector_rtc_2 instancia_escritor_lector_rtc_2 (
+    .clk(clk), 
+    .reset(reset), 
+    .in_dato(out_port),
+\t .port_id(port_id),
+\t .write_strobe(write_strobe), 
+\t .k_write_strobe(k_write_strobe),
+    .read_strobe(read_strobe),
+    .reg_a_d(AD), 
+    .reg_cs(CS), 
+    .reg_rd(RD), 
+    .reg_wr(WR), 
+    .out_dato(out_dato), 
+    .flag_done(fin_lectura_escritura), 
+    .dato(dato)
+    );
+\t 
+//Decodificaci\xf3n del puerto de entrada del microcontrolador
+
+always@(posedge clk)
+begin
+\t\tcase (port_id) 
+\t\t8'h0F : in_port <= fin_lectura_escritura;
+\t\t8'h10 : in_port <= out_dato;
+\t\t8'h02 : in_port <= wire_sw;
+\t  default : in_port <= 8'bXXXXXXXX;  
+\tendcase
+end
+\t \t 
+endmodule
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    23:15:32 03/28/2016 
+// Design Name: 
+// Module Name:    bloque_prueba_frames 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module bloque_prueba_frames
+(
+input wire [1:0]sw,
+output reg [3:0] digit0_HH, digit1_HH, digit0_MM, digit1_MM, digit0_SS, digit1_SS,//
+digit0_DAY, digit1_DAY, digit0_MES, digit1_MES, digit0_YEAR, digit1_YEAR,//
+digit0_HH_T, digit1_HH_T, digit0_MM_T, digit1_MM_T, digit0_SS_T, digit1_SS_T,//Decenas y unidades para los n\xfameros en pantalla (18 inputs de 3 bits)
+output reg AM_PM,//Entrada para conocer si en la informaci\xf3n de hora se despliega AM o PM
+output reg [1:0]funcion,//2-bits: cuatro estados del modo configuraci\xf3n
+output reg [1:0] cursor_location,//Marca la posici\xf3n del cursor en modo configuraci\xf3n
+output reg timer_end,//bandera proveniente del RTC que indica la finalizaci\xf3n del tiempo del timer
+output reg formato_hora//Se\xf1al que indica si la hora esta en formato 12 hrs o 24 hrs (0->24 hrs)
+);
+
+
+//L\xf3gica de salida
+always@*
+
+begin
+
+case(sw)
+
+2'h0:
+begin
+\tdigit0_HH = 4'b0000;
+\tdigit1_HH = 4'b0001;
+\tdigit0_MM = 4'b0010; 
+\tdigit1_MM = 4'b0011;
+\tdigit0_SS = 4'b0100;
+\tdigit1_SS = 4'b0101;//
+
+\tdigit0_DAY = 4'b0110;
+\tdigit1_DAY = 4'b0111;
+\tdigit0_MES = 4'b1000;
+\tdigit1_MES = 4'b1001;
+\tdigit0_YEAR = 4'b0000;
+\tdigit1_YEAR = 4'b0001;//
+
+\tdigit0_HH_T = 4'b0010; 
+\tdigit1_HH_T = 4'b0011;
+\tdigit0_MM_T = 4'b0100;
+\tdigit1_MM_T = 4'b0101;
+\tdigit0_SS_T = 4'b0110;
+\tdigit1_SS_T = 4'b0111;
+
+\tAM_PM = 1'b0;
+\tfuncion = 2'b00;
+\tcursor_location = 2'b00;
+\ttimer_end = 1'b1;
+\tformato_hora = 1'b1;
+end
+
+2'h1:
+begin
+\tdigit0_HH = 4'b0010;
+\tdigit1_HH = 4'b0011;
+\tdigit0_MM = 4'b0100; 
+\tdigit1_MM = 4'b0101;
+\tdigit0_SS = 4'b0110;
+\tdigit1_SS = 4'b0111;//
+
+\tdigit0_DAY = 4'b1000;
+\tdigit1_DAY = 4'b1001;
+\tdigit0_MES = 4'b0000;
+\tdigit1_MES = 4'b0001;
+\tdigit0_YEAR = 4'b0010;
+\tdigit1_YEAR = 4'b0011;//
+
+\tdigit0_HH_T = 4'b0100; 
+\tdigit1_HH_T = 4'b0101;
+\tdigit0_MM_T = 4'b0110;
+\tdigit1_MM_T = 4'b0111;
+\tdigit0_SS_T = 4'b1000;
+\tdigit1_SS_T = 4'b1001;
+
+\tAM_PM = 1'b1;
+\tfuncion = 2'b01;
+\tcursor_location = 2'b10;
+\ttimer_end = 1'b0;
+\tformato_hora = 1'b1;
+end
+
+2'h2:
+begin
+\tdigit0_HH = 4'b1001;
+\tdigit1_HH = 4'b0000;
+\tdigit0_MM = 4'b0001; 
+\tdigit1_MM = 4'b0010;
+\tdigit0_SS = 4'b0011;
+\tdigit1_SS = 4'b0100;//
+
+\tdigit0_DAY = 4'b0101;
+\tdigit1_DAY = 4'b0110;
+\tdigit0_MES = 4'b0111;
+\tdigit1_MES = 4'b1000;
+\tdigit0_YEAR = 4'b1001;
+\tdigit1_YEAR = 4'b0000;//
+
+\tdigit0_HH_T = 4'b0001; 
+\tdigit1_HH_T = 4'b0010;
+\tdigit0_MM_T = 4'b0011;
+\tdigit1_MM_T = 4'b0100;
+\tdigit0_SS_T = 4'b0101;
+\tdigit1_SS_T = 4'b0110;
+
+\tAM_PM = 1'b0;
+\tfuncion = 2'b10;
+\tcursor_location = 2'b01;
+\ttimer_end = 1'b0;
+\tformato_hora = 1'b0;
+end
+
+2'h3:
+begin
+\tdigit0_HH = 4'b0111;
+\tdigit1_HH = 4'b0110;
+\tdigit0_MM = 4'b0101; 
+\tdigit1_MM = 4'b0100;
+\tdigit0_SS = 4'b0011;
+\tdigit1_SS = 4'b0011;//
+
+\tdigit0_DAY = 4'b0010;
+\tdigit1_DAY = 4'b0001;
+\tdigit0_MES = 4'b0000;
+\tdigit1_MES = 4'b1001;
+\tdigit0_YEAR = 4'b1000;
+\tdigit1_YEAR = 4'b0111;//
+
+\tdigit0_HH_T = 4'b0110; 
+\tdigit1_HH_T = 4'b0101;
+\tdigit0_MM_T = 4'b0100;
+\tdigit1_MM_T = 4'b0011;
+\tdigit0_SS_T = 4'b0010;
+\tdigit1_SS_T = 4'b0001;
+
+\tAM_PM = 1'b0;
+\tfuncion = 2'b11;
+\tcursor_location = 2'b00;
+\ttimer_end = 1'b0;
+\tformato_hora = 1'b0;
+end
+
+endcase
+
+end
+
+endmodule
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: Jafet Chaves Barrantes
+// 
+// Create Date:    22:59:47 05/31/2016 
+// Design Name: 
+// Module Name:    top_reloj_digital_v2.0 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module top_reloj_digital_v2
+(
+input wire clk, reset,
+input wire ps2data, 
+input wire ps2clk, 
+inout [7:0] dato,
+output wire AD, CS, WR, RD,
+output wire alarma_sonora,
+output wire [7:0] RGB,
+output wire hsync, vsync
+);
+
+//Conexiones internas
+reg [7:0]in_port;
+wire [7:0]out_port;
+wire [7:0]port_id;
+wire write_strobe;
+wire k_write_strobe;
+wire read_strobe;
+wire interrupt;
+
+wire [7:0]out_seg_hora,out_min_hora,out_hora_hora;
+wire [7:0]out_dia_fecha,out_mes_fecha,out_jahr_fecha;
+wire [7:0]out_seg_timer,out_min_timer,out_hora_timer;
+
+wire fin_lectura_escritura;
+wire [7:0] out_dato;
+
+wire [7:0] ascii_code;
+
+assign interrupt = 1'b0;
+
+
+microcontrolador instancia_microcontrolador 
+(
+    .clk(clk), 
+    .reset(reset), 
+    .interrupt(interrupt), 
+    .in_port(in_port), 
+    .write_strobe(write_strobe), 
+    .k_write_strobe(k_write_strobe), 
+    .read_strobe(read_strobe), 
+    .interrupt_ack(), 
+    .port_id(port_id), 
+    .out_port(out_port)
+);
+
+escritor_lector_rtc_2 instancia_escritor_lector_rtc_2 
+(
+    .clk(clk), 
+    .reset(reset), 
+    .in_dato(out_port),
+\t .port_id(port_id),
+\t .write_strobe(write_strobe), 
+\t .k_write_strobe(k_write_strobe),
+    .read_strobe(read_strobe),
+    .reg_a_d(AD), 
+    .reg_cs(CS), 
+    .reg_rd(RD), 
+    .reg_wr(WR), 
+    .out_dato(out_dato), 
+    .flag_done(fin_lectura_escritura), 
+    .dato(dato)
+);
+\t 
+controlador_teclado_ps2 instancia_controlador_teclado_ps2 
+(
+    .clk(clk), 
+    .reset(reset), 
+    .ps2data(ps2data), 
+    .ps2clk(ps2clk), 
+    .port_id(port_id), 
+    .read_strobe(read_strobe), 
+    .ascii_code(ascii_code)
+);
+
+controlador_VGA instancia_controlador_VGA 
+(
+    .clock(clk), 
+    .reset(reset), 
+    .in_dato(out_port), 
+    .port_id(port_id), 
+    .write_strobe(write_strobe), 
+    .k_write_strobe(k_write_strobe), 
+    .out_seg_hora(out_seg_hora), 
+    .out_min_hora(out_min_hora), 
+    .out_hora_hora(out_hora_hora), 
+    .out_dia_fecha(out_dia_fecha), 
+    .out_mes_fecha(out_mes_fecha), 
+    .out_jahr_fecha(out_jahr_fecha), 
+    .out_seg_timer(out_seg_timer), 
+    .out_min_timer(out_min_timer), 
+    .out_hora_timer(out_hora_timer),
+\t .alarma_sonora(alarma_sonora),
+    .hsync(hsync), 
+    .vsync(vsync), 
+    .RGB(RGB)
+);
+
+//Decodificaci\xf3n del puerto de entrada del microcontrolador
+
+always@(posedge clk)
+begin
+\t\tcase (port_id) 
+\t\t8'h0F : in_port <= fin_lectura_escritura;
+\t\t8'h10 : in_port <= out_dato;
+\t\t8'h02 : in_port <= ascii_code;
+\t\t8'h12 : in_port <= out_seg_hora;
+\t\t8'h13 : in_port <= out_min_hora;
+\t\t8'h14 : in_port <= out_hora_hora;
+\t\t8'h15 : in_port <= out_dia_fecha;
+\t\t8'h16 : in_port <= out_mes_fecha;
+\t\t8'h17 : in_port <= out_jahr_fecha;
+\t\t8'h18 : in_port <= out_seg_timer;
+\t\t8'h19 : in_port <= out_min_timer;
+\t\t8'h1A : in_port <= out_hora_timer;
+\t  default : in_port <= 8'bXXXXXXXX;  
+\tendcase
+end
+
+endmodule
+"
+"`timescale 1ns / 1ps
+
+////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:
+//
+// Create Date:   13:56:16 05/24/2016
+// Design Name:   Controlador_reloj_digital
+// Module Name:   D:/TEC/I 2016/Lab Digitales/Proyecto III/Proyecto Xillinx/Proyecto_3/testbench_controlador_reloj_digital.v
+// Project Name:  Proyecto_3
+// Target Device:  
+// Tool versions:   
+// Description: 
+//
+// Verilog Test Fixture created by ISE for module: Controlador_reloj_digital
+//
+// Dependencies:
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// ////////////////////////////////////////////////////////////////////////////////
+
+module testbench_controlador_reloj_digital;
+
+\t// Inputs
+\treg clk;
+\treg reset;
+
+\t// Outputs
+\twire reg_a_d;
+\twire reg_cs;
+\twire reg_rd;
+\twire reg_wr;
+\twire [7:0]port_id;
+\twire [7:0]out_port;
+\twire[7:0]fin_lectura_escritura;
+
+\t// Bidirs
+\twire [7:0] dato; 
+
+\t// Instantiate the Unit Under Test (UUT)
+\tControlador_reloj_digital uut (
+\t\t.clk(clk), 
+\t\t.reset(reset), 
+\t\t.reg_a_d(reg_a_d), 
+\t\t.reg_cs(reg_cs), 
+\t\t.reg_rd(reg_rd), 
+\t\t.reg_wr(reg_wr), 
+\t\t.port_id(port_id),
+\t\t.out_port(out_port),
+\t\t.fin_lectura_escritura(fin_lectura_escritura),
+\t\t.dato(dato)
+\t);
+always #5 clk = ~clk;
+
+\tinitial begin
+\t\t// Initialize Inputs
+\t\tclk = 0;
+\t\treset = 1;
+\t\t#10 reset = 0;
+\t\t
+
+\t\t// Wait 100 ns for global reset to finish
+\t\t#100000 $stop;
+        
+\t\t// Add stimulus here
+
+\tend
+      
+endmodule
+
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: Jafet Chaves Barrantes
+// 
+// Create Date:    15:45:17 04/03/2016 
+// Design Name: 
+// Module Name:    contador_AD_MM_2dig 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module contador_AD_MM_2dig
+(
+input wire clk,
+input wire reset,
+input wire [3:0] en_count,
+input wire enUP,
+input wire enDOWN,
+output wire [7:0] data_MM
+);
+
+localparam N = 6; // Para definir el n\xfamero de bits del contador (hasta 59->6 bits)
+//Declaraci\xf3n de se\xf1ales
+reg [N-1:0] q_act, q_next;
+wire [N-1:0] count_data;
+reg [3:0] digit1, digit0;
+
+//Descripci\xf3n del comportamiento
+always@(posedge clk, posedge reset)
+begin\t
+\t
+\tif(reset)
+\tbegin
+\t\tq_act <= 6'b0;
+\tend
+\t
+\telse
+\tbegin
+\t\tq_act <= q_next;
+\tend
+end
+
+
+//L\xf3gica de salida
+always@*
+begin
+
+\tif (en_count == 2)
+\tbegin
+\t\tif (enUP)
+\t\tbegin
+\t\t\tif (q_act >= 6'd59) q_next = 6'd0;
+\t\t\telse q_next = q_act + 6'd1;
+\t\tend
+\t\t
+\t\telse if (enDOWN)
+\t\tbegin
+\t\t\tif (q_act == 6'd0) q_next = 6'd59;
+\t\t\telse q_next = q_act - 6'd1;
+\t\tend
+\t\telse q_next = q_act;
+\tend
+\telse q_next = q_act;
+\t
+end
+
+assign count_data = q_act;
+
+//Decodificaci\xf3n BCD (2 d\xedgitos)
+
+always@*
+begin
+case(count_data)
+6'd0: begin digit1 = 4'b0000; digit0 = 4'b0000; end
+6'd1: begin digit1 = 4'b0000; digit0 = 4'b0001; end
+6'd2: begin digit1 = 4'b0000; digit0 = 4'b0010; end
+6'd3: begin digit1 = 4'b0000; digit0 = 4'b0011; end
+6'd4: begin digit1 = 4'b0000; digit0 = 4'b0100; end
+6'd5: begin digit1 = 4'b0000; digit0 = 4'b0101; end
+6'd6: begin digit1 = 4'b0000; digit0 = 4'b0110; end
+6'd7: begin digit1 = 4'b0000; digit0 = 4'b0111; end
+6'd8: begin digit1 = 4'b0000; digit0 = 4'b1000; end
+6'd9: begin digit1 = 4'b0000; digit0 = 4'b1001; end
+
+6'd10: begin digit1 = 4'b0001; digit0 = 4'b0000; end
+6'd11: begin digit1 = 4'b0001; digit0 = 4'b0001; end
+6'd12: begin digit1 = 4'b0001; digit0 = 4'b0010; end
+6'd13: begin digit1 = 4'b0001; digit0 = 4'b0011; end
+6'd14: begin digit1 = 4'b0001; digit0 = 4'b0100; end
+6'd15: begin digit1 = 4'b0001; digit0 = 4'b0101; end
+6'd16: begin digit1 = 4'b0001; digit0 = 4'b0110; end
+6'd17: begin digit1 = 4'b0001; digit0 = 4'b0111; end
+6'd18: begin digit1 = 4'b0001; digit0 = 4'b1000; end
+6'd19: begin digit1 = 4'b0001; digit0 = 4'b1001; end
+
+6'd20: begin digit1 = 4'b0010; digit0 = 4'b0000; end
+6'd21: begin digit1 = 4'b0010; digit0 = 4'b0001; end
+6'd22: begin digit1 = 4'b0010; digit0 = 4'b0010; end
+6'd23: begin digit1 = 4'b0010; digit0 = 4'b0011; end
+6'd24: begin digit1 = 4'b0010; digit0 = 4'b0100; end
+6'd25: begin digit1 = 4'b0010; digit0 = 4'b0101; end
+6'd26: begin digit1 = 4'b0010; digit0 = 4'b0110; end
+6'd27: begin digit1 = 4'b0010; digit0 = 4'b0111; end
+6'd28: begin digit1 = 4'b0010; digit0 = 4'b1000; end
+6'd29: begin digit1 = 4'b0010; digit0 = 4'b1001; end
+
+6'd30: begin digit1 = 4'b0011; digit0 = 4'b0000; end
+6'd31: begin digit1 = 4'b0011; digit0 = 4'b0001; end
+6'd32: begin digit1 = 4'b0011; digit0 = 4'b0010; end
+6'd33: begin digit1 = 4'b0011; digit0 = 4'b0011; end
+6'd34: begin digit1 = 4'b0011; digit0 = 4'b0100; end
+6'd35: begin digit1 = 4'b0011; digit0 = 4'b0101; end
+6'd36: begin digit1 = 4'b0011; digit0 = 4'b0110; end
+6'd37: begin digit1 = 4'b0011; digit0 = 4'b0111; end
+6'd38: begin digit1 = 4'b0011; digit0 = 4'b1000; end
+6'd39: begin digit1 = 4'b0011; digit0 = 4'b1001; end
+
+6'd40: begin digit1 = 4'b0100; digit0 = 4'b0000; end
+6'd41: begin digit1 = 4'b0100; digit0 = 4'b0001; end
+6'd42: begin digit1 = 4'b0100; digit0 = 4'b0010; end
+6'd43: begin digit1 = 4'b0100; digit0 = 4'b0011; end
+6'd44: begin digit1 = 4'b0100; digit0 = 4'b0100; end
+6'd45: begin digit1 = 4'b0100; digit0 = 4'b0101; end
+6'd46: begin digit1 = 4'b0100; digit0 = 4'b0110; end
+6'd47: begin digit1 = 4'b0100; digit0 = 4'b0111; end
+6'd48: begin digit1 = 4'b0100; digit0 = 4'b1000; end
+6'd49: begin digit1 = 4'b0100; digit0 = 4'b1001; end
+
+6'd50: begin digit1 = 4'b0101; digit0 = 4'b0000; end
+6'd51: begin digit1 = 4'b0101; digit0 = 4'b0001; end
+6'd52: begin digit1 = 4'b0101; digit0 = 4'b0010; end
+6'd53: begin digit1 = 4'b0101; digit0 = 4'b0011; end
+6'd54: begin digit1 = 4'b0101; digit0 = 4'b0100; end
+6'd55: begin digit1 = 4'b0101; digit0 = 4'b0101; end
+6'd56: begin digit1 = 4'b0101; digit0 = 4'b0110; end
+6'd57: begin digit1 = 4'b0101; digit0 = 4'b0111; end
+6'd58: begin digit1 = 4'b0101; digit0 = 4'b1000; end
+6'd59: begin digit1 = 4'b0101; digit0 = 4'b1001; end
+
+
+default:  begin digit1 = 0; digit0 = 0; end
+endcase
+end
+
+assign data_MM = {digit1,digit0};
+
+endmodule
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: Jafet Chaves Barrantes
+// 
+// Create Date:    15:45:17 04/03/2016 
+// Design Name: 
+// Module Name:    contador_AD_SS_T_2dig 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module contador_AD_SS_T_2dig
+(
+input wire clk,
+input wire reset,
+input wire [3:0] en_count,
+input wire enUP,
+input wire enDOWN,
+output wire [7:0] data_SS_T
+);
+
+localparam N = 6; // Para definir el n\xfamero de bits del contador (hasta 59->6 bits)
+//Declaraci\xf3n de se\xf1ales
+reg [N-1:0] q_act, q_next;
+wire [N-1:0] count_data;
+reg [3:0] digit1, digit0;
+
+//Descripci\xf3n del comportamiento
+always@(posedge clk, posedge reset)
+begin\t
+\t
+\tif(reset)
+\tbegin
+\t\tq_act <= 6'b0;
+\tend
+\t
+\telse
+\tbegin
+\t\tq_act <= q_next;
+\tend
+end
+
+
+//L\xf3gica de salida
+
+always@*
+begin
+
+\tif (en_count == 8)
+\tbegin
+\t\tif (enUP)
+\t\tbegin
+\t\t\tif (q_act >= 6'd59) q_next = 6'd0;
+\t\t\telse q_next = q_act + 6'd1;
+\t\tend
+\t\t
+\t\telse if (enDOWN)
+\t\tbegin
+\t\t\tif (q_act == 6'd0) q_next = 6'd59;
+\t\t\telse q_next = q_act - 6'd1;
+\t\tend
+\t\telse q_next = q_act;
+\tend
+\telse q_next = q_act;
+\t
+end
+
+assign count_data = q_act;
+
+//Decodificaci\xf3n BCD (2 d\xedgitos)
+
+always@*
+begin
+case(count_data)
+6'd0: begin digit1 = 4'b0000; digit0 = 4'b0000; end
+6'd1: begin digit1 = 4'b0000; digit0 = 4'b0001; end
+6'd2: begin digit1 = 4'b0000; digit0 = 4'b0010; end
+6'd3: begin digit1 = 4'b0000; digit0 = 4'b0011; end
+6'd4: begin digit1 = 4'b0000; digit0 = 4'b0100; end
+6'd5: begin digit1 = 4'b0000; digit0 = 4'b0101; end
+6'd6: begin digit1 = 4'b0000; digit0 = 4'b0110; end
+6'd7: begin digit1 = 4'b0000; digit0 = 4'b0111; end
+6'd8: begin digit1 = 4'b0000; digit0 = 4'b1000; end
+6'd9: begin digit1 = 4'b0000; digit0 = 4'b1001; end
+
+6'd10: begin digit1 = 4'b0001; digit0 = 4'b0000; end
+6'd11: begin digit1 = 4'b0001; digit0 = 4'b0001; end
+6'd12: begin digit1 = 4'b0001; digit0 = 4'b0010; end
+6'd13: begin digit1 = 4'b0001; digit0 = 4'b0011; end
+6'd14: begin digit1 = 4'b0001; digit0 = 4'b0100; end
+6'd15: begin digit1 = 4'b0001; digit0 = 4'b0101; end
+6'd16: begin digit1 = 4'b0001; digit0 = 4'b0110; end
+6'd17: begin digit1 = 4'b0001; digit0 = 4'b0111; end
+6'd18: begin digit1 = 4'b0001; digit0 = 4'b1000; end
+6'd19: begin digit1 = 4'b0001; digit0 = 4'b1001; end
+
+6'd20: begin digit1 = 4'b0010; digit0 = 4'b0000; end
+6'd21: begin digit1 = 4'b0010; digit0 = 4'b0001; end
+6'd22: begin digit1 = 4'b0010; digit0 = 4'b0010; end
+6'd23: begin digit1 = 4'b0010; digit0 = 4'b0011; end
+6'd24: begin digit1 = 4'b0010; digit0 = 4'b0100; end
+6'd25: begin digit1 = 4'b0010; digit0 = 4'b0101; end
+6'd26: begin digit1 = 4'b0010; digit0 = 4'b0110; end
+6'd27: begin digit1 = 4'b0010; digit0 = 4'b0111; end
+6'd28: begin digit1 = 4'b0010; digit0 = 4'b1000; end
+6'd29: begin digit1 = 4'b0010; digit0 = 4'b1001; end
+
+6'd30: begin digit1 = 4'b0011; digit0 = 4'b0000; end
+6'd31: begin digit1 = 4'b0011; digit0 = 4'b0001; end
+6'd32: begin digit1 = 4'b0011; digit0 = 4'b0010; end
+6'd33: begin digit1 = 4'b0011; digit0 = 4'b0011; end
+6'd34: begin digit1 = 4'b0011; digit0 = 4'b0100; end
+6'd35: begin digit1 = 4'b0011; digit0 = 4'b0101; end
+6'd36: begin digit1 = 4'b0011; digit0 = 4'b0110; end
+6'd37: begin digit1 = 4'b0011; digit0 = 4'b0111; end
+6'd38: begin digit1 = 4'b0011; digit0 = 4'b1000; end
+6'd39: begin digit1 = 4'b0011; digit0 = 4'b1001; end
+
+6'd40: begin digit1 = 4'b0100; digit0 = 4'b0000; end
+6'd41: begin digit1 = 4'b0100; digit0 = 4'b0001; end
+6'd42: begin digit1 = 4'b0100; digit0 = 4'b0010; end
+6'd43: begin digit1 = 4'b0100; digit0 = 4'b0011; end
+6'd44: begin digit1 = 4'b0100; digit0 = 4'b0100; end
+6'd45: begin digit1 = 4'b0100; digit0 = 4'b0101; end
+6'd46: begin digit1 = 4'b0100; digit0 = 4'b0110; end
+6'd47: begin digit1 = 4'b0100; digit0 = 4'b0111; end
+6'd48: begin digit1 = 4'b0100; digit0 = 4'b1000; end
+6'd49: begin digit1 = 4'b0100; digit0 = 4'b1001; end
+
+6'd50: begin digit1 = 4'b0101; digit0 = 4'b0000; end
+6'd51: begin digit1 = 4'b0101; digit0 = 4'b0001; end
+6'd52: begin digit1 = 4'b0101; digit0 = 4'b0010; end
+6'd53: begin digit1 = 4'b0101; digit0 = 4'b0011; end
+6'd54: begin digit1 = 4'b0101; digit0 = 4'b0100; end
+6'd55: begin digit1 = 4'b0101; digit0 = 4'b0101; end
+6'd56: begin digit1 = 4'b0101; digit0 = 4'b0110; end
+6'd57: begin digit1 = 4'b0101; digit0 = 4'b0111; end
+6'd58: begin digit1 = 4'b0101; digit0 = 4'b1000; end
+6'd59: begin digit1 = 4'b0101; digit0 = 4'b1001; end
+
+default:  begin digit1 = 0; digit0 = 0; end
+endcase
+end
+
+assign data_SS_T = {digit1,digit0};
+
+endmodule
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: Jafet Chaves Barrantes
+// 
+// Create Date:    15:45:17 04/03/2016 
+// Design Name: 
+// Module Name:    contador_AD_MES_2dig 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module contador_AD_MES_2dig
+(
+input wire clk,
+input wire reset,
+input wire [3:0] en_count,
+input wire enUP,
+input wire enDOWN,
+output wire [7:0] data_MES
+);
+
+localparam N = 4; // Para definir el n\xfamero de bits del contador (hasta 12->4 bits)
+//Declaraci\xf3n de se\xf1ales
+reg [N-1:0] q_act, q_next;
+wire [N-1:0] count_data;
+reg [3:0] digit1, digit0;
+
+//Descripci\xf3n del comportamiento
+always@(posedge clk, posedge reset)
+begin\t
+\t
+\tif(reset)
+\tbegin
+\t\tq_act <= 4'b0;
+\tend
+\t
+\telse
+\tbegin
+\t\tq_act <= q_next;
+\tend
+end
+
+
+//L\xf3gica de salida
+
+always@*
+begin
+
+\tif (en_count == 5)
+\tbegin
+\t\tif (enUP)
+\t\tbegin
+\t\t\tif (q_act >= 4'd11) q_next = 4'd0;
+\t\t\telse q_next = q_act + 4'd1;
+\t\tend
+\t\t
+\t\telse if (enDOWN)
+\t\tbegin
+\t\t\tif (q_act == 4'd0) q_next = 4'd11;
+\t\t\telse q_next = q_act - 4'd1;
+\t\tend
+\t\telse q_next = q_act;
+\tend
+\telse q_next = q_act;
+\t
+end
+
+assign count_data = q_act + 1'b1;//Suma 1 a todas las cuentas de 0->11 a 1->12
+
+//Decodificaci\xf3n BCD (2 d\xedgitos)
+
+always@*
+begin
+case(count_data)
+
+8'd1: begin digit1 = 4'b0000; digit0 = 4'b0001; end
+8'd2: begin digit1 = 4'b0000; digit0 = 4'b0010; end
+8'd3: begin digit1 = 4'b0000; digit0 = 4'b0011; end
+8'd4: begin digit1 = 4'b0000; digit0 = 4'b0100; end
+8'd5: begin digit1 = 4'b0000; digit0 = 4'b0101; end
+8'd6: begin digit1 = 4'b0000; digit0 = 4'b0110; end
+8'd7: begin digit1 = 4'b0000; digit0 = 4'b0111; end
+8'd8: begin digit1 = 4'b0000; digit0 = 4'b1000; end
+8'd9: begin digit1 = 4'b0000; digit0 = 4'b1001; end
+
+8'd10: begin digit1 = 4'b0001; digit0 = 4'b0000; end
+8'd11: begin digit1 = 4'b0001; digit0 = 4'b0001; end
+8'd12: begin digit1 = 4'b0001; digit0 = 4'b0010; end
+
+default:  begin digit1 = 0; digit0 = 0; end
+endcase
+end
+
+assign data_MES = {digit1,digit0};
+
+endmodule
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    15:38:41 03/01/2016 
+// Design Name: 
+// Module Name:    Registro_universal 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module Registro_Universal
+#(parameter N = 8) //N\xfamero de bits y c\xf3digo de decodificado para habilitar el registro
+(
+\tinput wire hold,
+\tinput wire [N-1:0]in_rtc_dato,
+\tinput wire [N-1:0]in_count_dato,
+\tinput wire clk, //system clock
+\tinput wire reset, //system reset
+\tinput wire chip_select, //Control data
+\toutput wire [N-1:0]out_dato
+);
+reg [N-1:0]reg_dato;
+reg [N-1:0]next_dato;
+
+//Secuencial
+always@(negedge clk, posedge reset)
+begin
+\tif(reset) reg_dato <= 0;
+\telse reg_dato <= next_dato;
+end
+
+//Combinacional
+always@*
+\tbegin
+\tif (~hold) begin
+\tcase(chip_select)
+\t1'b0: next_dato = in_rtc_dato;
+\t1'b1: next_dato = in_count_dato;
+\tendcase
+\tend
+\telse next_dato = reg_dato;
+\tend
+
+assign out_dato = reg_dato;
+
+endmodule
+
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    22:04:51 05/16/2016 
+// Design Name: 
+// Module Name:    Controlador_reloj_digital 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module Controlador_reloj_digital(
+\t\tinput clk,reset,
+\t\toutput reg_a_d,reg_cs,reg_rd,reg_wr,
+\t\toutput [7:0]port_id,out_port,fin_lectura_escritura,
+\t\tinout [7:0]dato
+    );
+
+// CABLES DECONEXION DEL PICOBLAZE
+wire [11:0]address;
+wire [17:0]instruction;
+wire bram_enable; 
+reg [7:0]in_port;
+//wire [7:0]out_port;
+//wire [7:0]port_id;
+wire write_strobe;
+wire k_write_strobe;
+wire read_strobe;
+wire interrupt;
+wire interrupt_ack;
+wire sleep;
+wire rst;
+wire flag_done;
+reg [7:0]fin_lectura_escritura;
+wire [7:0]out_dato;
+
+reg state_reg_flag,state_next_flag;
+
+assign interrupt = 0;
+assign interrupt_ack = 0;
+assign sleep = 0;
+
+/// INTANCIACION DE MICROCONTROLADOR PICOBLAZE
+kcpsm6 microntroller_picoblaze (
+    .address(address), 
+    .instruction(instruction), 
+    .bram_enable(bram_enable), 
+    .in_port(in_port), 
+    .out_port(out_port), 
+    .port_id(port_id), 
+    .write_strobe(write_strobe), 
+    .k_write_strobe(k_write_strobe), 
+    .read_strobe(read_strobe), 
+    .interrupt(interrupt), 
+    .interrupt_ack(interrupt_ack), 
+    .sleep(sleep), 
+    .reset(rst), 
+    .clk(clk)
+    ); 
+\t 
+/// MEMORIA DE INSTRUCCIONES ROM
+ROM_programa ROM_0 (
+    .address(address), 
+    .instruction(instruction), 
+    .enable(bram_enable), 
+    .rdl(rst), 
+    .clk(clk)
+    );
+\t 
+escritor_lector_rtc instance_escritor_lector_rtc (
+    .clk(clk), 
+    .reset(reset), 
+    .port_id(port_id), 
+    .in_dato(out_port), 
+    .write_strobe(write_strobe), 
+    .read_strobe(read_strobe), 
+    .reg_a_d(reg_a_d), 
+    .reg_cs(reg_cs), 
+    .reg_rd(reg_rd), 
+    .reg_wr(reg_wr), 
+    .out_dato(out_dato), 
+    .fin_lectura_escritura(flag_done), 
+    .dato(dato)
+    );
+
+ always @ (posedge clk)
+  begin
+      case (port_id) 
+\t\t\t8'h0F : in_port <= fin_lectura_escritura;
+\t\t\t8'h10 : in_port <= out_dato;
+        default : in_port <= 8'bXXXXXXXX ;  
+      endcase
+  end
+  
+/// maquina de estados para manipular fin lectura escritura
+always @ (negedge clk,posedge reset) begin 
+\tif (reset) state_reg_flag = 1'b0;
+\telse state_reg_flag = state_next_flag;
+end
+
+always@ (*) begin
+state_next_flag = state_reg_flag;
+\tcase (state_reg_flag)
+\t1'b0: begin
+\t\tfin_lectura_escritura = 8'h00;
+\t\tif (flag_done == 1) state_next_flag = 1'b1;
+\t\telse state_next_flag = 1'b0;
+\t\tend
+\t1'b1: begin
+\t\tfin_lectura_escritura = 8'h01;
+\t\tif(port_id == 8'h0F && read_strobe == 1)  state_next_flag = 1'b0;
+\t\telse  state_next_flag = 1'b1; \t\t
+\tend
+\tendcase
+end
+endmodule
+"
+"`include ""dffe32.v""
+module regfile(rna, rnb, d, wn, we, clk, clrn, qa, qb, reg_addr, reg_out );
+  input [4:0] rna, rnb, wn;
+  input [31:0] d;
+  input clk, clrn, we;
+  output [31:0] qa, qb;
+  
+  input [4:0] reg_addr;
+  output [31:0] reg_out;
+  
+  wire [31:0] e;
+  wire [31:0] r00, r01, r02, r03, r04, r05, r06, r07;
+  wire [31:0] r08, r09, r10, r11, r12, r13, r14, r15;
+  wire [31:0] r16, r17, r18, r19, r20, r21, r22, r23;
+  wire [31:0] r24, r25, r26, r27, r28, r29, r30, r31;
+  
+  
+  dec5e decoder(wn, we, e);
+  assign r00 = 0;
+  dffe32 reg01 (d, clk, clrn, e[01], r01);
+  dffe32 reg02 (d, clk, clrn, e[02], r02);
+  dffe32 reg03 (d, clk, clrn, e[03], r03);
+  dffe32 reg04 (d, clk, clrn, e[04], r04);
+  dffe32 reg05 (d, clk, clrn, e[05], r05);
+  dffe32 reg06 (d, clk, clrn, e[06], r06);
+  dffe32 reg07 (d, clk, clrn, e[07], r07);
+  dffe32 reg08 (d, clk, clrn, e[08], r08);
+  dffe32 reg09 (d, clk, clrn, e[09], r09);
+  dffe32 reg10 (d, clk, clrn, e[10], r10);
+  dffe32 reg11 (d, clk, clrn, e[11], r11);
+  dffe32 reg12 (d, clk, clrn, e[12], r12);
+  dffe32 reg13 (d, clk, clrn, e[13], r13);
+  dffe32 reg14 (d, clk, clrn, e[14], r14);
+  dffe32 reg15 (d, clk, clrn, e[15], r15);
+  dffe32 reg16 (d, clk, clrn, e[16], r16);
+  dffe32 reg17 (d, clk, clrn, e[17], r17);
+  dffe32 reg18 (d, clk, clrn, e[18], r18);
+  dffe32 reg19 (d, clk, clrn, e[19], r19);
+  dffe32 reg20 (d, clk, clrn, e[20], r20);
+  dffe32 reg21 (d, clk, clrn, e[21], r21);
+  dffe32 reg22 (d, clk, clrn, e[22], r22);
+  dffe32 reg23 (d, clk, clrn, e[23], r23);
+  dffe32 reg24 (d, clk, clrn, e[24], r24);
+  dffe32 reg25 (d, clk, clrn, e[25], r25);
+  dffe32 reg26 (d, clk, clrn, e[26], r26);
+  dffe32 reg27 (d, clk, clrn, e[27], r27);
+  dffe32 reg28 (d, clk, clrn, e[28], r28);
+  dffe32 reg29 (d, clk, clrn, e[29], r29);
+  dffe32 reg30 (d, clk, clrn, e[30], r30);
+  dffe32 reg31 (d, clk, clrn, e[31], r31);
+
+  function [31:0] select;
+    input [31:0] r00, r01, r02, r03, r04, r05, r06, r07, r08, r09, r10, r11, r12, r13, r14, r15,                       
+                r16, r17, r18, r19, r20, r21, r22, r23, r24, r25, r26, r27, r28, r29, r30, r31;
+   input [4:0] s;
+   case(s)
+     5\'d00: select = r00;
+     5\'d01: select = r01;
+     5\'d02: select = r02;
+     5\'d03: select = r03;
+     5\'d04: select = r04;
+     5\'d05: select = r05;
+     5\'d06: select = r06;
+     5\'d07: select = r07;
+     5\'d08: select = r08;
+     5\'d09: select = r09;
+     5\'d10: select = r10;
+     5\'d11: select = r11;
+     5\'d12: select = r12;
+     5\'d13: select = r13;
+     5\'d14: select = r14;
+     5\'d15: select = r15;
+     5\'d16: select = r16;
+     5\'d17: select = r17;
+     5\'d18: select = r18;
+     5\'d19: select = r19;
+     5\'d20: select = r20;
+     5\'d21: select = r21;
+     5\'d22: select = r22;
+     5\'d23: select = r23;
+     5\'d24: select = r24;
+     5\'d25: select = r25;
+     5\'d26: select = r26;
+     5\'d27: select = r27;
+     5\'d28: select = r28;
+     5\'d29: select = r29;
+     5\'d30: select = r30;
+     5\'d31: select = r31;
+    endcase
+  endfunction
+   assign qa = select(r00, r01, r02, r03, r04, r05, r06, r07, r08, r09, r10, r11, r12, r13, r14, r15,
+                     r16, r17, r18, r19, r20, r21, r22, r23, r24, r25, r26, r27, r28, r29, r30, r31, rna);
+   assign qb = select(r00, r01, r02, r03, r04, r05, r06, r07, r08, r09, r10, r11, r12, r13, r14, r15,
+                     r16, r17, r18, r19, r20, r21, r22, r23, r24, r25, r26, r27, r28, r29, r30, r31, rnb);
+\tassign reg_out = select(r00, r01, r02, r03, r04, r05, r06, r07, r08, r09, r10, r11, r12, r13, r14, r15,
+                     r16, r17, r18, r19, r20, r21, r22, r23, r24, r25, r26, r27, r28, r29, r30, r31, reg_addr);
+endmodule
+
+module dec5e(n, ena, e);
+  input [4:0] n;
+  input ena;
+  output [31:0] e;
+  
+  function [31:0] decoder;
+    input [4:0] n;
+    input ena;
+    if(ena == 1\'b0) decoder = 32\'h00000000;
+    else begin
+      case(n)
+       5\'b00000: decoder = 32\'h00000001;
+       5\'b00001: decoder = 32\'h00000002;
+       5\'b00010: decoder = 32\'h00000004;
+       5\'b00011: decoder = 32\'h00000008;
+       5\'b00100: decoder = 32\'h00000010;
+       5\'b00101: decoder = 32\'h00000020;
+       5\'b00110: decoder = 32\'h00000040;
+       5\'b00111: decoder = 32\'h00000080;
+       5\'b01000: decoder = 32\'h00000100;
+       5\'b01001: decoder = 32\'h00000200;
+       5\'b01010: decoder = 32\'h00000400;
+       5\'b01011: decoder = 32\'h00000800;
+       5\'b01100: decoder = 32\'h00001000;
+       5\'b01101: decoder = 32\'h00002000;
+       5\'b01110: decoder = 32\'h00004000;
+       5\'b01111: decoder = 32\'h00008000;
+       5\'b10000: decoder = 32\'h00010000;
+       5\'b10001: decoder = 32\'h00020000;
+       5\'b10010: decoder = 32\'h00040000;
+       5\'b10011: decoder = 32\'h00080000;
+       5\'b10100: decoder = 32\'h00100000;
+       5\'b10101: decoder = 32\'h00200000;
+       5\'b10110: decoder = 32\'h00400000;
+       5\'b10111: decoder = 32\'h00800000;
+       5\'b11000: decoder = 32\'h01000000;
+       5\'b11001: decoder = 32\'h02000000;
+       5\'b11010: decoder = 32\'h04000000;
+       5\'b11011: decoder = 32\'h08000000;
+       5\'b11100: decoder = 32\'h10000000;
+       5\'b11101: decoder = 32\'h20000000;
+       5\'b11110: decoder = 32\'h40000000;
+       5\'b11111: decoder = 32\'h80000000;
+    endcase
+    end
+  endfunction
+  assign e = decoder(n, ena);
+endmodule"
+"module led (
+input  [15:0] x,
+input  clk,
+input  clr,
+output reg [6:0] a_to_g,
+output reg [3:0] an,
+output wire dp
+);
+wire [1:0] s;
+reg  [3:0] digit;
+wire [3:0] aen;
+reg  [19:0] clkdiv;
+assign dp = 1;
+assign s[0] = clkdiv[18]; // count every 5.2 ms\r
+assign s[1] = clkdiv[17];
+assign aen = 4'b1111; // enable all digits
+always @ ( * ) begin
+case (s)
+ 2'b00: digit = x[3:0];
+ 2'b01: digit = x[7:4];\r
+ 2'b10: digit = x[11:8];\r
+ 2'b11: digit = x[15:12];
+ default: digit = x[3:0];
+endcase\r
+end\r
+
+// 7 \xb6\xce\xca\xfd\xc2\xeb\xb9\xdc\xa3\xbahex7seg
+always @ ( * )
+case (digit)
+ 0: a_to_g = 7'b0000001;
+ 1: a_to_g = 7'b1001111;
+ 2: a_to_g = 7'b0010010;
+ 3: a_to_g = 7'b0000110;
+ 4: a_to_g = 7'b1001100;
+ 5: a_to_g = 7'b0100100;
+ 6: a_to_g = 7'b0100000;
+ 7: a_to_g = 7'b0001111;
+ 8: a_to_g = 7'b0000000;
+ 9: a_to_g = 7'b0000100;
+ 'hA: a_to_g = 7'b0001000; \r
+ 'hB: a_to_g = 7'b1100000;
+ 'hC: a_to_g = 7'b0110001;
+ 'hD: a_to_g = 7'b1000010;
+ 'hE: a_to_g = 7'b0110000;
+ 'hF: a_to_g = 7'b0111000;
+ default: a_to_g = 7'b0000001; // 0
+endcase\r
+
+// Digit select: ancode
+always @ ( * )
+begin
+an = 4'b1111;\r
+if (aen[s] == 1)
+\tan[s] = 0;
+end\r
+
+// \xca\xb1\xd6\xd3\xb7\xd6\xc6\xb5\xc6\xf7
+always @ (posedge clk or posedge clr)
+begin
+ if (clr == 1)
+ clkdiv <= 0;
+ else
+ clkdiv <= clkdiv + 1;
+end
+endmodule\r"
+"module dffe32(d, clk, clrn, e, q);
+  input [31:0] d;
+  input clk, clrn, e;
+  output [31:0] q;
+  
+  reg [31:0] q;
+  always @ ( posedge clk or posedge clrn)
+    if( clrn==1 ) 
+   begin
+     q = 0;
+   end
+   else
+   begin
+     if(e)
+      q = d;
+   end
+endmodule
+"
+"module addsub32(
+input [31:0] A,
+input [31:0] B,
+input aluc1,
+input aluc0,
+output [31:0]Result,
+output Zero,
+output Carry,
+output Nagative,
+output Overflow
+);
+
+reg [31:0]Result_temp;
+reg Zero_temp;
+reg Carry_temp;
+reg Nagative_temp;
+reg Overflow_temp;
+
+assign Result   = Result_temp;
+assign Zero     = Zero_temp;
+assign Carry    = Carry_temp;
+assign Overflow = Overflow_temp;
+assign Nagative = Nagative_temp;
+
+always @* begin
+    if( aluc1 == 0 && aluc0 == 0 )begin//unsigned
+        Result_temp = A + B;
+        if( Result_temp == 0 )
+            Zero_temp = 1;
+        else
+            Zero_temp = 0;
+        if ( Result_temp < A || Result_temp < B ) Carry_temp = 1;
+        else Carry_temp = 0;                 
+        Nagative_temp = 0;
+        Overflow_temp = 0;
+     end
+     else if( aluc1 == 1 && aluc0 == 0 )begin//signed
+        Result_temp = A + B;
+        
+        if( Result_temp[31] == 1 )
+            Nagative_temp = 1;
+         else if( Result_temp[31] == 0 )
+            Nagative_temp = 0;
+         Carry_temp=0;
+         if ( A[31] & ~B[31]) Overflow_temp = 0; //A < 0, B >= 0, overflow = 0
+         else if ( ~A[31] & B[31] )  Overflow_temp = 0; // A >= 0, B < 0, overflow = 0
+         else if ( A[31] & B[31] & Result_temp[31] ) Overflow_temp = 0; // A < 0, B < 0, C < 0, overflow = 0
+         else if ( ~A[31] & ~B[31] & ~Result_temp[31]) Overflow_temp = 0; // A >= 0, B >= 0, C >= 0, overflow = 0
+         else begin
+                Overflow_temp = 1;
+                Result_temp = 0;
+                end
+        if( Result_temp == 0 )
+            Zero_temp = 1;
+        else 
+            Zero_temp = 0;
+     end
+     else if( aluc1 == 0 && aluc0 == 1 )begin//unsigned
+        Result_temp = A - B;
+        if( Result_temp == 0 )
+            Zero_temp = 1;
+         else 
+            Zero_temp = 0;
+        if( A >= B )
+            Carry_temp = 0;
+        else
+            Carry_temp = 1;
+        Nagative_temp = 0;
+        Overflow_temp = 0;
+     end
+     else if( aluc1 == 1 && aluc0 == 1 )begin//signed
+        Result_temp = A - B;      
+        Carry_temp = 0;
+        if ( A[31] & B[31]) Overflow_temp = 0; //A < 0, B < 0, overflow = 0
+        else if ( ~A[31] & ~B[31] )  Overflow_temp= 0; //A >= 0, B >= 0, overflow = 0
+        else if ( A[31] & ~B[31] & Result_temp[31] ) Overflow_temp = 0; //A < 0, B >= 0, R < 0, overflow = 0
+        else if ( ~A[31] & B[31] & ~Result_temp[31] )  Overflow_temp = 0; //A >= 0, B < 0, R > 0, overflow = 0
+        else begin
+            Overflow_temp = 1;
+            Result_temp = 0;
+        end
+        if( Result_temp == 0 )
+           Zero_temp = 1;
+        else 
+           Zero_temp = 0;
+        if( Result_temp[31] == 1 )
+           Nagative_temp = 1;
+        else if( Result_temp[31] == 0 )
+           Nagative_temp = 0; 
+     end
+end
+endmodule"
+"module shifter(
+input [31:0] A, // 32 \xe4\xbd\x8d\xe5\x8e\x9f\xe5\xa7\x8b\xe8\xbe\x93\xe5\x85\xa5\xe6\x95\xb0\xe6\x8d\xae
+input [31:0] B, // 5 \xe4\xbd\x8d\xe8\xbe\x93\xe5\x85\xa5\xe6\x95\xb0\xe6\x8d\xae\xef\xbc\x8c\xe6\x8e\xa7\xe5\x88\xb6\xe7\xa7\xbb\xe4\xbd\x8d\xe7\x9a\x84\xe4\xbd\x8d\xe6\x95\xb0
+//input [1:0] aluc, // 2 \xe4\xbd\x8d\xe8\xbe\x93\xe5\x85\xa5\xe6\x8e\xa7\xe5\x88\xb6\xe7\xa7\xbb\xe4\xbd\x8d\xe7\x9a\x84\xe6\x96\xb9\xe5\xbc\x8f
+input aluc1,//aluc[1]
+input aluc0,//aluc[0]
+output  [31:0] Result,// 32 \xe4\xbd\x8d\xe8\xbe\x93\xe5\x87\xba\xef\xbc\x8c\xe7\x94\xb1 A \xe7\xbb\x8f\xe8\xbf\x87 B \xe4\xbd\x8d\xe9\x80\x9a\xe8\xbf\x87 aluc \xe6\x8c\x87\xe5\xae\x9a\xe7\x9a\x84\xe7\xa7\xbb\xe4\xbd\x8d\xe6\x96\xb9\xe5\xbc\x8f\xe7\xa7\xbb\xe4\xbd\x8d\xe8\x80\x8c\xe5\xbe\x97
+output Zero,
+output Carry,
+output Negative,
+output Overflow
+);
+reg [31:0] Result_temp;
+reg Zero_temp;
+reg Carry_temp;
+reg Nagative_temp;
+reg Overflow_temp;
+reg [4:0] shift_amount;
+
+
+assign Zero     = Zero_temp;
+assign Carry    = Carry_temp;
+assign Negative = Nagative_temp;
+assign Overflow = Overflow_temp;
+assign Result   = Result_temp;
+
+always @(*) begin
+    if( aluc1 == 0 && aluc0 == 0 )begin //SRA
+        shift_amount = A[4:0];
+        Result_temp = $signed(B)>>>shift_amount;
+        if( Result_temp == 0 ) 
+            Zero_temp = 1;
+        else 
+            Zero_temp = 0;
+        Nagative_temp = B[31];
+        if ( shift_amount == 0) 
+            Carry_temp = 0;
+        else 
+            Carry_temp = B[shift_amount -1];
+        Overflow_temp = 0;
+        Nagative_temp=Result_temp[31];
+    end
+    else if( aluc1 == 0 && aluc0 == 1 )begin //SRL
+        shift_amount = A[4:0];
+        Result_temp = B >> shift_amount;
+        if(Result_temp==0) 
+            Zero_temp=1;
+        else 
+            Zero_temp=0;
+        if(shift_amount==0)
+            Carry_temp=0;
+        else
+        Carry_temp=B[shift_amount-1];
+        Overflow_temp=0;
+        Nagative_temp = Result_temp[31];
+    end
+    else if( aluc1 == 1 && aluc0 == 0 )begin  //SLL
+        shift_amount = A[4:0];
+        Result_temp = B<<shift_amount;
+        if ( Result_temp == 0)
+            Zero_temp = 1;
+        else 
+            Zero_temp = 0;
+        if ( shift_amount ==0)
+            Carry_temp = 0;
+        else 
+            Carry_temp=B[32-shift_amount]; 
+        Overflow_temp = 0;  
+        Nagative_temp = Result_temp[31];
+    end
+    else if( aluc1 == 1 && aluc0 == 1 )begin //SLL
+        shift_amount = A[4:0];
+        Result_temp=B<<shift_amount;
+        if (Result_temp == 0)
+            Zero_temp = 1;
+        else Zero_temp = 0;
+        if (shift_amount ==0)
+          Carry_temp = 0;
+        else 
+        Carry_temp=B[32-shift_amount];
+        Overflow_temp = 0;
+        Nagative_temp = Result_temp[31];
+    end
+end
+endmodule   "
+"module mux2x5(a0, a1, s, y);
+  input [4:0] a0, a1;
+  input s;
+  output [4:0] y;
+  assign y = s ? a1 : a0;
+endmodule
+
+module mux2x16(a0, a1, s, y);
+  input [15:0] a0, a1;
+  input s;
+  output [15:0] y;
+  assign y = s ? a1 : a0;
+endmodule
+
+module mux2x32(a0, a1, s, y);
+  input [31:0] a0, a1;
+  input s;
+  output [31:0] y;
+  assign y = s ? a1 : a0;
+endmodule
+
+module mux4x32(a0, a1, a2, a3, s, y);
+  input [31:0] a0, a1, a2, a3;
+  input [1:0] s;
+  output [31:0] y;
+  
+  function [31:0] select;
+    input [31:0] a0, a1, a2, a3;
+     input [1:0] s;
+     case(s)
+       2'b00: select = a0;
+       2'b01: select = a1; 
+       2'b10: select = a2;
+       2'b11: select = a3;
+     endcase
+  endfunction
+  assign y = select(a0, a1, a2, a3, s);
+endmodule
+"
+"`include ""sccpu_dataflow.v""
+`include ""scinstmem.v""
+`include ""scdatamem.v""
+module sccomp_dataflow(clock, resetn, pc, inst, aluout, memout,reg_addr,reg_out  );
+   input clock, resetn;
+   output [31:0] inst, pc, aluout, memout;   
+\tinput [4:0] reg_addr;
+\toutput [31:0] reg_out;
+
+   
+   wire [31:0] datatomem;
+   wire wmem;
+
+   sccpu_dataflow cpu( clock, resetn, inst, memout, pc, wmem, aluout, datatomem,reg_addr,reg_out );
+   iram_ip iram_ip (
+    .a(pc[11:2]), // input [9 : 0] a
+    .spo(inst) // output [31 : 0] spo
+    );
+\t 
+\t 
+ 
+  //scinstmem imem ( pc, inst );  
+  scdatamem dmem (clock,memout, datatomem, aluout, wmem );
+endmodule
+
+"
+"module cla32(a, b, ci, s, co);
+  input [31:0] a, b;
+  input ci;
+  output [31:0] s;
+  output co;
+  
+  wire  g_out, p_out;
+  cla_32 cla(a, b, ci, g_out, p_out, s);
+  assign co = g_out | p_out & ci;
+endmodule
+
+module cla_32(a, b, c_in, g_out, p_out, s);
+  input [31:0] a, b;
+  input c_in;
+  output g_out, p_out;
+  output [31:0] s;
+
+  wire [1:0] g, p;
+  wire c_out;
+  cla_16 cla0 (a[15:0] ,b[15:0], c_in, g[0], p[0], s[15:0]);
+  cla_16 cla1 (a[31:16], b[31:16], c_out, g[1], p[1], s[31:16]);
+  g_p g_p0 (g, p, c_in, g_out, p_out, c_out);
+endmodule
+
+module cla_16(a, b, c_in, g_out, p_out, s);
+  input [15:0] a, b;
+  input c_in;
+  output g_out, p_out;
+  output [15:0] s;
+
+  wire [1:0] g, p;
+  wire c_out;
+  cla_8 cla0 (a[7:0], b[7:0], c_in, g[0], p[0], s[7:0]);
+  cla_8 cla1 (a[15:8], b[15:8], c_out, g[1], p[1], s[15:8]);
+  g_p g_p0(g, p, c_in, g_out, p_out, c_out);
+endmodule
+
+module cla_8(a, b, c_in, g_out, p_out, s);
+  input [7:0] a, b;
+  input c_in;
+  output g_out, p_out;
+  output [7:0] s;
+
+  wire [1:0] g, p;
+  wire c_out;
+  
+  cla_4 cla0 (a[3:0], b[3:0], c_in, g[0], p[0], s[3:0]);
+  cla_4 cla1 (a[7:4], b[7:4], c_out, g[1], p[1], s[7:4]);
+  g_p g_p0(g, p, c_in, g_out, p_out, c_out);
+endmodule
+
+module cla_4(a, b, c_in, g_out, p_out, s);
+  input [3:0] a, b;
+  input c_in;
+  output g_out, p_out;
+  output [3:0] s;
+  wire [1:0] g, p;
+  wire c_out;
+  
+  cla_2 cla0 (a[1:0], b[1:0], c_in, g[0], p[0], s[1:0]);
+  cla_2 cla1 (a[3:2], b[3:2], c_out, g[1], p[1], s[3:2]);
+  g_p g_p0(g, p, c_in, g_out, p_out, c_out);
+endmodule
+
+module cla_2(a, b, c_in, g_out, p_out, s);
+  input [1:0] a, b;
+  input c_in;
+  output g_out, p_out;
+  output [1:0] s;
+  wire [1:0] g, p;
+  wire c_out;
+  
+  add add0 (a[0], b[0], c_in, g[0], p[0], s[0]);
+  add add1 (a[1], b[1], c_out, g[1], p[1], s[1]);
+  g_p g_p0(g, p, c_in, g_out, p_out, c_out);
+endmodule
+
+module add(a, b, c, g, p, s);
+  input a, b, c;
+  output g, p, s;
+  assign s = a ^ b ^ c;
+  assign g = a & b;
+  assign p = a | b;
+endmodule
+
+module g_p(g, p, c_in, g_out, p_out, c_out);
+  input [1:0] g, p;
+  input c_in;
+  output g_out, p_out, c_out;
+  assign g_out = g[1] | p[1] & g[0];
+  assign p_out = p[1] & p[0];
+  assign c_out = g[0] | p[0] & c_in; 
+endmodule"
+"module sccu_dataflow(op, func, z, wmem, rmem, wreg, regrt, m2reg, aluc, shift, aluimm, pcsource, jal, sext, wpc);
+  input [5:0] op, func;
+  input z;
+  output wreg, regrt, m2reg,shift, aluimm, jal, sext, wmem, rmem, wpc;
+  output [3:0] aluc;
+  output [1:0] pcsource;
+
+  wire r_type = ~|op;
+  wire i_add = r_type & func[5] & ~func[4] & ~func[3] & ~func[2] & ~func[1] & ~func[0];
+  wire i_addu = r_type & func[5] & ~func[4] & ~func[3] & ~func[2] & ~func[1] & func[0];
+  wire i_sub = r_type & func[5] & ~func[4] & ~func[3] & ~func[2] & func[1] & ~func[0];
+  wire i_subu = r_type & func[5] & ~func[4] & ~func[3] & ~func[2] & func[1] & func[0];
+  wire i_and = r_type & func[5] & ~func[4] & ~func[3] & func[2] & ~func[1] & ~func[0];
+  wire i_or  = r_type & func[5] & ~func[4] & ~func[3] & func[2] & ~func[1] & func[0];
+  wire i_xor = r_type & func[5] & ~func[4] & ~func[3] & func[2] & func[1] & ~func[0];
+  wire i_nor = r_type & func[5] & ~func[4] & ~func[3] & func[2] & func[1] & func[0];
+  wire i_slt = r_type & func[5] & ~func[4] & func[3] & ~func[2] & func[1] & ~func[0];
+  wire i_sltu = r_type & func[5] & ~func[4] & func[3] & ~func[2] & func[1] & func[0];
+  wire i_sll = r_type & ~func[5] & ~func[4] & ~func[3] & ~func[2] & ~func[1] & ~func[0];
+  wire i_srl = r_type & ~func[5] & ~func[4] & ~func[3] & ~func[2] & func[1] & ~func[0];
+  wire i_sra = r_type & ~func[5] & ~func[4] & ~func[3] & ~func[2] & func[1] & func[0];
+  wire i_sllv = r_type & ~func[5] & ~func[4] & ~func[3] & func[2] & ~func[1] & ~func[0];
+  wire i_srlv = r_type & ~func[5] & ~func[4] & ~func[3] & func[2] & func[1] & ~func[0];
+  wire i_srav = r_type & ~func[5] & ~func[4] & ~func[3] & func[2] & func[1] & func[0];
+  wire i_jr  = r_type & ~func[5] & ~func[4] & func[3] & ~func[2] & ~func[1] & ~func[0];
+  wire i_addi = ~op[5] & ~op[4] & op[3] & ~op[2] & ~op[1] & ~op[0];
+  wire i_addiu = ~op[5] & ~op[4] & op[3] & ~op[2] & ~op[1] & op[0];
+  wire i_andi = ~op[5] & ~op[4] & op[3] & op[2] & ~op[1] & ~op[0];
+  wire i_ori  = ~op[5] & ~op[4] & op[3] & op[2] & ~op[1] & op[0];      
+  wire i_xori = ~op[5] & ~op[4] & op[3] & op[2] & op[1] & ~op[0];
+  wire i_lw   = op[5] & ~op[4] & ~op[3] & ~op[2] & op[1] & op[0];
+  wire i_sw   = op[5] & ~op[4] & op[3] & ~op[2] & op[1] & op[0];
+  wire i_beq  = ~op[5] & ~op[4] & ~op[3] & op[2] & ~op[1] & ~op[0];
+  wire i_bne  = ~op[5] & ~op[4] & ~op[3] & op[2] & ~op[1] & op[0];
+  wire i_slti = ~op[5] & ~op[4] & op[3] & ~op[2] & op[1] & ~op[0];
+  wire i_sltiu = ~op[5] & ~op[4] & op[3] & ~op[2] & op[1] & op[0];
+  wire i_lui  = ~op[5] & ~op[4] & op[3] & op[2] & op[1] & op[0];
+  wire i_j    = ~op[5] & ~op[4] & ~op[3] & ~op[2] & op[1] & ~op[0];
+  wire i_jal  = ~op[5] & ~op[4] & ~op[3] & ~op[2] & op[1] & op[0];
+  
+  assign wreg    = i_add|i_addu|i_sub|i_subu|i_and|i_or|i_xor|i_nor|i_slt|i_sltu|i_sll|i_srl|i_sra|
+                   i_sllv|i_srlv|i_srav|i_addi|i_addiu|i_andi|i_ori|i_xori|i_lw|i_slti|i_sltiu|
+                         i_lui|i_jal;
+  assign regrt   = i_addi|i_addiu|i_andi|i_ori|i_xori|i_lw|i_lui|i_slti|i_sltiu;
+  assign jal     = i_jal;
+  assign m2reg   = i_lw;
+  assign shift   = i_sll|i_srl|i_sra;
+  assign aluimm  = i_addi|i_addiu|i_andi|i_ori|i_xori|i_lw|i_lui|i_sw|i_slti|i_sltiu;
+  assign sext    = i_addi|i_addiu|i_lw|i_sw|i_beq|i_bne|i_slti; //signed ext
+  assign aluc[3] = i_slt|i_sltu|i_sll|i_srl|i_sra|i_sllv|i_srlv|i_srav|i_sltiu|i_slti|i_lui;
+  
+  assign aluc[2] = i_and|i_andi|i_or|i_ori|i_xor|i_xori|i_nor|i_sll|i_srl|i_sra|i_sllv|i_srlv|i_srav;
+  
+  assign aluc[1] = i_add|i_sub|i_xor|i_nor|i_slt|i_sltu|i_sll|i_sllv|i_addi|i_xori|i_lw|i_sw|i_beq|i_bne|i_slti|i_sltiu;
+                         
+  assign aluc[0] = i_sub|i_subu|i_or|i_nor|i_slt|i_srl|i_srlv|i_ori|i_beq|i_bne|i_slti;
+  /*
+  ALUC =
+    AND && SUB (6 instructions):
+    0000:addu, addiu
+    0010:add, addi
+    0001:subu
+    0011:sub
+    SHIFT (6 instructions):
+    1100:sra, srav
+    1101:srl, srlv
+    1110:sll, sllv
+    1111:
+    AND OR XOR NOR (7 instructions):
+    0100:and, andi
+    0101:or, ori
+    0110:xor,xori
+    0111:nor
+    LUI SLT SLTI SLTU SLTIU (5 instructions):
+    100x:lui
+    1011:slt, slti
+    1010:sltu, sltiu
+
+    NUMBER OF INSTRUCTIONS:
+    6+6+7+5 = 24
+    REMAINING:
+    SW, LW
+    JR, J, JAL, BEQ, BNE
+  */
+  
+  assign wmem    = i_sw;
+  assign rmem    = i_lw;
+  assign pcsource[1] = i_jr|i_j|i_jal;
+  assign pcsource[0] = i_beq&z|i_bne&~z|i_j|i_jal;
+  assign wpc = i_jal;
+  
+endmodule "
+"`include ""mux.v""
+`include ""addsub32.v""
+`include ""shifter.v""
+
+module alu(
+input [31:0] a,
+input [31:0] b,
+input [3:0] aluc,
+output [31:0] r, 
+output zero,
+output carry,
+output negative,
+output overflow 
+);
+
+reg zero_temp;
+reg carry_temp;
+reg negative_temp;
+reg overflow_temp;
+reg [31:0] r_temp;
+
+assign r=r_temp;
+assign zero=zero_temp;
+assign carry=carry_temp;
+assign negative=negative_temp;
+assign overflow=overflow_temp;
+
+wire [31:0] result_temp [7:0];
+wire [7:0] zero_flag;
+wire [7:0] carry_flag;
+wire [7:0] negative_flag;
+wire [7:0] overflow_flag;
+
+addsub32 as32_1(a,b,aluc[1],aluc[0],result_temp[0],zero_flag[0],carry_flag[0],negative_flag[0],overflow_flag[0]);
+addsub32 as32_2(a,b,aluc[1],aluc[0],result_temp[1],zero_flag[1],carry_flag[1],negative_flag[1],overflow_flag[1]);
+addsub32 as32_3(a,b,aluc[1],aluc[0],result_temp[2],zero_flag[2],carry_flag[2],negative_flag[2],overflow_flag[2]);
+addsub32 as32_4(a,b,aluc[1],aluc[0],result_temp[3],zero_flag[3],carry_flag[3],negative_flag[3],overflow_flag[3]);
+shifter shift_1(a,b,aluc[1],aluc[0],result_temp[4],zero_flag[4],carry_flag[4],negative_flag[4],overflow_flag[4]);
+shifter shift_2(a,b,aluc[1],aluc[0],result_temp[5],zero_flag[5],carry_flag[5],negative_flag[5],overflow_flag[5]);
+shifter shift_3(a,b,aluc[1],aluc[0],result_temp[6],zero_flag[6],carry_flag[6],negative_flag[6],overflow_flag[6]);
+shifter shift_4(a,b,aluc[1],aluc[0],result_temp[7],zero_flag[7],carry_flag[7],negative_flag[7],overflow_flag[7]);
+
+always @(*) begin
+    casex(aluc)
+         4\'b0000:begin // a + b (unsigned)
+            r_temp=result_temp[0];
+            zero_temp=zero_flag[0];
+            carry_temp=carry_flag[0];
+            negative_temp=negative_flag[0];
+            overflow_temp=overflow_flag[0];
+        end
+        4\'b0010:begin // a + b (signed)
+            zero_temp=zero_flag[1];
+            carry_temp=carry_flag[1];
+            negative_temp=negative_flag[1];
+            overflow_temp=overflow_flag[1];
+            if ( ~overflow_temp ) begin //fix bug
+                r_temp=result_temp[3];
+            end
+        end
+        4\'b0001:begin // a - b(unsigned)
+            r_temp=result_temp[2];
+            zero_temp=zero_flag[2];
+            carry_temp=carry_flag[2];
+            negative_temp=negative_flag[2];
+            overflow_temp=overflow_flag[2];
+        end
+        4\'b0011:begin // a - b(signed)
+            zero_temp=zero_flag[3];
+            carry_temp=carry_flag[3];
+            negative_temp=negative_flag[3];
+            overflow_temp=overflow_flag[3];
+            if ( ~overflow_temp ) begin //fix bug
+                r_temp=result_temp[3];
+            end
+        end
+        4\'b1100: begin //sra
+            r_temp=result_temp[4];
+            zero_temp=zero_flag[4];
+            carry_temp=carry_flag[4];
+            negative_temp=negative_flag[4];
+            overflow_temp=overflow_flag[4];
+        end
+        4\'b1110:begin //srl
+            r_temp=result_temp[5];
+            zero_temp=zero_flag[5];
+            carry_temp=carry_flag[5];
+            negative_temp=negative_flag[5];
+            overflow_temp=overflow_flag[5];
+        end
+        4\'b1111:begin //sll
+            r_temp=result_temp[6];
+            zero_temp=zero_flag[6];
+            carry_temp=carry_flag[6];
+            negative_temp=negative_flag[6];
+            overflow_temp=overflow_flag[6];
+        end
+        4\'b1101:begin //slv
+            r_temp=result_temp[7];
+            zero_temp=zero_flag[7];
+            carry_temp=carry_flag[7];
+            negative_temp=negative_flag[7];
+            overflow_temp=overflow_flag[7];
+        end
+        4\'b0100:begin // AND
+            r_temp = a & b; 
+            if( r_temp == 0 )
+                zero_temp = 1;
+            else 
+                zero_temp = 0;
+            carry_temp = 0;
+            overflow_temp = 0;
+            if( r_temp[31] == 1 )
+               negative_temp = 1;
+            else if( r_temp[31] == 0 )
+               negative_temp = 0;
+        end
+        4\'b0101: begin //OR
+            r_temp = a | b;
+            if( r_temp == 0 )
+                zero_temp=1;
+            else 
+                zero_temp=0;
+            carry_temp=0;
+            overflow_temp=0;
+            if( r_temp[31] == 1 )
+                negative_temp = 1;
+            else if( r_temp[31] == 0 )
+                negative_temp=0;
+        end  
+        4\'b0110:begin //XOR
+            r_temp = a^b;
+            if(r_temp==0)
+                zero_temp=1;
+            else 
+                zero_temp=0;
+            carry_temp=0;
+            overflow_temp=0;
+            if( r_temp[31] == 1 )
+               negative_temp = 1;
+            else if(r_temp[31] == 0 )
+               negative_temp = 0;
+        end 
+        4\'b0111:begin //NOR
+            r_temp = ~(a|b);
+            if( r_temp == 0 )
+                zero_temp = 1;
+            else 
+                zero_temp = 0;
+            carry_temp=0;
+            overflow_temp=0;
+            if(r_temp[31]==1)
+                negative_temp=1;
+            else if(r_temp[31]==0)
+            negative_temp=0;
+        end  
+        4\'b1000:begin //LUI
+            r_temp = {b[15:0],16\'b0};
+            if (r_temp == 0 )
+                zero_temp = 1;
+            else zero_temp = 0;
+            if (r_temp[31])
+                negative_temp = 1;
+            else negative_temp = 0;
+            carry_temp = 0;
+            overflow_temp = 0;
+        end
+        4\'b1001:begin //LUI
+            r_temp = {b[15:0],16\'b0};
+            if (r_temp ==0)
+                zero_temp =1;
+            else zero_temp = 0;
+            if (r_temp[31])
+              negative_temp = 1;
+            else negative_temp = 0;
+            carry_temp = 0;
+            overflow_temp = 0;
+        end
+        4\'b1011:begin //SLT, SLTI
+            r_temp=($signed(a)<$signed(b))?1:0;
+        end
+        4\'b1010:begin //SLTU, SLTIU
+            r_temp=(a<b)?1:0;
+        end
+    endcase
+end    
+endmodule"
+"module scinstmem #(parameter DEPTH = 1000)(
+  input [31:0] pc,
+  output [31:0] inst
+  );
+  
+  reg [31:0] ram [DEPTH-1:0];
+  assign inst = ram[pc[31:2]];
+  
+  integer i;
+  initial
+    begin 
+     for(i=0; i<32; i=i+1)
+      ram[i] = 0;  
+      $readmemh(""C:/Users/Lumit/Downloads/CPUtest/_2_lwsw.hex.txt"", ram);
+    end
+endmodule"
+"module scdatamem #(parameter DEPTH = 2000)(
+input clk, 
+output [31:0] dataout,
+input [31:0] datain,
+input [31:0] addr,
+input we
+);
+
+reg [31:0] ram[0:DEPTH-1];
+//assign dataout = ram[addr[15:0]];
+assign dataout = ram[addr];
+
+always@(posedge clk) begin
+\tif(we) ram[addr] = datain;
+end
+endmodule
+"
+"`timescale 1ns / 1ps
+
+module sccomp_top(clock, resetn, inst, pc, aluout, memout,  a_to_g,  an, dp, reg_addr, ispc, hl );
+  input clock, resetn;
+  output [31:0] inst, pc, aluout, memout; 
+  output  [6:0] a_to_g;
+  output  [3:0] an;
+  output  dp;
+  input [4:0] reg_addr;
+  input ispc;
+  input hl;
+
+  wire outclock;
+  re_hz re_hz(clock, resetn, outclock);
+  wire [31:0] reg_out;
+  wire [31:0] data_show;
+  wire [15:0] data_out;
+
+  
+  sccomp_dataflow sccomp( outclock, resetn, pc, inst, aluout, memout, reg_addr, reg_out );
+  //assign reg_22 = sccomp_top.sccomp.cpu.rf.reg22.q;
+  
+  //led led( inst[15:0], clock, resetn,  a_to_g, an, dp );
+  mux2x32 mux1(reg_out,pc,ispc,data_show);
+  mux2x16 mux2(data_show[15:0],data_show[31:16],hl, data_out);
+  
+  led led( data_out[15:0], clock, resetn,  a_to_g, an, dp );
+
+
+endmodule
+
+module re_hz( 
+input clock,
+input resetn,
+output outclock
+);
+
+reg [31:0] cnt;
+always @( posedge clock or posedge resetn)  begin
+  if( resetn == 1 )
+    cnt = 0;
+  else 
+    cnt = cnt + 1;
+end
+  assign outclock = cnt[21];
+endmodule"
+"`include ""sccu_dataflow.v""
+`include ""cla32.v""
+`include ""alu.v""
+`include ""regfile.v""
+
+module sccpu_dataflow(clock, resetn, inst, memout, pc, wmem, aluout, data2mem, reg_addr, reg_out );
+  input [31:0] inst, memout;  
+  input clock, resetn;
+  output [31:0] pc, aluout, data2mem;  
+  output wmem;
+  input [4:0]reg_addr;
+  output [31:0] reg_out;
+
+  wire [1:0] pcsource;  //\xcf\xc2\xd2\xbb\xcc\xf5\xd6\xb8\xc1\xee\xb5\xc4\xb5\xd8\xd6\xb7\xd1\xa1\xd4\xf1\xd0\xc5\xba\xc5  00\xce\xaapc+4, 01\xd1\xa1\xd7\xaa\xd2\xc6\xb5\xd8\xd6\xb7\xa3\xac10\xd1\xa1\xbc\xc4\xb4\xe6\xc6\xf7\xc4\xda\xb5\xc4\xb5\xd8\xd6\xb7\xa3\xac11\xd1\xa1\xcc\xf8\xd7\xaa\xb5\xd8\xd6\xb7
+  wire [3:0] aluc;  //ALU\xbf\xd8\xd6\xc6\xb2\xd9\xd7\xf7  
+  wire zero;  //\xc1\xe3\xb1\xea\xd6\xbe\xce\xbb beq,bnq
+  wire wmem;  //\xd0\xb4\xc8\xeb\xc4\xda\xb4\xe6dmem\xa3\xac\xce\xaa1\xca\xb1\xd0\xb4\xc8\xeb\xa3\xac\xb7\xf1\xd4\xf2\xb2\xbb\xd0\xb4\xa3\xac\xd4\xdalw\xa3\xacsw\xd6\xb8\xc1\xee\xd6\xd0
+  wire wreg;  //\xd0\xb4\xbc\xc4\xb4\xe6\xc6\xf7\xb6\xd1
+  wire regrt; //\xc4\xbf\xb5\xc4\xbc\xc4\xb4\xe6\xc6\xf7\xd1\xa1\xd4\xf1\xa3\xac\xce\xaa1\xca\xb1\xd1\xa1rt\xa3\xac\xce\xaa0\xca\xb1\xd1\xa1rd
+  wire m2reg; //\xb4\xe6\xb4\xa2\xca\xfd\xbe\xdd\xd0\xb4\xc8\xeb\xbc\xc4\xb4\xe6\xc6\xf7\xa3\xba\xce\xaa1\xca\xb1\xd1\xa1\xd4\xf1\xb4\xe6\xb4\xa2\xc6\xf7\xca\xfd\xbe\xdd\xa3\xac\xce\xaa0\xca\xb1\xd1\xa1\xd4\xf1ALU\xbd\xe1\xb9\xfb
+  wire shift; //ALU a\xca\xb9\xd3\xc3\xd2\xc6\xce\xbb\xce\xbb\xca\xfd\xa3\xba\xce\xaa1\xca\xb1\xca\xb9\xd3\xc3sa\xa3\xac\xb7\xf1\xd4\xf2\xca\xb9\xd3\xc3\xbc\xc4\xb4\xe6\xc6\xf7\xca\xfd\xbe\xdd
+  wire aluimm;  //ALU b\xd3\xc3\xc1\xa2\xbc\xb4\xca\xfd\xa3\xba\xce\xaa1\xca\xb1\xd3\xc3\xc1\xa2\xbc\xb4\xca\xfd\xa3\xac\xb7\xf1\xd4\xf2\xca\xb9\xd3\xc3\xbc\xc4\xb4\xe6\xc6\xf7\xca\xfd\xbe\xdd
+  wire jal;   //\xd7\xd3\xb3\xcc\xd0\xf2\xb5\xf7\xd3\xc3\xa3\xba\xce\xaa1\xca\xb1\xb1\xed\xca\xbe\xd6\xb8\xc1\xee\xca\xc7jal,\xb7\xf1\xd4\xf2\xb2\xbb\xca\xc7
+  wire sext;   //\xc1\xa2\xbc\xb4\xca\xfd\xb7\xfb\xba\xc5\xce\xbb\xc0\xa9\xd5\xb9\xa3\xba\xce\xaa1\xca\xb1\xb7\xfb\xba\xc5\xc0\xa9\xd5\xb9\xa3\xac\xb7\xf1\xd4\xf2\xc1\xe3\xc0\xa9\xd5\xb9
+  wire enable = 1;  //ip\xd0\xb4\xca\xb9\xc4\xdc
+  wire co, overflow, negative, carry;
+  wire [31:0] pcplus4out;
+  wire [31:0] pcplus8out;
+  wire [31:0] wpcout;
+  wire [31:0] alu1, alu2;
+  wire [31:0] rfouta;
+  wire [31:0] sa = {27\'b0, inst[10:6]};    //\xd2\xc6\xce\xbb\xd6\xb8\xc1\xee\xd6\xd0\xb5\xc4\xd2\xc6\xce\xbb\xce\xbb\xca\xfd   \xbd\xabrt\xd6\xb8\xb6\xa8\xbc\xc4\xb4\xe6\xc6\xf7\xd6\xd0\xb5\xc4\xc4\xda\xc8\xdd\xd2\xc6\xb6\xafsa\xce\xbb\xa3\xac\xd7\xa2\xd2\xe2\xa3\xbainst\xd6\xd0sa\xd6\xbb\xd3\xd05\xce\xbb\xa3\xac\xb4\xcb\xb4\xa6\xbd\xab\xcb\xfc\xc0\xa9\xd5\xb9\xce\xaa32\xce\xbb
+  wire e = sext & inst[15];  //\xc1\xa2\xbc\xb4\xca\xfd\xb7\xfb\xba\xc5\xce\xbb\xa3\xac\xc8\xf4sext\xce\xaa0\xd4\xf20\xc0\xa9\xd5\xb9
+  wire [15:0] imm = {16{e} };
+  wire [31:0] immediate = {imm, inst[15:0]}; //\xb7\xfb\xba\xc5\xce\xbb\xc0\xa9\xd5\xb9\xba\xf3\xb5\xc4\xc1\xa2\xbc\xb4\xca\xfd
+  wire [4:0] reg_dest;
+  wire [4:0] wn;
+  wire [31:0] offset = {imm[13:0], inst[15:0], 2\'b00};  //beq.bnq\xd6\xd0\xcf\xe0\xb6\xd4\xd7\xaa\xd2\xc6\xb5\xd8\xd6\xb7
+  wire [31:0] bpc;  //beq, bne\xd6\xd0\xb5\xc4\xd7\xaa\xd2\xc6\xb5\xd8\xd6\xb7
+  wire [31:0] jpc = {pcplus4out[31:28], inst[25:0], 2\'b00};  //j\xd6\xd0\xb5\xc4\xd7\xaa\xd2\xc6\xb5\xd8\xd6\xb7
+  wire [31:0] data;  //\xbc\xc4\xb4\xe6\xc6\xf7\xb6\xd1\xd6\xd0\xd2\xaa\xd0\xb4\xc8\xeb\xb5\xc4\xca\xfd\xbe\xdd
+  wire [31:0] nextpcout;
+  wire [31:0] resultout;
+
+  sccu_dataflow cpu_cu (inst[31:26], inst[5:0], zero, wmem, rmem, wreg, regrt, m2reg, aluc, shift, aluimm, pcsource, jal, sext, wpc);
+  
+  //ip\xa3\xac\xb4\xe6\xb7\xc5\xcf\xc2\xd2\xbb\xcc\xf5\xd6\xb8\xc1\xee\xb5\xd8\xd6\xb7
+  dffe32 ip(nextpcout, clock, resetn, enable, pc);
+  cla32 pcplus4(pc, 32\'h4, 1\'b0, pcplus4out, co); 
+  cla32 pcplus8(pc, 32\'h8, 1\'b0, pcplus8out, co);
+  mux2x5 reg_wn (inst[15:11], inst[20:16], regrt, reg_dest);
+  assign wn = reg_dest | {5{jal}};  //jal: r31 <-- pc+8, if jal == 1, wn = 31 else wn = reg_dest
+  mux2x32 pcorpc8(pc, pcplus8out, wpc, wpcout);  
+  mux2x32 result(aluout, memout, m2reg, resultout);
+  mux2x32 rf_add(resultout, pcplus8out, jal, data); 
+  regfile rf(inst[25:21], inst[20:16], data, wn, wreg, clock, resetn, rfouta, data2mem, reg_addr, reg_out );
+  mux2x32 alu_a(rfouta, sa, shift, alu1); 
+  mux2x32 alu_b(data2mem, immediate, aluimm, alu2);
+  alu aluunit(alu1, alu2, aluc, aluout, zero, negative, overflow, carry);
+  cla32 beqbnepc(pc, offset, 1\'b0, bpc, co);
+  mux4x32 nextpc(pcplus4out, bpc, rfouta , jpc, pcsource, nextpcout);
+endmodule"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2017/11/29 22:40:09
+// Design Name: 
+// Module Name: move
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module move(
+    input D,
+    input clk,
+    output [3:0] Q
+    );
+    
+    reg [3:0]Q;
+    
+    always@(posedge clk)
+    begin
+        Q[0]<=D;
+        Q[1]<=Q[0];
+        Q[2]<=Q[1];
+        Q[3]<=Q[2];
+    end
+    
+endmodule
+"
+"module counter(\r
+  input direction,\r
+  input clk,\r
+  output [1:0] select,\r
+  output [6:0] digital\r
+);\r
+reg [31:0] smalldiv;\r
+reg [31:0] bigdiv;\r
+reg [6:0] digital;\r
+reg [3:0] buffer;\r
+reg [1:0] select;\r
+reg [3:0] num [1:0];\r
+\r
+always@(posedge clk)\r
+begin\r
+  if(smalldiv >= 32'D49999)\r
+    begin\r
+    bigdiv <= bigdiv + 32'D1\r
+    smalldiv <= 32'D0\r
+    if(select == 2'B01)\r
+      select <= 2'B10\r
+    else\r
+      select <= 2'B01\r
+    end\r
+  else\r
+    smalldiv <= smalldiv + 32'D1\r
+\r
+  if(bigdiv >= 32'D200)\r
+    begin\r
+    bigdiv <= 32'D0\r
+    if(direction)\r
+      begin\r
+      if(num[0] < 4'D9 & num[0] >= 4'D0)\r
+        num[0] <= num[0] + 4'D1\r
+      else\r
+        begin\r
+        num[0] <= 4'D0\r
+        if(num[1] >= 4'D0 & num[1] < 4'D9)\r
+          num[1] <= num[1] + 4'D1\r
+        else\r
+          num[1] <= 4'D0\r
+        end\r
+      end\r
+      else\r
+      begin\r
+      if(num[0] <= 4'D9 & num[0] > 4'D0)\r
+        num[0] <= num[0] - 4'D1\r
+      else\r
+        begin\r
+        num[0] <= 4'D9\r
+        if(num[1] <= 4'D9 & num[1] > 4'D0)\r
+          num[1] <= num[1] - 4'D1\r
+        else\r
+          num[1] <= 4'D9\r
+      end\r
+    end\r
+\r
+    if(select == 2'B01)\r
+      buffer <= num[0]\r
+    else\r
+      buffer <= num[1]\r
+\r
+    case(buffer)\r
+    4'd0: digital <= 7'h3f;\t\t\t\t//\xe6\x98\xbe\xe7\xa4\xba0\r
+    4'd1: digital <= 7'h06;                //\xe6\x98\xbe\xe7\xa4\xba1\r
+    4'd2: digital <= 7'h5b;                //\xe6\x98\xbe\xe7\xa4\xba2\r
+    4'd3: digital <= 7'h4f;                //\xe6\x98\xbe\xe7\xa4\xba3\r
+    4'd4: digital <= 7'h66;                //\xe6\x98\xbe\xe7\xa4\xba4\r
+    4'd5: digital <= 7'h6d;                //\xe6\x98\xbe\xe7\xa4\xba5\r
+    4'd6: digital <= 7'h7d;                //\xe6\x98\xbe\xe7\xa4\xba6\r
+    4'd7: digital <= 7'h07;                //\xe6\x98\xbe\xe7\xa4\xba7\r
+    4'd8: digital <= 7'h7f;                //\xe6\x98\xbe\xe7\xa4\xba8\r
+    4'd9: digital <= 7'h67;                //\xe6\x98\xbe\xe7\xa4\xba9\r
+    endcase\r
+end\r
+endmodule\r
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 2017/11/29 22:40:09
+// Design Name:
+// Module Name: feedback
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module feedback(
+    input [3:0] Q,
+    input [1:0] C,
+    output D
+    );
+
+    wire [3:0]inD;
+
+    assign inD[0]=~(Q[0]|Q[1]|Q[2]);
+    assign inD[1]=~(Q[3])|(Q[3]&~Q[2]&~Q[1]&Q[0]);
+    assign inD[2]=~(Q[3])|(Q[3]&Q[2]&~Q[1]&~Q[0]);
+    assign inD[3]=(Q[0]^Q[3])|(~Q[0]&~Q[1]&~Q[2]&~Q[3])
+
+    assign D=(inD[0]&~C[0]&~C[1])|(inD[1]&C[0]&~C[1])|(inD[2]&~C[0]&C[1])|(inD[3]&C[0]&C[1]);
+
+endmodule
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 2017/11/29 22:40:09
+// Design Name:
+// Module Name: top
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module top_adder(
+    input clk,
+    input button,
+    output [1:0] C,
+    output [3:0] Q
+    );
+    reg [3:0]Q;
+    reg [1:0]C;
+    reg before;
+
+    wire D;
+    wire [3:0]inD;
+    wire [3:0]tempQ;
+    wire [1:0]tempC;
+
+    always@(posedge clk)
+    begin
+        if(~before&button)
+          C[1:0]<=tempC[1:0];
+        else
+          Q[3:0]<=tempQ[3:0];
+        before<=button;
+    end
+
+    assign inD[0]=~(Q[0]|Q[1]|Q[2]);
+    assign inD[1]=~(Q[3])|(Q[3]&~Q[2]&~Q[1]&Q[0]);
+    assign inD[2]=~(Q[3])|(Q[3]&Q[2]&~Q[1]&~Q[0]);
+    assign inD[3]=(Q[0]^Q[3])|(~Q[0]&~Q[1]&~Q[2]&~Q[3]);
+    assign D=(inD[0]&~C[0]&~C[1])|(inD[1]&C[0]&~C[1])|(inD[2]&~C[0]&C[1])|(inD[3]&C[0]&C[1]);
+
+    assign tempQ[0]=D;
+    assign tempQ[1]=Q[0];
+    assign tempQ[2]=Q[1];
+    assign tempQ[3]=Q[2];
+
+    assign tempC[0]=~C[0];
+    assign tempC[1]=C[0]^C[1];
+
+    endmodule
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2017/11/29 22:40:09
+// Design Name: 
+// Module Name: top
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+module top(
+    input button,
+    input clk,
+    output [1:0] C,
+    output [3:0] Q
+    );
+    reg [1:0]C;
+    reg [3:0]Q;
+    
+    wire D;
+    wire [1:0]tempC;
+    wire [3:0]tempQ;
+    adder(
+        .button(button),
+        .C(tempC[1:0])
+        );
+    feedback(
+            .Q(Q[3:0]),
+            .C(C[1:0]),
+            .D(D)
+            );
+     move(
+      .D(D),
+      .clk(clk),
+      .Q(tempQ[3:0])
+     );
+     
+   always@(*)
+      begin
+        C[1:0]<=tempC[1:0];
+        Q[3:0]<=tempQ[3:0];
+      end
+     
+    
+    
+endmodule
+"
+"`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2017/11/29 22:40:09
+// Design Name: 
+// Module Name: adder
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module adder(
+    input button,
+    output [1:0] C
+    );
+    
+    reg [1:0]C;
+    
+    always@(posedge button)
+    begin
+        C[0] <= ~C[0];
+        C[1] <= (~C[1]&C[0])|(~C[0]&C[1]);
+    end
+        
+endmodule
+"
+"module 0x28(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xC1(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x9B(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xAE(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x54(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x01(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x25(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x6C(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0xF9(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x20(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xEF(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xF4(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xEC(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x29(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x38(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module A(output out1,  input in1, in2);
+  always@(in1,in2)
+    begin
+      case({in1,in2})
+        2'b00: {out1} = 1'b0;
+        2'b01: {out1} = 1'b0;
+        2'b10: {out1} = 1'b0;
+        2'b11: {out1} = 1'b1;
+      endcase
+    end
+endmodule
+"
+"module 0xB9(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x79(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module multiplexer_alt(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x3F(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x38(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"\r
+\r
+module majority(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x47(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xAA(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x6B(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module C(output out, input IN1, IN2, IN3, IN4);
+
+   wire W1, W2, W3, W4, W5, W6, W7, W8;
+
+   nor (W1,IN2,IN4);
+   nor (W2,W1,IN1);
+   nor (W3,IN2,IN3);
+   or (out,W2,W3)
+   
+   
+endmodule
+"
+"module 0x14(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x95(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xDC(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x84(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x74(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xEE(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module majority_alt(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x11(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xA6(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xFA(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x4C(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xC8(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x23(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xB2(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xC0(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x81(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x56(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x91(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x70(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x5F(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x68(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module majority(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module F(output out, input IN1, IN2, IN3, IN4);
+
+   wire W1, W2, W3, W4, W5, W6, W7, W8;
+
+   not (W1,IN3);
+   nor (W2,W1,IN2);
+   nor (W3,W2,IN4);
+   nor (W4,IN1,IN2);
+   nor (W5,W4,IN3);
+   or (out,W3,W5);
+   
+   
+   
+endmodule
+"
+"module 0x47(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0xC9(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x62(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x37(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xFE(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xA6(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module consensus(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0xBC(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xE5(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x24(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xFC(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module structuralXOR(output out, input A, B, C, D);
+
+wire w1,w2,w3,w4,w5,w6,w7,w8,w9;
+
+   not (w9, D);
+   nor (w8, C, A);
+   not (w7, B);
+   nor (w6, w9, w7);
+   nor (w5, D, B);
+   nor (w4, w5, w6);
+   not (w3, w8);
+   not (w2, w4);
+   nor (w1, w2, w3);
+   not (out, w1);
+   
+endmodule
+
+"
+"\r
+\r
+module 0x37(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"\r
+\r
+module 0xF6(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x7D(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module demultiplexer(output out,input A,B);\r
+always@(B,A)\r
+ begin\r
+  case({B,A})\r
+   2'b00: {outZ,outY,outX,outW} = 4'b0010;\r
+   2'b01: {outZ,outY,outX,outW} = 4'b1000;\r
+   2'b10: {outZ,outY,outX,outW} = 4'b0100;\r
+   2'b11: {outZ,outY,outX,outW} = 4'b0001;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0xCA(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0xC7(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module AND(output out, input in1, in2);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2)
+    begin
+      case({in1,in2})
+        2'b00: out = 1'b0;
+        2'b01: out = 1'b0;
+        2'b10: out = 1'b0;
+        2'b11: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xB4(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xC4(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x1F(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xD5(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xC0(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x9F(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x64(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x18(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module structuralXOR(output out, input inA, inB, inC);
+
+wire w2,w3,w4,w6,w7,w8,w9;
+
+nor (w9, inB, inC);
+nor (w8, w9, inC);
+nor (w7, w9, inB);
+nor (w6, w7, w8);
+nor (w4, inA, w6);
+nor (w3, w4, w6);
+nor (w2, w4, inA);
+nor (out, w2, w3);
+   
+endmodule
+
+"
+"module 0xC5(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x00(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xF0(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x1B(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x8B(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x97(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x49(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x4F(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x37(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x40(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0xF9(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x88(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x0F(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x2E(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x82(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b2;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0xE3(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xE1(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x10(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xB2(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x7D(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xD1(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x50(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module NAND(output out,input A,B);\r
+always@(B,A)\r
+ begin\r
+  case({B,A})\r
+   2'b00: {out} = 1'b1;\r
+   2'b01: {out} = 1'b1;\r
+   2'b10: {out} = 1'b1;\r
+   2'b11: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x8D(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module structuralAND(output out, input inA, inB);
+
+wire w2,w3;
+
+   not (w3, inB);
+   not (w2, inA);
+   nor (out, w2, w3);
+   
+endmodule
+
+"
+"module 0x71(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x61(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x78(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0xC4(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0xC8(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x3D(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x32(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xC2(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xBA(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x82(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x8E(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0xE1(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xB1(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x3D(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x4E(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x28(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module A(output Qa, Qb, input in1, in2, C);
+
+   wire w1, w2, w3, w4, w5, D;
+
+
+   not (w4, in1);
+   not (w5, in2);
+   nor (D, w4, w5);
+   not (w1, D);
+   nor (w2, D, C);
+   nor (w3, w1, C);
+   nor (Qa, w2, Qb);
+   nor (Qb, w3, Qa);
+
+endmodule // A
+"
+"module 0xDD(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x68(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xD9(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xC7(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x3B(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xF9(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0xF7(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0xC1(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x31(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x0B(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x9B(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module structuralAND(output out, input inA, inB);
+
+   and (out, inA, inB);
+   
+endmodule
+
+"
+"module 0xEB(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x43(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x44(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x41(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0xEF(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xF8(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x0E(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0xAB(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module F7dec(output out, input in1, in2, in3, in4);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3, in4)
+    begin
+      case({in1, in2, in3, in4})
+        4'b0000: out = 1'b1;
+        4'b0001: out = 1'b0;
+        4'b0010: out = 1'b0;
+        4'b0011: out = 1'b0;
+        4'b0100: out = 1'b1;
+        4'b0101: out = 1'b1;
+        4'b0110: out = 1'b1;
+        4'b0111: out = 1'b0;
+\t4'b1000: out = 1'b1;
+        4'b1001: out = 1'b1;
+        4'b1010: out = 1'bx;
+        4'b1011: out = 1'bx;
+        4'b1100: out = 1'bx;
+        4'b1101: out = 1'bx;
+        4'b1110: out = 1'bx;
+        4'b1111: out = 1'bx;
+\t
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xA4(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x46(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x59(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x36(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x86(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x04(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xBA(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x78(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0xFC(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xC5(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x88(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xFD(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x04(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"\r
+\r
+module consensus_alt(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0xE5(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xB0(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x6C(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0xBD(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x45(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x5D(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x1D(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x8E(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xBE(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x12(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x86(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x31(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module A(output Qa, Qb, input D, C);
+
+   wire w1, w2, w3;
+
+   not (w1, D);
+   nor (w2, D, C);
+   nor (w3, w1, C);
+   nor (Qa, w2, Qb);
+   nor (Qb, w3, Qa);
+
+endmodule // A
+"
+"module 0x6D(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xE6(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module F7hex(output out, input in1, in2, in3, in4);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3, in4)
+    begin
+      case({in1, in2, in3, in4})
+        4'b0000: out = 1'b1;
+        4'b0001: out = 1'b0;
+        4'b0010: out = 1'b0;
+        4'b0011: out = 1'b0;
+        4'b0100: out = 1'b1;
+        4'b0101: out = 1'b1;
+        4'b0110: out = 1'b1;
+        4'b0111: out = 1'b0;
+\t4'b1000: out = 1'b1;
+        4'b1001: out = 1'b1;
+        4'b1010: out = 1'b1;
+        4'b1011: out = 1'b1;
+        4'b1100: out = 1'b1;
+        4'b1101: out = 1'b0;
+        4'b1110: out = 1'b1;
+        4'b1111: out = 1'b1;
+\t
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xE6(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module structuralAND(output out, input inA, inB, inC);
+
+   wire w1, w2;
+   
+   and (w1, inA, inB);
+   and (w2, w1, inC);
+   not (out, w2);
+   
+   
+endmodule
+
+"
+"\r
+\r
+module ANIMPLYB(output out,input A,B);\r
+always@(B,A)\r
+ begin\r
+  case({B,A})\r
+   2'b00: {out} = 1'b0;\r
+   2'b01: {out} = 1'b1;\r
+   2'b10: {out} = 1'b0;\r
+   2'b11: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0xD7(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x5B(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x65(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x19(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module AimplyB(output out, input in1, in2);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2)
+    begin
+      case({in1,in2})
+        2'b00: out = 1'b1;
+        2'b01: out = 1'b0;
+        2'b10: out = 1'b1;
+        2'b11: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x4D(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x51(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x9F(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0xA2(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x3B(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x63(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x98(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x8C(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x0F(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x63(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x01(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xF2(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x70(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x64(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xFE(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module NAND(output out, input in1, in2);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2)
+    begin
+      case({in1,in2})
+        2'b00: out = 1'b1;
+        2'b01: out = 1'b1;
+        2'b10: out = 1'b1;
+        2'b11: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x75(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x4D(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x85(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x8C(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x87(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x55(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xB8(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x5F(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xE4(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module B7dec(output out, input in1, in2, in3, in4);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3, in4)
+    begin
+      case({in1, in2, in3, in4})
+        4'b0000: out = 1'b1;
+        4'b0001: out = 1'b1;
+        4'b0010: out = 1'b1;
+        4'b0011: out = 1'b1;
+        4'b0100: out = 1'b1;
+        4'b0101: out = 1'b0;
+        4'b0110: out = 1'b0;
+        4'b0111: out = 1'b1;
+\t4'b1000: out = 1'b1;
+        4'b1001: out = 1'b1;
+        4'b1010: out = 1'bx;
+        4'b1011: out = 1'bx;
+        4'b1100: out = 1'bx;
+        4'b1101: out = 1'bx;
+        4'b1110: out = 1'bx;
+        4'b1111: out = 1'bx;
+\t
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x90(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x7F(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0xCD(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x7C(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x61(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x83(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x87(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0xB9(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module consensus_alt(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module E7hex(output out, input in1, in2, in3, in4);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3, in4)
+    begin
+      case({in1, in2, in3, in4})
+        4'b0000: out = 1'b1;
+        4'b0001: out = 1'b0;
+        4'b0010: out = 1'b1;
+        4'b0011: out = 1'b0;
+        4'b0100: out = 1'b0;
+        4'b0101: out = 1'b0;
+        4'b0110: out = 1'b1;
+        4'b0111: out = 1'b0;
+\t4'b1000: out = 1'b1;
+        4'b1001: out = 1'b0;
+        4'b1010: out = 1'b1;
+        4'b1011: out = 1'b1;
+        4'b1100: out = 1'b1;
+        4'b1101: out = 1'b1;
+        4'b1110: out = 1'b1;
+        4'b1111: out = 1'b1;
+\t
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x0D(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module A(output out1, out2,  input in1, in2);
+  reg r_out;
+  assign out = r_out;
+  always@(in1,in2)
+    begin
+      case({in1,in2})
+        2'b00: {out2,out1} = 2'b00;
+        2'b01: {out2,out1} = 2'b01;
+        2'b10: {out2,out1} = 2'b11;
+        2'b11: {out2,out1} = 2'b10;
+      endcase
+    end
+endmodule
+"
+"module 0xA0(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x54(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xF2(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0xAE(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x41(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x5A(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xDE(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xB6(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x91(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x99(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x0D(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x3F(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xD8(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module D7dec(output out, input in1, in2, in3, in4);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3, in4)
+    begin
+      case({in1, in2, in3, in4})
+        4'b0000: out = 1'b1;
+        4'b0001: out = 1'b0;
+        4'b0010: out = 1'b1;
+        4'b0011: out = 1'b1;
+        4'b0100: out = 1'b0;
+        4'b0101: out = 1'b1;
+        4'b0110: out = 1'b1;
+        4'b0111: out = 1'b0;
+\t4'b1000: out = 1'b1;
+        4'b1001: out = 1'b0;
+        4'b1010: out = 1'bx;
+        4'b1011: out = 1'bx;
+        4'b1100: out = 1'bx;
+        4'b1101: out = 1'bx;
+        4'b1110: out = 1'bx;
+        4'b1111: out = 1'bx;
+\t
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x7F(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xC9(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xE9(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x4A(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x6F(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x55(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x9E(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module XOR(output out,input A,B);\r
+always@(B,A)\r
+ begin\r
+  case({B,A})\r
+   2'b00: {out} = 1'b0;\r
+   2'b01: {out} = 1'b1;\r
+   2'b10: {out} = 1'b1;\r
+   2'b11: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"\r
+\r
+module 0xF6(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x38(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x46(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x15(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xFB(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x27(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x07(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0xDA(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xF0(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x07(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xB3(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x02(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x69(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x2D(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module A7hex(output out, input in1, in2, in3, in4);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3, in4)
+    begin
+      case({in1, in2, in3, in4})
+        4'b0000: out = 1'b1;
+        4'b0001: out = 1'b0;
+        4'b0010: out = 1'b1;
+        4'b0011: out = 1'b1;
+        4'b0100: out = 1'b0;
+        4'b0101: out = 1'b1;
+        4'b0110: out = 1'b1;
+        4'b0111: out = 1'b1;
+\t4'b1000: out = 1'b1;
+        4'b1001: out = 1'b1;
+        4'b1010: out = 1'b1;
+        4'b1011: out = 1'b0;
+        4'b1100: out = 1'b1;
+        4'b1101: out = 1'b0;
+        4'b1110: out = 1'b1;
+        4'b1111: out = 1'b1;
+\t
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x78(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module NOR(output out, input in1, in2);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2)
+    begin
+      case({in1,in2})
+        2'b00: out = 1'b1;
+        2'b01: out = 1'b0;
+        2'b10: out = 1'b0;
+        2'b11: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module structuralNOT(output out, input inA);
+
+   not (out, inA);
+   
+endmodule
+
+"
+"module 0x52(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x3D(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x92(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module XNOR(output out,input A,B);\r
+always@(B,A)\r
+ begin\r
+  case({B,A})\r
+   2'b00: {out} = 1'b1;\r
+   2'b01: {out} = 1'b0;\r
+   2'b10: {out} = 1'b0;\r
+   2'b11: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x24(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xB4(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x19(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x95(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x73(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0xC6(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0xCB(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x78(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x15(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module AND(output out,input A,B);\r
+always@(B,A)\r
+ begin\r
+  case({B,A})\r
+   2'b00: {out} = 1'b0;\r
+   2'b01: {out} = 1'b0;\r
+   2'b10: {out} = 1'b0;\r
+   2'b11: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x62(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x7C(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x2C(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x03(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x57(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x72(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module structuralXOR(output out, input A, B, C, D);
+
+wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11;
+
+   not (w9, D);
+   not (w7, C);
+   not (w6, B);
+   nor (w4, w6, C);
+   nor (w8, w9, w6);
+   nor (w5, w7, w8);
+   nor (w3, w4, w5);
+   not (w2, w3);
+   nor (w1, w2, A);
+   not (out, w1);
+
+endmodule
+
+"
+"module 0x2C(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x65(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x67(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x9E(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x26(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x60(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module demultiplexer(output out,input A,B);\r
+always@(B,A)\r
+ begin\r
+  case({B,A})\r
+   2'b00: {outZ,outY,outX,outW} = 4'b0010;\r
+   2'b01: {outZ,outY,outX,outW} = 4'b1000;\r
+   2'b10: {outZ,outY,outX,outW} = 4'b0100;\r
+   2'b11: {outZ,outY,outX,outW} = 4'b0001;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x84(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x0C(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module XOR(output out, input in1, in2);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2)
+    begin
+      case({in1,in2})
+        2'b00: out = 1'b0;
+        2'b01: out = 1'b1;
+        2'b10: out = 1'b1;
+        2'b11: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x82(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x7E(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module AIMPLYB(output out,input A,B);\r
+always@(B,A)\r
+ begin\r
+  case({B,A})\r
+   2'b00: {out} = 1'b1;\r
+   2'b01: {out} = 1'b0;\r
+   2'b10: {out} = 1'b1;\r
+   2'b11: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0xFA(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x2A(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x1E(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x58(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x14(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module G(output out, input IN1, IN2, IN3, IN4);
+
+   wire W1, W2, W3, W4, W5, W6, W7, W8;
+
+   not (W1,IN3);
+   nor (W2,IN1,IN4);
+   nor (W3,W1,W2);
+   nor (W4,IN1,IN2);
+   nor (W5,W3,W4);
+   nor (W6,W1,IN2);
+   or (out,W5,W6);
+   
+endmodule
+"
+"module C7dec(output out, input in1, in2, in3, in4);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3, in4)
+    begin
+      case({in1, in2, in3, in4})
+        4'b0000: out = 1'b1;
+        4'b0001: out = 1'b1;
+        4'b0010: out = 1'b0;
+        4'b0011: out = 1'b1;
+        4'b0100: out = 1'b1;
+        4'b0101: out = 1'b1;
+        4'b0110: out = 1'b1;
+        4'b0111: out = 1'b1;
+\t4'b1000: out = 1'b1;
+        4'b1001: out = 1'b1;
+        4'b1010: out = 1'bx;
+        4'b1011: out = 1'bx;
+        4'b1100: out = 1'bx;
+        4'b1101: out = 1'bx;
+        4'b1110: out = 1'bx;
+        4'b1111: out = 1'bx;
+\t
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x89(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module GrayCode(output out1, out2, out3, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in3,in2,in1})
+        3'b000: {out3,out2,out1} = 3'b000;
+\t3'b001: {out3,out2,out1} = 3'b001;
+\t3'b010: {out3,out2,out1} = 3'b011;
+\t3'b011: {out3,out2,out1} = 3'b010;
+\t3'b100: {out3,out2,out1} = 3'b110;
+\t3'b101: {out3,out2,out1} = 3'b111;
+\t3'b110: {out3,out2,out1} = 3'b101;
+\t3'b111: {out3,out2,out1} = 3'b100;
+
+\tdefault: {out1,out2,out3} = 3'b000;
+      endcase
+    end
+endmodule
+"
+"module 0x8F(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module XOR(output out,input A,B);\r
+always@(B,A)\r
+ begin\r
+  case({B,A})\r
+   2'b00: {out} = 1'b0;\r
+   2'b01: {out} = 1'b1;\r
+   2'b10: {out} = 1'b1;\r
+   2'b11: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"\r
+\r
+module 0xB9(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"\r
+\r
+module 0x70(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"\r
+\r
+module 0xC1(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module A(output out1,  input in1, in2, in3);
+  always@(in1,in2)
+    begin
+      case({in1,in2,in3})
+        3'b000: {out1} = 1'b1;
+        3'b001: {out1} = 1'b1;
+        3'b010: {out1} = 1'b1;
+        3'b011: {out1} = 1'b1;
+        3'b100: {out1} = 1'b1;
+        3'b101: {out1} = 1'b1;
+        3'b110: {out1} = 1'b1;
+        3'b111: {out1} = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x99(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xFF(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xBB(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xEA(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xC3(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xBC(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x36(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xBB(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0xF7(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"\r
+\r
+module NAND(output out,input A,B);\r
+always@(B,A)\r
+ begin\r
+  case({B,A})\r
+   2'b00: {out} = 1'b1;\r
+   2'b01: {out} = 1'b1;\r
+   2'b10: {out} = 1'b1;\r
+   2'b11: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"\r
+\r
+module 0x7F(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0xDB(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x2A(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xA8(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x1C(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x3B(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module A(output out1,  input in1, in2);
+  always@(in1,in2)
+    begin
+      case({in1,in2})
+        2'b00: {out1} = 1'b0;
+        2'b01: {out1} = 1'b0;
+        2'b10: {out1} = 1'b0;
+        2'b11: {out1} = 1'b1;
+      endcase
+    end
+endmodule
+"
+"module 0xE3(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x41(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x36(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"\r
+\r
+module 0xBD(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x77(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x73(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xD4(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x42(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module structural(output out1, out2, out3, out4, input inA, inB);
+
+   wire w1, w2;
+   
+   not (w1, inA);
+   nor (out4, inA, inB);
+   not (w2, inB);
+   nor (out3, inA, w2); 
+   nor (out2, inB, w1);
+   nor (out1, w1, w2); 
+   
+endmodule
+
+"
+"module 0xE4(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xF5(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x10(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module structuralAND(output out, input inA, inB);
+
+   wire w1;
+   
+   and (w1, inA, inB);
+   not (out, w1);
+   
+   
+endmodule
+
+"
+"module 0x40(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x1E(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xB5(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x3C(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x0E(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x0A(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xC2(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x79(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x43(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module D(output out, input IN1, IN2, IN3, IN4);
+
+   wire W1, W2, W3, W4, W5, W6, W7, W8;
+
+   
+   nor (W1,IN3,IN4);
+   nor (W2,W1,IN3);
+   nor (W3,W1,IN4);
+   nor (W4,W2,W3);
+   not (W5,IN2);
+   nor (W6,W4,W5);
+   nor (W7,W2,IN2);
+   or (out,W6,W7);
+   
+   
+endmodule
+"
+"module 0xF1(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xAD(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module consensus(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x48(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x17(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x38(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"\r
+\r
+module 0x60(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module A(output Qa, Qb, input C, D);
+
+   wire w1, w2, w3, w4, w5;
+   
+   nor (w1,w4,w2);
+   nor (w2,C,w1);
+   nor (w3,w4,C,w2);
+   nor (w4,w3,D);
+   nor (Qa,w2,Qb);
+   nor (Qb,w3,Qa);
+
+
+   
+endmodule
+"
+"module 0x3C(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x05(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x6E(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0xAA(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xD9(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0xC1(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module AND_NAND(output out1, out2, input in1, in2);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2)
+    begin
+      case({in1,in2})
+        2'b00: {out1,out2} = 2'b00;
+\t2'b01: {out1,out2} = 2'b00;
+\t2'b10: {out1,out2} = 2'b01;
+\t2'b11: {out1,out2} = 2'b11;
+
+\tdefault: {out1,out2} = 2'b00;
+      endcase
+    end
+endmodule
+"
+"module 0xD5(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module structuralXOR(output out, input A, B, C, D);
+
+wire w1,w2,w3,w4,w5,w6,w7,w8,w9;
+
+   not (w8, D);
+   not (w7, C);
+   not (w2, B);
+   nor (w5, D, C);
+   nor (w6, w7, w8);
+   nor (w4, w5, w6);
+   not (w3, w4);
+   nor (w1, w2, w3);
+   not (out, w1);
+   
+   
+endmodule
+
+"
+"module 0xAC(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xDC(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x22(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module BNIMPLYA(output out,input A,B);\r
+always@(B,A)\r
+ begin\r
+  case({B,A})\r
+   2'b00: {out} = 1'b0;\r
+   2'b01: {out} = 1'b0;\r
+   2'b10: {out} = 1'b1;\r
+   2'b11: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"\r
+\r
+module 0x98(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"\r
+\r
+module 0x04(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x01(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x04(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module D7hex(output out, input in1, in2, in3, in4);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3, in4)
+    begin
+      case({in1, in2, in3, in4})
+        4'b0000: out = 1'b1;
+        4'b0001: out = 1'b0;
+        4'b0010: out = 1'b1;
+        4'b0011: out = 1'b1;
+        4'b0100: out = 1'b0;
+        4'b0101: out = 1'b1;
+        4'b0110: out = 1'b1;
+        4'b0111: out = 1'b0;
+\t4'b1000: out = 1'b1;
+        4'b1001: out = 1'b0;
+        4'b1010: out = 1'b0;
+        4'b1011: out = 1'b1;
+        4'b1100: out = 1'b1;
+        4'b1101: out = 1'b1;
+        4'b1110: out = 1'b1;
+        4'b1111: out = 1'b0;
+\t
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xE7(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xBD(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xE7(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x3A(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xBE(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x93(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xAB(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module structuralXNOR(output out, input inA, inB, inC);
+
+wire w2,w3,w4,w6,w7,w8,w9;
+
+nor (w9, inB, inC);
+nor (w8, w9, inC);
+nor (w7, w9, inB);
+nor (w6, w7, w8);
+nor (w4, inA, w6);
+nor (w3, w4, w6);
+nor (w2, w4, inA);
+or (out, w2, w3);
+   
+endmodule
+"
+"module AND_NAND(output out1, out2, input in1, in2);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2)
+    begin
+      case({in1,in2})
+        2'b00: {out1,out2} = 2'b01;
+\t2'b01: {out1,out2} = 2'b01;
+\t2'b10: {out1,out2} = 2'b01;
+\t2'b11: {out1,out2} = 2'b10;
+
+\tdefault: {out1,out2} = 2'b00;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module priority_detector(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {outZ,outY,outX} = 3'b000;\r
+   3'b001: {outZ,outY,outX} = 3'b001;\r
+   3'b010: {outZ,outY,outX} = 3'b100;\r
+   3'b011: {outZ,outY,outX} = 3'b100;\r
+   3'b100: {outZ,outY,outX} = 3'b010;\r
+   3'b101: {outZ,outY,outX} = 3'b001;\r
+   3'b110: {outZ,outY,outX} = 3'b100;\r
+   3'b111: {outZ,outY,outX} = 3'b100;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x21(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x92(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x5E(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x19(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x80(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0xEA(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x85(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module multiplexer(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x2F(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x59(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module OR(output out, input in1, in2);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2)
+    begin
+      case({in1,in2})
+        2'b00: out = 1'b0;
+        2'b01: out = 1'b1;
+        2'b10: out = 1'b1;
+        2'b11: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x6A(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0xC9(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x89(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x4B(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x81(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x21(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x33(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module AND(output out,input A,B);\r
+always@(B,A)\r
+ begin\r
+  case({B,A})\r
+   2'b00: {out} = 1'b0;\r
+   2'b01: {out} = 1'b0;\r
+   2'b10: {out} = 1'b0;\r
+   2'b11: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0xCE(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x87(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module G7hex(output out, input in1, in2, in3, in4);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3, in4)
+    begin
+      case({in1, in2, in3, in4})
+        4'b0000: out = 1'b0;
+        4'b0001: out = 1'b0;
+        4'b0010: out = 1'b1;
+        4'b0011: out = 1'b1;
+        4'b0100: out = 1'b1;
+        4'b0101: out = 1'b1;
+        4'b0110: out = 1'b1;
+        4'b0111: out = 1'b0;
+\t4'b1000: out = 1'b1;
+        4'b1001: out = 1'b1;
+        4'b1010: out = 1'b1;
+        4'b1011: out = 1'b1;
+        4'b1100: out = 1'b0;
+        4'b1101: out = 1'b1;
+        4'b1110: out = 1'b1;
+        4'b1111: out = 1'b1;
+\t
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module A(output out, input IN1, IN2, IN3, IN4);
+
+   wire W1, W2, W3, W4, W5, W6, W7, W8;
+
+   nor (W1,IN2,IN3);
+   nor (W2,IN3,IN4);
+   nor (W3,W1,W2);
+   nor (W4,W2,IN1);
+   nor (W5,W4,IN2);
+   or (out,W3,W5);
+   
+
+endmodule
+"
+"module XNOR(output out, input in1, in2);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2)
+    begin
+      case({in1,in2})
+        2'b00: out = 1'b1;
+        2'b01: out = 1'b0;
+        2'b10: out = 1'b0;
+        2'b11: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xF3(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xBD(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xB5(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x16(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module A(output Qa, Qb, input R, S);
+
+   wire w1, w2;
+
+   nor (Qa, R, Qb);
+   nor (Qb, S, Qa);
+
+
+endmodule
+"
+"module 0x09(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xE2(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x5E(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x01(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0xB0(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xE9(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x3E(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xD2(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xED(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xCC(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0xFB(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module structuralXOR(output out, input A, B, C, D);
+
+wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11;
+
+   not (w8, C);
+   not (w7, B);
+   nor (w6, w8, B);
+   nor (w5, w7, C);
+   nor (w4, w6, D);
+   nor (w3, w4, w5);
+   not (w2, w3);
+   nor (w1, w2, A);
+   not (out, w1);
+   
+
+endmodule
+
+"
+"\r
+\r
+module 0x06(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x18(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x44(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x1F(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x36(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x07(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0xC7(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x02(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x53(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xC7(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x41(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x1A(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xD0(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x57(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xB1(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xE0(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xAE(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module AIMPLYB(output out,input A,B);\r
+always@(B,A)\r
+ begin\r
+  case({B,A})\r
+   2'b00: {out} = 1'b1;\r
+   2'b01: {out} = 1'b0;\r
+   2'b10: {out} = 1'b1;\r
+   2'b11: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x19(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x6F(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0xEA(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0xD4(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xE8(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x4A(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module AND_NAND(output out1, out2, input in1, in2);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2)
+    begin
+      case({in1,in2})
+        2'b00: {out1,out2} = 2'b00;
+\t2'b01: {out1,out2} = 2'b01;
+\t2'b10: {out1,out2} = 2'b11;
+\t2'b11: {out1,out2} = 2'b10;
+
+\tdefault: {out1,out2} = 2'b00;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0xCD(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module B(output out, input IN1, IN2, IN3, IN4);
+
+   wire W1, W2, W3, W4, W5, W6, W7, W8;
+
+   
+   not (W1,IN2);
+   nor (W2,W1,IN3);
+   nor (W3,W1,IN4);
+   nor (W4,W2,W3);
+   nor (W5,IN3,IN4);
+   or (out,W4,W5);
+   
+   
+endmodule
+"
+"module 0x1C(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xCF(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xAF(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x08(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x05(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xDB(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module TRUE(output out, input in1, in2);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2)
+    begin
+      case({in1,in2})
+        2'b00: out = 1'b1;
+        2'b01: out = 1'b1;
+        2'b10: out = 1'b1;
+        2'b11: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x35(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x7E(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x4E(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x5C(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x34(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x00(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module FALSE(output out, input in1, in2);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2)
+    begin
+      case({in1,in2})
+        2'b00: out = 1'b0;
+        2'b01: out = 1'b0;
+        2'b10: out = 1'b0;
+        2'b11: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x03(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xFB(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xED(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x52(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xC6(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x93(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xD3(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xF6(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module BNimplyA(output out, input in1, in2);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2)
+    begin
+      case({in1,in2})
+        2'b00: out = 1'b0;
+        2'b01: out = 1'b0;
+        2'b10: out = 1'b1;
+        2'b11: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0xAE(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0xA3(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x98(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"\r
+\r
+module multiplexer(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x3D(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module A(output out, input in1, in2);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2)
+    begin
+      case({in1,in2})
+        2'b00: out = 1'b0;
+        2'b01: out = 1'b1;
+        2'b10: out = 1'b0;
+        2'b11: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x56(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module E(output out, input IN1, IN2, IN3, IN4);
+
+   wire W1, W2, W3, W4, W5, W6, W7, W8;
+
+   not (W1,IN2);
+   nor (W2,W1,IN3);
+   nor (out,W2,IN4)
+   
+   
+endmodule
+"
+"module 0x34(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x30(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x12(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xEC(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x6E(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x6E(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x4D(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0xC6(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x7A(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x4B(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module structuralXOR(output out, input A, B, C, D);
+
+wire w1,w2,w3,w4,w5,w6,w7,w8,w9;
+
+   not (w4, C);
+   nor (w3, w4, B);
+   not (w2, w3);
+   nor (w1, w2, D);
+   not (out, w1);
+   
+   
+endmodule
+
+"
+"module 0xA3(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x48(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x7A(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xC3(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x22(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x8F(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xCB(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xFE(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x67(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xD7(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x0A(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x0B(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x0C(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x7B(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x75(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xCD(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x45(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xB7(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x6B(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x4C(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x87(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xD8(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x33(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0xC6(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"\r
+\r
+module 0xFB(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0xF3(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xD6(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module BNIMPLYA(output out,input A,B);\r
+always@(B,A)\r
+ begin\r
+  case({B,A})\r
+   2'b00: {out} = 1'b0;\r
+   2'b01: {out} = 1'b0;\r
+   2'b10: {out} = 1'b1;\r
+   2'b11: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x76(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x9A(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x8D(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xA1(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x80(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x8B(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x3A(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x17(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0xC4(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x13(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x49(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x39(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xAD(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xA9(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module structuralXOR(output out, input A, B, C, D);
+
+wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11;
+
+   not (w2, B);
+   nor (w1, w2, C);
+   nor (out, w1, D);
+
+endmodule
+
+"
+"module 0xD6(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x8A(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x97(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xF9(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xE0(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xD3(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module ANimplyB(output out, input in1, in2);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2)
+    begin
+      case({in1,in2})
+        2'b00: out = 1'b0;
+        2'b01: out = 1'b1;
+        2'b10: out = 1'b0;
+        2'b11: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x8E(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x6A(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module structuralAND(output out, input inA, inB);
+
+   wire w1, w2, w3, w4, w5;
+   
+   nor (w2, inA, inB);
+   not (w4, inB);
+   not (w5, inA);
+   nor (w3, w4, w5);
+   nor (w1, w2, w3);
+   not (out, w1);
+   
+endmodule
+
+"
+"module 0x81(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x29(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xB7(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x23(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module structuralXNOR(output out, input inA, inB, inC);
+
+wire w2,w3,w4,w6,w7,w8,w9;
+
+nor (w9, inB, inC);
+nor (w8, w9, inC);
+nor (w7, w9, inB);
+nor (w6, w7, w8);
+nor (w4, inA, w6);
+nor (w3, w4, w6);
+nor (w2, w4, inA);
+or (out, w2, w3);
+   
+endmodule
+"
+"\r
+\r
+module 0x6E(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module structuralXOR(output out, input A, B, C, D);
+
+wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11;
+
+
+   not (w11, C);
+   not (w10, D);
+   nor (w7, w10, C);
+   not (w9, w7);
+   not (w8, B);
+   nor (w6, w8, w9);
+   nor (w5, w7, B);
+   nor (w4, w5, w6);
+   not (w3, w4);
+   nor (w2, w11, D);   
+   nor (w1, w2, w3);
+   not (out, w1);
+   
+   
+   
+endmodule
+"
+"module 0x98(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xF1(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x5A(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x20(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module A7dec(output out, input in1, in2, in3, in4);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3, in4)
+    begin
+      case({in1, in2, in3, in4})
+        4'b0000: out = 1'b1;
+        4'b0001: out = 1'b0;
+        4'b0010: out = 1'b1;
+        4'b0011: out = 1'b1;
+        4'b0100: out = 1'b0;
+        4'b0101: out = 1'b1;
+        4'b0110: out = 1'b1;
+        4'b0111: out = 1'b1;
+\t4'b1000: out = 1'b1;
+        4'b1001: out = 1'b1;
+        4'b1010: out = 1'bx;
+        4'b1011: out = 1'bx;
+        4'b1100: out = 1'bx;
+        4'b1101: out = 1'bx;
+        4'b1110: out = 1'bx;
+        4'b1111: out = 1'bx;
+\t
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x08(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xF8(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xDF(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x6F(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x9C(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x71(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x2F(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x74(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x1C(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"\r
+\r
+module BIMPLYA(output out,input A,B);\r
+always@(B,A)\r
+ begin\r
+  case({B,A})\r
+   2'b00: {out} = 1'b1;\r
+   2'b01: {out} = 1'b1;\r
+   2'b10: {out} = 1'b0;\r
+   2'b11: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module BimplyA(output out, input in1, in2);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2)
+    begin
+      case({in1,in2})
+        2'b00: out = 1'b1;
+        2'b01: out = 1'b1;
+        2'b10: out = 1'b0;
+        2'b11: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xAC(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x08(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"\r
+\r
+module 0xB9(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0xA1(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x58(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x32(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xEA(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x4F(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0xC8(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0xF6(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x0B(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x80(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x90(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x37(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0xC9(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x6F(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x83(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xBF(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x2E(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x76(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xA5(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xB8(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module B(output out, input in1, in2);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2)
+    begin
+      case({in1,in2})
+        2'b00: out = 1'b0;
+        2'b01: out = 1'b0;
+        2'b10: out = 1'b1;
+        2'b11: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xF5(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x66(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x11(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module NOTB(output out, input in1, in2);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2)
+    begin
+      case({in1,in2})
+        2'b00: out = 1'b1;
+        2'b01: out = 1'b1;
+        2'b10: out = 1'b0;
+        2'b11: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x13(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module multiplexer_alt(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0xDE(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x9D(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x50(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xA7(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x60(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x16(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module priority_detector(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {outZ,outY,outX} = 3'b000;\r
+   3'b001: {outZ,outY,outX} = 3'b001;\r
+   3'b010: {outZ,outY,outX} = 3'b100;\r
+   3'b011: {outZ,outY,outX} = 3'b100;\r
+   3'b100: {outZ,outY,outX} = 3'b010;\r
+   3'b101: {outZ,outY,outX} = 3'b001;\r
+   3'b110: {outZ,outY,outX} = 3'b100;\r
+   3'b111: {outZ,outY,outX} = 3'b100;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0xA4(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x08(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xD1(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module E7dec(output out, input in1, in2, in3, in4);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3, in4)
+    begin
+      case({in1, in2, in3, in4})
+        4'b0000: out = 1'b1;
+        4'b0001: out = 1'b0;
+        4'b0010: out = 1'b1;
+        4'b0011: out = 1'b0;
+        4'b0100: out = 1'b0;
+        4'b0101: out = 1'b0;
+        4'b0110: out = 1'b1;
+        4'b0111: out = 1'b0;
+\t4'b1000: out = 1'b1;
+        4'b1001: out = 1'b0;
+        4'b1010: out = 1'bx;
+        4'b1011: out = 1'bx;
+        4'b1100: out = 1'bx;
+        4'b1101: out = 1'bx;
+        4'b1110: out = 1'bx;
+        4'b1111: out = 1'bx;
+\t
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xE2(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x27(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x94(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xBF(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module G7dec(output out, input in1, in2, in3, in4);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3, in4)
+    begin
+      case({in1, in2, in3, in4})
+        4'b0000: out = 1'b0;
+        4'b0001: out = 1'b0;
+        4'b0010: out = 1'b1;
+        4'b0011: out = 1'b1;
+        4'b0100: out = 1'b1;
+        4'b0101: out = 1'b1;
+        4'b0110: out = 1'b1;
+        4'b0111: out = 1'b0;
+\t4'b1000: out = 1'b1;
+        4'b1001: out = 1'b1;
+        4'b1010: out = 1'bx;
+        4'b1011: out = 1'bx;
+        4'b1100: out = 1'bx;
+        4'b1101: out = 1'bx;
+        4'b1110: out = 1'bx;
+        4'b1111: out = 1'bx;
+\t
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module XNOR(output out,input A,B);\r
+always@(B,A)\r
+ begin\r
+  case({B,A})\r
+   2'b00: {out} = 1'b1;\r
+   2'b01: {out} = 1'b0;\r
+   2'b10: {out} = 1'b0;\r
+   2'b11: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0xA7(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xA8(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x06(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"\r
+\r
+module 0xC8(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x66(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xF7(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x72(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xF7(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x80(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x7B(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xEB(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xFD(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x60(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x9F(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x8A(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module A(output Qa, Qb, input in1, in2, C);
+
+   wire w1, w2, w3, w4, w5;
+
+   not (w4, in1);
+   not (w5, in2);
+   nor (D, w4, w5);
+   nor (w1, D, C);
+   nor (w2, w1, C);
+   nor (Qa, w1, Qb);
+   nor (Qb, w2, Qa);
+
+endmodule // A
+"
+"\r
+\r
+module 0x7F(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module B7hex(output out, input in1, in2, in3, in4);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3, in4)
+    begin
+      case({in1, in2, in3, in4})
+        4'b0000: out = 1'b1;
+        4'b0001: out = 1'b1;
+        4'b0010: out = 1'b1;
+        4'b0011: out = 1'b1;
+        4'b0100: out = 1'b1;
+        4'b0101: out = 1'b0;
+        4'b0110: out = 1'b0;
+        4'b0111: out = 1'b1;
+\t4'b1000: out = 1'b1;
+        4'b1001: out = 1'b1;
+        4'b1010: out = 1'b1;
+        4'b1011: out = 1'b0;
+        4'b1100: out = 1'b0;
+        4'b1101: out = 1'b1;
+        4'b1110: out = 1'b0;
+        4'b1111: out = 1'b0;
+\t
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x5B(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xA9(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x9A(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x1C(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module A(output out1,  input in1, in2);
+ always@(in1,in2)
+  begin
+   case({in1,in2})
+    2'b00: {out1} = 1'b0;
+    2'b01: {out1} = 1'b1;
+    2'b10: {out1} = 1'b1;
+    2'b11: {out1} = 1'b0;
+   endcase
+  end
+endmodule
+"
+"module 0x4D(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module NOTA(output out, input in1, in2);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2)
+    begin
+      case({in1,in2})
+        2'b00: out = 1'b1;
+        2'b01: out = 1'b0;
+        2'b10: out = 1'b1;
+        2'b11: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xCD(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xDF(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xCE(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x25(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x77(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x9F(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xAF(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xB6(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0xE8(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x09(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module C7hex(output out, input in1, in2, in3, in4);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3, in4)
+    begin
+      case({in1, in2, in3, in4})
+        4'b0000: out = 1'b1;
+        4'b0001: out = 1'b1;
+        4'b0010: out = 1'b0;
+        4'b0011: out = 1'b1;
+        4'b0100: out = 1'b1;
+        4'b0101: out = 1'b1;
+        4'b0110: out = 1'b1;
+        4'b0111: out = 1'b1;
+\t4'b1000: out = 1'b1;
+        4'b1001: out = 1'b1;
+        4'b1010: out = 1'b1;
+        4'b1011: out = 1'b1;
+        4'b1100: out = 1'b0;
+        4'b1101: out = 1'b1;
+        4'b1110: out = 1'b0;
+        4'b1111: out = 1'b0;
+\t
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module structuralXOR(output out, input inA, inB, inC);
+
+wire w2,w3,w4,w6,w7,w8,w9;
+
+nor (w9, inB, inC);
+nor (w8, w9, inC);
+nor (w7, w9, inB);
+nor (w6, w7, w8);
+nor (w4, inA, w6);
+nor (w3, w4, w6);
+nor (w2, w4, inA);
+nor (out, w2, w3);
+   
+endmodule
+
+"
+"module 0x5D(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x94(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x6D(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xCF(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x07(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module A(output out1, out2, out3, out4,  input in1, in2);
+  reg r_out;
+  assign out = r_out;
+  always@(in1,in2)
+    begin
+      case({in1,in2})
+        2'b00: {out1,out2,out3,out4} = 4'b1000;
+        2'b01: {out1,out2,out3,out4} = 4'b0100;
+        2'b10: {out1,out2,out3,out4} = 4'b0010;
+        2'b11: {out1,out2,out3,out4} = 4'b0001;
+      endcase
+    end
+endmodule
+"
+"module 0xCC(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x1D(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xA5(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xC4(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x9D(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x3E(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x0E(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x2B(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xE8(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x39(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x82(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b2;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0xFF(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x3B(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x96(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x35(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xF4(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x30(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xA2(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module majority_alt(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b1;\r
+   3'b100: {out} = 1'b0;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x2B(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module ANIMPLYB(output out,input A,B);\r
+always@(B,A)\r
+ begin\r
+  case({B,A})\r
+   2'b00: {out} = 1'b0;\r
+   2'b01: {out} = 1'b1;\r
+   2'b10: {out} = 1'b0;\r
+   2'b11: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x53(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xEE(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xA0(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module A(output Qa, Qb, input D, C);
+
+   wire w1, w2, w3;
+   
+   nor (w1, D, C);
+   nor (w2, w1, C);
+   nor (Qa, w1, Qb);
+   nor (Qb, w2, Qa);
+
+endmodule // A
+"
+"module 0x51(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xB3(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x26(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x1A(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x2D(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xD2(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x5C(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0xE8(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b1;\r
+   3'b010: {out} = 1'b1;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b0;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x70(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b1;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x1B(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x42(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x06(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x8E(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b1;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"\r
+\r
+module 0x0B(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b0;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0xD0(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xDA(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"\r
+\r
+module 0x0E(output out,input A,B,C);\r
+always@(C,B,A)\r
+ begin\r
+  case({C,B,A})\r
+   3'b000: {out} = 1'b0;\r
+   3'b001: {out} = 1'b0;\r
+   3'b010: {out} = 1'b0;\r
+   3'b011: {out} = 1'b0;\r
+   3'b100: {out} = 1'b1;\r
+   3'b101: {out} = 1'b1;\r
+   3'b110: {out} = 1'b1;\r
+   3'b111: {out} = 1'b0;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"\r
+\r
+module BIMPLYA(output out,input A,B);\r
+always@(B,A)\r
+ begin\r
+  case({B,A})\r
+   2'b00: {out} = 1'b1;\r
+   2'b01: {out} = 1'b1;\r
+   2'b10: {out} = 1'b0;\r
+   2'b11: {out} = 1'b1;\r
+  endcase\r
+ end\r
+endmodule
+
+"
+"module 0x9C(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0x06(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b0;
+        3'b001: out = 1'b0;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b0;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xDD(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b1;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b1;
+        3'b110: out = 1'b0;
+        3'b111: out = 1'b1;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module 0xCA(output out, input in1, in2, in3);
+  reg r_out;
+  assign out = r_out;
+  always@(in1, in2, in3)
+    begin
+      case({in1,in2,in3})
+        3'b000: out = 1'b1;
+        3'b001: out = 1'b1;
+        3'b010: out = 1'b0;
+        3'b011: out = 1'b0;
+        3'b100: out = 1'b1;
+        3'b101: out = 1'b0;
+        3'b110: out = 1'b1;
+        3'b111: out = 1'b0;
+        default: out = 1'b0;
+      endcase
+    end
+endmodule
+"
+"module BNimplyA ( A, B, O );
+
+input A; 
+input B;
+output O;
+
+assign O = ( ~ ( A ) & B );
+
+endmodule
+"
+"module ANimplyB ( A, B, O );
+
+input A; 
+input B;
+output O;
+
+assign O = ( A & ~ ( B ) );
+
+endmodule
+"
+"module xnor2 (
+  A,
+  B,
+  O
+);
+
+input A;
+input B;
+output O;
+
+assign O = ( ( A & B ) | ( ( ~ A ) & ( ~ B ) ) );
+
+endmodule
+"
+"module or2 (
+  A,
+  B,
+  O
+);
+
+input A;
+input B;
+output O;
+
+assign O = ( A | B );
+
+endmodule
+"
+"module notA2 (
+  A,
+  B,
+  O
+);
+
+input A;
+input B;
+output O;
+
+assign O = ( ~ ( A ) );
+
+endmodule
+"
+"module notB2 (
+  A,
+  B,
+  O
+);
+
+input A;
+input B;
+output O;
+
+assign O = ( ~ ( B ) );
+
+endmodule
+"
+"module BimplyA ( A, B, O );
+
+input A; 
+input B;
+output O;
+
+assign O = A | ( ~ ( B ) );
+
+endmodule
+"